СПОСОБ ПОЛУЧЕНИЯ ДВУМЕРНОГО МАТЕРИАЛА

Изобретение относится к получению двумерного кристаллического материала, такого как графен (варианты) или другого двумерного кристаллического материала, такого как силицен, а также получения множества выложенных в стопу слоев двумерного кристаллического материала, получения гетероструктуры, гетероструктурного материала, содержащих двумерный кристаллический материал. Способ получения двумерного кристаллического материала, например графена или другого двумерного материала, такого как силицен, включает нагревание подложки, удерживаемой в реакционной камере, до достижения температуры, которая находится в пределах диапазона разложения предшественника и которая обеспечивает образование двумерного кристаллического материала из вещества, выделяющегося из разлагаемого предшественника. Создание крутого температурного градиента (предпочтительно >1000°С на метр), проходящего от поверхности подложки по направлению к впускному отверстию для предшественника. Введение предшественника через относительно ...

СПОСОБ ЛАЗЕРНОГО ОТДЕЛЕНИЯ ЭПИТАКСИАЛЬНОЙ ПЛЕНКИ ИЛИ СЛОЯ ЭПИТАКСИАЛЬНОЙ ПЛЕНКИ ОТ РОСТОВОЙ ПОДЛОЖКИ ЭПИТАКСИАЛЬНОЙ ПОЛУПРОВОДНИКОВОЙ СТРУКТУРЫ (ВАРИАНТЫ)

Изобретение относится к области лазерной обработки твердых материалов, в частности к способу отделения поверхностных слоев полупроводниковых кристаллов с помощью лазерного излучения. Способ лазерного отделения основан на использовании селективного легирования подложки и эпитаксиальной пленки мелкими донорными или акцепторными примесями. При селективном легировании концентрации свободных носителей в эпитаксиальной пленке и подложке могут существенно отличаться, и это может приводить к сильному отличию коэффициентов поглощения света в инфракрасной области вблизи области остаточных лучей, где существенны вклады в инфракрасное поглощение оптических фононов, свободных носителей и фонон-плазмонного взаимодействия оптических фононов со свободными носителями. Соответствующим подбором уровней легирования и частоты инфракрасного лазерного излучения можно добиться того, чтобы лазерное излучение поглощалось в основном в области сильного легирования вблизи границы раздела подложка - гомоэпитаксиальная ...

Verfahren zur Herstellung eines porösen halbleitenden Films

Verfahren zur Herstellung einer porösen halbleitenden Struktur, dadurch gekennzeichnet, dass A. dotierte Halbmetallpartikel erzeugt werden, und anschließend B. aus den nach Schritt A erhaltenen Halbmetallpartikeln eine Dispersion erzeugt wird, und anschließend C. ein Substrat mit der nach Schritt B erhaltenen Dispersion beschichtet wird, und anschließend D. die nach Schritt C erhaltene Schicht durch eine Lösung von Fluorwasserstoff in Wasser behandelt wird, und anschließend E. die nach Schritt D erhaltene Schicht thermisch behandelt wird, wobei eine poröse halbleitende Struktur erhalten wird.

Wafer bow reduction

A method of producing a two-dimensional material

A method of producing silicene, comprising; i) providing a substrate having nucleation sites within a close coupled reaction chamber having at least one precursor entry point to provide a separation between the substrate surface upon which the silicene is formed and the at least one precursor entry point that is sufficiently small; ii) cooling the at least one precursor entry point; iii) introducing at the at least one precursor entry point a precursor into the close coupled reaction chamber, the precursor being in a gas phase and/or suspended in a gas, and, iv) heating the substrate to a temperature that is within a decomposition range of the precursor, to provide a thermal gradient between the substrate surface and the at least one precursor entry point that is sufficiently steep, such that the fraction of precursor that reacts in the gas phase within the reaction chamber is low enough to allow the formation of silicene from silicon released from the decomposed precursor wherein the distance ...

A Method of Producing Graphene Using a Cold-Walled Reactor

Semiconductor and method for producing the same

A method of producing a two-dimensional material

RADIATION DETECTOR

Verfahren zur Herstellung von Selengleichrichtern

Verfahren zur Herstellung von Selengleichrichterplatten

Photoleitfähiger Stoff

Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures

DOPANT INTRODUCTION METHOD AND HEAT TREATMENT METHOD

Provided are a dopant introduction method which introduces a sufficient dopant without causing a defect and obtains a high activation rate, and a heat treatment method. A thin film including a dopant is formed on a surface of a semiconductor wafer. The semiconductor wafer formed with a thin film including a dopant is rapidly heated at a first peak temperature (Ts) by light irradiation from a halogen lamp to diffuse the dopant on the surface of the semiconductor wafer from the thin film. When thermal diffusion is performed by rapid heating, a sufficient dopant may be introduced into the semiconductor wafer without causing a defect. In addition, the semiconductor wafer is irradiated with flash rays from a flash lamp to heat the surface of the semiconductor wafer at a second peak temperature (Tp) so as to activate the dopant. When the flash ray irradiation is performed for an extremely short time, a high activation rate may be obtained without excessively diffusing the dopant. COPYRIGHT KIPO ...

플라즈마 도핑을 위한 도펀트의 고체 상태 도입

... 비-평탄 표면 또는 불량 뷰 팩터에 영향을 받는 기판의 표면을 도핑하는 방법이 제공된다. 프로세싱 챔버는 산소-함유 재료를 가지는 프로세싱 챔버의 윈도우, 벽 및 바닥부를 포함하고, 프로세스 챔버는 첨가물로서 산소 라디칼을 하나 이상의 도핑 재료에 공급하도록 구성된다. 하나 이상의 석영 피스가 프로세싱 챔버 내에 배치되고, 여기서 프로세싱 챔버에 근접한 자석은 프로세싱 챔버 내에 로컬 마그네트론 플라즈마를 생성하도록 구성된다. 불활성 가스, 승화된 도핑 재료 및 선택적으로 산소 가스를 함유하는 프로세스 가스가 프로세싱 챔버 내로 흐른다.

Method of manufacturing a semiconductor device

To obtain a TFT, in which an off-current value is low and the fluctuation is suppressed, and an electronic equipment provided with the TFT. A film deposition temperature is set to substantially the same between a base insulating film and an amorphous semiconductor film to improve flatness of the semiconductor film. Then, laser light irradiation is conducted.

GESN INFRARED PHOTODETECTORS

Photodiode devices with GeSn active layers can be integrated directly on p+ Si platforms under CMOS-compatible conditions. It has been found that even minor amounts of Sn incorporation (2 %) dramatically expand the range of IR detection up to at least 1750 nm and substantially increases the absorption. The corresponding photoresponse can cover of all telecommunication bands using entirely group IV materials.

METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS FOR PROVIDING LOW-RESISTANCE CONTACT TO BURIED LAYERS AND RELATED DEVICES

Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Composite semiconductor substrate, semiconductor device and method for manufacturing the same

A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.

Methods for forming FinFETs with non-merged epitaxial fin extensions

Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

METHODS AND APPARATUS FOR INTEGRATED SELECTIVE MONOLAYER DOPING

Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.

FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS

A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Halbleiterkomponente, die ein mit Kohlenstoff dotiertes Substrat aufweist

Gemäß einer Ausführungsform umfasst ein Verfahren zur Herstellung einer Halbleiterkomponente die Bereitstellung eines Halbleitermaterials, welches eine Fläche aufweist, Bildung einer epitaxialen Schicht von mit Kohlenstoff dotiertem Halbleitermaterial auf dem Halbleitersubstrat, wobei die epitaxiale Schicht eine Fläche aufweist, Bildung einer Keimbildungsschicht auf der epitaxialen Schicht; und Bildung einer Schicht aus III-Nitridmaterial auf der Keimbildungsschicht. Gemäß einer anderen Ausführungsform umfasst die Halbleiterkomponente ein Siliziumhalbleitersubstrat eines ersten Leitfähigkeitstyps; eine mit Kohlenstoff dotierte epitaxiale Schicht auf dem Siliziumhalbleitersubstrat; eine Pufferschicht über der mit Kohlenstoff dotierten Pufferschicht; und eine Kanalschicht über der mit Kohlenstoff dotierten Pufferschicht.

A Doped Graphene Sheet

A Method of Producing a Two-Dimensional Material

Improvements in the manufacture of alternating current rectifiers of the dry surface contact type

... 514,751. Asymmetrically-conducting resistances. WESTINGHOUSE BRAKE & SIGNAL CO., Ltd., WILLIAMS, A. L., and THOMPSON, L. E. May 14, 1938, No. 14443. [Class 37] In the manufacture of rectifiers of the copper-oxide type, the element boron, or its compounds, is introduced into the oxidizing furnace either in the form of vapour or in a suitable receptacle in the furnace chamber. The metal blanks or their supports may be previously immersed in a solution of a boron compound.

Reducing electrical activity of defects in silicon carbide grown on silicon

A method for reducing the electrical activity of defects in a silicon carbide epitaxial layer grown on a silicon wafer comprises reducing oxidation of silicon during growth of the silicon carbide layer. The method may comprise introducing a precursor during growth of the silicon carbide layer, wherein oxygen preferentially reacts with the precursor over the silicon. The precursor may comprise aluminium, titanium, magnesium or calcium. The silicon carbide layer may also be n-type doped, for example with nitrogen. The silicon carbide may be 3-step cubic silicon carbide (3C SiC). The defects may comprise stacking faults or microtwins. The method may comprise using a scavenger plate to remove oxygen from reactant gases during growth of the silicon carbide layer. A semiconductor structure comprising a silicon wafer and a silicon carbide epaxial layer doped with the precursor is also disclosed. A semiconductor device may comprise the semiconductor structure.

Method of forming graphene on a silicon substrate

A method for the formation of graphene on a silicon substrate comprising providing a silicon wafer having a growth surface which is free of native oxides, in a reaction chamber. Nitriding is used on the growth surface using a nitrogen-containing gas with the silicon wafer at a temperature above 800 degrees Celsius to form a silicon nitride layer. A graphene mono-layer or multiple layer structure is formed on the silicon nitride layer, wherein the method is performed in-situ and sequentially in a single reaction chamber. The growth surface may be contacted with hydrogen gas or treated with hydrofluoric acid to remove the native oxides. The reaction chamber may be an MOCVD reaction chamber. A graphene-on-silicon layer structure having an intervening silicon nitride layer obtainable by said method, wherein the nitride layer is provided on a Si(100) plane or Si(111) plane with an average crystal grain size of at least 500nm.

RADIATION DETECTOR

A method of producing a two-dimensional material

A method of producing graphene or other two-dimensional material such as graphene comprising heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000°C per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimising decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100mm.

A METHOD OF PRODUCING A TWO-DIMENSIONAL MATERIAL

A method of producing graphene or other two-dimensional material such as graphene comprising heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000°C per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimising decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100mm.

FABRICATING GALLIUM PHOSPHIDE DEVICE

METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS FOR PROVIDING LOW-RESISTANCE CONTACT TO BURIED LAYERS AND RELATED DEVICES

Methods of fabricating a semiconductor device include forming a first sem iconductor layer of a first conductivity type and having a first dopant conc entration, and forming a second semiconductor layer on the first semiconduct or layer. The second semiconductor layer has a second dopant concentration t hat is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conduct ivity type extending through the second semiconductor layer to contact the f irst semiconductor layer. A first electrode is formed on the implanted regio n of the second semiconductor layer, and a second electrode is formed on a n on-implanted region of the second semiconductor layer. Related devices are a lso discussed.

Crystalline laminated structure, and semiconductor device

DOPANT INTRODUCTION METHOD AND THERMAL TREATMENT METHOD

CMOS 공진 인터밴드 터널링 셀

... 반도체 장치는 제1 다이오드 연결된 제1 도전형의 트랜지스터 및 제2 다이오드 연결된 제2 도전형의 트랜지스터를 포함하되, 상기 제1 다이오드 연결된 트랜지스터 및 상기 제2 다이오드 연결된 트랜지스터는 직렬로 연결되고, 상기 제1 및 제2 다이오드 연결된 트랜지스터들의 각각은 인가된 전압에 반응하여 부성 미분 저항을 나타낸다. 상기 제1 다이오드 연결된 트랜지스터의 제1 드레인 영역 및 제1 소스 영역은 상기 제1 도전형의 도펀트들을 축퇴되는 농도로 포함하고, 상기 제1 다이오드 연결된 트랜지스터의 게이트는 상기 제2 도전형의 도펀트들을 포함하는 반도체의 일 함수에 해당하는 일 함수를 갖는다. 상기 제2 다이오드 연결된 트랜지스터의 제2 드레인 영역 및 제2 소스 영역은 상기 제2 도전형의 도펀트들을 축퇴되는 농도로 포함하고, 상기 제2 다이오드 연결된 트랜지스터의 게이트는 상기 제1 도전형의 도펀트들을 포함하는 반도체의 일 함수에 해당하는 일 함수를 갖는다.

Method for heteroepitaxial growth of high-quality N-face GaN, InN, and AIN and their alloys by metal organic chemical vapor deposition

Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (m sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

Method for forming an epitaxy layer

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A high-mobility material layer manufacturing method comprises: forming multiple precursors in and/or on a substrate (1); and performing pulse laser processing, so that the multiple precursors react with each other to form a high-mobility material layer. Also provided is a semiconductor device manufacturing method, comprising: forming a cushioning layer (3) on an insulating substrate; forming a first high-mobility material layer (6A) on the cushioning layer by using the high-mobility material layer manufacturing method; forming a second high-mobility material layer (6B) on the first high-mobility material layer (6A) by using the high-mobility material layer manufacturing method; and forming a groove isolation (8) in the first and the second high-mobility material layers and defining an active region. In the semiconductor manufacturing method, by adjusting the pulse quantity and energy density in the laser processing, a multi-layer high-mobility material is formed on the insulating substrate ...

FinFET having highly doped source and drain regions

A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Method for Forming a Thin Film Comprising an Ultrawide Bandgap Oxide Semiconductor

A method is disclosed for depositing a high-quality thin films of ultrawide bandgap oxide semiconductors at growth rates that are higher than possible using prior-art methods. Embodiments of the present invention employ LPCVD deposition using vapor formed by evaporating material as a precursor, where the material has a low vapor pressure at the growth temperature for the thin film. The vapor is carried to a reaction chamber by an inert gas, such as argon, where it mixes with a second precursor. The reaction chamber is held at a pressure that nucleation of the precursor materials occurs preferentially on the substrate surface rather than in vapor phase. The low vapor pressure of the material gives rise to growth rates on the substrate surface that a significantly faster than achievable using prior-art growth methods.

CONTACT RESISTANCE REDUCTION BY III-V Ga DEFICIENT SURFACE

A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.

SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS

A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

TAPERED VERTICAL FET HAVING III-V CHANNEL

A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.

METHOD FOR DOPING LAYER, THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A method for doping a layer, a thin film transistor and a method for fabricating the thin film transistor. The method comprises: forming a layer to be doped on a substrate by a first patterning process, wherein the layer comprises a first region, a second region and a third region, the first region is arranged in a middle region, the third region is arranged in an edge region, the second region is arranged between the first region and the third region; forming a first blocking layer and a second blocking layer on the layer in this order by a second patterning process, wherein an orthographic projection region of the first blocking layer on the layer exactly covers the first region, and an orthographic projection region of the second blocking layer on the layer exactly covers the first region and the second region; perform a first doping on the layer with an ion beam perpendicular to the substrate, to realize doping of the third region; rotating the substrate by a preset angle in a direction ...

COATING AND DEVELOPING SYSTEM AND COATING AND DEVELOPING METHOD

A coating and developing system for forming a resist film on a substrate by coating the substrate with a liquid resist and developing the resist film after the resist film has been processed by immersion exposure that forms a liquid layer on the surface of the substrate is capable of reducing difference in property among resist films formed on substrates. The coating and developing system includes: a cleaning unit for cleaning a surface of a substrate coated with a resist film; a carrying means for taking out the substrate from the cleaning unit and carrying the substrate to an exposure system that carries out an immersion exposure process; and a controller for controlling the carrying means such that a time interval between a wetting time point when the surface of the substrate is wetted with the cleaning liquid by the cleaning unit and a delivery time point when the substrate is delivered to the exposure system is equal to a predetermined set time interval. The set time interval is determined ...

FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers

In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

APPARATUS WITH A CURRENT-GAIN LAYOUT

An apparatus includes: a first substrate comprising a first channel that includes a first plurality of doped regions on the first substrate; a second substrate comprising a second channel that includes a second plurality of doped regions in the second substrate, wherein: the doped regions of the second substrate are electrically and/or physically separate from those of the first substrate, and the second channel is aligned colinearly with the first channel; and a conductive structure extending across the first substrate and the second substrate and electrically connecting matching doped regions of the first channel and the second channel.

Method of manufacturing semiconductor device, substrate processing apparatus and recording medium

There is provided a technique that includes (a) pre-etching a surface of a substrate made of single crystal silicon by supplying a first etching gas to the substrate; (b) forming a silicon film on the substrate with the pre-etched surface, by supplying a first silicon-containing gas to the substrate; (c) etching a portion of the silicon film by supplying a second etching gas, which has a different molecular structure from a molecular structure of the first etching gas, to the substrate; and (d) forming an additional silicon film on the etched silicon film by supplying a second silicon-containing gas to the substrate.

SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

VAPOR PHASE GROWTH METHOD AND VAPOR PHASE GROWTH APPARATUS

A vapor phase growth method of embodiments includes: forming a first silicon carbide layer having a first doping concentration on a silicon carbide substrate at a first growth rate by supplying a first process gas under a first gas condition; forming a second silicon carbide layer having a second doping concentration at a second growth rate higher than the first growth rate by supplying a second process gas under a second gas condition; and forming a third silicon carbide layer having a third doping concentration lower than the first doping concentration and the second doping concentration at a third growth rate higher than the second growth rate by supplying a third process gas under a third gas condition.

Method of forming graphene on a silicon substrate

A method for the formation of graphene on a silicon substrate comprising providing a silicon wafer having a growth surface which is free of native oxides, in a reaction chamber. Nitriding is used on the growth surface using a nitrogen-containing gas with the silicon wafer at a temperature above 800 degrees Celsius to form a silicon nitride layer. A graphene mono-layer or multiple layer structure is formed on the silicon nitride layer, wherein the method is performed in-situ and sequentially in a reaction chamber. A silicon wafer may be provided in a single reaction chamber and may be heated to a temperature above 900 degrees Celsius. The growth surface may be contacted with hydrogen gas to remove native oxides from the growth surface. The reaction chamber may be an MOCVD reaction chamber. A graphene-on-silicon layer structure having an intervening silicon nitride layer obtainable by said method.

A METHOD OF PRODUCING A TWO-DIMENSIONAL MATERIAL

... - 62 A method of producing a two-dimensional material such as graphene is disclosed comprising heating the substrate held within a reaction chamber to a temperature that is within a 5 decomposition range of a precursor. This allows a two-dimensional crystalline material to be formed from a species released from the decomposed precursor. This establishes a steep temperature gradient (preferably >1000°C per meter) that extends away from the substrate surface towards an inlet for the precursor. It also introduces precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep 10 temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimising any decomposition or other reaction of the precursor before it is proximate the substrate surface. It extends to a sheet of graphene having a mean grain size equal or greater than 20 micrometers that enables the sheet to substantially ...

GROUP IIIA NITRIDE GROWTH SYSTEM AND METHOD

A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes: controlling a temperature of a sputtering target, and modulating between a gallium-rich condition and a gallium-lean condition, wherein the gallium-rich condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, and wherein the gallium-lean condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value. Some embodiments include a load lock configured to load a substrate wafer into the system and remove the GaN structure from the system; and a plurality of deposition chambers, wherein the plurality of deposition chambers includes a GaN-deposition chamber configured to grow at least the first GaN layer on a template that includes the substrate wafer.

METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GAN, INN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION

Methods for the heteroepitaxial growth of smooth, high quality films of N - face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-fac e GaN and other Group III nitride films as disclosed herein. The present inv ention also avoids the typical large (.mu.m sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present i nvention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GAN, INN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION

Methods for the heteroepitaxial growth of smooth, high quality films of N- face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (µm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

method for fabricating a low dark current germanium-based diode matrix

FINFET WITH STRAINED WELL REGIONS

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

... 반도체 디바이스들 및 그 제조 방법들이 개시된다. 일 실시예에서, 반도체 디바이스를 제조하는 방법은 리세스를 갖는 기판을 제공하는 단계; 리세스 내에 도핑 반도체 물질을 포함하는 제1 층을 에피택셜 형성하는 단계; 및 리세스의 적어도 일부 위에 미도핑 반도체 물질을 포함하는 제2 층을 에피택셜 형성하는 단계를 포함할 수 있다.

Forming epitaxial structures in Fin field effect transistors

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

METHOD FOR MANUFACTURING SEMICONDUCTOR EPITAXIAL CRYSTAL SUBSTRATE

This invention provides a gallium nitride-type semiconductor epitaxial crystal substrate with a dielectric film, having a low gate leak current and very low and negligible gate lag, drain lag and current collapse characteristics. There is also provided a method for manufacturing a semiconductor epitaxial crystal substrate comprising a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form as a passivation film or a gate insulating film applied onto the surface of a nitride semiconductor crystal layer grown by an organometal vapor phase epitaxial growth method. After the nitride semiconductor crystal layer is grown within an epitaxial growth furnace, the dielectric layer is also continuously grown on the nitride semiconductor crystal layer in the same epitaxial growth furnace.

High efficiency FinFET diode

Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and ...

Tunability Of Dopant Concentration In Thin Hafnium Oxide Films

Methods of depositing thin films of hafnium oxide possessing strong ferroelectric properties are described. A hafnium oxide monolayer is formed in a first process cycle comprising sequential exposure of a substrate to a hafnium precursor, purge gas, first oxidant and purge gas. A doped hafnium oxide monolayer is formed in a second process cycle comprising sequential exposure of the substrate to a hafnium precursor, purge gas, dopant precursor, purge gas, second oxidant and purge gas. Thin films of hafnium oxide are also described.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, GAS SUPPLY SYSTEM, AND RECORDING MEDIUM

A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Method for heteroepitaxial growth of high-quality N-face GaN, InN, and AIN and their alloys by metal organic chemical vapor deposition

Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (mum sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium

There is provided a method of manufacturing a semiconductor device. The method includes: forming a first amorphous silicon film on a substrate in a process chamber; and etching a portion of the first amorphous silicon film using a hydrogen chloride gas under a temperature at which an amorphous state of the first amorphous silicon film is maintained, in the process chamber.

IMAGE SENSOR WITH SHALLOW TRENCH EDGE DOPING

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a photodetector region arranged within a semiconductor substrate. One or more dielectric materials are disposed within a trench defined by one or more interior surfaces of the semiconductor substrate. A doped epitaxial material is arranged within the trench and is laterally between the one or more dielectric materials and the photodetector region. A dielectric protection layer is arranged over the one or more dielectric materials within the trench. The dielectric protection layer laterally contacts a sidewall of the doped epitaxial material.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

DOMAIN WALL MAGNETIC MEMORY

Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first ...

High temperature GaN based super semiconductor and fabrication process

A low temperature GaN based super semiconductor comprising a GaN supercell having equal percentages of Cu and at least one material from the family of P, As, or Sb. The GaN supercell is doped in accordance with the formula Ga1-2xCuxAsxN, wherein x is from about 6.25% to about 25%. The supercell is deposited on GaN grown on silicon substrate.

Method for setting a nitrogen concentration of a silicon epitaxial film in manufacturing an epitaxial silicon wafer

A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.

СПОСОБ ПОЛУЧЕНИЯ ДВУМЕРНОГО МАТЕРИАЛА

Herstellen einer Halbleitervorrichtung durch Epitaxie

Ein Verfahren zur Herstellung einer Halbleitervorrichtung (1) wird vorgestellt. Das Verfahren (2) umfasst: Bereitstellen (20) eines Halbleitersubstrats (4), das eine Oberfläche (40) aufweist; epitaxiales Wachsenlassen (21) einer Rückseiten-Emitter-Schicht (125) auf der Oberseite der Oberfläche (40) entlang einer zur Oberfläche (40) senkrechten, vertikalen Richtung (Z), wobei die Rückseiten-Emitter-Schicht (125) Dotierstoffe eines ersten Leitfähigkeitstyps oder Dotierstoffe eines zweiten Leitfähigkeitstyps, der zu dem ersten Leitfähigkeitstyp komplementär ist, aufweist; epitaxiales Wachsenlassen (23) einer Drift-Schicht (123), die Dotierstoffe des ersten Leitfähigkeitstyps oberhalb der Rückseiten-Emitter-Schicht (125) aufweist, entlang einer vertikalen Richtung (Z), wobei eine Dotierstoffkonzentration der Rückseiten-Emitter-Schicht (125) höher als eine Dotierstoffkonzentration der Drift-Schicht (123) ist; und Erzeugen (24) entweder innerhalb oder auf der Oberseite der Drift-Schicht (123) ...

Ein Verfahren zum Bilden eines Halbleiterbauelements

Ein Verfahren zum Bilden eines Halbleiterbauelements umfasst das Bilden einer amorphen oder polykristallinen Halbleiterschicht benachbart zu zumindest einer Halbleiterdotierungsregion mit einem ersten Leitfähigkeitstyp, die in einem Halbleitersubstrat angeordnet ist. Das Verfahren umfasst ferner das Einbringen von Dotierstoffen in die amorphe oder polykristalline Halbleiterschicht während oder nach dem Bildern der amorphen oder polykristallinen Halbleiterschicht. Das Verfahren umfasst ferner das Ausheilen der amorphen oder polykristallinen Halbleiterschicht, um zumindest einen Teil der amorphen oder polykristallinen Halbleiterschicht in eine im Wesentlichen monokristalline Halbleiterschicht zu transformieren, und um zumindest eine Dotierungsregion mit dem zweiten Leitfähigkeitstyp in der monokristallinen Halbleiterschicht derart zu bilden, dass ein p-n-Übergang zwischen der zumindest einen Halbleiterdotierungsregion mit dem ersten Leitfähigkeitstyp und der zumindest einen Dotierungsregion ...

A method of producing a two-dimensional material

A graphene sheet (which may be a series of stacked sheets or a monolayer) having a diameter of at least 2 inches on a substrate selected from a semiconductor single crystal wafer (which may be Si, SiC, GaAs, InP, GaN, ZnO or InSb), an insulating material (which may be Al2O3 or SiO2) or a compound semiconductor homo or heterostructure (which may be InP/CdTe, GaN/InGaN/AlGaN, Si/AlN/GaN, GaAs/AlInGaP, GaN/BN or silicon on insulator). The graphene may have a grain size greater than 20 µm. The graphene may be doped with a doping element, which may be silicon, magnesium, zinc, arsenic, oxygen, boron, bromine or nitrogen.

Nanosheet transistors with different gate dielectrics and workfunction metals

Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

High resistance readout fet for cognitive device

A graphene heterostructure

Semiconductor Devices

... 1,176,950. Electroluminescence. WESTERN ELECTRIC CO. Inc. 18 April, 1967 [26 April, 1966], No. 17722/67. Heading C4S. [Also in Divisions C1 and H1] A PN junction light-emitting diode is formed in a body of III-V compound material containing bismuth as an impurity with a concentration in the range 1016 to 1019 atoms/cm3. The material is of crystalline form grown from a melt containing one or more III-V compounds and an appropriate proportion of bismuth. The presence of the bismuth in the melt is found to increase the efficiency of crystal growth -e.g. for a quoted gallium phosphide crystal forming technique the presence of bismuth produces a five-fold increase in the volume of the resulting crystal. Conductivity determining impurities, e.g. group IV elements, may also be added to the melt, and the PN junction formed by diffusion of further impurity into the resulting crystal. The drawing (not shown) depicts successive stages in the manufacture of a lightemitting ...

METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS FOR PROVIDING LOW-RESISTANCE CONTACT TO BURIED LAYERS AND RELATED DEVICES

Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

SEMICONDUCTOR DEVICE WITH SAME PHYSICAL GATE LENGTH AS MULTIPLE CHANNEL LENGTH AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor device with the same physical gate length as a multiple channel length and a manufacturing method thereof. The semiconductor device includes a first finFET (nFET) which includes a first fin, a first gate electrode structure (rst gate electrode structure), a first channel region, and a first source or drain region, and a second finFET which includes a second fin, a second gate electrode structure, a second channel region, and a second source or drain region. The first gate electrode structure includes a first gate metal and a first sidewall spacer. COPYRIGHT KIPO 2016 ...

3A족 질화물 성장 시스템 및 방법

... 템플릿을 제공하는 단계; 및 제1 스퍼터링 공정을 사용하여 상기 템플릿 상에 적어도 제1 GaN 층을 성장시키는 단계;를 포함하는 질화 갈륨(GaN) 구조를 성장시키는 방법 및 시스템을 개시한다. 상기 제1 스퍼터링 공정은, 스퍼터링 타겟의 온도를 제어하는 단계; 및 풍부한 갈륨 상태 및 희박한 갈륨 상태 사이에서 변조하는 단계를 포함한다. 상기 풍부한 갈륨 상태는 갈륨 대 질소 비율이 1보다 큰 제1 값을 가지고, 상기 희박한 갈륨 상태는 갈륨 대 질소 비율이 상기 제1 값보다 작은 제2 값을 가진다. 일 실시예에서, 기판 웨이퍼를 시스템에 로딩하고 시스템으로부터 GaN 구조를 제거하도록 구성된 로드 락; 및 복수의 증착 챔버를 포함한다. 상기 복수의 증착 챔버는 상기 기판 웨이퍼를 포함하는 템플릿 상에 상기 적어도 제1 GaN 층을 성장시키도록 구성된 GaN-증착 챔버를 포함한다.

Selective removal of boron doped carbon hard mask layers

Systems and methods for processing a substrate include arranging a substrate including a film layer on a substrate support in a processing chamber. The film layer includes a boron doped carbon hard mask. A plasma gas mixture is supplied and includes molecular hydrogen, nitrogen trifluoride, and a gas selected from a group consisting of carbon dioxide and nitrous oxide. Plasma is struck in the processing chamber or supplied to the processing chamber for a predetermined stripping period. The plasma strips the film layer during the predetermined stripping period and the plasma is extinguished.

Epitaxy of high tensile silicon alloy for tensile strain applications

Crystalline oxide semiconductor thin film and semiconductor device

METHOD AND APPARATUS FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS

A method for fabricating a semiconductor layer within a plasma enhanced chemical vapor deposition (PECVD) apparatus. The PECVD apparatus includes a plurality of walls defining a processing region, a substrate support, a shadow frame, a gas distribution showerhead, a gas source in fluid communication with the gas distribution showerhead and the processing region, a radio frequency power source coupled to the gas distribution showerhead, and one or more VHF grounding straps electrically coupled to at least one of the plurality of walls. The VHF grounding straps provide a low-impedance current path between at least one of the plurality of walls and at least one of a shadow frame or the substrate support. The method further includes delivering a semiconductor precursor gas and a dopant precursor gas and delivering a very high frequency (VHF) power to generate a plasma to form a first layer on the one or more substrates.

PROCESS FOR PRODUCING FILM USING ATMOSPHERIC PRESSURE HYDROGEN PLASMA, AND METHOD AND APPARATUS FOR PRODUCING PURIFICATION FILM

This invention provides a process for producing a thin film of polycrystalline Si and the like in a high-speed, homogeneous quality and low-cost manner, and an apparatus for use in the production process. An Si atom released from a low-temperature side target can be deposited onto a high-temperature side substrate by cooling one electrode with water, mounting an Si target on the one electrode, heating the other electrode, mounting any desired substrate on the other electrode, generating atmospheric hydrogen plasma between the Si target and the substrate. In this case, the incorporation of a doping element in the target can realize the production of a thin film of doped Si. Since there is no need to handle expensive and harmful gases such as SiH4, B2H6 and PH3, equipment and operation costs can be reduced. Further, only an intended substance can be purified from a target containing a plurality of substances by applying the production process according to the present invention.

Producing a semiconductor device by epitaxial growth

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration ...

CMOS with dual raised source and drain for NMOS and PMOS

An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

PROCESS FOR PRODUCING ZnO SINGLE CRYSTAL ACCORDING TO METHOD OF LIQUID PHASE GROWTH

AUSLESE-FET MIT EINEM HOHEN WIDERSTAND FÜR KOGNITIVE EINHEIT

Eine Halbleitereinheit weist einen Source-Bereich und einen Drain-Bereich auf, die in einer Transistorstruktur ausgebildet sind. Zwischen dem Source-Bereich und dem Drain-Bereich ist ein Kanalbereich ausgebildet. Auf dem Kanalbereich ist eine Überzugsschicht ausgebildet, wobei die Überzugsschicht ein Halbleitermaterial enthält. Auf der Überzugsschicht ist ein Gate-Dielektrikum einer Gate-Struktur ausgebildet.

Semiconductor and method for producing the same

In a method for producing a semiconductor by performing superimposed doping on a plurality of dopants in a semiconductor substrate, a (2xn) structure is evaporated by a first dopant and its thin line structure is formed on the substrate, the semiconductor substrate is then brought to a temperature capable of epitaxial growth and a semiconductor crystal layer is grown epitaxially on the semiconductor substrate where the first dopant is deposited after depositing a second or third or subsequent dopant on the semiconductor substrate. Subsequently, a superimposed doping layer composed of the first and second or third and subsequent dopants is formed in the semiconductor substrate, and the plurality of dopants are activated electrically or optically by annealing the superimposed doping layer at a high temperature. Consequently, superimposed doping of a plurality of kinds of elements as dopants can be performed to a specific depth even in the case of an element semiconductor.

A method of producing a two-dimensional material

A method of producing graphene, comprising; i) providing a substrate having nucleation sites within a close coupled reaction chamber; ii) introducing a precursor into the close coupled reaction chamber, the precursor being in a gas phase and/or suspended in a gas, wherein the reaction chamber provides a separation between the substrate surface upon which the graphene is formed and the point at which the precursor enters the reaction chamber that is sufficiently small, and, iii) heating the substrate to a temperature that is within a decomposition range of the precursor to provide a thermal gradient between the substrate surface and the point at which the precursor enters the chamber that is sufficiently steep, such that the fraction of precursor that reacts in the gas phase within the reaction chamber is low enough to allow graphene formation from carbon released from the decomposed precursor, wherein the distance between the surface of the substrate upon which graphene is produced and ...

Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material

The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.

Semiconductor light emitting device and method for manufacturing same

According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.

Sodium Sputtering Doping Method for Large Scale CIGS Based Thin Film Photovoltaic Materials

A method of processing sodium doping for thin-film photovoltaic material includes forming a metallic electrode on a substrate. A sputter deposition using a first target device comprising 4-12 wt % Na 2 SeO 3 and 88-96 wt % copper-gallium species is used to form a first precursor with a first Cu/Ga composition ratio. A second precursor over the first precursor has copper species and gallium species deposited using a second target device with a second Cu/Ga composition ratio substantially equal to the first Cu/Ga composition ratio. A third precursor comprising indium material overlies the second precursor. The precursor layers are subjected to a thermal reaction with at least selenium species to cause formation of an absorber material comprising sodium species and a copper to indium-gallium atomic ratio of about 0.9.

Graded high germanium compound films for strained semiconductor devices

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Semiconductor substrate, semiconductor device, and method of producing semiconductor substrate

A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S 1 ) of forming a first epitaxial layer; a trench forming step (S 2 ) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S 3, S 4, S 5 ) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Thin film transistor and method for manufacturing thin film transistor

(1) Disclosed is a thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said thin film transistor being characterized in that the channel layer is formed of an indium oxide film that is doped with tungsten and zinc and/or tin. (2) Disclosed is a bipolar thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said bipolar thin film transistor being characterized in that the channel layer is a laminate of an organic material film and a metal oxide film that contains indium doped with at least one of tungsten, tin or titanium and has an electrical resistivity that is controlled in advance. (3) Disclosed is a method for manufacturing a thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said method for manufacturing a thin film transistor being characterized in that at least the channel layer or a part of the channel layer is formed by forming a metal oxide film by a sputtering process using an In-containing target without heating the substrate, and a heat treatment is carried out after forming the above-described elements on the substrate.

Integrated electronic device and method for manufacturing thereof

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Fabrication of cis or cigs thin film for solar cells using paste or ink

Provided is a method for preparing a copper indium selenide (CIS) or copper indium gallium selenide (CIGS) thin film, including: (1) mixing Cu, In and Ga precursors in a solvent and adding a polymer binder to obtain a paste or ink; (2) coating the obtained CIG precursor paste or ink on a conductive substrate by printing, spin coating or spraying and heat-treating the same under air or oxygen gas atmosphere to remove remaining organic substances and obtain a CIG mixed oxide thin film; (3) heat-treating the obtained CIG mixed oxide thin film under hydrogen or sulfurizing gas atmosphere to obtain a reduced or sulfurized CIG mixed thin film; and (4) heat-treating the obtained reduced or sulfurized CIG mixed thin film under selenium-containing gas atmosphere to obtain a CIGS thin film. Since residual carbon resulting from organic additives, which is the biggest problem in the existing paste coating techniques, can be reduced remarkably, and CIGS crystal size can be improved, the disclosed method can improve efficiency of CIGS solar cells.

Group iii nitride semiconductor element and epitaxial wafer

A primary surface 23 a of a supporting base 23 of a light-emitting diode 21 a tilts by an off-angle of 10 degrees or more and less than 80 degrees from the c-plane. A semiconductor stack 25 a includes an active layer having an emission peak in a wavelength range from 400 nm to 550 nm. The tilt angle “A” between the (0001) plane (the reference plane S R3 shown in FIG. 5 ) of the GaN supporting base and the (0001) plane of a buffer layer 33 a is 0.05 degree or more and 2 degrees or less. The tilt angle “B” between the (0001) plane of the GaN supporting base (the reference plane S R4 shown in FIG. 5 ) and the (0001) plane of a well layer 37 a is 0.05 degree or more and 2 degrees or less. The tilt angles “A” and “B” are formed in respective directions opposite to each other with reference to the c-plane of the GaN supporting base.

Group-iii nitride semiconductor device, method for fabricating group-iii nitride semiconductor device, and epitaxial substrate

Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×10 17 cm −3 , and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.

Semiconductor element and manufacturing method of the same

A semiconductor element includes a semiconductor layer mainly composed of Mg x Zn 1-x O (0<=x<1), in which manganese contained in the semiconductor layer as impurities has a density of not more than 1×10 16 cm −3 .

Semiconductor Device

According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.

Process for producing doped silicon layers, silicon layers obtainable by the process and use thereof

The present invention relates to a process for producing a doped silicon layer on a substrate, comprising the steps of (a) providing a liquid silane formulation and a substrate, (b) applying the liquid silane formulation to the substrate, (c) introducing electromagnetic and/or thermal energy to obtain an at least partly polymorphic silicon layer, (d) providing a liquid formulation which comprises at least one aluminium-containing metal complex, (e) applying this formulation to the silicon layer obtained after step (c) and then (f) heating the coating obtained after step (e) by introducing electromagnetic and/or thermal energy, which decomposes the formulation obtained after step (d) at least to metal and hydrogen, and then (g) cooling the coating obtained after step (f) to obtain an Al-doped or Al- and metal-doped silicon layer, to doped silicon layers obtainable by the process and to the use thereof for production of light-sensitive elements and electronic components.

Low-temperature selective epitaxial growth of silicon for device integration

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Nanoscale chemical templating with oxygen reactive materials

A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Semiconductor light emitting device, wafer, and method for manufacturing nitride semiconductor crystal layer

According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.

Nitride semiconductor light emitting element and method for manufacturing the same

A nitride semiconductor light emitting element has: a substrate for growth; an n-type nitride semiconductor layer formed on the substrate for growth; a light emitting layer formed on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer formed on the light emitting layer, wherein pipe holes are formed at a density of 5000 pipe holes/cm 2 or less, each of which extends substantially vertically from a surface of the n-type nitride semiconductor layer on the light emitting layer side toward the substrate and has a diameter of 2 to 200 nm.

Crystalline silicon film forming method and plasma cvd apparatus

A high-quality crystalline silicon film can be formed at a high film forming rate by performing a plasma CVD process. In a crystalline silicon film forming method for forming a crystalline silicon film on a surface of a processing target object by using a plasma CVD apparatus for introducing microwave into a processing chamber through a planar antenna having a multiple number of holes and generating plasma, the crystalline silicon film forming method includes generating plasma by exciting a film forming gas containing a silicon compound represented as Si n H 2n+2 (n is equal to or larger than 2) by the microwave; and depositing a crystalline silicon film on the surface of the processing target substrate by performing the plasma CVD process with the plasma.

Silicon epitaxial wafer, method for manufacturing the same, bonded soi wafer and method for manufacturing the same

A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle Φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle Φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×10 19 /cm 3 . Even when an epitaxial layer having a dopant concentration of 1×10 19 /cm 3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

Method for forming pattern of metal oxide and method for manufacturing thin film transistor using the same

Disclosed are a method for forming a metal oxide pattern and a method of manufacturing a thin film transistor using the patterned metal oxide. The method for forming a metal oxide pattern includes: preparing an ink composition including at least one metal oxide precursor or metal oxide nanoparticle, and a solvent; ejecting the ink composition on a substrate to form a pattern on the substrate; and photosintering the formed pattern. Herein, the metal oxide precursor is ionic.

Display device and driving method thereof

In a display device, the anode voltage of an organic light emitting element is periodically reset. The control terminal of a driving transistor is periodically reset, and an input data voltage is connected to the control terminal through an input terminal and an output terminal of the driving transistor. As a result, good control over the displayed luminance is achieved. Other features are also provided.

Methods for depositing thin films comprising gallium nitride by atomic layer deposition

Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes.

Method for manufacturing diode, and diode

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

Method for producing a group iii nitride semiconductor light-emitting device

The present invention is a method for producing a light- emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process.

Replacement source/drain finfet fabrication

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Method and system for doping control in gallium nitride based devices

A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Metal chloride gas generator, hydride vapor phase epitaxy growth apparatus, and nitride semiconductor template

A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.

Metal Oxide Semiconductor Films, Structures, and Methods

Materials and structures for improving the performance of semiconductor devices include ZnBeO alloy materials, ZnCdOSe alloy materials, ZnBeO alloy materials that may contain Mg for lattice matching purposes, and BeO material. The atomic fraction x of Be in the ZnBeO alloy system, namely, Zn 1-x Be x O, can be varied to increase the energy band gap of ZnO to values larger than that of ZnO. The atomic fraction y of Cd and the atomic fraction z of Se in the ZnCdOSe alloy system, namely, Zn 1-y Cd y O 1-z Se z , can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped, or p-type or n-type doped, by use of selected dopant elements.

Nitride semiconductor light emitting device and manufacturing method thereof

A nitride semiconductor light emitting device and a manufacturing method thereof are provided. The nitride semiconductor light emitting device includes: forming a first conductivity-type nitride semiconductor layer on a substrate; forming an active layer on the first conductivity-type nitride semiconductor layer; and forming a second conductivity-type nitride semiconductor layer on the active layer. High output can be obtained by increasing doping efficiency in growing the conductivity type nitride semiconductor layer.

P-type doping layers for use with light emitting devices

A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.

Methods of Forming Semiconductor Devices Including an Epitaxial Layer and Semiconductor Devices Formed Thereby

Methods of forming a semiconductor device are provided. The methods may include forming an epitaxial layer by growing a crystalline layer using a semiconductor source gas in a reaction chamber, and by etching the crystalline layer using an etching gas in the reaction chamber.

Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels

A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

METHOD AND APPARATUS FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS

A method for fabricating a semiconductor layer within a plasma enhanced chemical vapor deposition (PECVD) apparatus. The PECVD apparatus includes a plurality of walls defining a processing region, a substrate support, a shadow frame, a gas distribution showerhead, a gas source in fluid communication with the gas distribution showerhead and the processing region, a radio frequency power source coupled to the gas distribution showerhead, and one or more VHF grounding straps electrically coupled to at least one of the plurality of walls. The VHF grounding straps provide a low-impedance current path between at least one of the plurality of walls and at least one of a shadow frame or the substrate support. The method further includes delivering a semiconductor precursor gas and a dopant precursor gas and delivering a very high frequency (VHF) power to generate a plasma to form a first layer on the one or more substrates. 1. A method for fabricating a semiconductor layer within a plasma enhanced chemical vapor deposition (PECVD) apparatus comprising: a plurality of walls defining a processing region;', 'a substrate support;', 'a shadow frame disposed over the substrate support;', 'a gas distribution showerhead disposed over the substrate support and in fluid communication with the processing region;', 'a gas source in fluid communication with the gas distribution showerhead and the processing region;', 'a radio frequency power source coupled to the gas distribution showerhead; and', 'one or more VHF grounding straps electrically coupled to at least one of the plurality of walls, wherein the one or more VHF grounding straps provide a low-impedance current path between the at least one of the plurality of walls and at least one of a shadow frame or the substrate support;, 'positioning one or more substrates in the PECVD apparatus, the PECVD apparatus comprisingdelivering a semiconductor precursor gas from the gas source through the gas distribution showerhead to the ...

Method of manufacturing p-type zno nanowires and method of manufacturing energy conversion device

A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution.

Method and Apparatus for Growing a III-Nitride Layer

A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. 114-. (canceled)15. An apparatus for fabrication of a doped III-nitride semiconductor body , said apparatus comprising:a reactor chamber to receive a substrate and reactant gas to grow a III-nitride semiconductor body on said substrate;an implanter in an implanter chamber to implant ions into said III-nitride semiconductor body and to dope said III-nitride semiconductor body during the growth of said III-nitride semiconductor body, said implanter chamber being separate from said reactor chamber;at least one pump coupled to said implanter chamber configured to create a near vacuum condition in said implanter chamber.16. The apparatus of claim 15 , wherein said implanter chamber comprises a plurality of subchambers.17. The apparatus of claim 15 , wherein said at least one pump performs differential pumping.18. The apparatus of claim 15 , further comprising a Faraday cup disposed within said reactor chamber.19. The apparatus of claim 15 , further comprising deflection plates to change a direction of travel of said ions.20. A method of fabricating a doped III-nitride semiconductor body claim 15 , said method comprising:placing a substrate in a reactor chamber;pumping reactant gas into said reactor chamber for growing said III-nitride semiconductor body on said substrate;{'b': '111', 'implanting ions from an implanter, disposed in an implanter chamber, into said III-nitride semiconductor body to dope said -nitride semiconductor body during said growing said III-nitride semiconductor body, said implanter chamber being separate from said reactor chamber;'}wherein said ions pass through said implanter chamber a near vacuum condition prior to reaching said III-nitride semiconductor body.21. The method of claim 20 , wherein said implanter chamber comprises a plurality of subchambers.22. The method of claim 20 , wherein said ...

Method for Manufacturing Optical Element

A method for manufacturing an optical element includes a step wherein an aluminum nitride single crystal layer is formed on an aluminum nitride seed substrate having an aluminum nitride single crystal surface as the topmost surface. A laminated body for an optical element is manufactured by forming an optical element layer on the aluminum nitride single crystal layer, and the aluminum nitride seed substrate is removed from the laminated body. An optical element having, as a substrate, an aluminum nitride single crystal layer having a high ultraviolet transmittance and a low dislocation density is provided.

Silicon/germanium nanoparticle inks, laser pyrolysis reactors for the synthesis of nanoparticles and associated methods

Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.

Method for manufacturing a flexible intraocular retinal implant having doped diamond electrodes

A method for manufacturing an intraocular retinal implant including: providing a mold capable of supporting growth of a layer of doped diamond, the mold including, on one face, elements all depressed or all projecting with respect to the surface of the face, and constituting a pattern cavity for the electrodes of the implant which it is desired to obtain; producing the doped diamond electrodes by growing a layer of doped diamond in all or part of a space occupied by the pattern cavity elements; forming a first insulating layer on the face of the mold including the pattern cavity; producing interconnection lines by depositing an electrically conductive material at least in spaces not covered by the first insulating layer; forming a second insulating layer on the mold face including the pattern cavity, the second layer covering the interconnection lines, the first and second insulating layers forming a flexible plate of the implant; removing the mold.

Nitride semiconductor device

A nitride semiconductor device includes a substrate, and a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer sequentially formed on the substrate. A channel is formed in the third nitride semiconductor layer, and includes carriers accumulated near an interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger than that of the third nitride semiconductor layer. The first nitride semiconductor layer has a band gap equal to or larger than that of the second nitride semiconductor layer, and has a carbon concentration higher than that of the second nitride semiconductor layer.

Method of forming a laminated semiconductor film

According to some embodiments of the present disclosures, a method of forming a laminated semiconductor film is constituted by alternately laminating first and second semiconductor films on an underlying film of each of a plurality of substrates to be processed. The method includes performing a first operation of forming the first semiconductor film and a second operation of forming the second semiconductor film until a predetermined number of laminated films are obtained. In the method, a film forming temperature in the first operation and a film forming temperature in the second operation are set to be equal to each other, and temperatures between the first and second operations are set to be constant.

Method of Forming P-Type ZnO Film

Disclosed herein is a method of forming a p-type zinc oxide thin film. A zinc oxide layer and an antimony oxide layer are alternately stacked one above another on a substrate, forming a superlattice layer. The superlattice layer is modified into a p-type zinc oxide thin film by annealing. Upon annealing, zinc atoms of the zinc oxide layer are diffused into the antimony oxide layer and antimony atoms of the antimony oxide layer are diffused into the zinc oxide layer.

COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer. 1. A method of manufacturing a composite substrate , comprising:preparing a first substrate which is formed of a first silicon having a dopant;forming a semiconductor layer formed by an epitaxial growth a second silicon on a main surface of the first substrate;bonding the semiconductor layer and a second substrate of insulating; andafter the bonding, selectively etching the semiconductor layer from a side of the first substrate up to a middle portion in a thickness direction of the semiconductor layer by using an etchant, whereinthe etchant has an etching rate with respect to silicon which decreases by a not less than an certain value in a dopant concentration of a threshold lower than a dopant concentration of the first substrate, andin the forming the semiconductor layer, the semiconductor layer is formed so as to comprise a first region in a thickness direction of the first substrate, the first region being in contact with the first substrate and in which a dopant concentration thereof decreases to the threshold as a distance from the first substrate increasing.2. The method of manufacturing a composite substrate according to claim 1 , wherein claim 1 ,in the forming the semiconductor layer, the semiconductor layer is formed so that the dopant concentration decreases as the distance from the first substrate increasing.3. The method of manufacturing a composite substrate according to claim 2 , wherein claim 2 ,in the forming the semiconductor layer, the epitaxial growth of the semiconductor layer is performed by diffusing the dopant from the first substrate, the ...

Semiconductor device and method for manufacturing semiconductor device

Provided is a semiconductor device that has a buffer layer with which a dislocation density is decreased. The semiconductor device includes a substrate, a buffer region formed over the substrate, an active layer formed on the buffer region, and at least two electrodes formed on the active layer. The buffer region includes at least one composite layer in which a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant that is different from the first lattice constant and formed in contact with the first semiconductor layer, and a third semiconductor layer having a third lattice constant that is between the first lattice constant and the second lattice constant are sequentially laminated.

Methods of forming contact regions using sacrificial layers

Methods of patterning semiconductor contact materials on a crystalline semiconductor material which allow high-quality interfaces between the crystalline semiconductor material and the patterned semiconductor contact material are provided. Blanket layers of passivation material and sacrificial material are formed on the crystalline semiconductor material. A first contact opening is formed into the blanker layer of sacrificial material. The first contact opening is extended into blanket layer of passivation material, stopping on a first surface portion of the crystalline semiconductor material, using remaining sacrificial material portions as an etch mask. A semiconductor contact material is formed on the exposed first surface portion of the crystalline semiconductor material. In some embodiments, an electrode material portion can be formed over the first contact opening, and then a second blanket layer of sacrificial material can be formed, followed by forming a next contact opening.

Solid state lighting devices without converter materials and associated methods of manufacturing

Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength.

Method for manufacturing nitride electronic devices

A substrate product is disposed in a growth furnace at time t0, and the substrate temperature is then raised to 950° C. At time t3 after the substrate temperature is sufficiently stable, trimethyl gallium and ammonia are supplied to the growth furnace, to grow an i-GaN film. The substrate temperature reaches 1080° C. at time t5. At time t6 after the substrate temperature is sufficiently stable, trimethyl gallium, trimethyl aluminum and ammonia are supplied to the growth furnace, to grow an i-AlGaN film. Supply of trimethyl gallium and trimethyl aluminum is stopped at time t7 to discontinue film deposition. Quickly thereafter, supply of ammonia and hydrogen to the growth furnace is stopped and supply of nitrogen is initiated, to change the atmosphere of ammonia and hydrogen in a growth furnace chamber to a nitrogen atmosphere. After formation of the nitrogen atmosphere, the substrate temperature starts being lowered at time t8.

Semiconductor laminate and process for production thereof, and semiconductor element

A semiconductor laminate having small electric resistivity in the thickness direction; a process for producing the semiconductor laminate; and a semiconductor element equipped with the semiconductor laminate. include a semiconductor laminate including a Ga 2 0 3 substrate; an AlGalnN buffer layer which is formed on the Ga 2 0 3 substrate; a nitride semiconductor layer which is formed on the AlGalnN buffer layer and contains Si; and an Si-rich region which is formed in an area located on the AlGalnN buffer layer side in the nitride semiconductor layer and has an Si concentration of 5×10 18 /cm 3 or more.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region. 1. A semiconductor device , comprising:a first semiconductor region of a first conductivity type;a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region;a third semiconductor region of a second conductivity type provided on the second semiconductor region; anda fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region, a lattice strain of the fourth semiconductor region being greater than a lattice strain of the third semiconductor region.2. The device according to claim 1 , whereinthe third semiconductor region is provided on a portion of the second semiconductor region, andthe fourth semiconductor region is provided from a region on the third semiconductor region to a region on the second semiconductor region.3. The device according to claim 1 , wherein the second semiconductor region and the third semiconductor region have crystal structures formed by epitaxial growth.4. The device according to claim 1 , wherein the fourth semiconductor region includes an impurity different from an impurity included in the third semiconductor region.5. The device according to claim 4 , ...

ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer. 1. An access device , comprising:a first-type semiconductor layer having a first dopant;a third-type semiconductor layer formed on the first-type semiconductor layer;a second-type semiconductor layer formed on the third-type semiconductor layer, the second-type semiconductor layer having a second dopant that is different than the first dopant;a first counter doping layer with respect to the first type semiconductor layer, interposed between the first type semiconductor layer and the third type semiconductor layer; anda second counter doping layer with respect to the second type semiconductor layer, interposed between the third type semiconductor layer and the second type semiconductor layer.2. The access device of claim 1 , wherein the first dopant is an N+ type ion.3. The access device of claim 2 , wherein the second dopant is a P+ type ion claim 2 ,the first counter doping layer is a semiconductor layer doped with a P− type ion, andthe second counter doping layer is a semiconductor layer doped with an N− type ion.4. The access device of claim 1 , wherein the first dopant is a P+ type ion.5. The access device of claim 4 , wherein the second dopant is an N+ type ion claim 4 ,the first counter doping layer is a semiconductor layer ...

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

The present invention discloses a method for manufacturing a high mobility material layer, comprising: forming a plurality of precursors in/on a substrate; and performing a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer. Furthermore, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming a buffer layer on an insulating substrate; forming a first high mobility material layer on the buffer layer using the method for manufacturing the high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the method for manufacturing the high mobility material layer; and forming trench isolations and defining active regions in the first and second high mobility material layers. 1. A method for manufacturing a high mobility material layer , comprising:forming a plurality of precursors in/on a substrate; andperforming a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer.2. The method of claim 1 , wherein the step of forming a plurality of precursors further comprises implanting a dopant to the substrate to form precursors in the substrate.3. The method of claim 2 , wherein the implantation energy is about 10 KeV-300 KeV claim 2 , and the implantation dose is about 1E15-1E17/cm.4. The method of claim 2 , wherein the implantation dose and energy of one of the plurality of precursors are adjusted to control the composition of the high mobility material layer.5. The method of claim 1 , wherein the step of forming a plurality of precursors further comprises depositing a plurality of precursors on the substrate.6. The method of claim 5 , wherein the pulse number claim 5 , the energy density and the pulse time of the pulse laser processing and the thickness of one of the plurality of precursors are adjusted to control the ...

Nitride semiconductor wafer

A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of Al x Ga 1-x N (0≦x≦0.05) and Al y Ga 1-y N (0<y≦1 and x<y) layers. Only the Al y Ga 1-y N layer in the alternating layer is doped with an acceptor.

Nitride semiconductor

To provide a high-quality nitride semiconductor ensuring high emission efficiency of a light-emitting element fabricated. In the present invention, when obtaining a nitride semiconductor by sequentially stacking a one conductivity type nitride semiconductor part, a quantum well active layer structure part, and a another conductivity type nitride semiconductor part opposite the one conductivity type, the crystal is grown on a base having a nonpolar principal nitride surface, the one conductivity type nitride semiconductor part is formed by sequentially stacking a first nitride semiconductor layer and a second nitride semiconductor layer, and the second nitride semiconductor layer has a thickness of 400 nm to 20 μm and has a nonpolar outermost surface. By virtue of selecting the above-described base for crystal growth, an electron and a hole, which are contributing to light emission, can be prevented from spatial separation based on the QCSE effect and efficient radiation is realized. Also, by setting the thickness of the second nitride semiconductor layer to an appropriate range, the nitride semiconductor surface can avoid having extremely severe unevenness.

Band Engineered Semiconductor Device and Method for Manufacturing Thereof

The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Compound semiconductor device and method of manufacturing the same

A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.

Contact Structure Of Semiconductor Device

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Semiconductor apparatus

A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.

Compound semiconductor device and method of manufacturing the same

An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.

Method for making epitaxial structure

A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (); a plurality of convex structures () formed on the substrate (), in which every two adjacent convex structures () are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures () is less than 50 nm in width; a plurality of floated films (), in which the floated films () are partitioned into a plurality of sets, a channel layer is formed on a convex structure () between the floated films () in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and the cavity between the every two adjacent convex structures () is filled with an insulating material (); and a gate stack () formed on each channel layer. 1. A semiconductor structure , comprising:a substrate;a plurality of convex structures formed on the substrate, wherein every two adjacent convex structures are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures is less than 50 nm in width;a plurality of floated films, wherein each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and the cavity size between the every two adjacent convex structures is filled with an insulating material so as to produce a strain in each channel layer; anda gate stack formed on each channel layer.2. The semiconductor structure according to claim 1 , wherein a width of each convex structure increases gradually from a middle part thereof to a top part thereof so that a cavity size between top parts of two adjacent convex ...

HYBRID MULTI-JUNCTION PHOTOVOLTAIC CELLS AND ASSOCIATED METHODS

A multi-junction photovoltaic cell includes a substrate and a back contact layer formed on the substrate. A low bandgap Group IB-IIIB-VIBmaterial solar absorber layer is formed on the back contact layer. A heterojunction partner layer is formed on the low bandgap solar absorber layer, to help form the bottom cell junction, and the heterojunction partner layer includes at least one layer of a high resistivity material having a resistivity of at least 100 ohms-centimeter. The high resistivity material has the formula (Zn and/or Mg)(S, Se, O, and/or OH). A conductive interconnect layer is formed above the heterojunction partner layer, and at least one additional single-junction photovoltaic cell is formed on the conductive interconnect layer, as a top cell. The top cell may have an amorphous Silicon or p-type Cadmium Selenide solar absorber layer. Cadmium Selenide may be converted from n-type to p-type with a chloride doping process. 1. A method of making a p-type Cadmium Selenide semiconductor material , comprising:depositing a layer of Cadmium Selenide;coating the layer of Cadmium Selenide with a solution comprising a solvent and at least one of chloride selected from the group consisting of chlorides of Group IA elements, chlorides of group IB elements, and chlorides of Group IIIB elements; andheating the layer of Cadmium Selenide in an environment having an ambient temperature of between 300 and 500 degrees Celsius for a time between three and thirty minutes while at least partially preventing the evaporation of Selenium from the layer of Cadmium Selenide.2. The method of claim 1 , wherein Selenium is at least partially prevented from evaporating from the layer of Cadmium Selenide during the step of heating by executing the step of heating in a Selenium enriched atmosphere.3. The method of claim 1 , wherein Selenium is at least partially prevented from evaporating from the layer of Cadmium Selenide during the step of heating by physically impeding the evaporation ...

Reducing Autodoping of III-V Semiconductors By Atomic Layer Epitaxy (ALE)

In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped III-V semiconductor materials are also provided. 1. A method for forming a doped III-V semiconductor material on a substrate , the method comprising the steps of:(a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element;(b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy.2. The method of claim 1 , wherein the substrate comprises an indium phosphide substrate.3. The method of claim 1 , wherein the step (a) comprises the steps of:contacting the substrate with at least one group III or at least one group V element vapor phase epitaxy source under conditions sufficient to form the first monolayer on the substrate; andpurging any remaining reactants.4. The method of claim 3 , wherein the conditions ...

FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS

A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. 1. A method of forming a fin structure comprising:forming fin structures from semiconductor material;removing a sacrificial channel portion of the fin structures, wherein doped source and drain regions portions of the fin structures remain between a channel opening formed by removing the sacrificial channel portion of the fin structures; andforming an intrinsic channel region in the channel opening.2. The method of claim 1 , wherein forming the intrinsic channel region:removing the sacrificial channel portion with an etch that is selective to a underlying semiconductor substrate and the and drain regions; andepitaxially forming the intrinsic channel region on an exposed surface of the semiconductor substrate.3. The method of claim 2 , wherein the intrinsic channel region is a functional channel region.4. The method of claim 2 , wherein the semiconductor material that the fin structures are formed from is in situ doped.5. The method of claim 4 , wherein the semiconductor material that the fin structures are formed from is epitaxially grown on the semiconductor substrate.6. The method of claim 4 , wherein the fin structures are formed using sidewall image transfer.7. A method of forming a fin structure comprising:forming fin structures from semiconductor material having a first conductivity type;removing a sacrificial channel portion of the fin structures, wherein doped source and drain regions portions of the fin structures having the first conductivity type remain ...

Fin Spacer Protected Source and Drain Regions in FinFETs

A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin. 1. A method comprising:etching a semiconductor substrate to form a first plurality of recesses;filling the first plurality of recesses to form Shallow Trench Isolation (STI) regions, wherein a portion of the semiconductor substrate between the STI regions forms a semiconductor strip, wherein edges of the semiconductor strip contact sidewalls of the STI regions;replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is formed over the first semiconductor layer, wherein the first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer;recessing the STI regions, wherein a portion of the semiconductor strip with edges exposed by the recessed STI regions forms a semiconductor fin;forming a gate stack over a middle portion of the semiconductor fin;forming gate spacers on sidewalls of the gate stack;forming fin spacers on sidewalls of an end portion of the semiconductor fin;recessing the end portion of the ...

High Efficiency FinFET Diode

Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. 1. A method of forming a semiconductor device , the method comprising:providing a substrate having opposing first and second ends;forming a first and a second groups of one or more substantially equal-spaced, parallel, elongated, and equal numbered semiconductor fin structures upon the substrate adjacent the first and the second ends, respectively, the first and second groups being spaced apart from each other;forming a plurality of dielectric strips to be disposed among the first and the second groups of fin structures for electric insulation from one another;implanting the substrate with a dopant of either a first conductivity type or a second conductivity type opposite the first conductivity type;forming one or more substantially equal-spaced and parallel elongated gate structures formed upon the first and the second groups of fin structures such that each gate structure traverses both the first and the second groups of fin structures perpendicularly;forming a ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film. 1. (canceled)2. A method for manufacturing a semiconductor device including a transistor comprises:forming an oxide semiconductor film;forming a first insulating film over the oxide semiconductor film;forming a metal oxide film over and in contact with the first insulating film;performing a heat treatment after forming the metal oxide film;forming a conductive film over the metal oxide film after performing the heat treatment; andforming a second insulating film over the conductive film,wherein a top surface of the oxide semiconductor film comprises a first region, a second region, and a third region between the first region and the second region,wherein each of the first region and the second region is in contact with the second insulating film,wherein the conductive film overlaps with the third region with the first insulating film and the metal oxide film therebetween,wherein the second insulating film comprises hydrogen, andwherein the metal oxide film and the conductive film are collectively configured to be a gate electrode of a transistor.3. The method for manufacturing a semiconductor device according to claim 2 ,wherein the metal oxide film comprises at least one of indium, gallium, zinc, and oxygen.4. The method for manufacturing a semiconductor device according to claim 2 ...

Contact structures and methods of forming the same

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Doped Diamond Semi-Conductor and Method of Manufacture

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

Epitaxial Layers in Source/Drain Contacts and Methods of Forming the Same

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Integrated Circuit Structure With Non-Gated Well Tap Cell

The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell. 1. A method , comprising:receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell;forming first fin active regions in the well tape cell and second fin active regions in the IC cell;forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active regions of the well tape cell;forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions;epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; andforming contacts landing on the first S/D features within the well tape cell.2. The method of claim 1 , wherein the epitaxially growing further includes epitaxially growing second S/D features on the second S/D regions of the second fin active regions within the IC cell using the gate stacks to constrain the epitaxially growing.3. The method of claim 1 , further comprising ...

High Surface Dopant Concentration Formation Processes and Structures Formed Thereby

Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region. 1. A structure comprising: a surface dopant region at an upper surface of the source/drain region, the surface dopant region comprising a peak dopant concentration proximate the upper surface of the source/drain region; and', 'a remainder portion of the source/drain region having a source/drain dopant concentration, the peak dopant concentration being at least an order of magnitude greater than the source/drain dopant concentration;, 'an active area on a substrate, the active area comprising a source/drain region, the source/drain region comprisinga dielectric layer over the active area; anda conductive feature through the dielectric layer to the active area and contacting the source/drain region at the upper surface of the source/drain region.2. The structure of claim 1 , wherein the surface dopant region comprises a dopant concentration gradient that decreases from the peak dopant concentration at a rate of 1 decade of concentration per 5 nm or less.3. The structure of claim 2 , wherein ...

Layered structure, semiconductor device including layered structure, and semiconductor system including semiconductor device

In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ε-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.

Method of forming shaped source/drain epitaxial layers of a semiconductor device

In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

VERTICAL TRANSISTORS HAVING IMPROVED CONTROL OF TOP SOURCE OR DRAIN JUNCTIONS

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a channel fin over a substrate and forming a top spacer region around a top portion of the channel fin, wherein the top spacer region includes a dopant. A dopant drive-in process is applied, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin to create a doped top portion of the channel fin and a top junction between the doped top portion of the channel fin and a main body portion of the channel fin. 1. A method of forming a semiconductor device , the method comprising:forming a channel fin over a substrate;forming a top spacer region around a top portion of the channel fin, wherein the top spacer region comprises a dopant; andapplying a dopant drive-in process, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin to create a doped top portion of the channel fin and a top junction between the doped top portion of the channel fin and a main body portion of the channel fin.2. The method of further comprising forming a gate structure across from the substrate and around the channel fin.3. The method of claim 2 , wherein the gate structure laterally overlaps the top junction.4. The method of claim 1 , wherein the top spacer comprises a low-k dielectric material.5. The method of wherein the location of the top junction is controlled based at least in part on a thickness dimension of the top spacer region.6. The method of wherein the location of the top junction is controlled based at least in part on a temperature of the dopant drive-in process.7. The method of wherein the location of the top junction is controlled based at least in part on a duration of the dopant drive-in process.8. The method of claim 1 , wherein claim 1 , subsequent to the dopant drive-in ...

Increasing Source/Drain Dopant Concentration to Reduced Resistance

A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage. 1. A device comprising:a semiconductor substrate;isolation regions extending into the semiconductor substrate;a semiconductor fin between opposite portions of the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions;a first gate stack and a second gate stack on top surfaces and sidewalls of a first portion and a second portion of the semiconductor fin, respectively; and a first silicon phosphorous layer having a first highest phosphorous atomic percentage; and', 'a second silicon phosphorous layer overlapping a bottom portion of the first silicon phosphorous layer, with the first silicon phosphorous layer comprising opposing sidewall portions on opposite sides of the second silicon phosphorous layer, wherein the second silicon phosphorous layer has a second highest phosphorous atomic percentage higher than about 6 percent, and the second highest phosphorous atomic percentage is higher than the first highest phosphorous atomic percentage., 'a source/drain region extending into a third portion of the semiconductor fin, wherein the third portion is ...

Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Semiconductor Device Having a Shaped Epitaxial Region

A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor. 1. A semiconductor device comprising:a channel region within a semiconductor material; and a bulk region with a first concentration of a first dopant;', 'an interface region with a second concentration of the first dopant less than the first concentration; and', 'a cleaning region with a third concentration of the first dopant greater than the second concentration., 'a source/drain region adjacent to the channel region, wherein the source/drain region has a height to width ratio of between about 0.5 and about 10 and comprises2. The semiconductor device of claim 1 , wherein the first dopant is phosphorous.3. The semiconductor device of claim 1 , wherein the cleaning region comprises a shaping dopant that is not present in the bulk region.4. The semiconductor device of claim 3 , wherein the shaping dopant is germanium.5. The semiconductor device of claim 4 , wherein the germanium has a concentration within the cleaning region of between about 1% and about 10%.6. The semiconductor device of claim 1 , wherein the first concentration is between about 1E+20 atom/cm3 and about 1E+23 atom/cm3 and the second concentration is between about 1E+20 atom/cm3 and about 1E+24 atom/cm3.7. The semiconductor device of claim 1 , wherein the cleaning region has a thickness of between about 1 nm and about 50 nm.8. The semiconductor device of claim 1 , wherein the source/drain region has a planar ...

CHALCOGENIDE FILMS FOR SELECTOR DEVICES

Methods are provided for depositing doped chalcogenide films. In some embodiments the films are deposited by vapor deposition, such as by atomic layer deposition (ALD). In some embodiments a doped GeSe film is formed. The chalcogenide film may be doped with carbon, nitrogen, sulfur, silicon, or a metal such as Ti, Sn, Ta, W, Mo, Al, Zn, In, Ga, Bi, Sb, As, V or B. In some embodiments the doped chalcogenide film may be used as the phase-change material in a selector device. 1. An atomic layer deposition (ALD) method for forming a selector device comprising depositing a doped chalcogenide film on a substrate by a process comprising multiple deposition cycles in which the substrate is alternately and sequentially contacted with two or more reactants for forming the chalcogenide film , and wherein the substrate is contacted with a third dopant precursor in one or more of the deposition cycles.2. The method of claim 1 , wherein the substrate is alternately and sequentially contacted with each of the reactants in the one or more of the deposition cycles.3. The method of claim 1 , wherein the ALD method comprises two or more deposition cycles in which the substrate is alternately and sequentially contacted with the first reactant claim 1 , the second reactant and the dopant precursor to form the doped chalcogenide film.4. The method of claim 1 , wherein the ALD method comprises a first primary deposition sub-cycle in which the substrate is alternately and sequentially contacted with the first reactant and a second reactant to form a chalcogenide material and a second dopant sub-cycle in which the substrate is contacted with the dopant precursor.5. The method of claim 4 , wherein the substrate is alternately and sequentially contacted with one or both of the first and second reactants and the dopant precursor in the dopant sub-cycle.6. The method of claim 4 , wherein the dopant sub-cycle is provided at one or more intervals in the ALD method to obtain the desired dopant ...

METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER

The present invention provides a method for manufacturing a silicon epitaxial wafer, characterized in that a silicon epitaxial layer is formed on an N-type silicon single crystal wafer manufactured by doping with arsenic to set a resistivity to 1.0 to 1.7 mΩcm and further doping with carbon, nitrogen, or both carbon and nitrogen. As a result, there can be provided the method for manufacturing a silicon epitaxial wafer that can suppress occurrence of stacking faults at the time of performing epitaxial growth on the arsenic-doped super-low resistance silicon single crystal wafer. 1. A method for manufacturing a silicon epitaxial wafer , wherein a silicon epitaxial layer is formed on an N-type silicon single crystal wafer manufactured by doping with arsenic to set a resistivity to 1.0 to 1.7 mΩcm and further doping with carbon , nitrogen , or both carbon and nitrogen.2. The method for manufacturing a silicon epitaxial wafer according to claim 1 ,wherein, at the time of doping with carbon in the N-type silicon single crystal wafer, carbon-doped concentration is set to 0.2 to 5 ppma.3. The method for manufacturing a silicon epitaxial wafer according to claim 1 ,{'sup': 13', '14', '3, 'wherein, at the time of doping with nitrogen in the N-type silicon single crystal wafer, nitrogen-doped concentration is set to 1×10to 2×10atoms/cm.'}4. The method for manufacturing a silicon epitaxial wafer according to claim 2 ,{'sup': 13', '14', '3, 'wherein, at the time of doping with nitrogen in the N-type silicon single crystal wafer, nitrogen-doped concentration is set to 1×10to 2×10atoms/cm.'} The present invention relates to a method for manufacturing a silicon epitaxial wafer having an epitaxial layer formed on a silicon single crystal wafer surface.In a majority of methods for manufacturing semiconductor electronic components, a silicon single crystal that is a starting material is manufactured by a so-called Czochralski (CZ) method or the like. For example, in the CZ method, a ...

METHOD OF PRODUCING A TWO-DIMENSIONAL MATERIAL

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm. 1. A method of producing a two-dimensional crystalline material , the method comprising:providing a substrate having nucleation sites within a reaction chamber;introducing at a precursor entry point a precursor into the reaction chamber, the precursor being in a gas phase and/or suspended in a gas;heating the substrate to a temperature that is within a decomposition range of the precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; andcooling the precursor entry point;wherein the reaction chamber is a close coupled reaction chamber such that a separation between the substrate surface upon which the two-dimensional crystalline material is formed and the point at which the precursor enters the reaction chamber is sufficiently small, and a thermal gradient between the substrate surface and the point at which the precursor enters the chamber is sufficiently steep, such that the fraction of precursor that reacts in the gas phase within the reaction chamber is low enough to ...

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Semiconductor device and method of manufacturing the same

A germanium optical receiver in which a dark current is small is achieved. The germanium optical receiver is formed of a p-type germanium layer, a non-doped i-type germanium layer, and an n-type germanium layer that are sequentially stacked on an upper surface of a p-type silicon core layer, a first cap layer made of silicon is formed on the side surface of the i-type germanium layer, and a second cap layer made of silicon is formed on the upper surface and side surface of the n-type germanium layer. The n-type germanium layer is doped with such an element as phosphorus or boron having a covalent bonding radius smaller than a covalent bonding radius of germanium.

FINFET WITH CONSTRAINED SOURCE-DRAIN EPITAXIAL REGION

A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer. 1. A method comprising:forming a plurality of fins on a substrate;forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed;forming spacers on opposite sidewalls of the second portion of the plurality of fins;removing the second portion of the plurality fins to form a trench between the spacers; andforming an epitaxial layer in the trench, wherein lateral growth of the epitaxial layer is constrained by the spacers.2. The method of claim 1 , wherein forming the epitaxial layer comprises:epitaxially growing an in-situ doped semiconductor material including silicon or silicon-germanium.3. The method of claim 1 , wherein the substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.4. The method of claim 1 , wherein removing the second portion of the plurality of fins to form the trench between the spacers comprises:removing an upper region of the second portion of the plurality of fins while a lower region of the second portion of the plurality of fins remains in the trench,wherein the lower region of the second portion of the plurality of fins provides a seed for growing the epitaxial layer on SOI substrates.5. The method of claim 1 , further comprising:forming an extended epitaxial region directly on top of the epitaxial layer and above the trench.6. The method of claim 5 , wherein the extended epitaxial region comprises epitaxial growth on a {111} plane.7. ...

DOPED SEMICONDUCTOR FILMS AND PROCESSING

A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

HALOGENATED DOPANT PRECURSORS FOR EPITAXY

A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions. 1. A method of forming a film on a substrate , comprising:positioning a substrate within a processing volume of a process chamber;heating the substrate; andforming a semiconductor film on the substrate by exposing the substrate to two or more reactants comprising a silicon source and a halogenated dopant source, wherein the semiconductor film comprises one or more epitaxial regions and one or more non-epitaxial regions.2. The method of claim 1 , wherein the one or more epitaxial regions comprise strained silicon layers.3. The method of claim 2 , wherein the one or more epitaxial regions have a dopant concentration of at least 1.0*10atoms per cubic centimeter.4. The method of claim 2 , wherein the halogenated dopant source comprises a compound having a chemical formula of DHX′ claim 2 , where D is a Group III or Group V dopant element claim 2 , H is hydrogen claim 2 , X′ is a halogen claim 2 , and x=1 claim 2 , 2 claim 2 , or 3.5. The method of claim 2 , wherein the halogenated dopant source comprises phosphorous claim 2 , boron claim 2 , arsenic claim 2 , or antimony.6. The method of claim 2 , wherein the halogenated dopant source comprises phosphorous trichloride.7. The method of claim 6 , wherein a flow rate of the phosphorous trichloride into the process chamber is between about 10 sccm and about 60 sccm.8. The method of claim 6 , further comprising:exposing the substrate to a non-halogenated dopant source while exposing the substrate to the halogenated dopant source.9. The method of claim 8 , wherein the non- ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate. The epitaxy region includes a substance with a lattice constant that is larger than a lattice constant of the substrate. The concentration profile of a substance in the epitaxy region is monotonically increasing from a bottom portion of the epitaxy region to a of the epitaxy region. A first layer of the epitaxy region has a height to width ratio of about 2. The first layer is a layer positioned closest to the substrate, and the first layer has an average concentration of the substance from about 20 to about 32 percent. A second layer disposed over the first layer. The second layer has a bottom portion with a concentration of the substance from about 27 percent to about 37 percent. 1. A semiconductor structure , comprising:a substrate; and a substance with a first lattice constant larger than a second lattice constant of the substrate; a concentration profile of the substance being monotonically increased from a portion closest to the substrate to a portion further away from the substrate; and', [ a bottom thickness; and', 'a lateral thickness,', 'wherein a thickness ratio of the bottom thickness and the lateral thickness is about 2; and, 'a first layer in proximity to an interface between the epitaxy region and the substrate, and the average concentration of the substance in the first layer is from about 20 to about 32 percent, the first layer comprising, a bottom portion, having a concentration of the substance from about 27 percent to about 37 percent; and', 'a dopant., 'a second layer, positioned over the first layer, comprising'}], 'a multilayer structure, each layer thereof having an average concentration of the substance different from other layers, the multilayer structure comprising], 'an epitaxy region, partially disposed in the substrate, comprising'}2. The semiconductor structure of claim 1 , wherein ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment. 1. A semiconductor structure , comprising:a substrate;a fin structure protruding from the substrate, the fin structure extending along a first direction;isolation features disposed on both sides of the fin structure;a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; andwherein the gate structure comprises a first segment and a second segment over the first segment, and the first segment is sandwiched by a first dielectric sidewalls doped with group III or group V elements.2. The semiconductor structure of claim 1 , wherein the second segment is sandwiched by a second dielectric sidewalls doped with carbon or nitrogen.3. The semiconductor structure of claim 1 , further comprising a high K dielectric layer between the fin structure and the first segment of the gate structure.4. The semiconductor structure of claim 1 , wherein the first segment and the second segment of the gate structure comprises metallic materials.5. The semiconductor structure of claim 1 , wherein a height of the first segment ranges from about 5 nm to about 50 nm.6. The semiconductor structure of claim 1 , wherein the ratio of a height of the second segment to a height of the first segment ranges from about 2 to about 6.7. The semiconductor structure of claim 1 , wherein ...

SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide epitaxial substrate includes: a silicon carbide single crystal substrate; a first silicon carbide layer on the silicon carbide single crystal substrate, the first silicon carbide layer having a first concentration of carriers; and a second silicon carbide layer on the first silicon carbide layer, the second silicon carbide layer having a second concentration of carriers. A transition region in which the concentration of the carriers is changed between the first concentration and the second concentration has a width of less than or equal to 1 μm. A ratio of a standard deviation of the second concentration to an average value of the second concentration is less than or equal to 5%, the ratio being defined as uniformity of the second concentration in a central region. The central region has an arithmetic mean roughness of less than or equal to 0.5 nm. 1. A silicon carbide epitaxial substrate comprising:a silicon carbide single crystal substrate having a first main surface;a first silicon carbide layer on the silicon carbide single crystal substrate, the first silicon carbide layer having a first concentration of carriers; anda second silicon carbide layer on the first silicon carbide layer, the second silicon carbide layer having a second concentration of carriers smaller than the first concentration, the second silicon carbide layer including a second main surface opposite to the first main surface,in a concentration profile of the carriers along a layering direction in which the first silicon carbide layer and the second silicon carbide layer are layered, a transition region in which the concentration of the carriers is changed between the first concentration and the second concentration having a width of less than or equal to 1 μm,a ratio of a standard deviation of the second concentration to an average value of the second concentration being less than or equal to 5%, the ratio being defined as uniformity of the second concentration in a central ...

CRYSTALLINE MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE

Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a corundum-structured crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide semiconductor thin film is 0.1 μm or less in a surface roughness (Ra). 110-. (canceled)11. A crystalline oxide semiconductor film comprising:a corundum-structured oxide semiconductor;a surface roughness (Ra) that is 0.1 μm or less; anda thickness that is 1 μm or more.12. The crystalline oxide semiconductor film of comprising:a non-magnetic metal.13. The crystalline oxide semiconductor film of claim 11 , wherein the crystalline oxide semiconductor film comprises at least gallium.14. The crystalline oxide semiconductor film of claim 11 , wherein the crystalline oxide semiconductor film is at least partially doped.15. The crystalline oxide semiconductor film of comprising:a dopant.16. The crystalline oxide semiconductor film of claim 15 , wherein the dopant is at least one selected from Ge claim 15 , Sn claim 15 , Si claim 15 , Ti claim 15 , Zr and Hf.17. The crystalline oxide semiconductor film of comprising:an insulating film.18. The crystalline oxide semiconductor film of claim 17 , wherein the crystalline oxide semiconductor film laminated on the insulating film has a multilayer structure.19. The crystalline oxide semiconductor film of comprising:at least one selected from Br and I.20. The crystalline oxide semiconductor film of comprising:{'sub': 2', '3, 'α-GaO.'}21. A semiconductor device comprising:{'claim-ref': {'@idref': 'CLM-00011', 'claim 11'}, 'the crystalline oxide semiconductor film of ; and'}an electrode arranged on the crystalline oxide semiconductor film.22. A semiconductor device comprising:{'claim-ref': {'@idref': 'CLM-00013', 'claim 13'}, 'the crystalline oxide semiconductor film of ; and'}an electrode arranged on the crystalline oxide ...

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE HAVING ENHANCED CHARGE TRAPPING EFFICIENCY

A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices. 1. A multilayer structure comprising:a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm, and further wherein the single crystal semiconductor handle substrate has a handle crystal orientation;an epitaxial layer in direct contact with the front surface of the single crystal semiconductor handle substrate, wherein the epitaxial layer has a resistivity between about 100 Ohm-cm and about 5000 Ohm-cm and further wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation;a charge trapping layer in direct contact with the epitaxial layer, the charge trapping layer comprising polycrystalline silicon and having a resistivity of at least about 3000 Ohm-cm;a dielectric layer in direct contact with the charge trapping layer; anda single crystal semiconductor device layer in direct contact with ...

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure and a second gate structure formed over a fin structure;raised source and drain regions formed adjacent to the first gate structure; andraised source and drain regions formed adjacent to the second gate structure,wherein side surfaces of the raised source and drain regions of the first gate structure contact a first liner material covering a portion of the first gate structure, which first liner material extends to an upper surface of the fin structure,wherein the side surfaces of the raised source and drain regions of the first gate structure are separated from a first spacer material formed on the first gate structure by the first liner material covering the portion of the first gate structure, andwherein side surfaces of the raised source and drain regions of the second gate structure contact a side surface of a second liner material covering a portion of the second gate structure and a side surface of a second spacer material formed on the second gate structure which is not covered by the second liner material.2. The structure of claim 1 , wherein the first gate structure is a gate structure of an N-type FET (NFET) and the second gate structure is a gate structure of a P-type FET (PFET).3. The structure of claim 2 , wherein:the first liner material and first spacer material formed on the first gate structure form a first sidewall spacer on a side surface of the first ...

Integrated CMOS Source Drain Formation With Advanced Control

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform. 1. A method of forming a semiconductor device , the method comprising:performing an anisotropic etch process on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material, the surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed;performing an isotropic etch process on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity; andforming a layer of deposited material via a selective epitaxial growth (SEG) process on a surface of the cavity, the substrate not subjected to a pre-clean process between formation of the cavity and SEG.2. The method of claim 1 , wherein the isotropic etch occurs in a first process chamber and the method further comprises moving the substrate from the first process chamber to a second process chamber for the SEG process.3. The method of claim 2 , further comprising determining the distance that the semiconductor material has been recessed after isotropic etch and prior to the SEG process.4. The method of claim 3 , further comprising ...

Integrated Circuit Device Fins

Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

DOPING CONTROL METHODS AND RELATED SYSTEMS

A system for cleaning dopant contamination in a process chamber is disclosed. The system includes a susceptor and a chamber kit component, a first plurality of lamps configured to heat the susceptor, a second plurality of lamps configured to heat the chamber kit component, and a gas supply configured to provide a chlorine cleaning gas. The system is configured to deposit a layer on a substrate at a deposition temperature and perform an in-situ clean of the process chamber, including the chamber kit component, at the deposition temperature. A method for cleaning dopant contamination includes depositing a layer over a substrate at a deposition temperature, performing an in-situ clean of the process chamber and a process kit component at the deposition temperature, unloading the substrate, and performing a dedicated clean at a clean temperature. In some examples, the clean temperature is about equal to the deposition temperature.

METHOD OF SELECTIVE EPITAXY

Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane. 1. A method of processing a substrate , comprising:epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound, wherein the trench has a sidewall, and the sidewall comprises an oxide and a nitride.2. The method of claim 1 , wherein the halogenated silicon compound comprises a chlorinated silane.3. The method of claim 2 , wherein the chlorinated silane comprises silicon tetrachloride (SiCl) claim 2 , monochlorosilane (SiHCl) claim 2 , dichlorosilane (SiHCl) claim 2 , trichlorosilane (SiHCl) claim 2 , hexachlorodisilane (SiCl) claim 2 , octachlorotrisilane (SiCl) claim 2 , or a combination of two or more thereof.4. The method of claim 1 , wherein the halogenated germanium compound comprises a chlorinated germane.5. The method of claim 4 , wherein the chlorinated germane comprises germanium tetrachloride (GeCl) claim 4 , chlorogermane (GeHCl) claim 4 , dichlorogermane (GeHCl) claim 4 , trichlorogermane (GeHCl) claim 4 , hexachlorodigermane (GeCl) claim 4 , octachlorotrigermane (GeCl) claim 4 , or a combination of two or more thereof.6. A method of processing a substrate claim 4 , comprising:forming a dielectric layer on a silicon substrate, wherein the dielectric layer comprises an oxide and a nitride;forming a ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second regions; providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate; and forming first trenches in the first region at both sides of the first gate structure. The method further includes forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer; forming second trenches in a second region at both sides of the second gate structure; and forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer.

FABRICATION METHOD FOR A 3-DIMENSIONAL NOR MEMORY ARRAY

A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity. 1. A process for forming a memory structure over a planar surface of a semiconductor substrate , comprising:forming above the semiconductor substrate a plurality of active stacks placed substantially at predetermined positions along a first direction that is substantially parallel to the planar surface, separated one from another by a first electrically insulative material, each active stack extending lengthwise along a second direction that is (i) substantially parallel to the planar surface and (ii) substantially orthogonal the first direction, wherein (i) each active stack comprises a plurality of active ...

METHOD FOR REDUCING CONTACT RESISTANCE IN SEMICONDUCTOR STRUCTURES

Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer. 115-. (canceled)16. A structure comprising;a fin over a substrate;a gate structure, on the fin, having a sidewall;a sidewall spacer adjacent to the sidewall;a source/drain (S/D) region adjacent to the sidewall spacer; anda layer of doped crystalline material disposed on the S/D region, wherein the layer of doped crystalline material comprises a higher doping concentration than a doping concentration of the S/D region.17. The structure of claim 16 , wherein the layer of doped crystalline material is disposed in the fin.18. The structure of claim 16 , wherein the layer of doped crystalline material comprises a layer of doped crystalline semiconductor material.19. The structure of claim 18 , wherein the layer of doped crystalline semiconductor material comprises a layer of n-doped crystalline silicon with a doping concentration in a range of about 5×10atoms/cmto about 7×10atoms/cm.20. A structure comprising;a fin, over a substrate, having a top surface and a pair of opposing side surfaces;a gate structure, on the fin, having a sidewall;a sidewall spacer adjacent to the sidewall;a source/drain (S/D) region in the fin and adjacent to the sidewall spacer, a portion of the source/drain (S/D) region being disposed in the fin; anda layer of doped crystalline material on the S/D region and formed on the side surface of the fin, wherein the layer of doped crystalline material comprises a higher doping concentration than a doping concentration of the S/D region.21. The structure of claim 18 , wherein the layer of doped ...

Transistor having high breakdown voltage and method of making the same

A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×10 19 ions/cm 3 . The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.