PROCEDURE FOR ZWEISCHICHT HDP CVD AND PE-CVDDECKSCHICHT IN HIGHLY DEVELOPED BEOLVERBINDUNGSSTRUKTUREN

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Techniques for enhancing vertical gate-all-around FET performance

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact. 1. A method of fabricating a semiconductor structure comprising a semiconductor substrate , a dielectric layer on the substrate , and a plurality of gates located within the dielectric layer , above the substrate , the plurality of gates including a first gate and a pair of adjacent gates on sides of the first gate , and each of the gates including a gate electrode , the method comprising:forming gate caps on the pair of adjacent gates;forming conductive metal trenches in the dielectric layer and on the sides of the first gate, between the first gate and the adjacent gates, each of the metal trenches being spaced from and electrically separated from the first gate; and depositing a conductive material above the first gate and above and on the conductive metal trenches, and', 'etching away a portion of the conductive material from above a second of the conductive metal trenches to separate electrically the contact from the second of the conductive metal trenches., 'after forming the conductive metal trenches, forming a contact over the gate electrode of the first gate and laterally extending from above the first gate, to and directly on a top of one of the ...

PE-ALD of TaN diffusion barrier region on low-k materials

Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaCl₅). The invention generates a sharp interface between low-k materials and liner materials.

A PROCEDURE FOR THE SEPARATION OF A LAYER OF METAL ON A SEMICONDUCTOR INTERKONNEKTSTRUKTUR WITH A SURFACE LAYER

在不使用化学机械抛光的情况下形成平坦的Cu互连的方法

... 本发明提供了一种在不使用化学机械抛光的情况下形成平坦的Cu互连的方法，即：控制铜互连结构的形状的方法，该方法具有以下步骤：使用第一镀覆方法在一镀液中以第一镀覆时间在铜籽晶层上镀覆具有预定最终形状的铜互连结构，其中第一镀覆时间小于镀覆全部最终形状所必需的总时间；以及在铜镀液中以第二时间段电处理镀覆的铜互连结构，第二时间段至少足够形成预定最终形状。 ...

Vertical Vacuum Channel Transistor

A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

Method to generate porous organic dielectric

The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas ...

VTFET having a V-shaped groove at the top junction region

A vertical transport field effect transistor (VTFET) is provided that includes a vertical semiconductor channel material structure (i.e., fin or pillar) having a V-shaped groove located in the topmost surface thereof. A top source/drain structure is formed in contact with the V-shaped groove present in the topmost surface of the vertical semiconductor channel material structure. No drive-in anneal is needed to form the top source/drain structure. The presence of the V-shaped groove at the top junction region provides a VTFET that has improved device performance.

Removal of semiconductor growth defects

After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

MTJ STACK ETCH USING IBE TO ACHIEVE VERTICAL PROFILE

Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d). 1. A method for MTJ patterning for a MTJ device , comprising:(a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer,(b) conducting a first ion beam etching of the MTJ device to remove a portion of a horizontal surface of the MTJ layer;(c) stopping the first ion beam etching and rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position;(d) stopping rotating the MTJ device and conducting a second ion beam etching of the MTJ device to further remove the portion of the horizontal surface of the MTJ layer; and(e) repeating steps (c) and (d) until the horizontal surface of the MTJ layer is substantially removed.2. The method of claim 1 , wherein the MTJ layer comprises a plurality of magnetic thin films with a tunnel barrier.3. The method of claim 1 , wherein the MTJ layer comprises a bottom electrode layer disposed on a bit line ...

Pe-ald of tan diffusion barrier re-gion on low-k materials

Extended contact area using undercut silicide extensions

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

MOSFET gate and source/drain contact metallization

A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Resistive memory device with electrical gate control

Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode.

Reducing Off-State Leakage Current in Si/SiGe Dual Channel CMOS

Techniques for reducing off-state current in dual channel CMOS devices are provided. In one aspect, a method for forming a dual channel finFET includes: patterning NFET/PFET fins on a wafer from a first channel material and a second Ge-containing channel material; depositing a GeOlayer on the fins; annealing the fins to selectively oxidize the at least one PFET fin; depositing a liner onto the fins which induces a negative charge in the PFET fin(s); removing unreacted GeOand the liner from the NFET fin(s); depositing a dielectric layer onto the fins which induces a positive charge in the NFET fin(s). A dual channel finFET device is also provided. 1. A method for forming a dual channel fin field-effect transistor (finFET) device , comprising the steps of:patterning fins on a wafer, wherein the fins comprise at least one n-channel FET (NFET) fin formed from a first channel material and at least one p-channel FET (PFET) fin formed from a second channel material comprising germanium (Ge), and wherein the first channel material and the second channel material comprise dual channels of the finFET device;{'sub': '2', 'depositing a germanium oxide (GeO) layer on the fins;'}{'sub': 2', '2, 'annealing the fins to selectively oxidize the at least one PFET fin based on a reaction of the GeOlayer with the second channel material thereby forming a first oxide layer on the at least one PFET fin while unreacted GeOremains on the at least one NFET fin;'}depositing a liner onto the fins, wherein the liner has a positive polarity which induces a negative charge in the at least one PFET fin;{'sub': '2', 'removing the unreacted GeOalong with the liner from the at least one NFET fin;'}forming a second oxide layer on the at least one NFET fin; anddepositing a dielectric layer onto the fins, wherein the dielectric layer has a negative polarity which induces a positive charge in the at least one NFET fin.2. The method of claim 1 , further comprising the steps of:forming gates over the fins; ...

Vertical transport fin field effect transistor with asymmetric channel profile

A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

LOW FORMING VOLTAGE NON-VOLATILE MEMORY (NVM)

A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first area and contacts a surface of one of the second electrically conductive structures that contacts a surface of an underlying first electrically conductive structure, and the other of the sacrificial conductive pads has a second area, different from the first area, and contacts a surface of another of the second electrically conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and to convert a dielectric switching material of the patterned material stack into a conductive filament. After plasma treatment, the pair of sacrificial conductive pads is removed.

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT

A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region. 1. A bipolar junction transistor , comprising:a collector having a first surface on a first level and a second surface on a second level;a base formed on the second level of the collector;an emitter formed on the base;a dielectric liner formed on vertical sidewalls of the collector, the base and the emitter and over the first surface;a conductive region formed adjacent to the base within the dielectric liner; anda base contact formed along one of the vertical sidewalls to connect to the base through the conductive region.2. The bipolar junction transistor as recited in claim 1 , wherein the base includes a graded profile having a region of higher reactant concentration and the conductive region being formed adjacent to the base corresponding with the region of higher reactant concentration.3. The bipolar junction transistor as recited in claim 1 , wherein the dielectric liner includes germanium oxide.4. The bipolar junction transistor as recited in claim 1 , wherein the dielectric liner includes a metal doped oxide.5. The bipolar junction transistor as recited in claim 4 , wherein the metal doped oxide includes a metal selected form the group consisting of Y claim 4 , Hf claim 4 , Al claim 4 , Sc claim 4 , La and combinations thereof.6. The bipolar junction transistor as recited in claim 1 , wherein the base includes germanium.7. The bipolar junction transistor as recited in claim 1 , wherein the conductive region formed adjacent to the ...

Finfet

FILM STRESS CONTROL FOR MEMORY DEVICE STACK

Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.

Boosted vertical field-effect transistor

Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.

INTEGRATED CIRCUIT (IC) WITH OFFSET GATE SIDEWALL CONTACTS AND METHOD OF MANUFACTURE

A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together. 1. An integrated circuit (IC) chip comprising: a plurality of FET pairs, each FET pair including a gate on a plurality of P-type fins and N-type fins,', 'a dielectric plug between the gates in selected FET pairs, said dielectric plug separating the PFET gate from the NFET gate in each selected FET pair, and', 'gate sidewall contacts stitching said respective pairs together, said gate sidewall contacts contacting a portion of cut ends of respective selected gate pairs to one side, said gate sidewall contacts each extending above a respective said dielectric plug offset to one side and through a contact dielectric layer;, 'one or more logic cells comprisinga wiring layer on said gate contact dielectric layer, wires in said wiring layer being oriented in a single direction and connecting to said gate sidewall contacts without jogging from said single direction; andat least one conductive via to a cell wire and directly above a gate sidewall contact.2. An IC chip as in claim 1 , wherein said gates are metal with nitride sidewalls at FET source/drain ends claim 1 , said plugs are nitride claim 1 , and said contact dielectric layer is oxide.3. An IC chip as in claim 2 , wherein said gate sidewall contacts are tungsten.4. An IC chip as in claim 3 , wherein said gate sidewall contacts have an ...

VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT

A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

CMOS NFET AND PFET COMPARABLE SPACER WIDTH

Embodiments of the present disclosure provide a structure including: a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate and source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate. 1. A structure comprising:a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate and source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate.2. The structure of claim 1 , further comprising:a first liner above and in direct contact with the pFET sidewall spacers and the pFET source drain region; anda second liner above and in direct contact with the nFET sidewall spacers and the NFET source drain region, such that substantially vertical portions of the first liner and the second liner are in direct contact with each other. The substantially vertical portion of the first liner and the substantially vertical portion of the second liner are located between the pFET device and the nFET device, and are in direct contact with one another.3. The structure of claim 1 , wherein a width or lateral thickness of the sidewall spacers of the pFET device are substantially equal to a width or lateral thickness of the sidewall spacers of the nFET device.4. The structure of wherein the first liner comprises silicon.5. The structure of claim 1 , wherein the first liner comprises a metal. The present invention generally relates to semiconductor manufacturing, and more particularly to complementary metal-oxide-semiconductor (CMOS) n-type field effect transistor (nFET) and p-type field effect ...

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Superfilled metal contact vias for semiconductor devices

In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

Vertical vacuum channel transistor with minimized air gap between tip and gate

A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

Removal of trilayer resist without damage to underlying structure

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof

An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Metallic boride and phosphide barrier layers for via linings

A material lining a via comprises either cobalt XY or nickel XY where X may be tungsten, tin or silicon, and Y is phosphorous or boron, in particular an embodiment disclosing cobalt tungsten phosphide is described. Multilayer linings including TaN are also envisaged. The layers are formed by an electroless plating method. The compounds when used to line a via opening act as a barrier to prevent material (eg copper) from wiring layers diffusing into the surrounding dielectric material.

FinFET with subset of sacrificial fins

A method of fabricating a FinFET 200 is disclosed which comprises the steps of forming a plurality of fins on a dielectric substrate. A gate layer (208, figure 2A) is deposited over the fins. In some embodiments the fin hardmask that is present on the tops of each fin is removed from some of the fins prior to the deposition of the gate layer. A gate hardmask (210) is then deposited over the gate layer. A portion of the gate hardmask layer and gate layer are then removed. In some embodiments this removal step also removes portions of the fins underneath. In other embodiments portions 202A, 202B, 202C of a subset of fins are removed with an etch. The portion of the etched sacrificial fins that remain are called finlets 220. These finlets remain under the gate of the FinFET. In some embodiments the remaining fins are subsequently merged together.

FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS

A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities. 1. A method for fabricating a field effect transistor device , the method comprising:patterning a fin on substrate;patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, wherein the gate stack includes a dielectric layer disposed over a channel region of the fin; a silicon material layer selected from the group consisting of amorphous silicon and polysilicon disposed over and in contact with the dielectric layer; a TaAN or TiAlN barrier layer disposed over and in contact with the silicon material layer; and a low resistivity metal layer formed of tungsten disposed over and in contact with the barrier layer, wherein the tungsten metal layer has a sheet resistivity of about 11 to about 15 ohm/square at a thickness of about 125 Angstroms;forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack;depositing a second insulator layer over portions of the fin and the protective barrier;performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the ...

FET trench dipole formation

A semiconductor structure includes a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors

A resistive processing unit includes an analog memory element coupled to a read row line and a read column line, a first current subtraction field-effect transistor (FET) coupled to the read row line and the analog memory element, and a second current subtraction FET coupled to the read column line and the analog memory element. The analog memory element is configured to store a weight value as its conductance. Application of a gate pulse voltage to one of the first current subtraction FET and the second current subtraction FET during application of a read pulse voltage to one of the read row line and the read column line reduces a measured conductance of the analog memory element, and the reduction of the measured conductance of the analog memory element provides net current for the stored weight value.

Minimize middle-of-line contact line shorts

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER

Forming stressed epitaxial layer using dummy gates

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

VERTICAL VACUUM CHANNEL TRANSISTOR WITH MINIMIZED AIR GAP BETWEEN TIP AND GATE

A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins. An emitter, a base and a collector contacts are formed to connect to the second semiconductor pattern ...

ILD GAP FILL FOR MEMORY DEVICE STACK ARRAY

A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material. 1. A semiconductor structure comprising:a memory device stack located on a surface of each electrically conductive structure of a plurality of electrically conductive structures that are embedded in an interconnect dielectric material layer and present in a memory device area, wherein each memory device stack includes a bottom electrode, a memory device pillar and a top electrode;a passivation dielectric material liner located laterally adjacent to each memory device stack and on a surface of the interconnect dielectric material layer; anda dual interlayer dielectric material structure located on the passivation dielectric material liner and entirely filling a gap between each memory device stack, wherein the dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.2. The semiconductor structure of claim 1 , wherein the first void free low-k ILD material is composed of a single ILD material having a low dielectric constant and an undulating top surface.3. The semiconductor structure of claim 1 , wherein the first void free low-k interlayer dielectric (ILD) material is composed of a void filling low-k dielectric material filling an entirety of each void present in a first ILD material having a low dielectric constant.4. The semiconductor structure of claim 3 , wherein the void filling low-k dielectric material is composed of a same low-k dielectric material as the first ILD material.5. The semiconductor structure of claim 1 , wherein the surface of the ...

Vertical fin-type bipolar junction transistor with self-aligned base contact

A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

FinFET with improved gate planarity

A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.

FinFET device with abrupt junctions

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

SALICIDE FORMATION ON REPLACEMENT METAL GATE FINFET DEVICES

A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.

Semiconductor device with trench epitaxy and contact

A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench.

BILAYER HDP CVD / PE CVD CAP IN ADVANCED BEOL INTERCONNECT STRUCTURES AND METHOD THEREOF

Techniques for enhancing vertical gate-all-around FET performance

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

Forming spacer for trench epitaxial structures

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Vertical fin type bipolar junction transistor (BJT) device with a self-aligned base contact

A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.

Spacer formation on semiconductor device

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

NANOSHEET ISOLATION FOR BULK CMOS NON-PLANAR DEVICES

A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure. 1. A method for semiconductor processing , comprising:removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure, a top layer of the trilayer structure in a second region of the semiconductor device being removed during the removal of the bottom layer in the first region; andafter removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.2. The method of claim 1 , further comprising removing claim 1 , prior to removing the middle and bottom layers in the first region claim 1 , the top layer from the first region to expose the middle layer in the first region.3. The method of claim 1 , further comprising removing the middle layer in the second region while the at least one first structure remains protected.4. The method of claim 1 , wherein the trilayer structure includes an organic layer claim 1 , inorganic layer and organic layer claim 1 , respectively claim 1 , for the top layer claim 1 , the middle layer and the bottom layer.5. The method of claim 1 , wherein the middle layer is resistant to etchants employed to etch the top layer and the bottom layer;6. The method of claim 1 , wherein filling the first region includes depositing a planarization layer including a same material as the bottom layer.7. The method of claim 1 , further ...

Electroplated copper interconnection structure, process for making and electroplating bath

Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 mum and via openings filled with electroplated copper than is substantially free of internal seams or voids.

FINFET MIT VERBESSERTER GATE-PLANARITÄT

Es wird ein FinFET mit verbesserter Gate-Planarität und ein Herstellungsverfahren offenbart. Die Gate-Zone ist vor dem Entfernen jeglicher unerwünschter Finnen auf einer Struktur von Finnen angeordnet. Es können lithographische Techniken oder Ätztechniken oder eine Kombination von beiden angewendet werden, um die unerwünschten Finnen zu entfernen. Alle oder einige der verbleibenden Finnen können vereinigt werden.

AIRGAP ISOLATION FOR BACKEND EMBEDDED MEMORY STACK PILLAR ARRAYS

A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES

A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate. 1. A method of making a semiconductor device , the method comprising:removing a first dummy gate of a plurality dummy gates to form a contact trench, the contact trench being arranged between an active gate and a second dummy gate of the plurality of dummy gates, the contact trench extending from a source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned between the second dummy gate and the contact trench and another portion of the source/drain positioned between the active gate and the contact trench, and the source/drain contacting a bottom sidewall of the contact trench; anddepositing a conductive material in contact trench to form a source/drain contact between the active gate and the second dummy gate.2. The method of claim 1 , wherein each dummy gate of the plurality of dummy gates comprises a sacrificial gate material.3. The method of claim 1 , wherein the active gate comprises a conductive gate stack.4. The method of claim 1 , wherein the source/drain comprises an epitaxially grown semiconductor material.5. The method of further comprising forming a silicide liner along the bottom sidewall of the contact trench and along a bottom endwall of the contact trench between the contact trench and the substrate.6. The method of claim 5 , wherein the silicide liner is also formed along an endwall of the trench.7. The method of claim 1 , wherein ...

Modified fin cut after epitaxial growth

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

VERTICAL TRANSPORT COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR WITH VARYING THRESHOLD VOLTAGES

Techniques regarding a vertical transport complementary metal-oxide-semiconductor with a plurality of fin field effect transistors with varying threshold voltages are provided. For example, one or more embodiments can regard an apparatus, which can comprise a semiconductor substrate. The apparatus can also comprise a first conducting channel comprising a first concentration of a first element. The first conducting channel can extend from the semiconductor substrate, and the first element can be germanium. The apparatus can further comprise a second conducting channel comprising a second concentration of the first element. The second conducting channel can extend from the semiconductor substrate, and the first concentration can be greater than the second concentration. Moreover, the apparatus can comprise a metal dielectric gate adjacent to the first conducting channel and the second conducting channel. 1. An apparatus , comprising:a semiconductor substrate;a first conducting channel comprising a first concentration of a first element, wherein the first conducting channel extends from the semiconductor substrate, and wherein the first element is germanium;a second conducting channel comprising a second concentration of the first element, wherein the second conducting channel extends from the semiconductor substrate, and wherein the first concentration is greater than the second concentration; anda metal dielectric gate adjacent to the first conducting channel and the second conducting channel, wherein the metal dielectric gate comprises a gate dielectric layer and a metal layer.2. The apparatus of claim 1 , further comprising:a third conducting channel extending from the semiconductor substrate, wherein the third conducting channel comprises a second element selected from a group consisting of periodic table group thirteen, periodic table group fourteen and periodic table group fifteen, and wherein the metal dielectric gate is further adjacent to the third conducting ...

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT

A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region. 1. A bipolar junction transistor , comprising:a base formed on a collector;an emitter formed on the base;a dielectric liner formed on vertical sidewalls of the collector, the base and the emitter and over the collector, wherein the dielectric liner includes germanium oxide; anda conductive region formed adjacent to the base within the dielectric liner.2. The bipolar junction transistor as recited in claim 1 , wherein the base includes a graded profile having a region of higher reactant concentration and the conductive region being formed adjacent to the base corresponding with the region of higher reactant concentration.3. The bipolar junction transistor as recited in claim 1 , wherein the base includes germanium.4. The bipolar junction transistor as recited in claim 1 , wherein the conductive region formed adjacent to the base includes a metal silicide or metal germanide.5. The bipolar junction transistor as recited in claim 1 , further comprising:a base contact formed along one of the vertical sidewalls to connect to the base through the conductive region, wherein the base contact is self-aligned to the conductive region along the liner on a vertical sidewall of the base.6. The bipolar junction transistor as recited in claim 1 , further comprising a collector contact landing on a first level of the collector.7. A bipolar junction transistor claim 1 , comprising:a base formed on a collector;an emitter formed on the base;a metal doped ...

MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE

A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. 1. A method of forming a semiconductor structure comprising:forming a replacement gate structure embedded within a planarization dielectric layer on a semiconductor substrate;removing said planarization dielectric layer to physically expose a semiconductor surface;forming a raised semiconductor structure by depositing a faceted semiconductor material on said physically exposed semiconductor surface to a height above a topmost surface of said replacement gate structure;depositing a first dielectric material over said replacement gate structure and said raised semiconductor structure;depositing a second dielectric material over said deposited first dielectric material; andrecessing a top surface of said raised semiconductor structure prior to, or after, depositing said second dielectric material.2. The method of claim 1 , wherein said top surface of said raised semiconductor structure is recessed prior to depositing said second dielectric material.3. The method of claim 2 , further comprising planarizing said first ...

METHOD FOR FORMING POROUS ORGANIC DIELECTRIC LAYER

PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure. SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned ...

VERFAHREN ZUR HERSTELLUNG EINES FINFET UND FINFETSTRUKTUR MIT VERBESSERTER GATE-PLANARITÄT

Es wird ein FinFET mit verbesserter Gate-Planarität und ein Herstellungsverfahren offenbart. Die Gate-Zone ist vor dem Entfernen jeglicher unerwünschter Finnen auf einer Struktur von Finnen angeordnet. Es können lithographische Techniken oder Ätztechniken oder eine Kombination von beiden angewendet werden, um die unerwünschten Finnen zu entfernen. Alle oder einige der verbleibenden Finnen können vereinigt werden.

Pe-ald of tan diffusion barrier re-gion on low-k materials

Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chlorides (TaCl5). The invention generates a sharp interface between low-k materials and the liner materials.

FinFET with epitaxial source and drain regions and dielectric isolated channel region

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

SPACER FOR DUAL EPI CMOS DEVICES

A method for making a semiconductor includes patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor, and etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process. 1. A method of making a semiconductor comprising:patterning a first transistor comprising two or more first gate stacks on a first source-drain area and second transistor comprising two or more second gate stacks on a second source-drain area;depositing a wet-etch resistant spacer material on the first and second transistors;removing the spacer from a first transistor fin region and a second transistor fin region with anisotropic spacer reactive ion etch;depositing a first nitride liner on the first and second transistors;depositing a dielectric layer on the first nitride layer;planarizing the dielectric layer;selectively removing the dielectric layer from between the spacer material in the first transistor fin region and the second transistor fin region;depositing a second nitride liner on the first and second transistors and selectively removing the second nitride liner from the first transistor;growing a first epitaxial layer on the first source-drain area by an epitaxial growth process;depositing a third nitride liner on the first and second ...

Techniques for Enhancing Vertical Gate-All-Around FET Performance

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques. 1. A method of forming a vertical field effect transistor (VFET) device , the method comprising the steps of:patterning at least one n-channel field-effect transistor (NFET) fin and at least one p-channel FET (PFET) fin in a substrate;forming NFET bottom source and drains at a base of the at least one NFET fin and PFET bottom source and drains at a base of the at least one PFET fins;forming bottom spacers on the NFET and PFET bottom source and drains;forming gates along sidewalls of the at least one NFET fin and along sidewalls of the at least one PFET fin;recessing the gates to expose top portions of the at least one NFET fin and the at least one PFET fin;forming an oxide layer along the sidewalls of the top portions of the at least one NFET fin and the at least one PFET fin;selectively forming a positively charged layer over the at least one NFET fin in contact with the oxide layer along the sidewalls of the top portions of the at least one NFET fin, wherein the positively charged layer induces a negative charge in the top portion of the at least one NFET fin forming a first dipole;selectively forming a negatively charged layer ...

Halbleiterstruktur und Prozess

Es wird eine Halbleiterstruktur bereitgestellt, die einen Halbleiterfinnenabschnitt mit einer Endwand umfasst, die sich von einem Substrat aufwärts erstreckt. Eine Gatestruktur überspannt einen Abschnitt des Halbleiterfinnenabschnitts. Ein erster Satz von Gateabstandshaltern ist auf gegenüberliegenden Seitenwandoberflächen der Gatestruktur positioniert und ein zweiter Satz von Gateabstandshaltern ist auf Seitenwänden des ersten Satzes von Gateabstandshaltern positioniert. Ein Gateabstandshalter des zweiten Satzes von Gateabstandshaltern hat einen unteren Abschnitt, der direkt mit der Endwand des Halbleiterfinnenabschnitts in Berührung steht.

EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. 1. A method of forming a contact silicide extension comprising: forming a liner layer on the gate spacer and the source-drain region;', 'forming the dielectric layer above the liner layer;', 'forming the contact trench in the dielectric layer to expose an upper surface of the liner layer; and', 'removing a portion of the liner layer directly beneath the dielectric layer., 'forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending laterally below the dielectric layer to a gate spacer formed on a sidewall of a gate stack wherein forming the undercut region below the dielectric layer and above the source-drain region comprises2. The method of claim 1 , wherein forming the liner layer comprises:forming the liner layer directly above a gate stack.3. The method of claim 1 , wherein removing the portion of the liner layer comprises:performing an isotropic wet etching process to remove the portion of the liner layer selective to the dielectric layer, the source-drain region, and the gate spacer.4. The method of claim 1 , wherein removing the portion of the liner layer comprises:performing an anisotropic etching process to remove a ...

SALICIDE FORMATION ON REPLACEMENT METAL GATE FINFET DEVICES

A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack. 1. A fin field effect transistor (finFET) device , comprising:a gate stack between sidewall spacers formed on a substrate, wherein an inside wall of each sidewall spacer contacts the gate stack and the gate stack comprises a gate metal;an epitaxially grown raised source drain (RSD) on the substrate, wherein the RSD is adjacent to outer walls of the sidewall spacers and the outside wall of each sidewall spacer is on an opposite side of the respective inside wall of the sidewall spacer;a silicide on a surface of the RSD and along a surface of the outer walls of the sidewall spacers above the RSD; anda contact metal above a portion of the gate stack and the RSD, wherein the contact metal contacts the silicide along the outside walls of the sidewall spacers adjacent to the portion of the gate stack.2. The device according to claim 1 , wherein the contact metal contacts the silicide on the surface of the portions of the RSD in an nFET region.3. The device according to claim 1 , further comprising a nickel platinum (NiPt) layer on the silicide above the portions of the gate stack and the RSD.4. The device according to claim 3 , wherein the contact metal contacts the NiPt layer above the portions of the gate stack and the RSD in a pFET region.5. The device according to claim 1 , wherein the silicide is ...

Salicide formation on replacement metal gate finFet devices

A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.

Method And Structure For Forming MRAM Device

A method of forming a bottom electrode for MRAM comprises: depositing a conductive material into a trench in a substrate and planarizing; depositing a selective cap on the conductive material; depositing a layer of high stress material on upper surfaces of the substrate and the cap; patterning the high stress material to remove the layer of high stress material on the upper surfaces of the substrate and leaving the layer of high stress material on the upper surfaces of the cap; depositing a layer of dielectric material on the upper surfaces of the substrate and on upper surfaces of the high stress material on the cap; planarizing the layer of dielectric material; and forming a magnetic tunnel junction stack on the dielectric material over the conductive material.

MTJ stack etch using IBE to achieve vertical profile

Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).

GATE CHANNEL LENGTH CONTROL IN VFET

A semiconductor structure is provided utilizing a cost effective method in which the vertical gate channel length is substantially the same for vertical field effect transistors (VFETs) that are present in a dense device region and an isolated device region. The VFETs have improved uniformity, device functionality and better yield. No additional lithographic process is used in making such a semiconductor structure.

Superfilled metal contact vias for semiconductor devices

Removal of work function metal wing to improve device yield in vertical FETs

A vertical transistor that includes a gate structure containing a work function metal liner that is wing-free is provided. The wing-free work function metal liner is provided by recessing a sacrificial material layer portion that is located adjacent to a work function metal liner having a winged surface near the channel and fin ends. The recessed sacrificial material layer portion allows for multi-directional etching of the winged surface of the work function metal liner and thus the wing surface can be removed forming a wing-free work function metal liner. The vertical transistor of the present application has reduced parasitic capacitance and a reduced tendency of electrical shorting between a top source/drain structure and the gate structure. The method of the present application can improve device yield.

Method and structure of improving contact resistance for passive and long channel devices

A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.

SPACER FOR TRENCH EPITAXIAL STRUCTURES

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material. 1. A structure , comprising:a plurality of first-type gate structures;a plurality of second-type gate structures; anda low-k dielectric spacer material surrounding separately the plurality of first-type gate structures and the plurality of second-type gate structures and which defined therebetween are a plurality of trenches for source and drain regions of the plurality of first-type gate structures and the plurality of second-type gate structures.2. The structure of claim 1 , wherein the low-k dielectric spacer material is a nitride or oxide material.3. The structure of claim 1 , wherein the first-type gate structures are p-type finFET devices and the second-type gate structures are n-type finFET devices.4. The structure of claim 1 , further comprising a first capping layer of a first capping material formed on the plurality of first-type gate structures and the plurality of second-type gate structures.5. The structure of claim 4 , further comprising a second capping layer of a second capping material formed on a spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over the first capping layer.6. A structure claim 4 , comprising:first-type gate structures and second-type gate structures;a capping layer on the first-type gate structures and the second-type gate structures;a first spacer material formed on sidewalls of the first-type gate structures and second-type gate structures and over the capping layer;a ...

Spacer for trench epitaxial structures

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Salicide formation on replacement metal gate finFET devices

A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.

Structure and process to tuck fin tips self-aligned to gates

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure and a second gate structure formed over a fin structure;raised source and drain regions formed adjacent to the first gate structure; andraised source and drain regions formed adjacent to the second gate structure,wherein side surfaces of the raised source and drain regions of the first gate structure contact a first liner material covering a portion of the first gate structure, which first liner material extends to an upper surface of the fin structure,wherein the side surfaces of the raised source and drain regions of the first gate structure are separated from a first spacer material formed on the first gate structure by the first liner material covering the portion of the first gate structure, andwherein side surfaces of the raised source and drain regions of the second gate structure contact a side surface of a second liner material covering a portion of the second gate structure and a side surface of a second spacer material formed on the second gate structure which is not covered by the second liner material.2. The structure of claim 1 , wherein the first gate structure is a gate structure of an N-type FET (NFET) and the second gate structure is a gate structure of a P-type FET (PFET).3. The structure of claim 2 , wherein:the first liner material and first spacer material formed on the first gate structure form a first sidewall spacer on a side surface of the first ...

Nanosheet isolation for bulk CMOS non-planar devices

A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

Minimize middle-of-line contact line shorts

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Spacer formation on semiconductor device

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

PLANAR GATE-INSULATED VACUUM CHANNEL TRANSISTOR

A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES

In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.

FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Vertical transport fin field effect transistor with asymmetric channel profile

A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

FINFET WITH IMPROVED GATE PLANARITY

A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged. 1. A method of fabricating a FinFET , comprising:forming a pattern of fins, wherein each fin comprises a fin hardmask layer disposed thereon;depositing a gate layer over the pattern of fins;depositing a gate hardmask layer over the gate layer;removing a portion of the gate hardmask layer and the gate layer, thereby exposing the pattern of fins;depositing an etch-resistant layer over a first subset of fins from the pattern of fins;removing a second subset of the fins from the pattern of fins with an etch; andmerging at least some of the first subset of fins.2. The method of claim 1 , wherein depositing an etch-resistant layer over a first subset of the fins comprises depositing a layer comprising carbon.3. The method of claim 1 , wherein depositing an etch-resistant layer over a first subset of the fins comprises depositing a layer comprising photoresist.4. The method of claim 1 , wherein forming a pattern of fins comprises forming a pattern of fins with a pitch ranging from about 20 nanometers to about 60 nanometers.5. The method of claim 1 , wherein removing a second subset of the fins further includes a wet etch.6. The method of claim 1 , wherein removing a second subset of the fins further includes a dry etch.7. The method of claim 1 , wherein forming a pattern of fins further includes depositing a hardmask comprised of a material selected from the group consisting of: silicon oxide claim 1 , silicon nitride claim 1 , silicon carbide claim 1 , TiN claim 1 , TaN claim 1 , and amorphous carbon.8. The method of claim 1 , wherein forming a pattern of fins further includes depositing a conformal film of a material selected from the group consisting of: ...

Superfilled metal contact vias for semiconductor devices

In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION

A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals. 1. A method for fabricating a field effect transistor comprising:selecting a Si containing substrate having a source, drain and channel regions exposed through openings in a dielectric layer, said openings to said channel region having sidewall spacers;forming a dielectric layer on said channel region;forming a metal gate layer over said dielectric layer;forming a metal silicide in said source and drain regions;forming a first metal liner layer over said metal silicide in said source and drain regions and over said metal gate layer and over the sidewalls of said openings in said dielectric layer;forming a second metal layer over said first metal liner layer having a thickness to fill said openings; andplanarizing said first metal layer and said second metal layer down to said dielectric layer.2. The method of wherein said forming a first metal liner layer includes forming a layer selected from the group consisting of tantalum claim 1 , titanium claim 1 , titanium nitride claim 1 , tantalum nitride claim 1 , titanium silicon nitride claim 1 , ruthenium claim 1 , ruthenium oxide claim 1 , ruthenium phosphorus claim 1 , hafnium claim 1 , zirconium claim 1 , aluminum claim 1 , manganese claim 1 , copper manganese claim 1 , iridium claim 1 , copper iridium claim 1 , cobalt claim 1 , cobalt tungsten claim 1 , cobalt tungsten phosphorus claim 1 , tungsten claim 1 , lanthanum claim 1 , lutetium claim 1 , transition metal elements claim 1 , rare earth elements claim 1 , a metal carbide claim 1 , a conductive metal oxide and combinations thereof.3. The method of wherein said forming a second metal layer includes forming a layer selected from the group consisting of copper claim 1 , ruthenium claim 1 , palladium claim 1 , platinum claim 1 , cobalt claim 1 , nickel claim 1 , ruthenium ...

Semiconductor plural gate lengths

Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask. 1. A method , comprising:forming a first gate structure with a first critical dimension, using a pattern of a mask; andforming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.2. The method of claim 1 , wherein the first gate structure comprises a first material and the second gate structure comprises a second material.3. The method of claim 2 , wherein the first material is amorphous silicon and the second material is polysilicon claim 2 , which have different etch rates.4. The method of claim 3 , wherein the first critical dimension is smaller than the second critical dimension due to different etch rates of the first material and the second material.5. The method of claim 4 , wherein the first critical dimension and the second critical dimension are gate lengths.6. The method of claim 1 , wherein the forming of the first gate structure and the second gate structure comprise:forming a first material on a substrate;blocking a first section of the first material on the substrate with a blocking material;subjecting an unmasked portion of the first material of a second section to a fabrication process to convert the first material to a second material, which has a different etch rate than the first material;forming a hardmask over the first material and the second material; andpatterning the hardmask and underlying first material and second material, by subjecting the hardmask, the first material and the second material to a same etching process.7. The method of claim 6 ...

VERTICAL CMOS DEVICES WITH COMMON GATE STACKS

A semiconductor structure includes a first nanowire of a first material formed on a substrate, at least a second nanowire of a second material different than the first material formed on the substrate and a common gate stack surrounding the first nanowire and the second nanowire. The first nanowire and the second nanowire are vertical with respect to a horizontal plane of the substrate. The first material may be indium gallium arsenide (InGaAs) and the first nanowire may form part of an NFET channel of a CMOS device, while the second material may be germanium (Ge) and the second nanowire may form part of a PFET channel of the CMOS device. 1. A semiconductor structure , comprising:a first nanowire of a first material formed on a substrate;at least a second nanowire of a second material different than the first material formed on the substrate; anda common gate stack surrounding the first nanowire and the second nanowire;wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the substrate.2. The semiconductor structure of claim 1 , wherein the first material comprises a group III-V material and the second material comprises a group II-IV material.3. The semiconductor structure of claim 1 , wherein the first material comprises indium gallium arsenide (InGaAs) and the first nanowire forms at least a portion of a negative field-effect transistor (NFET) channel of a complementary metal-oxide-semiconductor (CMOS) device claim 1 , and the second material comprises germanium (Ge) and the second nanowire forms at least a portion of a positive field-effect transistor (PFET) channel of the CMOS device.4. The semiconductor structure of claim 1 , wherein the first nanowire comprises a first dummy channel surrounded by the first material and the second nanowire comprises a second dummy channel surrounded by the second material claim 1 , the first dummy channel and the second dummy channel comprising a third material different than the ...

NANOWIRE FET INCLUDING NANOWIRE CHANNEL SPACERS

A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack. 1. A method of forming nanowire channel spacers in a nanowire field effect transistor (FET) , the method comprising:forming a multi-stack semiconductor fin on an upper surface of a semiconductor substrate, the multi-stack semiconductor fin comprising a plurality of vertically stacked semiconductor material layers including plurality of nanowire channel layers, each nanowire channel layer vertically separated from one another by a sacrificial layer;forming a gate stack on the upper surface of the semiconductor substrate, the gate stack wrapping around the outer surfaces of the multi-stack semiconductor fin;forming source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions contacting the multi-stack fin and being separated from the gate stack by a void that exposes portions of the sacrificial layers and the nanowire channel layers;etching the exposed portions of the sacrificial layers to form cavities that release opposing ends of the nanowire channel layers and form stacked nanowire channels; andfiling the cavities with a spacer material that encapsulates the released ends and forms the nanowire channel spacers.2. The method of claim 1 , wherein the nanowire channel spacers are interposed between the source/drain regions and the gate stack.3. The ...

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

FinFET DEVICE WITH ABRUPT JUNCTIONS

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE

A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. 1. A semiconductor structure comprising:a field effect transistor including a raised source region and a raised drain region and located on a substrate;a gate level dielectric layer comprising a first dielectric material and overlying a gate electrode of said field effect transistor;a contact level dielectric layer comprising a second dielectric material and overlying said gate level dielectric layer; anda contact via structure electrically shorted to one of said raised source region and raised drain region and extending through said contact level dielectric layer and said gate level dielectric layer as a single contiguous structure, wherein a lower portion of said contact via structure embedded within said gate level dielectric layer is narrower than an upper portion of said contact via structure embedded within said contact level dielectric layer along a horizontal direction parallel to a direction of a channel of said field effect transistor.2. The semiconductor structure of claim 1 , wherein said lower portion ...

EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. 1. A method of forming a contact silicide extension comprising:forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; andforming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.2. The method of claim 1 , wherein the forming the undercut region below the dielectric layer and above the source-drain region comprises:forming a liner layer on the gate spacer, and the source-drain region;forming the dielectric layer on the liner layer and the gate stack;forming the contact trench in the dielectric layer, the bottom of the contact trench exposing a portion of the liner layer; andremoving a portion of the liner layer, the portion of the liner layer extending from directly below the bottom of the contact trench and below the dielectric layer to the gate spacer.3. The method of claim 2 , wherein the removing the portion of the liner layer comprises:performing an isotropic wet etching process to remove the portion of the liner layer selective to the dielectric layer, the source-drain region, ...

HETEROJUNCTION BIPOLAR TRANSISTOR WITH A SILICON OXIDE LAYER ON A SILICON GERMANIUM BASE

A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant. 17-. (canceled)8. A heterojunction bipolar transistor comprising:a base epitaxially grown on a collector;an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin; andan epitaxy layer epitaxially grown on sidewalls of the fin, the epitaxy layer is made of silicon.9. The heterojunction bipolar transistor of claim 8 , wherein the epitaxy layer is formed into a silicon oxide layer.10. The heterojunction bipolar transistor of claim 8 , wherein the base is made of silicon germanium.11. The heterojunction bipolar transistor of claim 8 , wherein the emitter and the collector are made of silicon.12. The heterojunction bipolar transistor of claim 8 , wherein the base is doped with a p-type dopant.13. The heterojunction bipolar transistor of claim 8 , wherein the emitter and the collector are doped with a n-type dopant.14. A method of forming a heterojunction bipolar transistor claim 8 , the method comprising:epitaxially growing a base on a collector;epitaxially growing an emitter on the base, the emitter and the base being patterned into a fin; andepitaxially growing an epitaxy layer on sidewalls of the fin, the epitaxy layer is made of silicon.15. The method of ...

METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES

A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate. 1forming a plurality of dummy gates comprising a sacrificial material on a substrate;forming an active gate comprising a conductive gate stack on the substrate adjacent to the plurality of dummy gates;removing at least one dummy gate of the plurality dummy gates to form a contact trench, the contact trench being arranged between the active gate and a dummy gate of the plurality of dummy gates, the contact trench extending from a source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned between the dummy gate and the contact trench and another portion of the source/drain positioned between the active gate and the contact trench, and the source/drain contacting a bottom sidewall of the contact trench;forming a silicide liner along the bottom sidewall of the contact trench and along a bottom endwall of the contract trench between the contact trench and the substrate; anddepositing a conductive material in contact trench to form a source/drain contact between the active gate and the dummy gate.. A method of making a semiconductor device, the method comprising: This application is a continuation of and claims priority from U.S. patent application Ser. No. 14/968,063, filed on Dec. 14, 2015, entitled “METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES,” the entire contents of which are incorporated herein by ...

METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS

A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask. 1. A method , comprising:forming a layer of material above a semiconductor substrate;performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above said layer of material, wherein said first plurality of spacers are positioned above a first region of said semiconductor substrate and said second plurality of spacers are positioned above a second region of said semiconductor substrate, said first and second pluralities of spacers having a same initial width and a same pitch spacing;forming a masking layer above said layer of material, said masking layer covering said first plurality of spacers and exposing said second plurality of spacers; andperforming a first etching process through said masking layer on said exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than said initial width, wherein said first plurality of spacers and said plurality of reduced-width spacers define an etch mask.2. The method of claim 1 , wherein said layer of material is a layer of hard mask ...

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. 1. A method of forming a semiconductor structure , the method comprising:forming a gate structure straddling a semiconductor fin;forming a dielectric material over the semiconductor fin and on sidewall surfaces of the gate structure;forming a patterned material stack over the dielectric material, the patterned material stack having an opening that exposes one side of the gate structure;cutting the semiconductor fin utilizing the patterned material stack and a portion of the dielectric material within the opening as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall; andforming outer gate spacers, wherein one of the outer gate spacers contains a lower sidewall portion that directly contacts the entirety of the exposed end wall of the semiconductor fin portion.2. The method of claim 1 , wherein a portion of the opening exposes a portion of the dielectric material over the semiconductor fin.3. The method of claim 2 , wherein the cutting the semiconductor fin includes etching the exposed portion of the dielectric material over the semiconductor fin to expose a topmost surface of the gate structure and to provide inner gate spacers.4. The method of claim 3 , wherein each of the inner gate spacers straddles over the surface of the semiconductor fin portion claim 3 , and wherein one of the inner gate spacers located in the opening has an outer edge that is vertically aligned to the end wall ...

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. 1. A method of forming a semiconductor structure , the method comprising:forming a gate structure straddling a portion of a semiconductor fin,providing a first set of gate spacers on opposing sidewalls of the gate structure and straddling another portion of the semiconductor fin;forming a sacrificial dielectric liner over the first set of gate spacers and the gate structure and straddling a remaining portion of the semiconductor fin;forming a patterned material stack having an opening;cutting the semiconductor fin utilizing the patterned material stack, a portion of sacrificial dielectric liner within the opening and one gate spacer of the first set of gate spacers as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall;performing a lateral etch to pull back the expose end wall of the semiconductor fin portion underneath or aligned to a sidewall of the one gate spacer of the first set of gate spacers within the opening; andforming a second set of gate spacers, wherein one gate spacer of the second set of gate spacers contains a lower portion that directly contacts the exposed end wall of the semiconductor fin portion.2. The method of claim 1 , wherein a portion of the opening exposes a portion of the sacrificial dielectric liner over the semiconductor fin.3. The method of claim 2 , wherein prior to cutting the semiconductor fin claim 2 , an etch is performed to remove the exposed ...

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A method , comprising:forming a first gate stack and a second gate stack over a fin structure;forming a spacer material over the first gate stack and the second gate stack;forming source and drain regions abutting the spacer material of the first gate stack;forming a sidewall spacer for the first gate stack by depositing a liner material over the spacer material on sidewalls of the first gate stack, wherein the liner material of the first gate stack extends to an upper surface of the fin structure; andforming a sidewall spacer for the second gate stack by depositing the liner material over the spacer material on sidewalls of the second gate stack, wherein a portion of the spacer material formed over the second gate stack is not covered by the liner material, and wherein the liner material of the second gate stack is separated from the upper surface of the fin structure by the portion of the spacer material formed over the second gate stack which is not covered by the liner material.2. The method of claim 1 , wherein the first gate stack is a PFET and the second gate stack is an NFET.3. The method of claim 1 , further comprising forming source and drain regions adjacent the second gate stack.4. The method of claim 3 , further comprising forming a space between the source and drain regions and the spacer material of the first gate stack by thinning the spacer material on sidewalls of the first gate stack and the second gate ...

SPACER FORMATION ON SEMICONDUCTOR DEVICE

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack. 1. A semiconductor device comprising:a semiconductor fin arranged on a substrate;a first gate stack arranged over a first channel region of the fin;a second gate stack arranged over a second channel region of the fin;a first spacer having a first thickness arranged adjacent to the first gate stack;a second spacer having the first thickness arranged adjacent to the second gate stack;a first source/drain region arranged on the fin adjacent to the first spacer; anda second source/drain region arranged on the fin adjacent to the second spacer.2. The device of claim 1 , further comprising a layer of nitride material arranged on the substrate between the first source/drain region and the second source/drain region.3. The device of claim 1 , wherein the first source/drain region includes a crystalline semiconductor material. This application is a division of U.S. application Ser. No. 15/229,665 filed Aug. 5, 2016, which is a continuation of U.S. Pat. No. 9,443,855 issued Sep. 13, 2016, the disclosures of both of which are incorporated herein by reference in their entirety.The present invention relates to semiconductor devices, ...

Removal of semiconductor growth defects

After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure and a second gate structure formed over a fin structure,a liner material covering a portion of the first gate structure and extending to an upper surface of the fin structure; anda liner material covering a portion of the second gate structure,wherein the liner material covering a portion of the second gate structure is separated from the upper surface of the fin structure by a portion of a spacer material formed over the second gate structure which is not covered by the liner material.2. The structure of claim 1 , wherein a space between source and drain regions of the first gate structure and a spacer material of the first gate structure comprises thinned spacer material on sidewalls of the first gate structure.3. The structure of claim 2 , wherein the liner material of the first gate structure extends into the space between the source and drain regions and the spacer material of the first gate structure to contact the upper surface of the fin structure.4. The structure of claim 3 , wherein the liner material of the first gate structure has a lower dielectric constant than a dielectric constant of the spacer material of the first gate structure.5. The structure of claim 4 , wherein the first gate structure and the second gate structure each include a dielectric layer formed in contact with an upper surface of the fin structure and in contact with inner walls of the spacer ...

Nanosheet isolation for bulk cmos non-planar devices

A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure comprising a sidewall spacer abutting raised source and drain regions; anda second gate structure comprising a sidewall spacer abutting raised source and drain regions, wherein:the sidewall spacer of the first gate structure has a same thickness as the sidewall spacer of the second gate structure; andthe sidewall spacer of the first gate structure and the sidewall spacer of the second gate structure comprise a combination of a spacer material and a liner material.2. The structure of claim 1 , wherein the sidewall spacer of the first gate structure and the sidewall spacer of the second gate structure comprise the liner material over spacer material on sidewalls of the first gate stack and the second gate stack.3. The structure of claim 2 , wherein a space between source and drain regions and the spacer material of the first gate structure comprises thinned spacer material on sidewalls of the first gate structure and the second gate structure.4. The structure of claim 3 , wherein the space has a width dependent on a thickness of the liner material.5. The structure of claim 4 , wherein the spacer material is a thickness of about 3 nm to 15 nm and the liner material is a thickness of about 1 nm to 5 nm.6. The structure of claim 5 , further comprising source and drain regions for the first gate stack and the second gate stack claim 5 , the source and drain regions of the second ...

BOOSTED VERTICAL FIELD-EFFECT TRANSISTOR

Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins. 1. A logic device , comprising:a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer, wherein a bottom source/drain contact is between a first surface of the logic device and the first epitaxial layer, and a top source/drain contact is between the first surface and the second epitaxial layer; anda boosted bipolar junction transistor, wherein a bipolar junction transistor contact is between the first surface and the second epitaxial layer.2. The logic device of claim 1 , wherein the vertical field effect transistor is an n-channel field effect transistor.3. The logic device of claim 1 , wherein the vertical field effect transistor is a p-channel field effect transistor.4. The logic device of claim 1 , wherein the bipolar junction transistor contact provides a boosted voltage level for the logic device.5. The logic device of claim 1 , further comprising a self-aligned gate on the logic device and a gate contact between the first surface of the logic device and the self-aligned gate.6. The logic device of claim 1 , further comprising a spacer adjacent the second ...

FinFET DEVICE WITH ABRUPT JUNCTIONS

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers. 1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;providing a dielectric spacer on vertical sidewalls of each gate structure;removing portions of each semiconductor fin and a portion of said insulator layer utilizing each dielectric spacer and each gate structure as an etch mask, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; anddiffusing a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along said one exposed ...

NANOWIRE FET INCLUDING NANOWIRE CHANNEL SPACERS

A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack. 1. A stacked nanowire field effect transistor (FET) comprising:a plurality of vertically stacked nanowire channels, each nanowire channel vertically separated from one another by sacrificial segment;a gate stack on the upper surface of the semiconductor substrate, the gate stack including a conductive element that wraps around the nanowire channels;source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions directly contacting ends of the nanowire channel; andnanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.2. The stacked nanowire FET of claim 1 , wherein the nanowire channel spacers encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.3. The stacked nanowire FET of claim 2 , wherein the ends include a first end that extends beneath the gate stack and an opposing second end that contacts inner sidewalls of the source/drain regions.4. The stacked nanowire FET of claim 3 , wherein the second end stops at the inner sidewalls without extending into the source/drain regions claim 3 ,5. The stacked nanowire FET of claim 4 , wherein the nanowire channel spacers include intermediate nanowire channel ...

METHOD AND STRUCTURE TO FORM VERTICAL FIN BJT WITH GRADED SIGE BASE DOPING

A device including a vertical fin bipolar junction transistor (BJT) with graded doping SiGe base with molecular layer doping (MLD), where a lower doped base is grown and a top emitter is formed and then additional late doping is provided on an Si layer on a side of the emitter and a method of manufacture thereof. 1. A device comprising:a vertical fin bipolar junction transistor (BJT) with a graded doping SiGe base with molecular layer doping (MLD), a lower-doped base is grown as the graded doping SiGe base having a low doping characteristic at an upper portion of the lower-doped base and a high doping characteristic at a lower portion of the lower-doped base;', 'a top emitter including Si is formed on the top portion of the lower-doped base; and', 'the low doping characteristic at the upper portion of the lower-doped base is changed to a high doping characteristic via the MLD such that the too emitter and the upper portion and the lower portion of the lower-doped base include the high doping characteristic., 'wherein2. The device of claim 1 , wherein the fin BJT includes:a base contact formed of a metal deposited between an oxide and a spacer on the SiGe base; anda collector contact formed of the metal deposited between the oxide and the spacer on an Si (N type) layer and an Si (N++ type) layer of a substrate.3. The device of claim 1 ,wherein a pitch of the vertical fin bipolar junction transistor (BJT) is approximately 5 nm.4. A method of manufacturing a vertical fin bipolar junction transistor (BJT) claim 1 , the method comprising:selectively removing an oxide from a recess between fins at a top portion of an SiGe layer;performing doping around an Si layer and the recess around the SiGe layer; anddrive in annealing to make the SiGe layer highly doped at the top portion of the SiGe layer and the Si layer.5. The method of claim 4 , further comprising:prior to the selectively removing, depositing the oxide in the recess of the fins of the fin BJT up to a top surface ...

Uniform Voltage Drop in Arrays of Memory Devices

Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided. 1. A phase change memory (PCM) device , comprising:at least one PCM cell comprising a phase change material disposed on a heater; andat least one resistor in series with the at least one PCM cell, wherein the at least one resistor comprises a same combination of materials as the heater.2. The PCM device of claim 1 , wherein the same combination of materials alternates between layers of a first material and a second material.3. The PCM device of claim 2 , wherein the first material is selected from the group consisting of: tantalum nitride (TaN) and silicon nitride (SiN) claim 2 , and wherein the second material comprises titanium nitride (TiN).4. The PCM device of claim 1 , wherein a top surface of the heater is coplanar with a top surface of the at least one resistor.5. The PCM device of claim 1 , wherein the phase change material comprises a chalcogenide alloy.6. The PCM device of claim 5 , wherein the chalcogenide alloy comprises tellurium (Te) in combination with an element selected from the group consisting of: antimony (Sb) claim 5 , germanium (Ge) claim 5 , and combinations thereof.7. The PCM device of claim 1 , wherein the at least one PCM cell further comprises:a bottom electrode on which the heater is disposed; anda top electrode disposed on the phase change material.8. The PCM device of claim 1 , further comprising:an encapsulation layer disposed on the at least one PCM cell and along sidewalls of the phase change material, and on the ...

SPACER FOR TRENCH EPITAXIAL STRUCTURES

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material. 1. A method , comprising:forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures;growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; andgrowing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.2. The method of claim 1 , wherein the spacer material is a low-k dielectric material which defines trench structures for the source and drain material for the first-type gate structures and the second-type gate structures.3. The method of claim 2 , wherein the spacer material is nitride or oxide material.4. The method of claim 1 , wherein the growing source and drain material about the first-type gate structures and the second-type gate structures is an epitaxial growth process.5. The method of claim 4 , wherein the growing source and drain material about the first-type gate structures is formed while blocking growth of material about the second-type gate structures.6. The method of claim 5 , further comprising etching blocking material over the first-type gate structures to expose source and drain regions associated with the first-type gate structures claim 5 , while protecting source and drain regions of the second-type gate structures.7. The method of claim 6 , wherein the first-type gate structures is p-type devices and the second-type gate ...

FORMING STRESSED EPITAXIAL LAYER USING DUMMY GATES

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures. 1. A method comprising:forming a doped silicon layer over a substrate;forming a plurality of fin structures from the doped silicon layer;forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch;forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures;removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; andforming an epitaxial region over the plurality of fin structures and the substrate between the two of the remaining gate structures.2. The method of claim 1 , further comprising forming a plurality of epitaxial regions over the plurality of fin structures and the substrate between the plurality of gate structures separated by the first pitch.3. The method of claim 2 , wherein the epitaxial region between the two of the remaining gate structures has a greater stress level than the epitaxial regions between the plurality of gate ...

RESISTIVE SWITCHING DEVICE HAVING CONTROLLED FILAMENT FORMATION

Embodiments of the invention are directed to an integrated circuit structure that includes a resistive switching device (RSD). The RSD includes a bottom electrode, an insulator region, and a top electrode. The insulator region includes a filament region and is communicatively coupled to the bottom electrode. The top electrode is communicatively coupled to the insulator region. The filament region includes an apex region having a first apex region sidewall and a second apex region sidewall that intersects the first apex region sidewall at an angle that is less than about 90 degrees. 1. An integrated circuit structure comprising: a bottom conductive electrode;', 'an insulator region communicatively coupled to the bottom conductive electrode, wherein the insulator region comprises a filament region; and', 'a top conductive electrode communicatively coupled to the insulator region;, 'a resistive switching device (RSD) comprisingwherein the filament region comprises an apex region comprising a first apex region sidewall and a second apex region sidewall; andwherein the second apex region sidewall intersects the first apex region sidewall at an angle that is less than about 90 degrees.2. The structure of claim 1 , wherein the first apex region sidewall is substantially planar and the second apex region sidewall is substantially planar.3. The structure of claim 1 , wherein the first apex region sidewall is substantially non-planar and the second apex region sidewall is substantially non-planar.4. The structure of claim 1 , wherein the RSD is configured to claim 1 , based on a voltage applied across the bottom conductive electrode and the top conductive electrode claim 1 , form filaments in the filament region.5. The structure of claim 4 , wherein more than one half of the filaments formed in the filament region are formed in the apex region.6. The structure of claim 1 , wherein the filament region comprises a metal oxide.7. The structure of claim 6 , wherein the metal ...

NON VOLATILE RESISTIVE MEMORY LOGIC DEVICE

A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells. 1. A resistance switching random access memory (RAM) NAND device comprising:a first resistance switching RAM cell and a first input node electrically connected to the first resistance switching RAM cell;a second resistance switching RAM cell and a second input node electrically connected to the second resistance switching RAM cell; anda shared output node electrically connected to both the first resistance switching RAM cell and to the second resistance switching RAM cell.2. The resistance switching RAM NAND device of claim 1 , wherein when both the first resistance switching RAM cell and the second resistance switching RAM cell is in a high resistance state (HRS) claim 1 , a logical high ‘1’ is present on the shared output node.3. The resistance switching RAM NAND device of claim 1 , wherein when only one of the first resistance switching RAM cell or the second resistance switching RAM cell is in a high resistance state (HRS) and the other of the first resistance switching RAM cell or the second resistance switching RAM cell is in a low resistance state (LRS) claim 1 , a logical high ‘1’ is present on the shared output node.4. The resistance switching RAM NAND device of claim 1 , wherein when both the first resistance switching RAM cell and the second resistance switching RAM cell is in a low resistance state (LRS) claim 1 , a logical low ‘0’ is present on the shared output node.5. The resistance switching RAM NAND device of claim 2 , wherein a low current sum is sensed at ...

SPACER FORMATION PREVENTING GATE BENDING

A method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates. The method further includes removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers including a first portion proximate the top surface of the substrate having a first width and a second portion above the first portion with a second width smaller than the first width. 1. A method of forming a fin field-effect transistor (finFET) structure , comprising:depositing a spacer material over a top surface of a fin substrate and two or more spaced-apart gates formed on the top surface of the fin substrate;depositing a sacrificial liner over the spacer material;etching the sacrificial liner and the spacer material to expose portions of the top surface of the fin substrate between the two or more spaced-apart gates;removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers comprising a first portion proximate the top surface of the fin substrate having a first width and a second portion above the first portion with a second width smaller than the first width; andfurther comprising growing epitaxial layers in a first region of the finFET structure over the top surface of the fin substrate between at least two adjoining spacers surrounding at least one adjoining pair of the spaced-apart gates, each of the epitaxial layers having a substantially uniform height relative to the top surface of the fin substrate.2. The method of claim 1 , wherein a first ...

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure comprising a sidewall spacer abutting raised source and drain regions; anda second gate structure comprising a sidewall spacer abutting raised source and drain regions, wherein:the sidewall spacer of the first gate structure and the sidewall spacer of the second gate structure each comprise a combination of a spacer material and a liner material formed over the spacer material;a portion of the spacer material formed on the sidewall of the second gate structure is devoid of the liner material; andthe raised source and drain regions abutting the second gate structure directly abut sidewalls of the liner material of the second gate structure and the portion of the spacer material formed on the sidewall of the second gate structure which is devoid of the liner material.2. The structure of claim 1 , wherein a space between the source and drain regions and the spacer material of the first gate structure comprises thinned spacer material on sidewalls of the first gate structure and the second gate structure.3. The structure of claim 2 , wherein the space has a width dependent on a thickness of the liner material.4. The structure of claim 3 , wherein the spacer material is a thickness of about 3 nm to 15 nm and the liner material is a thickness of about 1 nm to 5 nm.5. The structure of claim 4 , wherein the raised source and drain regions of the first gate structure and the second ...

VERTICAL FIN TYPE BIPOLAR JUNCTION TRANSISTOR (BJT) DEVICE WITH A SELF-ALIGNED BASE CONTACT

A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion. 1. A method of forming a silicon-germanium heterojunction bipolar transistor (HBT) device , comprising:forming a stack of four doped semiconductor layers on a semiconductor substrate;forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers;removing portions of the second, third, and fourth semiconductor layers to form a vertical fin;recessing the second doped semiconductor layer and fourth doped semiconductor layer;depositing a condensation layer on the exposed surfaces of the second doped semiconductor layer, third doped semiconductor layer, and fourth doped semiconductor layer; andreacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion of the third doped semiconductor layer.2. The method of claim 1 , wherein the material of the first doped semiconductor layer is silicon claim 1 , the material of the second doped semiconductor layer is silicon claim 1 , the material of the third doped semiconductor layer is silicon-germanium claim 1 , and the material of the fourth doped semiconductor layer is silicon.3. ...

MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR

A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeOlayer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins. 1. A method for fabricating a vertical transistor device , comprising:forming a first plurality of fins in a first device region on a substrate, wherein the first plurality of fins comprises a first portion on the substrate and a second portion on the first portion, wherein the first portion is Si and the second portion is SiGe;forming a second plurality of Si fins in a second device region on the substrate, wherein a length of the first plurality of fins is equal to a length of the second plurality of fins;forming a plurality of metal gate layers on the substrate and on at least a portion of sidewalls of the first portion of the first plurality of fins and at least a portion of sidewalls of the second plurality of fins;forming a spacer layer on the plurality of metal gate layers and in contact with the sidewalls of each of the first and second plurality of fins up to a top of the first portion of the first plurality of fins thereby exposing a remaining portion of the first plurality of fins and the second plurality of fins above a top surface of the spacer layer;forming a dielectric layer on and up to the top surface of the spacer layer; and{'sub': '2', 'forming a first GeOlayer on the top surface of the spacer layer and the dielectric layer and over the exposed portion of the first plurality of fins and the second plurality of fins.'}2. The method according to claim 1 , ...

SEMICONDUCTOR STRUCTURES INCLUDING MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK

A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches. 1. A semiconductor structure comprising:one or more semiconductor devices on a wafer, the one or more devices having source/drain junctions;a recessed middle-of-line (MOL) oxide layer;a nitride layer over the one or more semiconductor devices;one or more self-aligned contact areas (CAs) through a dielectric layer and over a silicide filling trenches formed through the nitride layer down to the source/drain junctions; andan air-gap oxide layer including one or more introduced air-gaps having a height to the one or more self-aligned CAs and the nitride layer.2. The semiconductor structure of claim 1 , wherein the silicide comprises tungsten (W).3. The semiconductor structure of claim 2 , further comprising:a metal in the one or more CAs.4. The semiconductor structure of claim 3 , wherein the one or more semiconductor devices comprise metal gates.5. The semiconductor structure of claim 1 , further comprising metal caps over the metal gates and the one or more CAs.6. The semiconductor structure of claim 1 , wherein the one or more introduced air-gaps reduces capacitance of the MOL oxide layer. Nitride stacks are formed by opening contact holes in nitride and oxide layers covering one or more semiconductor devices on a silicon wafer. In a conventional MOL process, the nitride layer is formed to a thickness (e.g., 40 nanometers (nm)) and a thinner oxide layer is formed over the nitride layer ( ...

EFFECTIVE DEVICE FORMATION FOR ADVANCED TECHNOLOGY NODES WITH AGGRESSIVE FIN-PITCH SCALING

After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance. 1. A semiconductor structure comprising:a plurality of semiconductor fins located over a substrate;a gate stack straddling a portion of each of the plurality of semiconductor fins;a gate liner laterally surrounding a lower portion of the gate stack that contacts the plurality of semiconductor fins; anda gate spacer present atop the gate liner and laterally surrounding an upper portion of the gate stack that locates above the plurality of semiconductor fins,wherein outer sidewalls of at least a portion of the gate liner are offset from outer sidewalls of the gate spacer.2. The semiconductor structure of claim 1 , wherein the gate liner has a width less than a width of the gate spacer.3. The semiconductor structure of claim 2 , wherein the width of the gate liner ranges from 1 nm to 5 nm claim 2 , and the width of the gate spacer ranges from 5 nm to 50 nm.4. The semiconductor structure of claim 1 , wherein the gate liner has a top surface coplanar with a top surface of each of the plurality of semiconductor fins claim 1 , and the gate spacer has a bottom surface coplanar with the top surface of each of the plurality of semiconductor fins.5. The semiconductor structure of claim 1 , wherein the gate liner comprises a dielectric material different from a dielectric material of the gate spacer.6. The semiconductor structure of claim 1 , wherein the gate liner comprises silicoboron carbonitride claim 1 , ...

MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK

A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer. 1. A method of forming a semiconductor structure comprising:forming at least one self-aligned contact area (CA) element on a middle-of-line (MOL) oxide layer of the semiconductor structure, the MOL oxide layer including a plurality of gate stacks formed on a substrate;selectively recessing the MOL oxide layer to the at least one self-aligned CA element, a cap layer of the plurality of gate stacks and a nitride layer;selectively recessing the cap layer of the plurality of gate stacks;depositing an air-gap oxide layer introducing one or more air-gaps in the deposited air-gap oxide layer; andperforming chemical-mechanical planarization (CMP) on the deposited air-gap oxide layer reducing the air gap oxide layer to the at least one self-aligned CA element and the nitride layer.2. The method of claim 1 , further comprising:depositing metal caps to the at least one self-aligned CA element and at least one gate element, wherein the at least one gate element comprises a tungsten (W) gate element, and CMP on the deposited air-gap oxide layer stops on the metal caps on the at least one self-aligned CA element.3. The method of claim 1 , further comprising:masking the at least one self-aligned CA element of the semiconductor structure prior to selectively recessing the MOL oxide layer.4. The method of claim 3 , further comprising:recessing tungsten (W) and titanium nitride (TiN) after selectively recessing the MOL oxide layer.5. The method of claim 4 , wherein selectively recessing the cap layer of the plurality of gate stacks comprises etching the cap layer using reactive ion ...

IMPROVING CHANNEL STRAIN AND CONTROLLING LATERAL EPITAXIAL GROWTH OF THE SOURCE AND DRAIN IN FINFET DEVICES

A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure. 1. A multi-gate finFET structure comprising:an epitaxial semiconductor layer, wherein the epitaxial semiconductor layer fills, at least in part, an area between a first gate structure and a second gate structure; anda stress-inducing material that fills a fin cut trench that is adjacent to the first gate structure.2. The multi-gate finFET structure of further comprising:a MOL ILD layer, wherein the MOL ILD layer abuts portions of the epitaxial semiconductor layer.3. The multi-gate finFET structure of claim 2 , wherein the MOL ILD layer is one or both of: silicon dioxide and a low-κ dielectric material.4. The multi-gate finFET structure of claim 1 , wherein the first and second gate structures are each one of a sacrificial gate or a true gate.5. The multi-gate finFET structure of claim 1 , wherein one or both of the first and second gate structures include one or more of: silicon claim 1 , doped polysilicon with metal silicide claim 1 , tungsten claim 1 , titanium claim 1 , tantalum claim 1 , aluminum claim 1 , nickel claim 1 , ruthenium claim 1 , palladium claim 1 , platinum claim 1 , tungsten nitride claim 1 , aluminum nitride claim 1 , titanium nitride claim 1 , tungsten silicide claim 1 , nickel silicide claim 1 , and titanium silicide.6. The multi-gate finFET structure of claim 1 , wherein the stress-inducing material is a stress nitride.7. The multi-gate finFET structure of claim 1 , wherein the stress- ...

FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure. 1. A method comprising:providing at least one fin structure over a stacked structure of an insulator layer that is present over at least one semiconductor layer;providing a gate structure on a channel region portion of the at least one fin structure;removing exposed portions of the at least one fin structure;forming a sacrificial spacer on a sidewall of the gate structure;removing exposed portions of the insulator layer to provide a pedestal of insulating material exposing a portion of at least one semiconductor layer;forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer, the first epitaxial material layer contacting the sacrificial spacer;removing the sacrificial spacer; andforming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer to provide source and drain regions.2. The method according to further comprising forming a gate sidewall spacer directly on the sidewall of the gate structure prior to the removing of the exposed portions of the insulator layer claim 1 , wherein said forming the sacrificial spacer over the ...

SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE

A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer. 1. A method of forming a semiconductor device , the method comprising:providing a first plurality of semiconductor fins that are spaced apart from each other and are located on a top surface of a first semiconductor layer, the first semiconductor material layer is present in at least a first region of a bulk semiconductor substrate;forming at least one first region gate structure straddling over a portion of the first plurality of semiconductor fins;partially removing the first semiconductor layer from the first region to provide a vertical semiconductor material portion located beneath a portion of at least one of the first plurality of semiconductor fins that is overlapped by the at least one first region gate structure and to form a first region space, wherein the vertical semiconductor material portion contacts the bulk semiconductor substrate and the at least one of the first plurality of semiconductor fins; anddepositing a first dielectric layer filling in the first region space and laterally surrounding the vertical semiconductor material portion such that the at least one first region gate structure and the first plurality of ...

SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE

A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer. 1. A semiconductor device comprising:a first plurality of semiconductor fins spaced apart from each other and located on a first region of a bulk semiconductor substrate;at least one first region gate structure straddling over a portion of the first plurality of semiconductor fins;at least one vertical semiconductor material portion located in a first region space located between a top surface of the first region of the bulk semiconductor substrate and a bottom surface of the first plurality of semiconductor fins and a bottom surface of the at least one first region gate structure, wherein the at least one vertical semiconductor material portion provides a heat dissipation path from the at least one first region gate structure and at least one of the first plurality of semiconductor fins to the first region of the bulk semiconductor substrate;a first dielectric layer filling in the first region space and laterally surrounding the at least one vertical semiconductor material portion in the first region space such that the first plurality of semiconductor fins and the at least one first region gate structure are partially isolated from the bulk ...

Middle-of-line (mol) capacitance reduction for self-aligned contact in gate stack

A method of forming a semiconductor structure includes forming a middle-of-line (MOL) oxide layer in the semiconductor structure. The MOL oxide layer including multiple gate stacks formed on a substrate. A nitride layer is formed over a silicide in the MOL oxide layer. At least one self-aligned contact area (CA) element is formed within the nitride layer. The MOL oxide layer is selectively recessed on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and a nitride. A nitride cap of the plurality of gate stacks is selectively recessed. An air-gap oxide layer is deposited for introducing one or more air-gaps in the deposited air-gap oxide layer. The air gap oxide layer is reduced to the at least one self-aligned CA element and the nitride layer.

VERTICAL NANO-WIRE COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH CYLINDRICAL III-V COMPOUND AND GERMANIUM CHANNEL

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures. 1. A semiconductor structure comprising at least:a substrate;a first source/drain layer in contact with at least the substrate;a vertical channel comprising indium gallium arsenide in contact with at least the first/source drain layer;a gate structure in contact with at least the vertical channel; anda second source/drain layer in contact with at least inner sidewalls of the vertical channel.2. The semiconductor structure of claim 1 , wherein the substrate comprises silicon.3. The semiconductor structure of claim 1 , further comprising:a first spacer layer in contact with at least the first source/drain layer and the vertical channel; anda second spacer layer in contact with the gate structure and the second source/drain layer.4. The semiconductor structure of claim 3 , wherein the gate structure comprises a dielectric layer in contact with the vertical channel claim 3 , the first spacer layer claim 3 , and the second spacer layer claim 3 , and wherein the gate structure further comprises a metal layer in contact with the dielectric layer and the second spacer.5. The semiconductor structure of claim 1 , further comprising:a silicide region in contact with the second source/drain layer.6. The semiconductor structure of claim 1 , wherein the vertical ...

Modified fin cut after epitaxial growth

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

MODIFIED FIN CUT AFTER EPITAXIAL GROWTH

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions. 1. A semiconductor structure comprising:a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the first plurality of fins;a second plurality of fins located in a second region of the substrate, wherein a second junction is located on a second set of fins in the second plurality of fins;an intermediate plurality of fins located in an intermediate region of the substrate, wherein the intermediate region is located between the first region and the second region, wherein the length of the intermediate plurality of fins is substantially shorter than a length of the first plurality of fins; anda gate running substantially perpendicular to the first plurality of fins, the intermediate plurality of fins, and the second plurality of fins.2. The structure of claim 1 , wherein the first junction comprises a semiconductor material.3. The structure of claim 2 , wherein the semiconductor material comprises silicon claim 2 , silicon-germanium or silicon-carbon.4. The structure of claim 1 , wherein the second junction material comprises a semiconductor material.5. The structure of claim 4 , wherein the semiconductor material comprises silicon claim 4 , silicon-germanium or silicon-carbon.6. The structure of claim 1 , wherein the substrate is a semiconductor on insulator substrate.7. The structure of claim 1 , wherein the fin pitch amongst the fins is substantially uniform.8. The structure of claim 1 , wherein the intermediate plurality of fins is only located beneath the gate.9. The structure of claim 1 , wherein the gate has a substantially uniform density.10. A semiconductor structure comprising:a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the ...

Finfet with epitaxial source and drain regions and dielectric isolated channel region

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Spacer for dual epi cmos devices

Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

SPACER FOR DUAL EPI CMOS DEVICES

Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process. 1. A method of making a semiconductor comprising:patterning a first transistor comprising two or more first gate stacks on a first source-drain area and second transistor comprising two or more second gate stacks on a second source-drain area;depositing a wet-etch resistant spacer material on the first and second transistors;removing the spacer from a first transistor fin region and a second transistor fin region with anisotropic spacer reactive ion etch;depositing a first nitride liner on the first and second transistors;depositing a dielectric layer on the first nitride layer;planarizing the dielectric layer;selectively removing the dielectric layer from between the spacer material in the first transistor fin region and the second transistor fin region;depositing a second nitride liner on the first and second transistors and selectively removing the second nitride liner from the first transistor;growing a first epitaxial layer on the first source-drain area by an epitaxial growth process; ...

SPACER FORMATION ON SEMICONDUCTOR DEVICE

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack. 1. A method for forming a semiconductor device , the method comprising:forming a semiconductor fin on a substrate;forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin;forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack;depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack;depositing a first sacrificial layer on the first liner layer;removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack; andgrowing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.2. The method of claim 1 , further comprising:depositing a second sacrificial layer on the first source drain region, the first sacrificial gate stack and the second sacrificial gate stack;removing a portion of the second sacrificial layer and the first sacrificial ...

METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES

A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate. 1. A semiconductor device , comprising:a gate arranged on a substrate;a source/drain formed on the substrate adjacent to the gate;a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; anda silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.2. The semiconductor device of claim 1 , wherein the source/drain comprises an epitaxially grown semiconductor material.3. The semiconductor device of claim 1 , wherein the ILD contacts a sidewall of the source/drain contact.4. The semiconductor device of claim 1 , wherein the silicide is a U-shaped film.5. The semiconductor device of claim 1 , wherein the ILD is disposed between the source/drain contact and the gate.6. The semiconductor device of claim 1 , wherein a width of the source/drain contact is in a range from about 7 to about 35 nm.7. A semiconductor device claim 1 , comprising:a gate arranged on a substrate;an epitaxially grown semiconductor material formed on the substrate adjacent to the gate;a trench extending from the substrate through an interlayer dielectric (ILD) disposed over the substrate and between the trench and the gate, a ...

VERTICAL FIN BIPOLAR JUNCTION TRANSISTOR WITH HIGH GERMANIUM CONTENT SILICON GERMANIUM BASE

A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins. An emitter, a base and a collector contacts are formed to connect to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively. The BJT structures manufactured are also provided. 1. A bipolar junction transistor (BJT) structure comprising:a first semiconductor layer disposed on a substrate;a plurality of vertical fins disposed on the first semiconductor layer, spaced apart in a first direction and extending in a second direction crossing the first direction, each of the plurality of vertical fins vertically protruding in a third direction perpendicular to the first and second directions, and comprising a silicon germanium pattern and a second semiconductor pattern sequentially stacked on the first semiconductor layer;a dielectric material formed over the first semiconductor layer to fill all spaces among the plurality of vertical fins; andan emitter contact, a base contact and a collector contact formed within the dielectric material to connect to the second semiconductor pattern, the silicon germanium pattern and the first ...

PHASE CHANGE MEMORY

An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include a phase change element located above a heater. The heater may include a conductive element surrounding a dielectric element. The dielectric element may include an air gap. 1. A memory structure comprising:a phase change element located above a heater: andwherein the heater comprises a conductive element surrounding a dielectric element.2. The structure of claim 1 , wherein the dielectric element includes an air gap.3. The structure of claim 1 , wherein the conductive element comprises a first conductive liner and a second conductive liner.4. The structure of claim 3 , wherein the second conductive liner is about 0.05 to about 0.5 times a resistance of the first conductive liner.5. The structure of further comprising a projection liner between the heater and the phase change element.6. The structure of claim 2 , wherein a material of the dielectric element is selected from the group consisting of: SiN claim 2 , SiO2 claim 2 , and SiCxOy.7. The structure of claim 2 , wherein the air gap comprises at least 0.1% of the volume of a region containing the dielectric element.8. The structure of claim 3 , wherein a material of the first conductive liner is selected from the group consisting of: TaN and SiN.9. The structure of claim 3 , wherein a material of the second conductive liner is selected from the group consisting of: TiN claim 3 , graphene claim 3 , TaN claim 3 , W claim 3 , Cu claim 3 , Ru claim 3 , Au claim 3 , and Pt.10. The structure of claim 5 , wherein a material of the projection liner is TaN.11. A memory structure comprising:a phase change element located on a projection liner above a heater andwherein the heater comprises a conductive element surrounding a dielectric element, wherein the dielectric element includes an air gap.12. The structure of claim 11 , wherein the conductive element comprises a first conductive liner and a second conductive ...

Techniques for Enhancing Vertical Gate-All-Around FET Performance

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques. 1. A method of forming a vertical field effect transistor (VFET) device , the method comprising the steps of:patterning at least one fin in a substrate;forming bottom source and drains at a base of the at least one fin;forming bottom spacers on the bottom source and drains;forming a gate along sidewalls of the at least one fin;recessing the gate to expose a top portion of the at least one fin;forming an oxide layer along the sidewalls of the top portion of the at least one fin;depositing a charged layer over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;forming top spacers above the gate; andforming top source and drains above the top spacers.2. The method of claim 1 , wherein the charged layer has a positive charge.3. The method of claim 2 , wherein the charged layer is formed from a material selected from the group consisting of: strontium oxide (SrO) claim 2 , lanthanum oxide (LaO) claim 2 , lutetium oxide (LuO) claim 2 , yttrium oxide (YO) claim 2 , and combinations thereof.4. The method of claim 1 , wherein ...

VERTICAL FIELD EFFECT TRANSISTOR WITH LOW-RESISTANCE BOTTOM SOURCE-DRAIN CONTACT

A method of forming a semiconductor structure includes forming a metal liner above and in direct contact with a bottom source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom source/drain region includes an epitaxially grown material in direct contact with a bottom portion of the fin not covered by the fin spacer, forming an organic planarization layer directly above the metal liner, simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed and only portions of the metal liner parallel to the substrate remain in contact with the bottom source/drain region, and annealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom source/drain region. 1. A method of forming a semiconductor structure , the method comprising:forming a metal liner above and in direct contact with a bottom epitaxially grown source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom epitaxially grown source/drain region is in direct contact with a bottom portion of the fin not covered by the fin spacer;forming an organic planarization layer directly above the metal liner;simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed from the semiconductor structure, wherein only portions of the metal liner parallel to the substrate remain in contact with the bottom epitaxially grown source/drain region; andannealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom epitaxially grown source/drain region, wherein only a bottom surface and sidewalls of the metal silicide layer are in ...

REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions. 1. A method of fabricating a semiconductor device , the method comprising:forming at least one semiconductor fin on a semiconductor substrate;forming an etch stop layer on an upper surface of the at least one semiconductor fin;forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material;patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;depositing a spacer layer that conforms with an outer surface of each dummy gate element; andetching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin.2. The method of claim 1 , further comprising epitaxially growing a semiconductor material from the exposed portion of the semiconductor fin after etching the spacer layer and the portion of the etch stop layer.3. The method of ...

FINFET WITH DIELECTRIC ISOLATED CHANNEL

Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution. 1. A semiconductor structure comprising:a semiconductor substrate;a punchthrough stopper region formed on the semiconductor substrate;an insulator region formed on a portion of the punchthrough stopper region;a gate formed on the insulator region;a fin formed over the punchthrough stopper region, and traversing the gate; andan epitaxial semiconductor region disposed on the fin, and in direct physical contact with a bottom surface of the fin, and in direct physical contact with the punchthrough stopper region.2. The semiconductor structure of claim 1 , wherein the semiconductor substrate comprises a silicon substrate.3. The semiconductor structure of claim 1 , wherein the punchthrough stopper (PTS) region comprises a doped region of the semiconductor substrate and comprises a (100) crystalline surface.4. The semiconductor structure of claim 1 , wherein the epitaxial semiconductor region is also in direct physical contact with the punchthrough stopper region.5. The semiconductor structure of claim 2 , wherein the punchthrough stopper region comprises arsenic dopants.6. The semiconductor structure of claim 2 , wherein the punchthrough stopper region ...

Embedded BEOL Memory Device with Top Electrode Pillar

Embedded BEOL memory devices having a top electrode pillar are provided. In one aspect, a method of forming an embedded memory device includes: depositing a first ILD on a substrate; forming first/second interconnect in the first ILD over logic/memory regions of the substrate; depositing a capping layer onto the first ILD; forming a memory film stack on the capping layer; patterning the memory film stack into a memory device(s) including a bottom electrode, a dielectric element, and a top electrode; patterning the top electrode to form a pillar-shaped top electrode; depositing a conformal encapsulation layer over the capping layer and memory device(s); depositing a second ILD over the conformal encapsulation layer; and forming a first metal line(s) in the second ILD in contact with the first interconnect(s), and a second metal line(s) in the second ILD in contact with the pillar-shaped top electrode. A device is also provided. 1. A method of forming an embedded memory device , the method comprising the steps of:depositing a first interlayer dielectric (ILD) on a substrate;forming at least one first interconnect in the first ILD over a logic region of the substrate, and at least one second interconnect in the first ILD over a memory region of the substrate;depositing a capping layer onto the first ILD over the at least one first interconnect and the at least one second interconnect;forming a memory film stack on the capping layer, the memory film stack comprising a bottom electrode layer disposed on the capping layer, a dielectric layer disposed on the bottom electrode layer, and a top electrode layer disposed on the dielectric layer;{'b': '1', 'patterning the memory film stack into at least one memory device comprising a bottom electrode disposed on the capping layer over the at least one second interconnect, a dielectric element disposed on the bottom electrode, and a top electrode disposed on the dielectric element, wherein the at least one memory device has a ...

FinFET DEVICE WITH ABRUPT JUNCTIONS

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers. 1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;providing a dielectric spacer on vertical sidewalls of each gate structure;removing portions of each semiconductor fin and a portion of said insulator layer utilizing each dielectric spacer and each gate structure as an etch mask, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; anddiffusing a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along said one exposed ...

Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided. 1. A method of forming a nanosheet device , the method comprising the steps of:forming an alternating series of sacrificial and active channel nanosheets as a stack on a substrate;forming gates on the stack;forming spacers alongside opposite sidewalls of the gates;patterning the stack, in between the spacers, into individual PFET and NFET stacks, wherein the patterning forms pockets in the substrate between the PFET and NFET stacks;laterally recessing the sacrificial nanosheets in the PFET and NFET stacks to expose tips of the active channel nanosheets in the PFET and NFET stacks;forming inner spacers alongside the PFET and NFET stacks covering the tips of the active channel nanosheets;forming an oxide protective layer lining the pockets in the substrate;selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET and NFET stacks,wherein the ...

Removal of trilayer resist without damage to underlying structure

A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.

Methods of patterning features having differing widths

Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR WITH ASYMMETRIC CHANNEL PROFILE

A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer. 1. A method of forming a plurality of vertical fin field effect transistors , comprising:forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate;forming an isolation region between the first region and the second region;forming a gate dielectric layer on the first vertical fin and the second vertical fin;forming a first work function layer on the gate dielectric layer;removing an upper portion of the first work function layer to expose an upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region; andforming a second work function layer on a remaining portion of the first work function layer and the exposed upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region, wherein the remaining portion of the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.2. The method of claim 1 , further comprising ...

MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR

A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeOlayer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins. 1. A vertical transistor device , comprising:a first plurality of Si fins disposed in a first device region on a substrate;a second plurality of Si fins disposed in a second device region on the substrate;a first metal gate layer disposed on the substrate and on a portion of sidewalls of the first plurality of fins in the first device region;a second metal gate layer disposed on the substrate and on a portion of sidewalls of the second plurality of fins in the second device region;a first spacer layer disposed on the first metal gate layer and on a remaining portion of the sidewalls of the first plurality of fins;a second spacer layer disposed on the second metal gate layer and on another portion of the sidewalls of the second plurality of fins thereby exposing a remaining portion of the second plurality of fins above a top surface of the second spacer layer;a dielectric layer disposed on and up to the top surface of the second spacer layer;a plurality of top source/drain regions extending from an exposed top surface of the first plurality of fins in the first device region, wherein the top source/drain regions in the first device region are in a triangle shaped configuration; anda plurality of top source/drain regions extending from an exposed top surface of the second plurality of fins in the second device region, wherein the top source/drain regions in the second device ...

REMOVAL OF WORK FUNCTION METAL WING TO IMPROVE DEVICE YIELD IN VERTICAL FETS

A vertical transistor that includes a gate structure containing a work function metal liner that is wing-free is provided. The wing-free work function metal liner is provided by recessing a sacrificial material layer portion that is located adjacent to a work function metal liner having a winged surface near the channel and fin ends. The recessed sacrificial material layer portion allows for multi-directional etching of the winged surface of the work function metal liner and thus the wing surface can be removed forming a wing-free work function metal liner. The vertical transistor of the present application has reduced parasitic capacitance and a reduced tendency of electrical shorting between a top source/drain structure and the gate structure. The method of the present application can improve device yield. 1. A vertical transistor comprising:a semiconductor fin located on a mesa portion of a semiconductor substrate;a bottom source/drain structure extending from a sidewall of the mesa portion of the semiconductor structure;a gate structure located adjacent to a sidewall of the semiconductor fin and spaced apart from the bottom source/drain structure, the gate structure comprising a gate dielectric material liner and a wing-free work function metal liner;a sacrificial material liner located on the wing-free work function metal liner; anda top source/drain structure spaced apart from the gate structure and contacting an upper portion of the sidewall of semiconductor fin and a topmost surface of the semiconductor fin.2. The vertical transistor of claim 1 , further comprising a bottom spacer located between the bottom source/drain structure and the gate structure and contacting a lower portion of the sidewall of the semiconductor fin.3. The vertical transistor of claim 2 , further comprising a top spacer located between the top source/drain structure and the gate structure and contacting a portion of the sidewall of the semiconductor fin.4. The vertical transistor of ...

SPACER FOR TRENCH EPITAXIAL STRUCTURES

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material. 1. A method , comprising:forming a source and drain material about first-type gate structures, confined within an area defined by a spacer material; andforming the source and drain material about second-type gate structures, confined within the area defined by the spacer material.2. The method of claim 1 , further comprising:forming additional spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over a first capping layer; andforming the spacer material on a second capping layer in source and drain regions between the first-type gate structures and the second-type gate structures;3. The method of claim 2 , wherein the spacer material is a low-k dielectric material which defines trench structures for the source and drain material for the first-type gate structures and the second-type gate structures.4. The method of claim 2 , wherein the additional spacer material is nitride or oxide material.5. The method of claim 2 , wherein the forming source and drain material about the first-type gate structures and the second-type gate structures is an epitaxial growth process.6. The method of claim 5 , wherein the forming source and drain material about the first-type gate structures is formed while blocking growth of material about the second-type gate structures.7. The method of claim 6 , further comprising etching a mask over the first-type gate structures to expose the source and drain regions associated with the ...

SPACER FOR TRENCH EPITAXIAL STRUCTURES

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material. 1. A structure , comprising:a plurality of first-type gate structures;a plurality of second-type gate structures; anda low-k dielectric spacer material defining trenches for source and drain regions of the plurality of first-type gate structures and the plurality of second-type gate structures and which confines epitaxial source and drain material from shorting between adjacent ones of the plurality of first-type gate structures and the plurality of second-type gate structures due to a spacing of fins.2. The structure of claim 1 , wherein the low-k dielectric spacer material is a nitride or oxide material.3. The structure of claim 1 , wherein the first-type gate structures are p-type finFET devices and the second-type gate structures are n-type finFET devices.4. The structure of claim 1 , further comprising a first capping layer of a first capping material formed on the plurality of first-type gate structures and the plurality of second-type gate structures.5. The structure of claim 4 , further comprising a second capping layer of a second capping material formed on a spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over the first capping layer6. A structure claim 4 , comprising:a first spacer material formed on sidewalls of first-type gate structures and second-type gate structures and over a first capping layer;a second spacer material formed on a second capping layer in source and drain regions between ...

Finfet with dielectric isolated channel

Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution.

OXIDE-BASED RESISTIVE MEMORY HAVING A PLASMA-EXPOSED BOTTOM ELECTRODE

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment. 1. A method of fabricating a resistive switching device , the method comprising:forming a metal interconnect electrode;forming a memory stack comprising a plurality of layers, wherein the plurality of layers includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode; andperforming a charge particle treatment on at least one of the plurality of layers of the memory stack.2. The method of claim 1 , wherein the memory stack is formed on the metal interconnect electrode claim 1 , wherein dimensions of the memory stack are larger than the metal interconnect electrode.3. The method of claim 2 , wherein the metal interconnect electrode is formed on a surface of a metal interconnect layer.4. The method of claim 3 , wherein the metal interconnect layer is formed in an inter-level dielectric over a substrate.5. The method of further comprising:etching the top electrode of the memory stack;performing charge particle treatment on the top electrode of the memory stack; andetching the dielectric layer and bottom electrode.6. The method of further comprising:etching the top electrode of the memory stack;etching the dielectric layer; andperforming the charge particle treatment on the bottom electrode of the memory stack.7. The method of claim 1 , wherein ...

REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region. The middle layer is disposed between the top layer and a bottom layer of the trilayer photoresist structure. The middle layer and the bottom layer in the first region are removed to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region. The first region is filled to protect the at least one first structure. The middle layer in the second region is removed while the at least one first structure remains protected. 1. A method for semiconductor processing , comprising:removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region, the middle layer being disposed between the top layer and a bottom layer of the trilayer photoresist structure;removing the middle layer and the bottom layer in the first region to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region;filling the first region to protect the at least one first structure; andremoving the middle layer in the second region while the at least one first structure remains protected.2. The method as recited in claim 1 , wherein the trilayer photoresist structure includes an organic layer claim 1 , inorganic layer and organic layer claim 1 , respectively claim 1 , for the top layer claim 1 , the middle layer and the bottom layer.3. The method as recited in claim 1 , wherein the middle layer is resistant to etchants employed to etch the ...

BOOSTED VERTICAL FIELD-EFFECT TRANSISTOR

Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins. 1. A logic device , comprising:a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer, wherein a bottom source/drain contact is between a first surface and the first epitaxial layer, and a top source/drain contact is between the first surface and the second epitaxial layer at a respective first portion of one or more vertical fins; anda boosted bipolar junction transistor, wherein a bipolar junction transistor contact is between the first surface and the second epitaxial layer at a respective second portion of the one or more vertical fins, wherein the respective first portion and the respective second portion are opposite portions of the one or more vertical fins.2. The logic device of claim 1 , wherein the vertical field effect transistor is an n-channel field effect transistor.3. The logic device of claim 1 , wherein the vertical field effect transistor is a p-channel field effect transistor.4. The logic device of claim 1 , wherein the bipolar junction transistor contact provides a boosted voltage level for the logic device.5. The logic device of claim 1 , further ...

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) NANOSHEET DEVICES WITH EPITAXIAL SOURCE/DRAINS AND REPLACEMENT METAL GATE STRUCTURES

A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices is provided. The method includes forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks. The method further includes forming a protective cap layer over the trimmed stacks, and forming a sacrificial fill layer on the protective cap layer. The method further includes forming a recess through the sacrificial fill layer and protective cap layer between the stacks, depositing a recess liner in the recess, and forming a dielectric fill layer in the recess on the recess liner. The method further includes forming a capping layer on one of the trimmed stacks, removing the sacrificial fill layer from another one of the trimmed stacks, and forming a source/drain on the semiconductor nanosheet segments. 1. A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices , comprising:forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks;replacing a portion of each of the sacrificial sheet segments with an inner spacer;forming a protective cap layer over the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;forming a sacrificial fill layer on the protective cap layer;forming a recess through the sacrificial fill layer and protective cap layer between the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;depositing a recess liner in the recess;forming a dielectric fill layer in the recess on the recess liner;forming a capping layer on one of the at least two adjacent trimmed stacks;removing the sacrificial fill layer from at least another one of the at ...

PHASE CHANGE MEMORY STRUCTURE WITH EFFICIENT HEATING SYSTEM

A semiconductor device and method of forming a semiconductor device are provided. The semiconductor device includes a pore-type heater having a center pore recess. The semiconductor device further includes a tapered structure formed on the pore-type heater and having a tip portion at least extending down to the center pore recess. The semiconductor device also includes a containment layer confining volatile active material during any of a fabrication and an operation of the semiconductor device performed above a threshold temperature. 1. A semiconductor device , comprising:a pore-type heater having a center pore recess;a tapered structure formed on the pore-type heater and having a tip portion at least extending down to the center pore recess; anda containment layer confining volatile active material during any of a fabrication and an operation of the semiconductor device performed above a threshold temperature.2. The semiconductor device of claim 1 , wherein the tapered structure is filled with at least two metals.3. The semiconductor device of claim 2 , wherein the at least two metals form a metallic heater structure comprising a first metal forming a core encapsulated by a second metal such that a majority of a current flow through the metallic structure is through the first metal due to a resistance differential between the first metal and the second metal.4. The semiconductor device of claim 3 , wherein the first metal is Titanium Nitride and the second metal is Tantalum Nitride.5. The semiconductor device of claim 2 , wherein the at least two metals comprises Tantalum Nitride.6. The semiconductor device of claim 2 , wherein the at least two metals comprises Titanium Nitride.7. The semiconductor device of claim 1 , wherein the tapered structure is at least partially formed within a dielectric.8. The semiconductor device of claim 1 , wherein the tapered structure has a V-shape.9. The semiconductor device of claim 1 , wherein the tip portion extends within the ...

Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided. 1. A nanosheet device , comprising:individual PFET and NFET stacks on a substrate, wherein the PFET and NFET stacks each comprises active channel nanosheets;pockets in the substrate between the PFET and NFET stacks;an oxide protective layer lining the pockets in the substrate;epitaxial source and drains on opposite sides of the PFET and NFET stacks;gates surrounding at least a portion of each of the active channel nanosheets; andinner spacers offsetting the gates from the epitaxial source and drains.2. The nanosheet device of claim 1 , wherein the gates surround the active channel nanosheets in a gate-all-around configuration.3. The nanosheet device of claim 1 , wherein the active channel nanosheets comprise silicon (Si).4. The nanosheet device of claim 1 , wherein the active channel nanosheets comprise silicon germanium (SiGe).5. The nanosheet device of claim 1 , further comprising:a second oxide protective layer over the epitaxial source and drains on the opposite sides of the PFET stacks. ...

SPACER FOR TRENCH EPITAXIAL STRUCTURES

The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material. 1. A method , comprising:forming source and drain material confined within an area defined by a single spacer material; andsubsequent to the forming the source and drain material, forming a plurality of first-type gate structures and a plurality of second-type gate structures separated from the plurality of the first-type gate structures by the single spacer material.2. The method of claim 1 , further comprising:forming additional spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over a first capping layer; andforming the single spacer material on a second capping layer in source and drain regions between the first-type gate structures and the second-type gate structures.3. The method of claim 2 , wherein the single spacer material is a low-k dielectric material which defines trench structures for the source and drain material for the first-type gate structures and the second-type gate structures.4. The method of claim 2 , wherein the additional spacer material is nitride or oxide material.5. The method of claim 2 , wherein the forming the source and drain material is an epitaxial growth process.6. The method of claim 1 , wherein the first-type gate structures are p-type devices and the second-type gate structures are n-type devices.7. The method of claim 1 , wherein the first-type gate structures are p-type finFET devices and the second-type gate structures are n-type finFET devices.8. The method of claim ...

FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure. 1. A structure comprising:a pedestal of an insulating material present over at least one layer of a semiconductor material;at least one fin structure in contact with the pedestal of the insulating material;source and drain region structures on opposing sides of the at least one fin structure, at least one of the source and drain region structures comprising at least two epitaxial material layers, wherein a first epitaxial material layer of the at least two epitaxial layers is in contact with the at least one layer of semiconductor material, and a second epitaxial material layer of the at least two epitaxial layers is in contact with the at least one fin structure, the first epitaxial material layer being separated from the at least one fin structure by the second epitaxial material layer; anda gate structure present on the at least one fin structure.2. The structure according to claim 1 , wherein the at least one fin structure is a channel region claim 1 , and an interface between the second epitaxial material layer of the source and drain region structures and the channel region is substantially free of defects.3. The structure according to claim 1 , wherein the at least ...