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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 292. Отображено 158.
30-01-2018 дата публикации

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Номер: US0009882048B2
Автор: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang, ANDERSON BRENT A, KANAKASABAPATHY SIVANANDA K, SHEARER JEFFREY C, SIEG STUART A, SPORRE JOHN R, WANG JUNLI, Anderson Brent A., Kanakasabapathy Sivananda K., Shearer Jeffrey C., Sieg Stuart A., Sporre John R., Wang Junli
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.

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Номер записи: 1
26-09-2017 дата публикации

Aligning conductive vias with trenches

Номер: US0009773700B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, COLBURN MATTHEW E, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE, Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material.

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Номер записи: 2
10-10-2017 дата публикации

Self aligned conductive lines

Номер: US0009786554B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, DESILVA ANUJA E, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE A, Burns Sean D., Clevenger Lawrence A., DeSilva Anuja E., Felix Nelson M., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

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Номер записи: 3
07-02-2017 дата публикации

Semiconductor structure containing semiconductor fins and insulating fence fins on a same substrate

Номер: US0009564438B2
Автор: Sivananda K. Kanakasabapathy, KANAKASABAPATHY SIVANANDA K, Kanakasabapathy Sivananda K.
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.

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Номер записи: 4
25-04-2017 дата публикации

System and method for source-drain extension in FinFETs

Номер: US0009634009B1
Автор: Atsuro Inada, Sivananda K. Kanakasabapathy, INADA ATSURO, KANAKASABAPATHY SIVANANDA K, Inada Atsuro, Kanakasabapathy Sivananda K.
Принадлежит: International Business Machines Corporation, IBM

A fin-type field effect transistor (finFET) device includes a gate disposed over at least two fins, each fin defining a source outboard portion and a drain outboard portion extending beyond the gate. There is a source contact that electrically connects the source outboard portions of the fins, and similarly on the opposed side of the gate there is a drain contact electrically connecting the drain outboard portions of the fins. A first dielectric spacer layer is disposed adjacent to the gate and overlying the fins, and a second dielectric spacer layer is disposed adjacent to the first spacer layer and also overlying the fins. The second dielectric spacer layer electrically isolates the gate from the drain contact and/or from the source contact. A method of making a finFET device is also detailed.

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Номер записи: 5
22-08-2017 дата публикации

Fin cut during replacement gate formation

Номер: US0009741823B1
Автор: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre, GREENE ANDREW M, PRANATHARTHIHARAN BALASUBRAMANIAN S, KANAKASABAPATHY SIVANANDA K, SPORRE JOHN R, Greene Andrew M., Pranatharthiharan Balasubramanian S., Kanakasabapathy Sivananda K., Sporre John R.
Принадлежит: Internation Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.

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Номер записи: 6
28-03-2017 дата публикации

Self aligned conductive lines with relaxed overlay

Номер: US0009607886B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, COLBURN MATTHEW E, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE A, Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

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Номер записи: 7
06-10-2016 дата публикации

STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES

Номер: US20160293492A1
Автор: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит:

A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

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Номер записи: 8
24-11-2016 дата публикации

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

Номер: US20160343861A1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, LIU DERRICK, SEO SOON-CHEON, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Liu Derrick, Seo Soon-Cheon, Sieg Stuart A.
Принадлежит:

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

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Номер записи: 9
30-01-2018 дата публикации

Static random access memory (SRAM) density scaling by using middle of line (MOL) flow

Номер: US0009881926B1
Автор: Veeraraghavan S. Basker, Kangguo Cheng, Sivananda K. Kanakasabapathy, Theodorus E. Standaert, Junli Wang, BASKER VEERARAGHAVAN S, CHENG KANGGUO, KANAKASABAPATHY SIVANANDA K, STANDAERT THEODORUS E, WANG JUNLI, Basker Veeraraghavan S., Cheng Kangguo, Kanakasabapathy Sivananda K., Standaert Theodorus E., Wang Junli
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer.

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Номер записи: 10
06-12-2016 дата публикации

Bulk fin formation with vertical fin sidewall profile

Номер: US0009515089B1
Автор: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin, CHENG KANGGUO, HE HONG, KANAKASABAPATHY SIVANANDA K, TSENG CHIAHSUN, YIN YUNPENG, Cheng Kangguo, He Hong, Kanakasabapathy Sivananda K., Tseng Chiahsun, Yin Yunpeng
Принадлежит: International Business Machines Corporation, IBM

Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.

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Номер записи: 11
31-10-2017 дата публикации

Strained finFET device fabrication

Номер: US0009805991B2
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

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Номер записи: 12
22-11-2016 дата публикации

Strained finFET device fabrication

Номер: US0009502411B1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

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Номер записи: 13
22-08-2017 дата публикации

Stress retention in fins of fin field-effect transistors

Номер: US0009741856B2
Автор: Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, SIEG STUART A, SPORRE JOHN R, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Sieg Stuart A., Sporre John R.
Принадлежит: International Business Machines Corporation, IBM

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

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Номер записи: 14
28-02-2017 дата публикации

Conformal doping for punch through stopper in fin field effect transistor devices

Номер: US0009583563B1
Автор: Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie, Tenko Yamashita, BU HUIMING, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, YAMASHITA TENKO, Bu Huiming, Kanakasabapathy Sivananda K., Lie Fee Li, Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

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Номер записи: 15
05-09-2017 дата публикации

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

Номер: US0009754798B1
Автор: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu, BI ZHENXING, CANAPERI DONALD F, DEVARAJAN THAMARAI S, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, XU PENG, Bi Zhenxing, Canaperi Donald F., Devarajan Thamarai S., Kanakasabapathy Sivananda K., Lie Fee Li, Xu Peng
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

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Номер записи: 16
27-03-2018 дата публикации

Material removal process for self-aligned contacts

Номер: US9929016B2
Автор: KANAKASABAPATHY SIVANANDA K, OZCAN AHMET S, Kanakasabapathy Sivananda K., Ozcan Ahmet S.
Принадлежит: IBM, International Business Machines Corporation

A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.

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Номер записи: 17
23-01-2018 дата публикации

Structure and process to tuck fin tips self-aligned to gates

Номер: US0009876074B2
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, LIU DERRICK, SEO SOON-CHEON, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Liu Derrick, Seo Soon-Cheon, Sieg Stuart A.
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

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Номер записи: 18
23-02-2017 дата публикации

STRAINED FINFET DEVICE FABRICATION

Номер: US20170054024A1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит:

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin. 1. A field effect transistor device comprising:a fin having a first semiconductor segment, a second semiconductor segment and an insulator material region disposed between the first semiconductor segment and the second semiconductor segment; anda first gate stack arranged over the first semiconductor segment.2. The device of claim 1 , further comprising a second gate stack arranged over the second semiconductor segment.3. The device of claim 1 , wherein the first semiconductor segment includes a silicon germanium material.4. The device of claim 1 , wherein the insulator material region includes an oxide material.5. The device of claim 1 , wherein the insulator material region includes a nitride material.6. The device of claim 1 , wherein the insulator material region is operative to electrically isolate the first semiconductor segment from the second semiconductor segment. This application is a divisional application of U.S. patent application Ser. No. 14/833,363, filed Aug. 24, 2015, entitled “STRAINED FINFET DEVICE FABRICATION,” which is a continuation application of U.S. patent application Ser. No. 14/830,969, filed on Aug. 20, 2015, entitled “STRAINED FINFET DEVICE FABRICATION,” the entire contents of which are incorporated herein by reference.The present invention relates to field ...

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Номер записи: 19
26-12-2017 дата публикации

Self aligned conductive lines

Номер: US0009852946B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, COLBURN MATTHEW E, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE, Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to the first and second sacrificial mandrels. A filler material is deposited on the second hardmask. A first mask is formed on a portion of the second sacrificial mandrel. A first cavity and a second cavity are formed that expose portions of the second hardmask, and exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. Exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a trench in the insulator layer and the trench is filled with a conductive material.

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Номер записи: 20
01-12-2016 дата публикации

PREVENTING STRAINED FIN RELAXATION

Номер: US20160351590A1
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит:

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

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Номер записи: 21
23-02-2017 дата публикации

STRAINED FINFET DEVICE FABRICATION

Номер: US20170053942A1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит:

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin. 1. A field effect transistor device comprising:a first semiconductor fin having a first distal end and a second distal end arranged on a substrate;a second semiconductor fin having a first distal end and a second distal end arranged on the substrate, the second semiconductor fin and the first semiconductor fin having a common longitudinal axis;an insulator material disposed between and in contact with the first distal end of the first semiconductor fin and the first distal end of the second semiconductor fin such that the insulator material exerts a tensile force on the first distal end of the first semiconductor fin and the first distal end of the second semiconductor fin; anda semiconductor layer arranged over an entirety of a longitudinal length of the first semiconductor fin.2. The device of claim 1 , wherein the semiconductor layer is arranged over an entirety of a longitudinal length of the second semiconductor fin.3. The device of claim 1 , wherein the insulator material includes an oxide material.4. The device of claim 1 , wherein the insulator material includes a tensile oxide material.5. The device of claim 1 , wherein the first semiconductor fin includes a silicon germanium material and the second semiconductor fin includes a silicon germanium material.6. (canceled)7. The ...

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Номер записи: 22
04-12-2013 дата публикации

Borderless contact for an aluminum-containing gate and forming method thereof

Номер: CN103426919A
Автор: Kanakasabapathy Sivananda K., Horak David V., Jagannathan Hemanth
Принадлежит:

The invention provides borderless contact for an aluminum-containing gate and a forming method thereof. An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from ...

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Номер записи: 23
22-06-2017 дата публикации

ENABLING LARGE FEATURE ALIGNMENT MARKS WITH SIDEWALL IMAGE TRANSFER PATTERNING

Номер: US20170179305A1
Автор: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan, CHENG KANGGUO, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, MILLER ERIC R, SHEARER JEFFREY C, SPORRE JOHN R, TEEHAN SEAN, Cheng Kangguo, Kanakasabapathy Sivananda K., Lie Fee Li, Miller Eric R., Shearer Jeffrey C., Sporre John R., Teehan Sean
Принадлежит:

In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks. 1. An integrated circuit component comprising:a gate electrode layer; anda hard mask layer on the gate electrode layer;wherein the hard mask layer is patterned with an alignment feature and a sidewall feature comprising a critical dimension;wherein a width of the alignment feature is greater than the critical dimension; andwherein the critical dimension is less than or equal to about 100 nanometers.2. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 5 to 100 nanometers.3. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 10 to 100 nanometers.4. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 10 to 40 nanometers.5. The integrated circuit component of claim 1 , wherein the alignment feature has a width of greater than or equal to 1 micrometer.6. The integrated circuit component of claim 1 , wherein the alignment feature has a width of greater than or equal to 25 nanometers.7. The integrated circuit component of claim 1 , wherein the alignment feature has a width of 25 to 100 nanometers.8. The integrated circuit component of claim 1 , wherein the hard layer mask comprisesa memory layer located on top of the gate electrode layer,an oxide layer located on top of the memory layer, anda hard mask planarization layer located on top of the oxide layer.9. The integrated circuit component of claim 8 , wherein the memory layer comprises a dielectric material comprising an oxide claim 8 , an oxide precursor claim 8 , or a nitride.10. The integrated circuit component of claim 8 , wherein the memory layer comprises a silicon nitride.11. The integrated circuit component of claim 8 , ...

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Номер записи: 24
10-01-2017 дата публикации

Asymmetric multi-gate finFET

Номер: US0009543435B1
Автор: Veeraraghavan S. Basker, Andres Bryant, Huiming Bu, Sivananda K. Kanakasabapathy, Tenko Yamashita, BASKER VEERARAGHAVAN S, BRYANT ANDRES, BU HUIMING, KANAKASABAPATHY SIVANANDA K, YAMASHITA TENKO, Basker Veeraraghavan S., Bryant Andres, Bu Huiming, Kanakasabapathy Sivananda K., Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.

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Номер записи: 25
15-06-2017 дата публикации

MATERIAL REMOVAL PROCESS FOR SELF-ALIGNED CONTACTS

Номер: US20170170019A1
Автор: Sivananda K. Kanakasabapathy, Ahmet S. Ozcan, KANAKASABAPATHY SIVANANDA K, OZCAN AHMET S, Kanakasabapathy Sivananda K., Ozcan Ahmet S.
Принадлежит:

A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process. 1. A method for fabricating a semiconductor device , the method comprising:subjecting a first material to a gas cluster ion beam etch process to remove the first material, the first material disposed over a second material and adjacent to a field effect transistor gate comprising a gate sidewall layer that comprises an etch-resistant material on a gate sidewall; anddetecting exposure of the second material during the gas cluster ion beam etch process.2. The method of claim 1 , further comprising terminating the gas cluster ion beam etch process in response to detecting exposure of the second material.3. The method of claim 1 , wherein the first material subjected to the gas cluster ion beam etch is disposed between adjacent field effect transistor gates comprising sidewall spacer layers.4. The method of claim 1 , wherein the first material comprises a dielectric material.5. The method of claim 1 , wherein the first material comprises a layer of said etch-resistant material.6. The method of claim 1 , wherein the second material comprises a source or drain of the field effect transistor.7. The method of claim 1 , further comprising subjecting the first material or another material adjacent to the gate sidewall to an etch process other than gas cluster ion beam etching.8. The method of claim 1 , wherein the gas cluster ion beam etch process is performed by a gas cluster ion beam etch apparatus that includes a sensor for detecting exposure of the second material.9. The method of claim 8 , wherein the gas cluster ion beam etch ...

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Номер записи: 26
02-05-2017 дата публикации

FinFET device with channel strain

Номер: US0009640640B1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

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Номер записи: 27
17-11-2016 дата публикации

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

Номер: US20160336347A1
Автор: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin, CHENG KANGGUO, HE HONG, KANAKASABAPATHY SIVANANDA K, TSENG CHIAHSUN, YIN YUNPENG, Cheng Kangguo, He Hong, Kanakasabapathy Sivananda K., Tseng Chiahsun, Yin Yunpeng
Принадлежит:

Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.

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Номер записи: 28
23-02-2017 дата публикации

STRAINED FINFET DEVICE FABRICATION

Номер: US20170053838A1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит: International Business Machines Corp

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

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Номер записи: 29
12-12-2017 дата публикации

Self-aligned quadruple patterning process

Номер: US0009842737B2
Автор: Matthew E. Colburn, Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg, COLBURN MATTHEW E, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, SIEG STUART A, Colburn Matthew E., Kanakasabapathy Sivananda K., Lie Fee Li, Sieg Stuart A.
Принадлежит: International Business Machines Corporation, IBM

Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks.

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Номер записи: 30
18-04-2017 дата публикации

Structure and method for replacement gate integration with self-aligned contacts

Номер: US0009627510B1
Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, JAGANNATHAN HEMANTH, KANAKASABAPATHY SIVANANDA K, Jagannathan Hemanth, Kanakasabapathy Sivananda K.
Принадлежит: International Business Machines Corporation, IBM

A method for fabricating a semiconductor device comprises forming a dummy gate on a substrate; forming spacers at opposing sides of the dummy gate; depositing a sacrificial interlayer dielectric over the dummy gate; planarizing the interlayer dielectric to expose the dummy gate; removing the dummy gate; forming a replacement metal gate with a protective cap between the spacers and on the substrate to replace the removed dummy gate; removing the sacrificial interlayer dielectric; siliciding exposed areas of the substrate adjacent to the replacement metal gate; depositing a final interlayer dielectric over the replacement metal gate and the exposed silicided areas; and forming vias through the final interlayer dielectric to the silicided areas.

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Номер записи: 31
21-02-2017 дата публикации

Preventing strained fin relaxation by sealing fin ends

Номер: US0009576979B2
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

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Номер записи: 32
17-01-2017 дата публикации

Asymmetric multi-gate FinFET

Номер: US0009548379B1
Автор: Veeraraghavan S. Basker, Andres Bryant, Huiming Bu, Sivananda K. Kanakasabapathy, Tenko Yamashita, BASKER VEERARAGHAVAN S, BRYANT ANDRES, BU HUIMING, KANAKASABAPATHY SIVANANDA K, YAMASHITA TENKO, Basker Veeraraghavan S., Bryant Andres, Bu Huiming, Kanakasabapathy Sivananda K., Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.

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Номер записи: 33
26-09-2017 дата публикации

Forming a sacrificial liner for dual channel devices

Номер: US0009773893B1
Автор: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu, BU HUIMING, CHENG KANGGUO, GUO DECHAO, KANAKASABAPATHY SIVANANDA K, XU PENG, Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.

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Номер записи: 34
12-09-2017 дата публикации

Material removal process for self-aligned contacts

Номер: US0009761455B2
Автор: Sivananda K. Kanakasabapathy, Ahmet S. Ozcan, KANAKASABAPATHY SIVANANDA K, OZCAN AHMET S, Kanakasabapathy Sivananda K., Ozcan Ahmet S.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.

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Номер записи: 35
25-08-2016 дата публикации

REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS

Номер: US20160247766A1
Автор: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg, CONKLIN DAVID J, GABOR ALLEN H, KANAKASABAPATHY SIVANANDA K, KIM BYEONG Y, LIE FEE LI, SIEG STUART A, Conklin David J., Gabor Allen H., Kanakasabapathy Sivananda K., Kim Byeong Y., Lie Fee Li, Sieg Stuart A.
Принадлежит:

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least ...

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Номер записи: 36
03-04-2018 дата публикации

Self aligned pattern formation post spacer etchback in tight pitch configurations

Номер: US0009934970B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, COLBURN MATTHEW E, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE A, Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Felix Nelson M., Kanakasabapathy Sivananda K., Penny Christopher J., Quon Roger A., Saulnier Nicole A.
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

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Номер записи: 37
06-12-2016 дата публикации

FinFET device with channel strain

Номер: US0009515141B1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

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Номер записи: 38
07-03-2017 дата публикации

Pitch scalable active area patterning structure and process for multi-channel finFET technologies

Номер: US0009589958B1
Автор: Sivananda K. Kanakasabapathy, Fee Li Lie, Eric Miller, Stuart A. Sieg, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, MILLER ERIC, SIEG STUART A, Kanakasabapathy Sivananda K., Lie Fee Li, Miller Eric, Sieg Stuart A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.

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Номер записи: 39
13-03-2018 дата публикации

Strained FinFET device fabrication

Номер: US0009917019B2
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

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Номер записи: 40
26-01-2017 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20170025418A1
Автор: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang, CHAN KEVIN K, KANAKASABAPATHY SIVANANDA K, KHAN BABAR A, KOBAYASHI MASAHARU, LEOBANDUNG EFFENDI, STANDAERT THEODORUS E, WANG XINHUI, Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, Standaert Theodorus E., Wang Xinhui
Принадлежит:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure;a plurality of SOI fins each of which having ends in contact with respective fin structures of the deep trench capacitors;an insulator material on the fin structures of the plurality of deep trench capacitors;a gate structure extending over the insulator material and the SOI fins; andan epitaxial material on ends of the SOI fins and ends of the fin structures of the deep trench capacitors to provide a connection between the SOI fins and the fin structures of the deep trench capacitors,wherein each of the SOI fins are between the fin structures of the deep trench capacitors such that the ends of the SOI fins contact the ends of the fin structures of the deep trench capacitors.2. The structure of claim 1 , wherein the deep trench capacitors are eDRAM structures.3. The structure of claim 1 , wherein the SOI fins comprise portions of FinFETs.4. The structure of claim 1 , wherein the fin structures are polysilicon fins.5. The structure of claim 4 , wherein the polysilicon fins and the SOI fins are formed in contact with one another.6. The structure of claim 5 , wherein the insulator material is oxide material blanket deposited on the polysilicon fins.7. The structure of claim 6 , wherein the connection is provided by material of the ...

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Номер записи: 41
02-01-2018 дата публикации

Registration mark formation during sidewall image transfer process

Номер: US0009859224B2
Автор: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg, CONKLIN DAVID J, GABOR ALLEN H, KANAKASABAPATHY SIVANANDA K, KIM BYEONG Y, LIE FEE LI, SIEG STUART A, Conklin David J., Gabor Allen H., Kanakasabapathy Sivananda K., Kim Byeong Y., Lie Fee Li, Sieg Stuart A.
Принадлежит: International Business Machines Corporation, IBM

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least ...

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Номер записи: 42
16-03-2017 дата публикации

STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES

Номер: US20170077098A1
Автор: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит:

A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure. 1. A method of forming a multiple threshold voltage transistor structure , the method comprising:forming a first transistor having a high-k dielectric material with a first height; andforming a second transistor having the high-k dielectric material with a second height, the first height of the high-k dielectric material being different from the second height.2. The method of claim 1 , wherein the first transistor has a first channel and the second transistor has a second channel.3. The method of claim 2 , wherein the high-k dielectric material of the first transistor is in the first channel; andwherein the high-k dielectric material of the second transistor is in the second channel.4. The method of claim 3 , wherein the first channel and the second channel are formed on a fin.5. The method of claim 4 , wherein spacers define the first channel and the second channel.6. The method of claim 5 , wherein a work function metal is formed on the high-k dielectric material in the first channel and the second channel.7. The method of claim 6 , wherein a gate conduction metal is formed on the work function metal.8. The method of claim 7 , wherein the gate ...

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Номер записи: 43
10-04-2018 дата публикации

Tunable TiOxNy hardmask for multilayer patterning

Номер: US0009941142B1
Автор: Abraham Arceo De La Pena, Ekmini A. De Silva, Nelson M. Felix, Sivananda K. Kanakasabapathy, ARCEO DE LA PENA ABRAHAM, DE SILVA EKMINI A, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, Arceo De La Pena Abraham, De Silva Ekmini A., Felix Nelson M., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.

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Номер записи: 44
08-12-2016 дата публикации

REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS

Номер: US20160358861A1
Автор: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg, CONKLIN DAVID J, GABOR ALLEN H, KANAKASABAPATHY SIVANANDA K, KIM BYEONG Y, LIE FEE LI, SIEG STUART A, Conklin David J., Gabor Allen H., Kanakasabapathy Sivananda K., Kim Byeong Y., Lie Fee Li, Sieg Stuart A.
Принадлежит:

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least ...

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Номер записи: 45
22-06-2017 дата публикации

CONFINED EPTAXIAL GROWTH FOR CONTINUED PITCH SCALING

Номер: US20170178976A1
Автор: Sivananda K. Kanakasabapathy, Balasubramanian Pranatharthiharan, KANAKASABAPATHY SIVANANDA K, PRANATHARTHIHARAN BALASUBRAMANIAN, Kanakasabapathy Sivananda K., Pranatharthiharan Balasubramanian
Принадлежит:

A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on the substrate, each including a gate, a hard mask and an oxide layer. A dielectric spacer layer is deposited. A sacrificial fill material is deposited on the finFET device and planarized. A second hard mask is deposited, a trench area is patterned in the hard mask parallel to the first and second semiconductor fins, and the sacrificial fill material is anisotropically etched to create a trench. A dielectric wall is formed in the trench and the second hard mask and sacrificial fill material are removed. 1. A CMOS transistor comprising:a first transistor comprising a plurality of first semiconductor fins patterned on a substrate, and a first transistor active area,a first epitaxial layer on the first transistor,a second transistor comprising a plurality of second semiconductor fins patterned on a substrate and a second transistor active area,a second epitaxial layer on the second transistor,at least two gate stacks arranged over channel regions of the first and second semiconductor fins, anda dielectric wall having four vertical surfaces positioned in between the first transistor active area and the second transistor active area and extending between two of the at least two gate stacks, wherein the dielectric wall contacts each of the at least two gate stacks with one of the vertical surfaces,wherein the first epitaxial layer is confined to the first transistor by the dielectric wall.2. The CMOS transistor according to claim 1 , wherein the dielectric wall is substantially perpendicular to the gate.3. The CMOS transistor according to claim 1 , wherein the first transistor is an nFET transistor and the second transistor is a pFET transistor.4. The CMOS transistor according to claim 1 , wherein the first epitaxial layer is adjacent to the dielectric wall of the first transistor.5. The CMOS transistor according to ...

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Номер записи: 46
03-04-2018 дата публикации

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

Номер: US0009935015B1
Автор: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu, BI ZHENXING, CANAPERI DONALD F, DEVARAJAN THAMARAI S, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, XU PENG, Bi Zhenxing, Canaperi Donald F., Devarajan Thamarai S., Kanakasabapathy Sivananda K., Lie Fee Li, Xu Peng
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

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Номер записи: 47
27-02-2018 дата публикации

Replacement metal gate stack for diffusion prevention

Номер: US0009905665B2
Автор: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, ANDO TAKASHI, FALTERMEIER JOHNATHAN E, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Ando Takashi, Faltermeier Johnathan E., Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит: International Business Machines Corporation, IBM

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

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Номер записи: 48
21-02-2017 дата публикации

Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture

Номер: US0009576096B2
Автор: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang, CHAN KEVIN K, KANAKASABAPATHY SIVANANDA K, KHAN BABAR A, KOBAYASHI MASAHARU, LEOBANDUNG EFFENDI, STANDAERT THEODORUS E, WANG XINHUI, Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, Standaert Theodorus E., Wang Xinhui
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

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Номер записи: 49
15-06-2017 дата публикации

METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS

Номер: US20170170171A1
Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Alexander Reznicek, JAGANNATHAN HEMANTH, KANAKASABAPATHY SIVANANDA K, REZNICEK ALEXANDER, Jagannathan Hemanth, Kanakasabapathy Sivananda K., Reznicek Alexander
Принадлежит:

A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin. 1. A method for forming an integrated circuit , the method comprising the steps of:receiving a fin with a dummy gate passing thereover;removing the dummy gate to form a space over the fin;placing a temporary layer into the space;causing an element from the temporary layer to pass into a portion of the fin to form a modified fin portion;removing the temporary layer; andetching away at least part of the modified fin portion to form a gap in the fin.2. The method of claim 1 , wherein a width of the gap is about equal to a width of the dummy gate.3. The method of claim 1 , further comprising the step of forming a mask with an opening overlying the space.4. The method of claim 3 , wherein the step of placing the temporary layer is performed with the mask in place.5. The method of claim 3 , wherein the step of causing an element from the temporary layer to pass into the portion of the fin is performed with the mask in place.6. The method of claim 3 , wherein the step of removing the temporary layer is performed with the mask in place.7. The method of claim 1 , wherein the dummy gate comprises polysilicon.8. The method of claim 7 , wherein the space is bordered on two sides by sidewall spacers.9. The method of claim 8 , wherein the sidewall spacers comprise at least one of siliconborocarbonitride claim 8 , siliconoxycarbonitride claim 8 , and siliconoxycarbide.10. The method of claim 1 , wherein:the fin comprises silicon; andthe temporary layer comprises germanium.11. The method of claim 1 , wherein ...

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Номер записи: 50
06-03-2018 дата публикации

Self aligned conductive lines

Номер: US0009911647B2
Автор: Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, DESILVA ANUJA E, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE A, Burns Sean D., Clevenger Lawrence A., DeSilva Anuja E., Felix Nelson M., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

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Номер записи: 51
11-07-2017 дата публикации

Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation

Номер: US0009704860B1
Автор: Karthik Balakrishnan, Keith E. Fogel, Sivananda K. Kanakasabapathy, Alexander Reznicek, BALAKRISHNAN KARTHIK, FOGEL KEITH E, KANAKASABAPATHY SIVANANDA K, REZNICEK ALEXANDER, Balakrishnan Karthik, Fogel Keith E., Kanakasabapathy Sivananda K., Reznicek Alexander
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

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Номер записи: 52
06-10-2016 дата публикации

STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES

Номер: US20160293493A1
Автор: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит:

A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

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Номер записи: 53
27-04-2017 дата публикации

CONFORMAL DOPING FOR PUNCH THROUGH STOPPER IN FIN FIELD EFFECT TRANSISTOR DEVICES

Номер: US20170117365A1
Автор: Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie, Tenko Yamashita, BU HUIMING, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, YAMASHITA TENKO, Bu Huiming, Kanakasabapathy Sivananda K., Lie Fee Li, Yamashita Tenko
Принадлежит:

A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures. 1. A method of forming a semiconductor device comprising:forming a spacer of a dielectric material on sidewalls of fin structures;exposing a portion of the fin structures underlying the spacer of the dielectric material; anddoping the exposed portion of the fin structures underlying the spacer with a dopant having a first conductivity type to form a punch through stop region.2. The method of claim 1 , wherein the spacer of said dielectric material is composed of a nitride.3. The method of further comprising a hard mask present on an upper surface of the fin structures.4. The method of claim 1 , wherein said forming the spacer of the dielectric material comprises depositing a conformal dielectric layer on the fin structures claim 1 , and anisotropically etching the conformal dielectric layer to remove horizontal portions that are overlying the dielectric isolation regions.5. The method of claim 1 , wherein said exposing said portion of the fin structures comprises recessing dielectric isolation regions to expose a portion of the fin structures underlying the spacer comprises an etch process that is selective to the spacer.6. The method of claim 5 , wherein the etch process that is selective to the spacer is isotropic.7. The method of claim 1 , wherein said doping the exposed portion of the fin structures underlying the spacer comprises gas ...

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Номер записи: 54
01-08-2017 дата публикации

Cutting fins and gates in CMOS devices

Номер: US0009721848B1
Автор: Huiming Bu, Kangguo Cheng, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy, Gauri Karve, Balasubramanian S. Pranatharthiharan, Stuart A. Sieg, John R. Sporre, Gen Tsutsui, Rajasekhar Venigalla, Huimei Zhou, BU HUIMING, CHENG KANGGUO, GREENE ANDREW M, GUO DECHAO, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, PRANATHARTHIHARAN BALASUBRAMANIAN S, SIEG STUART A, SPORRE JOHN R, TSUTSUI GEN, VENIGALLA RAJASEKHAR, ZHOU HUIMEI, Bu Huiming, Cheng Kangguo, Greene Andrew M., Guo Dechao, Kanakasabapathy Sivananda K., Karve Gauri, Pranatharthiharan Balasubramanian S., Sieg Stuart A., Sporre John R., Tsutsui Gen, Venigalla Rajasekhar, Zhou Huimei
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

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Номер записи: 55
30-01-2018 дата публикации

Preventing strained fin relaxation

Номер: US0009881937B2
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

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Номер записи: 56
24-10-2017 дата публикации

Application of titanium-oxide as a patterning hardmask

Номер: US0009799534B1
Автор: Abraham Arceo de la Pena, Ekmini A. De Silva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Indira P. Seshadri, ARCEO DE LA PENA ABRAHAM, DE SILVA EKMINI A, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, SESHADRI INDIRA P, Arceo de la Pena Abraham, De Silva Ekmini A., Felix Nelson M., Kanakasabapathy Sivananda K., Seshadri Indira P.
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

An organic planarization layer (OPL) is formed above a functional layer located on a substrate. A titanium-oxide layer is formed above the OPL, wherein forming the titanium-oxide layer comprises titanium, oxide, carbon, and nitrogen. A photoresist layer is patterned above a first portion of the titanium-oxide layer. A second portion of the titanium-oxide layer is removed using a wet stripping technique. The photoresist layer and the OPL are removed using a dry etch technique, wherein the first portion of the titanium-oxide layer remains over a remaining portion of the OPL. The first portion of the titanium-oxide layer and the functional layer are removed using the wet stripping technique. The remaining portion of the OPL is removed using a dry stripping technique.

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Номер записи: 57
03-01-2017 дата публикации

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Номер: US0009536791B2
Автор: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

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Номер записи: 58
02-02-2017 дата публикации

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

Номер: US20170033103A1
Автор: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin, CHENG KANGGUO, HE HONG, KANAKASABAPATHY SIVANANDA K, TSENG CHIAHSUN, YIN YUNPENG, Cheng Kangguo, He Hong, Kanakasabapathy Sivananda K., Tseng Chiahsun, Yin Yunpeng
Принадлежит: International Business Machines Corp

A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

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Номер записи: 59
06-06-2017 дата публикации

Gate cutting for a vertical transistor device

Номер: US0009673199B1
Автор: Brent A. Anderson, Sivananda K. Kanakasabapathy, Stuart A. Sieg, John R. Sporre, Junli Wang, ANDERSON BRENT A, KANAKASABAPATHY SIVANANDA K, SIEG STUART A, SPORRE JOHN R, WANG JUNLI, Anderson Brent A., Kanakasabapathy Sivananda K., Sieg Stuart A., Sporre John R., Wang Junli
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of gate cutting for a device with multiple vertical transistors is provided. The method includes memorizing an initial structure of the device to identify a location for a gate strap to connect a portion of the multiple vertical transistors, building a bilayer hard mask over the device with a photoresist (PR) opening at the location, removing successive layers of the bilayer hard mask to identify first and second sections of the device based on a position of the PR opening and removing remaining layers of the bilayer hard mask and the first section of the device while preserving the second section of the device to form the gate strap.

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Номер записи: 60
18-10-2016 дата публикации

Directional chemical oxide etch technique

Номер: US0009472415B2
Автор: Emre Alptekin, Sivananda K. Kanakasabapathy, Ahmet S. Ozcan, Viraj Y. Sardesai, Cung D. Tran, ALPTEKIN EMRE, KANAKASABAPATHY SIVANANDA K, OZCAN AHMET S, SARDESAI VIRAJ Y, TRAN CUNG D, Alptekin Emre, Kanakasabapathy Sivananda K., Ozcan Ahmet S., Sardesai Viraj Y., Tran Cung D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench.

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Номер записи: 61
16-05-2017 дата публикации

Replacement metal gate including dielectric gate material

Номер: US0009653573B2
Автор: Linus Jang, Sivananda K. Kanakasabapathy, Sanjay C. Mehta, Soon-Cheon Seo, Raghavasimhan Sreenivasan, JANG LINUS, KANAKASABAPATHY SIVANANDA K, MEHTA SANJAY C, SEO SOON-CHEON, SREENIVASAN RAGHAVASIMHAN, Jang Linus, Kanakasabapathy Sivananda K., Mehta Sanjay C., Seo Soon-Cheon, Sreenivasan Raghavasimhan
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., IBM, GLOBALFOUNDRIES INC, International Business Machines Corporation, GLOBALFOUNDRIES Inc.

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

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Номер записи: 62
27-04-2017 дата публикации

PREVENTING STRAINED FIN RELAXATION

Номер: US20170117300A1
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит:

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion. 1. A semiconductor structure comprising:a first strained fin portion and a second strained fin portion upon a multilayered substrate;a pair of inactive inner gate structures upon the multilayered substrate and upon respective strained fin portions, wherein the first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures, and;spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces.2. The semiconductor structure of claim 1 , wherein the spacer formed upon the first strained fin portion and the second strained fin portion end surfaces limit relaxation of the first strained fin portion and the second strained fin portion.3. The semiconductor structure of claim 1 , wherein the spacer formed upon the first strained fin portion and the second strained fin portion end surfaces limits shorting between the first strained fin portion and the second strained fin portion.4. The semiconductor ...

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Номер записи: 63
03-01-2017 дата публикации

Enabling large feature alignment marks with sidewall image transfer patterning

Номер: US0009536744B1
Автор: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan, CHENG KANGGUO, KANAKASABAPATHY SIVANANDA K, LIE FEE LI, MILLER ERIC R, SHEARER JEFFREY C, SPORRE JOHN R, TEEHAN SEAN, Cheng Kangguo, Kanakasabapathy Sivananda K., Lie Fee Li, Miller Eric R., Shearer Jeffrey C., Sporre John R., Teehan Sean
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.

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Номер записи: 64
08-08-2017 дата публикации

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Номер: US0009728462B2
Автор: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita, FAN SU CHEN, KANAKASABAPATHY SIVANANDA K, OK INJO, YAMASHITA TENKO, Fan Su Chen, Kanakasabapathy Sivananda K., Ok Injo, Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

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Номер записи: 65
07-03-2017 дата публикации

Fin cut enabling single diffusion breaks

Номер: US0009589845B1
Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Vamsi K. Paruchuri, Alexander Reznicek, JAGANNATHAN HEMANTH, KANAKASABAPATHY SIVANANDA K, PARUCHURI VAMSI K, REZNICEK ALEXANDER, Jagannathan Hemanth, Kanakasabapathy Sivananda K., Paruchuri Vamsi K., Reznicek Alexander
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A dummy gate is removed from a finned structure to expose the top regions of the fins, the bottom fin regions being within a shallow trench isolation region. Selective vapor phase etching follows sequential ion implantation of the top and bottom fin regions to form a diffusion break cut region. The non-implanted regions of the substrate and the shallow trench isolation region remain substantially intact during each etching procedure. Double diffusion break cut regions are also enabled by the method.

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Номер записи: 66
27-04-2017 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20170117281A1
Автор: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang, CHAN KEVIN K, KANAKASABAPATHY SIVANANDA K, KHAN BABAR A, KOBAYASHI MASAHARU, LEOBANDUNG EFFENDI, STANDAERT THEODORUS E, WANG XINHUI, Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, Standaert Theodorus E., Wang Xinhui
Принадлежит:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure;a plurality of SOI fins each of which have ends in contact with respective fin structures of the deep trench capacitors; anda gate structure extending over the SOI fins,wherein the gate structure comprises a gate dielectric material, a semiconductor material over the gate dielectric material, and a capping material over the semiconductor material.2. The structure of claim 1 , further comprising an epitaxial material connecting the plurality of SOI fins with the respective fin structures of the deep trench capacitors.3. The structure of claim 2 , wherein the epitaxial material comprises silicon at a depth of about 15 nm to 25 nm to reduce strap resistance and to make a connection between the plurality of SOI fins and the respective fin structures of the deep trench capacitors.4. The structure of claim 1 , wherein the deep trench capacitors are eDRAM structures.5. The structure of claim 1 , wherein the SOI fins comprise portions of FinFETs.6. The structure of claim 1 , wherein the fin structures are polysilicon fins.7. The structure of claim 6 , wherein the polysilicon fins and the SOI fins are formed in contact with one another.8. The structure of claim 7 , further comprising an insulator material on the polysilicon fins claim 7 ...

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Номер записи: 67
15-06-2017 дата публикации

METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS

Номер: US20170170176A1
Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Alexander Reznicek, JAGANNATHAN HEMANTH, KANAKASABAPATHY SIVANANDA K, REZNICEK ALEXANDER, Jagannathan Hemanth, Kanakasabapathy Sivananda K., Reznicek Alexander
Принадлежит:

A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin. 1. An integrated circuit comprising:a gate;a first fin portion ending in a first terminus; anda second fin portion lined up with the first fin portion and ending in a second terminus;wherein the first terminus and the second terminus are separated by about a width of the gate.2. The integrated circuit of claim 1 , further comprising:a first sidewall spacer abutting the first terminus; anda second sidewall spacer abutting the second terminus. This patent application is a divisional of U.S. patent application Ser. No. 14/964,445 filed Dec. 9, 2015, entitled “METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS.” The complete disclosure of the aforementioned U.S. patent application Ser. No. 14/964,445 is expressly incorporated herein by reference in its entirety for all purposes.The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to methods for cutting fins in integrated circuits comprising FinFETs.Multi-gate field-effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a FinFET, a narrow channel feature (i.e., fin) is raised above the substrate and passes under a gate, which effectively wraps around the fin. The gate is thereby capacitively coupled to the top as well as the sides of the fin. So structured, very little leakage ...

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Номер записи: 68
18-10-2016 дата публикации

Confined eptaxial growth for continued pitch scaling

Номер: US0009472447B1
Автор: Sivananda K. Kanakasabapathy, Balasubramanian Pranatharthiharan, KANAKASABAPATHY SIVANANDA K, PRANATHARTHIHARAN BALASUBRAMANIAN, Kanakasabapathy Sivananda K., Pranatharthiharan Balasubramanian
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on the substrate, each including a gate, a hard mask and an oxide layer. A dielectric spacer layer is deposited. A sacrificial fill material is deposited on the finFET device and planarized. A second hard mask is deposited, a trench area is patterned in the hard mask parallel to the first and second semiconductor fins, and the sacrificial fill material is anisotropically etched to create a trench. A dielectric wall is formed in the trench and the second hard mask and sacrificial fill material are removed.

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Номер записи: 69
18-10-2016 дата публикации

Registration mark formation during sidewall image transfer process

Номер: US0009472506B2
Автор: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg, CONKLIN DAVID J, GABOR ALLEN H, KANAKASABAPATHY SIVANANDA K, KIM BYEONG Y, LIE FEE LI, SIEG STUART A, Conklin David J., Gabor Allen H., Kanakasabapathy Sivananda K., Kim Byeong Y., Lie Fee Li, Sieg Stuart A.
Принадлежит: International Business Machines Corporation, IBM

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least ...

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Номер записи: 70
08-06-2017 дата публикации

STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS

Номер: US20170162685A1
Автор: Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, SIEG STUART A, SPORRE JOHN R, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Sieg Stuart A., Sporre John R.
Принадлежит:

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. 1. A method of forming fin field-effect transistor with a looped fin comprising:forming a looped spacer around a first portion of a mandrel on an upper surface of a substrate;wherein the looped spacer is adjacent to a first sidewall of the first portion of the mandrel, an inner edge of the first portion of the mandrel, and a second sidewall of the first portion of the mandrel;removing the first portion of the mandrel;removing an exposed portion of the substrate, wherein the removing the exposed portion of the substrate forms the looped fin below the looped spacer;removing the looped spacer; andforming a gate extending in a first direction on the upper surface of the substrate and on a curved portion of the looped fin, wherein at least a portion of the curved portion of the loop fin is under the gate and extends in the first direction.2. The method of claim 1 , further comprising:forming a confining layer on the upper surface of the substrate parallel to at least a portion of the curved portion of the looped fin.3. The method of claim 1 , further comprising:forming another gate on the ...

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Номер записи: 71
23-02-2017 дата публикации

STRAINED FINFET DEVICE FABRICATION

Номер: US20170054002A1
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит:

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin. 1. A method for forming a fin on a substrate , the method comprising:patterning and etching a layer of a first semiconductor material to define a strained fin;depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the strain in the strained fin;etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin;etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment;depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin; andetching to remove a portion of the second semiconductor material to define a dummy gate stack over the first segment of the fin that defines a channel region on the fin.2. The method of claim 1 , wherein the first semiconductor material includes silicon germanium.3. The method of claim 1 , wherein the second semiconductor material includes amorphous silicon.4. The method of claim 1 , wherein the layer of the first semiconductor material is arranged on an insulator layer of a substrate.5. The method of claim 1 , wherein the fin has a longitudinal length that is greater than a width of the fin.6. The ...

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Номер записи: 72
03-10-2017 дата публикации

Method and structure for cut material selection

Номер: US0009779944B1
Автор: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier, BURNS SEAN D, CLEVENGER LAWRENCE A, COLBURN MATTHEW E, FELIX NELSON M, KANAKASABAPATHY SIVANANDA K, MIGNOT YANN A M, PENNY CHRISTOPHER J, QUON ROGER A, SAULNIER NICOLE A, Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Felix Nelson M., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole A.
Принадлежит: International Business Machines Corporation, IBM

A method for manufacturing a semiconductor device includes forming a plurality of mandrels on a dielectric layer, conformally depositing a spacer layer on the plurality of mandrels, removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels, removing the at least one of the plurality of mandrels to create at least one opening, and filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer.

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Номер записи: 73
31-10-2017 дата публикации

Strained finFET device fabrication

Номер: US0009805992B2
Автор: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LIE FEE LI, SIEG STUART A, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Lie Fee Li, Sieg Stuart A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

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Номер записи: 74
26-01-2012 дата публикации

STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20120018730A1
Автор: Jagannathan Hemanth, Kanakasabapathy Sivananda K., Mehta Sanjay
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. 1. A method of fabricating a fully depleted non-planar semiconductor structure comprising:forming a plurality of parallel oriented semiconducting fins on a surface of a semiconductor substrate, wherein a gate stack is located on a portion of each of the semiconductor fins;forming at least one liner on at least an upper surface of the gate stack, wherein the at least one liner encapsulating underlying portions of each of the semiconductor fins;performing an amorphizing ion implantation process, wherein portions of each of the semiconductor fins adjacent to the gate stack have a disoriented crystal structure after performing the amorphizing ion implantation process;forming at least one stress inducing liner atop the at least one liner, wherein the at least one stress inducing liner imparts a stress to a channel region of each of the semiconductor fins that is located beneath the gate stack;performing a stress latching annealing, wherein the stress imparted to the channel region of each semiconductor fins is permanently transferred to the channel region of each ...

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Номер записи: 75
09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1
Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

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Номер записи: 76
16-02-2012 дата публикации

Differential stoichiometries by infusion thru gcib for multiple work function metal gate cmos

Номер: US20120037999A1
Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices.

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Номер записи: 77
22-03-2012 дата публикации

Structure for nano-scale metallization and method for fabricating same

Номер: US20120068346A1
Автор: Charles W. Koburger, III, Chih-Chao Yang, David V. Horak, Elbert E. Huang, Shom Ponoth, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

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Номер записи: 78
19-07-2012 дата публикации

Methods for Forming Field Effect Transistor Devices With Protective Spacers

Номер: US20120181613A1
Автор: Basker Veeraraghavan S., Furukawa Toshiharu, Holmes Steven J., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer. 1. A method for forming a field effect transistor device , the method comprising:forming a first gate stack and a second gate stack on a substrate;depositing a first photoresist material over the second gate stack and a portion of the substrate;implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack;depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material;removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region; andremoving the first photoresist material.2. The method of claim 1 , wherein the method includes removing the first spacer following the removal of the first photoresist material.3. The method of claim 1 , wherein the method further includes:depositing a second photoresist material over the first gate stack and a portion of the substrate following the removal of the first spacer;implanting ions in exposed regions of the substrate to define a second ...

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Номер записи: 79
08-11-2012 дата публикации

Spacer as hard mask scheme for in-situ doping in cmos finfets

Номер: US20120280250A1
Автор: Bruce B. Doris, Hemant Adhikari, Johnathan E. Faltermeier, Kangguo Cheng, Sivananda K. Kanakasabapathy, Veeraraghavan S. Basker
Принадлежит: Globalfoundries Inc, International Business Machines Corp

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

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Номер записи: 80
29-11-2012 дата публикации

SELF ALIGNING VIA PATTERNING

Номер: US20120302057A1
Автор: Arnold John Christopher, Burns Sean D., Kanakasabapathy Sivananda K., Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch. 1. A method for patterning a self-aligned via in a dielectric , the method comprising the steps of:forming a hard mask on top of a dielectric;forming a first trench within the hard mask, wherein the first trench extends partially through a depth of the hard mask;forming a second trench within the hard mask, wherein the second trench intersects at least a portion of the first trench, and wherein the intersection of the first and second trench creates a hole pattern extending through the depth of the hard mask to expose a first area of the dielectric;etching the exposed first area of the dielectric to create a via hole extending into the dielectric;exposing a second area of the dielectric by re-etching the first trench to extend through the depth of the hard mask, wherein the exposed second area of the dielectric includes the via hole;etching the exposed area of the dielectric corresponding to the first trench to create a wiring path in the dielectric, wherein the wiring path extends partially through a depth of the dielectric and wherein the wiring path intersects the via hole; anddepositing a ...

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Номер записи: 81
27-12-2012 дата публикации

METAL SEMICONDUCTOR ALLOY STRUCTURE FOR LOW CONTACT RESISTANCE

Номер: US20120326241A1
Автор: HARAN BALASUBRAMANIAN S., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via. 1. A semiconductor structure comprising:a trench located in a semiconductor material region in a semiconductor substrate;a metal semiconductor alloy region located within said trench; anda contact via structure including a lower contact via portion that is located within said metal semiconductor alloy region and laterally spaced from said semiconductor material region by said metal semiconductor alloy region.2. The semiconductor structure of claim 1 , wherein an entirety of said metal semiconductor alloy region is of integral construction and includes an upper metal semiconductor alloy portion and a lower metal semiconductor alloy portion claim 1 , wherein said upper metal semiconductor alloy portion laterally surrounds said lower contact via portion and said lower metal semiconductor alloy portion underlies said lower contact via portion.3. The semiconductor structure of claim 2 , wherein an inner sidewall and an outer sidewall of said upper metal semiconductor alloy portion are laterally spaced by a substantially constant width throughout ...

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Номер записи: 82
03-01-2013 дата публикации

FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION

Номер: US20130001749A1
Автор: ARNOLD JOHN C., Kanakasabapathy Sivananda K., Schmitz Stefan, Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask. 1. A method for formation of a fin field effect transistor (FinFET) device , the method comprising:forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer;etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; andetching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.2. The method of claim 1 , wherein the film stack further comprises:a buried oxide (BOX) layer located underneath the SOI layer;a thermal silicon oxide layer located on top of the SOI layer and underneath the metal hardmask layer;an amorphous carbon layer located on top of the metal hardmask layer; anda cap layer located on top of the amorphous carbon layer.3. The method of claim 2 , wherein the cap layer comprises silicon nitride.4. The method of claim 2 , wherein forming the mandrel mask and the FX mask comprises:etching the amorphous carbon layer to form a plurality of mandrels on the metal hardmask layer;depositing a sidewall image transfer (SIT) spacer layer over the plurality of mandrels and on the metal hardmask layer;performing etchback of the SIT spacer layer to expose top surfaces of the plurality of mandrels; andremoving the plurality of mandrels, wherein a portion of the SIT spacer layer that remains on the metal hardmask layer comprises the mandrel mask.5. The method of claim 4 , wherein the ...

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Номер записи: 83
03-01-2013 дата публикации

FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION

Номер: US20130001750A1
Автор: ARNOLD JOHN C., Kanakasabapathy Sivananda K., Schmitz Stefan, Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask. 1. A method for formation of a fin field effect transistor (FinFET) device , the method comprising:forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer;forming a large feature (FX) mask on the metal hardmask layer;etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer;etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.2. The method of claim 1 , wherein forming the mandrel mask comprises:forming a plurality of mandrels on the metal hardmask layer;depositing a sidewall image transfer (SIT) spacer layer over the plurality of mandrels and on the metal hardmask layer;performing etchback of the SIT spacer layer to expose top surfaces of the plurality of mandrels; andremoving the plurality of mandrels, wherein a portion of the SIT spacer layer that remains on the metal hardmask layer comprises the mandrel mask.3. The method of claim 2 , wherein the SIT spacer layer comprises one of silicon oxide and silicon nitride claim 2 , and is deposited by conformal deposition.4. The method of claim 2 , wherein the FX mask is formed on the metal hardmask layer after the plurality of mandrels are removed.5. The method of claim 2 , wherein the FX mask is formed on the SIT spacer layer before etchback of the SIT spacer layer is performed such that a portion of the SIT spacer layer ...

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Номер записи: 84
17-01-2013 дата публикации

LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI

Номер: US20130015509A1
Автор: HARAN BALASUBRAMANIAN S., Jagannathan Hemanth, Kanakasabapathy Sivananda K., Mehta Sanjay
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions. 1. A method of forming a semiconductor structure comprising:forming a gate structure including at least a gate dielectric, a gate electrode, and a first gate spacer on a semiconductor substrate, wherein outer sidewalls of said first gate spacer is vertically coincident with sidewalls of said gate dielectric;forming raised epitaxial semiconductor portions contacting said sidewalls of said gate dielectric on a semiconductor layer in said semiconductor substrate;forming a disposable gate spacer on said first gate spacer and over peripheral regions of said raised epitaxial semiconductor portions;forming raised source and drain regions on said raised epitaxial semiconductor portions;removing said disposable gate spacer; andforming source and drain extension regions by implanting electrical dopants through cavities between said gate structure and said raised source and drain regions and into said semiconductor layer and said raised epitaxial semiconductor portions.2. The method of ...

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Номер записи: 85
17-01-2013 дата публикации

LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI

Номер: US20130015512A1
Автор: HARAN BALASUBRAMANIAN S., Jagannathan Hemanth, Kanakasabapathy Sivananda K., Mehta Sanjay
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

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Номер записи: 86
24-01-2013 дата публикации

Borderless Contacts in Semiconductor Devices

Номер: US20130020615A1
Автор: David Horak, Sivananda K. Kanakasabapathy, Su Chen Fan
Принадлежит: International Business Machines Corp

A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

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Номер записи: 87
24-01-2013 дата публикации

Borderless Contacts in Semiconductor Devices

Номер: US20130023115A1
Автор: Fan Su Chen, Horak David V., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity. 1. A method comprising:depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate;removing portions of the dummy fill material to expose portions of the substrate;forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack;removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material;depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack;removing portions of the dielectric layer to expose portions of the spacer material;removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer; anddepositing a conductive material in the at least one cavity.2. The method of claim 1 , wherein the dummy fill material includes an amorphous silicon material.3. The method of claim 1 , wherein the removing portions of the dummy fill material to expose portions of the substrate and the gate stack includes a photolithographic patterning and ...

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Номер записи: 88
21-03-2013 дата публикации

Method for Forming A Self-Aligned Hard Mask for Contact to a Tunnel Junction

Номер: US20130069183A1
Автор: Assefa Solomon, Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack. 1. A magnetic memory cell , comprising:a magnetic storage element formed on a semiconductor substrate; anda hard mask which is self-aligned with the magnetic storage element, the hard mask including: a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element; an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; and a photoresist layer formed on at least a portion of an upper surface of the ARC layer;wherein selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack.2. The magnetic memory cell of claim 1 , wherein the magnetic storage element comprises a magnetic tunnel junction (MTJ). This application is a Divisional of U.S. patent application Ser. No. 12/126,245, filed on May 23, 2008, the disclosure of which is fully incorporated herein by reference.The present invention is directed generally to semiconductors, and more particularly to ...

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Номер записи: 89
18-04-2013 дата публикации

Finfet parasitic capacitance reduction using air gap

Номер: US20130093019A1
Автор: Josephine B. Chang, Pranita Kulkarni, Sivananda K. Kanakasabapathy, Takashi Ando, Tenko Yamashita, Theodorus E. Standaert
Принадлежит: International Business Machines Corp

A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

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Номер записи: 90
18-04-2013 дата публикации

Finfet Parasitic Capacitance Reduction Using Air Gap

Номер: US20130095629A1
Автор: Ando Takashi, Chang Josephine B., Kanakasabapathy Sivananda K., Kulkarni Pranita, STANDAERT Theodorus E., Yamashita Tenko
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers. 1. A method to fabricate a transistor , comprising:forming over a substrate at least one electrically conductive channel between a source region and a drain region;forming a gate structure to be disposed over a portion of said at least one electrically conductive channel, said gate structure having a width and a length and a height defining two opposing sidewalls of said gate structure and being formed such that said at least one electrically conductive channel said passes through said sidewalls of said gate structure;forming spacers on said sidewalls of said gate structure;forming a layer of epitaxial silicon over said at least one electrically conductive channel;removing said spacers; andforming a dielectric layer to be disposed over said gate structure and portions of said electrically conductive channel that are external to said gate structure such that an air gap underlies said dielectric layer, said air gap being disposed adjacent to said sidewalls of said gate structure in a region formerly occupied by said spacers.2. The method of claim 1 , where said air gap has a width of about 5 nm to about 10 ...

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Номер записи: 91
04-07-2013 дата публикации

METHODS FOR FORMING FIELD EFFECT TRANSISTOR DEVICES WITH PROTECTIVE SPACERS

Номер: US20130168775A1
Автор: Basker Veeraraghavan S., Furukawa Toshiharu, Holmes Steven J., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A field effect transistor device prepared by a process including forming a first gate stack and a second gate stack on a substrate and depositing a first photoresist material over the second gate stack and a portion of the substrate. The process also includes implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack and depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material. The process further includes removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region and removing the first photoresist material. 1. A field effect transistor device prepared by a process comprising the steps of:forming a first gate stack and a second gate stack on a substrate;depositing a first photoresist material over the second gate stack and a portion of the substrate;implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack;depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material;removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region; andremoving the first photoresist material.2. The field effect transistor device of claim 1 , wherein the process further comprises removing the first spacer following the removal of the first photoresist material.3. The field effect transistor device of claim 1 , wherein the process further comprises:depositing a second photoresist material over the first gate stack and a portion of the substrate following the removal ...

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Номер записи: 92
25-07-2013 дата публикации

STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20130187234A1
Автор: Jagannathan Hemanth, Kanakasabapathy Sivananda K., Mehta Sanjay
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. 1. A method of forming a fully depleted non-planar semiconductor structure comprising:forming a plurality of parallel oriented semiconducting fins on a surface of a semiconductor substrate, wherein a gate stack is located on a portion of each of the semiconductor fins;forming a dielectric liner and a sacrificial dielectric liner around said gate stack and each of said semiconductor fins;performing an amorphizing ion implantation process, wherein portions of each of the semiconductor fins adjacent to the gate stack have a disoriented crystal structure after performing the amorphizing ion implantation process;forming at least one stress inducing liner atop the at least one liner, wherein the at least one stress inducing liner imparts a stress to a channel region of each of the semiconductor fins that is located beneath the gate stack;performing a stress latching annealing, wherein the stress imparted to the channel region of each semiconductor fins is permanently transferred to the channel region of each semiconductor fins, while simultaneously recrystallizing the disoriented crystal structure in portions of each ...

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Номер записи: 93
01-08-2013 дата публикации

STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME

Номер: US20130193579A1
Автор: Horak David V., Huang Elbert E., III Charles W., Kanakasabapathy Sivananda K., Koburger, Ponoth Shom, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography. 1. An interconnect structure comprising:at least two layers on a substrate, said layers comprising metal interconnect structure embedded within dielectric material, each of said layers having at least one via that extends to the top of said layer and at least one line formed along the bottom of said layer,wherein said at least one via of the lower of said layers extends into the upper of said layers.2. The interconnect structure of wherein said at least one via of said upper layer extends to said at least one via of the lower of said layers.3. The interconnect structure of further comprising an adhesion layer formed between said at least two layers.4. The interconnect structure of wherein a surface of said at least one line of said upper layer is in direct contact with an adhesion layer claim 1 , which adhesion layer is in direct contact with dielectric material of said lower layer.5. An interconnect structure comprising:at least two dielectric layers on a substrate, said at least two dielectric layers each comprising a metal via and a metal line within a single layer of dielectric material, wherein said metal line of each said at least two dielectric layers is along the bottom of its respective dielectric layer.6. The interconnect structure of wherein said metal via of the upper of said at least two dielectric layers consists essentially of tungsten.7. The interconnect structure of wherein said metal line of the upper of said at least two ...

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Номер записи: 94
22-08-2013 дата публикации

LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS

Номер: US20130214358A1
Автор: Jagannathan Hemanth, Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device. 1. A semiconductor structure comprising:a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, a buried insulator layer, and a top semiconductor layer;a U-shaped gate dielectric comprising a high dielectric constant (high-k) material including a dielectric metal oxide and having a dielectric constant greater than 3.9 and having a bottommost surface that is in contact with a first portion of a topmost surface of said top semiconductor layer;a raised source region in contact with a second portion of said topmost surface of said top semiconductor layer and with said high-k material at a lower portion of a first outer sidewall of said U-shaped gate dielectric;a raised drain region in contact with a third portion of said topmost surface of said top semiconductor layer and with said high-k material at a lower portion of a second outer sidewall of said U-shaped gate dielectric; anda dielectric gate spacer laterally contacting upper portions of said first and second outer sidewalls of said U-shaped gate dielectric.2. The semiconductor structure of claim 1 , wherein an interface between said raised source region and said dielectric gate ...

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Номер записи: 95
22-08-2013 дата публикации

LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS

Номер: US20130217190A1
Автор: Jagannathan Hemanth, Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device. 1. A method of forming a semiconductor structure , said method comprising:forming a disposable dielectric structure on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein all physically exposed surfaces of said disposable dielectric structure are dielectric surfaces;forming a raised source region and a raised drain region above a plane including an interface between said disposable dielectric structure and said SOI substrate by selective deposition of a semiconductor material on a semiconductor surface of said top semiconductor layer of said SOI substrate, wherein said deposited semiconductor material is in direct contact with a sidewall of said disposable dielectric structure;forming a dielectric gate spacer around said disposable dielectric structure over, and directly on, a portion of each of said raised source region and said raised drain region, while physically exposing another portion of each of said raised source region and said raised drain region;forming a planarization dielectric layer over said dielectric gate spacer;physically exposing a top surface of said disposable dielectric structure by planarizing ...

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Номер записи: 96
21-11-2013 дата публикации

Borderless Contact For An Aluminum-Containing Gate

Номер: US20130307033A1
Автор: Horak David V., Jagannathan Hemanth, Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES

An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. 1. A semiconductor structure comprising:a semiconductor device located on a semiconductor substrate, said semiconductor device including an aluminum-containing material portion;a contact level dielectric layer located over a topmost surface of said aluminum-containing material portion;a contact via structure extending through said contact level dielectric layer and in contact with a conductive material portion of said semiconductor device; anda dielectric aluminum compound portion in contact with said aluminum-containing material portion and said contact via structure.2. The semiconductor structure of claim 1 , further comprising a planarization dielectric layer located over a top surface of said semiconductor substrate and under said contact level dielectric layer and embedding said dielectric aluminum compound portion.3. The semiconductor structure of claim 1 , further comprising:a work function material layer in contact with a bottom surface and outer sidewalls of said aluminum-containing material portion; ...

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Номер записи: 97
21-11-2013 дата публикации

BORDERLESS CONTACT FOR AN ALUMINUM-CONTAINING GATE

Номер: US20130309852A1
Автор: Horak David V., Jagannathan Hemanth, Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. 1. A method of forming a semiconductor structure comprising:forming a semiconductor device including an aluminum-containing material portion on a semiconductor substrate;forming a contact level dielectric layer over a topmost surface of said aluminum-containing material portion;forming a contact via cavity by etching through said contact level dielectric layer and into a sub-portion of said aluminum-containing material portion; andconverting a surface portion of said aluminum-containing material portion into a dielectric aluminum compound portion.2. The method of claim 1 , further comprising:forming a planarization dielectric layer over said semiconductor substrate;forming a gate cavity within said planarization dielectric layer; anddepositing and planarizing an aluminum-containing material within a portion of said gate cavity, wherein a remaining portion of said aluminum-containing material after said planarizing constitutes said aluminum-containing material portion.3. The method of claim 2 , further ...

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Номер записи: 98
23-01-2014 дата публикации

IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER

Номер: US20140023834A1
Автор: Jung Ryan O., Kanakasabapathy Sivananda K., Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer. 1. A lithographic structure comprising:an underlying material layer located on a substrate;at least one mask layer comprising at least one of a dielectric material and a metallic material and located over said underlying material layer;an organic planarizing layer (OPL) located over said at least one mask layer;an antireflective coating (ARC) layer located on said OPL; anda patterned structure located over said ARC layer.2. The lithographic structure of claim 1 , wherein said patterned structure has a pattern of a plurality of parallel lines.3. The lithographic structure of claim 1 , wherein said patterned structure comprises a set of photoresist material portions having a lithographic minimum pitch.4. The lithographic structure of claim 1 , wherein said patterned structure comprises spacer structures having a sublithographic pitch.5. The lithographic structure of claim 4 , wherein each of said spacer structures has a same lateral width.6. The lithographic structure of claim 4 , further comprising mandrel structures claim 4 , wherein each of said spacer structures laterally contacts and laterally surrounds one of said mandrel structures.7. The lithographic structure of claim 6 , said mandrel ...

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Номер записи: 99
23-01-2014 дата публикации

METHOD OF SIMULTANEOUSLY FORMING MULTIPLE STRUCTURES HAVING DIFFERENT CRITICAL DIMENSIONS USING SIDEWALL TRANSFER

Номер: US20140024209A1
Автор: Jung Ryan O., Kanakasabapathy Sivananda K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer. 1. A method , comprising:forming a plurality of mandrels on a layer on a substrate;forming a first conformal layer on said mandrels and on a top surface of said layer;forming a second conformal layer on said first conformal layer;forming a block mask over a second less than whole portion of said plurality of mandrels;performing an isotropic etch to completely remove said second conformal layer from a first less than whole portion of said plurality of mandrels where said second conformal layer is not protected by said block mask;performing an anisotropic etch of said first and second conformal layers, said anisotropic etch forming first sidewall spacers on said first less than whole portion of said plurality mandrels, said first sidewall spacers comprise first regions of said first conformal layer and no regions of said second conformal layer and forming second sidewall spacers on said second less than whole portion of said plurality mandrels, said second sidewall spacers comprise second regions of said first conformal layer and regions of said second conformal layer on said second regions of said first conformal layer, said first and second sidewall spacers having different widths, a width of said first sidewall spacers based on a thickness of said first conformal layer on sidewalls of said first less than whole portion of said plurality of mandrels and a width of said second sidewall spacers based on a thickness of said first and second conformal layers on sidewalls of said second less than whole portion of said plurality of mandrels;removing said plurality of mandrels; andusing said first and second sidewall ...

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Номер записи: 100
23-01-2014 дата публикации

IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER

Номер: US20140024219A1
Автор: Jung Ryan O., Kanakasabapathy Sivananda K., Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer. 1. A method of patterning a structure comprising:forming an underlying material layer on a substrate;forming a stack of two mask layers comprising a dielectric material and a metallic material, respectively, over said underlying material layer;forming a first pattern in one of said two mask layers, wherein a patterned mask layer including said first pattern is formed by remaining portions of said one of said two mask layers, while another of said two mask layers remains unpatterned;forming an overlying structure including a second pattern over said patterned mask layer, wherein said second pattern includes at least one blocking area;removing portions of said patterned mask layer that do not underlie said blocking area, wherein remaining portions of said patterned mask layer include a composite pattern that is an intersection of said first pattern and said second pattern;applying a photoresist material directly on surfaces of said patterned mask layer and on surfaces of said another of said two mask layers that remains unpatterned;patterning said photoresist material to form at least one photoresist block portion having an additional pattern directly on a topmost surface of said another of said ...

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Номер записи: 101
13-03-2014 дата публикации

Semiconductor plural gate lengths

Номер: US20140070414A1
Автор: Hartig Michael J., Kanakasabapathy Sivananda K., Seo Soon-Cheon, SREENIVASAN Raghavasimhan
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask. 1. A method , comprising:forming a first gate structure with a first critical dimension, using a pattern of a mask; andforming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.2. The method of claim 1 , wherein the first gate structure comprises a first material and the second gate structure comprises a second material.3. The method of claim 2 , wherein the first material is amorphous silicon and the second material is polysilicon claim 2 , which have different etch rates.4. The method of claim 3 , wherein the first critical dimension is smaller than the second critical dimension due to different etch rates of the first material and the second material.5. The method of claim 4 , wherein the first critical dimension and the second critical dimension are gate lengths.6. The method of claim 1 , wherein the forming of the first gate structure and the second gate structure comprise:forming a first material on a substrate;blocking a first section of the first material on the substrate with a blocking material;subjecting an unmasked portion of the first material of a second section to a fabrication process to convert the first material to a second material, which has a different etch rate than the first material;forming a hardmask over the first material and the second material; andpatterning the hardmask and underlying first material and second material, by subjecting the hardmask, the first material and the second material to a same etching process.7. The method of claim 6 ...

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Номер записи: 102
04-01-2018 дата публикации

HIGH ASPECT RATIO GATES

Номер: US20180005833A1
Автор: Cheng Kangguo, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes forming a substrate and forming a gate material extending over a major surface of the substrate. The method further includes forming a trench extending through the gate material and into the substrate in a first direction, wherein the trench further extends through the gate material and the substrate in a second direction. The method further includes filling the trench with a fill material and forming individual gates from the gate material, wherein the individual gates extend along a third direction. 1. A method of forming a feature of a semiconductor device , the method comprising:forming a substrate;forming a feature material extending over a major surface of the substrate;forming a trench having at least one inner sidewall and extending through the feature material and into the substrate in a first direction, wherein the trench further extends through the feature material and the substrate in a second direction;filling the trench with a fill material such that the fill material extends along and physically couples to at least a portion of the at least one inner trench sidewall; andforming individual feature structures from the feature material;wherein each of the individual feature structures comprises:a first sidewall having a height (H) dimension extending along a first direction;a second sidewall formed from a portion of the at least one inner trench sidewall and having a thickness (T) dimension extending along a second direction; anda third sidewall having a length (L) dimension extending along a third direction;where T is less than H;wherein the fill material is physically coupled to the second sidewall of each of the individual feature structures.2. The method of claim 1 , wherein:the feature comprises a gate;the feature material comprises a gate material; andthe feature structure comprises a gate ...

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Номер записи: 103
04-01-2018 дата публикации

HIGH ASPECT RATIO GATES

Номер: US20180005834A1
Автор: Cheng Kangguo, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes forming a substrate and forming a gate material extending over a major surface of the substrate. The method further includes forming a trench extending through the gate material and into the substrate in a first direction, wherein the trench further extends through the gate material and the substrate in a second direction. The method further includes filling the trench with a fill material and forming individual gates from the gate material, wherein the individual gates extend along a third direction. 1. A semiconductor structure comprising:a first trench extending into a substrate in a first direction and a second direction, wherein the first direction is substantially perpendicular to the second direction;a first anchor formed in the first trench;a top portion of the first anchor extending above a major surface of the substrate; andindividual feature structures formed over the major surface of the substrate;wherein the individual features structures extend along a third direction;wherein each of the individual feature structures is physically coupled to the top portion f the first anchor.2. The structure of further comprising a second trench extending into the substrate in the first direction and the second direction.3. The structure of further comprising a second anchor formed in the second trench.4. The structure of further comprising a top portion of the second anchor extending above the major surface of the substrate.5. The structure of claim 4 , wherein each of the individual feature structures is physically coupled to the top portion of the second anchor.6. The structure of claim 5 , wherein a distance from the first trench to the second trench in the third direction matches a selected length dimension of each of the individual feature structures.7. The structure of claim 6 , wherein the length ...

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Номер записи: 104
04-01-2018 дата публикации

SELF-ALIGNED PATTERN FORMATION FOR A SEMICONDUCTOR DEVICE

Номер: US20180005875A1
Автор: Burns Sean D., Clevenger Lawrence A., Felix Nelson M., Kanakasabapathy Sivananda K., Penny Christopher J., Saulnier Nicole
Принадлежит:

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described. 1. A method of forming vias , the method comprising:providing a semiconductor wafer in which front end of line (FEOL) processing has been completed;depositing a hard mask on an optical planarization layer (OPL);forming a first layer with one or more mandrels on the hard mask;placing a non-mandrel material between each of the one or more mandrels;depositing an etch stop layer over the first layer of one or more mandrels;forming a second layer with one or more mandrels on the etch stop layer;etching the non-mandrel material that is not covered by the second layer; andremoving the one or more mandrels of the first layer and the one or more mandrels of the second layer down to the hard mark to form a pattern in the hard mask.2. The method of claim 1 , wherein each mandrel on the first layer of one or more mandrels is parallel to each other.3. The method of claim 2 , wherein each mandrel on the second layer of one or more mandrels is parallel to each other and orthogonal to each mandrel on the first layer of one or more mandrels.4. The method of further comprising:forming one or more vias based on the pattern in the hard mask.5. The method of claim 1 , wherein:forming the first layer of one or more mandrels on the hard mask further comprises forming spacers next to each of the one or more mandrels.6. The method of claim 5 , wherein:forming the second layer of one or more mandrels on the hard mask further comprises forming spacers next to each of the one or more mandrels.7. The method of claim 6 , wherein the spacers are formed of an oxide.8. The method of claim 1 , wherein the hard mask comprises ...

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Номер записи: 105
04-01-2018 дата публикации

SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY

Номер: US20180005885A1
Автор: Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Kanakasabapathy Sivananda K., Mignot Yann A.M., Penny Christopher J., Quon Roger A., SAULNIER Nicole A.
Принадлежит:

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material. 1. A semiconductor structure , comprising:a first hardmask on an insulator layer;a planarizing layer on the first hardmask;a second hardmask on a portion of the planarizing layer;a third hardmask on the planarizing layer and on the second hardmask;sacrificial mandrels on portions of the second hardmask and on portions of the third hardmask;a fourth hardmask on the sacrificial mandrels;spacer material on portions of the second hardmask and on portions of the third hardmask; anda mandrel including the spacer material on the third hardmask; andan organic planarizing layer on the third hardmask, on the spacer material, on the sacrificial mandrels, and on the mandrel including the spacer material.2. The semiconductor structure of claim 1 , wherein the second hardmask is on only a portion of the planarizing layer.3. The semiconductor structure of claim 2 , wherein the sacrificial mandrels are on only portions of the second hardmask and on only portions of the third hardmask.4. (canceled)5. The semiconductor structure of claim 1 , wherein the spacer material is on the third ...

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Номер записи: 106
04-01-2018 дата публикации

GATE CUT ON A VERTICAL FIELD EFFECT TRANSISTOR WITH A DEFINED-WIDTH INORGANIC MASK

Номер: US20180006150A1
Автор: ANDERSON Brent A., Kanakasabapathy Sivananda K., SHEARER JEFFREY C., SIEG STUART A., Sporre John R., Wang Junli
Принадлежит:

A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET. 1. A method of cutting a gate on a vertical field effect transistor (VFET) , comprising:depositing a memorization layer onto the VFET around a spacer on a sidewall of the field effect transistor;patterning a planarizing layer onto the memorization layer;patterning an anti-reflective coating layer onto the planarizing layer;patterning a photoresist layer onto the anti-reflective coating on ends of fins extending from a substrate in the VFET, wherein the planarizing layer, the anti-reflective coating layer, and the photoresist form a mask;etching the anti-reflective coating layer portion of the mask from the VFET;arc etching the planarizing layer and the photoresist layer portions of the mask from VFET;pulling down the spacer forming a void between gates on the VFET and exposing a hard mask on the fins;reactive ion etching the hard mask by pulling down on the hard mask and reactive ion etching vertically around the gates to form gates with a defined width mask; andremoving the memorization layer from the VFET.2. The method of claim 1 , wherein the depositing of the memorization layer is done ...

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Номер записи: 107
03-01-2019 дата публикации

UTILIZING MULTILAYER GATE SPACER TO REDUCE EROSION OF SEMICONDUCTOR FIN DURING SPACER PATTERNING

Номер: US20190006506A1
Автор: Greene Andrew M., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Miller Eric R., MONTANINI Pietro
Принадлежит:

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN). 1. A method for fabricating a semiconductor device , comprising:forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device; andforming a multilayer gate spacer on the dummy gate structure;wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer; andwherein forming the multilayer gate spacer on the dummy gate structure comprises:depositing a first conformal layer of dielectric material over the dummy gate structure and portions of the vertical semiconductor fin which extend from sidewalls of the dummy gate structure;depositing a second conformal layer of dielectric material over the first conformal layer of dielectric material;performing a first etch process to etch the second conformal layer of dielectric material selective to the first conformal layer of dielectric material to form the second dielectric layer of the multilayer gate spacer, wherein the first etch process results in (i) removing portions of the second conformal layer of dielectric material covering the portions of ...

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Номер записи: 108
22-01-2015 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20150021610A1
Автор: Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, STANDAERT Theodorus E., Wang Xinhui
Принадлежит:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure;a plurality of SOI fins each of which having ends in contact with respective fin structures of the deep trench capacitors;an insulator material on the fin structures of the plurality of deep trench capacitors; anda gate structure extending over the insulator material and the SOI fins.2. The structure of claim 1 , further comprising an epitaxial material connecting the plurality of SOI fins with the respective fin structures of the deep trench capacitors.3. The structure of claim 1 , wherein the deep trench capacitors are eDRAM structures.4. The structure of claim 1 , wherein the SOI fins comprise portions of FinFETs.5. The structure of claim 1 , wherein the fin structures are polysilicon fins.6. The structure of wherein the polysilicon fins and the SOI fins are formed in contact with one another.7. The structure of claim 6 , wherein the insulator layer is oxide material blanket deposited on the polysilicon fins.8. The structure of claim 6 , further comprising an epitaxial material over a connection between the polysilicon fins and the SOI fins.9. The structure of claim 8 , wherein the connection is provided by material of the polysilicon fins and semiconductor material of the SOI fins.10. The structure of claim 9 , wherein the ...

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Номер записи: 109
25-01-2018 дата публикации

ALIGNING CONDUCTIVE VIAS WITH TRENCHES

Номер: US20180025943A1
Автор: Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Kanakasabapathy Sivananda K., Mignot Yann A. M., Penny Christopher J., Quon Roger A., Saulnier Nicole
Принадлежит:

A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material. 1. A method for forming conductive contacts on a semiconductor wafer , the method comprising:forming a hardmask on an insulator layer, a planarizing layer on the hardmask and a layer of sacrificial mandrel material on the planarizing layer;removing portions of the layer of sacrificial mandrel material to expose portions of the planarizing layer and form a first sacrificial mandrel and a second sacrificial mandrel on the planarizing layer;depositing a layer of spacer material over the planarizing layer, the first sacrificial mandrel and the second sacrificial mandrel;depositing a first filler material over the layer of spacer material;patterning a first mask over the filler material;removing portions of the first filler material to expose a portion of the layer of spacer material over a portion of the first sacrificial mandrel and removing the mask;removing a portion of the layer of spacer material and an exposed portion of the first sacrificial mandrel to form a first cavity that exposes a portion of the planarizing layer;filling the first cavity with a ...

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Номер записи: 110
29-01-2015 дата публикации

TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER

Номер: US20150031201A1
Автор: Kanakasabapathy Sivananda K., Tseng Chiahsun, Xu Yongan, Yin Yunpeng
Принадлежит:

A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure. 1. A method comprising:forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask comprising a second hardmask layer above a first hardmask layer;removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask;forming a set of sidewall spacers above the tetra-layer hardmask defining a device pattern; andtransferring a portion of the device pattern into the substrate within the pattern region of the structure.2. The method of claim 1 , wherein forming the set of sidewall spacers above the tetra-layer hardmask defining the device pattern comprises:creating a mandrel, lithographically, from a photo-resist material;depositing a conformal layer of dielectric material covering the mandrel;performing a directional etch of the conformal layer of dielectric material forming the set of sidewall spacers; andremoving the mandrel.3. The method of claim 1 , wherein transferring the portion of the device pattern into the substrate within the pattern region of the structure comprises:transferring the portion of the device pattern into the first hardmask layer within the pattern region of the structure; andtransferring the portion of the device pattern from the first hardmask layer into the substrate within the pattern region of the structure.4. The method of claim 3 , wherein transferring the portion of the device pattern into the first ...

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Номер записи: 111
03-03-2022 дата публикации

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

Номер: US20220069118A1
Автор: Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer. 1. A method comprising:providing a substrate having thereon a layer of epitaxial channel material;patterning a hardmask above the layer of epitaxial channel material;performing a first etch to a first depth, using the hardmask as a mask, to form an upper portion of a fin, wherein the first depth extends beyond a bottom surface of the layer of epitaxial channel material;forming a liner over exposed surfaces of the upper portion of the fin;performing a second etch to a second depth, using the liner as a mask, to form a lower portion of the fin;removing the liner; andforming a gate dielectric disposed on exposed surfaces of the upper portion of the fin.2. The method of claim 1 , further comprising:oxidizing exposed surfaces of the lower portion of the fin prior to removing the liner.3. A method comprising:providing a substrate having thereon a layer of epitaxial channel material;patterning a hardmask above the layer of epitaxial channel material;performing a first etch, using the hardmask as a mask, to form an upper portion of a first fin and an upper portion of a second fin, the first fin adjacent to the second fin, the first etch extending past a bottom surface of the layer of epitaxial channel material;forming a liner over exposed surfaces of the upper portions of the first and second fins; ...

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Номер записи: 112
13-02-2020 дата публикации

Semiconductor structures with deep trench capacitor and methods of manufacture

Номер: US20200051984A1
Автор: Babar A. Khan, Effendi Leobandung, Kevin K. Chan, Masaharu Kobayashi, Sivananda K. Kanakasabapathy, Theodorus E. Standaert, Xinhui Wang
Принадлежит: International Business Machines Corp

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

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Номер записи: 113
01-03-2018 дата публикации

REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS

Номер: US20180061773A1
Автор: Conklin David J., Gabor Allen H., Kanakasabapathy Sivananda K., Kim Byeong Y., LIE Fee Li, SIEG STUART A.
Принадлежит:

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask. 1. A method of forming a registration mark , the method comprising:forming a plurality of mandrels over a hard mask over a semiconductor layer;forming a conformal spacer material covering a top and side of the mandrels and in between the mandrels;selecting at least one selected mandrel and forming a mask over the at least one selected mandrel;forming a spacer adjacent each of an uncovered group of the plurality of the mandrels that are uncovered by the mask;removing the uncovered group of mandrels leaving the spacers;removing the mask;a first etching to pattern the sub-lithographic structures into the hard mask, using the spacers as a pattern of the sub-lithographic structure; anda second etching to: form the sub-lithographic structures in the semiconductor layer using the patterned hard mask, and form the registration mark over the semiconductor layer using the at least one selected mandrel.2. The method of claim 1 , wherein the ...

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Номер записи: 114
01-03-2018 дата публикации

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

Номер: US20180061941A1
Автор: Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, LIE Fee Li, Liu Derrick, Seo Soon-Cheon, SIEG STUART A.
Принадлежит:

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. 1. A method of forming a semiconductor structure , the method comprising:forming a gate structure straddling a semiconductor fin;forming a dielectric material over the semiconductor fin and on sidewall surfaces of the gate structure;forming a patterned material stack over the dielectric material, the patterned material stack having an opening that exposes one side of the gate structure;cutting the semiconductor fin utilizing the patterned material stack and a portion of the dielectric material within the opening as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall; andforming outer gate spacers, wherein one of the outer gate spacers contains a lower sidewall portion that directly contacts the entirety of the exposed end wall of the semiconductor fin portion.2. The method of claim 1 , wherein a portion of the opening exposes a portion of the dielectric material over the semiconductor fin.3. The method of claim 2 , wherein the cutting the semiconductor fin includes etching the exposed portion of the dielectric material over the semiconductor fin to expose a topmost surface of the gate structure and to provide inner gate spacers.4. The method of claim 3 , wherein each of the inner gate spacers straddles over the surface of the semiconductor fin portion claim 3 , and wherein one of the inner gate spacers located in the opening has an outer edge that is vertically aligned to the end wall ...

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Номер записи: 115
01-03-2018 дата публикации

STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES

Номер: US20180061942A1
Автор: Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, LIE Fee Li, Liu Derrick, Seo Soon-Cheon, SIEG STUART A.
Принадлежит:

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion. 1. A method of forming a semiconductor structure , the method comprising:forming a gate structure straddling a portion of a semiconductor fin,providing a first set of gate spacers on opposing sidewalls of the gate structure and straddling another portion of the semiconductor fin;forming a sacrificial dielectric liner over the first set of gate spacers and the gate structure and straddling a remaining portion of the semiconductor fin;forming a patterned material stack having an opening;cutting the semiconductor fin utilizing the patterned material stack, a portion of sacrificial dielectric liner within the opening and one gate spacer of the first set of gate spacers as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall;performing a lateral etch to pull back the expose end wall of the semiconductor fin portion underneath or aligned to a sidewall of the one gate spacer of the first set of gate spacers within the opening; andforming a second set of gate spacers, wherein one gate spacer of the second set of gate spacers contains a lower portion that directly contacts the exposed end wall of the semiconductor fin portion.2. The method of claim 1 , wherein a portion of the opening exposes a portion of the sacrificial dielectric liner over the semiconductor fin.3. The method of claim 2 , wherein prior to cutting the semiconductor fin claim 2 , an etch is performed to remove the exposed ...

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Номер записи: 116
10-03-2016 дата публикации

SELF-ALIGNED QUADRUPLE PATTERNING PROCESS

Номер: US20160071771A1
Автор: Colburn Matthew E., Kanakasabapathy Sivananda K., LIE Fee Li, SIEG STUART A.
Принадлежит:

Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks. 1. A method of forming a mandrel structure comprising:forming a plurality of first mandrel structures comprising a neighboring pair of first mandrel structures on a surface of a substrate;forming an additive mask on facing sidewall surfaces of said neighboring pair of first mandrel structures and on said surface of said substrate that is located between said neighboring pair of first mandrel structures;forming a first spacer on said additive mask and exposed surfaces of each first mandrel structure and said exposed surfaces of said substrate;removing portions of each first spacer and said additive mask to provide providing a first set of second mandrel structures having a first width on said facing sidewall surfaces of said neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width that is less than said first width on non-facing sidewall surfaces of said neighboring pair of first mandrel structures;removing each first mandrel structure;forming a second spacer on a sidewall surface of said first and second sets of second mandrel ...

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Номер записи: 117
08-03-2018 дата публикации

PREVENTING STRAINED FIN RELAXATION

Номер: US20180069027A1
Автор: Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, LIE Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит:

A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin. 1. A semiconductor structure comprising:a strained fin upon a substrate;a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; anda spacer upon the sidewall of the gate and upon the fin end surface of the strained fin.2. The semiconductor structure of claim 1 , wherein the spacer limits relaxation of the strained fin.3. The semiconductor structure of claim 1 , wherein the gate is an inactive gate.4. The semiconductor structure claim 1 , wherein the gate is electrically inactive.5. The semiconductor structure of claim 4 , wherein the spacer prevents epitaxial nodule growth from the fin end surface.6. The semiconductor structure of claim 1 , wherein the substrate is a multilayered substrate.7. A wafer comprising:a strained fin upon a substrate;a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; anda spacer upon the sidewall of the gate and upon the fin end surface of the strained fin.8. The wafer of claim 1 , wherein the spacer limits relaxation of the strained fin.9. The wafer of claim 1 , wherein the gate is an inactive gate.10. The wafer claim 1 , wherein the gate is electrically inactive.11. The wafer of claim 1 , wherein the spacer prevents epitaxial nodule growth from the fin end surface.12. The wafer of claim 1 , wherein the substrate is a multilayered substrate.13. A semiconductor structure fabrication method comprising:forming a strained fin upon a substrate;forming a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; ...

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Номер записи: 118
05-03-2020 дата публикации

SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONS

Номер: US20200075336A1
Автор: Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Felix Nelson M., Kanakasabapathy Sivananda K., Penny Christopher J., Quon Roger A., SAULNIER Nicole A.
Принадлежит:

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures. 1. An etch method comprising:forming first spacer on sidewalls of a first mask that are present on a substrate, the first mask formed using a subtractive method;forming a second mask using an additive method between sidewalls of said first spacers that are not in contact with the first mask formed using the subtractive method;forming second spacers on sidewalls of an etch mask having a window that exposes a connecting portion of one of the first spacers in the etch window;removing the connecting portion of said one of the first spacers; andetching the substrate using a remaining portion of the first spacers as an etch mask, wherein an opening is formed from the space provided by said removing the connecting portion of the first spacer connects a first trench patterned by the first mask structure formed using the subtractive method and a second trench patterned by the second mask using the additive method.2. The etch method of claim 1 , wherein the first trench patterned by the first mask structure formed using the subtractive method and the second trench patterned by the second mask using the additive method are on a same lithographic level.3. The etch ...

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Номер записи: 119
12-06-2014 дата публикации

FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS

Номер: US20140162447A1
Автор: Edge Lisa F., Frank Martin M., HARAN BALASUBRAMANIAN S., INADA Atsuro, Kanakasabapathy Sivananda K., KNORR Andreas, Narayanan Vijay, Paruchuri Vamsi K., Seo Soon-Cheon
Принадлежит:

A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities. 1. A method for fabricating a field effect transistor device , the method comprising:patterning a fin on substrate;patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, wherein the gate stack includes a dielectric layer disposed over a channel region of the fin; a silicon material layer selected from the group consisting of amorphous silicon and polysilicon disposed over and in contact with the dielectric layer; a TaAN or TiAlN barrier layer disposed over and in contact with the silicon material layer; and a low resistivity metal layer formed of tungsten disposed over and in contact with the barrier layer, wherein the tungsten metal layer has a sheet resistivity of about 11 to about 15 ohm/square at a thickness of about 125 Angstroms;forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack;depositing a second insulator layer over portions of the fin and the protective barrier;performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the ...

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Номер записи: 120
22-03-2018 дата публикации

REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

Номер: US20180083117A1
Автор: Ando Takashi, Faltermeier Johnathan E., Fan Su Chen, Kanakasabapathy Sivananda K., OK Injo, Yamashita Tenko
Принадлежит:

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. 1. A semiconductor structure comprising:a gate structure formed above a substrate, the gate structure comprising:a metal gate above a conductive barrier, anda gate dielectric layer below the conductive barrier; anda capping layer above the gate structure, wherein the conductive barrier separates the capping layer from the gate dielectric layer.2. The semiconductor structure of claim 1 , wherein the gate structure comprises a length less than 20 nm.3. The semiconductor structure of claim 1 , wherein the conductive barrier comprises an n-type workfunction metal.4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.5. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a vertical portion and a horizontal portion claim 1 , the vertical portion of the gate dielectric layer having a height less than a height of the metal gate measured from a top surface of the substrate.6. The semiconductor structure of claim 5 , wherein the height of the vertical portion of the gate dielectric layer is within a range from 1 nm to ...

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Номер записи: 121
12-03-2020 дата публикации

Additive core subtractive liner for metal cut etch processes

Номер: US20200083349A1
Автор: Andrew M. Greene, David L. Rath, Indira P.V. Seshadri, Kisup Chung, Rajasekhar Venigalla, Ruqiang Bao, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner

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Номер записи: 122
12-03-2020 дата публикации

ADDITIVE CORE SUBTRACTIVE LINER FOR METAL CUT ETCH PROCESSES

Номер: US20200083350A1
Автор: Bao Ruqiang, Chung Kisup, Greene Andrew M., Kanakasabapathy Sivananda K., Rath David L., Seshadri Indira P.V., Venigalla Rajasekhar
Принадлежит:

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner 1. A method of forming contacts to an electrical device comprising:forming a metal liner from a first region of at least one source/drain region to a second region of at least one source/drain region;forming at least one dielectric layer over the first and second region;performing a metal cut to subtractively remove a portion of the metal liner between the first and second regions forming a tapered metal cut trench in the at least one dielectric layer;forming a dielectric fill in the metal cut trench; andforming electrically conductive contacts to the remaining portions of the metal liner on opposing sides of the dielectric fill.2. The method of claim 1 , wherein the electrically conductive contacts have a lesser width at their upper surface than at their base surface3. The method of claim 2 , wherein said subtractively remove comprises a wet etch.4. The method of claim 2 , wherein said taper comprises an angle ranging from 2° to 10°.5. The method of claim 2 , wherein said forming electrically conductive contacts to the remaining portions of the metal liner comprises removing the remaining portions of the at least one dielectric layer selective to the dielectric fill to provide openings to the remaining portions of the metal liner.6. The method of claim 5 , wherein said forming electrically ...

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Номер записи: 123
12-03-2020 дата публикации

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

Номер: US20200083364A1
Автор: Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer. 1. A semiconductor device , comprising: a top channel portion formed from a channel material;', 'a middle portion; and', 'a bottom substrate portion formed from a same material as an underlying substrate;, 'one or more fins, each fin comprisingan isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;an oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; anda gate dielectric, protruding into the space and in contact with the middle portion, formed over the one or more fins and comprising a portion formed from a material different from the oxide layer.2. The semiconductor device of claim 1 , comprising a plurality of such fins claim 1 , wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises a top channel portion formed from a second channel material.3. The semiconductor device of claim 2 , wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.4. ...

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Номер записи: 124
29-03-2018 дата публикации

HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES

Номер: US20180090367A1
Автор: Bi Zhenxing, Canaperi Donald F., Devarajan Thamarai S., Kanakasabapathy Sivananda K., LIE Fee Li, Xu Peng
Принадлежит:

A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers. 1. A semiconductor device having a uniform height across different fin densities , comprising:a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins; andone or more dielectric layers formed at a base of the fins and the isolation regions and having a uniform height across the fins and the isolation regions, the uniform height including a less than 2 nanometer difference across the one or more dielectric layers.2. The device as recited in claim 1 , wherein the one or more dielectric materials include a same dielectric material formed by a different process.3. The device as recited in claim 1 , wherein the one or more dielectric materials include different dielectric materials.4. The device as recited in claim 1 , further comprising a liner formed below the one or more dielectric materials.5. The device as recited in claim 1 , wherein a fin reveal depth includes a linear relationship with space between the fins.6. The device as recited in claim 1 , wherein a normalized fin reveal depth includes negligible variation over spacings from about 0 nm to about 1000 nm.7. The device as recited in claim 1 , wherein the uniform height includes a less than 1 nanometer difference across the one or more dielectric layers.8. A semiconductor device having a uniform height across different fin densities claim 1 , comprising:a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins;a liner formed ...

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Номер записи: 125
29-03-2018 дата публикации

HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES

Номер: US20180090384A1
Автор: Bi Zhenxing, Canaperi Donald F., Devarajan Thamarai S., Kanakasabapathy Sivananda K., LIE Fee Li, Xu Peng
Принадлежит:

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material. 1. A method for uniform fin reveal depth for semiconductor devices , comprising:dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches wherein the quasi-ALE process includes a plurality of gas and bias pulse cycles of depositing a polymer with embedded etchant and removing the polymer to release the etchant to remove the dielectric material; andcompensating for a lateral bias induced by the quasi-ALE process by isotropically etching the dielectric material.2. (canceled)3. The method as recited in claim 1 , wherein the quasi-ALE process laterally etches isolation regions without fins slower than dense fin regions claim 1 , and the isotropically etching reversely laterally etches the isolation regions faster than the dense fin regions.4. The method as recited in claim 1 , wherein isotropically etching includes a plasma free reactive cleaning or remote plasma etch.5. The method as recited in claim 1 , further comprising a plasma strip to remove a polymer collected from the quasi-ALE process.6. The method as recited in claim 5 , wherein the plasma strip includes NHor Oplasma.7. The method as recited in claim 1 , further comprising deglazing the dielectric material to remove footings formed by the dry etching at the base of the fins to achieve the depth uniformity across different fin pitches.8. A method for uniform fin reveal depth for semiconductor devices claim 1 , comprising:forming a liner over semiconductor fins and a substrate;forming one or more dielectric materials over the liner;dry etching ...

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Номер записи: 126
29-03-2018 дата публикации

HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES

Номер: US20180090385A1
Автор: Bi Zhenxing, Canaperi Donald F., Devarajan Thamarai S., Kanakasabapathy Sivananda K., LIE Fee Li, Xu Peng
Принадлежит:

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material. 1. A method for uniform fin reveal depth for semiconductor devices , comprising:dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches; andcompensating for a lateral bias induced by the quasi-ALE process by isotropically etching the dielectric material.2. The method as recited in claim 1 , wherein isotropically etching includes a plasma free reactive cleaning or remote plasma etch.3. The method as recited in claim 1 , further comprising a plasma strip to remove a polymer collected from the quasi-ALE process.4. The method as recited in claim 5 , wherein the plasma strip includes NHor Oplasma.5. The method as recited in claim 1 , further comprising deglazing the dielectric material to remove footings formed by the dry etching at the base of the fins to achieve the depth uniformity across different fin pitches.6. The method as recited in claim 1 , wherein the deglazing includes a HF acid etch.7. A method for uniform fin reveal depth for semiconductor devices claim 1 , comprising:forming a liner over semiconductor fins and a substrate;forming one or more dielectric materials over the liner;dry etching the one or more dielectric materials to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches and different material types or qualities;isotropically etching the one or more dielectric materials with a plasma free reactive cleaning or remote plasma etch to compensate for lateral bias induced by the quasi-ALE process; ...

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Номер записи: 127
29-03-2018 дата публикации

Forming a sacrificial liner for dual channel devices

Номер: US20180090599A1
Автор: Dechao Guo, Huiming Bu, Kangguo Cheng, Peng Xu, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.

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Номер записи: 128
29-03-2018 дата публикации

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

Номер: US20180090604A1
Автор: Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space. 1. A semiconductor device , comprising:one or more fins, each fin comprising:a top channel portion formed from a channel material; anda bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion;an isolation dielectric layer formed between and around the bottom substrate portion of the one or more finsan oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; anda gate dielectric formed over the one or more fins and in the space.2. The semiconductor device of claim 1 , comprising a plurality of such fins claim 1 , wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises a top channel portion formed from a second channel material.3. The semiconductor device of claim 2 , wherein the first channel material is silicon and wherein the second channel material is silicon germanium.4. The semiconductor device of claim 1 , wherein the top channel portion of each of the one or more fins has a width that is greater than a width of the bottom substrate portion of each respective ...

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Номер записи: 129
29-03-2018 дата публикации

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

Номер: US20180090606A1
Автор: Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space. 1. A semiconductor device , comprising: a top channel portion formed from a channel material; and', 'a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion;, 'one or more fins, each fin comprisingan isolation dielectric layer fowled between and around the bottom substrate portion of the one or more fins;an oxide layer formed between the bottom substrate portion of each fin and the isolation dielectric layer, wherein a space exists between a sidewall of at least a top portion of the oxide layer and an adjacent sidewall of the one or more fins; anda gate dielectric formed over the one or more fins and in the space.2. The semiconductor device of claim 1 , comprising a plurality of such fins claim 1 , wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises a top channel portion formed from a second channel material.3. The semiconductor device of claim 2 , wherein the first channel material is silicon and wherein the second channel material is silicon germanium.4. The semiconductor device of claim 1 , wherein a top channel portion of each of the one or more fins has a width that is lower than a width of the bottom substrate portion of each respective fin.5. The ...

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Номер записи: 130
19-03-2020 дата публикации

Self-aligned pattern formation for a semiconductor device

Номер: US20200090985A1
Автор: Christopher J. Penny, Lawrence A. Clevenger, Nelson M. Felix, Nicole Saulnier, Sean D. Burns, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

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Номер записи: 131
19-03-2020 дата публикации

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

Номер: US20200091336A1
Автор: Bu Huiming, Cheng Kangguo, Guo Dechao, Kanakasabapathy Sivananda K., Xu Peng
Принадлежит:

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion. 1. A semiconductor device , comprising: a top channel portion formed from a channel material; and', 'a bottom substrate portion formed from a same material as an underlying substrate;, 'one or more fins, each fin comprisingan isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;a single oxide layer formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer; anda gate dielectric formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.2. The semiconductor device of claim 1 , comprising a plurality of such fins claim 1 , wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises a top channel portion formed from a second channel material.3. The semiconductor device of claim 2 , wherein the first channel material is silicon and wherein the second channel material is ...

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Номер записи: 132
05-04-2018 дата публикации

EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION

Номер: US20180096997A1
Автор: Balakrishnan Karthik, Fogel Keith E., Kanakasabapathy Sivananda K., Reznicek Alexander
Принадлежит:

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures. 1. A semiconductor device comprising:a plurality of fin structures having a uniform strain extending from edge to edge of each fin structure in said plurality of fin structures;an epitaxial oxide present in a gate cut opening present between edges of said plurality of fin structures;a gate structure present on a channel region of the fin structures having the uniform strain; andsource and drain regions formed on opposing sides of the channel region.2. The semiconductor device of claim 1 , wherein the fin structures are present on a substrate having a different lattice dimension than a lattice dimension for the fin structures.3. The semiconductor device of claim 1 , wherein the fin structures comprise silicon claim 1 , germanium claim 1 , silicon germanium or a combination thereof claim 1 ,4. The semiconductor device of claim 1 , wherein the epitaxial oxide is a rare earth oxide composition.5. The semiconductor device of claim 1 , wherein the epitaxial oxide is selected from the group consisting of cerium oxide (CeO) claim 1 , lanthanum oxide (LaO) claim 1 , yttrium oxide (YO) claim 1 , gadolinium oxide (GdO) claim 1 , europium oxide (EuO) claim 1 , terbium oxide (TbO) and combinations thereof.6. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 133
05-04-2018 дата публикации

GATE CUT ON A VERTICAL FIELD EFFECT TRANSISTOR WITH A DEFINED-WIDTH INORGANIC MASK

Номер: US20180097107A1
Автор: ANDERSON Brent A., Kanakasabapathy Sivananda K., SHEARER JEFFREY C., SIEG STUART A., Sporre John R., Wang Junli
Принадлежит:

A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET. 1. A vertical field effect transistor (VFET) comprising:a first spacer disposed on a silicon substrate;a fin extending from the substrate through the spacer;an oxide layer disposed on the fin;a hard mask layer disposed on the oxide layer; anda second spacer with a defined width disposed around the fin, oxide layer and hard mask layer forming a gate around the fin.2. The VFET of claim 1 , wherein the first spacer comprises an insulating material.3. The VFET of claim 2 , wherein the insulating material comprises silicon nitride.4. The VFET of claim 1 , wherein the second spacer comprises an insulating material.5. The VFET of claim 4 , wherein the insulating material comprises silicon nitride.6. The VFET of claim 1 , further comprising a tungsten gate disposed around the fin.7. The VFET of claim 1 , wherein the hard mask on the fins comprises an inorganic hard mask.8. The VFET of claim 1 , wherein the hard mask comprises a non-conducting material.9. The VFET of claim 8 , wherein the non-conducting material comprises silicon nitride claim 8 , SiBCN claim 8 , SiOCN claim 8 , or a combination ...

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Номер записи: 134
19-04-2018 дата публикации

STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS

Номер: US20180108752A1
Автор: Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, LIE Fee Li, SIEG STUART A., Sporre John R.
Принадлежит:

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. 1. A method of forming fin field-effect transistor with a fin comprising:forming a spacer around a first portion of a mandrel on an upper surface of a substrate, wherein the spacer is adjacent to a first sidewall of the mandrel extending in a first direction and a second sidewall of the mandrel extending in a second direction;removing the first portion of the mandrel;removing an exposed portion of the substrate, wherein the removing the exposed portion of the substrate forms a fin below the spacer, wherein the fin comprises a first portion extending in the first direction and a second portion extending in the second direction;removing the spacer; andforming a gate extending in the first direction on the upper surface of the substrate and on the second portion of the fin, wherein at least a portion of the first portion of the fin is under the gate.2. The method of claim 1 , further comprising:forming a confining layer on the upper surface of the substrate parallel to at least a portion of the fin.3. The method of claim 1 , further comprising:forming another gate on the upper surface of ...

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Номер записи: 135
26-04-2018 дата публикации

STATIC RANDOM ACCESS MEMORY (SRAM) DENSITY SCALING BY USING MIDDLE OF LINE (MOL) FLOW

Номер: US20180114792A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Kanakasabapathy Sivananda K., STANDAERT Theodorus E., Wang Junli
Принадлежит:

A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer. 1. A semiconductor structure comprising:gate contacts formed on a semiconductor substrate; andtrench silicide (TS) contacts formed on the semiconductor substrate, the TS contacts recessed to form a gap region;wherein the gap region of the recessed TS contacts is filled with a dielectric, the gate contacts are selectively etched to form a first conducting layer, and the TS contacts are selectively etched to form a second conducting layer.2. The structure of claim 1 , wherein the gate contacts are formed between the TS contacts.3. The structure of claim 1 , wherein the dielectric is silicon carbide (SiC).4. The structure of claim 1 , wherein the dielectric is silicon carbide nitride (SiCN).5. The structure of claim 1 , wherein the first and second conducting layers are different.6. The structure of claim 1 , wherein the first and second conducting layers are the same.7. The structure of claim 6 , wherein the first and second conducting layers are Tungsten (W).8. The structure of claim 1 , wherein gate contact to TA contact shorts are prevented by a TS cap layer.9. A semiconductor structure for performing static random access memory (SRAM) density scaling claim 1 , the structure comprising:gate contacts and trench silicide (TS) contacts formed in an alternating manner over a semiconductor substrate;gap regions formed after recessing the TS contacts;a dielectric for selectively filling only the gap regions of the recessed TS contacts;a first metal layer deposited over the gate contacts; anda second metal layer ...

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Номер записи: 136
26-04-2018 дата публикации

Finfet with reduced parasitic capacitance

Номер: US20180114846A1
Автор: Emre Alptekin, Sivananda K. Kanakasabapathy, Veeraraghavan S. Basker
Принадлежит: International Business Machines Corp

A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.

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Номер записи: 137
26-04-2018 дата публикации

FINFET WITH REDUCED PARASITIC CAPACITENCE

Номер: US20180114847A1
Автор: Alptekin Emre, Basker Veeraraghavan S., Kanakasabapathy Sivananda K.
Принадлежит:

A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact. 1forming a dummy gate above and perpendicular to semiconductor fins;forming sidewall spacers on opposite sides of the dummy gate;covering exposed portions of the semiconductor fins not covered by the dummy gate or the sidewall spacers with a dummy dielectric material;forming an isolation region adjacent to and in direct contact with the dummy dielectric material, an upper surface of the isolation region is substantially flush with an upper surface of the dummy dielectric material;replacing the dummy gate with a metal gate electrode covered by a dielectric gate cap;replacing the dummy dielectric material with a self-aligned silicide contact, the self-aligned silicide contact being adjacent to and in direct contact with the sidewall spacers which separates it from the metal gate electrode, wherein the dummy dielectric material is removed selective to the isolation region, the sidewall spacers, and the dielectric gate cap;forming a blanket metal layer on top of both the metal gate electrode and the self-aligned silicide contact, the blanket metal layer being in direct contact with the self-aligned silicide contact but physically isolated from the metal gate electrode by ...

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Номер записи: 138
09-04-2020 дата публикации

BOTTOM CONTACT FORMATION FOR VERTICAL TRANSISTOR DEVICES

Номер: US20200111895A1
Автор: De Silva Ekmini A., Fan Su Chen, Kanakasabapathy Sivananda K.
Принадлежит:

A method for fabricating a semiconductor device includes forming at least one contact trench corresponding to at least one bottom contact area associated with at least one vertical transistor, laterally etching through the at least one contact trench to form at least one bottom contact region corresponding to the at least one bottom contact area, and filling the at least one bottom contact region with a conductive material to form at least one bottom contact. 1. A method for fabricating a semiconductor device , comprising:forming at least one contact trench corresponding to at least one bottom contact area associated with at least one vertical transistor;laterally etching through the at least one contact trench to form at least one bottom contact region corresponding to the at least one bottom contact area; andfilling the at least one bottom contact region with a conductive material to form at least one bottom contact.2. The method of claim 1 , wherein forming the at least one contact trench includes vertically etching to land on at least one substrate corresponding to the at least one vertical transistor.3. The method of claim 1 , wherein laterally etching through the at least one contact trench to form the at least one bottom contact region further includes using a wet etch process selective to isolation material.4. The method of claim 1 , wherein the at least one bottom contact region is formed through a boundary of adjacent regions of a memory cell.5. The method of claim 4 , wherein the memory cell includes a static random-access memory (SRAM) memory cell.6. The method of claim 1 , further comprising forming a middle-of-the-line interlayer dielectric within the at least one contact trench to an exposed surface of the at least one bottom contact.7. The method of claim 6 , further comprising forming at least one top source/drain contact on at least one top source/drain region associated with the at least one vertical transistor.8. The method of claim 7 , wherein ...

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Номер записи: 139
03-05-2018 дата публикации

FIN CUT DURING REPLACEMENT GATE FORMATION

Номер: US20180122708A1
Автор: Greene Andrew M., Kanakasabapathy Sivananda K., PRANATHARTHIHARAN Balasubramanian S., Sporre John R.
Принадлежит:

A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack. 1. A method of forming a semiconductor structure , the method comprising:depositing a dielectric over a plurality of fins;applying a mask over a first section of the plurality of fins to expose a second section of the plurality of fins including fins to be cut;removing the dielectric from the fins to be cut;depositing a replacement gate stack; andcutting the second section of the plurality of fins during etching of the replacement gate stack.2. The method of claim 1 , wherein removal of the fins to be cut results in recesses formed within a semiconductor layer receiving the plurality of fins.3. The method of claim 2 , further comprising depositing a spacer within the recesses formed by the removal of the fins to be cut.4. The method of claim 3 , wherein the spacer is a non-conducting dielectric layer.5. The method of claim 1 , wherein the replacement gate stack includes a dummy gate and a gate hard mask.6. The method of claim 5 , wherein the dummy gate is formed of amorphous silicon.7. The method of claim 1 , wherein the mask is an organic planarization layer (OPL).8. The method of claim 1 , wherein each of the plurality of fins ...

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Номер записи: 140
03-05-2018 дата публикации

Fin cut during replacement gate formation

Номер: US20180122801A1
Автор: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, John R. Sporre, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.

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Номер записи: 141
14-05-2015 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20150135156A1
Автор: Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, STANDAERT Theodorus E., Wang Xinhui
Принадлежит:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A method in a computer-aided design system for generating a functional design model of an integrated FinFET and deep trench capacitor structure using a computing device , the method comprising:generating a functional representation, using the computing device, of a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure;generating a functional representation, using the computing device, of a plurality of SOI fins each of which having ends in contact with respective fin structures of the deep trench capacitors;generating a functional representation, using the computing device, of an insulator material on the fin structures of the plurality of deep trench capacitors; andgenerating a functional representation, using the computing device, of a gate structure extending over the insulator material and the SOI fins.2. The method of claim 1 , further comprising generating a functional representation of an epitaxial material connecting the plurality of SOI fins with the respective fin structures of the deep trench capacitors.3. The method of claim 1 , wherein the functional representations reside on storage medium as a data format used for the exchange of layout data of integrated circuits.4. The method of claim 1 , wherein the functional representations reside in a programmable gate array.5. The method of claim 1 , ...

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Номер записи: 142
28-05-2015 дата публикации

finFET Isolation by Selective Cyclic Etch

Номер: US20150145065A1
Автор: Kanakasabapathy Sivananda K., SIEG STUART A., STANDAERT Theodorus E., Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Etching interleaved structures of semiconductor material forming fins of finFETs and local isolation material interposed between the fins is performed alternately and cyclically by alternating etchants cyclically such as by alternating gases during reactive ion etching. Etchants are preferably alternated when one of the semiconductor material and the local isolation material protrudes above the other by a predetermined distance. Since protruding surfaces are etched more rapidly than recessed surfaces, the overall etching process is accelerated and completed in less time such that erosion of other materials to which the etchants are less than optimally selective is reduced and allow improved etching of trenches for improved isolation structures to be formed. 1. A method for forming a trench for an isolation structure from a structure including excess fins formed from a layer of semiconductor material with local isolation material deposited between said fins , said method comprising steps ofdepositing hard mask material over a portion of said local isolation material and selected ones of said fins,patterning said hard mask material, andcyclically etching said excess fins selectively to said hard mask material and said local isolation material alternatingly with etching said local isolation material selectively to said excess fins and said hard mask material in respective etching cycles to form a trench between said selected ones of said fins while limiting protrusion of portions of said excess fins above portions of said local isolation material and limiting protrusion of portions of said local isolation material above said portions of said excess fins.2. The method as recited in claim 1 , further including a step ofetching said semiconductor material beyond a base of a said fin in accordance with said hard mask.3. The method as recited in claim 2 , wherein said step of etching said semiconductor material in accordance with said hard mask provides a substantially ...

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Номер записи: 143
31-05-2018 дата публикации

FINFET WITH REDUCED PARASITIC CAPACITANCE

Номер: US20180151686A1
Автор: Alptekin Emre, Basker Veeraraghavan S., Kanakasabapathy Sivananda K.
Принадлежит:

A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact. 1. A finFET semiconductor device comprising:a plurality of fins etched from a semiconductor substrate;a gate electrode above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gate electrode;a self-aligned silicide contact positioned above and between active fin regions, wherein the self-aligned silicide contact has a stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being above the second upper surface; anda metal contact above and in direct contact with only the first upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the metal contact to the active fin regions.2. The structure of claim 1 , wherein the active fin regions are completely covered by the self-aligned silicide contact such that the second upper surface of the self-aligned silicide contact is above the active fin regions.3. The structure of claim 1 , wherein the first upper surface of the self-aligned silicide contact is substantially flush with an upper surface of a dielectric gate cap directly above the gate electrode.4. The ...

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Номер записи: 144
09-06-2016 дата публикации

SELF-ALIGNED QUADRUPLE PATTERNING PROCESS

Номер: US20160163600A1
Автор: Colburn Matthew E., Kanakasabapathy Sivananda K., LIE Fee Li, SIEG STUART A.
Принадлежит:

Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks. 1. A method of forming a mandrel structure comprising:providing a first set of second mandrel structures having a first width on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width that is less than said first width on non-facing sidewall surfaces of said neighboring pair of first mandrel structures;removing each first mandrel structure;forming a spacer on a sidewall surface of said first and second sets of second mandrel structures, wherein in a region between said neighboring pair of first mandrel structures a merged spacer is formed;removing said first and second sets of second mandrel structures; andpatterning a portion of an underlying substrate utilizing said second spacer and said merged spacer as etch masks.2. The method of claim 1 , wherein said first set of second mandrel structures comprises a remaining portion of an additive mask and a remaining portion of a spacer material.3. The method of claim 2 , wherein a sidewall surface of said remaining portion of said additive mask is in ...

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Номер записи: 145
16-06-2016 дата публикации

Modified fin cut after epitaxial growth

Номер: US20160172379A1
Автор: Fee Li LIE, Raghavasimhan Sreenivasan, Sivananda K. Kanakasabapathy, Soon-Cheon Seo
Принадлежит: International Business Machines Corp

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

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Номер записи: 146
16-06-2016 дата публикации

MODIFIED FIN CUT AFTER EPITAXIAL GROWTH

Номер: US20160172380A1
Автор: Kanakasabapathy Sivananda K., LIE Fee Li, Seo Soon-Cheon, SREENIVASAN Raghavasimhan
Принадлежит:

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions. 1. A semiconductor structure comprising:a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the first plurality of fins;a second plurality of fins located in a second region of the substrate, wherein a second junction is located on a second set of fins in the second plurality of fins;an intermediate plurality of fins located in an intermediate region of the substrate, wherein the intermediate region is located between the first region and the second region, wherein the length of the intermediate plurality of fins is substantially shorter than a length of the first plurality of fins; anda gate running substantially perpendicular to the first plurality of fins, the intermediate plurality of fins, and the second plurality of fins.2. The structure of claim 1 , wherein the first junction comprises a semiconductor material.3. The structure of claim 2 , wherein the semiconductor material comprises silicon claim 2 , silicon-germanium or silicon-carbon.4. The structure of claim 1 , wherein the second junction material comprises a semiconductor material.5. The structure of claim 4 , wherein the semiconductor material comprises silicon claim 4 , silicon-germanium or silicon-carbon.6. The structure of claim 1 , wherein the substrate is a semiconductor on insulator substrate.7. The structure of claim 1 , wherein the fin pitch amongst the fins is substantially uniform.8. The structure of claim 1 , wherein the intermediate plurality of fins is only located beneath the gate.9. The structure of claim 1 , wherein the gate has a substantially uniform density.10. A semiconductor structure comprising:a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the ...

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Номер записи: 147
18-09-2014 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20140264522A1
Автор: Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, STANDAERT Theodorus E., Wang Xinhui
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A method , comprising:forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate;simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate;forming an insulator layer on the polysilicon fins; andforming gate structures over the SOI fins and the insulator layer on the polysilicon fins.2. The method of claim 1 , wherein the polysilicon fins and the SOI fins are formed in contact with one another claim 1 , in the same processing step.3. The method of claim 1 , wherein the SOI fins are formed by a sidewall image transfer process.4. The method of claim 1 , wherein the insulator layer is oxide material blanket deposited on the polysilicon fins and the SOI fins claim 1 , and subsequently removed from the SOI fins prior to formation of the gate structures.5. The method of claim 1 , further comprising forming an epitaxial material over a connection between the polysilicon fins and the SOI fins.6. The method of claim 5 , wherein the connection is provided by material of the polysilicon fins and semiconductor material of the SOI fins.7. The method of claim 6 , wherein the forming of the epitaxial material comprises growing semiconductor material over exposed sidewalls of the polysilicon fins and semiconductor material of the SOI fins.8. The method of claim 7 , wherein the semiconductor material is silicon.9. The method of ...

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Номер записи: 148
06-06-2019 дата публикации

EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION

Номер: US20190172827A1
Автор: Balakrishnan Karthik, Fogel Keith E., Kanakasabapathy Sivananda K., Reznicek Alexander
Принадлежит:

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures. 1. A structure comprising:a plurality of fin structures having a strain extending from edge to edge of each fin structure in said plurality of fin structures; andan epitaxial oxide present in an opening present between edges of said plurality of fin structures, wherein epitaxial oxide prevents said strain in said plurality of fin structures from relaxing.2. The structure of claim 1 , wherein the plurality of fin structures are present on a substrate having a different lattice dimension than a lattice dimension for the fin structures.3. The structure of claim 1 , wherein each of the plurality of fin structures comprise silicon claim 1 , germanium claim 1 , silicon germanium or a combination thereof claim 1 ,4. The structure of claim 1 , wherein the epitaxial oxide is a rare earth oxide composition.5. The structure of claim 1 , wherein the epitaxial oxide is selected from the group consisting of cerium oxide (CeO) claim 1 , lanthanum oxide (LaO) claim 1 , yttrium oxide (YO) claim 1 , gadolinium oxide (GdO) claim 1 , europium oxide (EuO) claim 1 , terbium oxide (TbO) and combinations thereof.6. The semiconductor device of claim 1 , wherein the strain is a compressive strain.7. The structure of claim 1 , wherein the strain is a tensile strain.8. ...

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Номер записи: 149
06-06-2019 дата публикации

Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning

Номер: US20190172940A1
Автор: Andrew M. Greene, Eric R. Miller, Gauri Karve, Hong He, Pietro Montanini, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

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Номер записи: 150
07-07-2016 дата публикации

REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

Номер: US20160197157A1
Автор: Ando Takashi, Faltermeier Johnathan E., Fan Su Chen, Kanakasabapathy Sivananda K., OK Injo, Yamashita Tenko
Принадлежит:

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. 1. A semiconductor structure comprising: a metal gate above a conductive barrier, and', 'a gate dielectric layer below the conductive barrier; and, 'a gate structure formed above a substrate, the gate structure comprisinga capping layer above the gate structure, wherein the conductive barrier separates the capping layer from the gate dielectric layer.2. The semiconductor structure of claim 1 , wherein the gate structure comprises a length less than 20 nm.3. The semiconductor structure of claim 1 , wherein the conductive barrier comprises an n-type workfunction metal.4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.5. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a vertical portion and a horizontal portion claim 1 , the vertical portion of the gate dielectric layer having a height less than a height of the metal gate measured from a top surface of the substrate.6. The semiconductor structure of claim 5 , wherein the height of the vertical portion of the gate dielectric layer is within a range from 1 ...

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Номер записи: 151
12-07-2018 дата публикации

SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONS

Номер: US20180197738A1
Автор: Burns Sean D., Clevenger Lawrence A., Colburn Matthew E., Felix Nelson M., Kanakasabapathy Sivananda K., Penny Christopher J., Quon Roger A., SAULNIER Nicole A.
Принадлежит:

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures. 1. An etch method comprising:forming first dielectric spacers on sidewalls of a plurality of mandrel structures that are present on a substrate;forming second dielectric spacers on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer in the etch window, wherein the second dielectric spacers cover said first dielectric spacers that do not include the connecting portion;removing the connecting portion of the centralized first dielectric spacer; andetching the substrate using the first dielectric spacers as an etch mask, wherein an opening is formed from the space provide by said removing the connecting portion of the centralized first dielectric spacer that connects a first trench proximate to the mandrel structure and a second trench proximate to a non-mandrel structure.2. The etch method of claim 1 , wherein the substrate is a silicon containing dielectric layer3. The etch method of claim 2 , wherein the opening in the substrate is filled to provide a metal line.4. The etch method of claim 1 , wherein forming the first dielectric spacers on sidewalls of the mandrel structures comprises: ...

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Номер записи: 152
12-07-2018 дата публикации

TUNABLE TiOxNy HARDMASK FOR MULTILAYER PATTERNING

Номер: US20180197752A1
Автор: Arceo de la Pena Abraham, De Silva Ekmini A., Felix Nelson M., Kanakasabapathy Sivananda K.
Принадлежит:

Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures. 1. A multilayer lithographic structure comprising:an organic planarizing layer;a titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride comprises TiOxNy, wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25; anda photosensitive resist layer on the titanium oxynitride layer.2. The multilayer lithographic structure of claim 1 , further comprising a bottom antireflective layer intermediate the titanium oxynitride layer and the organic planarizing layer.3. The multilayer lithographic structure of claim 1 , wherein the photosensitive resist layer is a methacrylate polymer claim 1 , a phenolic based polymer or a copolymer thereof.4. The multilayer lithographic structure of claim 1 , wherein the organic planarizing layer has a thickness from 50 nm to 300 nm claim 1 , the titanium oxynitride layer has a thickness of 3 nm to 50 nm claim 1 , and the photosensitive resist layer has a thickness of 30 nm to 300 nm.5. The multilayer lithographic structure of claim 1 , wherein the titanium oxynitride layer is selected to have an extinction coefficient (k) less than 1 from a wavelength range from 400 nm to 800 nm.6. The multilayer lithographic structure of claim 1 , wherein the titanium oxynitride layer is selected to have an extinction coefficient (k) less than 0.5 from a wavelength range from 400 nm to 800 nm.7. The multilayer lithographic structure of claim ...

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Номер записи: 153
30-07-2015 дата публикации

STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION

Номер: US20150214244A1
Автор: Ho Herbert L., Kanakasabapathy Sivananda K., Krishnan Rishikesh, RIM Kern
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures. 1. An integrated circuit includinga substrate having a predetermined bulk resistance,a logic/support area,at least two deep trench capacitors spaced from each other and extending into said substrate,a moat isolation structure located between said logic/support area and said deep trench capacitor, said moat isolation structure extending into said substrate farther than said deep trench capacitor whereby a conduction path below said isolation structure is at least one micron longer than a distance between said at least two deep trench capacitors and wherein said materials in said moat isolation structure and said deep trench capacitor are different.2. An integrated circuit as recited in claim 1 , wherein said at least two deep trench capacitors include a conductive lining in deep trenches but no conductive lining is included in said moat isolation structure.3. An integrated circuit as recited in claim 2 , wherein said conductive lining comprises a metal.4. An integrated circuit as recited in claim 2 , wherein said conductive lining comprises a silicide.5. An integrated circuit as recited in claim 1 , wherein said moat isolation ...

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Номер записи: 154
30-07-2015 дата публикации

REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL

Номер: US20150214331A1
Автор: Jang Linus, Kanakasabapathy Sivananda K., Mehta Sanjay C., Seo Soon-Cheon, SREENIVASAN Raghavasimhan
Принадлежит:

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions. 1. A method of fabricating a semiconductor device , the method comprising:forming at least one semiconductor fin on a semiconductor substrate;forming an etch stop layer on an upper surface of the at least one semiconductor fin;forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material;patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;depositing a spacer layer that conforms with an outer surface of each dummy gate element; andetching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin.2. The method of claim 1 , further comprising epitaxially growing a semiconductor material from the exposed portion of the semiconductor fin after etching the spacer layer and the portion of the etch stop layer.3. The method of ...

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Номер записи: 155
27-07-2017 дата публикации

PITCH SCALABLE ACTIVE AREA PATTERNING STRUCTURE & PROCESS FOR MULTI-CHANNEL FIN FET TECHNOLOGIES

Номер: US20170213825A1
Автор: Kanakasabapathy Sivananda K., LIE Fee Li, Miller Eric, SIEG STUART A.
Принадлежит:

Provided herein is a multi-channel finFET having a plurality of fins prepared by a process. The process includes forming a series of mandrels on hard mask layer which overlays a semiconductor layer. The semiconductor layer has areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer. The process includes applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins. The process includes removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels. The process includes removing the series of mandrels and etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask. 1. A multi-channel finFET having a plurality of fins prepared by a process comprising:forming a series of mandrels on hard mask layer which overlays a semiconductor layer, the semiconductor layer having areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer;applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins;removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels;removing the series of mandrels;etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask;removing undesired fins of the spacer layer sacrificial fins to leave desired fins;applying a second conformal coating to build a total thickness of the desired fins and the second conformal coating being equal to a critical dimension plus an etchback allowance;applying a third conformal coating layer to build a final thickness of the desired fins and the second and third conformal coatings being substantially equal to an additional etchback allowance of the first and second ...

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Номер записи: 156
26-07-2018 дата публикации

Fin Cut to Prevent Replacement Gate Collapse on STI

Номер: US20180211955A1
Автор: Greene Andrew M., Kanakasabapathy Sivananda K., Pranatharthiharan Balasubramanian, Sporre John R.
Принадлежит:

The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided. 1. A method of forming a fin field-effect transistor (finFET) , the method comprising:patterning at least one fin in a substrate;forming an oxide layer on the at least one fin;depositing a first dummy gate material onto the oxide layer over the at least one fin, wherein the first dummy gate material serves to pin a lattice constant of the at least one fin;forming a trench in the first dummy gate material and the oxide layer over at least one region of the at least one fin;extending the trench into the substrate, removing the at least one region of the at least one fin;partially filling the trench with a first dielectric to a level above the at least one fin;depositing a second dummy gate material into the trench on top of the first dielectric;patterning the first dummy gate material and the second dummy gate material into dummy gates, wherein at least one of the dummy gates is disposed on the first dielectric and at least another one of the dummy gates is disposed on the at least one fin, and wherein the at least one dummy gate disposed on the first dielectric has an aspect ratio less than an aspect ratio of the at least one dummy gate disposed on the at least one fin;surrounding the dummy gates with a second dielectric;selectively removing the dummy gates forming gate trenches in the second dielectric; andforming replacement gates in the gate trenches.2. The method of claim 1 , wherein the substrate comprises a ...

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Номер записи: 157
04-07-2019 дата публикации

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

Номер: US20190206871A1
Автор: Chan Kevin K., Kanakasabapathy Sivananda K., Khan Babar A., Kobayashi Masaharu, Leobandung Effendi, STANDAERT Theodorus E., Wang Xinhui
Принадлежит:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure including epitaxial material comprising semiconductor material over exposed sidewalls of fin structures and semiconductor material of SOI fins each of which have ends in contact with respective fin structures of the deep trench capacitors.2. The structure of claim 1 , wherein the epitaxial material is on ends of the SOI fins and ends of the fin structures of the deep trench capacitors3. The structure of claim 1 , wherein the semiconductor material is silicon.4. The structure of claim 1 , wherein the fin structures are polysilicon fins formed in contact with the SOI fins claim 1 , and ends of the SOI fins are connected to respective polysilicon fins.5. The structure of claim 1 , wherein the ends of the SOI fins contact ends of the fin structures of the deep trench capacitors in a longitudinal direction.6. The structure of claim 5 , wherein the epitaxial material comprises silicon at a depth of about 15 nm to 25 nm to reduce strap resistance and make a robust connection between the plurality of SOI fins and the respective fin structures of the deep trench capacitors.7. The structure of claim 1 , further comprising a gate structure extending over an insulator material and the SOI fins claim 1 , the gate structure comprises a gate ...

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Номер записи: 158