Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 31879. Отображено 100.
05-01-2012 дата публикации

ESD Clamp Adjustment

Номер: US20120002333A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses. 1. An electrostatic discharge (ESD) protection device for protecting a semiconductor device , the ESD protection device comprising:a trigger element to monitor power on a first circuit node and provide a trigger signal indicative of whether the monitored power is representative of an incoming ESD pulse;a variable resistor coupled between the first circuit node and a second circuit node and which is arranged to selectively shunt power of the incoming ESD pulse, if any, from the first circuit node to the second circuit node and away from the semiconductor device;a gate driver circuit to provide a gate voltage, which is based on the trigger signal and a control signal, to a control terminal of the variable resistor to enable the selective shunting of power; andwherein a regulator element provides the control signal to the gate driver circuit to selectively adjust the power shunted over the variable resistor.2. The ESD protection device of claim 1 , wherein a voltage level of the control signal reflects a relationship between a voltage on the first circuit node and a first voltage threshold.3. The ESD protection device of claim 1 , wherein the gate driver circuit comprises a ...

Подробнее
Номер записи: 1
12-01-2012 дата публикации

High-Voltage Bipolar Transistor with Trench Field Plate

Номер: US20120007176A1
Автор: Kadow Christoph, Krischke Norbert, Meyer Thorsten
Принадлежит: INFINEON TECHNOLOGIES AG

A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. 1. A bipolar transistor structure , comprising:an epitaxial layer on a semiconductor substrate;a bipolar transistor device formed in the epitaxial layer;a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device, the trench structure including a field plate spaced apart from the epitaxial layer by an insulating material;a base contact connected to a base of the bipolar transistor device;an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact; andan electrical connection between the emitter contact and the field plate.2. A bipolar transistor structure according to claim 1 , wherein the trench structure surrounds the bipolar transistor device on all lateral sides of the bipolar transistor device.3. A bipolar transistor structure according to claim 1 , wherein the trench structure extends into the epitaxial layer to a depth ranging between 1/3 and 1.5 times a thickness of the epitaxial layer.4. A bipolar transistor structure according to claim 1 , wherein a ratio between a width of the trench structure and a width of the epitaxial layer in a region surrounded by the trench structure is between 2/1 and 1/2.5. A bipolar transistor structure according to claim 1 , ...

Подробнее
Номер записи: 2
12-01-2012 дата публикации

Transistor Half-Bridge Control

Номер: US20120008238A1
Автор: Thiele Steffen
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A circuit for driving a transistor half bridge is disclosed that comprises a series circuit of a first and a second transistor both having intrinsic or external free-wheeling diodes coupled in parallel. The circuit for driving a transistor half bridge comprises: an over-current detection circuit that is configured to signal an over-current condition when a load current flowing through the first transistor exceeds a first threshold; a protection circuit that is coupled to the over-current detection circuit and that is configured to disable an activation of the first transistor in response to a detected over-current and to re-enable the activation of the first transistor after a first time interval has elapsed; an evaluation circuit that is coupled to the over-current detection circuit and that is configured to check whether a further over-current condition is detected within a second time interval that follows the first time interval. An active free-wheeling by activating the second transistor is disabled when a further over-current condition is detected within the second time interval, and an active free-wheeling by activating the second transistor is enabled during the first time interval when no further over-current condition is detected within the second time interval. 1. A circuit for driving a transistor half bridge that comprises a series circuit of a first transistor and a second transistor each having a respective intrinsic or external free-wheeling diode coupled in parallel , the circuit comprising:an over-current detection circuit configured to signal an over-current condition when a load current flowing through the first transistor exceeds a first threshold;a protection circuit coupled to the over-current detection circuit and configured to disable an activation of the first transistor in response to a detected over-current and to re-enable the activation of the first transistor after a first time interval has elapsed;an evaluation circuit coupled to the ...

Подробнее
Номер записи: 3
12-01-2012 дата публикации

Digital Phase Feedback for Determining Phase Distortion

Номер: US20120008715A1
Автор: Mayer Thomas, Shute Nick
Принадлежит: INFINEON TECHNOLOGIES AG

A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information. 1. A method comprising:generating a first signal from a reference signal and a frequency modulation signal;deriving a feedback signal from the first signal for use in a feedback path;dividing a frequency of the feedback signal using a divisor determined according to the frequency modulation signal to remove phase modulation from the feedback signal;determining a phase difference between the feedback signal and the reference signal; andoutputting a digital signal that is representative of the phase distortion of the first signal caused at least in part by the generating of the first signal.2. The method according to claim 1 , further comprising:amplifying the first signal prior to deriving the feedback signal from the first signal; andremoving amplitude information from the feedback signal prior to the dividing.3. The method according to claim 1 , further comprising:passing the digital signal through a lowpass filter to remove noise added to the feedback signal.4. The method according to claim 1 , further comprising:delaying the frequency modulation signal to match a delay of the feedback signal; andusing the delayed frequency modulation signal to determine a divisor for dividing the feedback signal to remove the phase modulation from the feedback signal.5. The method according to claim 1 , further comprising:using a time-to-digital converter for determining a time difference between the feedback signal and the reference signal, and for outputting the digital signal representative of the phase difference, said digital signal representative of the phase difference corresponding to transmit phase distortion caused at least in part by the generating of the first signal.6. The method according to claim 1 , further comprising:using the digital signal representative of the ...

Подробнее
Номер записи: 4
19-01-2012 дата публикации

Semiconductor Device Including a Channel Stop Zone

Номер: US20120012902A1
Автор: Elpelt Rudolf
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone. 1. A semiconductor device , comprising:a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region;a gate control region of the first conductivity type adjoining the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region;a source zone of the second conductivity type within the body region; anda channel stop zone of the second conductivity type arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region, the channel stop zone including a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone.2. The semiconductor device of claim 1 , whereina dimension of the channel stop zone along a direction perpendicular to the first side is within a range of 5 nm to 100 nm.3. The semiconductor device of claim 1 , wherein{'sup': 17', '− ...

Подробнее
Номер записи: 5
19-01-2012 дата публикации

Vertical Transistor Component

Номер: US20120012924A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface. 1. A vertical transistor component , comprising:a semiconductor body with a first surface and a second surface;a drift region;at least one source region and at least one body region arranged between the drift region and the first surface, wherein the body region is arranged between the source region and the drift region;at least one gate electrode arranged adjacent to the body zone, and a gate dielectric arranged between the gate electrode and the at least one body region;a drain region arranged between the drift region and the second surface;a source electrode electrically contacting the at least one source region, electrically insulated from the gate electrode and arranged on the first surface;a drain electrode electrically contacting the drain region and arranged on the second surface;at least one gate contact electrode which is electrically insulated from the semiconductor body, extends through the semiconductor body from the first surface to the second surface, and is electrically connected with the at least one gate electrode.2. The vertical transistor component of claim 1 ,wherein the at least one gate electrode is arranged in a gate trench which extends into the semiconductor body from the first surface, andwherein the at least one gate contact electrode is arranged at least partially below the gate electrode and extends from the at least one gate electrode to the second surface.3. The vertical transistor component of claim 2 , wherein the at least one gate contact electrode is arranged only below sections of the at least one gate electrode.4. The vertical ...

Подробнее
Номер записи: 6
19-01-2012 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE

Номер: US20120012994A1
Автор: Lackner Gerald, Ottowitz Markus, Schrettlinger Karin, von Koblinski Carsten
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer. 1. A method for manufacturing semiconductor devices , comprising:providing a semiconductor wafer comprising a first surface and a second surface opposite to the first surface, the semiconductor wafer comprising a plurality of doping regions and metal pads, which are arranged on or at the first surface;providing a first glass substrate comprising a bonding surface and at least one of cavities and openings at the bonding surface;bonding the first glass substrate with its bonding surface to the first surface of the semiconductor wafer such that one or more metal pads are arranged within respective cavities or openings of the first glass substrate;machining the second surface of the semiconductor wafer;forming at least one metallisation region on the machined second surface of the semiconductor wafer; anddicing the semiconductor wafer and the first glass substrate to obtain separate semiconductor devices.2. The method of claim 1 , further comprising bonding the first glass substrate to the first surface of the semiconductor wafer by at least one of anodic bonding claim 1 , adhesive bonding claim 1 , fusion bonding and glass-fit bonding.3. The method of claim 1 , further comprising machining the first glass substrate to expose the cavities.4. The method of claim 1 , further comprising forming a metallic seed layer on the second surface of the ...

Подробнее
Номер записи: 7
19-01-2012 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER

Номер: US20120013029A1
Автор: Ganitzer Paul, Zelsacher Rudolf
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. 1. A method for manufacturing semiconductor devices , comprising:providing a semiconductor substrate comprising a first surface, a second surface opposite to the first surface and a plurality of semiconductor components, the semiconductor substrate comprising a device thickness at least in the region of each semiconductor component;forming at least one metallisation layer on the second surface of the semiconductor substrate, the metallisation layer comprising a thickness which is greater than the device thickness of the semiconductor substrate; anddicing the semiconductor substrate along separation regions between adjacent semiconductor components to obtain separate semiconductor devices.2. The method of claim 1 , further comprising:structuring the at least one metallisation layer to form spaced apart metallisation portions on the second surface before dicing the semiconductor substrate.3. The method of claim 1 , further comprising:forming, on the second surface of the semiconductor substrate, a mask layer comprising a plurality of openings, the openings defining the size and location of metallisation portions;depositing a metal or metal-alloy in the openings of the mask layer to form metallisation portions constituting the metallisation layer.4. The method of claim 1 , further comprising:forming a barrier layer on the second surface prior to forming the metallisation layer.5. The method of claim 1 , further comprising:forming a seed layer on the second surface prior to forming the metallisation layer.6. ...

Подробнее
Номер записи: 8
19-01-2012 дата публикации

Metrology Systems and Methods for Lithography Processes

Номер: US20120013884A1
Автор: Lian Jingyu, Lipinski Matthias, Sarma Chandrasekhar, Zhuang Haoren
Принадлежит: INFINEON TECHNOLOGIES AG

Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask. 1. A lithography system , including:a support for a device having a layer of photosensitive material disposed thereon;a projection lens system proximate the support for the device;an illuminator proximate the projection lens system; anda lithography mask disposed between the projection lens system and the illuminator, the lithography mask including a plurality of corner rounding test patterns, the plurality of corner rounding test patterns including at least two angle-containing patterns, wherein an amount of corner rounding of a lithography process of the lithography system may be determined by analyzing a plurality of corner rounding test features formed on the layer of photosensitive material of the device relative to other of the plurality of corner rounding test features.2. The lithography system according to claim 1 , wherein the amount of corner rounding of the lithography process is determinable by an operator of the lithography system.3. The lithography system according to claim 1 , further ...

Подробнее
Номер записи: 9
26-01-2012 дата публикации

Method for Protecting a Semiconductor Device Against Degradation, a Semiconductor Device Protected Against Hot Charge Carriers and a Manufacturing Method Therefor

Номер: US20120018798A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. 1. A method for protecting a semiconductor device against degradation of its electrical characteristics , comprising:providing a semiconductor device comprising a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface, the first semiconductor region comprising majority charge carriers of a first charge type, and the charged dielectric layer comprising fixed charges of the first charge type; andconfiguring a charge carrier density per area of the fixed charges such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region.2. The method of claim 1 , further comprising providing the semiconductor device with the charged dielectric layer being arranged along a drift region formed by the first semiconductor region.3. The method of claim 1 , further comprising providing the semiconductor device with the charged dielectric layer forming at least a part of a field dielectric layer which insulates a field plate from the first semiconductor region.4. The method of claim 1 , wherein the charge carrier density per area of the fixed charges changes ...

Подробнее
Номер записи: 10
26-01-2012 дата публикации

Surge-Current-Resistant Semiconductor Diode With Soft Recovery Behavior and Methods for Producing a Semiconductor Diode

Номер: US20120018846A1
Автор: Baburske Roman, Lutz Josef, Schulze Hans-Joachim, Siemieniec Ralf
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor. 1. A bipolar semiconductor component , comprising:a semiconductor body having a first horizontal surface, a second surface which runs substantially parallel to the first surface, and at least one load pn junction;a first metallization arranged on the first surface;a second metallization arranged on the second surface; andat least one current path which runs in the semiconductor body from the first metallization to the second metallization only through n-doped zones.2. The bipolar semiconductor component as claimed in claim 1 , wherein claim 1 , in the semiconductor body claim 1 , an n-doped first semiconductor region is arranged in ohmic contact with the second metallization; wherein a plurality of p-doped second semiconductor regions spaced apart from one another horizontally in the semiconductor body are arranged in a sectional plane perpendicular to the first surface claim 1 , the second semiconductor regions being in ohmic contact with the first metallization and respectively forming a load pn junction with the first semiconductor region in the perpendicular sectional plane; and wherein an n-doped channel zone is arranged between second semiconductor regions that are adjacent in the perpendicular sectional plane claim 1 , the current path running through said channel zone.3. The bipolar semiconductor component as claimed in claim 2 , wherein the second semiconductor regions have a maximum dopant concentration greater than 5*10/cm.4. The bipolar semiconductor component as claimed in claim 2 , wherein the first semiconductor region has a maximum dopant ...

Подробнее
Номер записи: 11
26-01-2012 дата публикации

Semiconductor Device With Drift Regions and Compensation Regions

Номер: US20120018856A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type. 1. A method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type , comprising:providing a first semiconductor layer;forming a plurality of layer stack arrangements one above the other on the first semiconductor layer, each layer stack arrangement comprising at least one second semiconductor layer, a plurality of first dopant regions with dopants of the first doping type and a plurality of second dopant regions with dopants of the second dopant type, at least some of the first dopant regions and at least some of the second dopant regions being arranged alternatingly and distant from one another, and interlayer segments between at least some neighbouring first and second dopant regions, wherein the interlayer segments are formed separately for each of the layer stack arrangements, wherein the first dopant regions and the second dopant regions of two adjacent layer stack arrangements are formed such that at least some of the first dopant regions are arranged substantially one above the other in a first direction and at least some of the second dopant regions are arranged substantially one above the other in the first direction; anddiffusing the dopants of the first and second dopant regions such that drift regions are formed from dopants of the first dopant regions, and such that compensation regions are formed from dopants of the second dopant regions.2. The method of claim 1 , wherein at least one of the layer stack arrangements includes exactly one second semiconductor layer.3. The method of claim 1 , wherein at least one of the layer stacks includes a plurality of more than one second semiconductor layer claim 1 , and wherein in ...

Подробнее
Номер записи: 12
26-01-2012 дата публикации

Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor

Номер: US20120019284A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A normally-off power field-effect transistor semiconductor structure is provided. The structure includes a channel, a source electrode, a gate electrode and trapped charges which arranged between the gate electrode and the channel such that the channel is in an off-state when the source electrode and the gate electrode are on the same electric potential. Further, a method for forming a semiconductor device and a method for programming a power field effect transistor are provided. 1. A normally-off transistor , comprising a semiconductor body , comprising:a body region of a first conductivity type comprising a first doping concentration;a channel region of a second conductivity type forming a pn-junction with the body region;an insulated gate electrode structure comprising a gate electrode and a layer of trapped charges arranged between the gate electrode and the channel region, the gate electrode being insulated against the channel region; andwherein a charge type of the trapped charges is equal to a charge type of majority charge carriers of the channel region, and a carrier density per area of the trapped charges is equal to or larger than a carrier density obtained by integrating the first doping concentration along a line in the channel region between the body region and the gate electrode structure.2. The normally-off transistor of claim 1 , wherein an absolute value of the carrier density per area is larger than about 10/cm.3. The normally-off transistor of claim 1 , wherein a minimum distance between the channel region and the gate electrode is larger than about 50 nm.4. The normally-off transistor of claim 1 , wherein the layer of trapped charges is formed by a floating gate electrode comprising the trapped charges.5. The normally-off transistor of claim 4 , wherein a minimum distance between the channel region and the floating gate electrode is larger than about 50 nm.6. The normally-off transistor of claim 1 , wherein the insulated gate electrode structure ...

Подробнее
Номер записи: 13
26-01-2012 дата публикации

Identification Circuit and Method for Generating an Identification Bit

Номер: US20120020145A1
Автор: "dArgouges Michel", Hatsch Joel, Huber Peter, Kamp Winfried, Koeppe Siegmar
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another. 1. A semiconductor device comprising an identification circuit , the identification circuit comprising:a memory cell including a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic, the identification circuit being operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor; anda drive circuit for the memory cell which is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.2. The semiconductor device as claimed in claim 1 , wherein the memory cell is an SRAM memory cell.3. The semiconductor device as claimed in claim 1 , wherein the drive circuit comprises a pMOS transistor operable to control the upper supply potential of the memory cell and an nMOS transistor operable to control the lower supply potential.4. The semiconductor device as claimed in claim 1 , wherein the ...

Подробнее
Номер записи: 14
02-02-2012 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE

Номер: US20120025303A1
Автор: Blank Oliver, Born Mathias, Haeberlen Oliver, Hiller Uli, Hirler Franz, Krumrey Joachim, Poelzl Martin, Rieger Walter, Roesch Maximilian, Ropohl Jan, Siemieniec Ralf, Wood Andrew, Zelsacher Rudolf
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material. 1. A semiconductor device comprising:a semiconductor body;a drift region of a first conductivity type;at least one trench extending into the drift region;at least one gate electrode;a field plate in at least a portion of the at least one trench; anda dielectric material, wherein the dielectric material at least partially surrounds the gate electrode and the field plate;wherein the field plate comprises a first semiconducting material, wherein the first semiconducting material comprises a variable doping concentration, the variable doping concentration decreasing in a vertical direction towards a base of the at least one trench.2. The semiconductor device of claim 1 , wherein the at least one gate electrode is arranged in an upper portion of the at least one trench and the field plate is at least partially arranged in a lower portion of the at least one trench.3. The semiconductor device of claim 1 , wherein the first semiconducting material is at least partially of a second conductivity type claim 1 , the second conductivity type being complementary to the first conductivity type.4. The semiconductor device of claim 3 , wherein the number of charge carriers of the first conductivity type in the drift region is essentially equal to the number of charge carriers of the second conductivity type in the first semiconducting material.5. The semiconductor device of claim 1 , wherein the field plate comprises a contact region claim 1 , the contact region electrically coupling the field plate to a first electrode.6. The semiconductor device of claim 5 , wherein the ...

Подробнее
Номер записи: 15
02-02-2012 дата публикации

Trench Semiconductor Device and Method of Manufacturing

Номер: US20120025304A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device includes a semiconductor body including a trench with first and second opposing sidewalls. A first electrode is arranged in a lower portion of the trench and a second electrode in an upper portion of the trench. A dielectric structure is arranged in the trench, including a first portion between the electrodes. The first portion includes, in sequence along a lateral direction from the first sidewall to the second sidewall, a first part including a first dielectric material, a second part including a second dielectric material selectively etchable to the first dielectric material, a third part including the first dielectric material, the first dielectric material of the third part being continuously arranged along a vertical direction from a top side of the first electrode to a bottom side of the second electrode, a fourth part including the second dielectric material and a fifth part including the first dielectric material. 1. A semiconductor device , comprising:a semiconductor body including a trench, a first sidewall of the trench being opposed to a second sidewall of the trench;a first electrode in a lower portion of the trench;a second electrode in an upper portion of the trench;a dielectric structure in the trench, the dielectric structure including a first portion between the first electrode and the second electrode; and whereinthe first portion of the dielectric structure includes, in sequence along a lateral direction from the first sidewall to the second sidewall, a first part including a first dielectric material, a second part including a second dielectric material being selectively etchable to the first dielectric material, a third part including the first dielectric material, the first dielectric material of the third part being continuously arranged along a vertical direction from a top side of the first electrode to a bottom side of the second electrode, a fourth part including the second dielectric material and a fifth part ...

Подробнее
Номер записи: 16
02-02-2012 дата публикации

Asymmetric Segmented Channel Transistors

Номер: US20120025325A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. 1. An integrated circuit comprising an asymmetric segmented transistor , the asymmetric segmented transistor comprising:an active region disposed at a surface of a semiconductor body;a source region and a drain region disposed within the active region;a floating source/drain region disposed within the active region;a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width;a second channel region disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width;a first gate dielectric overlying the first channel region;a second gate dielectric overlying the second channel region;a first gate line overlying the first gate dielectric; anda second gate line overlying the second gate dielectric, wherein the first gate line and second gate line are coupled.2. The integrated circuit of claim 1 , wherein the integrated circuit comprises analog circuitry comprising the asymmetric ...

Подробнее
Номер записи: 17
02-02-2012 дата публикации

Devices Formed With Dual Damascene Process

Номер: US20120025382A1
Автор: Kaltalioglu Erdem, Riess Philipp, Wendt Hermann
Принадлежит: INFINEON TECHNOLOGIES AG

Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. 1. A semiconductor device comprising multiple levels of metallization , at least one metallization level comprising:a first metal level overlying a via level, the first metal level comprising metal lines embedded in an insulating layer; andvias disposed in the via level, and disposed underneath the first metal level, wherein a top width of the metal lines in a region overlying the vias is about the same as a top width of the metal lines in a region not overlying the vias.2. The semiconductor device of claim 1 , wherein the metal lines comprise a first metal line claim 1 , wherein the vias comprise a first via claim 1 , and wherein the first metal line and the first via are formed as a single structure without a diffusion layer separating the first via from the first metal line.3. The semiconductor device of claim 1 , wherein the vias and the metal lines comprise copper.4. The semiconductor device of claim 1 , wherein the metal lines comprise a first metal line having first sidewalls claim 1 , wherein the vias comprise a first via having second sidewalls claim 1 , and wherein a metal liner continuously covers the first sidewalls and the second sidewalls.5. The semiconductor device of claim 4 , wherein the metal liner comprises a diffusion barrier metal.6. The semiconductor device of claim 4 , wherein the metal liner comprises a material selected from the group consisting of titanium nitride claim 4 , titanium claim 4 , tantalum claim 4 , tantalum nitride claim 4 , tungsten nitride claim 4 , tungsten carbonitride (WCN) claim 4 , and ruthenium.7. The semiconductor device of claim 4 , wherein a conductive material is disposed ...

Подробнее
Номер записи: 18
02-02-2012 дата публикации

ELECTRONIC DEVICE AND METHOD FOR PRODUCTION

Номер: US20120025384A1
Автор: Hosseini Khalil, Stecher Matthias
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. 1. An electronic device , comprising:an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the first layer; anda connection apparatus which is arranged on the first layer and on the second layer.2. The device of claim 1 , comprising:wherein the connection apparatus is composed of copper or a copper alloy or contains copper or a copper alloy,or wherein the connection apparatus is composed of aluminum or an aluminum alloy, or contains aluminum or an aluminum alloy,or wherein the connection apparatus is composed of gold or a gold alloy, or contains gold or a gold alloy.3. The device of claim 1 , comprising wherein the connection apparatus is arranged outside the integrated component.4. The device of claim 1 , comprising wherein the connection apparatus passes through the second layer.5. The device of claim 1 , comprising wherein the second layer is arranged on the first layer.6. The device of claim 1 , comprising wherein the second layer is composed of or contains aluminum or an aluminum alloy claim 1 , or the second layer is composed of or contains a metal from the fourth to sixth group in the periodic table claim 1 , or the second layer is composed of metal and phosphorus claim 1 , or contains metal and phosphorus.7. The device of claim 6 , comprising:wherein the second layer is composed of or contains aluminum or an aluminum alloy,wherein the thickness of the second layer is in the range from 5 ...

Подробнее
Номер записи: 19
02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Автор: Andre Roehrig, Olaf Kirsch, Peter Kanschat, Thilo Stolze
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Подробнее
Номер записи: 20
02-02-2012 дата публикации

OFF-CENTER ANGLE MEASUREMENT SYSTEM

Номер: US20120025808A1
Автор: Ausserlechner Udo, Granig Wolfgang, HAMMERSCHMIDT Dirk
Принадлежит: INFINEON TECHNOLOGIES AG

A method for measuring an angular position of a rotating shaft, the method including providing a magnetic field which rotates with the shaft about an axis of rotation, positioning an integrated circuit having first and second magnetic sensing bridges within the magnetic field at a radially off-center position from the axis of rotation, the first and second magnetic sensing bridges respectively providing first and second signals representative of first and second magnetic field directions, the integrated circuit having a set of adjustment parameters for modifying attributes of the first and second signals, modifying values of the set of adjustment parameters until errors in the first and second signals are substantially minimized, and determining an angular position of the shaft based on the first and second signals. 1. An angle measurement system comprising:a magnet coupled to a rotating member and providing a magnetic field which rotates with the rotating member about a rotational axis of the rotating member; first and second bridges configured to respectively provide first and second signals representative of first and second directional components of the magnetic field and together representative of an angular position of the rotating member, wherein the first and second bridges are positioned adjacent to one another along a radius extending from the rotational axis and proximate to and in parallel with a surface of the magnet; and', 'a set of adjustment parameters for adjusting attributes of the first and second signals having values selected to minimize errors in the first and second signals., 'an integrated circuit angle sensor disposed within the magnetic field at a radially off-center position from the rotational axis and including2. The angle measurement system of claim 1 , wherein the magnet comprises a ring magnet coupled about the rotating member at a position along shaft away from ends of the shaft.3. The angle measurement system of claim 1 , wherein ...

Подробнее
Номер записи: 21
02-02-2012 дата публикации

RESISTIVE MEMORY AND METHOD

Номер: US20120026781A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. 1. A method of interacting with a resistive memory , the method comprising:controlling current through a fin or multiple connected fins of a multi gate field effect transistor; andinteracting with a programmable volume portion of a resistive memory element abutting an end of the fin.2. The method of wherein interacting comprises applying a write current.3. The method of wherein interacting comprises applying a reset current.4. The method of wherein interacting comprises applying a read current.5. The method of claim 1 , wherein the end of the fin abutting the resistive memory element is tapered from a first cross section area associated with a drain terminal of the multi gate field effect transistor to a second cross sectional area associated with the programmable volume portion claim 1 , and wherein the first cross sectional area is larger than the second cross sectional area.6. The method of claim 5 , wherein the taper comprises a vertical taper of the end of the fin.7. The method of claim 6 , wherein the taper further comprises a longitudinal taper of the fin.8. The method of claim 1 , wherein a gate of the multi gate field effect transistor is coupled to a word line claim 1 , and wherein controlling current comprises applying a voltage to the word line.9. The method of claim 8 , wherein a drain of the multi gate field effect transistor is coupled to a bit line claim 8 , and a source of the multi gate field effect transistor is coupled to a predetermined potential claim 8 , and wherein controlling current comprises controlling a current traveling through the bit line and multi gate field effect transistor to the predetermined potential.10. The method of claim 1 , wherein the multi gate field effect transistor and the programmable volume portion are laterally disposed from one another.11. The method of ...

Подробнее
Номер записи: 22
02-02-2012 дата публикации

Nonvolatile Memory Cell With Extended Well

Номер: US20120026793A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device also includes a transistor having a source region, a drain region, and a gate region, where the gate region is coupled to the second capacitor plate. The transistor is formed over a second portion of the semiconductor substrate. A well region is disposed in the first and second portions of the semiconductor substrate and has a doping-type that is opposite a doping-type of the semiconductor substrate. Other embodiments are also disclosed. 1. A memory device , comprising:a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate;a transistor having a source region, a drain region, and a gate region, the gate region being coupled to the second capacitor plate; wherein the transistor is formed over a second portion of the semiconductor substrate; anda well region disposed in the first and second portions of the semiconductor substrate and having a doping-type that is opposite a doping-type of the semiconductor substrate.2. The memory device of claim 1 , further comprising:control circuitry configured to store a first data value in the memory cell by applying a voltage difference across the control gate and the well region, wherein the control gate receives a higher voltage than the well region while the voltage difference is applied to store the first data value; andwherein the control circuitry is further configured to store a second data value in the memory cell by applying the voltage difference across the control gate and the well region, wherein the control gate receives a lower voltage than the well ...

Подробнее
Номер записи: 23
02-02-2012 дата публикации

ELECTRONIC DEVICE

Номер: US20120027928A1
Автор: Otremba Ralf
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 μm. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 μm. 1. A method , comprising:providing a metallic body;depositing a first electrically insulating layer on the metallic body from a gas phase;depositing a first thermally conductive layer on the first electrically insulating layer, the first thermally conductive layer having a thermal conductivity of more than 50 W/(m·K); anddepositing a second electrically insulating layer on the first thermally conductive layer from a gas phase.2. The method of claim 1 , comprising wherein the first thermally conductive layer is electrically conductive.3. The method of claim 1 , comprising depositing a second thermally conductive layer on the second electrically insulating layer claim 1 , the second thermally conductive layer having a thermal conductivity of more than 50 W/(m·K).4. The method of claim 1 , comprising depositing a third electrically insulating layer on the second electrically insulating layer from a gas phase.5. A method claim 1 , comprising:providing a metallic body;depositing a first electrically insulating material on the metallic body from a gas phase; anddepositing a second electrically insulating material on the first electrically insulating material from a gas phase.6. The method of claim 5 , comprising wherein one of the first material and the second material is an epoxy material claim 5 , a duroplast material or an imide material and the other of the first material and the second material is a metal oxide material claim 5 , a semiconductor oxide material claim 5 , a ceramic material or a ...

Подробнее
Номер записи: 24
02-02-2012 дата публикации

SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF

Номер: US20120028382A1
Автор: Bauer Michael, Fuergut Edward
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. 1. A method for producing a semiconductor device , comprising:producing a semiconductor wafer with semiconductor device positions arranged in rows and columns for semiconductor devices in flip-chip technology with contact areas on an active top side including flip-chip contacts;applying an electrically insulating layer as underfill material to the active top side of the semiconductor wafer while covering the flip-chip contacts, the electrically insulating layer comprising a UV B-stageable material;applying a patterned mask on the active top side of the semiconductor wafer;exposing the mask by means of UV radiation, so that the flip-chip contacts are not exposed and at least a surface of the exposed regions is brought to a cured intermediate state;removing the unexposed regions of the layer while leaving free at least a tip of the flip-chip contacts; andseparating the semiconductor wafer into individual semiconductor devices.2. The method according to claim 1 , comprising evaporating solvent after the application of the electrically insulating layer.3. The method according to claim 1 , wherein before the wafer is separated into individual semiconductor devices claim 1 , testing the functionality of the semiconductor devices in the semiconductor device positions via the external contact tips.4. The method according to claim 1 , comprising applying the electrically insulating layer by spin-coating claim 1 , dispensing claim 1 , spraying on claim 1 , jet printing methods claim 1 , stencil printing methods or dipping methods.5. The method according to claim 1 , comprising:providing a rewiring ...

Подробнее
Номер записи: 25
02-02-2012 дата публикации

SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME

Номер: US20120028417A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode. 1. A method for producing a plurality of semiconductor chips for semiconductor components with cell structures , comprising:patterning a semiconductor wafer composed of a monocrystalline semiconductor body with cell structures for MOSFETs, IGBTs or JFETs with a lateral or vertical drift path arranged between a first region of the semiconductor body for a first cell electrode and a second region of the semiconductor body for a second cell electrode, wherein the first region has a surrounding body zone with semiconductor material doped complementarily to the drift path, which body zone can be activated by a cell control electrode in interaction with a component control electrode;arranging the cell structures in semiconductor chip positions to form a first active cell array provided below a first or a second component electrode; andarranging the cell structures in at least one partial region of the semiconductor chip positions to form a second active cell array of the partial region, the array being provided below a component control electrode.2. The method of claim 1 , wherein arranging the cell structures comprises ...

Подробнее
Номер записи: 26
02-02-2012 дата публикации

RADIO COMMUNICATION DEVICES, INFORMATION PROVIDERS, METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE AND METHODS FOR CONTROLLING AN INFORMATION PROVIDER

Номер: US20120028638A1
Автор: Mueck Markus Dominik, Schmidt Andreas
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a radio communication device may be provided. The radio communication device may include a first receiver configured to receive from a first cell first data representing a content encoded using a first codec; a second receiver configured to receive from a second cell second data representing the content encoded using a second codec; and a combiner configured to combine the first data and the second data. 1. A radio communication device , comprising:a first receiver configured to receive from a first cell first data representing a content encoded using a first codec;a second receiver configured to receive from a second cell second data representing the content encoded using a second codec;a combiner configured to combine the first data and the second data.2. The radio communication device of claim 1 , further comprising:a decoder configured to decode the combined data;a reception discontinuation determiner configured to determine whether the first receiver stops receiving the first data and to determine whether the second receiver stops receiving the second data;wherein the decoder is further configured to decode the first data when the reception discontinuation determiner determines that the second receiver stops receiving the second data, andwherein the decoder is further configured to decode the second data when the reception discontinuation determiner determines that the first receiver stops receiving the first data.3. The radio communication device of claim 1 , further comprising:a further receiver configured to receive from a further cell further data representing the content encoded using a further codec.4. The radio communication device of claim 1 , further comprising:a locator configured to determine the position of the radio communication device.5. The radio communication device of claim 1 , further comprising:an available cell determiner configured to determine, whether a predetermined cell is available for the radio communication device. ...

Подробнее
Номер записи: 27
02-02-2012 дата публикации

Safe Memory Storage By Internal Operation Verification

Номер: US20120030531A1
Автор: Brewerton Simon, Eder Alfred, Hastie Neil, Hubbert Paul, Oberlaender Klaus, Vilela Antonio, Wiesner Robert
Принадлежит: INFINEON TECHNOLOGIES AG

The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous. 1. A memory block , comprisinga host processing unit configured to provide a memory operation request comprising a requested memory address;a first memory array having a plurality of address lines;a first address decoder configured to receive the requested memory address and to and to selectively activate a respective address line associated with the requested memory address; andan address signature generator configured to receive the memory operation request and further configured to generate an address signature based upon the activated address line and to compare the generated address signature and the requested memory address,wherein an error signal is generated if the address lines of the generated address signature are not the same as the address lines of the requested memory address.2. The memory block of claim 1 , wherein the address signature generator comprises:a second memory array configured to store additional address information; andan address comparator configured to receive the generated address ...

Подробнее
Номер записи: 28
09-02-2012 дата публикации

INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT

Номер: US20120032255A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. 1. A vertical component comprising:a semiconductor body of a first conductivity type, having a first main surface and a second main surface opposite the first main surface;a first electrode arranged on the first main surface;a second electrode arranged on the second main surface;a semiconductor substrate of the first conductivity type, the semiconductor substrate adjoining the second electrode;a first zone of the first conductivity type, the first zone adjoining the first electrode;a body zone of a second conductivity type, the body zone adjoining the first electrode;a drift zone of the first conductivity type that lies between the semiconductor substrate and the body zone; andat least one compensation region located in the drift zone configured continuously in a connection direction between the first and the second electrode in pillar-type fashion and extending with its longitudinal direction parallel to a connecting direction between the first and the second electrode, wherein the compensation region has a tapering cross-sectional area in the direction toward the second electrode.2. The vertical component of claim 1 , comprising:where the drift zone is weakly doped relative to the first zone and the body zone.3. The vertical component as claimed in claim 1 , comprising:wherein the compensation region extends in the drift zone proceeding from the body zone toward the semiconductor substrate only to an extent such that a pedestal region of the drift zone remains between the end of the compensation region and the semiconductor substrate and in a manner adjoining the latter.4. The vertical component as claimed in claim 3 ,wherein a thickness of the ...

Подробнее
Номер записи: 29
09-02-2012 дата публикации

ELECTRONIC DEVICE WITH CONNECTING STRUCTURE

Номер: US20120032260A1
Автор: Hirler Franz, Zundel Markus
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device including a connecting structure includes an edge region, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region. 1. A semiconductor device including a connecting structure comprising:an edge region;a first trench and a second trench running toward the edge region;a first electrode within the first trench; anda second electrode within the second trench;wherein the first and second electrodes are arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches;wherein the first electrode extends, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region; andwherein the first electrode is connected to a connection structure for a first potential, and the second electrode is connected to a connection structure for a second potential.2. The semiconductor device of claim 1 , wherein the connection structure for the first potential contacts the first electrode in a region which extends further to the edge region.3. The semiconductor device of claim 1 , wherein the first trench extends farther toward the edge region than do/does the second electrode and/or the second trench.4. The semiconductor device of claim 1 , further comprising a further edge region which is essentially opposite the edge region claim 1 , and wherein the second electrode claim 1 , at an end of the second trench ...

Подробнее
Номер записи: 30
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Подробнее
Номер записи: 31
09-02-2012 дата публикации

Controller for a Resonant Switched-Mode Power Converter

Номер: US20120033453A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment, a switch controller for a switched-mode power supply includes an oscillator, an advance timing generator, and a dead zone generator. The advance timing generator generates an advance timing output pulse having a first pulse width that is asserted when the oscillator reaches a first phase. The dead zone generator produces a dead zone output having a second pulse width when the advance timing output pulse is de-asserted. This dead zone output pulse is coupled to a freeze input of the oscillator that freezes the phase accumulation of the oscillator when asserted. The controller also has a primary switch logic circuit that produces primary switch drive signals having a dead zone coincident with the dead zone output, and a secondary switch logic circuit that generates a secondary switch drive signal that is de-asserted when the advance timing output pulse becomes asserted. 1. A switch controller for a switched-mode power supply , the controller comprising:an oscillator comprising a freeze input, wherein the oscillator stops accumulating phase when the freeze input is asserted;an advance timing generator configured to generate an advance timing output pulse having a first pulse width, the advance timing generator configured to assert a pulse when the oscillator reaches a first phase; the dead zone timing generator is configured to generate a pulse when the advance timing output pulse is de-asserted, and', 'the dead zone output is coupled to the freeze input of the oscillator., 'a dead zone timing generator configured to generate a dead zone output having a second pulse width, wherein'}a primary switch logic circuit configured to generate primary switch drive signals for primary power supply switches, the switch drive signals having a dead zone coincident with the dead zone output; anda secondary switch logic circuit configured to generate secondary switch drive signals for secondary power supply switches, wherein at least one of the ...

Подробнее
Номер записи: 32
09-02-2012 дата публикации

Communication devices, method for data communication, and computer program product

Номер: US20120033621A1
Автор: Markus Dominik Mueck
Принадлежит: INFINEON TECHNOLOGIES AG

A communication device is described comprising a transceiver, a determining circuit configured to determine whether the communication device may use radio resources, which are allocated to be used by a wireless bidirectional communication system in the geographical region in which the communication device is located, for radio data communication without participation by the wireless bidirectional communication system, and a controller configured to control the transceiver to carry out radio data communication using the radio resources if the communication device may use the radio resources.

Подробнее
Номер записи: 33
09-02-2012 дата публикации

Device, method for displaying a change from a first picture to a second picture on a display, and computer program product

Номер: US20120036483A1
Автор: Christian Erben, Michael Soegtrop
Принадлежит: INFINEON TECHNOLOGIES AG

A device is described having a memory storing data specifying a change animation between pictures to be displayed successively on the display, a setting circuit configured to store a setting specifying that a change animation between pictures to be displayed successively on the display is to be carried out in accordance with the specification of the change animation given by the data, a display controller configured to control a display to display a first picture, a detector configured to detect an event which triggers that a second picture is to be displayed on the display, a determination circuit configured to read the setting and to determine, based on the setting, a change animation between the first picture and the second picture, wherein the display controller is configured to control the display to display the change animation, and, after the change animation, to display the second picture.

Подробнее
Номер записи: 34
16-02-2012 дата публикации

Silicone Carbide Trench Semiconductor Device

Номер: US20120037920A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench. 1. A semiconductor device , comprising:a silicon carbide semiconductor body;a trench extending into the silicon carbide semiconductor body at a first surface;a gate dielectric and a gate electrode within the trench;a body zone of a first conductivity type adjoining to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone;an extension zone of the first conductivity type electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction; and whereina distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.2. The semiconductor device of claim 1 , whereina width of an upper part of the ...

Подробнее
Номер записи: 35
16-02-2012 дата публикации

Transistor Component with Reduced Short-Circuit Current

Номер: US20120037955A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency γ of less than 0.7. 1. A transistor component , comprising:in a semiconductor body a source zone and a drift zone of a first conduction type;a body zone of a second conduction type complementary to the first conduction type, the body zone being arranged between the drift zone and the source zone;a source electrode in contact with the source zone and the body zone;a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer; a first emitter zone adjoining the drift zone in the semiconductor body; and', 'a second emitter zone of the first conduction type adjoining the first emitter zone, the second emitter zone being connected to the source electrode and having an emitter efficiency γ of less than 0.7., 'a diode structure connected between the drift zone and the source electrode and which comprises2. The transistor component as claimed in claim 1 , wherein the emitter efficiency of the second emitter zone is less than 0.5 or less than 0.3.3. The transistor component as claimed in claim 1 , wherein the first emitter zone comprises a monocrystalline semiconductor material. ...

Подробнее
Номер записи: 36
16-02-2012 дата публикации

REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD

Номер: US20120038063A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. 1. A device , comprising:a first body comprising a first semiconductor chip and a first metal layer;a second body comprising a second semiconductor chip and a second metal layer, wherein the first body is attached to the second body along a first plane; andan electrically conductive bulge arranged in the first plane and attaching the first metal layer to the second metal layer.2. The device of claim 1 , comprising wherein the first semiconductor chip is embedded in a first electrically insulating material claim 1 , the second semiconductor chip is embedded in a second electrically insulating material claim 1 , and the first electrically insulating material is attached to the second electrically insulating material along the first plane.3. The device of claim 2 , comprising wherein the first electrically insulating material is a mold material or a laminate material.4. The device of claim 1 , comprising wherein the bulge is made of an electrically conductive adhesive.5. The device of claim 1 , comprising wherein the bulge is made by electrochemically depositing an electrically conductive material.6. The device of claim 1 , comprising wherein an adhesive material or an underfiller material is arranged between the first body and the second body along the first plane.7. The device of claim 1 , comprising wherein a dielectric material is placed over the bulge.8. A device claim 1 , comprising:a first body comprising a first semiconductor chip and a first metal layer;a second body comprising a second semiconductor chip and a ...

Подробнее
Номер записи: 37
16-02-2012 дата публикации

METHOD AND DEVICE INCLUDING TRANSISTOR COMPONENT HAVING A FIELD ELECTRODE

Номер: US20120040505A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench. 1. A method of forming a transistor component , including:providing a semiconductor arrangement including: a semiconductor body having a first side and at least one first trench extending from the first side, the at least one first trench having sidewalls and lower and upper trench sections, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric;forming a dielectric layer on the first field electrode in the at least one first trench, forming the dielectric layer including a deposition process that deposits a dielectric material on the first side of the semiconductor body and on the first field electrode at a higher deposition rate than on sidewalls of the at least one first trench;forming a gate dielectric, the gate dielectric at least lining the sidewalls in the upper trench section of the at least one first trench; andforming a gate electrode in the upper trench section, the gate electrode being insulated from the first field electrode by the dielectric layer.2. The method of claim 1 , wherein forming the dielectric layer further includes:producing a protection layer covering the dielectric layer in the at least one first trench and on the first side, the protection layer completely filling the at least one first ...

Подробнее
Номер записи: 38
16-02-2012 дата публикации

Transceiver with Interferer Control

Номер: US20120040628A1
Автор: Krug Erwin, Laaser Peter, Wang Jiang
Принадлежит: INFINEON TECHNOLOGIES AG

Some embodiments of the present disclosure relate to a transceiver that includes multiple communication subunits associated with multiple communication protocols, respectively. The transceiver includes a conflict detection and control unit that determines whether interference is present or anticipated to occur between two or more of the communication subunits. If interference is present or anticipated, a local oscillator (LO) tuning unit changes an LO frequency provided to at least one of the two or more communication units. For example, in some embodiments, the LO tuning unit changes the LO frequency from high-side injection to low-side injection, or vice versa, or changes the intermediate frequency (IF) associated with a given communication subunit. In these ways, the techniques disclosed herein limit signal degradation due to interference from communication subunits residing within the transceiver. 1. A communication device , comprising:a first communication unit to transmit or receive a first signal over a first frequency channel via a first communication path in the communication device;a second communication unit to transmit or receive a second signal over a second frequency channel via a second communication path in the communication device, wherein the second communication unit provides an LO signal to the second communication path, which frequency converts the second signal; anda conflict detection and control unit to determine whether present or anticipated communication for the first communication unit interferes with present or anticipated communication for the second communication unit and selectively adjust a frequency of the LO signal based on whether interference is present or anticipated from the first to the second communication unit.2. The communication device of claim 1 , wherein the conflict detection and control unit analyzes whether interference is present or anticipated by evaluating whether a fundamental or harmonic frequency of the LO ...

Подробнее
Номер записи: 39
16-02-2012 дата публикации

Asymmetric Segmented Channel Transistors

Номер: US20120042296A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. 1. A method of designing an integrated circuit , the method comprising:designing a first transistor comprising a first threshold voltage, a first gate length and a first width;designing a second transistor comprising a second threshold voltage, a second gate length and a second width, wherein the first gate length is smaller than the second gate length, wherein the first threshold voltage is higher than the second threshold voltage;designing an asymmetric transistor by combining the first transistor and the second transistor, wherein the combining comprises electrically coupling a drain of the first transistor and a source of the second transistor and electrically coupling a gate of the first transistor with a gate of the second transistors, wherein, under a forward bias, the asymmetric transistor has a voltage gain higher than a symmetric long channel transistor having a gate length longer than a sum of the first and the second gate lengths.2. The method of claim 1 , further comprising replacing a symmetric transistor in a current mirror circuit with the asymmetric ...

Подробнее
Номер записи: 40
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Подробнее
Номер записи: 41
23-02-2012 дата публикации

TIME-TO-DIGITAL CONVERTER WITH BUILT-IN SELF TEST

Номер: US20120044102A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices. 1. An apparatus , comprising:a first input;a second input;a time-to-digital converter, said time-to-digital converter comprising a first time-to-digital converter input, a second time-to-digital converter input, a first oscillator, and a second oscillator;a first multiplexer, a first input of said first multiplexer being coupled with said first input, a second input of said first multiplexer being coupled with an output of said first oscillator, and an output of said first multiplexer being coupled with said first time-to-digital converter input;a second multiplexer, a first input of said second multiplexer being coupled with said second input, a second input of said second multiplexer being coupled with an output of said second oscillator, and an output of said second multiplexer being coupled with said second time-to-digital converter input; andevaluation logic coupled to an output of said time-to-digital converter.2. The apparatus of claim 1 , wherein said first oscillator and said second oscillator are free running oscillators.3. The apparatus of claim 1 , wherein said first oscillator is configured to output a signal with a first frequency and said second oscillator is configured to output a signal with a second frequency different from said first frequency.4. The apparatus of claim 3 , wherein said second frequency differs from said first frequency by at most 20%.5. The apparatus of claim 1 , wherein said evaluation ...

Подробнее
Номер записи: 42
01-03-2012 дата публикации

Method for Forming a Semiconductor Device, and a Semiconductor with an Integrated Poly-Diode

Номер: US20120049270A1
Автор: Anton Mauder, Frank Pfirsch, Franz Hirler, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

Подробнее
Номер записи: 43
01-03-2012 дата публикации

DEPLETION MOS TRANSISTOR AND CHARGING ARRANGEMENT

Номер: US20120049273A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A depletion transistor includes a source region and a drain region of a first conductivity type, a channel region of the first conductivity type arranged between the source region and the drain region and a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric. The depletion transistor further includes a first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential. The depletion transistor can be included in a charging circuit. 1. A depletion transistor comprising:a source region and a drain region of a first conductivity type;a channel region of the first conductivity type arranged between the source region and the drain region;a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric; anda first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential.2. The depletion transistor of claim 1 , wherein the discharge region is arranged distant to the source region.3. The depletion transistor of claim 1 , wherein the terminal for the reference potential is the gate electrode.4. The depletion transistor of claim 1 , further comprising:a semiconductor body with a first and a second surface in which the source region, the drain region, the channel region and the discharge region are arranged,wherein the first gate electrode is arranged in at least one trench extending from the first surface in a vertical direction of the semiconductor body.5. The depletion transistor of claim 4 , wherein the first gate electrode is arranged between the source region and the discharge region.6. The depletion transistor of claim 4 , wherein the first gate electrode has a substantially ring-shaped geometry.7. The depletion transistor of claim 6 , wherein ...

Подробнее
Номер записи: 44
01-03-2012 дата публикации

Trench Structures in Direct Contact

Номер: US20120049274A1
Автор: Elattari Brahim, Hirler Franz
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor structure includes a semiconductor substrate of a first conductivity, an epitaxial layer of a second conductivity on the substrate and a buried layer of the second conductivity interposed between the substrate and the epitaxial layer. A first trench structure extends through the epitaxial layer and the buried layer to the substrate and includes sidewall insulation and conductive material in electrical contact with the substrate at a bottom of the first trench structure. A second trench structure extends through the epitaxial layer to the buried layer and includes sidewall insulation and conductive material in electrical contact with the buried layer at a bottom of the second trench structure. A region of insulating material laterally extends from the conductive material of the first trench structure to the conductive material of the second trench structure and longitudinally extends to a substantial depth of the second trench structure. 1. A semiconductor structure comprising:a semiconductor substrate of a first conductivity;an epitaxial layer of a second conductivity on the substrate;a buried layer of the second conductivity interposed between the substrate and the epitaxial layer;a first trench structure extending through the epitaxial layer and the buried layer to the substrate, the first trench structure including sidewall insulation and conductive material in electrical contact with the substrate at a bottom of the first trench structure;a second trench structure extending through the epitaxial layer to the buried layer, the second trench structure including sidewall insulation and conductive material in electrical contact with the buried layer at a bottom of the second trench structure; anda region of insulating material laterally extends from the conductive material of the first trench structure to the conductive material of the second trench structure and longitudinally extends to a substantial depth of the second trench structure.2. The ...

Подробнее
Номер записи: 45
01-03-2012 дата публикации

High Voltage Semiconductor Devices

Номер: US20120049279A1
Автор: Cornelius Christian Russ, Harald Gossner, Maryam Shojaei Baghini, Mayank Shrivastava, Ramgopal Rao
Принадлежит: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY, INFINEON TECHNOLOGIES AG

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Подробнее
Номер записи: 46
01-03-2012 дата публикации

INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR ARRANGEMENT AND METHOD FOR PRODUCING IT

Номер: US20120049325A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

An integrated circuit having a semiconductor component arrangement and production method is disclosed. In one embodiment, an oxide layer region is provided as a protection against oxidation in the edge region on the surface region of an underlying semiconductor material region. 1. An integrated circuit having a semiconductor component arrangement comprising:a semiconductor material region having a surface region;an arrangement of one or more semiconductor components is formed in a central region of the semiconductor material region;a passivation layer region formed on the surface region in an edge region, the passivation layer region being configured to realize a field distribution at the edge of the semiconductor component arrangement; and whereinthe passivation layer region is formed with a base layer including hydrogen containing amorphous carbon at the bottom and directly adjoining the semiconductor material region;an oxide layer region is provided as a protection against oxidation on and in direct contact with the surface region of the semiconductor material region in the edge region;the passivation layer region is formed between the oxide layer region and the central region;the oxide layer region or a part of the oxide layer region is formed in direct contact with one or more channel stopper regions, a channel stopper region being formed as a doped zone or as a plurality of doped zones of a first conductivity type in the surface region of the semiconductor material region; anda doped zone or a VLD zone having a varying doping of a second conductivity type, namely one that decreases toward the edge of the semiconductor material region, is formed in the surface region of the semiconductor material region in the transition between the central region and the edge region of the semiconductor material region, the doped zone or VLD zone reaching as far as the one or more channel stopper regions.2. The integrated circuit of claim 1 , wherein at least part of the oxide ...

Подробнее
Номер записи: 47
01-03-2012 дата публикации

Integrated Circuit Including Interconnect Levels

Номер: US20120049373A1
Автор: Finke Benjamin, Gietler Herbert, Zojer Gerhard
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area. 1. An integrated circuit , comprising:at least first, second, third and fourth interconnect levels; whereinthe first interconnect level includes a plurality of first interconnect areas electrically coupled to a first terminal of a semiconductor device formed within a semiconductor substrate and further includes a plurality of second interconnect areas electrically coupled to a second terminal of the semiconductor device;the second interconnect level includes a third interconnect area, the third interconnect area including a plurality of first openings;the third interconnect level includes a fourth interconnect area, the fourth interconnect area including a plurality of second openings;the fourth interconnect level includes a first contact area and a second contact area, the first contact area being electrically coupled to the first interconnect areas of the first interconnect level via the fourth interconnect area and first contacts extending through the plurality of first openings in the third interconnect area, the second contact area being electrically coupled to the second interconnect areas of the first interconnect level via the third interconnect area and second contacts extending through the plurality of second openings in the fourth interconnect area.2. The integrated circuit of claim 1 , whereinthe first interconnect areas include first metal lines extending ...

Подробнее
Номер записи: 48
01-03-2012 дата публикации

Crack Sensors for Semiconductor Devices

Номер: US20120049884A1
Автор: Kaltalioglu Erdem
Принадлежит: INFINEON TECHNOLOGIES AG

Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure. 1. A method of testing a semiconductor device , the method comprising:providing the semiconductor device, the semiconductor device comprising at least one integrated circuit including a crack sensor disposed proximate a perimeter of the at least one integrated circuit, the crack sensor comprising a conductive structure disposed in at least one conductive material layer of the integrated circuit, the conductive structure comprising a first end and a second end, the crack sensor including a first terminal coupled to the first end of the conductive structure and a second terminal coupled to the second end of the conductive structure; andtesting for a presence of a crack in the at least one integrated circuit by making electrical contact to a portion of the crack sensor.2. The method according to claim 1 , wherein the testing for the presence of the crack comprises applying a voltage across the first terminal and the second terminal of the crack sensor claim 1 , and determining if a current passes through the crack sensor.3. The method according to claim 2 , wherein a crack is detected in the at least one integrated circuit if the current does not pass through the crack sensor when the voltage is applied across the first terminal and the second terminal of the crack sensor.4. The method according to claim 1 , wherein providing the semiconductor device comprises ...

Подробнее
Номер записи: 49
01-03-2012 дата публикации

CIRCUIT WITH NOISE SHAPER

Номер: US20120049907A1
Автор: DA DALT Nicola, Thaller Edwin
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping. 1. A circuit , comprising:an oscillator configured to generate an output signal having a frequency,a feedback value generator coupled to said oscillator configured to generate a feedback value depending on said output signal,a reference value generator comprising a noise shaper circuit configured to generate a noise shaped reference value depending on a predetermined value,a combiner configured to combine said noise shaped reference value and said feedback value and to output a combined signal, anda loop filter configured to generate a control signal to control said oscillator based on said combined signal,wherein said reference value generator is further configured to generate said noise shaped reference value independent of signal values in a path from said combiner to said oscillator via said loop filter and independent of signal values in a path from said oscillator to said combiner via said feedback value generator.2. The circuit of claim 1 ,wherein said predetermined value determines a relationship between a frequency of a reference clock and said frequency of said output signal.3. The circuit of claim 1 ,wherein said predetermined value comprises at least one first value and at least one second value,wherein said reference value comprises at least one first reference value and at least one second reference value,wherein said reference value generator is configured to generate said first reference value depending on said first value without using said noise shaper circuit and to generate said second reference value depending on said at least one second value using said noise shaper circuit.4. The circuit of claim 1 ,wherein said loop filter comprises a modulator configured to modulate said control signal based on said output ...

Подробнее
Номер записи: 50
01-03-2012 дата публикации

Transponder Power Supply, a Transponder and a Method for Providing a Transponder Power Supply Current

Номер: US20120052798A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A transponder power supply for providing a supply current based on an antenna input signal. The transponder power supply comprises an emergency circuit comprising a charging circuit, an emergency capacitor, and an output stage. The charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage which is higher than a voltage of the antenna input signal. The output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor. 1. A transponder power supply for providing a supply current based on an antenna input signal , the transponder power supply comprising:an emergency circuit comprising a charging circuit, an emergency capacitor and an output stage;wherein the charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage, which is higher than a voltage of the antenna input signal; andwherein the output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor.2. The transponder power supply according to claim 1 ,wherein the output stage comprises a step down converter circuit configured to provide the contribution to the supply current using the charge of the emergency capacitor.3. The transponder power supply according to claim 1 ,wherein the charging circuit comprises a first charge pump coupled to an antenna port for the antenna input signal; andwherein the first charge pump is configured to provide a first charge current to the emergency capacitor based on the antenna input signal.4. The transponder power supply according to claim 3 ,wherein the first charge pump is configured to vary an amount of charge transferred from the antenna input signal to the emergency capacitor in dependence on a charge-pump-adjust signal; andwherein the transponder power supply comprises a charge pump adjuster configured to provide the charge-pump-adjust signal in ...

Подробнее
Номер записи: 51
01-03-2012 дата публикации

DC Power Control for Power Amplifiers

Номер: US20120052823A1
Автор: Andreas Langer
Принадлежит: INFINEON TECHNOLOGIES AG

Some embodiments of the present disclosure relate to transmission techniques that result in power savings relative to previous solutions. These techniques often transmit a signal-of-interest by using two paths, namely, a transmission path (which includes a power amplifier) and a control path. The signal-of-interest is evaluated in “fast-track” fashion on the control path, such that the control path can “tune” a DC supply signal provided to the power amplifier. Thus, when a delayed version of the signal-of-interest is provided over the transmission path to the power amplifier, the DC supply signal provided to the power amplifier helps ensure that the power amplifier has “just enough” DC supply to ensure reliable operation without dissipating excess power. In this way, the techniques disclosed herein help to reduce power consumption in transmitters, thereby potentially helping to extend battery life and reduce undesired heating for users.

Подробнее
Номер записи: 52
08-03-2012 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20120056240A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate. 1. A semiconductor device comprising:a baseplate;a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate;a first and a second diode substrate coupled to the baseplate;a first, a second, and a third control substrate coupled to the baseplate;bond wires coupling the first and second IGBT substrates to the first control substrate;bond wires coupling the first and second IGBT substrates to the second control substrate via the first and second diode substrates; andbond wires coupling the first and second IGBT substrates to the third control substrate via the second diode substrate.2. The semiconductor device of claim 1 , wherein the first IGBT substrate and the second IGBT substrate are identical.3. The semiconductor device of claim 1 , wherein the first diode substrate and the second diode substrate are identical.4. The semiconductor device of claim 1 , wherein the first control substrate claim 1 , the second control substrate claim 1 , and the third control substrate are identical.5. The semiconductor device of claim 1 , wherein the first control substrate provides an auxiliary collector control pad claim 1 ,wherein the second control substrate provides an auxiliary emitter control pad, andwherein the third control substrate provides a gate control pad.6. The semiconductor device ...

Подробнее
Номер записи: 53
08-03-2012 дата публикации

Method and Apparatus for Defined Magnetizing of Permanently Magnetizable Elements and Magnetoresistive Sensor Structures

Номер: US20120056615A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

An apparatus includes a sensor arrangement with a sensor chip. A magnetic field generator is configured to generate a secondary magnetic field opposing an external primary magnetic field at the sensor chip. The magnetic field generator protects the sensor arrangement against the external primary magnetic field. 1. A method of monitoring alignment of a magnetic field of a reference magnet with respect to a magnetic field sensor structure comprising a magnetic field main sensor structure and an associated magnetic field auxiliary sensor structure , the method comprising:detecting the magnetic field penetrating the magnetic field sensor structure and providing a reference signal based on the magnetic field by the magnetic field auxiliary sensor structure; anddetermining a deviation of the alignment of the magnetic field of the reference magnet by comparing the reference signal with a set signal corresponding to a predetermined magnetic field distribution of the magnetic field in a detection plane of the magnetic field auxiliary sensor structure.2. The method according to claim 1 , wherein the magnetic field auxiliary sensor structure is a Hall sensor claim 1 , and the magnetic field main sensor structure is a tunnel magnetoresistance (TMR) claim 1 , a giant magnetoresistance (GMR) or an anisotropic magnetoresistance (AMR) sensor structure.3. A method of protecting a sensor arrangement comprising a sensor chip against an external primary magnetic field claim 1 , the method comprising:generating a secondary magnetic field opposing the external primary magnetic field at the sensor chip.4. The method according to claim 3 , wherein in generating the opposing secondary magnetic field claim 3 , a compensation coil arranged around the sensor chip is electrically excited by a current proportional to the external primary magnetic field.5. The method according to claim 4 , wherein a compensation coil and a primary coil are connected in series and wherein in generating the ...

Подробнее
Номер записи: 54
08-03-2012 дата публикации

TRANSPONDER AND METHOD FOR OPERATING A TRANSPONDER

Номер: US20120056718A1
Автор: Baglin Thomas, Haid Josef, Hofer Robert, Kargl Walter, Leutgeb Thomas, Missoni Albert, Riegebauer Josef, Scheiblhofer Dietmar, Skofitsch Friedrich, Unterlercher Markus, Zimek Bernd
Принадлежит: INFINEON TECHNOLOGIES AG

An RFID transponder having an adjustable response field strength including a determination circuit formed to determine a quantity which is derivable from a field strength of an electromagnetic field prevailing at the location of the RFID transponder, a comparator formed to compare the determined quantity derived from the field strength with a threshold value, wherein the threshold value is based on the adjustable response field strength, which is higher than the minimum field strength required for the operation of the RFID transponder, and a deactivator formed to deactivate a functionality of the RFID transponder if the derived quantity falls below the threshold value. 1. An RFID transponder having an adjustable response field strength , comprising:a determination circuit formed to determine a quantity which is derivable from a field strength of an electromagnetic field prevailing at the location of the RFID transponder;a comparator formed to compare the determined quantity derived from the field strength with a threshold value, wherein the threshold value is based on the adjustable response field strength, which is higher than the minimum field strength required for the operation of the RFID transponder; anda deactivator formed to deactivate a functionality of the RFID transponder if the derived quantity falls below the threshold value.2. The RFID transponder according to claim 1 , wherein the deactivator is formed to deactivate a data communication functionality and/or a CPU functionality of the RFID transponder if the derived quantity falls below the threshold value.3. The RFID transponder according to claim 1 , further comprising an energy load circuit claim 1 , and wherein the determination circuit includes a measurement circuit to detect a residual power signal depending upon part of the energy provided by the electromagnetic field that is not needed by the energy load circuit.4. The RFID transponder according to claim 3 , wherein the measurement circuit is ...

Подробнее
Номер записи: 55
08-03-2012 дата публикации

Polar Transmitter Suitable for Monolithic Integration in SoCs

Номер: US20120057655A1
Автор: Dai Yanzhong, Li Puma Giuseppe, MARSILI Stefano, Thaller Edwin, Van Waasen Stefan
Принадлежит: INFINEON TECHNOLOGIES AG

The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. 1. A transmission circuit configured to transmit over a plurality of transmission signal bands , comprising:a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency;one or more frequency dividers configured to selectively generate one or more reduced frequency signals by selectively dividing the DCO signal;a clock selection circuit configured to receive one of the reduced frequency signals and based thereupon to generate a sampling frequency;a digital to analog converter (DAC) configured to sample a digital amplitude modulated signal at the sampling frequency to generate an analog amplitude modulated signal; anda mixer configured to combine the analog amplitude modulated signal and a phase modulated carrier signal to generate an output signal having a frequency that is outside of the downlink frequencies of other signals within the plurality of transmission signal bands.2. The circuit of claim 1 , wherein the one or more frequency dividers comprise a first frequency ...

Подробнее
Номер записи: 56
08-03-2012 дата публикации

METHOD FOR DEPOSITING METAL ON A SUBSTRATE; METAL STRUCTURE AND METHOD FOR PLATING A METAL ON A SUBSTRATE

Номер: US20120058362A1
Автор: Bradl Stephan, Zistler Markus
Принадлежит: INFINEON TECHNOLOGIES AG

Various embodiments provide a method for depositing metal on a substrate. The method may include carrying out a first immersion plating process, thereby forming a first metal portion on the substrate; providing an immersion plating activating substance on the first metal portion; and carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion. 1. A method for depositing metal on a substrate , the method comprising:carrying out a first immersion plating process, thereby forming a first metal portion on the substrate;providing an immersion plating activating substance on the first metal portion;carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion.2. The method of claim 1 , further comprising:providing an immersion plating activating substance on the substrate before the first immersion plating process is carried out.3. The method of claim 1 ,wherein the first metal portion and the second metal portion comprise the same metal.4. The method of claim 1 ,wherein the immersion plating activating substance has a lower chemical potential than the metal of at least one of the first metal portion and the second metal portion.5. The method of claim 4 ,wherein the immersion plating activating substance comprises a substance selected from a group consisting of: Ag; Al; Co; Cu; Fe; Mn; Mo; Ni; Ni(X)P alloys, wherein X is a metal; Pd; Pt; Rh; Ru; Zn; and an alloy comprising one or more of the above substances.6. The method of claim 1 ,wherein the metal of at least one of the first metal portion and the second metal portion comprises a metal selected from a group of metals consisting of: Au; Ag; Cu; Pt; and Pd.7. The method of claim 1 , further comprising:providing an immersion plating activating substance on the second metal portion;carrying out a third immersion plating ...

Подробнее
Номер записи: 57
08-03-2012 дата публикации

Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures

Номер: US20120058606A1
Автор: Chai Wei Heng, Gerhard Deml, Khai Huat Jeffrey Low, Stanley Job Doraisamy, Wae Chet YONG
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.

Подробнее
Номер записи: 58
15-03-2012 дата публикации

Micro-Electromechanical System Devices

Номер: US20120061734A1
Автор: Gruenberger Robert, Mueller Karl-Heinz, Winkler Bernhard
Принадлежит: INFINEON TECHNOLOGIES AG

Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer. 1. A micro-electromechanical system (MEMS) device , comprising:an semiconductive layer disposed over a substrate;a trench disposed in the semiconductive layer, the trench comprising a first sidewall and an opposite second sidewall;a first insulating material layer disposed over an upper portion of the first sidewall;a conductive material disposed within the trench;a first air gap disposed between the conductive material and the semiconductive layer; anda second air gap disposed over the substrate and the second air gap disposed entirely below a bottom surface of the semiconductive layer.2. The MEMS device of claim 1 , wherein the semiconductive layer comprises upper claim 1 , middle and lower layers claim 1 , the upper layer disposed on the middle layer claim 1 , the middle layer disposed on the lower layer claim 1 , wherein the upper and lower layers comprise a lower conductivity than the middle layer.3. The MEMS device of claim 1 , wherein the first air gap is disposed on the second sidewall and a lower portion of the first sidewall.4. The MEMS device of claim 1 , the first and second air gaps are connected.5. The MEMS device of claim 4 , wherein a third air gap extends over a top surface of the semiconductive layer claim 4 , the top surface being opposite to the bottom surface claim 4 , the third air gap being connected to the first air gap.6. The MEMS device of claim 5 , wherein the third air gap is encapsulated by a second insulating ...

Подробнее
Номер записи: 59
15-03-2012 дата публикации

APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES

Номер: US20120061811A1
Автор: Nelle Peter, Stecher Matthias
Принадлежит: INFINEON TECHNOLOGIES AG

An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. 1. An apparatus comprising:a semiconductor chip;a heat sink plate; anda layer structure comprising at least a diffusion solder layer and a buffer layer, wherein the layer structure is arranged between the semiconductor chip and the heat sink plate, andwherein the buffer layer comprises a ductile material, which is soft in comparison to a material of the diffusion solder layer, and the buffer layer comprises a layer thickness that is greater than 500 nm such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.2. The apparatus of claim 1 , wherein the predetermined values comprises 6 GPa or 50 MPa and the temperature range is between minus 55° C. and 320° C.3. The apparatus of claim 1 , wherein the heat sink plate comprises copper claim 1 , molybdenum or a copper alloy.4. The apparatus of claim 1 , wherein the ductile material of the buffer layer comprises aluminum or aluminum/magnesium.5. The apparatus of claim 1 , wherein the layer structure consists of gold and tin claim 1 , or copper and tin.6. The apparatus of claim 1 , wherein the semiconductor chip comprises silicon or the heat sink plate comprises copper.7. The apparatus of claim 1 , wherein the layer structure comprises a layer comprising aluminum or titanium or tantalum or nickel or magnesium.8. The apparatus ...

Подробнее
Номер записи: 60
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Подробнее
Номер записи: 61
15-03-2012 дата публикации

DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE

Номер: US20120061835A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. 1. A die structure , comprising:a die; anda metallization layer disposed over the front side of the die, the metallization layer comprising copper, wherein at least a part of the metallization layer has a rough surface profile, the part with the rough surface profile including a wire bonding region, to which a wire bonding structure is to be bonded.2. The die structure as claimed in claim 1 ,wherein the metallization layer has a thickness in the range from about 1 μm to about 80 μm.3. The die structure as claimed in claim 1 ,wherein the metallization layer almost completely covers the front side of the die.4. The die structure as claimed in claim 3 ,wherein the entire metallization layer has the rough surface profile.5. The die structure as claimed in claim 1 ,wherein the rough surface profile has a peak-to-peak roughness of at least 0.1 μm.6. The die structure as claimed in claim 5 ,wherein the rough surface profile has a peak-to-peak roughness in the range from about 1 μm to about 5 μm.7. The die structure as claimed in claim 1 ,wherein the metallization layer is made of copper.8. A die arrangement claim 1 , comprising:{'claim-ref': [{'@idref': 'CLM-00001', 'claims 1'}, {'@idref': 'CLM-00007', '7'}], 'a die structure as claimed in one of to ;'}a wire bonding structure bonded to the wire bonding region of the metallization layer of the die structure.9. The die arrangement as claimed in claim 8 ,wherein the wire bonding structure comprises copper.10. A die arrangement claim 8 , comprising:a die;a metallization layer disposed over the front side of the die, wherein at least a part of the metallization layer has a rough surface profile; ...

Подробнее
Номер записи: 62
15-03-2012 дата публикации

Methods for filling a contact hole in a chip package arrangement and chip package arrangements

Номер: US20120061845A1
Автор: Alles Benjamin, Fuergut Edward, Mahler Joachim, Nikitin Ivan
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a method for filling a contact hole in a chip package arrangement is provided. The method may include introducing electrically conductive discrete particles into a contact hole of a chip package; and forming an electrical contact between the electrically conductive particles and a contact terminal of the front side and/or the back side of the chip. 1. A method for filling a contact hole in a chip package arrangement , the method comprising:attaching a chip including a contact terminal to a chip carrier;at least partially encapsulating the chip;introducing electrically conductive discrete particles into a contact hole of a chip package; andforming an electrical contact between the electrically conductive particles and a contact terminal of at least one of a front side and a back side of a chip that is attached to the chip carrier.2. The method of claim 1 ,wherein the electrically conductive discrete particles are coated with electrically conductive material.3. The method of claim 1 ,wherein the electrically conductive discrete particles are coated with at least one of a metal and an intrinsic conductive polymer material.4. The method of claim 1 ,wherein the electrically conductive discrete particles are metal particles.5. The method of claim 1 ,wherein the diameter of the electrically conductive discrete particles is in the range from about 1 nm to about 50 jum.6. The method of claim 1 , further comprising:forming a metalization layer on the upper surface of the chip package such that the metalization layer is in electrical contact with the electrically conductive discrete particles in the contact hole to thereby form an electrical contact between the metalization layer and the contact terminal of at least one of the front side and the back side of the chip via the electrically conductive discrete particles.7. The method of claim 1 , further comprising:partially melting or sintering or curing the electrically conductive particles in such a ...

Подробнее
Номер записи: 63
15-03-2012 дата публикации

Method for Detection of Non-Zero-Voltage Switching Operation of a Ballast of Fluorescent Lamps, and Ballast

Номер: US20120062137A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A method for use in a lamp ballast includes obtaining a measurement signal representative of a voltage at an output of a half-bridge circuit. The half-bridge circuit includes first and second semiconductor switching elements, a resonant circuit connected to the half-bridge circuit, and a snubber capacitance connected in parallel with one of the semiconductor switching elements. The method also includes providing a comparison sinal by comparing heeasurem ment signal with a reference value. The method further includes detecting one of a first type of non-zero-voltage switching operation and a second type of non-zero-voltage switching operation based on evaluations of the comparison signal, wherein the evaluations of the comparison signal occurs in each case before the first semiconductor element is switched on and in each case before the second semiconductor element is switched on. 1. A method for use in a lamp ballast , comprising:a) obtaining a voltage measurement signal representative of a voltage at an output of a half-bridge circuit, the half-bridge circuit including a first and a second semiconductor switching element, a resonant circuit connected to the half-bridge circuit, and a snubber capacitance connected in parallel with one of the semiconductor switching elements;b) providing a comparison signal by comparing the voltage measurement signal with a reference value;c) detecting one of a first type of non-zero-voltage switching operation and a second type of non-zero-voltage switching operation based on evaluations of the comparison signal, wherein the evaluations of the comparison signal occurs in each case before the first semiconductor element is switched on and in each case before the second semiconductor element is switched on.2. The method as claimed in claim 1 , further comprising employing a value that assymetically located between a minimum possible value of the voltage measurement signal and a maximum possible value of the measurement signal as the ...

Подробнее
Номер записи: 64
15-03-2012 дата публикации

Digital Voltage Converter Using A Tracking ADC

Номер: US20120062204A1
Автор: Draxelmayr Dieter
Принадлежит: INFINEON TECHNOLOGIES AG

The disclosed DC-to-DC converter circuit comprises a tracking ADC configured to drive a DC-to-DC converter. In particular, the tracking ADC is configured to receive an analog feedback voltage from the output of the DC-to-DC converter. The analog feedback voltage is compared to an analog reference voltage and based upon the comparison a digital ADC output signal, comprising a digital code, is generated to drive the DC-to-DC converter. The digital ADC output signal is received by the DC-to-DC converter, which is configured to compare the digital code to a target code value. Based upon this comparison, the digital signal drives operation of the DC-to-DC converter by indicating whether the output of the DC-to-DC converter will be adjusted (e.g., by telling the DC-to-DC converter to increase its output voltage, to decrease its output voltage, or to keep its output voltage the same). Other systems and methods are also disclosed. 1. A circuit , comprising:a tracking analog-to-digital (ADC) converter configured to output a digital ADC output signal comprising; anda voltage converter configured to receive the digital ADC output signal and to adjust an output voltage of the voltage converter based thereupon.2. The circuit of claim 1 , wherein the digital ADC output signal comprises a digital code indicative of an adjustment to the output voltage.3. The circuit of claim 2 ,wherein the tracking ADC converter is configured to generate the digital code from a comparison between an analog feedback voltage, based upon the output voltage, and an analog reference voltage; andwherein the voltage converter is configured to compare the digital code to a target code value and to adjust the output voltage based upon the comparison of the digital code and the target code value.4. The circuit of claim 3 , wherein the tracking ADC comprises:a digital to analog converter (DAC) configured to receive an ADC feedback signal comprising the digital code and to output the analog reference signal ...

Подробнее
Номер записи: 65
15-03-2012 дата публикации

Chip Comprising a Radio Frequency Switch Arrangement, Circuit Arrangement and Method for Producing a Radio Frequency Circuit Arrangement

Номер: US20120062306A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A chip includes an RF switch arrangement that has a plurality of RF switches arranged jointly on the chip. Each of the RF switches has at least one first RF connection accessible from outside the chip and one second RF connection accessible from outside the chip. Furthermore, each of the RF switches is designed to activate, in response to a driving, at least one RF path between two of its RF connections. The RF connections of different switches from among the RF switches are separated from one another in terms of radio frequency. 1. A chip comprising a radiofrequency switch arrangement , the chip comprising:a plurality of RF switches arranged jointly on the chip;wherein each of the RF switches from the plurality of RF switches has at least one first RF connection accessible from outside the chip and one second RF connection accessible from outside the chip and is designed to activate, in response to a driving, at least one RF path between two of its RF connections; andwherein the RF connections of different switches from among the RF switches are separated from one another in terms of radio frequency.2. The chip as claimed in claim 1 , further comprising a drive circuit arranged on the chip claim 1 , the drive circuit being designed to provide claim 1 , for each RF switch from the plurality of RF switches claim 1 , a driving in such a way that at any point in time overall at most one RF path of the RF switches of the chip is activated claim 1 , such that simultaneous activation of a plurality of RF paths of the RF switches is avoided.3. The chip as claimed in claim 2 , wherein the drive circuit has a common logic table for driving the RF paths of the RF switches claim 2 , wherein claim 2 , in the logic table claim 2 , table entries are allocated to RF paths of the RF switches in such a way that each table entry is allocated to at most one RF path of the RF switches.4. The chip as claimed in claim 3 ,wherein the drive circuit has a plurality of digital drive ...

Подробнее
Номер записи: 66
15-03-2012 дата публикации

PA Bias Optimization for Modulation Schemes with Variable Bandwidth

Номер: US20120064849A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

One embodiment of the present invention relates to a method for improving the power consumption of a transmission chain by varying the operating point of a power amplifier to optimize (e.g., reduce) the current that is consumed by the amplifier. The operating point is varied by changing the bias voltage(s) (e.g., supply voltage, quiescent voltage) of the amplifier to a predetermined value that is chosen based upon the effect that a given transmitted signal modulation scheme characteristic (e.g., channel bandwidth and/or number of subcarriers) has on the operating point of a power amplifier. For example, if the characteristics indicate a good power amplifier performance the linear output power capability of a power amplifier can be lowered, by changing the bias voltage(s) supplied to the power amplifier, to reduce the output power capability and current consumption of the power amplifier. 1. A transmission circuit , comprising:a first transmission path extending between a signal generator and an antenna, wherein the transmission path is configured to provide a modulated signal to the antenna for transmission using a modulation scheme;a power amplifier, comprised within the first transmission path, configured to receive one or more bias voltages that vary the power amplifier's current consumption; anda control circuit configured to provide one or more predetermined bias voltages to the power amplifier, wherein the one or more predetermined bias voltages are selected based upon one or more characteristics of the modulation scheme to have a value that optimizes the power amplifier's current consumption.2. The transmission circuit of claim 1 , wherein the one or more characteristics of the modulation scheme comprise a number of resource blocks which determine the instantaneous effective bandwidth of the modulation scheme and a channel bandwidth which determines the maximum bandwidth; andwherein the predetermined bias voltage has a value selected to optimize the power ...

Подробнее
Номер записи: 67
22-03-2012 дата публикации

Method for producing a structure element and semiconductor component comprising a structure element

Номер: US20120068260A1
Автор: Poelzl Martin
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body. 1. A method for producing a structure element on a surface of a semiconductor body , the method comprising:providing a semiconductor body having a surface;producing a cutout at the surface, the cutout extending from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface, the cutout having a base and at least one sidewall;producing a first auxiliary layer on the surface of the semiconductor body and in the cutout so that the first auxiliary layer forms a well above the cutout, the well having a well base and at least one well sidewall which forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body;producing a second auxiliary layer within the well at the well base and at the at least one well sidewall, the first auxiliary layer and the second auxiliary layer forming a common surface at an identical surface level, the second auxiliary layer comprising a different material than the first auxiliary layer; andselectively removing regions of the first auxiliary layer which are not covered by the second auxiliary layer.2. A method according to claim 1 , wherein the first auxiliary layer is produced by an HDP process.3. A ...

Подробнее
Номер записи: 68
22-03-2012 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE

Номер: US20120068323A1
Автор: Gooi Boon Huan, Tan Chip King
Принадлежит: INFINEON TECHNOLOGIES AG

A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface. 1. A semiconductor device comprising:a plurality of leads, at least one of the leads comprising a recessed portion on a surface of the lead; anda semiconductor chip being provided in the recessed portion.2. The semiconductor device of claim 1 , wherein the semiconductor device further comprising a layer of bonding material being placed between the semiconductor chip and the recessed portion.3. The semiconductor device of claim 2 , wherein the layer of bonding material comprises an electrically insulating and thermally conductive material.4. The semiconductor device of claim 1 , wherein the semiconductor device further comprising a plurality of wires being attached between the semiconductor chip and the leads.5. The semiconductor device of claim 1 , wherein the semiconductor device further comprising a molding compound covering the semiconductor chip and at least a portion of the leads.6. The semiconductor device of claim 1 , comprising wherein at least one of the leads protrude from the molding compound.7. The semiconductor device of claim 6 , comprising wherein the semiconductor device further comprising a layer of conductive material being provided on the protruding leads.8. An electronic device comprising:a plurality of electrical connection elements, at least one of the electrical connection elements comprising a recessed portion on a surface of the electrical connection element; andan electronic component being provided in the recessed portion.9. The electronic device of claim 8 , comprising wherein the electrical connection elements are in the ...

Подробнее
Номер записи: 69
22-03-2012 дата публикации

LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS

Номер: US20120068345A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. 1. A layer stack , comprising:a carrier;a first metal disposed over the carrier;a second metal disposed over the first metal; anda solder material disposed over the second metal, or a material that provides contact to a solder that is supplied by an external source;wherein the second metal has a melting temperature of at least 1800° C. and is an adhesive layer to the solder material and may substantially not be dissolved in the solder material during a soldering process.2. The layer stack of claim 1 , further comprising:at least one electronic component in or on the carrier.3. The layer stack of claim 1 ,wherein the first metal comprises a metal selected from a group of metals consisting of aluminum; titanium; and an alloy of the mentioned metals.4. The layer stack of claim 1 ,wherein the second metal comprises a metal selected from a group of metals consisting of: tungsten (W), tantalum (Ta), nickel (Ni), iron (Fe), palladium (Pd), cobalt (Co), molybdenum (Mo), manganese (Mn), chromium (Cr), copper (Cu), niobium (Nb), and vanadium (V).5. The layer stack of claim 1 ,wherein the second metal comprises a plurality of metal components;wherein a first metal component of the plurality of metal components comprises a metal selected from a group of metals consisting of: tungsten; tantalum; molybdenum; chromium; niobium; and hafnium; andwherein a second metal component of the plurality of metal components comprises a metal selected from a group of metals ...

Подробнее
Номер записи: 70
22-03-2012 дата публикации

Passivation of Multi-Layer Mirror for Extreme Ultraviolet Lithography

Номер: US20120069311A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A reflector structure suitable for extreme ultraviolet lithography (EUVL) is provided. The structure comprises a substrate having a multi-layer reflector. A capping layer is formed over the multi-layer reflector to prevent oxidation. In an embodiment, the capping layer is formed of an inert oxide, such as AlO, HfO, ZrO, TaO, YO-stabilized ZrO, or the like. The capping layer may be formed by reactive sputtering in an oxygen environment, by non-reactive sputtering wherein the materials are sputtered directly from the respective oxide targets, by non-reactive sputtering of the metallic layer followed by full or partial oxidation (e.g., by natural oxidation, by oxidation in oxygen-containing plasmas, by oxidation in ozone (O), or the like), by atomic level deposition (e.g., ALCVD), or the like. 1. A reflective mask comprising:a substrate formed of a low-thermal expansion material (LTEM);a multi-layer reflector of alternating layers of molybdenum and silicon formed on the substrate; anda capping layer formed in direct contact onto the multi-layer reflector, the capping layer comprising a single layer of an oxide that is chemically inert in an oxidizing environment, said layer of oxide selected from the group consisting of HfO2, Y2O3-stabilized ZrO2, and combinations thereof, the substrate, the multi-layer reflector, and the capping layer forming the reflective mask.2. The reflective mask of claim 1 , wherein the substrate comprises ultra-low expansion (ULE) glass.3. The reflective mask of claim 1 , wherein each pair of alternating layers of molybdenum and silicon is about 6.8 nm in thickness.4. The reflective mask of claim 1 , wherein the capping layer is about 1 nm to about 5 nm in thickness.5. The reflective mask of claim 4 , wherein the substrate comprises ultra-low expansion (ULE) glass.6. The reflective mask of claim 1 , wherein said substrate has a top surface and said multi-layer reflector is formed over and in contact with said top surface.7. A method of forming ...

Подробнее
Номер записи: 71
22-03-2012 дата публикации

METHOD AND DEVICE FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORIES

Номер: US20120069673A1
Автор: Backhausen Ulrich, Kern Thomas, Syassen Joerg
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal. 1. A method comprising:programming data into a non-volatile memory with a first programming mode;generating a control signal; andchanging over the data programming to a second, different programming mode in response to the generated control signal.2. The method of claim 1 , wherein programming in the second programming mode has a shorter programming time and a shorter data retention time in comparison with the first programming load.3. The method of claim 1 , wherein programming in the second programming mode is effected with a smaller number of programming pulses or a higher programming voltage claim 1 , or both claim 1 , compared with the first programming mode.4. The method of claim 1 , wherein claim 1 , in the first programming mode claim 1 , the programming of the memory cells is checked and claim 1 , if appropriate claim 1 , individual memory cells are reprogrammed claim 1 , and wherein claim 1 , in the second programming mode claim 1 , programming is effected without checking and reprogramming.5. The method of claim 1 , wherein the first programming mode is a programming mode in which claim 1 , for programming a data value into a memory cell claim 1 , a programming pulse can be repeated one or a plurality of times claim 1 , and wherein the second programming mode is a programming mode in which claim 1 , for programming a data value claim 1 , a programming pulse is applied only once.6. The method of claim 1 , wherein a memory cell of the non-volatile memory has a field effect transistor with a floating gate for storing information.7. The method of claim 6 , wherein a programming operation for programming a data value into a memory cell comprises Fowler-Nordheim tunneling.8. The method of ...

Подробнее
Номер записи: 72
22-03-2012 дата публикации

MODULE WITH SILICON-BASED LAYER

Номер: US20120070941A1
Автор: Otremba Ralf, Schilz Christof Matthias, Schloegel Xaver
Принадлежит: INFINEON TECHNOLOGIES AG

The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound. 1. A method comprising the steps: providing a carrier element; mounting a semiconductor device on said carrier element; and depositing a silicon-based insulating layer on a side of the carrier element opposite to the side on which the semiconductor device is or is to be mounted.2. The method according to claim 1 , wherein the insulating layer is a silicon carbide layer and/or a silicon oxide layer.3. The method according to claim 1 , wherein the insulating layer is doped with impurity atoms and/or groups of impurity atoms.4. The method according to claim 3 , wherein the impurity atoms and/or the groups of impurity atoms are given by metal atoms and/or oxygen atoms and/or nitrogen atoms and/or hydrogen atoms and/or hydroxide groups.5. The method according to claim 3 , wherein the doping concentration of the impurity atoms and/or groups of impurity atoms is between 0.1% and 10%.6. The method according to claim 1 , wherein the insulating layer is deposited via a chemical vapor deposition (CVD) process.7. The method according to claim 1 , wherein the insulating layer is deposited via a physical vapor deposition (PVD) process.8. The method according to claim 1 , wherein the insulating layer is deposited via plasma pyrolysis.9. A method claim 1 , comprising the steps: providing a semiconductor device; depositing a mold compound on said semiconductor device; and depositing a silicon-based passivation layer on a periphery of said mold ...

Подробнее
Номер записи: 73
22-03-2012 дата публикации

Methods For Forming Contacts in Semiconductor Devices

Номер: US20120070977A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance. 1. A method of manufacturing a semiconductor device , the method comprising:forming an insulating layer over a substrate;coating a first photo resist layer over the insulating layer;using a first mask, patterning the first photo resist layer thereby forming first features oriented in a first direction, the first mask comprising a first plurality of lines oriented in the first direction;after patterning the first photo resist layer, coating a second photo resist layer;using a second mask, patterning the second photo resist layer thereby forming second features oriented in a second direction, wherein the second mask comprises a second plurality of lines oriented in the second direction orthogonal to the first direction, wherein the second mask is aligned relative to the first mask such that the first features are perpendicular to the second features;after patterning the second photo resist layer, coating a third photo resist layer;using a third mask, patterning the third photo resist layer thereby forming third features, wherein the first, the second, and the third features comprise a pattern for forming contact holes; andforming contact holes by etching the insulating layer using the first, the second, and the third features.2. The method of claim 1 , further comprising:freezing the first features after patterning the first photo resist layer, wherein the second photo resist layer is coated after freezing the first features; andfreezing the second ...

Подробнее
Номер записи: 74
22-03-2012 дата публикации

Adaptive Adjustment of Active Area for Power Amplifier

Номер: US20120071120A1
Автор: Camuffo Andrea, Goe Chi-Tao, Mueller Jan-Erik, Pinarello Sandro, Shute Nick
Принадлежит: INFINEON TECHNOLOGIES AG

One embodiment of the present invention relates to a transmission circuit configured to dynamically adjust a number of active transistor cells within a power amplifier based upon a signal quality measurement determined from a feedback. The transmission circuit comprises a transmission chain having a power amplifier configured to provide an output signal. A feedback loop extends from the output of the power, amplifier to a control circuit and is configured to provide measured information about output signal (e.g., phase, amplitude, etc.) to the control circuit. The control circuit utilizes the measured signal information to evaluate a measured signal quality of the output signal. The control circuit dynamically adjusts a number of active transistor cells within a power amplifier based upon a signal quality measurement until the power amplifier is optimized to operate at an operating point for low current and good transmission quality. 1. A transmitter circuit , comprising:a power amplifier, having a plurality of transistor cells that can be selectively activated or de-activated, configured to provide an output signal from a power amplifier output to an antenna; anda control circuit configured to receive information about the output signal from a feedback loop extending from the power amplifier output to the control circuit,wherein the control circuit utilizes the received information to determine a measured signal quality of the output signal, and wherein the control circuit dynamically activates or deactivates a number of the plurality of transistor cells based upon the measured signal quality, thereby optimizing a current consumption of the power amplifier.2. The transmitter circuit of claim 1 , wherein the measured signal quality is evaluated against a predetermined quality threshold value.3. The transmitter circuit of claim 2 , wherein the number of activated transistor cells is reduced if the measured signal quality of the output signal is above the ...

Подробнее
Номер записи: 75
22-03-2012 дата публикации

BASE STATIONS AND RADIO DEVICES

Номер: US20120071190A1
Автор: Bienas Maik, Choi Hyung-Nam
Принадлежит: INFINEON TECHNOLOGIES AG

According to an embodiment, a base station operates a first radio cell of a mobile communication network and signals, for a mobile terminal in the first radio cell having a communication connection via the base station, to a first radio device of a plurality of radio devices located in the first radio cell, wherein each radio device operates a second radio cell, that the first radio device is to provide a communication connection for the mobile terminal. Further, the base station signals, for the mobile terminal, to at least one second radio device of the plurality of radio devices, that the at least one second radio device is to take into account the allocation of radio resources by the first radio device for the communication connection to be provided for the mobile terminal when allocating radio resources for communication within the second radio cell operated by the at least one second radio device. 1. A base station of a mobile communication network , wherein the base station operates a first radio cell of the mobile communication network , the base station comprisinga first signaling circuit configured to signal, for a mobile terminal located in the first radio cell having a communication connection with the mobile communication network via the base station, to a first radio device of a plurality of radio devices located in the first radio cell, wherein each radio device operates a second radio cell of the mobile communication network, that the first radio device is to provide a communication connection between the mobile terminal and the mobile communication network anda second signaling circuit, configured to signal, for the mobile terminal, to at least one second radio device of the plurality of radio devices, that the at least one second radio device is to take into account the allocation of radio resources by the first radio device for the communication connection to be provided for the mobile terminal when allocating radio resources for communication ...

Подробнее
Номер записи: 76
22-03-2012 дата публикации

Method and device for selecting a serving base station, mobile communication network, base station, and method for determining transmission characteristics

Номер: US20120071200A1
Автор: Hyung-Nam Choi, Maik Bienas
Принадлежит: INFINEON TECHNOLOGIES AG

According to one embodiment, a device for selecting a serving base station of a plurality of base stations of a mobile communication system is described which comprises a receiving circuit configured to receive, for each base station of the plurality of base stations, a message including information related to a possible communication between the base station and a mobile terminal and a selecting circuit configured to select, based on the determined information, a base station of the plurality of base stations that is to provide a communication connection for the mobile terminal.

Подробнее
Номер записи: 77
22-03-2012 дата публикации

Identification circuit and method for generating an identification bit using physical unclonable functions

Номер: US20120072476A1
Автор: Marco Bucci, Raimondo Luzzi
Принадлежит: INFINEON TECHNOLOGIES AG

An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Подробнее
Номер записи: 78
22-03-2012 дата публикации

Methods and devices for authorization in collaborative communications sessions

Номер: US20120072503A1
Автор: Frank Kowalewski
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a method for changing a collaborative communications session may be provided. The method may include: sending a request message requesting for authorizing a change of a collaborative communications session to an end device of the collaborative communications session; determining whether an authorization message is received from the end device in response to the request message sent; and changing the collaborative communications session, in case it is determined that an authorization message is received from the end device in response to the request message sent.

Подробнее
Номер записи: 79
22-03-2012 дата публикации

DEVICES AND METHODS FOR MANAGING COLLABORATIVE COMMUNICATIONS SESSIONS

Номер: US20120072504A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a method for providing information for managing a collaborative communications session may be provided. The method may include generating a first message according to a call control protocol; generating a second message according to the call control protocol, the second message including information for managing the collaborative communications session; and sending the first message to a call managing server. The first message may be generated to include the second message. 1. A method for providing information for managing a collaborative communications session , the method comprising:generating a first message according to a call control protocol;generating a second message according to the call control protocol, the second message comprising information for managing the collaborative communications session; andsending the first message to a call managing server;wherein the first message is generated to include the second message.2. The method of claim 1 ,wherein the call control protocol comprises at least one protocol selected from a list of protocols consisting of:Session Initiation Protocol SIP;Real-Time Control Protocol RTCP;Hyper Text Transport Protocol http;File Transfer Protocol FTP;Simple Mail Transfer Protocol SMTP; andXML Configuration Access Protocol XCAP.3. The method of claim 1 ,wherein the second message comprises information for changing an existing communication session.4. The method of claim 1 ,wherein the second message comprises information for initiating a collaborative communications session in a not yet existing communication session.5. The method of claim 1 ,wherein the second message is at least one of a SIP REFER message and a SIP INFO message.6. The method of claim 1 ,wherein the first message comprises information for managing a communication session.7. The method of claim 1 ,wherein a call identifier of the first message and a call identifier of the second message are the same.8. A method for managing a collaborative ...

Подробнее
Номер записи: 80
29-03-2012 дата публикации

MICROELECTROMECHANICAL SENSOR

Номер: US20120073371A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a microelectromechanical system may include a mass element; a substrate; a signal generator; and a fixing structure configured to fix the mass element to the substrate; wherein the mass element is fixed in such a way that, upon an acceleration of the microelectromechanical system, the mass element can be moved relative to the substrate in at least two spatial directions, and wherein a signal is generated by the movement of the mass element by means of the signal generator. 1. A microelectromechanical system , comprising:a mass element;a substrate;a signal generator; anda fixing structure configured to fix the mass element to the substrate;wherein the mass element is fixed in such a way that, upon an acceleration of the microelectromechanical system, the mass element can be moved relative to the substrate in at least two spatial directions, andwherein a signal is generated by the movement of the mass element by means of the signal generator.2. The microelectromechanical system as claimed in claim 1 ,wherein the mass element has a chip with a signal detector and evaluator.3. The microelectromechanical system as claimed in claim 2 ,wherein the chip has a transponder.4. The microelectromechanical system as claimed in claim 1 ,wherein the substrate forms a hollow body, andwherein the mass element is fixed within the hollow body.5. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator comprises coils for generating magnetic effects.6. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator has electrodes for generating capacitive effects.7. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator comprises flexible connecting elements for generating piezoresistive signals.8. The microelectromechanical system as claimed in claim 1 ,wherein the fixing structure configured to fix the mass element comprise elastic connecting elements.9. The microelectromechanical ...

Подробнее
Номер записи: 81
29-03-2012 дата публикации

MICROELECTROMECHANICAL SYSTEM

Номер: US20120073372A1
Автор: Theuss Horst
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a microelectromechanical system may include a chip, a substrate, a signal generator, and a fixing structure configured to fix the chip to the substrate. The chip may be fixed in such a way that, upon an acceleration of the microelectromechanical system, the chip is moved relative to the substrate. Furthermore, a signal may be generated by the movement of the chip by means of the signal generator. 1. A microelectromechanical system , comprising:a chip;a substrate;a signal generator; anda fixing structure configured to fix the chip to the substrate;wherein the chip is fixed in such a way that, upon an acceleration of the microelectromechanical system, the chip is moved relative to the substrate, andwherein a signal is generated by the movement of the chip by means of the signal generator.2. The microelectromechanical system as claimed in claim 1 ,wherein the chip is embodied as a signal detector and evaluator.3. The microelectromechanical system as claimed in claim 1 ,wherein the chip has a transponder.4. The microelectromechanical system as claimed in claim 1 ,wherein the substrate forms a hollow body, andwherein the chip is fixed within the hollow body.5. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator comprises at least one coil for generating magnetic fields.6. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator comprises electrodes configured to generate capacitive effects.7. The microelectromechanical system as claimed in claim 1 ,wherein the signal generator comprises at least one flexible connecting element for generating piezoresistive signals.8. The microelectromechanical system as claimed in claim 1 ,wherein the fixing structure configured to fix the chip comprises elastic connecting elements.9. The microelectromechanical system as claimed in claim 8 ,wherein the fixing structure configured to fix the chip comprises at least one helical spring.10. The ...

Подробнее
Номер записи: 82
29-03-2012 дата публикации

TRANSPONDER INLAY FOR A DOCUMENT FOR PERSONAL IDENTIFICATION, AND A METHOD FOR PRODUCING A TRANSPONDER INLAY

Номер: US20120074228A1
Автор: Gruenauer Matthias, Karl Andreas, Mueller-Hipper Andreas, Pueschner Frank, Scherl Peter
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a transponder inlay for a document for personal identification may include a cover; an adhesive layer arranged on the cover; a chip arranged on the adhesive layer; an antenna connected to the chip; and a top layer on the adhesive layer, wherein the top layer has a top and a bottom and wherein the bottom of the top layer is connected to the cover by means of the adhesive layer and wherein the antenna is arranged on the top of the top layer such that the antenna is at least to some extent physically separated from the adhesive layer by the top layer. 1. A transponder inlay for a document for personal identification , the transponder inlay comprising:a cover;an adhesive layer arranged on the cover;a chip arranged on the adhesive layer;an antenna connected to the chip; anda top layer on the adhesive layer,wherein the top layer has a top and a bottom and wherein the bottom of the top layer is connected to the cover by means of the adhesive layer and wherein the antenna is arranged on the top of the top layer such that the antenna is at least to some extent physically separated from the adhesive layer by the top layer.2. The transponder inlay as claimed in claim 1 ,wherein a further top layer is arranged such that the antenna is at least to some extent arranged between the top layer and the further top layer.3. The transponder inlay as claimed in claim 2 ,wherein the top layer and the further top layer are connected to one another.4. The transponder inlay as claimed in claim 1 ,wherein the adhesive layer is an adhesive film which has hotmelt.5. The transponder inlay as claimed in claim 1 ,wherein the adhesive layer has epoxy resin.6. The transponder inlay as claimed in claim 1 ,wherein the antenna has a coil having at least one turn.7. The transponder inlay as claimed in claim 1 ,wherein the at least one turn of the coil is arranged on the top layer and the top layer has cutouts which are suitable for holding the coil.8. The transponder inlay as ...

Подробнее
Номер записи: 83
29-03-2012 дата публикации

Process for the Simultaneous Deposition of Crystalline and Amorphous Layers with Doping

Номер: US20120074405A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics. 1. A method for the concurrent deposition of multiple crystalline structures on a semiconductor body by means of in-situ differential epitaxy , comprising:forming a preparation surface associated with a semiconductor body, the preparation surface having a first region comprising monocrystalline silicon substrate and a second region comprising an isolating layer; andforming two or more sub-layers, each using different process parameters, to concurrently provide a monocrystalline silicon layer having two or more sub-layers directly on the preparation surface in the first region and an amorphous silicon layer having two or more sub-layers directly on the preparation surface in the second region.2. The method of claim 1 , wherein formation of the two or more sub-layers comprises:depositing a first sub-layer directly on the preparation surface in the first and second region;depositing a second sub-layer over the first sub-layer; anddepositing a third sub-layer over the second sub-layer.3. The method of claim 2 , wherein the first sub-layer is deposited at a first pressure claim 2 , the second sub-layer is deposited at a second pressure claim 2 , and the third sub-layer is deposited at a third pressure.4. ...

Подробнее
Номер записи: 84
29-03-2012 дата публикации

Integrated Circuits and Methods of Design and Manufacture Thereof

Номер: US20120074499A1
Автор: Eller Manfred, Haffner Henning, Lindsay Richard
Принадлежит: INFINEON TECHNOLOGIES AG

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives. 1. An integrated circuit comprising:a first transistor that includes a first gate line disposed in a first region;at least one dummy gate line disposed over a first isolation region adjoining the first region; anda second transistor that includes a second gate line disposed in a second region, wherein no dummy gate line overlies a second isolation region adjoining the second region.2. The integrated circuit of claim 1 , wherein the first transistor and the second transistor each comprise an isolated transistor.3. The integrated circuit of claim 1 , wherein the first gate line is a gate line of a first transistor array in the first region and wherein the second gate line is a gate line of a second transistor array in the second region.4. The integrated circuit of claim 1 , wherein the first transistor comprises an isolated transistor in the first region and wherein the second transistor comprises a transistor in a transistor array in the second region.5. The integrated circuit of claim 1 , wherein the first transistor comprises a transistor in a transistor array in the first region and wherein the second transistor comprises an isolated transistor in the second region.6. An integrated circuit comprising:a first active region disposed in a semiconductor body;a first isolation region adjacent to the first active region;a second active region disposed in the semiconductor body;a second isolation region adjacent to the ...

Подробнее
Номер записи: 85
29-03-2012 дата публикации

Methods of Manufacturing Semiconductor Devices and Structures Thereof

Номер: US20120074536A1
Автор: Beck Michael, Kaltalioglu Erdem
Принадлежит: INFINEON TECHNOLOGIES AG

Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern. 1. A semiconductor device comprising:a workpiece;an etch stop layer disposed over the workpiece, the etch stop layer having a top surface and including a substance having a potential to deleteriously affect a photosensitive material;a first material layer over the etch stop layer, the first material layer including a transition layer adapted to prevent the substance from leaving the top surface of the etch stop layer, wherein the first material layer is patterned with a first pattern in a lower portion and wherein the first material layer is patterned with a second pattern in an upper portion, the second pattern being different than the first pattern; anda second material layer disposed within the first pattern and the second pattern of the first material layer, the second material layer comprising a different material than the first material layer.2. The semiconductor device according to claim 1 , wherein the substance of the etch stop layer comprises nitrogen.3. The semiconductor device according to claim 2 , wherein the etch stop layer comprises SiCN claim 2 , SiNor SiON.4. The semiconductor device according to claim 1 , wherein the transition layer of the material layer comprises an oxide.5. The semiconductor device according to claim 1 , wherein the transition layer is disposed directly above the etch stop layer.6. The ...

Подробнее
Номер записи: 86
29-03-2012 дата публикации

Method and system for minimizing carrier stress of a semiconductor device

Номер: US20120074568A1
Автор: Joachim Mahler, Khalil Hosseini, Manfred Mengel, Oliver EICHINGER
Принадлежит: INFINEON TECHNOLOGIES AG

A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.

Подробнее
Номер записи: 87
29-03-2012 дата публикации

Method for Forming a Through Via in a Semiconductor Element and Semiconductor Element Comprising the Same

Номер: US20120074570A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side thereof. The semiconductor element further includes an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element. The method also includes selectively etching a through via from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer and removing at least partly the etch stop layer, so that the conductive region is exposed to the backside and filling at least partly the through via with a conductive material, wherein the conductive material is electrically isolated from the semiconductor element. 1. A method for forming a through via in a semiconductor element , the method comprising:providing a semiconductor element having an electronic circuitry integrated on or in a main side thereof, the semiconductor element comprising an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element;selectively etching a through hole from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer, thereby exposing a portion of the etch stop layer in the through hole;removing the exposed portion of the etch stop layer in the through hole in order to expose the conductive region to the backside of the semiconductor element; andfilling at least partially the through hole with a conductive material so as to form the through via, wherein the conductive material is electrically connected to the conductive region and electrically isolated from the remaining semiconductor element.2. The method according to claim 1 , further comprising generating an electrically isolating layer on at least the side walls of the ...

Подробнее
Номер записи: 88
29-03-2012 дата публикации

Semiconductor structure and method for making same

Номер: US20120074572A1
Автор: Andreas STUECKJUERGEN, Juergen Foerster, Thomas Fischer, Werner Robl
Принадлежит: INFINEON TECHNOLOGIES AG

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Подробнее
Номер записи: 89
29-03-2012 дата публикации

CHIP, METHOD FOR PRODUCING A CHIP AND DEVICE FOR LASER ABLATION

Номер: US20120074598A1
Автор: Kalz Franz-Peter
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation. 1. A chip , comprising:a substrate; anda coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation;wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation.2. The chip as claimed in claim 1 ,wherein the chip is a semiconductor chip.3. The chip as claimed in claim 2 ,wherein the chip comprises an MEMS or an MOEMS.4. The chip as claimed in claim 1 ,wherein the laser detector layer is a florescent layer.5. The chip as claimed in claim 4 ,wherein the florescent layer is a stilbene layer.6. The chip as claimed in claim 1 ,wherein the chip comprises a contact area; andwherein the coating covers the contact area at least partially.7. The chip as claimed in claim 1 ,wherein the coating is a polymer layer.8. The chip as claimed in claim 7 ,wherein the coating is of parylene.9. A device for laser ablation claim 7 , comprising:a laser, the laser being arranged for stripping a coating from a chip; anda detector, the detector being designed for detecting a detector signal which is emitted by a laser detector layer applied to the chip.10. The device for laser ablation as claimed in claim 9 ,wherein the detector is a photodiode; andwherein the detector signal is a light signal.11. The device for laser ablation as claimed in claim 9 ,wherein the device for laser ablation comprises additionally at least one of a mirror and ...

Подробнее
Номер записи: 90
29-03-2012 дата публикации

Failure Detection for Series of Electrical Loads

Номер: US20120074947A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

A device can be used for detecting failures in an illumination device having a plurality of light emitting diodes connected in series. A first circuit node, a second circuit node, and a third circuit node interface the illumination device such that a voltage supplying the plurality of light emitting diodes is applied between the first and the second circuit node and a first fraction of the supply voltage drop is provided between the third and the second circuit node. An evaluation unit is coupled to the first circuit node, the second circuit node, and the third circuit node and configured to assess whether a voltage present at the third circuit node is within a pre-defined range of tolerance about a nominal value that is defined as a second fraction of the supply voltage present between the first and the second circuit node. 1. An apparatus for detecting failures in an illumination device comprising a plurality of light emitting diodes connected in series , the device comprising:a first circuit node, a second circuit node, and a third circuit node for interfacing the illumination device such that a voltage supplying the plurality of light emitting diodes is applied between the first and the second circuit node and a first fraction of a supply voltage drop is provided between the third and the second circuit node; andan evaluation unit coupled to the first circuit node, the second circuit node, and the third circuit node and configured to assess whether a voltage present at the third circuit node is within a pre-defined range of tolerance about a nominal value that is defined as a second fraction of the supply voltage present between the first and the second circuit node,wherein the second fraction is preset such that the nominal value substantially equals the voltage present at the third circuit when the illumination device includes only faultless light emitting diodes.2. The apparatus of claim 1 , wherein the evaluation unit comprises a measurement circuit ...

Подробнее
Номер записи: 91
29-03-2012 дата публикации

MULTI-CHIP PACKAGE

Номер: US20120075812A1
Автор: Hable Wolfram
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a chip module may include a substrate; electronic components, the electronic components being arranged on a first side of the substrate; and an insulating layer, which is applied to the first side of the substrate and to the electronic components, contact openings being arranged in the insulating layer which permit electrical contacting of the electronic components; and an electrically conducting layer being arranged on the insulating layer and in the contact openings, which connects the electronic components electrically to one another. 1. A chip module , comprising:a substrate;electronic components, the electronic components being arranged on a first side of the substrate; andan insulating layer, which is applied to the first side of the substrate and to the electronic components,contact openings being arranged in the insulating layer which permit electrical contacting of the electronic components; andan electrically conducting layer being arranged on the insulating layer and in the contact openings, which connects the electronic components electrically to one another.2. The chip module as claimed in claim 1 ,wherein the electrically conducting layer is deposited on the insulating layer by means of electrodeposition.3. The chip module as claimed in claim 1 ,wherein the electronic components is connected to one another by means of a further electrically conducting layer applied to the substrate.4. The chip module as claimed in claim 3 ,wherein the conducting layer and the further conducting layer are electrically connected to one another by means of the contact openings.5. The chip module as claimed in claim 1 ,wherein the substrate comprises a DCB ceramic.6. The chip module as claimed in claim 1 ,wherein the insulating layer comprises epoxy resin.7. The chip module as claimed in claim 1 ,wherein the insulating layer comprises at least one of glass fibers and filling particles.8. The chip module as claimed in claim 1 ,wherein the insulating ...

Подробнее
Номер записи: 92
29-03-2012 дата публикации

Ip2 calibration methods and techniques

Номер: US20120077452A1
Автор: Harald Froehlich, Krzysztof Dufrene
Принадлежит: INFINEON TECHNOLOGIES AG

Some embodiments of the present disclosure relate to improved techniques for performing IP2 calibration in receivers having two complementary data paths (e.g., i-data path and q-data path). In these techniques, one of the two data paths (e.g., the i-data path) is used to generate a reference signal for the other data path (e.g., the q-data path), and/or vice versa. The other data path then performs calibration using the reference signal. Compared to previous techniques (which required separate, dedicated circuitry for generating a reference signal), the inventive techniques reduce the amount of circuitry and correspondingly reduce the manufacturing costs and power consumption. This is because the inventive techniques use the existing circuitry in complementary fashion during calibration (e.g., during calibration an i-data path generates a reference signal for a q-data path, and vice versa).

Подробнее
Номер записи: 93
29-03-2012 дата публикации

APPARATUS AND METHOD FOR DETERMINATION OF A POSITION OF A 1 BIT ERROR IN A CODED BIT SEQUENCE, APPARATUS AND METHOD FOR CORRECTION OF A 1-BIT ERROR IN A CODED BIT SEQUENCE AND DECODER AND METHOD FOR DECODING AN INCORRECT, CODED BIT SEQUENCE

Номер: US20120079343A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence. 1. An apparatus for determination of a position of a 1-bit error in a bit sequence that is coded by means of an inner code and an outer non-linear code , comprising:an error position determiner of the inner code configured to determine at least one possible error position of a bit error in the coded bit sequence based on the inner code;an error syndrome determiner of the outer code configured to determine a value of a non-linear syndrome bit of the outer code based on a non-linear function of bits in the coded bit sequence;a derivative determiner configured to determine a value of a derivative bit for at least one determined, possible error position of the bit error, based on derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence; andan overall error position determiner configured to determine an error position of the bit error based on the non-linear syndrome bit and at least one derivative bit when the error position determiner of the inner code determines more than one possible error position of the bit error, or the overall error ...

Подробнее
Номер записи: 94
05-04-2012 дата публикации

Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core

Номер: US20120080690A1
Автор: Berger Rudolf, Foerg Raimund, Gruber Hermann, Lehnert Wolfgang, Mauder Anton, Ruhl Guenther, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate. 1. A method for manufacturing a composite wafer , comprising:providing a monocrystalline semiconductor wafer comprising a first side and a second side arranged opposite the first side;depositing a moulding composition comprising at least one of carbon powder and pitch on the second side of the semiconductor wafer; andannealing the deposited moulding composition to form a graphite carrier attached to the semiconductor wafer.2. A method according to claim 1 , wherein the moulding composition further comprises a binder.3. A method according to claim 1 , wherein depositing a moulding composition comprises at least one of injection moulding and compression moulding.4. A method according to claim 1 , wherein annealing the deposited moulding composition comprises a first annealing process in a first temperature range and a subsequent second annealing process in a second temperature range different than the first temperature range.5. A method according to claim 1 , further comprising:forming a first protective layer at least on the first side of the monocrystalline semiconductor wafer prior to depositing the moulding composition.6. A method according to claim 5 , further comprising:removing the first protective layer from the monocrystalline semiconductor wafer after depositing the moulding composition or after annealing the deposited moulding composition.7. A method according to claim 1 , further comprising:forming a second protective layer at least on the graphite carrier.8. A method according to claim 1 , further comprising:forming an intermediate layer on the second side of the monocrystalline semiconductor wafer; anddepositing the moulding composition on the intermediate layer.9. A method according to claim 1 , further comprising:forming a recess in the second side of the monocrystalline ...

Подробнее
Номер записи: 95
05-04-2012 дата публикации

Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert

Номер: US20120080799A1
Автор: Bayerer Reinhold, Hohlfeld Olaf
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The insert is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom side metallization layer and insert by means of a solder packing all interstices between the metal surface and bottom side metallization layer with the solder. 1. A semiconductor module comprising:a rigid base;an insulating substrate comprising an insulation carrier having a top side provided with a top side metallization layer, and a bottom side provided with a bottom side metallization layer;a power semiconductor chip arranged on the top side metallization layer;an insert arranged between the base and the bottom side metallization layer and comprising a wavy shape with a plurality of wave crests and a plurality of wave troughs, the wave crests facing toward the bottom side metallization layer and the wave troughs facing toward the base; anda solder arranged between the bottom side metallization layer and the base, the solder completely filling all interstices between the bottom side metallization layer and the base.2. The semiconductor module as set forth in claim 1 , wherein the solder comprises first regions claim 1 , each of which:comprises at least 90% by volume of one ore more copper-tin intermetallic phases; andextends continuously either between the bottom side metallization layer and one of the wave crests, or between the base and one of the wave troughs.3. The semiconductor module as set forth in claim 2 , wherein the solder comprises a second region arranged outside the first regions and exhibiting a melting point of which is lower than the melting point of a Cu6Sn5 copper-tin intermetallic phase.4. The semiconductor module as set forth in claim 3 , wherein the solder ...

Подробнее
Номер записи: 96
05-04-2012 дата публикации

Hall sensor arrangement for the redundant measurement of a magnetic field

Номер: US20120081109A1
Автор: ASTEGHER Berthold, Wietschorke Helmut
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a Hall sensor arrangement for the redundant measurement of a magnetic field may include a first Hall sensor on a top side of a first semiconductor substrate; a second Hall sensor on a top side of a second semiconductor substrate; a carrier having a top side and an underside; wherein the first Hall sensor is arranged on the top side of the carrier and the second Hall sensor is arranged on the underside of the carrier; and wherein the measuring area of the first Hall sensor projected perpendicularly onto the carrier at least partly overlaps the measuring area of the second Hall sensor projected perpendicularly onto the carrier. 1. A Hall sensor arrangement for the redundant measurement of a magnetic field , the Hall sensor arrangement comprising:a first Hall sensor on a top side of a first semiconductor substrate;a second Hall sensor on a top side of a second semiconductor substrate;a carrier having a top side and an underside;wherein the first Hall sensor is arranged on the top side of the carrier and the second Hall sensor is arranged on the underside of the carrier; andwherein the measuring area of the first Hall sensor projected perpendicularly onto the carrier at least partly overlaps the measuring area of the second Hall sensor projected perpendicularly onto the carrier.2. The Hall sensor arrangement for the redundant measurement of a magnetic field according to claim 1 ,wherein the measuring area of the first Hall sensor projected perpendicularly onto the carrier substantially completely overlaps the measuring area of the second Hall sensor projected perpendicularly onto the carrier.3. The Hall sensor arrangement for the redundant measurement of a magnetic field according to claim 1 ,wherein a moulding compound completely encloses the first Hall sensor and the second Hall sensor.4. The Hall sensor arrangement for the redundant measurement of a magnetic field according to claim 1 ,wherein the first and the second semiconductor substrate ...

Подробнее
Номер записи: 97
05-04-2012 дата публикации

Level Shifter Circuits and Methods

Номер: US20120081166A1
Автор: Draxelmayr Dieter
Принадлежит: INFINEON TECHNOLOGIES AG

Some embodiments of the present disclosure relate to a level shifter that provides improved response time and/or low static power dissipation compared to conventional level shifters. In some embodiments, a level shifter circuit includes an input terminal coupled to a first semiconductor device, and an output terminal coupled to a second semiconductor device. The first semiconductor device is designed to operate over a first voltage range associated with an input signal, and the second semiconductor device is designed to operate over a second, different voltage range associated with an latched output signal. To transform the input voltage range to the output voltage range, the level shifter circuit includes a signal analyzer and an output latch, wherein the signal analyzer includes at least one state change element for setting a voltage level of the latched output signal. 1. A level-shifter circuit , comprising:an input terminal to receive an input signal having an input voltage level that varies between a first DC offset and a second DC offset;a signal analyzer to selectively provide a change-of-state signal based on whether the input voltage level changes from the first DC offset to the second DC offset;an output latch to output a latched output signal having an output voltage level that varies between a third DC offset and a fourth DC offset, wherein the output voltage level is set to the third or fourth DC offset based on the change-of-state signal.2. The level shifter of claim 1 , further comprising:a state change element to selectively couple a storage node of the output latch to a supply voltage based on the change-of-state signal.3. The level shifter of claim 2 , wherein the state change element comprises a transistor claim 2 , the transistor comprising:a control terminal on which the change-of-state signal is received,a second terminal coupled to a supply voltage; anda third terminal coupled to the storage node of the output latch, wherein the third terminal ...

Подробнее
Номер записи: 98
05-04-2012 дата публикации

RADIO BASE STATIONS, MOBILE RADIO TERMINALS, METHODS FOR CONTROLLING A RADIO BASE STATION, AND METHODS FOR CONTROLLING A MOBILE RADIO TERMINAL

Номер: US20120082099A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a radio base station is provided. The radio base station may include: a receiver configured to receive, via a pre-determined radio resource, a Random Access Preamble from a mobile radio terminal; a load determiner configured to determine whether a load situation which fulfills a pre-determined criterion is present for at least one communication resource of the radio base station; a Random Access Response message generator configured to generate, based on the determination of the load determiner, a Random Access Response message including controlling information for controlling access to the pre-determined radio resource and recipient information indicating whether a recipient of the Random Access Response message is to apply the controlling information; and a sender configured to send the Random Access Response message in response to the received Random Access Preamble to the mobile radio terminal. 1. A radio base station , comprising:a receiver configured to receive, via a pre-determined radio resource, a Random Access Preamble from a mobile radio terminal;a load determiner configured to determine whether a load situation which fulfills a pre-determined criterion is present for at least one communication resource of the radio base station;a Random Access Response message generator configured to generate, based on the determination of the load determiner, a Random Access Response message including controlling information for controlling access to the pre-determined radio resource and recipient information indicating whether a recipient of the Random Access Response message is to apply the controlling information; anda sender configured to send the Random Access Response message in response to the received Random Access Preamble to the mobile radio terminal.2. The radio base station of claim 1 ,wherein the at least one communication resource of the radio base station comprises the pre-determined radio resource.3. The radio base station of claim 2 , ...

Подробнее
Номер записи: 99
05-04-2012 дата публикации

METHOD FOR PRODUCING A GATE ELECTRODE STRUCTURE

Номер: US20120083081A1
Автор:
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure. 1. A method for producing a transistor with a gate electrode structure , the method comprising:providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface;forming a first trench extending from the first surface into the semiconductor body, wherein forming the first trench comprises removing the sacrificial layer in a section adjacent the first surface;forming a second trench by isotropically etching the semiconductor body in the first trench;forming a third trench below the second trench by removing at least a part of the first sacrificial layer below the second trench;forming a dielectric layer which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench; andforming a gate electrode on the dielectric layer in the second trench, the gate electrode and the dielectric layer in the second trench forming the gate electrode structure.2. The method of claim 1 , wherein the dielectric layer completely fills the ...

Подробнее
Номер записи: 100