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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 223. Отображено 161.
18-03-2021 дата публикации

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

Номер: US20210082861A1
Автор: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei, MAHLER JOACHIM, BAUER MICHAEL, DANGELMAIER JOCHEN, ENGL REIMUND, GATTERBAUER JOHANN, HILLE FRANK, HUETTINGER MICHAEL, KANERT WERNER, KOERNER HEINRICH, RUEHLE BRIGITTE, SANTOS RODRIGUEZ FRANCISCO JAVIER, VELLEI ANTONIO, Mahler, Joachim, Bauer, Michael, Dangelmaier, Jochen, Engl, Reimund, Gatterbauer, Johann, Hille, Frank, Huettinger, Michael, Kanert, Werner, Koerner, Heinrich, Ruehle, Brigitte, Santos Rodriguez, Francisco Javier, Vellei, Antonio
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

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Номер записи: 1
03-04-2018 дата публикации

Method for processing a wafer and wafer structure

Номер: US0009935060B2
Автор: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez, YEDURU SRINIVASA REDDY, GASSER KARL HEINZ, WOEHLERT STEFAN, MAYER KARL, SANTOS RODRIGUEZ FRANCISCO JAVIER, Yeduru Srinivasa Reddy, Gasser Karl Heinz, Woehlert Stefan, Mayer Karl, Santos Rodriguez Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

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Номер записи: 2
18-10-2011 дата публикации

Method for producing a semiconductor device including connecting a functional wafer to a carrier substrate and selectively etching the carrier substrate

Номер: US0008039313B2
Автор: Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten von Koblinski, KROENER FRIEDRICH, SANTOS RODRIGUEZ FRANCISCO JAVIER, VON KOBLINSKI CARSTEN, RODRIGUEZ FRANCISCO JAVIER SANTOS
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 3
14-03-2019 дата публикации

APPARATUS AND METHOD FOR CHEMICAL VAPOR DEPOSITION PROCESS FOR SEMICONDUCTOR SUBSTRATES

Номер: US20190078211A1
Автор: Matthias Kuenle, Johannes Baumgartl, Manfred Engelhardt, Christian Illemann, Francisco Javier Santos Rodriguez, Olaf Storbeck, KUENLE MATTHIAS, BAUMGARTL JOHANNES, ENGELHARDT MANFRED, ILLEMANN CHRISTIAN, SANTOS RODRIGUEZ FRANCISCO JAVIER, STORBECK OLAF, Kuenle, Matthias, Baumgartl, Johannes, Engelhardt, Manfred, Illemann, Christian, Santos Rodriguez, Francisco Javier, Storbeck, Olaf
Принадлежит:

A CVD reactor, including a deposition chamber housing a first susceptor and a second susceptor, the first susceptor having a cavity for receiving a first substrate, the first substrate having a front surface and a back surface, the second susceptor having a cavity for receiving a second substrate, the second substrate having a front surface and a back surface, and the first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel. 1. A CVD reactor , comprising:a deposition chamber housing a first susceptor and a second susceptor;the first susceptor configured to receive a first substrate, the first substrate comprising a front surface and a back surface;the second susceptor configured to receive a second substrate, the second substrate comprising a front surface and a back surface; andthe first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel.2. The CVD reactor of claim 1 , wherein the first and second susceptors are rotatable about their respective central axes.3. The CVD reactor of claim 1 , wherein a central axis of the first susceptor is aligned with a central axis of the second susceptor.4. The CVD reactor of claim 1 , wherein the front surface of the first substrate is parallel to the front surface of the second substrate.5. The CVD reactor of claim 1 , wherein the front surface of the first substrate and the front surface of the second substrate are inclined towards each other.6. The CVD reactor of claim 1 , further comprising:at least one gas inlet and at least one gas outlet provided in a side wall of the deposition chamber, the at least one gas inlet and the at least one gas outlet are disposed opposite each other and are aligned with the gas flow channel.7. The ...

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Номер записи: 4
09-11-2023 дата публикации

Methods of Forming Semiconductor Devices in a Layer of Epitaxial Silicon Carbide

Номер: US20230361196A1
Автор: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
Принадлежит:

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

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Номер записи: 5
26-10-2017 дата публикации

Method for Forming a Semiconductor Device and a Semiconductor Device

Номер: US20170309517A1
Автор: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит:

In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips. 120-. (canceled)21. A semiconductor device comprising: a semiconductor body having a first side and a second side opposite the first side and comprising a wide band-gap semiconductor material, the wide band-gap semiconductor material comprising silicon carbide or gallium nitride;', 'a graphite substrate bonded to the second side of the semiconductor body by a ceramic-forming polymer precursor and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate;', 'a back-side metallization arranged in the opening of the graphite substrate, surrounded by the graphite substrate, and electrically contacting the area of the second side; and', 'a front-side metallization formed on the first side of the semiconductor body and electrically contacting the semiconductor body;, 'a plurality of semiconductor chips each comprisinga foil attached to each of the plurality of semiconductor chips such that the graphite substrate of each of the plurality of semiconductor chips is arranged between at least a portion of the foil and the semiconductor body of each of the plurality of semiconductor chips;a plurality of separation trenches, each of the plurality of separation trenches separating one of the ...

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Номер записи: 6
05-05-2020 дата публикации

Methods of thinning and structuring semiconductor wafers by electrical discharge machining

Номер: US0010643860B2
Автор: Nirdesh Ojha, Francisco Javier Santos Rodriguez
Принадлежит: Infineon Technologies AG

A method of structuring and/or thinning a semiconductor wafer having a plurality of functional chip sites includes forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer, and forming an electrode at one of the frontside or a backside of the semiconductor wafer. The side of the semiconductor wafer at which the electrode is formed is structured by applying voltage pulses between the electrode and a tool electrode positioned above the semiconductor wafer as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the side of the semiconductor wafer being structured after the electrode is removed by the EDM process.

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Номер записи: 7
07-03-2017 дата публикации

Method for processing a wafer and wafer structure

Номер: US0009589880B2
Автор: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
Принадлежит: INFINEON TECHNOLOGIES AG

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

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Номер записи: 8
03-02-2022 дата публикации

Methods for Forming a Semiconductor Device

Номер: US20220037165A1
Автор: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
Принадлежит: INFINEON TECHNOLOGIES AG

A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

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Номер записи: 9
09-01-2020 дата публикации

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

Номер: US20200013749A1
Автор: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei, MAHLER JOACHIM, BAUER MICHAEL, DANGELMAIER JOCHEN, ENGL REIMUND, GATTERBAUER JOHANN, HILLE FRANK, HUETTINGER MICHAEL, KANERT WERNER, KOERNER HEINRICH, RUEHLE BRIGITTE, SANTOS RODRIGUEZ FRANCISCO JAVIER, VELLEI ANTONIO, Mahler, Joachim, Bauer, Michael, Dangelmaier, Jochen, Engl, Reimund, Gatterbauer, Johann, Hille, Frank, Huettinger, Michael, Kanert, Werner, Koerner, Heinrich, Ruehle, Brigitte, Santos Rodriguez, Francisco Javier, Vellei, Antonio
Принадлежит:

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

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Номер записи: 10
02-11-2017 дата публикации

Semiconductor Device Having a Defined Oxygen Concentration

Номер: US20170316929A1
Автор: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит:

A method for manufacturing a substrate wafer includes providing a device wafer () having a first side () and a second side (); subjecting the device wafer () to a first high temperature process for reducing the oxygen content of the device wafer () at least in a region () at the second side (); bonding the second side () of the device wafer () to a first side () of a carrier wafer () to form a substrate wafer (); processing the first side () of the substrate wafer () to reduce the thickness of the device wafer (); subjecting the substrate wafer () to a second high temperature process for reducing the oxygen content at least of the device wafer (); and at least partially integrating at least one semiconductor component () into the device wafer () after the second high temperature process. 120-. (canceled)21. A semiconductor device , comprising:a semiconductor substrate having a first side, a second side opposite the first side, and a thickness;at least one semiconductor component integrated in the semiconductor substrate;a first metallization at the first side of the semiconductor substrate;a second metallization at the second side of the semiconductor substrate;wherein the semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side,wherein the global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.22. The semiconductor device of claim 21 , wherein the global maximum is at least 5-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.23. The semiconductor device of claim 21 , wherein the global maximum of the oxygen concentration is less than 5*10/cm.24. The semiconductor device of claim 21 , wherein the global maximum of the oxygen concentration is equal to or less ...

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Номер записи: 11
26-09-2019 дата публикации

Methods of Thinning and Structuring Semiconductor Wafers by Electrical Discharge Machining

Номер: US20190295855A1
Автор: Nirdesh Ojha, Francisco Javier Santos Rodriguez, OJHA NIRDESH, SANTOS RODRIGUEZ FRANCISCO JAVIER, Ojha, Nirdesh, Santos Rodriguez, Francisco Javier
Принадлежит:

A method of structuring and/or thinning a semiconductor wafer having a plurality of functional chip sites includes forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer, and forming an electrode at one of the frontside or a backside of the semiconductor wafer. The side of the semiconductor wafer at which the electrode is formed is structured by applying voltage pulses between the electrode and a tool electrode positioned above the semiconductor wafer as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the side of the semiconductor wafer being structured after the electrode is removed by the EDM process. 1. A method of thinning a semiconductor wafer having a plurality of functional chip sites , the method comprising:forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer;forming an electrode at a backside of the semiconductor wafer opposite the frontside, the electrode having a greater electrical conductivity than the backside of the semiconductor wafer; andthinning the semiconductor wafer by applying voltage pulses between the electrode at the backside of the semiconductor wafer and a tool electrode positioned over the backside as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the backside of the semiconductor wafer after the electrode is removed by the EDM process.2. The method of claim 1 , wherein the EDM process comprises:covering the backside of the semiconductor wafer with a dielectric liquid; andmoving the tool electrode and/or the semiconductor wafer in the dielectric liquid in a vertical direction to maintain a plasma between the tool ...

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Номер записи: 12
15-09-2020 дата публикации

Wafer arrangement and method for processing a wafer

Номер: US0010777444B2
Автор: Francisco Javier Santos Rodriguez, Gerald Lackner, Josef Unterweger, SANTOS RODRIGUEZ FRANCISCO JAVIER, LACKNER GERALD, UNTERWEGER JOSEF, Santos Rodriguez, Francisco Javier, Lackner, Gerald, Unterweger, Josef
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.

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Номер записи: 13
07-12-2023 дата публикации

Methods for Forming a Semiconductor Device Having a Second Semiconductor Layer on a First Semiconductor Layer

Номер: US20230395394A1
Автор: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
Принадлежит:

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

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Номер записи: 14
12-07-2018 дата публикации

Wafer Carrier, Method for Manufacturing the Same and Method for Carrying a Wafer

Номер: US20180197766A1
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Ronny Kern, Josef Unterweger
Принадлежит:

A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for carrying the wafer. The first and the second foil are connected to each other so as to form the chamber. The chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried. 1. A wafer carrier comprising:a first foil comprising a perforation and configured to carry a wafer;a second foil; anda chamber between the first foil and the second foil, wherein the first foil and the second foil are connected to each other so as to form the chamber,wherein the chamber is configured to be evacuated to form a vacuum in the chamber so that the vacuum causes an underpressure at the perforation to provide a carrying force to the wafer.2. The wafer carrier according to claim 1 , wherein the first and second foils are structurally supported.3. The wafer carrier according to claim 2 , wherein a grid or a porous plate is arranged between the first and second foils to structurally support the first and second foils.4. The wafer carrier according to claim 1 , wherein the first and second foils are connected to each other such that the vacuum within the chamber is maintained when the wafer is carried.5. The wafer carrier according to claim 1 , wherein the first and second foils are connected to each other using a common edge surrounding the chamber.6. The wafer carrier according to claim 5 , wherein the common edge comprises a welded portion connecting the first and second foils and encapsulating the chamber.7. The wafer carrier according to claim 5 , wherein the common edge comprises a zip connecting the first and second foils and encapsulating the chamber.8. The wafer carrier according to claim 1 , wherein the first foil and/or the second foil has a diameter which is larger than the diameter of the wafer ...

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Номер записи: 15
14-11-2019 дата публикации

Methods for Processing a Wide Band Gap Semiconductor Wafer, Methods for Forming a Plurality of Thin Wide Band Gap Semiconductor Wafers, and Wide Band Gap Semiconductor Wafers

Номер: US20190348328A1
Автор: Francisco Javier Santos Rodriguez, Guenter Denifl, Tobias Franz Wolfgang Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
Принадлежит:

A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer. 1. A method for processing a wide band gap semiconductor wafer , the method comprising:depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer;depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; andsplitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the non-monocrystalline support layer.2. The method of claim 1 , wherein a thermal expansion coefficient of the non-monocrystalline support layer differs from a thermal expansion coefficient of the wide band gap semiconductor wafer by at most 10% of the thermal expansion coefficient of the wide band gap semiconductor wafer.3. The method of claim 1 , wherein the non-monocrystalline support layer is deposited at a deposition rate of at least 50 μm/hour.4. The method of claim 1 , wherein the non-monocrystalline support layer is a poly-silicon carbide layer or a molybdenum layer.5. The method of claim 1 , wherein a total thickness of the remaining wafer including the non-monocrystalline support layer is at least 200 μm and at most 1500 μm.6. The method of claim 1 , wherein a protective layer is located at the front side of the wide band gap semiconductor wafer during the depositing of the non-monocrystalline support layer.7. The method of claim 1 , further comprising:depositing a further non-monocrystalline support layer ...

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Номер записи: 16
04-07-2017 дата публикации

Metal deposition on substrates

Номер: US0009698106B2
Автор: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler, WANG KAE-HORNG, SANTOS RODRIGUEZ FRANCISCO JAVIER, KNABL MICHAEL, KOFFLER GUENTHER, Wang Kae-Horng, Santos Rodriguez Francisco Javier, Knabl Michael, Koffler Guenther
Принадлежит: Infineon Technologies Austria AG, INFINEON TECHNOLOGIES AUSTRIA AG

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

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Номер записи: 17
09-04-2019 дата публикации

Forming a metal contact layer on silicon carbide and semiconductor device with metal contact structure

Номер: US0010256097B2
Автор: Ravi Keshav Joshi, Romain Esteve, Roland Rupp, Francisco Javier Santos Rodriguez, Gerald Unegg, JOSHI RAVI KESHAV, ESTEVE ROMAIN, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, UNEGG GERALD, Joshi, Ravi Keshav, Esteve, Romain, Rupp, Roland, Santos Rodriguez, Francisco Javier, Unegg, Gerald
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.

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Номер записи: 18
08-08-2017 дата публикации

Method for manufacturing a semiconductor wafer, and semiconductor device having a low concentration of interstitial oxygen

Номер: US0009728395B2
Автор: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, OEFNER HELMUT, CASPARY NICO, MOMENI MOHAMMAD, PLOSS REINHARD, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HANS-JOACHIM, Oefner Helmut, Caspary Nico, Momeni Mohammad, Ploss Reinhard, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

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Номер записи: 19
18-08-2020 дата публикации

Battery, integrated circuit and method of manufacturing a battery

Номер: US0010749216B2
Автор: Ravi Keshav Joshi, Alexander Breymesser, Bernhard Goller, Kamil Karlovsky, Francisco Javier Santos Rodriguez, Peter Zorn
Принадлежит: Infineon Technologies AG

A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity.

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Номер записи: 20
18-06-2013 дата публикации

Method for fabricating a porous semiconductor body region

Номер: US0008466046B2
Автор: Hans-Joachim Schulze, Anton Mauder, Francisco Javier Santos Rodriguez, SCHULZE HANS-JOACHIM, MAUDER ANTON, SANTOS RODRIGUEZ FRANCISCO JAVIER
Принадлежит: Infineon Technologies AG, SCHULZE HANS-JOACHIM, MAUDER ANTON, SANTOS RODRIGUEZ FRANCISCO JAVIER, INFINEON TECHNOLOGIES AUSTRIA, INFINEON TECHNOLOGIES AG

A method may include producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, then producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and then filling the trench with a semiconductor material of the semiconductor body.

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Номер записи: 21
18-01-2018 дата публикации

METHOD FOR PROCESSING ONE SEMICONDUCTOR WAFER OR A PLURALITY OF SEMICONDUCTOR WAFERS AND PROTECTIVE COVER FOR COVERING THE SEMICONDUCTOR WAFER

Номер: US20180019150A1
Автор: Francisco Javier Santos Rodriguez, Roland Rupp
Принадлежит:

In various embodiments, a method for processing a semiconductor wafer is provided. The semiconductor wafer includes a first main processing side and a second main processing side, which is arranged opposite the first main processing side, and at least one circuit region having at least one electronic circuit on the first main processing side. The method includes forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region, and thinning the semiconductor wafer, including the stiffening structure, from the second main processing side. 1. A method for processing a semiconductor wafer , a first main processing side and a second main processing side, which is arranged opposite the first main processing side;', 'at least one circuit region having at least one electronic circuit on the first main processing side;, 'the semiconductor wafer comprising forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region;', 'thinning the semiconductor wafer, comprising the stiffening structure, from the second main processing side., 'the method comprising2. The method of claim 1 , further comprising:forming a filling body in the cutout, which filling body is in physical contact with the circuit region and differs from the stiffening structure.3. The method of claim 2 , further comprising:forming a stiffening structure cover above the cutout, wherein the stiffening structure is arranged between the stiffening structure cover and the circuit region.4. The method of claim 3 ,wherein forming the filling body comprises at least one of introducing a material into the cutout or solidifying said material therein while the semiconductor ...

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Номер записи: 22
26-02-2015 дата публикации

Method for Manufacturing a Semiconductor Device by Thermal Treatment with Hydrogen

Номер: US20150056784A1
Автор: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Anton Mauder, Johannes Baumgartl, Carsten Ahrens, SCHULZE HANS-JOACHIM, SANTOS RODRIGUEZ FRANCISCO JAVIER, MAUDER ANTON, BAUMGARTL JOHANNES, AHRENS CARSTEN
Принадлежит:

A semiconductor device is manufactured by forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer. This includes forming a porous area at a surface of a semiconductor body that includes a porous structure in the porous area, forming the semiconductor layer on the porous area by epitaxial growth so as to have a thickness in a range of 5 μm to 200 μm, and forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer by ion implantation. After forming the semiconductor regions, hydrogen is introduced into the porous area by a thermal treatment, activating a reallocation of pores and causing cavities to be generated. The semiconductor layer is separated from the semiconductor body along the porous area. After the separation, rear side processing is applied to the semiconductor layer. 1. A method of manufacturing a semiconductor device , comprising:forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer by:forming a porous area at a surface of a semiconductor body, wherein the semiconductor body includes a porous structure in the porous area;forming the semiconductor layer on the porous area by epitaxial growth so as to have a thickness in a range of 5 μm to 200 μm;forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer by ion implantation;introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, thereby activating a reallocation of pores and causing cavities to be generated, so that the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; andapplying, after separation of the semiconductor layer, rear side processing to the semiconductor layer,wherein the rear side processing comprises ion ...

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Номер записи: 23
25-05-2017 дата публикации

Method of Manufacturing a Semiconductor Device Having a Vertical Edge Termination Structure

Номер: US20170148663A1
Автор: Alexander Breymesser, Andre Brockmeier, Elmar Falck, Francisco Javier Santos Rodriguez, Holger Schulze, BREYMESSER ALEXANDER, BROCKMEIER ANDRE, FALCK ELMAR, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HOLGER, Breymesser Alexander, Brockmeier Andre, Falck Elmar, Santos Rodriguez Francisco Javier, Schulze Holger
Принадлежит:

A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench. 1. A method of manufacturing a semiconductor device , the method comprising:forming a frame trench extending from a first surface into a base substrate;forming, in the frame trench, an edge termination structure comprising a glass structure;forming a conductive layer on the semiconductor substrate and the edge termination structure; andremoving a portion of the conductive layer above the edge termination structure, wherein a remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.2. The method of claim 1 , wherein filling the frame trench comprises molding glass in the frame trench.3. The method of claim 2 , wherein the glass is mechanically connected to the semiconductor body in a form-fitting manner during molding.4. The method of claim 1 , wherein forming the edge termination structure comprises bringing a source material based on glass in contact with a surface of the semiconductor substrate and pressing the source material and the semiconductor substrate against each other claim 1 , wherein a temperature of the source material and a force exerted on the source material and the semiconductor substrate are controlled such that fluidified source material flows into the frame trench and the fluidified source material re-solidifies to form a glass piece comprising a protrusion ...

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Номер записи: 24
05-07-2016 дата публикации

Glass carrier with embedded semiconductor device and metal layers on the top surface

Номер: US0009385075B2
Автор: Alexander Breymesser, Andre Brockmeier, Franz Dielacher, Francisco Javier Santos Rodriguez, BREYMESSER ALEXANDER, BROCKMEIER ANDRE, DIELACHER FRANZ, SANTOS RODRIGUEZ FRANCISCO JAVIER
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.

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Номер записи: 25
02-11-2017 дата публикации

Semiconductor Device and Manufacturing Therefor

Номер: US20170317165A1
Автор: Philip Christoph Brandt, Andre Rainer Stegner, Francisco Javier Santos Rodriguez, Frank Dieter Pfirsch, Hans-Joachim Schulze, Manfred Pfaffenlehner, Thomas Auer
Принадлежит:

An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region. 1. A semiconductor device , comprising: a first side;', 'an edge delimiting the semiconductor body in a direction parallel to the first side;', 'an active area;', 'a peripheral area arranged between the active area and the edge;', 'a first semiconductor region of a first conductivity type extending from the active area into the peripheral area;', 'a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region;', 'a first edge termination region of the second conductivity type adjoining the first semiconductor region in the peripheral area, and arranged at the first side and between the second semiconductor region and the edge; and', 'a second edge termination region of the first conductivity type comprising a varying concentration of dopants of the first conductivity type, which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region and/or with an increasing distance from the active ...

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Номер записи: 26
29-06-2021 дата публикации

Method for processing a monocrystalline substrate and micromechanical structure

Номер: US0011046577B2
Автор: Andre Brockmeier, Roland Rupp, Francisco Javier Santos Rodriguez, BROCKMEIER ANDRE, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, Brockmeier, Andre, Rupp, Roland, Santos Rodriguez, Francisco Javier
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.

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Номер записи: 27
29-11-2022 дата публикации

Method for processing a semiconductor wafer, semiconductor composite structure and support structure for semiconductor wafer

Номер: US0011515264B2
Автор: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
Принадлежит: Infineon Technologies AG

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

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Номер записи: 28
10-11-2022 дата публикации

Method for Processing a Semiconductor Wafer and Semiconductor Composite Structure

Номер: US20220359428A1
Автор: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
Принадлежит:

A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

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Номер записи: 29
01-10-2015 дата публикации

SEMICONDUCTOR DEVICE INCLUDING A VERTICAL EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURING

Номер: US20150279930A1
Автор: Alexander Breymesser, Andre Brockmeier, Elmar Falck, Francisco Javier Santos Rodriguez, Holger Schulze
Принадлежит:

A semiconductor device includes a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface connecting the first and second surfaces. An edge termination structure includes a glass structure and extends along the edge surface, at least from a plane coplanar with the first surface towards the second surface. A conductive structure extends parallel to the first surface and overlaps the glass structure at the first side. 1. A semiconductor device , comprising:a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface connecting the first and second surfaces;an edge termination structure including a glass structure and extending along the edge surface at least from a plane coplanar with the first surface towards the second surface; anda conductive structure extending parallel to the first surface and overlapping the glass structure at the first side.2. The semiconductor device of claim 1 , whereinthe semiconductor body comprises a heavily doped pedestal region directly adjoining the second surface and the edge surface, andthe glass structure extends to at least the pedestal region.3. The semiconductor device of claim 2 , whereinthe pedestal region extends parallel to the second surface.4. The semiconductor device of claim 1 , whereinthe glass structure results from a glass molding process.5. The semiconductor device of claim 1 , whereinthe edge termination structure extends at least from the first surface to a plane coplanar with the second surface.6. The semiconductor device of claim 1 , whereinthe edge termination structure includes an auxiliary structure in direct contact with at least a portion of the third surface.7. The semiconductor device of claim 1 , whereinthe edge termination structure includes an auxiliary structure in direct contact with the complete third surface.8. The semiconductor device of claim 1 , whereinthe third ...

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Номер записи: 30
05-05-2011 дата публикации

BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Номер: US20110101416A1
Автор: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

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Номер записи: 31
28-12-2021 дата публикации

Semiconductor device and method of manufacturing a semiconductor device

Номер: US0011211459B2
Автор: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
Принадлежит: Infineon Technologies AG

An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.

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Номер записи: 32
13-03-2018 дата публикации

Wafer carrier, method for manufacturing the same and method for carrying a wafer

Номер: US0009917000B2
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Ronny Kern, Josef Unterweger, SANTOS RODRIGUEZ FRANCISCO JAVIER, RUPP ROLAND, KERN RONNY, UNTERWEGER JOSEF, Santos Rodriguez Francisco Javier, Rupp Roland, Kern Ronny, Unterweger Josef
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for carrying the wafer. The first and the second foil are connected to each other so as to form the chamber. The chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried.

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Номер записи: 33
15-11-2022 дата публикации

Vertical power semiconductor device, semiconductor wafer or bare-die arrangement, carrier, and method of manufacturing a vertical power semiconductor device

Номер: US0011502190B2
Автор: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит: Infineon Technologies Austria AG

A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 μm to 200 μm. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 μm to 5 μm.

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Номер записи: 34
05-01-2023 дата публикации

METHOD FOR SPLITTING SEMICONDUCTOR WAFERS

Номер: US20230005794A1
Автор: Christian Beyer, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Marko David Swoboda
Принадлежит:

A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

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Номер записи: 35
01-12-2020 дата публикации

Method for producing IGBT with dV/dt controllability

Номер: US0010854739B2
Автор: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez, VELLEI ANTONIO, BENINGER-BINA MARKUS, DAINESE MATTEO, JAEGER CHRISTIAN, LAVEN JOHANNES GEORG, PHILIPPOU ALEXANDER, SANTOS RODRIGUEZ FRANCISCO JAVIER, Vellei, Antonio, Beninger-Bina, Markus, Dainese, Matteo, Jaeger, Christian, Laven, Johannes Georg, Philippou, Alexander, Santos Rodriguez, Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

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Номер записи: 36
15-03-2016 дата публикации

Semiconductor device and method for producing the same

Номер: US0009287165B2
Автор: Gerhard Schmidt, Matthias Müller, Francisco Javier Santos Rodriguez, Daniel Schlögl
Принадлежит: Infineon Technologies AG

A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.

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Номер записи: 37
23-07-2020 дата публикации

Method for Producing IGBT with dV/dt Controllability

Номер: US20200235232A1
Автор: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez, VELLEI ANTONIO, BENINGER-BINA MARKUS, DAINESE MATTEO, JAEGER CHRISTIAN, LAVEN JOHANNES GEORG, PHILIPPOU ALEXANDER, SANTOS RODRIGUEZ FRANCISCO JAVIER, Vellei, Antonio, Beninger-Bina, Markus, Dainese, Matteo, Jaeger, Christian, Laven, Johannes Georg, Philippou, Alexander, Santos Rodriguez, Francisco Javier
Принадлежит:

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current. 1. A power semiconductor device , comprising:a first load terminal and a second load terminal, wherein the power semiconductor device is configured to conduct a load current along a vertical direction between the load terminals;a drift region of a first conductivity type;a plurality of IGBT cells, wherein each of the IGBT cells comprises a plurality of trenches that extend into the drift region along the vertical direction and that laterally confine at least one active mesa, the at least one active mesa comprising an upper section of the drift region; andan electrically floating barrier region of a second conductivity type that is spatially confined, in and against the vertical direction, by the drift region,wherein a total volume of all active mesas is divided into a first share and into a second share, the first share not laterally overlapping with the electrically floating barrier region and the second share laterally overlapping with the electrically floating barrier region,wherein the first share is configured to carry the load current at least within a range of 0% to 100% of a nominal load ...

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Номер записи: 38
13-04-2021 дата публикации

Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer

Номер: US0010978418B2
Автор: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei, MAHLER JOACHIM, BAUER MICHAEL, DANGELMAIER JOCHEN, ENGL REIMUND, GATTERBAUER JOHANN, HILLE FRANK, HUETTINGER MICHAEL, KANERT WERNER, KOERNER HEINRICH, RUEHLE BRIGITTE, SANTOS RODRIGUEZ FRANCISCO JAVIER, VELLEI ANTONIO, Mahler, Joachim, Bauer, Michael, Dangelmaier, Jochen, Engl, Reimund, Gatterbauer, Johann, Hille, Frank, Huettinger, Michael, Kanert, Werner, Koerner, Heinrich, Ruehle, Brigitte, Santos Rodriguez, Francisco Javier, Vellei, Antonio
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

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Номер записи: 39
30-01-2024 дата публикации

Methods for processing a wide band gap semiconductor wafer using a support layer and methods for forming a plurality of thin wide band gap semiconductor wafers using support layers

Номер: US0011887894B2
Автор: Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
Принадлежит: Infineon Technologies AG

A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.

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Номер записи: 40
23-01-2024 дата публикации

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

Номер: US0011881397B2
Автор: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит: Infineon Technologies AG

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

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Номер записи: 41
23-09-2014 дата публикации

Chip package and a method for manufacturing a chip package

Номер: US0008841768B2
Автор: Carsten Von Koblinski, Michael Knabl, Ursula Meyer, Francisco Javier Santos Rodriguez, Alexander Breymesser, Andre Brockmeier, VON KOBLINSKI CARSTEN, KNABL MICHAEL, MEYER URSULA, SANTOS RODRIGUEZ FRANCISCO JAVIER, BREYMESSER ALEXANDER, BROCKMEIER ANDRE
Принадлежит: Infineon Technologies AG, VON KOBLINSKI CARSTEN, KNABL MICHAEL, MEYER URSULA, SANTOS RODRIGUEZ FRANCISCO JAVIER, BREYMESSER ALEXANDER, BROCKMEIER ANDRE, INFINEON TECHNOLOGIES AG

A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to ...

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Номер записи: 42
19-10-2021 дата публикации

Glass piece and methods of manufacturing glass pieces and semiconductor devices with glass pieces

Номер: US0011148943B2
Автор: Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, BREYMESSER ALEXANDER, BROCKMEIER ANDRE, VON KOBLINSKI CARSTEN, SANTOS RODRIGUEZ FRANCISCO JAVIER, Breymesser, Alexander, Brockmeier, Andre, von Koblinski, Carsten, Santos Rodriguez, Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A semiconductor element is formed in a mesa portion of a semiconductor substrate. A cavity is formed in a working surface of the semiconductor substrate. The semiconductor substrate is brought in contact with a glass piece made of a glass material and having a protrusion. The glass piece and the semiconductor substrate are arranged such that the protrusion extends into the cavity. The glass piece is bonded to the semiconductor substrate. The glass piece is in-situ bonded to the semiconductor substrate by pressing the glass piece against the semiconductor substrate. During the pressing a temperature of the glass piece exceeds a glass transition temperature and the temperature and a force exerted on the glass piece are controlled to fluidify the glass material and after re-solidifying the protrusion completely fills the cavity.

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Номер записи: 43
11-11-2014 дата публикации

Method for manufacturing a semiconductor device

Номер: US0008883612B2
Автор: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Anton Mauder, Johannes Baumgartl, Carsten Ahrens, SCHULZE HANS-JOACHIM, RODRIGUEZ FRANCISCO JAVIER SANTOS, MAUDER ANTON, BAUMGARTL JOHANNES, AHRENS CARSTEN
Принадлежит: Infineon Technologies Austria AG, SCHULZE HANS-JOACHIM, RODRIGUEZ FRANCISCO JAVIER SANTOS, MAUDER ANTON, BAUMGARTL JOHANNES, AHRENS CARSTEN, INFINEON TECHNOLOGIES AUSTRIA, INFINEON TECHNOLOGIES AUSTRIA AG

A method of manufacturing a semiconductor device includes forming a porous area of a semiconductor body. The semiconductor body includes a porous structure in the porous area. A semiconductor layer is formed on the porous area. Semiconductor regions are formed in the semiconductor layer. Then, the semiconductor layer is separated from the semiconductor body along the porous area, including introducing hydrogen into the porous area by a thermal treatment.

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Номер записи: 44
24-04-2018 дата публикации

Method of forming a transistor, method of patterning a substrate, and transistor

Номер: US0009954068B2
Автор: Philip Christoph Brandt, Francisco Javier Santos Rodriguez, Andre Rainer Stegner, BRANDT PHILIP CHRISTOPH, SANTOS RODRIGUEZ FRANCISCO JAVIER, STEGNER ANDRE RAINER, Brandt, Philip Christoph, Santos Rodriguez, Francisco Javier, Stegner, Andre Rainer
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

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Номер записи: 45
17-11-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER

Номер: US20220367191A1
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
Принадлежит:

A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.

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Номер записи: 46
05-10-2021 дата публикации

Semiconductor device and method of manufacturing a semiconductor device

Номер: US0011139375B2
Автор: Carsten Schaeffer, Alexander Breymesser, Bernhard Goller, Ronny Kern, Matteo Piccin, Roland Rupp, Francisco Javier Santos Rodriguez, SCHAEFFER CARSTEN, BREYMESSER ALEXANDER, GOLLER BERNHARD, KERN RONNY, PICCIN MATTEO, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, Schaeffer, Carsten, Breymesser, Alexander, Goller, Bernhard, Kern, Ronny, Piccin, Matteo, Rupp, Roland, Santos Rodriguez, Francisco Javier
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.

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Номер записи: 47
07-10-2014 дата публикации

Semiconductor device including trenches and method of manufacturing a semiconductor device

Номер: US0008853774B2
Автор: Maria Cotorogea, Hans Peter Felsl, Yvonne Gawlina, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Georg Seibert, Andre Rainer Stegner, Wolfgang Wagner, COTOROGEA MARIA, FELSL HANS PETER, GAWLINA YVONNE, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HANS-JOACHIM, SEIBERT GEORG, STEGNER ANDRE RAINER, WAGNER WOLFGANG
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

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Номер записи: 48
04-08-2022 дата публикации

Silicon Carbide Devices, Semiconductor Devices and Methods for Forming Silicon Carbide Devices and Semiconductor Devices

Номер: US20220246745A1
Автор: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
Принадлежит:

A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.

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Номер записи: 49
14-07-2016 дата публикации

Metal Deposition on Substrates

Номер: US20160203979A1
Автор: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler, WANG KAE-HORNG, SANTOS RODRIGUEZ FRANCISCO JAVIER, KNABL MICHAEL, KOFFLER GUENTHER
Принадлежит:

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate. 1. An apparatus comprising:an isolation forming device configured to form an isolation layer over a substrate such that the isolation layer being limited to a peripheral region of the substrate; anda metal deposition station configured to deposit at least one metal layer over a side of the substrate.2. The apparatus of claim 1 , wherein the isolation forming device comprises an isolation deposition station configured to deposit the isolation layer over the side of the substrate claim 1 , and a lithography station configured to restrict the isolation layer to the peripheral region of the substrate.3. The apparatus of claim 2 , wherein the lithography station is configured to coat the isolation layer with a photoresist claim 2 , to partially expose the photoresist to light claim 2 , to partially remove the photoresist claim 2 , and to remove the isolation layer at places where the photoresist has been removed.4. The apparatus of claim 1 , wherein the isolation forming device is configured to perform a plasma-enhanced chemical vapor deposition.5. The apparatus of claim 1 , wherein the isolation forming device is configured to form at least one of an oxide or a nitride.6. The apparatus of claim 1 , wherein the metal deposition station comprises an electroless plating device.7. An apparatus comprising:an isolation forming device for forming an isolation layer over a semiconductor wafer, wherein the isolation layer is substantially limited to a peripheral region of the semiconductor wafer; anda metal deposition station for depositing at least one metal layer over a side of the semiconductor wafer, the metal layer being at least partially adjacent the isolation layer.8. The apparatus of claim 7 , wherein the isolation forming device comprises an isolation deposition ...

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Номер записи: 50
30-12-2014 дата публикации

Method for producing a composite material, associated composite material and associated semiconductor circuit arrangements

Номер: US0008922016B2
Автор: Oliver Hellmund, Daniel Kraft, Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten Von Koblinski, HELLMUND OLIVER, KRAFT DANIEL, KROENER FRIEDRICH, SANTOS RODRIGUEZ FRANCISCO JAVIER, VON KOBLINSKI CARSTEN
Принадлежит: Infineon Technologies AG, HELLMUND OLIVER, KRAFT DANIEL, KROENER FRIEDRICH, SANTOS RODRIGUEZ FRANCISCO JAVIER, VON KOBLINSKI CARSTEN, INFINEON TECHNOLOGIES AG

A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another.

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Номер записи: 51
21-04-2015 дата публикации

Semiconductor device, a semiconductor wafer structure, and a method for forming a semiconductor wafer structure

Номер: US0009013027B2
Автор: Holger Huesken, Francisco Javier Santos Rodriguez, Wolfgang Wagner, HUESKEN HOLGER, SANTOS RODRIGUEZ FRANCISCO JAVIER, WAGNER WOLFGANG
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

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Номер записи: 52
02-02-2017 дата публикации

Method for Forming a Wafer Structure, a Method for Forming a Semiconductor Device and a Wafer Structure

Номер: US20170033010A1
Автор: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, RUPP ROLAND, LEHNERT WOLFGANG, SANTOS RODRIGUEZ FRANCISCO JAVIER, Rupp Roland, Lehnert Wolfgang, Santos Rodriguez Francisco Javier
Принадлежит:

A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite, splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed, removing the carrier wafer above an inner portion of the split layer while leaving a residual portion of the carrier wafer attached to the split layer to form a partially supported wafer, and further processing the partially supported wafer. 1. A method for forming a semiconductor device , comprising:attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite;splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed;forming a partially supported wafer comprising removing the carrier wafer above an inner portion of the split layer while leaving a residual portion of the carrier wafer attached to the split layer; andfurther processing the partially supported wafer.2. The method of claim 1 , wherein attaching the donor wafer comprises at least one of:depositing a ceramic-forming polymer precursor on a bonding surface of the donor wafer;depositing the ceramic-forming polymer precursor on the carrier wafer;forming a stack comprising the carrier wafer, the donor wafer and a bonding layer comprising the ceramic-forming polymer precursor, and arranged between the carrier wafer and the bonding surface of the donor wafer; andtempering the stack at a temperature between 200° C. to 700° C.3. The method of claim 2 , wherein the ceramic-forming polymer precursor comprises a polycarbosilane.4. The method of claim 2 , wherein the tempering takes place in an atmosphere comprising nitrogen claim 2 , argon and/or hydrogen.5. The method of prior to at least partly removing the carrier wafer further comprising at least ...

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Номер записи: 53
18-01-2018 дата публикации

METHOD FOR PROCESSING A WAFER, AND LAYER STACK

Номер: US20180019127A1
Автор: Francisco Javier Santos Rodriguez
Принадлежит:

In various embodiments, a method for processing a wafer is provided. The method includes forming a layer stack, including a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, a lower mechanical and/or chemical resistance than the support layer and than the useful layer. The support layer has a depression, which exposes the sacrificial region. The method further includes forming at least one channel in the exposed sacrificial region by means of the processing fluid. The channel connects the depression to an exterior of the layer stack. 1. A method for processing a wafer , the method comprising:forming a layer stack, comprising a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, at least one of a lower mechanical or chemical resistance than the support layer and than the useful layer;wherein the support layer has a depression, which exposes the sacrificial region;forming at least one channel in the exposed sacrificial region by means of the processing fluid, wherein the channel connects the depression to an exterior of the layer stack.2. The method of claim 1 ,wherein the useful layer comprises at least one electrical circuit element.3. The method of claim 1 ,wherein the depression is formed through the support layer or at least into the latter by virtue of material being removed from the support layer or by virtue of material being deposited by means of a mask.4. The method of claim 1 ,wherein the support layer comprises the wafer; orwherein the useful layer is arranged between the support layer and the wafer.5. The method of claim 1 ,wherein at least one of the useful layer and the support layer or the useful layer and the sacrificial region have an epitaxial relation to one another.6. The method of claim 1 ,wherein the useful layer is grown epitaxially onto the support layer and the sacrificial region ...

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Номер записи: 54
23-11-2017 дата публикации

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

Номер: US20170338169A1
Автор: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
Принадлежит:

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material; 'Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, Zr.', 'wherein the protective layer comprises or essentially consists of at least one material of a group of inorganic materials, the group consisting of'}2. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface, wherein the metal contact structure comprises copper and/or silver;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material;wherein the protective layer comprises or essentially consists of an azole and/or tetracyanoquinodimethane that is different from the packaging material.3. A leadframe based chip package , comprising:a chip;a metal contact structure comprising a non-noble metal and electrically contacting the chip;a packaging material; anda ...

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Номер записи: 55
07-04-2020 дата публикации

Method for processing a monocrystalline substrate and micromechanical structure

Номер: US0010611630B2
Автор: Andre Brockmeier, Roland Rupp, Francisco Javier Santos Rodriguez, BROCKMEIER ANDRE, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, Brockmeier, Andre, Rupp, Roland, Santos Rodriguez, Francisco Javier
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.

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Номер записи: 56
20-06-2017 дата публикации

Semiconductor to metal transition for semiconductor devices

Номер: US0009685504B2
Автор: Andreas Haertl, Frank Hille, Francisco Javier Santos Rodriguez, Daniel Schloegl, Andre Rainer Stegner, Christoph Weiss, HAERTL ANDREAS, HILLE FRANK, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHLOEGL DANIEL, STEGNER ANDRE RAINER, WEISS CHRISTOPH, Haertl Andreas, Hille Frank, Santos Rodriguez Francisco Javier, Schloegl Daniel, Stegner Andre Rainer, Weiss Christoph
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.

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Номер записи: 57
14-03-2013 дата публикации

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20130065379A1
Автор: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Anton Mauder, Johannes Baumgartl, Carsten Ahrens
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method of manufacturing a semiconductor device includes forming a porous area of a semiconductor body. The semiconductor body includes a porous structure in the porous area. A semiconductor layer is formed on the porous area. Semiconductor regions are formed in the semiconductor layer. Then, the semiconductor layer is separated from the semiconductor body along the porous area, including introducing hydrogen into the porous area by a thermal treatment. 1. A method of manufacturing a semiconductor device , comprising:forming a porous area at a surface of a semiconductor body, wherein the semiconductor body includes a porous structure in the porous area;forming a semiconductor layer on the porous area;forming semiconductor regions in the semiconductor layer; andintroducing hydrogen into the porous area by a thermal treatment, thereby activating a reallocation of pores and causing cavities to be generated, so that the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area.24-. (canceled)5. The method of claim 1 , wherein the hydrogen is introduced into the porous area by diffusion of the hydrogen through the semiconductor layer into the porous area.6. The method of claim 1 , wherein forming the semiconductor layer on the porous area comprises forming the semiconductor layer by epitaxial growth.7. The method of claim 1 , wherein forming the semiconductor layer on the porous area comprises forming a thickness of the semiconductor layer in a range of 5 μm to 200 μm.8. The method of claim 1 , wherein the semiconductor body is one of Si and SiC.9. The method of claim 1 , wherein forming the porous area of the semiconductor body comprises anodic dissolution of the semiconductor body.10. The method of claim 9 , wherein the anodic dissolution of the semiconductor body comprises anodic dissolution of silicon in a chemical mixture of hydrofluoric acid and ethanol or acetic acid.11. The method claim 9 , wherein forming ...

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Номер записи: 58
06-09-2012 дата публикации

Method for fabricating a porous semiconductor body region

Номер: US20120225540A1
Автор: Hans-Joachim Schulze, Anton Mauder, Francisco Javier Santos Rodriguez, SCHULZE HANS-JOACHIM, MAUDER ANTON, SANTOS RODRIGUEZ FRANCISCO JAVIER
Принадлежит:

A method for fabricating a porous semiconductor body region, comprising: 1. Method for fabricating a porous semiconductor body region , comprising:producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body,then producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench,then filling the trench with a semiconductor material of the semiconductor body.2. Method according to claim 1 , in which the at least one porous semiconductor body region is produced by means of anodic oxidation of the semiconductor body in the trench.3. Method according to claim 1 , in which the ratio L/B of length to width of the porous semiconductor body region is greater than 3.4. Method according to claim 1 , in which the trench is filled epitaxially.5. Method according to claim 1 , in which a plurality of adjacent trenches are produced claim 1 , starting from which a plurality of adjacent porous semiconductor body regions are produced.6. Method according to claim 5 , in which at least two adjacent porous semiconductor body regions are produced such that a cohesive porous semiconductor body region is created.7. Method for introducing a foreign substance into a semiconductor body claim 5 , comprising: producing at least one trench in the semiconductor body, starting from a surface of the semiconductor body,', 'then producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench,', 'then filling the trench with a semiconductor material of the semiconductor body,, 'fabricating a porous semiconductor body region, involving'}providing a foreign substance in the porous semiconductor body region,heating the semiconductor body with the porous semiconductor body region produced therein, wherein the foreign substance diffuses along ...

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Номер записи: 59
26-09-2019 дата публикации

Forming Semiconductor Devices in Silicon Carbide

Номер: US20190296125A1
Автор: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez, SCHULZE HANS-JOACHIM, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, Schulze, Hans-Joachim, Rupp, Roland, Santos Rodriguez, Francisco Javier
Принадлежит:

A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids. 1. A method , comprising:providing a first layer of porous silicon carbide supported by a silicon carbide substrate;providing a second layer of epitaxial silicon carbide on the first layer;forming a plurality of semiconductor devices in the second layer; andseparating the substrate from the second layer at the first layer.2. The method of claim 1 , wherein a thickness of the second layer is at least 20 μm or at most 30 μm.3. The method of claim 1 , wherein the porous silicon carbide of the first layer forms an interconnected network of pores.4. The method of claim 1 , wherein the first layer comprises a first sublayer having a first pore density and a second sublayer having a second pore density claim 1 , wherein the first sublayer is arranged in between the second sublayer and the substrate claim 1 , and wherein the first pore density is larger than the second pore density.5. The method of claim 1 , wherein providing the first layer comprises using an epitaxial growth process.6. The method of claim 1 , wherein providing the first layer comprises using an electrochemical etching process.7. The method of claim 1 , wherein providing the second layer comprises using an epitaxial growth process claim 1 , wherein the second layer comprises a first sublayer and a second sublayer claim 1 , wherein the first sublayer is arranged in between the second sublayer and the first layer claim 1 , and wherein a growth rate of the epitaxial growth process of the first sublayer is smaller than a growth rate of the epitaxial growth process of the second sublayer.8. The method of claim 1 , wherein the first layer comprises ...

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Номер записи: 60
10-07-2018 дата публикации

Method for forming a semiconductor device and a semiconductor device

Номер: US0010020226B2
Автор: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, RUPP ROLAND, LEHNERT WOLFGANG, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HANS-JOACHIM, Rupp, Roland, Lehnert, Wolfgang, Santos Rodriguez, Francisco Javier, Schulze, Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.

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Номер записи: 61
28-11-2019 дата публикации

Method for Processing a Semiconductor Wafer, Semiconductor Composite Structure and Support Structure for Semiconductor Wafer

Номер: US20190363057A1
Автор: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
Принадлежит:

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed. 1. A method for processing a semiconductor wafer , the method comprising:welding at least one support structure onto a semiconductor wafer; andreducing a thickness of the semiconductor wafer before or after welding the at least one support structure onto the semiconductor wafer.2. The method of claim 1 , wherein welding the at least one support structure onto the semiconductor wafer comprises:placing the at least one support structure on the semiconductor wafer; andirradiating light through the at least one support structure or through the semiconductor wafer to form a weld region,wherein the weld region is an interface between the at least one support structure and the semiconductor wafer, and/or a joining structure between the at least one support structure and the semiconductor wafer.3. The method of claim 2 , wherein light of a first wavelength is irradiated through the at least one support structure claim 2 , and wherein at least 50% of the light of the first wavelength impinging on the support structure is transmitted through the support structure and reaches the weld region.4. The method of claim 1 , further comprising:before welding the at least one support structure, forming an absorption region on the semiconductor wafer or on the at least one support structure.5. The method of claim 4 , wherein the ...

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Номер записи: 62
01-02-2022 дата публикации

Semiconductor wafers and semiconductor devices with barrier layer and methods of manufacturing

Номер: US0011239384B2
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIESAG

A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

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Номер записи: 63
01-10-2015 дата публикации

Lithium Ion Battery, Integrated Circuit and Method of Manufacturing a Lithium Ion Battery

Номер: US20150280288A1
Автор: Vijaye Kumar Rajaraman, Kamil Karlovsky, Thomas Neidhart, Karl Mayer, Rainer Leuschner, Christine Moser, Ravi Keshav Joshi, Alexander Breymesser, Bernhard Goller, Francisco Javier Santos Rodriguez, Peter Zorn
Принадлежит:

A lithium ion battery includes a first substrate having a first main surface, and a lid including an insulating material. The lid is attached to the first main surface of the first substrate, and a cavity is defined between the first substrate and the lid. The lithium ion battery further includes an electrical interconnection element in the lid, the electrical interconnection element providing an electrical connection between a first main surface and a second main surface of the lid. The lithium ion battery further includes an electrolyte in the cavity, an anode at the first substrate, the anode including a component made of a semiconductor material, and a cathode at the lid. 1. A lithium ion battery , comprising:a first substrate having a first main surface;a lid comprising an insulating material, the lid being attached to the first main surface of the first substrate, a cavity being defined between the first substrate and the lid;an electrical interconnection element in the lid, the electrical interconnection element providing an electrical connection between a first main surface and a second main surface of the lid;an electrolyte in the cavity;an anode at the first substrate, the anode comprising a component made of a semiconductor material; anda cathode at the lid.2. The lithium ion battery according to claim 1 , wherein the cavity comprises a recess in the lid claim 1 , the cathode being disposed in the recess.3. The lithium ion battery according to claim 1 , wherein the first substrate includes a patterned structure.4. The lithium ion battery according to claim 1 , wherein the electrical interconnection element comprises a via hole extending from the first main surface to the second main surface claim 1 , the via hole being filled with a conductive material.5. The lithium ion battery according to claim 1 , wherein the first substrate is a semiconductor substrate and the lid comprises a glass substrate.6. The lithium ion battery according to claim 1 , further ...

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Номер записи: 64
26-12-2023 дата публикации

Rogowski coil integrated in glass substrate

Номер: US0011856711B2
Автор: Alexander Breymesser, Francisco Javier Santos Rodriguez, Klaus Sobe
Принадлежит: Infineon Technologies Austria AG

A method of forming a current measurement device includes providing a glass substrate having first and second substantially planar surfaces that are opposite one another, forming a plurality of through-vias in the glass substrate that each extend between the first and second substantially planar surfaces, and forming conductive tracks on the glass substrate that connect adjacent ones of the through-vias together. Forming the plurality of through-vias includes applying radiation to the glass substrate, and the conductive tracks and the through-vias collectively form a coil structure in the glass substrate.

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Номер записи: 65
26-08-2014 дата публикации

Semiconductor device with buried electrode

Номер: US0008816503B2
Автор: Carsten Ahrens, Johannes Baumgartl, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит: Infineon Technologies Austria AG

A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.

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Номер записи: 66
07-04-2020 дата публикации

Superjunction structure in a power semiconductor device

Номер: US0010615040B2
Автор: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Ronny Kern, Francisco Javier Santos Rodriguez, Carsten von Koblinski, RUPP ROLAND, BREYMESSER ALEXANDER, BROCKMEIER ANDRE, KERN RONNY, SANTOS RODRIGUEZ FRANCISCO JAVIER, VON KOBLINSKI CARSTEN, Rupp, Roland, Breymesser, Alexander, Brockmeier, Andre, Kern, Ronny, Santos Rodriguez, Francisco Javier, von Koblinski, Carsten
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method of processing a power semiconductor device includes: providing a semiconductor body of the power semiconductor device; coupling a mask to the semiconductor body; and subjecting the semiconductor body to an ion implantation such that implantation ions traverse the mask prior to entering the semiconductor body.

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Номер записи: 67
05-05-2020 дата публикации

Method of forming a semiconductor device

Номер: US0010643897B2
Автор: Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HANS-JOACHIM, Rupp, Roland, Santos Rodriguez, Francisco Javier, Schulze, Hans-Joachim
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

Methods of forming a semiconductor device are provided. A method includes introducing impurities into a part of a semiconductor substrate at a first surface of the semiconductor substrate by ion implantation, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate. The method further includes forming a semiconductor layer on the first surface of the semiconductor substrate. The method further includes irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate local damage of a crystal lattice of the semiconductor substrate. The method further includes separating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, where the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical ...

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Номер записи: 68
27-04-2023 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AND SEMICONDUCTOR DEVICE

Номер: US20230125859A1
Автор: Daniel Schlögl, Hans-Joachim Schulze, Moriz Jelinek, Francisco Javier Santos Rodriguez
Принадлежит:

A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. The method includes implanting protons through the second surface into the semiconductor body. The method further includes implanting ions through the second surface into the semiconductor body. The ions are ions of a non-doping element having an atomic number of at least 9. Thereafter, the method further includes processing the semiconductor body by thermal annealing.

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Номер записи: 69
17-10-2017 дата публикации

Method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure

Номер: US0009793167B2
Автор: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, RUPP ROLAND, LEHNERT WOLFGANG, SANTOS RODRIGUEZ FRANCISCO JAVIER, Rupp Roland, Lehnert Wolfgang, Santos Rodriguez Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite, splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed, removing the carrier wafer above an inner portion of the split layer while leaving a residual portion of the carrier wafer attached to the split layer to form a partially supported wafer, and further processing the partially supported wafer.

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Номер записи: 70
22-12-2016 дата публикации

Semiconductor to Metal Transition for Semiconductor Devices

Номер: US20160372539A1
Автор: Andreas Haertl, Frank Hille, Francisco Javier Santos Rodriguez, Daniel Schloegl, Andre Rainer Stegner, Christoph Weiss, HAERTL ANDREAS, HILLE FRANK, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHLOEGL DANIEL, STEGNER ANDRE RAINER, WEISS CHRISTOPH, Haertl Andreas, Hille Frank, Santos Rodriguez Francisco Javier, Schloegl Daniel, Stegner Andre Rainer, Weiss Christoph
Принадлежит:

A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region. 1. A semiconductor device comprising a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers , wherein the first semiconductor region comprises:a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers;a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration; anda damage region between the contact region and the transition region, the damage region being configured to reduce lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.2. The semiconductor device of claim 1 , wherein the contact region is doped with a contact region doping material claim 1 , the contact region doping material comprising at least one of boron and phosphorus claim 1 , and wherein the contact region doping material establishes a presence of the first ...

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Номер записи: 71
06-07-2017 дата публикации

METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20170194450A1
Автор: Hans-Joachim Schulze, Andreas Haertl, Francisco Javier Santos Rodriguez, André Rainer Stegner, Daniel Schloegl, SCHULZE HANS-JOACHIM, HAERTL ANDREAS, SANTOS RODRIGUEZ FRANCISCO JAVIER, STEGNER ANDRÉ RAINER, SCHLOEGL DANIEL, Schulze Hans-Joachim, Haertl Andreas, Santos Rodriguez Francisco Javier, Stegner André Rainer, Schloegl Daniel
Принадлежит:

A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body. 1. A semiconductor device , comprising:a semiconductor body;a plurality of regions in the semiconductor body each comprising a eutectic of a first metallization material and material of the semiconductor body; anda second metallization material disposed over the semiconductor body and in contact with the at least one region of the a plurality of regions in the semiconductor body.2. The semiconductor device of claim 1 , wherein two or more of the plurality of regions are non-contiguous and separated by a portion of the semiconductor body.3. The semiconductor device of claim 1 , wherein the plurality of regions are spike-shaped regions.4. The semiconductor device of claim 3 , wherein at least one of the plurality of spike-shaped regions extends to a depth of about 100 nm to about 1 μm claim 3 , measured from a surface of the semiconductor body.5. The semiconductor device of claim 3 , wherein at least one of the plurality of spike-shaped regions has a first diameter proximate a surface of the semiconductor body and a second diameter distant from the surface of the semiconductor body claim 3 , wherein the first diameter is larger than the second diameter.6. The semiconductor device of claim 3 , wherein a diameter of at least one of the plurality of spike-shaped regions at a surface of the semiconductor body is in a range from about 200 nm to about 2 μm.7. The semiconductor device of claim 3 , wherein a distance between at least two neighboring spike-shaped ...

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Номер записи: 72
22-08-2023 дата публикации

Methods of re-using a silicon carbide substrate

Номер: US0011735642B2
Автор: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
Принадлежит: Infineon Technologies AG

A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.

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Номер записи: 73
06-10-2020 дата публикации

Method for processing a wafer, and layer stack

Номер: US0010796914B2
Автор: Francisco Javier Santos Rodriguez, SANTOS RODRIGUEZ FRANCISCO JAVIER, Santos Rodriguez, Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

In various embodiments, a method for processing a wafer is provided. The method includes forming a layer stack, including a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, a lower mechanical and/or chemical resistance than the support layer and than the useful layer. The support layer has a depression, which exposes the sacrificial region. The method further includes forming at least one channel in the exposed sacrificial region by means of the processing fluid. The channel connects the depression to an exterior of the layer stack.

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Номер записи: 74
03-12-2019 дата публикации

Method of manufacturing a semiconductor device having an undulated profile of net doping in a drift zone

Номер: US0010497801B2
Автор: Elmar Falck, Andreas Haertl, Manfred Pfaffenlehner, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze, Andre Stegner, Johannes Georg Laven, FALCK ELMAR, HAERTL ANDREAS, PFAFFENLEHNER MANFRED, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHLOEGL DANIEL, SCHULZE HANS-JOACHIM, STEGNER ANDRE, LAVEN JOHANNES GEORG, Falck, Elmar, Haertl, Andreas, Pfaffenlehner, Manfred, Santos Rodriguez, Francisco Javier, Schloegl, Daniel, Schulze, Hans-Joachim, Stegner, Andre, Laven, Johannes Georg
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 1×1013 cm−3 and 5×1014 cm−3.

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Номер записи: 75
01-06-2017 дата публикации

METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE

Номер: US20170154857A1
Автор: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez, YEDURU SRINIVASA REDDY, GASSER KARL HEINZ, WOEHLERT STEFAN, MAYER KARL, SANTOS RODRIGUEZ FRANCISCO JAVIER, Yeduru Srinivasa Reddy, Gasser Karl Heinz, Woehlert Stefan, Mayer Karl, Santos Rodriguez Francisco Javier
Принадлежит:

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer. 1. A wafer structure , comprising:a wafer;a structure formed at an edge region on one side of the wafer, the structure at least partially surrounding an inner portion of the wafer and the structure comprising an upper surface; andprinted material in the inner portion of the wafer;wherein an upper surface of the printed material and the upper surface of the structure are level with each other.2. The wafer structure of claim 1 ,wherein the structure is a ring structure at least partially surrounding the inner portion of the wafer.3. The wafer structure of claim 2 ,wherein the ring structure is enclosing the inner portion of the wafer.4. The wafer structure of claim 2 ,wherein the ring structure is a circular ring structure.5. The wafer structure of claim 2 ,wherein the structure is a Taiko ring structure.6. The wafer structure of claim 1 ,wherein the structure has a height of less than or equal to 25 μm.7. The wafer structure of claim 1 ,wherein the structure is formed on a backside of the wafer.8. The wafer structure of claim 1 ,wherein the printed material is printed with a material thickness of less than or equal to 25 μm.9. The wafer structure of claim 1 ...

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Номер записи: 76
07-04-2020 дата публикации

Method for producing IGBT with dV/dt controllability

Номер: US0010615272B2
Автор: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez, VELLEI ANTONIO, BINA MARKUS, DAINESE MATTEO, JAEGER CHRISTIAN, LAVEN JOHANNES GEORG, PHILIPPOU ALEXANDER, SANTOS RODRIGUEZ FRANCISCO JAVIER, Vellei, Antonio, Bina, Markus, Dainese, Matteo, Jaeger, Christian, Laven, Johannes Georg, Philippou, Alexander, Santos Rodriguez, Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

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Номер записи: 77
30-03-2017 дата публикации

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND METHOD FOR OPERATING AN ELECTRONIC DEVICE

Номер: US20170092659A1
Автор: Thoralf Kautzsch, Alessia Scire, Steffen Bieselt, Franz Hirler, Anton Mauder, Wolfgang Scholz, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, KAUTZSCH THORALF, SCIRE ALESSIA, BIESELT STEFFEN, HIRLER FRANZ, MAUDER ANTON, SCHOLZ WOLFGANG, SCHULZE HANS-JOACHIM, SANTOS RODRIGUEZ FRANCISCO JAVIER, Kautzsch Thoralf, Scire Alessia, Bieselt Steffen, Hirler Franz, Mauder Anton, Scholz Wolfgang, Schulze Hans-Joachim, Santos Rodriguez Francisco Javier
Принадлежит:

According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material. 1. A method for manufacturing an electronic device , the method comprising:providing a carrier comprising a hollow chamber structure within the carrier;forming a first trench structure extending from a surface of the carrier to the at least one hollow chamber structure such that an electrically isolated region is formed over the hollow chamber structure; and at the same time,forming at least one second trench structure extending from the surface of the carrier into a second region of the carrier, the second region of the carrier being laterally adjacent to the electrically isolated region, the second trench structure being at least a part of an electronic component provided in the second region of the carrier.2. The method of claim 1 ,wherein forming at least one first trench structure and forming at least one second trench structure further comprises covering at least one sidewall of each trench structure with an electrically insulating material (e.g. an oxide).3. The method of claim 1 ,wherein forming at least one first trench structure and forming at least one second trench structure further comprises at least partially filling the least one first trench structure and the least one second trench structure with an electrically conductive material ...

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Номер записи: 78
23-05-2019 дата публикации

Method of Manufacturing a Semiconductor Device Having an Undulated Profile of Net Doping in a Drift Zone

Номер: US20190157435A1
Автор: Elmar Falck, Andreas Haertl, Manfred Pfaffenlehner, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze, Andre Stegner, Johannes Georg Laven, FALCK ELMAR, HAERTL ANDREAS, PFAFFENLEHNER MANFRED, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHLOEGL DANIEL, SCHULZE HANS-JOACHIM, STEGNER ANDRE, LAVEN JOHANNES GEORG, Falck, Elmar, Haertl, Andreas, Pfaffenlehner, Manfred, Santos Rodriguez, Francisco Javier, Schloegl, Daniel, Schulze, Hans-Joachim, Stegner, Andre, Laven, Johannes Georg
Принадлежит:

A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 1×10cmand 5×10cm. 1. A method of manufacturing a semiconductor device , the method comprising:forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons; and generating hydrogen-related donors by annealing the semiconductor body,{'sup': 13', '−3', '14', '−3, 'wherein at least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 1×10cmand 5×10cm.'}2. The method of claim 1 , wherein the annealing is carried out in a temperature range of 300° C. and 500° C. for a duration between one to four hours.3. The method of claim 1 , wherein the multiple irradiations with protons is carried out from the second side.4. The method of claim 1 , further comprising forming distinct p-doped regions at the second sides claim 1 , and forming a continuous n-region laterally surrounding the distinct p-doped regions at the second side.5. The method of claim 1 , further comprising forming p-doped regions buried in the semiconductor body at the second side and embedded in n-doped semiconductor material of the semiconductor body.6. The method of claim 1 , wherein the undulated profile of net doping of the drift zone includes hydrogen-related donors.7. The method of claim 1 , wherein the undulated profile of net doping of the drift zone includes at least two minima claim 1 , and wherein a doping concentration of the at least two minima decreases from the second side to the first side.8. The method of claim 1 , further ...

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Номер записи: 79
09-08-2018 дата публикации

Method of Manufacturing Semiconductor Devices by Using Epitaxy and Semiconductor Devices with a Lateral Structure

Номер: US20180226471A1
Автор: Frank Hille, Andre Brockmeier, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze
Принадлежит:

Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed. 1. A method of manufacturing semiconductor devices , the method comprising:forming epitaxy troughs in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material;forming crystalline epitaxy regions of a second semiconductor material in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density; andforming, from the epitaxy regions, at least main body portions of semiconductor bodies of the semiconductor devices.2. The method of claim 1 , wherein the first and second semiconductor materials have a same main constituent or same main constituents.3. The method of claim 2 , wherein the same main constituent is silicon or the same main constituents is silicon carbide.4. The method of claim 1 , whereinforming at least the main body portions comprises forming, in each main body portion, an anode/body well forming a first pn junction with a main structure in the semiconductor body.5. The method of claim 1 , wherein forming at least the main body portions comprises forming claim 1 , in each main body portion claim 1 , a plurality of transistor cells electrically arranged in series.6. The method of claim 1 , further comprising diffusing impurities from the matrix section into the epitaxy regions.7. ...

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Номер записи: 80
19-05-2016 дата публикации

Semiconductor to Metal Transition

Номер: US20160141406A1
Автор: Andreas Haertl, Frank Hille, Francisco Javier Santos Rodriguez, Daniel Schloegl, Andre Rainer Stegner, Christoph Weiss, HAERTL ANDREAS, HILLE FRANK, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHLOEGL DANIEL, STEGNER ANDRE RAINER, WEISS CHRISTOPH
Принадлежит:

A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region. 1. A semiconductor device comprising a diffusion barrier layer , a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers , wherein the first semiconductor region comprises:a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers;a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration; anda damage region between the contact region and the transition region, the damage region being configured to reduce the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.2. The semiconductor device of claim 1 , wherein the contact region is doped with a contact region ...

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Номер записи: 81
22-12-2016 дата публикации

Method for Manufacturing a Semiconductor Device by Hydrogen Treatment

Номер: US20160372336A1
Автор: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Anton Mauder, Johannes Baumgartl, Carsten Ahrens, SCHULZE HANS-JOACHIM, SANTOS RODRIGUEZ FRANCISCO JAVIER, MAUDER ANTON, BAUMGARTL JOHANNES, AHRENS CARSTEN, Schulze Hans-Joachim, Santos Rodriguez Francisco Javier, Mauder Anton, Baumgartl Johannes, Ahrens Carsten
Принадлежит:

A method of manufacturing a semiconductor device includes: forming a porous area at a surface of a semiconductor body; forming a semiconductor layer on the porous area by epitaxial growth; forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device. 1. A method of manufacturing a semiconductor device , the method comprising:forming a porous area at a surface of a semiconductor body;forming a semiconductor layer on the porous area by epitaxial growth;forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device;introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; andapplying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device.2. The method of claim 1 , wherein the hydrogen is introduced into the porous area by diffusion of the hydrogen through the semiconductor layer into the porous area.3. The method of claim 1 , wherein the ...

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Номер записи: 82
19-11-2020 дата публикации

Semiconductor Wafers and Semiconductor Devices with Barrier Layer and Methods of Manufacturing

Номер: US20200365754A1
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze, SANTOS RODRIGUEZ FRANCISCO JAVIER, RUPP ROLAND, SCHULZE HANS-JOACHIM, Santos Rodriguez, Francisco Javier, Rupp, Roland, Schulze, Hans-Joachim
Принадлежит:

A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface. 1. A semiconductor wafer comprising:a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface;a barrier layer from at least one of silicon carbide, a ternary nitride and a ternary carbide disposed on the rear side surface; anda passivation layer directly disposed on at least one of the front side surface and the rear side surface.2. The semiconductor wafer of claim 1 , wherein the barrier layer is directly disposed on the semiconductor slice.3. The semiconductor wafer of claim 1 , wherein the passivation layer is disposed on both the front side surface and the rear side surface.4. The semiconductor wafer of claim 1 , further comprising:a supplementary layer from polycrystalline silicon disposed between the rear side surface and the barrier layer.5. The semiconductor wafer of claim 1 , wherein the passivation layer comprises a thermal semiconductor oxide.6. The semiconductor wafer of claim 1 , wherein a portion of the passivation layer disposed on the front side surface comprises at least one of silicon carbide claim 1 , ternary nitride and ternary carbide.7. The semiconductor wafer of claim 1 , wherein the semiconductor slice is cylindrical and an outer lateral surface of the semiconductor slice comprises at least one of a flat and a notch.8. The semiconductor wafer of claim 1 , wherein an outer lateral surface of the semiconductor slice comprises four orthogonal sections.9. A semiconductor device comprising:semiconductor elements disposed at a front side of a semiconductor portion; anda barrier portion comprising at least one of ...

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Номер записи: 83
28-04-2022 дата публикации

Rogowski Coil Integrated in Glass Substrate

Номер: US20220132677A1
Автор: Alexander Breymesser, Francisco Javier Santos Rodriguez, Klaus Sobe
Принадлежит:

A method of forming a current measurement device includes providing a glass substrate having first and second substantially planar surfaces that are opposite one another, forming a plurality of through-vias in the glass substrate that each extend between the first and second substantially planar surfaces, and forming conductive tracks on the glass substrate that connect adjacent ones of the through-vias together. Forming the plurality of through-vias includes applying radiation to the glass substrate, and the conductive tracks and the through-vias collectively form a coil structure in the glass substrate.

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Номер записи: 84
01-09-2020 дата публикации

Wafer carrier, method for manufacturing the same and method for carrying a wafer

Номер: US0010763151B2
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Ronny Kern, Josef Unterweger
Принадлежит: Infineon Technologies AG

A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for carrying the wafer. The first and the second foil are connected to each other so as to form the chamber. The chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried.

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Номер записи: 85
26-05-2020 дата публикации

Method for processing a semiconductor device and semiconductor device

Номер: US0010665687B2
Автор: Hans-Joachim Schulze, Andreas Haertl, Francisco Javier Santos Rodriguez, André Rainer Stegner, Daniel Schloegl, SCHULZE HANS-JOACHIM, HAERTL ANDREAS, SANTOS RODRIGUEZ FRANCISCO JAVIER, STEGNER ANDRÉ RAINER, SCHLOEGL DANIEL, Schulze, Hans-Joachim, Haertl, Andreas, Santos Rodriguez, Francisco Javier, Stegner, André Rainer, Schloegl, Daniel
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.

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Номер записи: 86
29-05-2008 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SUCH A DEVICE

Номер: US20080122041A1
Автор: Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten von Koblinski
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 87
25-05-2017 дата публикации

METHOD FOR THINNING SUBSTRATES

Номер: US20170148664A1
Автор: Roland Rupp, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Iris Moder, Ingo Muri, RUPP ROLAND, SCHULZE HANS-JOACHIM, RODRIGUEZ FRANCISCO JAVIER SANTOS, MODER IRIS, MURI INGO, Rupp Roland, Schulze Hans-Joachim, Rodriguez Francisco Javier Santos, Moder Iris, Muri Ingo
Принадлежит:

According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer. 1. A method , comprising:providing a substrate having a first side and a second side opposite the first side;forming a buried layer at least one of in or over the substrate by processing the first side of the substrate,thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.2. The method of claim 1 , further comprising:forming an epitaxial layer over the substrate, wherein the buried layer is formed at least one of in the substrate, in the epitaxial layer, or between the substrate and the epitaxial layer.3. The method of claim 2 ,wherein the epitaxial layer comprises a material of the substrate.4. The method of claim 1 ,wherein forming the buried layer comprises implanting a chemical element having a greater electronegativity than the substrate.5. The method of claim 1 ,wherein forming the buried layer in the substrate comprises:forming a plurality of trenches into the substrate;introducing a chemical element having a higher electronegativity than the substrate through the plurality of trenches into the substrate;filling the plurality of trenches.6. The method of claim 2 , further comprising:forming at least one of the following circuit components in the epitaxial layer: an insulated-gate bipolar transistor, a diode, a transistor, a metal-oxide semiconductor field-effect transistor, a power metal-oxide ...

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Номер записи: 88
11-11-2021 дата публикации

Methods for Processing a Wide Band Gap Semiconductor Wafer Using a Support Layer and Methods for Forming a Plurality of Thin Wide Band Gap Semiconductor Wafers Using Support Layers

Номер: US20210351077A1
Автор: Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
Принадлежит:

A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer. 1. A method for processing a wide band gap semiconductor wafer , the method comprising:depositing a support layer comprising semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon;depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; andsplitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.2. The method of claim 1 , wherein a thermal expansion coefficient of the support layer differs from a thermal expansion coefficient of the wide band gap semiconductor wafer by at most 10% of the thermal expansion coefficient of the wide band gap semiconductor wafer.3. The method of claim 1 , wherein the support layer is deposited at a deposition rate of at least 50 μm/hour.4. The method of claim 1 , wherein the support layer is a poly-silicon carbide layer or a molybdenum layer.5. The method of claim 1 , wherein a total thickness of the remaining wafer including the support layer is at least 200 μm and at most 1500 μm.6. The method of claim 1 , wherein a protective layer is located at the front side of the wide band gap semiconductor wafer during the depositing of the support layer.7. The method of claim 1 , further comprising: ...

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Номер записи: 89
23-01-2024 дата публикации

Method of manufacturing a semiconductor device and semiconductor wafer

Номер: US0011881406B2
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
Принадлежит: Infineon Technologies AG

A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.

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Номер записи: 90
08-06-2021 дата публикации

Forming semiconductor devices in silicon carbide

Номер: US0011031483B2
Автор: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez, SCHULZE HANS-JOACHIM, RUPP ROLAND, SANTOS RODRIGUEZ FRANCISCO JAVIER, Schulze, Hans-Joachim, Rupp, Roland, Santos Rodriguez, Francisco Javier
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

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Номер записи: 91
14-08-2018 дата публикации

Method for thinning substrates

Номер: US0010049914B2
Автор: Roland Rupp, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Iris Moder, Ingo Muri, RUPP ROLAND, SCHULZE HANS-JOACHIM, RODRIGUEZ FRANCISCO JAVIER SANTOS, MODER IRIS, MURI INGO, Rupp, Roland, Schulze, Hans-Joachim, Rodriguez, Francisco Javier Santos, Moder, Iris, Muri, Ingo
Принадлежит: Infineon Technologies AG, INFINEON TECHNOLOGIES AG

According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

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Номер записи: 92
14-04-2016 дата публикации

Method for Manufacturing a Semiconductor Wafer, and Semiconductor Device Having a Low Concentration of Interstitial Oxygen

Номер: US20160104622A1
Автор: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIES AG

A method for manufacturing a substrate wafer includes providing a device wafer () having a first side () and a second side (); subjecting the device wafer () to a first high temperature process for reducing the oxygen content of the device wafer () at least in a region () at the second side (); bonding the second side () of the device wafer () to a first side () of a carrier wafer () to form a substrate wafer (); processing the first side () of the substrate wafer () to reduce the thickness of the device wafer (); subjecting the substrate wafer () to a second high temperature process for reducing the oxygen content at least of the device wafer (); and at least partially integrating at least one semiconductor component () into the device wafer () after the second high temperature process. 1. A method for manufacturing a substrate wafer , the method comprising:providing a device wafer having a first side and a second side opposite the first side, the device wafer being made of a semiconductor material and having a first thickness;subjecting the device wafer to a first high temperature process for reducing the oxygen content of the device wafer at least in a region at the second side;bonding the second side of the device wafer to a first side of a carrier wafer to form a substrate wafer comprising the device wafer bonded to the carrier wafer, the carrier wafer having a second side opposite the first side which second side of the carrier wafer forms the second side of the substrate wafer, wherein the first side of the device wafer forms a first side of the substrate wafer;processing the first side of the substrate wafer, which is formed by the first side of the device wafer, to reduce the thickness of the device wafer to a second thickness less than the first thickness of the device wafer;subjecting the substrate wafer to a second high temperature process for reducing the oxygen content at least of the device wafer bonded to the carrier wafer;at least partially ...

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Номер записи: 93
14-12-2017 дата публикации

Superjunction Structure in a Power Semiconductor Device

Номер: US20170358452A1
Автор: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Ronny Kern, Francisco Javier Santos Rodriguez, Carsten von Koblinski
Принадлежит: INFINEON TECHNOLOGIES AG

A method of processing a power semiconductor device includes: providing a semiconductor body of the power semiconductor device; coupling a mask to the semiconductor body; and subjecting the semiconductor body to an ion implantation such that implantation ions traverse the mask prior to entering the semiconductor body.

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Номер записи: 94
03-07-2012 дата публикации

Device and method including a soldering process

Номер: US0008211752B2
Автор: Paul Ganitzer, Francisco Javier Santos Rodriguez, Martin Sporn, Daniel Kraft, GANITZER PAUL, RODRIGUEZ FRANCISCO JAVIER SANTOS, SPORN MARTIN, KRAFT DANIEL
Принадлежит: Infineon Technologies AG, GANITZER PAUL, RODRIGUEZ FRANCISCO JAVIER SANTOS, SPORN MARTIN, KRAFT DANIEL, INFINEON TECHNOLOGIES AG

A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

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Номер записи: 95
07-01-2020 дата публикации

Method for processing one semiconductor wafer or a plurality of semiconductor wafers and protective cover for covering the semiconductor wafer

Номер: US0010529612B2
Автор: Francisco Javier Santos Rodriguez, Roland Rupp, SANTOS RODRIGUEZ FRANCISCO JAVIER, RUPP ROLAND, Santos Rodriguez, Francisco Javier, Rupp, Roland
Принадлежит: INFINEON TECHNOLOGIES AG, Infineon Technologies AG

In various embodiments, a method for processing a semiconductor wafer is provided. The semiconductor wafer includes a first main processing side and a second main processing side, which is arranged opposite the first main processing side, and at least one circuit region having at least one electronic circuit on the first main processing side. The method includes forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region, and thinning the semiconductor wafer, including the stiffening structure, from the second main processing side.

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Номер записи: 96
08-02-2024 дата публикации

Power Semiconductor Device, Method of Producing a Power Semiconductor Device and Method of Operating a Power Semiconductor Device

Номер: US20240047457A1
Автор: Francisco Javier Santos Rodriguez, Roman Baburske, Hans-Joachim Schulze, Daniel Schlögl
Принадлежит:

A power semiconductor device includes at a first side and electrically isolated from first and second load terminals, first control electrodes for controlling a load current in first semiconductor channel structures formed in an active region at the first side, and at a second side and electrically isolated from the first and second load terminals, second control electrodes for controlling the load current in second semiconductor channel structures formed in the active region at the second side. At the second side and in a contiguous area of modified control (AMC) belonging to the active region and having a lateral extension of at least 30% of a thickness of a semiconductor body of the device, either no second control electrodes are provided or the second control electrodes are less effective in removing free charge carriers out of the power semiconductor device than the second control electrodes outside the AMC.

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Номер записи: 97
15-02-2022 дата публикации

Power semiconductor device and method of processing a power semiconductor device

Номер: US0011251266B2
Автор: Philip Christoph Brandt, Manfred Pfaffenlehner, Frank Dieter Pfirsch, Francisco Javier Santos Rodriguez, Steffen Schmidt, Frank Umbach
Принадлежит: Infineon Technologies AG

A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.

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Номер записи: 98
27-06-2013 дата публикации

METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE

Номер: US20130164939A1
Автор: Gerald Lackner, Christian Maier, Francisco Javier Santos Rodriguez
Принадлежит: Infineon Technologies AG

Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area. 1. A method comprising:placing a semiconductor wafer in contact with a substrate holder at a first location and a second location of the substrate holder, wherein the second location projects with respect to the first location; andprocessing the semiconductor wafer.2. The method of claim 1 , further comprising producing a reduced pressure between the semiconductor wafer and the substrate holder.3. The method of claim 1 , further comprising moving the second location with respect to the first location until the first location is in contact with the semiconductor wafer and the second location is in contact with the semiconductor wafer.4. The method of claim 1 , further comprising forcing the second location away from the first location.5. The method of claim 4 , wherein forcing the second location away from the first location further comprises forcing the second location away from the first location with springs.6. The method of claim 1 , further comprising pressing a contact needle in a direction of the semiconductor wafer.7. The method of claim 1 , further comprising pressing a plurality of contact needles in a direction of the semiconductor wafer.8. The method of claim 1 , wherein placing the semiconductor wafer in contact with the substrate holder further comprises placing the semiconductor wafer in contact with the substrate holder at a first surface area and a second surface area of the substrate holder claim 1 , wherein the second surface area projects with respect to the first surface area.9. The method of claim 1 , wherein processing the ...

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Номер записи: 99
02-02-2017 дата публикации

Method for Forming a Semiconductor Device and a Semiconductor Device

Номер: US20170033011A1
Автор: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, RUPP ROLAND, LEHNERT WOLFGANG, SANTOS RODRIGUEZ FRANCISCO JAVIER, SCHULZE HANS-JOACHIM, Rupp Roland, Lehnert Wolfgang, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer. 1. A method for forming a semiconductor device , comprising:providing a wafer stack comprising a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material, the device wafer having a first side and a second side opposite the first side, the second side being attached to the carrier wafer;defining device regions of the wafer stack;partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; andfurther processing the device wafer while the device wafer remains supported by the residual of the carrier wafer.2. The method of claim 1 , further comprising at least one of:forming front-side metallizations on the first side in the device regions so that the front-side metallizations are separated from each other;forming a back-side metallization in at least one of the device regions comprising filling the openings in the carrier wafer with a conductive material; andremoving the residual of the carrier wafer after forming the back-side metallization.3. The method of claim 2 , wherein further processing comprises at least one of:temporarily contacting the front-side metallization in ...

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Номер записи: 100
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 101
05-04-2012 дата публикации

Semiconductor Devices and Methods of Manufacturing Thereof

Номер: US20120080686A1
Автор: Hirler Franz, Mauder Anton, Rodriguez Francisco Javier Santos, Schulze Hans-Joachim, Timme Hans-Joerg
Принадлежит:

In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer. 1. A method of forming a semiconductor device , the method comprising:forming a first porous semiconductor layer over a top surface of a substrate;forming a first epitaxial layer over the first porous semiconductor layer; andforming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer.2. The method of claim 1 , wherein the substrate is a silicon wafer.3. The method of claim 1 , wherein forming the first porous semiconductor layer comprises:depositing an optional epitaxial layer; andelectrochemically etching at least a portion of the optional epitaxial layer.4. The method of claim 3 , wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping claim 3 , and a second layer having a second doping different from the first layer.5. The method of claim 1 , wherein forming the first porous semiconductor layer comprises:converting a top region of the substrate into the first porous semiconductor layer by etching.6. The method of claim 1 , further comprising:thinning the substrate from a back surface to form a thinned substrate; anddicing the substrate to form singulated chips.7. The method of claim 6 , wherein the thinning removes the first porous semiconductor layer.8. The method of claim 6 , wherein the thinning is stopped before reaching the first porous semiconductor layer.9. The method of claim 6 , wherein the thinning exposes a surface of the first porous semiconductor layer claim 6 , the method further comprising forming a back side contact by depositing a metal layer over the ...

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Номер записи: 102
28-02-2013 дата публикации

Semiconductor Device with Buried Electrode

Номер: US20130049203A1
Автор: Ahrens Carsten, Baumgartl Johannes, Rodriguez Francisco Javier Santos, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate. 1. A semiconductor device , comprising:an active device region formed in an epitaxial layer disposed on a semiconductor substrate; anda buried electrode disposed below the active device region in a cavity formed within the semiconductor substrate, the buried electrode comprising an electrically conductive material different than the material of the semiconductor substrate.2. The semiconductor device of claim 1 , wherein the buried electrode comprises a metal material.3. The semiconductor device of claim 2 , wherein the buried electrode comprises TiN or Tungsten.4. The semiconductor device of claim 1 , wherein the buried electrode comprises polysilicon.5. The semiconductor device of claim 1 , wherein the buried electrode comprises carbon.6. The semiconductor device of claim 1 , further comprising an electrically conductive contact which extends from the buried electrode to a surface of the semiconductor substrate.7. The semiconductor device of claim 6 , wherein the contact extends vertically from the buried electrode to the surface of the semiconductor substrate on which the epitaxial layer is disposed.8. The semiconductor device of claim 6 , wherein the contact extends vertically from the buried electrode to the opposite surface of the semiconductor substrate on which the epitaxial layer is disposed.9. The semiconductor device of claim 6 , wherein the contact extends laterally from the buried electrode to a side surface of the semiconductor substrate which is disposed between top and bottom surfaces of the semiconductor substrate.10. The semiconductor ...

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Номер записи: 103
12-09-2013 дата публикации

Semiconductor device, wafer assembly and methods of manufacturing wafer assemblies and semiconductor devices

Номер: US20130234297A1
Автор: Alexander Breymesser, Andre Brockmeier, Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Gerhard Schmidt, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls.

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Номер записи: 104
12-09-2013 дата публикации

Glass Piece and Methods of Manufacturing Glass Pieces and Semiconductor Devices with Glass Pieces

Номер: US20130237034A1
Автор: Breymesser Alexander, Brockmeier Andre, Santos Rodriguez Francisco Javier, von Koblinski Carsten
Принадлежит: INFINEON TECHNOLOGIES AG

A source material, which is based on a glass, is arranged on a working surface of a mold substrate. The mold substrate is made of a single-crystalline material. A cavity is formed in the working surface. The source material is pressed against the mold substrate. During pressing a temperature of the source material and a force exerted on the source material are controlled to fluidify source material. The fluidified source material flows into the cavity. Re-solidified source material forms a glass piece with a protrusion extending into the cavity. After re-solidifying, the glass piece may be bonded to the mold substrate. On the glass piece, protrusions and cavities can be formed with slope angles less than 80 degrees, with different slope angles, with different depths and widths of 10 micrometers and more. 1. A method of manufacturing a glass piece , the method comprising:bringing a source material based on a glass in contact with a working surface of a mold substrate which is made of a single-crystalline material, the working surface provided with a cavity; andpressing the source material and the mold substrate against each other, wherein a temperature of the source material and a force exerted on the source material are controlled such that fluidified source material flows into the cavity.2. The method according to claim 1 , further comprising controlling the temperature and the force to re-solidify the fluidified source material claim 1 , the re-solidified source material forming a glass piece with a protrusion extending into the cavity.3. The method according to claim 1 , further comprising controlling the temperature and the force to re-solidify the fluidified source material claim 1 , the re-solidified source material forming a glass piece with a protrusion that fills the cavity completely.4. The method according to claim 1 , wherein the source material is a material exhibiting a glass transition claim 1 , and the temperature of the source material is controlled ...

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Номер записи: 105
19-12-2013 дата публикации

METHOD FOR FABRICATING A POROUS SEMICONDUCTOR BODY REGION

Номер: US20130337640A1
Автор: Mauder Anton, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for fabricating a porous semiconductor body region, including producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and filling the trench with a semiconductor material of the semiconductor body. 1. A method for introducing a dopant into a semiconductor body , comprising: producing at least one trench in the semiconductor body, starting from a surface of the semiconductor body,', 'producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of a side wall of the at least one trench, and filling the at least one trench with a semiconductor material of the semiconductor body,, 'fabricating a porous semiconductor body region, the fabricating including,'}providing the dopant at the surface of the semiconductor body,heating the semiconductor body with the porous semiconductor body region produced therein, wherein the dopant diffuses through the porous semiconductor body region into the semiconductor body.2. The method according to claim 1 , wherein the porous semiconductor body region is produced such that the porous semiconductor body region extends from the surface of the semiconductor body into the semiconductor body.3. The method according to claim 1 , wherein the dopant is provided as a solid layer at the surface of the semiconductor body.4. The method according to claim 1 , wherein the dopant is provided in gaseous form at the surface of the semiconductor body.5. The method according to claim 1 , wherein the dopant is implanted into the porous semiconductor body region.6. The method according to claim 1 , wherein the dopant provided is oxygen.7. The method according to claim 1 , in which the dopant diffuses through the porous semiconductor body ...

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Номер записи: 106
23-01-2014 дата публикации

CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

Номер: US20140021610A1
Автор: Breymesser Alexander, Brockmeier Andre, KNABL Michael, MEYER Ursula, Santos Rodriguez Francisco Javier, von Koblinski Carsten
Принадлежит: INFINEON TECHNOLOGIES AG

A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region. 1. A chip package , comprising:a first encapsulation structure;a first passivation layer formed over the first encapsulation structure and a first electrically conductive layer formed over the first passivation layer;at least one chip arranged over the first electrically conductive layer and the first passivation layer wherein at least one chip contact pad contacts the first electrically conductive layer;at least one cavity formed in the first encapsulation structure, wherein the at least one cavity exposes a portion of the first passivation layer covering the at least one chip contact pad;a second encapsulation structure disposed over the first encapsulation structure and covering the at least one cavity, wherein a chamber region over the at least one chip contact pad is defined by the at least one cavity and the second encapsulation structure;wherein the second encapsulation structure comprises an inlet and outlet connected to the chamber region, wherein the ...

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Номер записи: 107
01-01-2015 дата публикации

Semiconductor Device and Method for Producing the Same

Номер: US20150001719A1
Автор: Müller Matthias, Santos Rodriguez Francisco Javier, Schlögl Daniel, Schmidt Gerhard
Принадлежит:

A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided. 1. A power semiconductor device , comprising:a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone;a metallization layer on a front surface of the semiconductor body and connected to the active zone;a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer; anda second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material,wherein the first barrier layer and the second barrier layer partially overlap and form an overlap zone, the overlap zone extending over an entire circumference of the active zone.2. The power semiconductor device of claim 1 , wherein the overlap zone has a width of about 0.5 μm to about 100 μm.3. The power semiconductor device of claim 1 , wherein the second barrier layer comprises at least one of amorphous silicon claim 1 , semi-isolating poly-silicon claim 1 , diamond-like carbon claim 1 , and ...

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Номер записи: 108
09-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20200013859A1
Автор: Breymesser Alexander, Goller Bernhand, Kern Ronny, Piccin Matteo, Rupp Roland, Santos Rodriguez Francisco Javier, Schaeffer Carsten
Принадлежит:

According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions. 1. A method of manufacturing a semiconductor device , comprising:providing a silicon carbide substrate with a plurality of device regions;providing a front side metallization at a front side of the silicon carbide substrate; andproviding an auxiliary structure at a backside of the silicon carbide substrate, wherein the auxiliary structure comprises a plurality of laterally separated metal portions, and wherein each metal portion is in contact with one device region of the plurality of device regions.2. The method according to claim 1 , wherein the silicon carbide substrate comprises a grid-shaped idle region that laterally separates the plurality of device regions.3. The method according to claim 1 , wherein providing the auxiliary structure comprises:structurally connecting a top surface of the auxiliary structure with a backside surface of the silicon carbide substrate.4. The method according to claim 1 , whereinthe auxiliary structure comprises a metal disc with a grid-shaped trench, and wherein the grid-shaped trench extends from a top surface of the auxiliary structure into the metal disc and laterally separates metal portions of the plurality of laterally separated metal portions from each other.5. The method according to claim 1 , wherein providing the auxiliary structure comprises:providing an auxiliary base with laterally separated trenches extending from a top surface of the auxiliary structure into the auxiliary base, and forming metal ...

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Номер записи: 109
24-01-2019 дата публикации

Method of Manufacturing a Plurality of Glass Members, a Method of Manufacturing an Optical Member, and Array of Glass Members in a Glass Substrate

Номер: US20190023600A1
Автор: Breymesser Alexander, Brockmeier Andre, Santos Rodriguez Francisco Javier, von Koblinski Carsten, Zorn Peter
Принадлежит:

An array of glass members is arranged in a glass substrate includes a plurality of depressions formed in a first main surface of the glass substrate, and a plurality of openings formed in a second main surface of the glass substrate. 1. An array of glass members arranged in a glass substrate , comprising:a plurality of depressions formed in a first main surface of the glass substrate; anda plurality of openings formed in a second main surface of the glass substrate.2. The array of glass members according to claim 1 , wherein the glass members are optical components claim 1 , a surface portion of the glass substrate defining the depression implementing an active surface of an optical component.3. The array of glass members according to claim 2 , wherein each of the depressions extend towards the second main surface and are disposed between thicker sections of the glass substrate.4. The array of glass members according to claim 2 , wherein each of the depressions extend away from a planar outer surface portion of the first main surface.5. The array of glass members according to claim 4 , wherein at least one of the depressions has a trapezoid shape.6. The array of glass members according to claim 4 , wherein at least one of the depressions has a semi-circle shape.7. The array of glass members according to claim 3 , wherein the openings extend towards the first main surface and are disposed within the thicker sections of the glass substrate.8. The array of glass members according to claim 7 , wherein each one of the thicker sections comprises two of the openings.9. The array of glass members according to claim 3 , wherein each one of the openings is configured as a kerf that defines a perimeter of each optical component.10. The array of glass members according to claim 9 , wherein each one of the kerfs have an enclosed shape.11. A glass substrate claim 9 , comprising:a first main surface;a second main surface opposite from the first main surface;a plurality of ...

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Номер записи: 110
29-01-2015 дата публикации

Semiconductor Device, a Semiconductor Wafer Structure, and a Method for Forming a Semiconductor Wafer Structure

Номер: US20150028456A1
Автор: Francisco Javier Santos Rodriguez, Holger Huesken, Wolfgang Wagner
Принадлежит: INFINEON TECHNOLOGIES AG

Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

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Номер записи: 111
02-02-2017 дата публикации

Method of Manufacturing a Plurality of Glass Members, a Method of Manufacturing an Optical Member, and Array of Glass Members in a Glass Substrate

Номер: US20170029311A1
Автор: Breymesser Alexander, Brockmeier Andre, Santos Rodriguez Francisco Javier, von Koblinski Carsten, Zorn Peter
Принадлежит:

A method of manufacturing a plurality of glass members comprises bringing a first main surface of a glass substrate in contact with a first working surface of a first mold substrate, the first working surface being provided with a plurality of first protruding portions, and bringing a second main surface of the glass substrate in contact with a second working surface of a second mold substrate, the second working surface being provided with a plurality of second protruding portions. The method further comprises controlling a temperature of the glass substrate to a temperature above a glass-transition temperature to form the plurality of glass members, removing the first and the second mold substrates from the glass substrate, and separating adjacent ones of the plurality of glass members. 1. A method of manufacturing a plurality of glass members , the method comprising:bringing a first main surface of a glass substrate in contact with a first working surface of a first mold substrate, the first working surface being provided with a plurality of first protruding portions;bringing a second main surface of the glass substrate in contact with a second working surface of a second mold substrate, the second working surface being provided with a plurality of second protruding portions;controlling a temperature of the glass substrate to a temperature above a glass-transition temperature to form the plurality of glass members;removing the first and the second mold substrates from the glass substrate; andseparating adjacent ones of the plurality of glass members.2. The method according to claim 1 , further comprising pressing the first and the second mold substrates together claim 1 , while the temperature of the glass substrate is controlled to the temperature above the glass-transition temperature.3. The method according to claim 1 , wherein the temperature of the glass substrate is controlled to a temperature above a Littleton point of the glass substrate.4. The method ...

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Номер записи: 112
01-05-2014 дата публикации

Semiconductor Devices and Methods for Manufacturing Semiconductor Devices

Номер: US20140117530A1
Автор: Breymesser Alexander, Brockmeier Andre, Dielacher Franz, Santos Rodriguez Francisco Javier
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane. 1. A device , comprising:a semiconductor material comprising a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface;a first electrical contact element arranged on the first main surface of the semiconductor material; anda glass material comprising a second main surface, wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.2. The device of claim 1 , wherein the glass material completely covers the side surface of the semiconductor material.3. The device of claim 1 , wherein the glass material contacts the opposite surface of the semiconductor material.4. The device of claim 1 , wherein the opposite surface of the semiconductor material is exposed from the glass material.5. The device of claim 1 , further comprising an active electronic component disposed in the semiconductor material.6. The device of claim 1 , further comprising a passive electronic component arranged over the second main surface of the glass material.7. The device of claim 1 , wherein the semiconductor material comprises a functional area operating in a radio frequency range.8. The device of claim 1 ...

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Номер записи: 113
18-02-2021 дата публикации

Method of Processing a Power Semiconductor Device

Номер: US20210050436A1
Автор: Beninger-Bina Markus, Dainese Matteo, Jaeger Christian, Laven Johannes Georg, Philippou Alexander, Santos Rodriguez Francisco Javier, Vellei Antonio
Принадлежит:

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches. 1. A method of processing a power semiconductor device , the method comprising:providing a semiconductor body with a drift region of a first conductivity type;forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction;providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction;forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type;removing the mask arrangement; andextending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed ...

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Номер записи: 114
17-03-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING FRAME STRUCTURES LATERALLY SURROUNDING BACKSIDE METAL STRUCTURES

Номер: US20220085174A1
Автор: Brockmeier Andre, Denifl Guenter, Kern Ronny, KNABL Michael, Piccin Matteo, Santos Rodriguez Francisco Javier
Принадлежит:

A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures. 1. A method of manufacturing a semiconductor device , the method comprising:providing a silicon carbide substrate that comprises a plurality of device regions and a grid-shaped kerf region laterally separating the device regions;forming a mold structure on a backside surface of the grid-shaped kerf region;forming backside metal structures on a backside surface of the device regions; andseparating the device regions,wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.2. The method of claim 1 , further comprising:prior to forming the mold structure, providing an auxiliary structure that comprises stencil sections,wherein the stencil sections are provided on the backside surface of the device regions and each stencil section is assigned to one device region,wherein the mold structure fills a space between the stencil sections.3. The method of claim 2 , further comprising:after forming the mold structure, removing the auxiliary structure.4. The method of claim 3 , further comprising:after removing the auxiliary structure, forming at least a portion of the backside metal structures in spaces left by removing the stencil sections.5. The method of claim 4 , further comprising:prior to providing the auxiliary structure, forming a metal seed layer on the backside surface of the device regions,wherein forming the backside metal structures comprises electrochemical deposition of a main metal portion on exposed sections of the ...

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Номер записи: 115
08-03-2018 дата публикации

Semiconductor Devices and Method for Forming Semiconductor Devices

Номер: US20180068975A1
Автор: Breymesser Alexander, Brockmeier Andre, Kern Ronny, Rupp Roland, Santos Rodriguez Francisco Javier, von Koblinski Carsten
Принадлежит:

A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure. 1. A method for forming semiconductor devices , the method comprising:attaching a glass structure to a wide band-gap semiconductor wafer comprising a plurality of semiconductor devices; andforming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.2. The method of claim 1 , wherein attaching the glass structure to the wide band-gap semiconductor wafer comprises heating the glass structure to a glass-transition temperature of the glass structure and exerting pressure on at least a part of the glass structure.3. The method of claim 1 , wherein attaching the glass structure to the wide band-gap semiconductor wafer comprises anodic bonding of the glass structure to the wide band-gap semiconductor wafer.4. The method of claim 1 , further comprising forming at least one trench structure extending into the wide band-gap semiconductor wafer between neighboring semiconductor devices of the plurality of semiconductor devices.5. The method of claim 4 , wherein the plurality of semiconductor devices each comprise a semiconductor substrate and a glass sub-structure claim 4 , the method further comprising cutting the wide band-gap semiconductor wafer along the at least one trench structure to separate the plurality of semiconductor devices claim 4 , wherein the glass sub-structure is in contact with a vertical surface of ...

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Номер записи: 116
05-06-2014 дата публикации

Semiconductor Device Including Trenches and Method of Manufacturing a Semiconductor Device

Номер: US20140151789A1
Автор: Cotorogea Maria, Felsl Hans Peter, Gawlina Yvonne, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim, Seibert Georg, Stegner Andre Rainer, Wagner Wolfgang
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench. 1. A semiconductor device , comprising:a first transistor cell including a first gate electrode in a first trench;a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected;a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches; anda dielectric in the third trench covering a bottom side and walls of the third trench,wherein a thickness of the dielectric lining a wall of the third trench at a vertical level coinciding with a gate dielectric in the first and second trenches is greater than a thickness of the gate dielectric in the first and second trenches.2. The semiconductor device of claim 1 , wherein the third trench is wider at the first side than the first and second trenches.3. The semiconductor device of claim 1 , wherein a depth of the first and second trenches equals d.4. The semiconductor device of claim 1 , wherein the third trench further includes a conductive material.5. The semiconductor device of claim 4 , wherein the conductive material is electrically floating.6. The semiconductor device of claim 4 , wherein the conductive material is electrically connected ...

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Номер записи: 117
27-02-2020 дата публикации

CARRIER, LAMINATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20200068709A1
Автор: Brockmeier Andre, HOECHBAUER Tobias Franz Wolfgang, Metzger-Brueckl Gerhard, Piccin Matteo, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier. 1. A carrier configured to be attached to a semiconductor substrate via a first surface , comprising:a continuous carbon structure defining the first surface of the carrier, wherein the continuous carbon structure is made of carbon; anda reinforcing material constituting at least 2 vol-% of the carrier.2. The carrier of claim 1 , wherein the reinforcing material is embedded in the continuous carbon structure.3. The carrier of claim 1 , wherein the reinforcing material includes at least one of carbon nanotubes claim 1 , graphene flakes claim 1 , polycrystalline silicon claim 1 , diamond claim 1 , silicon nitride balls claim 1 , or molybdenum balls.4. The carrier of claim 1 , wherein the continuous carbon structure comprises a carbon layer defining the first surface of the carrier claim 1 , the reinforcing material embedded in a part of the continuous carbon structure adjoining the carbon layer.5. The carrier of claim 1 , wherein the continuous carbon structure comprises:a carbon layer defining the first surface of the carrier, andtrenches extending into the carbon layer from a second surface of the carrier opposite to the first surface, the reinforcing material filling at least part of the trenches.6. The carrier of claim 5 , wherein the reinforcing material comprises at least one of silicon carbide claim 5 , molybdenum claim 5 , a matrix comprising carbon nanotubes claim 5 , or a matrix comprising graphene flakes.7. The carrier of claim 1 , wherein the continuous carbon structure is a carbon layer and the reinforcing material is at least one of a reinforcing layer or a stack of reinforcing layers adjoining the continuous carbon structure.8. The carrier of claim 1 , wherein the reinforcing material is a metal layer.9. The carrier of ...

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Номер записи: 118
17-03-2016 дата публикации

SEMICONDUCTOR DEVICE ARRANGEMENT AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE ARRANGEMENT

Номер: US20160079183A1
Автор: Santos Rodriguez Francisco Javier
Принадлежит:

A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side. 1. A semiconductor device arrangement comprising:a semiconductor substrate comprising a semiconductor substrate front side and a semiconductor substrate back side, wherein the semiconductor substrate comprises at least one electrical element formed at the semiconductor substrate front side; anda plurality of porous semiconductor regions formed at the semiconductor substrate back side.2. The semiconductor device arrangement according to claim 1 , wherein at least part of the semiconductor substrate has a thickness which lies between 10 μm and 220 μm.3. The semiconductor device arrangement according to claim 1 , wherein the plurality of porous semiconductor regions have a porosity which lies between 5% and 95%.4. The semiconductor device arrangement according to claim 1 , wherein the semiconductor substrate comprises a plurality of chips claim 1 , each chip comprising at least one electrical element at the semiconductor substrate front side claim 1 , and wherein the plurality of porous semiconductor regions are formed in kerf regions between the plurality of chips.5. The semiconductor device arrangement according to claim 1 , wherein the semiconductor substrate comprises at least one chip comprising the at least one electrical element formed at a chip front side and at least one porous semiconductor region of the plurality of porous semiconductor regions formed at a chip back side.6. The semiconductor device arrangement according to claim 1 , further comprising a back side metallization layer formed over the semiconductor substrate back side claim 1 ...

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Номер записи: 119
24-03-2016 дата публикации

WAFER ARRANGEMENT AND METHOD FOR PROCESSING A WAFER

Номер: US20160086838A1
Автор: Lackner Gerald, Santos Rodriguez Francisco Javier, Unterweger Josef
Принадлежит:

A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably attachable to one another. 1. A wafer arrangement , comprising:a wafer; anda wafer support ring,wherein the wafer and the wafer support ring are configured to be releasably attachable to one another.2. The wafer arrangement of claim 1 , wherein the wafer and the wafer support ring are configured such that the wafer support ring can be detached from the wafer without causing damage to the wafer or the wafer support ring.3. The wafer arrangement of claim 1 , wherein the wafer and the wafer support ring are configured to be reversibly mechanically attachable to one another.4. The wafer arrangement of claim 1 , wherein the wafer and the wafer support ring are configured to be reversibly mechanically attachable to one another by bringing the wafer and the wafer support ring into mechanical contact with one another and then rotating at least one of the wafer and the wafer support ring relative to one another about an axis that is perpendicular to a main processing surface of the wafer.5. The wafer arrangement of claim 1 , wherein the wafer support ring comprises a first material and the wafer comprises a second material claim 1 , wherein the first material and the second material have at least substantially the same coefficient of thermal expansion.6. The wafer arrangement of claim 1 , wherein the wafer support ring comprises at least one material selected from a group of materials claim 1 , the group consisting of: alkaline free glass claim 1 , borosilicate glass claim 1 , molybdenum claim 1 , silicon claim 1 , or a combination of two or more of the aforementioned materials.7. The wafer arrangement of claim 1 , wherein the wafer and the wafer support ring comprise the same material.8. The wafer arrangement of claim 1 , wherein the wafer support ring has a thickness in the range from about ...

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Номер записи: 120
24-03-2016 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Having a Glass Piece and a Single-Crystalline Semiconductor Portion

Номер: US20160086854A1
Автор: Alexander Breymesser, Andre Brockmeier, Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Gerhard Schmidt, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with the edge surface of the single-crystalline semiconductor portion.

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Номер записи: 121
29-03-2018 дата публикации

METHOD FOR PROCESSING A MONOCRYSTALLINE SUBSTRATE AND MICROMECHANICAL STRUCTURE

Номер: US20180086630A1
Автор: Brockmeier Andre, Rupp Roland, Santos Rodriguez Francisco Javier
Принадлежит:

In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments. 1. A method of processing a monocrystalline substrate , the method comprising:severing the substrate along a main processing side into at least two monocrystalline substrate segments; andforming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.2. The method of claim 1 ,wherein the substrate furthermore comprises a desired separating layer, by means of which the two substrate segments are connected to one another;wherein the severing is carried out by canceling a cohesion of the desired separating layer.3. The method of claim 2 , further comprising:forming the desired separating layer by altering a chemical composition between the two substrate segments.4. The method of claim 3 ,wherein a resistance of the substrate between the two substrate segments vis-à-vis the severing is reduced by means of the altering.5. The method of claim 1 , further comprising:securing the at least one monocrystalline substrate segment on an additional substrate before the severing.6. The method of claim 5 ,wherein the securing comprises bonding the substrate and the additional substrate onto one another.7. The method of claim 5 ,wherein securing is carried out by means of an adhesion layer arranged between the at least one monocrystalline substrate segment and the additional substrate.8. The method of claim 5 ,wherein the additional substrate comprises an electrode; orwherein the electrode is formed by means of the at least one monocrystalline substrate segment.9. The method of claim 5 ,wherein forming the micromechanical structure comprises forming an additional ...

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Номер записи: 122
31-03-2016 дата публикации

Method of Forming a Transistor, Method of Patterning a Substrate, and Transistor

Номер: US20160093706A1
Автор: Brandt Philip Christoph, Santos Rodriguez Francisco Javier, Stegner Andre Rainer
Принадлежит:

A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode. 1. A method of forming a transistor including a gate electrode , the method comprising:forming a sacrificial layer over a semiconductor substrate;forming a patterning layer over the sacrificial layer;patterning the patterning layer to form patterned structures;forming spacers adjacent to sidewalls of the patterned structures;removing the patterned structures;etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate; andfilling a conductive material in the trenches in the semiconductor substrate to form gate electrodes.2. The method of claim 1 , wherein etching through the sacrificial layer and etching into the substrate also forms first through holes in the sacrificial layer claim 1 , and wherein the conductive material also fills the first through holes in the sacrificial layer.3. The method of claim 1 , further comprising forming a hard mask layer over the semiconductor substrate before forming the sacrificial layer claim 1 , the sacrificial layer being selectively etchable with respect to the hard mask layer.4. The method of claim 3 , further comprising etching through the hard mask layer using the patterned sacrificial layer as an etching mask to form second through holes in the hard mask layer and to form patterned hardmask ...

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Номер записи: 123
09-04-2015 дата публикации

METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE

Номер: US20150097294A1
Автор: Gasser Karl Heinz, Mayer Karl, Santos Rodriguez Francisco Javier, Woehlert Stefan, YEDURU Srinivasa Reddy
Принадлежит: INFINEON TECHNOLOGIES AG

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer. 1. A method for processing a wafer , the method comprising:removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer; andprinting material into the inner portion of the wafer using the structure as a printing mask.2. The method of claim 1 ,wherein the structure is a ring structure arranged to at least partially surround the inner portion of the wafer.3. The method of claim 2 ,wherein the ring structure is enclosing the inner portion of the wafer.4. The method of claim 2 ,wherein the ring structure is a circular ring structure.5. The method of claim 1 ,wherein the structure is a Taiko ring structure.6. The method of claim 1 ,wherein the structure has a height of less than or equal to 25 μm.7. The method of claim 1 ,wherein removing wafer material from the inner portion of the wafer comprises grinding wafer material from the inner portion of the wafer.8. The method of claim 1 ,wherein removing wafer material from the inner portion of the wafer comprises removing wafer material from the inner portion of a backside of the wafer.9. The method of ...

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Номер записи: 124
06-04-2017 дата публикации

Wafer Carrier, Method for Manufacturing the Same and Method for Carrying a Wafer

Номер: US20170098569A1
Автор: Kern Ronny, Rupp Roland, Santos Rodriguez Francisco Javier, Unterweger Josef
Принадлежит:

A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for carrying the wafer. The first and the second foil are connected to each other so as to form the chamber. The chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried. 1. A wafer carrier comprising:a first foil for carrying a wafer, the first foil having a perforation;a second foil; anda chamber between the first foil and the second foil, wherein the first foil and the second foil are connected to each other so as to form the chamber,wherein the chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried.2. The wafer carrier according to claim 1 , wherein the first and second foils are structurally supported.3. The wafer carrier according to claim 2 , wherein a grid or a porous plate is arranged between the first and second foils to structurally support the first and second foils.4. The wafer carrier according to claim 1 , wherein the first and second foils are connected to each other such that the vacuum within the chamber is maintained when the wafer is carried.5. The wafer carrier according to claim 1 , wherein the first and second foils are connected to each other using a common edge surrounding the chamber.6. The wafer carrier according to claim 5 , wherein the common edge comprises a welded portion connecting the first and second foils and encapsulating the chamber.7. The wafer carrier according to claim 5 , wherein the common edge comprises a zip connecting the first and second foils and encapsulating the chamber.8. The wafer carrier according to claim 1 , wherein the first foil and/or the second foil has a diameter which is larger than the ...

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Номер записи: 125
06-04-2017 дата публикации

SUBSTRATE CARRIER, A PROCESSING ARRANGEMENT AND A METHOD

Номер: US20170098570A1
Автор: Kern Ronny, Rupp Roland, Santos Rodriguez Francisco Javier, Unterweger Josef
Принадлежит:

According to various embodiments, a substrate carrier may include: a substrate-supporting region for supporting a substrate; wherein a first portion of the substrate-supporting region including a pore network of at least partially interconnected pores; wherein a second portion of the substrate-supporting region surrounds the first portion and includes a sealing member for providing a contact sealing; at least one evacuation port for creating a vacuum in the pore network, such that a substrate received over the substrate-supporting region is adhered by suction; and at least one valve configured to control a connection between the pore network and the at least one evacuation port, such that a vacuum can be maintained in the pore network; wherein the pore network includes a first pore characteristic in a first region and a second pore characteristic in a second region different from the first pore characteristic. 1. A substrate carrier comprising:a substrate-supporting region for supporting a substrate;wherein a first portion of the substrate-supporting region comprises a pore network of at least partially interconnected pores;wherein a second portion of the substrate-supporting region surrounds the first portion and comprises a sealing member for providing a contact sealing;at least one evacuation port for creating a vacuum in the pore network, such that a substrate received over the substrate-supporting region is adhered by suction; andat least one valve configured to control a connection between the pore network and the at least one evacuation port, such that a vacuum can be maintained in the pore network;wherein the pore network comprises a first pore characteristic in a first region and a second pore characteristic in a second region different from the first pore characteristic.2. The substrate carrier of claim 1 , further comprising:an evacuation line structure coupling the pore network with the at least one evacuation port and comprising at least one of: an ...

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Номер записи: 126
14-04-2016 дата публикации

Semiconductor Devices and Methods of Manufacturing Thereof

Номер: US20160104780A1
Автор: Hirler Franz, Mauder Anton, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim, Timme Hans-Joerg
Принадлежит:

In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer. 1. A method of forming a semiconductor device , the method comprising:forming a first porous semiconductor layer over a top surface of a substrate;forming a first epitaxial layer over the first porous semiconductor layer;forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer;thinning the substrate from a back surface to form a thinned substrate; anddicing the substrate to form singulated chips, wherein the thinning is stopped before reaching the first porous semiconductor layer.2. The method of claim 1 , wherein the substrate is a silicon wafer.3. The method of claim 1 , wherein forming the first porous semiconductor layer comprises:depositing an optional epitaxial layer; andelectrochemically etching at least a portion of the optional epitaxial layer.4. The method of claim 3 , wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping claim 3 , and a second layer having a second doping different from the first layer.5. The method of claim 1 , wherein forming the first porous semiconductor layer comprises:converting a top region of the substrate into the first porous semiconductor layer by etching.6. The method of claim 1 , further comprising forming sublayers within the first porous semiconductor layer by exposing the first porous semiconductor layer to a hydrogen anneal.7. The method of claim 1 , wherein forming a first epitaxial layer comprises exposing the first porous semiconductor layer to a hydrogen anneal.8. The method of claim 1 , wherein the substrate ...

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Номер записи: 127
04-05-2017 дата публикации

INSULATED GATE SEMICONDUCTOR DEVICE WITH SOFT SWITCHING BEHAVIOR

Номер: US20170125407A1
Автор: Niedernostheide Franz-Josef, Pfirsch Frank Dieter, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim, VOSS STEPHAN, Wagner Wolfgang
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method for producing thereof is provided. The semiconductor device includes a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; and an electrically conductive gate layer comprising the gate electrodes or electrically connected to the gate electrodes of the plurality of device cells. The gate layer is electrically connected to a gate conductor and includes at least one of an increased resistance region and a decreased resistance region. 1. A semiconductor device , comprising:a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; andan electrically conductive gate layer electrically connected to the gate electrodes of the plurality of device cells,wherein the gate layer is electrically connected to a gate conductor and comprises at least one of an increased resistance region and a decreased resistance region.2. The semiconductor device of claim 1 , wherein the increased resistance region comprises a recess in the gate layer.3. The semiconductor device of claim 2 , wherein the recess is filled with a recess material different from a material of the gate layer.4. The semiconductor device of claim 3 , wherein the recess material is an electrically insulating material.5. The semiconductor device of claim 2 , wherein the recess extends completely through the gate layer.6. The semiconductor device of claim 1 , wherein the gate layer comprises a polycrystalline semiconductor material with a basic doping concentration and a doping concentration higher than the basic doping concentration in the decreased resistance region.7. The semiconductor device of claim 6 , wherein the decreased resistance region comprises one of phosphorous and selenium atoms.8. The ...

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Номер записи: 128
25-04-2019 дата публикации

Method for Producing IGBT with dV/dt Controllability

Номер: US20190123185A1
Автор: Bina Markus, Dainese Matteo, Jaeger Christian, Laven Johannes Georg, Philippou Alexander, Santos Rodriguez Francisco Javier, Vellei Antonio
Принадлежит:

A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches. 1. A method of processing a power semiconductor device , the method comprising:providing a semiconductor body with a drift region of a first conductivity type;forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction;providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction;subjecting the semiconductor body and the mask arrangement to a dopant material providing step, thereby forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type;removing the mask arrangement;subjecting the semiconductor body to a temperature annealing step, to extend the plurality of doping regions in parallel to the first lateral direction so as to overlap and to ...

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Номер записи: 129
25-04-2019 дата публикации

IGBT with dV/dt Controllability

Номер: US20190123186A1
Автор: Bina Markus, Dainese Matteo, Jaeger Christian, Laven Johannes Georg, LEENDERTZ Caspar, Philippou Alexander, Sandow Christian Philipp, Santos Rodriguez Francisco Javier, Vellei Antonio
Принадлежит:

A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region. 1. A power semiconductor device , comprising a first load terminal and a second load terminal , the power semiconductor device being configured to conduct a load current along a vertical direction between the first and second load terminals and comprising:an active cell region with a drift region of a first conductivity type;an edge termination region having a well region of a second conductivity type; [ at least one control trench having a control electrode;', 'at least one dummy trench having a dummy electrode electrically coupled to the control electrode;', 'at least one source trench having a source electrode electrically connected with the first load terminal;, 'the plurality of trenches comprising, at least one active mesa arranged between the at least one control trench and the at least one source trench;', 'at least one inactive mesa arranged adjacent to the at least one dummy trench;, 'the plurality of mesas comprising, 'an electrically floating barrier region of the second conductivity type, wherein at least both a bottom of the dummy trench and a bottom of the source ...

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Номер записи: 130
03-06-2021 дата публикации

Vertical Power Semiconductor Device, Semiconductor Wafer or Bare-Die Arrangement, Carrier, and Method of Manufacturing a Vertical Power Semiconductor Device

Номер: US20210167195A1
Автор: Brockmeier Andre, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 μm to 200 μm. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 μm to 5 μm. 1. A vertical power semiconductor device , comprising:a semiconductor body having a first main surface and a second main surface opposite to the first main surface, wherein a thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 μm to 200 μm;active device elements in the semiconductor body at the first main surface;edge termination elements at least partly surrounding the active device elements at the first main surface; anda diffusion region extending into the semiconductor body from the second main surface, wherein a doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 μm to 5 μm.2. The vertical power semiconductor device of claim 1 , wherein the semiconductor body is a magnetic Czochralski (MCZ) or a float zone (FZ) silicon semiconductor body.3. The vertical power semiconductor device of claim 1 , wherein a Gaussian function or complementary error function fits to the doping concentration profile of the diffusion region.4. The vertical ...

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Номер записи: 131
17-05-2018 дата публикации

Semiconductor Wafers and Semiconductor Devices with Barrier Layer and Methods of Manufacturing

Номер: US20180138353A1
Автор: Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface. 1. A method of manufacturing semiconductor wafers , the method comprising:slicing a semiconductor ingot to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface;forming a passivation layer directly on at least one of the front side surface and the rear side surface; andforming a barrier layer from at least one of silicon carbide, a ternary nitride, and a ternary carbide on the rear side surface.2. The method of claim 1 , whereinthe barrier layer is formed directly on the rear side surface.3. The method of claim 1 , whereinthe passivation layer is formed directly on at least the rear side surface before forming the barrier layer.4. The method of claim 1 , further comprising:forming a supplementary layer from polycrystalline silicon directly on the rear side surface before forming the barrier layer.5. The method of claim 1 , further comprising:forming a supplementary layer from polycrystalline silicon on the rear side surface before forming the barrier layer.6. The method of claim 1 , whereinthe passivation layer is formed by oxidation of the semiconductor slice.7. The method of claim 1 , wherein a portion of the passivation layer on the front side surface is formed from at least one of silicon carbide claim 1 , ternary nitride and ternary carbide.8. The method of claim 1 , whereinthe semiconductor slice is sliced from a cylindrical semiconductor ingot.9. The method of claim 1 , whereinthe semiconductor slice is sliced from a semiconductor ingot with a polygonal cross-section orthogonal to a longitudinal axis.10. A ...

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Номер записи: 132
10-06-2021 дата публикации

Method for Splitting Semiconductor Wafers

Номер: US20210175123A1
Автор: BEYER Christian, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim, Swoboda Marko
Принадлежит:

A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures. 1. A method of splitting a semiconductor wafer , the method comprising:forming one or more epitaxial layers on the semiconductor wafer;forming a plurality of device structures in the one or more epitaxial layers;forming a metallization layer and/or a passivation layer over the plurality of device structures;attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer;forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; andapplying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device ...

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Номер записи: 133
15-09-2022 дата публикации

METHOD FOR FORMING SEMICONDUCTOR DEVICES USING A GLASS STRUCTURE ATTACHED TO A WIDE BAND-GAP SEMICONDUCTOR WAFER

Номер: US20220293558A1
Автор: Breymesser Alexander, Brockmeier Andre, Kern Ronny, Rupp Roland, Santos Rodriguez Francisco Javier, von Koblinski Carsten
Принадлежит:

A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described. 1. A method for forming semiconductor devices , the method comprising:attaching a glass structure to a wide band-gap semiconductor wafer comprising a plurality of semiconductor devices;forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; andreducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure.2. The method of claim 1 , further comprising forming at least one trench structure extending into the wide band-gap semiconductor wafer between neighboring semiconductor devices of the plurality of semiconductor devices.3. The method of claim 2 , wherein the plurality of semiconductor devices each comprise a semiconductor substrate and a glass sub-structure claim 2 , the method further comprising:cutting the wide band-gap semiconductor wafer along the at least one trench structure to separate the plurality of semiconductor devices, wherein each of the glass sub-structures is in contact with a vertical surface of an edge of the semiconductor substrate after the cutting of the wide band-gap semiconductor wafer.4. The method of claim 1 , further comprising forming the least one opening of the glass structure after attaching the ...

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Номер записи: 134
11-06-2015 дата публикации

ELECTRONIC DEVICE, A METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE, AND A METHOD FOR OPERATING AN ELECTRONIC DEVICE

Номер: US20150163915A1
Автор: Bieselt Steffen, Hirler Franz, Kautzsch Thoralf, Mauder Anton, Santos Rodriguez Francisco Javier, Scholz Wolfgang, Schulze Hans-Joachim, Scire Alessia
Принадлежит: INFINEON TECHNOLOGIES DRESDEN GMBH

According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material. 1. An electronic device , comprising:a carrier comprising at least a first region and a second region being laterally adjacent to each other;an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure;a first electronic component arranged in the first region of the carrier over the electrically insulating structure;a second electronic component arranged in the second region of the carrier;wherein the electrically insulating structure comprises one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.2. The electronic device of claim 1 , further comprising:at least one first trench structure formed in the carrier extending from a surface of the carrier, the at least one first trench structure electrically separating the first electronic component from the second electronic component; the at least one first trench structure comprising at least one sidewall being covered with an electrically insulating material.3. The electronic device of claim 2 ,wherein the trench structure is at least partially filled with an electrically conductive material.4. The ...

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Номер записи: 135
08-06-2017 дата публикации

Forming a Contact Layer on a Semiconductor Body

Номер: US20170162390A1
Автор: Konrath Jens Peter, Rupp Roland, Santos Rodriguez Francisco Javier, Schaeffer Carsten, Schulze Hans-Joachim, Schustereder Werner, Wellenzohn Guenther
Принадлежит:

Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C. 1. A method , comprising:forming a metal layer on a first surface of a semiconductor body:irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; andannealing the semiconductor body, wherein the annealing comprises heating at least the metal atom containing region to a temperature of less than 500° C.2. The method of claim 1 , wherein the temperature is higher than 350° C.3. The method of claim 1 , wherein a duration of the annealing is in a range between 30 seconds and 30 minutes.4. The method of claim 1 , wherein the semiconductor body comprises a doped region in a region adjoining the first surface.5. The method of claim 4 , wherein a doping concentration of the doped region is in a range between 2E17 cmand 2E20 cm.6. The method of claim 1 , wherein the particles comprise noble gas ions.7. The method of claim 1 , wherein the particles comprise one of semiconductor and metal ions.8. The method of claim 1 , wherein the particles comprise dopant ions.9. The method of claim 8 , wherein the semiconductor body comprises SiC and the dopant ions are selected from the group consisting of: aluminum ions; and nitrogen atoms.10. The method of claim 1 , wherein irradiating the metal layer comprises irradiating the metal layer with different types of particles.11. The method of claim 1 , further comprising:removing the metal layer after the annealing.12. The method of claim 11 , further comprising:forming a further metal layer ...

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Номер записи: 136
21-05-2020 дата публикации

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE COMPRISING A PASTE LAYER AND SEMICONDUCTOR DEVICE

Номер: US20200161269A1
Автор: Craes Fabian, Eichinger Barbara, Mischitz Martin, Otto Frederik, Santos Rodriguez Francisco Javier, Thion Fabien
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions. 2. The method of claim 1 , wherein the paste comprises an electrically conductive material.3. The method of claim 2 , wherein the paste is a sinter paste.4. The method of claim 1 , where the electromagnetic radiation comprises microwaves or photonic curing.5. The method of claim 1 , where applying electromagnetic radiation includes using a laser or high energy flash lamp.6. The method of claim 1 , wherein precuring the paste comprises in addition applying heat in a range of 25° C. to 250° C.7. The method of claim 1 , wherein the semiconductor dies comprise a backside metallization layer and wherein the paste is applied to the backside metallization layer.8. The method of claim 1 , wherein the substrate comprises a reinforcing structure and wherein the method further comprises:removing the reinforcing structure prior to applying the paste.9. The method of claim 4 , wherein the structuring comprises removing the paste above the cutting regions after the precuring.10. The method of claim 9 , wherein the paste is removed by physical or chemical methods.11. The method of claim 1 , further comprising:masking the substrate above the cutting regions prior to applying the paste.12. The method of claim 11 , wherein the substrate is masked using photoresist.13. The method of claim 1 , wherein the structuring comprises arranging a photomask on the layer of the paste and removing the paste above the cutting regions.14. The method of claim 1 , wherein the carrier is a temporary carrier and wherein the method further comprises:removing the plurality of semiconductor dies from ...

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Номер записи: 137
18-09-2014 дата публикации

Metal Deposition on Substrates

Номер: US20140264779A1
Автор: KNABL Michael, Koffler Guenther, Santos Rodriguez Francisco Javier, Wang Kae-Horng
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate. 1. A method , comprising:providing a substrate;forming an isolation layer over the substrate, the isolation layer being substantially limited to a peripheral region of the substrate; andforming at least one first metal layer over a side of the substrate.2. The method of claim 1 , wherein the isolation layer is formed after forming the first metal layer.3. The method of claim 1 , wherein the first metal layer is formed after forming the isolation layer.4. The method of claim 1 , wherein forming the isolation layer comprises forming the isolation layer within the peripheral region and outside the peripheral region claim 1 , and removing the isolation layer from outside the peripheral region.5. The method of claim 1 , wherein forming the isolation layer comprises performing a photolithography.6. The method of claim 1 , wherein providing the substrate comprises providing a thinned semiconductor substrate with a ring thicker than the thinned substrate at the peripheral region.7. The method of claim 1 , further comprising forming at least one second metal layer after forming the first metal layer and after forming the isolation layer.8. The method of claim 7 , wherein the second metal layer comprises nickel.9. The method of claim 8 , wherein the nickel is in the form of at least one of pure nickel claim 8 , nickel alloy or nickel compound.10. The method of claim 1 , wherein the forming the first metal layer includes electroless plating the first metal layer.11. The method of claim 1 , wherein the peripheral region comprises at least one of a peripheral portion of the side of the substrate or at least a portion of an edge of the substrate.12. An apparatus claim 1 , comprising:an isolation forming device configured to form an isolation layer over a substrate such that the ...

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Номер записи: 138
21-06-2018 дата публикации

Forming a Metal Contact Layer on Silicon Carbide and Semiconductor Device with Metal Contact Structure

Номер: US20180174840A1
Автор: ESTEVE Romain, Joshi Ravi Keshav, Rupp Roland, Santos Rodriguez Francisco Javier, Unegg Gerald
Принадлежит:

A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body. 1. A method of manufacturing a semiconductor device , the method comprising:forming, on a process surface of a silicon carbide body, a starting layer from a material comprising a silicide-forming metal; andforming, from the starting layer and a portion of the silicon carbide body, isolated interface particles comprising a silicide kernel and a carbon cover, wherein a connection portion of the process surface between the isolated interface particles is exposed.2. The method of claim 1 , further comprising:forming a metal contact layer directly on the connection portion of the process surface, wherein the interface particles are embedded between the metal contact layer and the silicon carbide body.3. The method of claim 1 , wherein the starting layer comprises at least one opening exposing an uncoated portion of the process surface.4. The method of claim 1 , wherein the starting layer completely covers the process surface claim 1 , and wherein material claim 1 , configuration and thickness of the starting layer are selected to expose the connection portion during the formation of the interface particles.5. The method of claim 1 , wherein the silicide-forming metal is one of nickel claim 1 , tungsten claim 1 , vanadium claim 1 , titanium claim 1 , cobalt and iron.6. The method of claim 1 , wherein the starting layer comprises at least one of a metal claim 1 , a metal oxide and a metal-organic material.7. The method of claim 1 , wherein the starting layer is formed by a heat treatment of a solution comprising a solute containing the ...

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Номер записи: 139
21-06-2018 дата публикации

Method for manufacturing an electronic device and method for operating an electronic device

Номер: US20180175069A1
Автор: Alessia Scire, Anton Mauder, Francisco Javier Santos Rodriguez, Franz Hirler, Hans-Joachim Schulze, Steffen Bieselt, Thoralf Kautzsch, Wolfgang Scholz
Принадлежит: Infineon Technologies Dresden GmbH and Co KG

According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.

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Номер записи: 140
04-06-2020 дата публикации

Silicon Carbide Devices, Semiconductor Devices and Methods for Forming Silicon Carbide Devices and Semiconductor Devices

Номер: US20200176580A1
Автор: AICHINGER Thomas, Moder Iris, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim, Siemieniec Ralf, von Koblinski Carsten
Принадлежит:

A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell. 1. A silicon carbide device , comprising:a silicon carbide substrate comprising a body region and a source region of a transistor cell; anda titanium carbide gate electrode of the transistor cell.2. The silicon carbide device of claim 1 , wherein the titanium carbide gate electrode is located in a gate trench claim 1 , and wherein the gate trench extends from a surface of the silicon carbide substrate into the silicon carbide substrate.3. The silicon carbide device of claim 2 , further comprising a titanium carbide contact electrode located in the gate trench or in a contact trench claim 2 , wherein the titanium carbide contact electrode is electrically connected to the source region of the transistor cell.4. The silicon carbide device of claim 2 , wherein a width of the gate trench measured at the surface of the silicon carbide substrate is at most 1.5 μm.5. The silicon carbide device of claim 1 , wherein the transistor cell is a vertical transistor cell configured to conduct current between a front side of the silicon carbide substrate and a backside of the silicon carbide substrate.6. The silicon carbide device of claim 1 , wherein a gate insulation layer is located between the titanium carbide gate electrode and the silicon carbide substrate claim 1 , wherein the titanium carbide gate electrode comprises at least a layer of titanium carbide adjacent to the gate insulation layer claim 1 , and wherein the layer of titanium carbide has a thickness of at least 50 nm.7. The silicon carbide device of claim 1 , further comprising a plurality of stripe-shaped gate trenches claim 1 , wherein a titanium carbide gate electrode is located in each stripe-shaped gate trench of the plurality of stripe-shaped gate trenches.8. The silicon carbide device ...

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Номер записи: 141
30-07-2015 дата публикации

Semiconductor Device Including Undulated Profile of Net Doping in a Drift Zone

Номер: US20150214347A1
Автор: Falck Elmar, Haertl Andreas, Laven Johannes Georg, PFAFFENLEHNER Manfred, Santos Rodriguez Francisco Javier, Schloegl Daniel, Schulze Hans-Joachim, Stegner Andre
Принадлежит:

A semiconductor device includes a semiconductor body having opposite first and second sides. The semiconductor device further includes a drift zone in the semiconductor body between the second side and a pn junction. A profile of net doping of the drift zone along at least 50% of a vertical extension of the drift zone between the first and second sides is undulated and includes doping peak values between 1×10cmand 5×10cm. A device blocking voltage Vis defined by a breakdown voltage of the pn junction between the drift zone and a semiconductor region of opposite conductivity type that is electrically coupled to the first side of the semiconductor body. 1. A semiconductor device , comprising:a semiconductor body having opposite first and second sides; anda drift zone in the semiconductor body between the second side and a pn junction,{'sup': 13', '−3', '14', '−3, 'wherein a profile of net doping of the drift zone along at least 50% of a vertical extension of the drift zone between the first and second sides is undulated and includes multiple doping peak values between 1×10cmand 5×10cm,'}{'sub': 'br', 'wherein a device blocking voltage Vis defined by a breakdown voltage of a pn junction between the drift zone and a semiconductor region of opposite conductivity type that is electrically coupled to the first side of the semiconductor body.'}2. The semiconductor device of claim 1 , wherein the undulated profile of net doping includes hydrogen-related donors.3. The semiconductor device of claim 1 , wherein the undulated profile of net doping includes at least two minima claim 1 , and a doping concentration of the at least two minima decreases from the second side to the first side.4. The semiconductor device of claim 1 , wherein the undulated profile of net doping includes at least three minima claim 1 , and a doping concentration of the at least three minima decreases from the second side to the first side.5. The semiconductor device of claim 1 , wherein the undulated ...

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Номер записи: 142
18-06-2020 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device

Номер: US20200194558A1
Автор: Brockmeier Andre, Denifl Guenter, Kern Ronny, KNABL Michael, Piccin Matteo, Santos Rodriguez Francisco Javier
Принадлежит:

An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions. 1. A method of manufacturing a semiconductor device , the method comprising:providing an auxiliary carrier and a silicon carbide substrate, the silicon carbide substrate comprising an idle layer and a device layer, the device layer being located between the idle layer and a main surface of the silicon carbide substrate at a front side of the silicon carbide substrate, the device layer comprising a plurality of laterally separated device regions, each device region extending from the main surface to the idle layer, the auxiliary carrier being structurally connected with the silicon carbide substrate at the front side;removing the idle layer;forming a mold structure filling a grid-shaped groove that laterally separates the device regions; and separating the device regions,wherein parts of the mold structure form frame structures laterally surrounding the device regions.2. The method of claim 1 , wherein the grid-shaped groove is formed prior to removing the idle layer.3. The method of claim 1 , wherein the grid-shaped groove is formed after removing the idle layer.4. The method of claim 1 , further comprising:prior to molding, redistributing the device regions such that at least one of the device regions is replaced with a supplementary device ...

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Номер записи: 143
20-07-2017 дата публикации

METHOD OF FORMING A SEMICONDUCTOR DEVICE

Номер: US20170207124A1
Автор: Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AG

Methods of forming a semiconductor device are provided. A method includes introducing impurities into a part of a semiconductor substrate at a first surface of the semiconductor substrate by ion implantation, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate. The method further includes forming a semiconductor layer on the first surface of the semiconductor substrate. The method further includes irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate local damage of a crystal lattice of the semiconductor substrate. The method further includes separating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, where the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical stress. 1. A method of forming a semiconductor device , the method comprising:forming a semiconductor layer on a first surface of a semiconductor substrate, wherein impurities are introduced into a first sub-layer adjoining the semiconductor substrate at the first surface of the semiconductor substrate, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate;irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate a local damage of a crystal lattice of the semiconductor substrate; andseparating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, wherein the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical stress.2. A method of forming a ...

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Номер записи: 144
25-06-2020 дата публикации

METHOD FOR PROCESSING A MONOCRYSTALLINE SUBSTRATE AND MICROMECHANICAL STRUCTURE

Номер: US20200198963A1
Автор: Brockmeier Andre, Rupp Roland, Santos Rodriguez Francisco Javier
Принадлежит:

In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments. 1. A micromechanical structure , comprising:a substrate comprising a cavity;a monocrystalline semiconductor layer comprising a first section and a second section;wherein the second section adjoins the cavity and is coupled to the substrate by means of the first section.2. The micromechanical structure of claim 1 , further comprising:a functional structure comprising a functional region, which is deflectable relative to the substrate as a reaction to a force acting thereon;wherein the second section comprises the functional region.3. The micromechanical structure of claim 1 , further comprising:an electrode arranged at the substrate; anda functional structure comprising a functional region, which is deflectable relative to the electrode as a reaction to a force acting thereon;wherein the electrode comprises the second section.4. The micromechanical structure of claim 1 , further comprising: silicon carbide;', 'gallium nitride;', 'a greater modulus of elasticity than the substrate; and', 'a greater mechanical hardness than the substrate., 'wherein the second section may include at least one of the following5. The micromechanical structure of claim 1 , further comprising:an additional semiconductor layer, which differs from the monocrystalline semiconductor layer in its modulus of elasticity and/or in its mechanical hardness;wherein the cavity is arranged between the monocrystalline semiconductor layer and the additional semiconductor layer.6. An electromechanical transducer claim 1 , comprising:a substrate;a microelectromechanical structure in double electrode configuration;wherein the microelectromechanical structure ...

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Номер записи: 145
16-10-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

Номер: US20140306327A1
Автор: Baumgartl Johannes, Lackner Gerald, Mauder Anton, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a device carrier and a semiconductor chip attached to the device carrier. Further, the semiconductor device includes a lid having a recess. The lid includes a semiconductor material and is attached to the device carrier such that the semiconductor chip is accommodated in the recess. 1. An apparatus , comprising:a device carrier;a semiconductor chip attached to the device carrier; anda lid having a recess, wherein the lid is attached to the device carrier, the semiconductor chip is accommodated in the recess and the lid comprises a semiconductor material.2. The apparatus of claim 1 , wherein the recess is formed in the semiconductor material.3. The apparatus of claim 1 , wherein the device carrier comprises a material which is selected of the group consisting of a semiconductor material claim 1 , a printed circuit board claim 1 , a leadframe claim 1 , and a metal bonded ceramics.4. The apparatus of claim 1 , wherein the device carrier comprises an electrically insulating layer.5. The apparatus of claim 4 , wherein the semiconductor chip is attached to the electrically insulating layer.6. The apparatus of claim 4 , wherein the insulating layer is buried in the device carrier.7. The apparatus of claim 1 , wherein the semiconductor chip is a power semiconductor chip.8. The apparatus of claim 1 , wherein the lid has at least one opening through which a chip electrode is electrically connected to an external contact terminal of the semiconductor device claim 1 , wherein the external contact terminal is located at an outer surface of the lid.9. The apparatus of claim 8 , wherein all external contact terminals of the semiconductor device are located at the outer surface of the lid.10. The apparatus of claim 1 , wherein an inner surface of the lid is supported by a first support structure which includes the semiconductor chip.11. The apparatus of claim 1 , wherein an inner surface of the lid is supported by a second support structure which is ...

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Номер записи: 146
06-11-2014 дата публикации

Semiconductor Device with an Electrode Buried in a Cavity

Номер: US20140327103A1
Автор: Ahrens Carsten, Baumgartl Johannes, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate. 1. A semiconductor device , comprising:an active device region formed in an epitaxial layer disposed on a semiconductor substrate; anda buried electrode disposed below the active device region in a cavity formed within the semiconductor substrate, the buried electrode comprising an electrically conductive material different than the material of the semiconductor substrate.2. The semiconductor device of claim 1 , wherein the buried electrode comprises a metal material.3. The semiconductor device of claim 2 , wherein the buried electrode comprises TiN or Tungsten.4. The semiconductor device of claim 1 , wherein the buried electrode comprises polysilicon.5. The semiconductor device of claim 1 , wherein the buried electrode comprises carbon.6. The semiconductor device of claim 1 , further comprising an electrically conductive contact which extends from the buried electrode to a surface of the semiconductor substrate.7. The semiconductor device of claim 6 , wherein the contact extends vertically from the buried electrode to the surface of the semiconductor substrate on which the epitaxial layer is8. The semiconductor device of claim 6 , wherein the contact extends vertically from the buried electrode to the opposite surface of the semiconductor substrate on which the epitaxial layer is disposed.9. The semiconductor device of claim 6 , wherein the contact extends laterally from the buried electrode to a side surface of the semiconductor substrate which is disposed between top and bottom surfaces of the semiconductor substrate.10. The semiconductor device of ...

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Номер записи: 147
26-08-2021 дата публикации

Methods of Re-using a Silicon Carbide Substrate

Номер: US20210265484A1
Автор: Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described. 1. A method , comprising:providing a layer of porous silicon carbide supported by a silicon carbide substrate;providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide;forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide; andseparating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide.2. The method of claim 1 , wherein a thickness of the layer of epitaxial silicon carbide is at least 20 μm or at most 30 μm.3. The method of claim 1 , wherein the layer of porous silicon carbide comprises an interconnected network of pores.4. The method of claim 1 , wherein the layer of porous silicon carbide comprises a first sublayer having a first pore density and a second sublayer having a second pore density claim 1 , wherein the first sublayer is arranged in between the second sublayer and the substrate claim 1 , and wherein the first pore density is larger than the second pore density.5. The method of claim 1 , wherein providing the layer of porous silicon carbide comprises using an epitaxial growth process.6. The method of claim 1 , wherein providing the layer of porous silicon carbide comprises using an electrochemical etching process.7. The method of claim 1 , wherein providing the layer of epitaxial silicon carbide comprises using an epitaxial growth process claim 1 , wherein the layer of epitaxial silicon carbide comprises a first sublayer and a second sublayer claim 1 , wherein the first sublayer is arranged in between the second sublayer and the ...

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Номер записи: 148
13-09-2018 дата публикации

WAFER ARRANGEMENT AND METHOD FOR PROCESSING A WAFER

Номер: US20180261487A1
Автор: Lackner Gerald, Santos Rodriguez Francisco Javier, Unterweger Josef
Принадлежит:

A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring. 1. A wafer arrangement , comprising:a wafer; anda wafer support ring,wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.2. The wafer arrangement of claim 1 , wherein the wafer and the wafer support ring are configured to be releasably coupled to one another by magnetic coupling claim 1 , electrostatic coupling claim 1 , adhesive coupling claim 1 , or mechanical coupling.3. The wafer arrangement of claim 2 , wherein the wafer arrangement comprises one wafer and one wafer support ring.4. The wafer arrangement of claim 3 , wherein the wafer and the wafer support ring have approximately the same diameter.5. The wafer arrangement of claim 3 , wherein the wafer support ring comprises a first material and the wafer comprises a second material claim 3 , wherein the first material and the second material have at least substantially the same coefficient of thermal expansion.6. The wafer arrangement of claim 3 , wherein the wafer support ring comprises at least one material selected from a group of materials claim 3 , the group consisting of: alkaline free glass claim 3 , borosilicate glass claim 3 , molybdenum claim 3 , silicon claim 3 , or a combination of two or more of the aforementioned materials.7. The wafer arrangement of claim 3 , wherein the wafer support ring is rigid and has a thickness in the range from about 100 μm to about 2000 μm claim 3 , thereby providing mechanical stability during processing of the wafer.8. The wafer arrangement of claim 3 , wherein the wafer ...

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Номер записи: 149
20-09-2018 дата публикации

Glass Piece and Methods of Manufacturing Glass Pieces and Semiconductor Devices with Glass Pieces

Номер: US20180265354A1
Автор: Breymesser Alexander, Brockmeier Andre, Santos Rodriguez Francisco Javier, von Koblinski Carsten
Принадлежит:

A semiconductor element is formed in a mesa portion of a semiconductor substrate. A cavity is formed in a working surface of the semiconductor substrate. The semiconductor substrate is brought in contact with a glass piece made of a glass material and having a protrusion. The glass piece and the semiconductor substrate are arranged such that the protrusion extends into the cavity. The glass piece is bonded to the semiconductor substrate. The glass piece is in-situ bonded to the semiconductor substrate by pressing the glass piece against the semiconductor substrate. During the pressing a temperature of the glass piece exceeds a glass transition temperature and the temperature and a force exerted on the glass piece are controlled to fluidify the glass material and after re-solidifying the protrusion completely fills the cavity. 1. A method of manufacturing a semiconductor device , the method comprising:forming a semiconductor element in a mesa portion of a semiconductor substrate;forming a cavity in a working surface of the semiconductor substrate;bringing the semiconductor substrate in contact with a glass piece made of a glass material and having a protrusion, wherein the glass piece and the semiconductor substrate are arranged such that the protrusion extends into the cavity; andbonding the glass piece to the semiconductor substrate, wherein the glass piece is in-situ bonded to the semiconductor substrate by pressing the glass piece against the semiconductor substrate, wherein during the pressing a temperature of the glass piece exceeds a glass transition temperature and the temperature and a force exerted on the glass piece are controlled to fluidify the glass material and after re-solidifying the protrusion completely fills the cavity.2. The method according to claim 1 , further comprising providing an adhesive material between the semiconductor substrate and the glass piece before bonding claim 1 , wherein the glass piece is adhesive bonded to the semiconductor ...

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Номер записи: 150
01-10-2015 дата публикации

Battery, Integrated Circuit and Method of Manufacturing a Battery

Номер: US20150280287A1
Автор: Breymesser Alexander, Goller Bernhard, Joshi Ravi Keshav, Karlovsky Kamil, Santos Rodriguez Francisco Javier, Zorn Peter
Принадлежит:

A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity. 1. A battery , comprising:a first substrate having a first main surface;a second substrate made of a conducting material or a semiconductor material;a carrier of an insulating material, having first and second main surfaces, the second substrate being attached to the carrier;an opening in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate, the second main surface of the carrier being attached to the first substrate, thereby forming a cavity; andan electrolyte disposed in the cavity.2. The battery according to claim 1 , wherein the battery is a lithium ion battery having an anode comprising a component made of silicon.3. The battery according to claim 2 , wherein the anode of the battery is formed at the first substrate claim 2 , and a cathode of the battery is formed at the second substrate.4. The battery according to claim 2 , wherein the anode of the battery is formed at the second substrate claim 2 , and a cathode of the battery is formed at the first substrate.5. The battery according to claim 1 , wherein the second substrate is embedded into the carrier.6. The battery according to claim 5 , wherein the second substrate includes a patterned structure.7. The battery according to claim 1 , further comprising a liquid electrolyte.8. An integrated circuit including a battery comprising:a first substrate ...

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Номер записи: 151
20-08-2020 дата публикации

Power Semiconductor Device and Method of Processing a Power Semiconductor Device

Номер: US20200266269A1
Автор: Francisco Javier Santos Rodriguez, Frank Dieter Pfirsch, Frank Umbach, Manfred Pfaffenlehner, Philip Christoph Brandt, Steffen Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.

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Номер записи: 152
10-09-2020 дата публикации

SEMICONDUCTOR DEVICE WITH A POROUS PORTION, WAFER COMPOSITE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20200286730A1
Автор: Goller Bernhard, HOECHBAUER Tobias Franz Wolfgang, Moder Iris, Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface. 1. A method of manufacturing a semiconductor device , comprising:providing a semiconductor substrate that comprises a base portion, an auxiliary layer on the base portion, and a surface layer on the auxiliary layer, wherein the surface layer is in contact with a first main surface of the semiconductor substrate, and wherein the auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer;converting at least a portion of the auxiliary layer and at least a portion of the surface layer into a porous structure; andforming, after the converting, an epitaxial layer on the first main surface.2. The method according to claim 1 , comprising:separating the epitaxial layer from the base portion along the porous structure.3. The method according to claim 1 , whereinthe epitaxial layer and the semiconductor substrate differ in at least one main constituent.4. The method according to claim 1 , whereina mean net dopant concentration in the auxiliary layer is at least 100 times a mean net dopant concentration in the surface layer.5. The method according to claim 1 , whereinthe surface layer and the auxiliary layer have a same conductivity type.6. The method according to claim 1 , whereinthe semiconductor substrate is a silicon carbide substrate.7. The method according to claim 1 , whereinthe first main surface is exposed during the forming ...

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Номер записи: 153
26-11-2015 дата публикации

METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20150340234A1
Автор: Haertl Andreas, Santos Rodriguez Francisco Javier, Schloegl Daniel, Schulze Hans-Joachim, Stegner Andre Rainer
Принадлежит: INFINEON TECHNOLOGIES AG

A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body. 1. A method for processing a semiconductor device , comprising:depositing a first metallization material over a semiconductor body;performing a heating process so as to form at least one region in the semiconductor body comprising a eutectic of the first metallization material and material of the semiconductor body; anddepositing a second metallization material over the semiconductor layer so as to contact the semiconductor layer via the at least one region in the semiconductor layer.2. The method of claim 1 , wherein performing a heating process so as to form at least one region in the semiconductor body comprises:performing the heating process so as to form at least one spike-shaped region in the semiconductor body comprising the eutectic of the first metallization material and material of the semiconductor body.3. The method of claim 1 , wherein performing a heating process so as to form at least one region in the semiconductor body comprises:performing the heating process so as to form a plurality of spike-shaped regions in the semiconductor body comprising the eutectic of the first metallization material and material of the semiconductor body.4. The method of claim 2 , wherein the at least one spike-shaped region extends to a depth of about 100 nm to about 1 μm claim 2 , measured from a surface of the semiconductor body.5. The method of claim 2 , wherein the at least one spike-shaped region has a first diameter proximate a surface of the ...

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Номер записи: 154
15-11-2018 дата публикации

Method for Thinning Substrates

Номер: US20180330981A1
Автор: Moder Iris, Muri Ingo, Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer. 1. A method , comprising:providing a substrate having a first side and a second side opposite the first side;forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; andthinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.2. The method of claim 1 , wherein implanting the chemical element into the first side of the substrate comprises:implanting at least one of carbon ions and nitrogen ions into the first side of the substrate.3. The method of claim 1 , wherein implanting the chemical element into the first side of the substrate comprises:exposing the first side of the substrate to an ion current including ions of the chemical element.4. The method of claim 1 , wherein the buried layer is formed in the substrate and covered by a first portion of the substrate claim 1 , wherein a thickness of the first portion of the substrate is in a range from about 50 nm to about 500 nm claim 1 , and wherein a thickness of the buried layer is in a range from about 10 nm to about 100 nm.5. The method of claim 4 , wherein the thickness of the first portion of the substrate is in a range from about 100 nm ...

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Номер записи: 155
07-11-2019 дата публикации

Slicing SiC Material by Wire Electrical Discharge Machining

Номер: US20190337069A1
Автор: Claudia Friza, Francisco Javier Santos Rodriguez, Karin Delalut, Markus Heinrici, Nirdesh Ojha, Roland Rupp
Принадлежит: INFINEON TECHNOLOGIES AG

A method of yielding a thinner product wafer from a thicker base SiC wafer cut from a SiC ingot includes: supporting the base SiC wafer with a support substrate: and while the base SiC wafer is supported by the support substrate, cutting through the base SiC wafer in a direction parallel to a first main surface of the base SiC wafer using a wire as part of a wire electrical discharge machining (WEDM) process, to separate the product wafer from the base SiC wafer, the product wafer being attached to the support substrate when cut from the base SiC wafer.

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Номер записи: 156
29-10-2020 дата публикации

Edge Shaping of Substrates

Номер: US20200343085A1
Автор: Ojha Nirdesh, Rupp Roland, Santos Rodriguez Francisco Javier
Принадлежит:

A method includes producing a bulk substrate and beveling an edge of the bulk substrate using an electrical discharge machining (EDM) process and/or an electrochemical discharge machining (ECDM) process. 1. A method , comprising:producing a thinner substrate from a thicker bulk substrate; andprocessing an edge of the thinner substrate using an electrical discharge machining (EDM) process and/or an electrochemical discharge machining (ECDM) process.2. The method of claim 1 , wherein the thicker bulk substrate has a beveled edge prior to producing the thinner substrate from the thicker bulk substrate claim 1 , and wherein processing the edge of the thinner substrate using the EDM process and/or ECDM process comprises:processing a part of the beveled edge of the thicker bulk substrate retained by the thinner substrate using the EDM process and/or ECDM process.3. The method of claim 2 , wherein processing the part of the beveled edge of the thicker bulk substrate retained by the thinner substrate using the EDM process comprises:covering the part of the beveled edge of the thicker bulk substrate retained by the thinner semiconductor substrate with a dielectric liquid;applying voltage pulses between a tool electrode and the part of the beveled edge of the thicker bulk substrate retained by the thinner substrate; andmoving the tool electrode and/or the thinner substrate in the dielectric liquid to maintain a plasma between the tool electrode and the thinner.4. The method of claim 3 , further comprising:tilting the tool electrode along one or more different axes during the EDM process to change an angle of the beveled edge of the thicker bulk substrate retained by the thinner substrate and/or to change the shape of the beveled edge of the thicker bulk substrate retained by the thinner substrate.5. The method of claim 3 , wherein the tool electrode is moved only in a vertical direction to maintain the plasma and so that an angle of the beveled edge of the thicker bulk ...

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Номер записи: 157
03-12-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER

Номер: US20200381256A1
Автор: Rupp Roland, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure. 1. A method of manufacturing a semiconductor device , the method comprising:forming a carbon structure on a handle substrate at a first surface of the handle substrate;attaching a first surface of a semiconductor substrate to the first surface of the handle substrate;processing the semiconductor substrate; andperforming a separation process to separate the handle substrate from the semiconductor substrate, wherein the separation process comprises modifying the carbon structure.2. The method of claim 1 , wherein the forming the carbon structure comprises:forming trenches in the handle substrate at the first surface of the handle substrate; andfilling the trenches at least partially with carbon.3. The method of claim 2 , wherein:a depth of the trenches ranges from 50 nanometers (nm) to 1000 nm; anda lateral distance between two adjacent trenches of the trenches ranges from 20 nm to 200 nm.4. The method of claim 1 , wherein the forming the carbon structure comprises at least one of:heating the handle substrate up to at least 900° Celsius in an inert atmosphere or vacuum;heating a surface part of the handle substrate by absorption of laser radiation; orcarbonizing a resist formed on the handle substrate.5. The method of claim 1 , wherein the forming the carbon structure comprises: each carbon layer of the plurality of carbon layers comprises a plurality of carbon regions laterally spaced from one another, and', 'a degree of coverage of the ...

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Номер записи: 158
10-12-2020 дата публикации

GENERATING A MEMS DEVICE WITH GLASS COVER AND MEMS DEVICE

Номер: US20200385264A1
Автор: Brockmeier Andre, Janski Rafael, KIRILLOV Boris, Oldsen Marten, ROESSLER Clemens, Santos Rodriguez Francisco Javier, Sgouridis Sokratis, Sorschag Kurt
Принадлежит: INFINEON TECHNOLOGIES AG

In a method of generating a microelectromechanical system, MEMS, device, a MEMS substrate including a movable element is provided. A glass cover member including a glass cover is formed by hot embossing. The glass cover member is bonded to the MEMS substrate so as to hermetically seal by the glass cover a cavity in which the movable element is arranged. 1. A method of generating a microelectromechanical system (MEMS) device , the method comprising:providing a MEMS substrate comprising a movable element;forming a first glass cover member comprising a glass cover by hot embossing; andbonding the first glass cover member to the MEMS substrate so as to hermetically seal by the glass cover a cavity in which the movable element is arranged.2. The method of claim 1 , wherein the first glass cover member is bonded to a first side of the MEMS substrate claim 1 , the method further comprising:bonding a second glass cover member to a second side of the MEMS substrate opposite the first side thereof.3. The method of claim 1 , wherein providing the MEMS substrate comprises providing a MEMS wafer comprising a plurality of movable elements claim 1 , wherein the first glass cover member comprises a plurality of glass covers and wherein the first glass cover member is bonded to the MEMS substrate so as to hermetically seal by each glass cover one of a plurality of cavities claim 1 , wherein one of the plurality of movable elements is arranged in each of the plurality of cavities.4. The method of claim 2 , wherein providing the MEMS substrate comprises providing a MEMS wafer comprising a plurality of movable elements claim 2 , wherein the first glass cover member comprises a plurality of first glass covers claim 2 , wherein the second glass cover member comprises a plurality of second glass covers claim 2 , wherein the first glass cover member and the second glass cover member are bonded to the MEMS substrate so as to hermetically seal by a respective one of the first and the second ...

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Номер записи: 159
24-12-2020 дата публикации

Method for Processing a Substrate Assembly and Wafer Composite Structure

Номер: US20200402832A1
Автор: Francisco Javier Santos Rodriguez, Peter Irsigler
Принадлежит: INFINEON TECHNOLOGIES AG

A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.

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Номер записи: 160
10-12-2020 дата публикации

Production of a MEMS component with a glass cover and MEMS component

Номер: DE102019208373A1
Автор: Andre Brockmeier, Boris KIRILLOV, Clemens Roessler, Francisco Javier Santos Rodriguez, Kurt Sorschag, Marten Oldsen, Rafael Janski, Sokratis Sgouridis
Принадлежит: INFINEON TECHNOLOGIES AG

Bei einem Verfahren zum Herstellen eines Mikroelektromechanisches-System-, MEMS-, Bauelements wird ein MEMS-Substrat mit einem beweglichen Element bereitgestellt. Ein Glasabdeckbauteil mit einer Glasabdeckung wird durch Heiß-Prägen gebildet. Das Glasabdeckbauteil ist an das MEMS-Substrat gebunden, um so durch die Glasabdeckung eine Kavität, in der das bewegliche Element angeordnet ist, hermetisch abzudichten. In a method for producing a microelectromechanical system, MEMS, component, a MEMS substrate with a movable element is provided. A glass cover component with a glass cover is formed by hot stamping. The glass cover component is bonded to the MEMS substrate in order to hermetically seal a cavity in which the movable element is arranged through the glass cover.

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Номер записи: 161