Rekeyable lock cylinder and rekeying method thereof

A rekeyable lock cylinder comprises a cylinder body, a plug, an adjusting block and a plurality of rack component assemblies. The plug disposed within the cylinder body has a trench and a plurality of rack component runners communicating with the trench. The adjusting block disposed at the trench has an arc sidewall, a plurality of leading slots corresponding to the rack component runners one by one and a position groove recessed from the arc sidewall. The position groove has a notch portion and a groove inner portion, wherein a depth of the groove inner portion is larger than a depth of the notch portion. Each of the rack component assemblies comprises a first rack component disposed at the rack component runner and a second rack component capable of engaging with the first rack component. Each of the first rack components has a rib portion located at the leading slot.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A BARRIER STRUCTURE

A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes. 1. A method of manufacturing a semiconductor device , the method comprising:forming a barrier structure over a substrate;forming a channel layer over the barrier structure;depositing an active layer over the channel layer;forming source/drain electrodes over the channel layer; andannealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.2. The method of claim 1 , wherein forming the barrier structure comprises:forming a first barrier layer over the substrate;forming a buffer layer over the first barrier layer; andforming a second barrier layer over the buffer layer.3. The method of claim 2 , wherein forming the barrier structure comprises forming at least one of the first barrier layer or the second barrier layer comprising at least one material selected from the group consisting of SiC claim 2 , SiCNand BN.4. The method of claim 2 , wherein forming the buffer layer comprises forming the buffer layer comprising the p-type dopant.5. The method of claim 4 , wherein forming the buffer layer comprises forming the buffer layer comprising at least one element selected from the group consisting of C claim 4 , Fe claim 4 , Mg and Zn.6. The method of claim 2 , wherein forming the first barrier layer comprises forming the first barrier layer over the substrate comprises a Si substrate claim 2 , forming the buffer layer comprises forming the buffer layer comprising GaN doped with C claim 2 , and forming the channel layer comprises forming ...

Electrical connector assembly and method of manufacturing the same

An electrical connector assembly comprises: a metallic housing having a receiving space extending along a longitudinal and two openings respectively formed on top and bottom surfaces thereof and communicated with the receiving space; a pair of flexible printed circuit boards (FPCs) received into the receiving space and arranged in a back-to-back manner. Each of the FPC defines a protuberant portion extending into the corresponding opening. And each of the protuberant portion has a plurality of contacts formed on one side thereof and communicated with an exterior. A pair of supporting pieces are received into the receiving space and attached to another side of the protuberant portion. And a spacer is received into the receiving space and sandwiched between the pair of flexible printed circuit boards and supporting pieces.

Equalizer with auto-calibration and self-test

In the present invention, a transmission line length estimation circuit with continuous feedback equalizer is provided. The transmission line length estimation circuit comprises a DC bias circuit and a peak detector circuit to generate a DC voltage according to a different cable length. An equalizer core circuit is for receiving the first signal and generating a second signal. A peak detector circuit is used for the first signal and the second signal. A transmission line length detector circuit is coupled to the peak detector circuit and used for generating a plurality of first parameters for phase shift and amplitude losses according to the different cable length. An internal pattern calibration circuit is multiplexed to the first signal and used for generating a plurality of second parameters for calibration of close loop. A feedback control circuit is connected to the equalizer core circuit and used for continuously fine tuning of the equalizer core circuit according to the first parameters ...

Semiconductor device, transistor having doped seed layer and method of manufacturing the same

A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.

High electron mobility transistor and method of forming the same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode. 1. A High Electron Mobility Transistor (HEMT) comprising:a first III-V compound layer having a first band gap;a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap;a crystalline interfacial layer over and in contact with the second III-V compound layer;a gate dielectric over the crystalline interfacial layer;a gate electrode over the gate dielectric; anda source region and a drain region over the second III-V compound layer and on opposite sides of the gate electrode.2. The HEMT of claim 1 , wherein the first III-V compound layer and the second III-V compound layer are configured so that a Two-Dimensional Electron Gas (2DEG) is formed in the first III-V compound layer and close to an interface between the first III-V compound layer and the second III-V compound layer.3. The HEMT of claim 1 , wherein the crystalline interfacial layer is a dielectric layer.4. The HEMT of claim 1 , wherein the crystalline interfacial layer is a semiconductor layer.5. The HEMT of claim 1 , wherein the gate electrode claim 1 , the gate dielectric claim 1 , and the crystalline interfacial layer are co-terminus claim 1 , with edges of the crystalline interfacial layer aligned to respective edges of the gate electrode and the gate dielectric.6. The HEMT of claim 1 , wherein the crystalline interfacial layer ...

Rekeyable lock cylinder

A rekeyable lock cylinder comprises a plurality of first rack components, a plurality of second rack components and a guide bar having a first surface engaged with the first rack components. The second rack components are movable via contacting against a first matched key which is inserted in a first direction. The guide bar has a second surface, a first side, a second side, and a tool-receiving portion recessed into the first side. The tool-receiving portion is parallel to the first direction, and the first rack components are actuated by the guide bar via acting force applied by the rekeying tool accommodated in the tool-receiving portion therefore enabling the first rack components to move in a transverse direction relative to the first direction and disengaging the first rack components from the second rack components.

High Electron Mobility Transistors

The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

High electron mobility transistors

The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method of fabricating a semiconductor device , comprising:providing a silicon substrate having opposite first and second sides, at least one of the first and second sides including a silicon (111) surface;forming a first high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate, the first high CTE layer having a CTE greater than a CTE of silicon;forming a buffer layer over the second side of the silicon substrate, the buffer layer having a CTE greater than the CTE of silicon;forming a second high CTE layer over the second side of the silicon substrate, the second high CTE layer having a CTE greater than the CTE of silicon;removing the second high CTE layer; andafter removing the second high CTE layer, forming a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer.2. The method of claim 1 , wherein:the forming the high CTE layer is carried out in a manner so that the first high CTE layer includes a material selected from the group consisting of: silicon nitride, doped glass, and silicon carbide; andthe forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.3. The method of claim 1 , wherein the ...

BOOTSTRAP CIRCUIT WITHOUT A REGULATOR OR A DIODE

A bootstrap circuit without a regulator and a diode includes a comparator, a first switch, and a capacitor. The comparator has a first terminal for receiving a reference voltage, a second terminal coupled to a bootstrap voltage output terminal of the bootstrap circuit, and a third terminal for outputting a switch control signal. The first switch has a first terminal for receiving an input voltage, a second terminal for receiving the switch control signal, and a third terminal coupled to the bootstrap voltage output terminal. The capacitor is coupled between a voltage switching terminal and the second terminal of the comparator. 1. A bootstrap circuit without a regulator or a diode , the bootstrap circuit comprising:a comparator having a first terminal for receiving a reference voltage, a second terminal coupled to a bootstrap voltage output terminal of the bootstrap circuit, and a third terminal for outputting a switch control signal;a first switch having a first terminal for receiving an input voltage, a second terminal for receiving the switch control signal, and a third terminal coupled to the bootstrap voltage output terminal; anda capacitor coupled between a voltage switching terminal and the second terminal and the comparator.2. The bootstrap circuit of claim 1 , further comprising:a first voltage dividing resistor coupled between the bootstrap voltage output terminal and the second terminal of the comparator; anda second voltage dividing resistor coupled between the second terminal of the comparator and a ground.3. The bootstrap circuit of claim 2 , further comprising:a second switch coupled between the bootstrap voltage output terminal and the first voltage dividing resistor, wherein a second terminal of the second switch is coupled to the third terminal of the comparator to receive the switch control signal.4. The bootstrap circuit of claim 1 , wherein the first switch is a P-type metal-oxide-semiconductor.5. The bootstrap circuit of claim 1 , wherein the ...

METHOD FOR FORMING SOI SUBSTRATE

A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Circular saw assembly

A plurality of circular saw blades 15 are mounted on a common hollow shaft 22 spaced apart by spacers 23. A blower 12 drives cooling medium e.g. air into the hollow shaft whence it passes centrifugally through slits 222 in the shaft and slots 233 formed in the spacers to pass across and cool the blades 15. The shaft is mounted in a bearing 11 and driven by belts 14 engaging pulley 13 all these items being cooled by medium passing through constriction 24. ...

High Electron Mobility Transistors

The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of Al z Ga (1-z) N, a resistance-reducing layer of Al x Ga (1-x) N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

Rekeyable lock cylinder, plug assembly of the same and method for rekeying the same

A rekeyable lock cylinder comprises a cylinder body and a plug assembly disposed within the cylinder body. The plug assembly comprises a plug body, a plurality of pin assemblies and a guide bar. The plug body has a longitudinal axis, a transverse axis perpendicular to the longitudinal axis and a tool-receiving hole. Each of the pin assemblies is movably disposed in the plug body and comprises a first rack component and a second rack component selectively engaging with the first rack component. The guide bar is coupled to the plug body and has a plurality of pin runners for engaging with the first rack components and a tool-receiving portion exposed by the tool-receiving hole. The guide bar is capable of moving along transverse axis-direction of the plug body to disengage the first rack components from the second rack components.

REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER

Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

Peak detector and detecting method thereof

The invention provides a peak detector having input signal triggering control and low frequency energy attenuation capability. The peak detector includes a charging unit and a discharging unit. By being triggered by a peak value detected in a received input signal by comparing voltage potential levels of the output signal of the peak detector and the received signal, the charging unit charges an electrical charge storage unit, for example, a capacitor, connected to the output terminal of the peak detector for a pre-determined charge duration in accordance with a charge pulse being in a logic high. After the pre-determined charge duration of charging operation, before being triggered by a next peak value of the received input signal, the discharging unit discharges the electrical charge storage unit for a pre-determined discharge duration in accordance with a discharge pulse being in a logic high or in accordance with a plurality of discharge pulses, which is determined by design desired ...

Lock escutcheon assembly

Semiconductor Structures With Improved Reliability

Semiconductor structures and methods are provided. An exemplary semiconductor structures according to the present disclosure includes a semiconductor substrate including a first region and a second region surrounding the first region, a III-V semiconductor layer disposed directly over the first region, a compound semiconductor device formed in and over the III-V semiconductor layer, a first plurality of conductive features disposed over and electrically coupled to a source contact of the compound semiconductor device, and a seal ring disposed directly over the second region and comprising a second plurality of conductive features, a top surface of a topmost conductive feature of the first plurality of conductive features is higher than a top surface of a topmost conductive feature of the second plurality of conductive features.

High electron mobility transistor and method of forming the same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

METHOD FOR ADJUSTING A LOCK ASSEMBLY TO FIT WITH DIFFERENT KEYS

A method for adjusting a lock assembly includes steps of providing a lock assembly, inserting a first key into the lock assembly, rotating a lock cylinder with the first key to an operating position, moving the lock cylinder relative to a housing in a first moving direction, moving the lock cylinder relative to the housing in a second moving direction, removing the first key from the lock cylinder, inserting a second key into the lock cylinder and rotating the lock cylinder with the second key. Accordingly, to adjust the lock assembly to fit with different keys is convenient and quick.

Source/drains in semiconductor devices and methods of forming thereof

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Method of embedding semiconductor element in carrier and embedded structure thereof

A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

REKEYABLE LOCK CYLINDER AND OPERATING METHOD THEREOF

A rekeyable lock cylinder comprises a cylinder body and a plug assembly disposed within the cylinder body. The plug assembly comprises a plug body, a plurality of assembled pins and a position block. The plug body has a longitudinal axis, a transverse axis vertical to the longitudinal axis, a keyhole and a first through hole. Each of the assembled pins is movably disposed in the plug body and comprises a first rack component and a second rack component selectively engaging with the first rack component. The position block disposed at the plug body has a plurality of pin runners used for disposing the first rack components, a second through hole corresponding to the first through hole and a tool-contacting surface located within the second through hole. The position block can move along the transverse axis-direction of the plug body to make each of the first rack components reengage with each of the second rack components.

ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE

Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. 1. A semiconductor arrangement , comprising:a substrate comprising a front side surface and a backside surface;one or more devices formed over the front side surface; andan isolation trench formed through the backside surface of the substrate, the isolation trench comprising a tapered portion and a non-tapered portion, the non-tapered portion having a non-tapered width that is less than a tapered width of the tapered portion.2. The semiconductor arrangement of claim 1 , the tapered portion formed between the backside surface of the substrate and the non-tapered portion.3. The semiconductor arrangement of claim 1 , the non-tapered portion formed between the front side surface of the substrate and the tapered portion.4. The semiconductor arrangement of claim 1 , the non-tapered portion formed by a wet etch technique and the tapered portion formed by a dry etch technique.5. The semiconductor arrangement of claim 4 , the dry etch technique performed after the wet etch technique.6. The semiconductor arrangement of claim 1 , the tapered portion comprising a curved profile.7. The semiconductor arrangement ...

Transmission device for a door lock

A transmission device for a door lock has a solenoid switch, a driven device and a linkage assembly. The solenoid switch has a solenoid core, a guide tube, a sleeve and a clutch cap. The guide tube is mounted in the solenoid core and has a connecting end. The connecting end is formed on one end of the guide tube and protrudes out of the solenoid core. The sleeve is mounted slidably in the solenoid core and around the guide tube and has at least one engaging tab formed on and protruding from the sleeve at one end adjacent to the connecting end of the guide tube. The clutch cap is mounted around the connecting end of the guide tube and has at least one engaging notch selectively and detachably engaging respectively with a corresponding engaging tab on the sleeve.

Method of implanting dopants into a group III-nitride structure and device formed

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material. 1. A method comprising:depositing a first III-V compound layer on a substrate;depositing a second III-V compound layer over the first III-V compound layer, the second III-V compound layer having a higher bandgap than the first III-V compound layer; andimplanting a first dopants and a group V species into the first III-V compound layer and the second III-V compound layer to define a source/drain region extending through the second III-V compound layer into the first III-V compound layer, wherein a region of the source/drain region below a bottommost surface of the second III-V compound layer comprises the group V species as a result of implanting the group V species into the first III-V compound layer.2. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises simultaneously implanting the first dopants and the group V species.3. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants before implanting the group V species.4. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants after implanting the group V species.5. The method of ...

High electron mobility transistor and method of forming the same

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Stacked LED structure and associated manufacturing method

A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other.

High electron mobility transistors

The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

LED lamp and component, heat dissipating base and LED wireless dimming system thereof

An LED lamp and a component, a heat dissipating base and an LED wireless dimming system thereof are provided. The LED lamp component comprises a heat dissipating base, a light emitting module and a lens, the heat dissipating base has a bearing surface and a back surface opposite to the bearing surface, the bearing surface is provided with a first recessed section therein, the back surface is provided with heat dissipating structures; the heat dissipating base further comprises a first joint portion; the light emitting module is disposed in the first recessed section, and the lens covering the light emitting module.

STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER

The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. 1. A semiconductor structure comprising:a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer;a first buffer layer disposed on the silicon substrate;a heterogeneous buffer layer disposed on the first buffer layer; anda gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions.2. The semiconductor structure of claim 1 , wherein the silicon substrate has a (111) oriented surface.3. The semiconductor structure of claim 1 , wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide claim 1 , silicon nitride claim 1 , and silicon oxynitride.4. The semiconductor structure of claim 1 , whereinthe dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; andthe first set of features intersects the second set of features, defining the plurality of regions.5. The semiconductor structure of claim 4 , wherein the first set of features and second set of features include solid lines and dashed lines;each of the solid lines and the dashed lines has a width ranging between about 0.1 micron and about 5 mm; andthe solid lines and dashed lines in each of the first and second sets are spaced from each other with a spacing ranging between about 100 ...

PISTON ASSEMBLY FOR AIR PUMP

A piston assembly of an air pump is provided herein. The piston of the piston assembly has a through exhaust channel along the direction of the piston's back-and-forth movement. The exhaust channel is made up of two aligned exhaust holes, and a space is preserved at where the two exhaust holes interface. A flexible valve piece is provided inside the space, which will flip upward and downward to block the exhaust holes when the piston moves downward and upward, respectively. When the air pump is turned off and the piston stops moving, the exhaust valve piece would be automatically restored to its un-bended state by its own flexibility, allowing the compressed air inside the cylinder to escape through the exhaust holes and around the exhaust valve piece inside the space.

Transistor having high breakdown voltage and method of making the same

A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×1019 ions/cm3. The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.

Valve plate of a piston cylinder

The structure of an air outlet valve plate of a piston cylinder of an air pump is disclosed. The air outlet valve plates comprises a cylinder mount, an air outlet valve plate, a cylinder, a cylinder inner pad and piston module, characterized in that the cylinder mount is locked to the cylinder by a locking element with the air outlet valve plate being positioned between the mount and the cylinder, and each of a branch plate of the valve plate is corresponding to each of the air hole on the top face of the cylinder, and the valve plate is a plate body with circular connection edge, and the interior of the valve plate is extended outward to form a plurality of equal branch plates, and an equidistant gap s formed between each of the branch plate and the branch plate is independently to be opened or closed, and the bottom face of the connection edge is provided with at least one positioning edge which is corresponding to the sealing pads arranged between the cylinder mount and the cylinder ...

Driving circuit capable of enhancing energy conversion efficiency and driving method thereof

A driving circuit includes a switch, a detecting unit, and a current supply unit. A first terminal of the switch is used for coupling to a first terminal of a first LED group of a plurality of LED groups and receiving a first voltage, and a third terminal of the switch is used for coupling to a first terminal of a last LED group of the plurality of LED groups. The detecting unit is used for outputting a switch control signal to a second terminal of the switch for controlling turning-on and turning-off of the switch. The current supply unit has a plurality of input current terminals, and a ground terminal coupled to ground, where each input current terminal of the plurality of input current terminals is used for coupling to a second terminal of a corresponding LED group of the plurality of LED groups.

LOCK STRUCTURE

A lock structure includes a lock cylinder, a plug and a pin assembly, the plug is within an accommodating space of the lock cylinder. The plug comprises an outer lateral wall, a plurality of first lower pin holes and at least one second lower pin hole, each of the first lower pin holes comprises a first blocking edge, the second lower pin hole comprises a second blocking edge, wherein a second depth defined between the second blocking edge and the outer lateral wall is smaller than a first depth defined between the first blocking edge and the outer lateral wall. By height difference between the position of the first blocking edge and the position of the second blocking edge, an unmatched key can not contact with the second lower pin under instantaneous bump to prevent an unlock situation. Therefore, the burglar proof function is achieved. 1. A lock structure includes:a lock cylinder having an accommodating space;a plug disposed in the accommodating space and having an outer lateral wall, a plurality of first lower pin holes, at least one second lower pin hole and a keyhole, wherein each of the first lower pin holes and the at least one second lower pin hole are recessed from the outer lateral wall, each of the first lower pin holes comprises a first hole surface and a first blocking edge formed at the first hole surface, the at least one second lower pin hole comprises a second hole surface and a second blocking edge formed at the second hole surface, wherein a second depth defined between the second blocking edge and the outer lateral wall is smaller than a first depth defined between the first blocking edge and the outer lateral wall; anda pin assembly including a plurality of first lower pins and at least one second lower pin, each of the first lower pins is disposed at each of the first lower pin holes, and the at least one second lower pin is disposed at the at least one second lower pin hole.2. The lock structure in accordance with claim 1 , wherein the lock ...

Lock assembly

A lock assembly has a housing, a lock cylinder, an adjusting block and multiple rack assemblies. The adjusting block is slidably received in the lock cylinder and has a wedge side facing the lock cylinder and a plurality of first wedge elements formed on the wedge side. The rack assemblies are slidably received respectively in the lock cylinder. Each rack assembly has a rack element, an adjusting base and a resilient member arranged between the rack element and the adjusting base. Each rack element and each adjusting base have a plurality teeth formed thereon and detachably engaged each other respectively. Each rack element has a second wedge element that is selectively engaged or disengaged from one of the first wedge elements on the adjusting block.

Electrostatic discharge protection circuit and driving circuit for an LCD using the same

An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the transistors are connected to each other, and the source electrodes of the transistors are respectively connected to the drain electrodes of the next adjacent transistors in both sets of the transistors. The gate electrode of the ESD transistor, the source electrodes of last transistors of the first and second sets of the transistors are connected to each other, the source electrode of the ESD transistor is connected to the drain electrode of a first transistor of the first set of the transistors, and the drain electrode of the ESD transistor is connected to the drain electrode of a first transistor of the second set of the transistors.

Multi-layer active layer having a partial recess

A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

Structure and method to reduce wafer warp for gallium nitride on silicon wafer

The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

Reducing wafer distortion through a high CTE layer

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

High Electron Mobility Transistor and Method of Forming the Same

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. 1. A semiconductor structure comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition;a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is interposed between the second III-V compound layer and the third III-V compound layer; anda source contact and a drain contact disposed on the second III-V compound layer, wherein the third III-V compound layer is interposed between the source contact and the drain contact.2. The semiconductor structure of claim 1 , further comprising a gate electrode disposed over the third III-V compound layer.3. The semiconductor structure of claim 2 , wherein a width of the third III-V compound layer is less than a width of the gate electrode.4. The semiconductor structure of claim 2 , further comprising a gate dielectric layer claim 2 , the gate dielectric layer being interposed between the gate electrode and the second III-V compound layer.5. The semiconductor structure of claim 1 , wherein a ...

WAFER EDGE PROTECTION STRUCTURE

Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

PISTON STRUCTURE FOR AN AIR PUMP

A piston for an air pump is disclosed. The piston has a piston rod having a connecting axle hole for positioning a bearing, which is protected with a bearing protection cap. The bearing is firmly secured within the axle hole.

LOCK SET TRANSMISSION MECHANISM

A lock set transmission mechanism includes a lock case, a lock core, a transmission rod, a supporting member and a fixing member. The lock core is arranged on the lock case and configured to be driven by a key to rotate relative to the lock case. The transmission rod has a first end configured to be connected to a latch, and a second end. The supporting member includes a first supporting ring sleeved on the lock core, a second supporting ring configured to support the second end of the transmission rod, and at least one supporting rib connected to the first and second supporting rings. The fixing member is configured to fix the supporting member to the lock core. Wherein, when the lock core is rotated relative to the lock case, the transmission rod is driven by the lock core to rotate, in order to move the latch.

ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

High electron mobility transistors

The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon () surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method , comprising:providing a wafer having opposite first and second sides;forming a layer over the first side of the wafer, the layer having a coefficient-of-thermal-expansion (CTE) that is higher than that of the wafer; andforming a III-V family layer over the second side of the wafer, the III-V family layer having a CTE that is higher than that of the wafer.2111. The method of claim 1 , wherein the wafer includes a silicon () surface.3. The method of claim 1 , wherein the forming the layer having the CTE higher than that of the wafer is carried out in a manner so that the layer has a thickness that is less than about 2 microns.4. The method of claim 1 , wherein the forming the III-V family layer is carried out using an epitaxial process claim 1 , the epitaxial process having a process temperature range from about 800 degrees Celsius to about 1400 degrees Celsius; and further including:after the forming the III-V family layer, cooling the III-V family layer and the wafer to a temperature range from about 20 degrees Celsius to about 30 degrees Celsius.5. The method of claim 1 , wherein the forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.6. The method of claim 1 , wherein the forming the ...

FinFET device and method of manufacturing same

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

High Electron Mobility Transistor and Method of Forming the Same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode. 1. A High Electron Mobility Transistor (HEMT) comprising:a first III-V compound layer having a first band gap;a crystalline starting layer having a crystalline structure over and in contact with the first III-V compound layer;a gate dielectric over the crystalline starting layer;a gate electrode over the gate dielectric; anda source region and a drain region in contact with the first III-V compound layer and on opposite sides of the gate electrode.2. The HEMT of further comprising a second III-V compound layer having a second band gap underlying and in contact with the first III-V compound layer claim 1 , wherein the second band gap is smaller than the first band gap.3. The HEMT of further comprising a Two-Dimensional Electron Gas (2DEG) in the second III-V compound layer.4. The HEMT of claim 1 , wherein the crystalline starting layer is a dielectric layer.5. The HEMT of claim 4 , wherein the gate dielectric is an amorphous dielectric layer.6. The HEMT of claim 1 , wherein the crystalline starting layer is a semiconductor layer with a third band gap higher than the first band gap.7. The HEMT of claim 1 , wherein the gate electrode claim 1 , the gate dielectric claim 1 , and the crystalline starting layer are co-terminus claim 1 , with edges of the crystalline starting layer aligned to respective edges of the gate electrode and the gate dielectric.8. The HEMT of claim 1 , wherein the ...

Rough buffer layer for group III-V devices on silicon

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Peak detector

A peak detector comprising of a comparator, an input-trigger device, a gate-width control block, an AND gate, a first current source, a second current source, a first switch, a second switch and a capacitor. The peak detector of this invention uses simple circuits to obtain low frequency energy attenuation. The low frequency attenuation can be programmed and hence able to find the actual average voltage peak. In addition, the simple design makes the peak detector of this invention a suitable replacement candidate for the complicated analogue-to-digital converter conventionally used for detecting average energy attenuation after passing through an electric cable. The peak detector can also be used to measure voltage attenuation for signals passing through LAN, transmission medium such as cable or twisted pair or other related products.

Diffusion barrier layer for source and drain structures to increase transistor performance

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

High electron mobility transistor and method of forming the same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.

Hand-carried air-compressor for car

Lock cylinder structure

A lock cylinder structure comprises a cylinder body, a plug disposed within the cylinder body, a pin assembly and a key positioning assembly. The cylinder body has a plurality of upper pin holes and an accommodating hole. The plug has an outside wall, a keyhole, a plurality of lower pin holes and a through hole in communication with the outside wall and the keyhole. The pin assembly comprises a plurality of upper pins disposed within the upper pin holes and a plurality of lower pins disposed within the lower pin holes. The key positioning assembly comprises a first movable member disposed at the accommodating hole of the cylinder body and a second movable member disposed at the through hole of the plug. The second movable member contacts against the first movable member and has a push-receiving surface.

ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Strengthened lock structure

A strengthened lock structure is disclosed. The lock structure has an outdoor handle group, a bolt, and an indoor handle group. Two first legs of the outdoor handle group are inserted to a respective first location hole and a second location hole defined in the bolt, and a bar of the outdoor handle group is inserted to a first hole defined in the bolt. In this way, the two first legs and the bar form a three point engagement between the outdoor handle and the bolt, whereby the engagement strength between the outdoor handle (11) and the bolt is enhanced to prevent forced entry.

Magnetic memory arrays

A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.

Seed layer structure for growth of III-V materials on silicon

The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

Lock escutcheon assembly

SIDEWALL PASSIVATION FOR HEMT DEVICES

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Lock collar

Cable connector assembly with improved luminous effect

A cable connector assembly (100) comprises: a first connector (10) having a main body (120), a number of contacts (121) retained in the main body, a first circuit board (130) electrically connected to the contacts, and a metal shell (110) enclosing the first circuit board; a cable (30) electrically connected between the first circuit board and a power source to provide a power to the first circuit board; a second circuit board (150) vertically fixed on the metal shell; a cover enclosing the first and the second circuit board; a luminous element (152) disposed on a front side of the second circuit board and electrically connected to the first circuit board; and a translucent portion (1610) defined on a front end of the cover to pass light emitted by the luminous element.

Apparatus for input power detection and method thereof

An electronic device includes an input power detection unit, a transmission control unit and a converter. The input power detection unit is configured to determine an input voltage value and an input current value of an input power. In response to the input power, the transmission control unit is configured to determine a first voltage value and a first current value associated with another electronic device via a handshake process. The voltage converter is configured to convert the input power into a first power required by the another electronic device.

Method of implanting dopants into a group III-nitride structure and device formed

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Graphics Pipeline That Supports Multiple Concurrent Processes

A Graphics Processing Unit (GPU) concurrently executes kernel codes programmed in more than one programming framework. The GPU includes a first command decoder that decodes a first set of commands issued by a first Application Programming Interface (API) for executing a first kernel code. The GPU also includes a second command decoder that decodes a second set of commands issued by a second API for executing a second kernel code. The GPU also includes a plurality of shader cores and a pipe manager. According to decoded commands, the pipe manager assigns a first set of shader cores and a second set of shader cores to concurrently execute the first kernel code and the second kernel code, respectively. 1. A Graphics Processing Unit (GPU) operative to concurrently execute kernel codes programmed in more than one programming framework , the GPU comprising:a first command decoder to decode a first set of commands issued by a first Application Programming Interface (API) for executing a first kernel code of a first programming framework;a second command decoder to decode a second set of commands issued by a second API for executing a second kernel code of a second programming framework;a plurality of shader cores; anda pipe manager coupled to the first command decoder, the second command decoder and the shader cores, the pipe manager to assign a first set of shader cores and a second set of shader cores to concurrently execute the first kernel code and the second kernel code, respectively, according to decoded commands.2. The GPU of claim 1 , further comprising:a fixed-function pipeline operative to execute the first kernel code with the first set of the shader cores according to the first set of commands decoded by the first command decoder.3. The GPU of claim 2 , wherein the fixed-function pipeline and the first set of the shader cores are operative to perform operations of 3D graphics rendering and image composition according to the first kernel code.4. The GPU of claim ...

LOCK ASSEMBLY

A lock assembly has a housing, a lock cylinder, an adjusting block and multiple rack assemblies. The adjusting block is slidably received in the lock cylinder and has a wedge side facing the lock cylinder and a plurality of first wedge elements formed on the wedge side. The rack assemblies are slidably received respectively in the lock cylinder. Each rack assembly has a rack element, an adjusting base and a resilient member arranged between the rack element and the adjusting base. Each rack element and each adjusting base have a plurality teeth formed thereon and detachably engaged each other respectively. Each rack element has a second wedge element that is selectively engaged or disengaged from one of the first wedge elements on the adjusting block.

Lock escutcheon assembly

High electron mobility transistor with indium nitride layer

A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the indium gallium nitride layer, the annealed region comprising indium atoms driven from the indium gallium nitride layer into the active layer.

Method of manufacturing a semiconductor device including a barrier structure

A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.

Clock duty cycle control circuit

A clock duty cycle control circuit comprises a reference voltage circuit and a constant current generator connected to the reference voltage circuit. A duty-cycle adjustment circuit is used to receive a clock signal and controlled by the bias voltage of the bias voltage generating circuit which is connected to constant current generator. Accordingly, by a method of controlling duty-cycle adjustment circuit, the bias voltage has capability for adjusting a charging time and a discharging time of the clock signal. Finally, an open-drain driver with open-drain output is connected to the duty-cycle adjustment circuit, and thereby substantially stabilizing the output duty cycle of the clock signal.

REKEYABLE LOCK CYLINDER

A rekeyable lock cylinder comprises a cylinder body, a plug assembly disposed within the cylinder body and an operation error preventing unit. The cylinder body has a plurality of upper pin holes and an accommodating hole. The plug assembly comprises a plug body, a plurality of assembled rack components and a position block disposed within the plug body. The plug body has an outside wall, a keyhole, a plurality of lower pin holes and a first hole in communication with the outside wall and the keyhole. The assembled rack components are disposed at each of the lower pin holes of the plug body respectively. The operation error preventing unit comprises a first movable member disposed at the accommodating hole of the cylinder body and a second movable member disposed at the first hole of the plug body, and the first movable member may contact against the second movable member.

Magnetic random access memory with tape read line, fabricating method and circuit thereof

A magnetic random access memory with tape read line, fabricating method and circuit thereof is provided. The memory is composed of a top write line, a bottom write line which is vertical to the top write line, a MTJ formed on the bottom write line, a spacer formed around the MTJ, and a tape read line formed on the MTJ. The fabricating steps involves forming a bottom write line, forming a MTJ on the bottom write, and forming a tape read line on the MTJ sequentially. In the circuit, the tape read line is either parallel to or vertical to the top write line.

Card edge connector with durable key

A card edge connector (100) adapted for a daughter card with at least one notch comprises a housing (1) made from insulating material and contacts. The housing comprises a slot (12) for receiving the daughter card along its length direction and channels (14) communicating with the slot. The contacts (2) is received in the channels, each comprising a contacting section extending in the slot for contacting with the daughter card and a leg extending out of the housing. At least one key (5) for matching with the at least one notch of the daughter card is transverly retained in the slot and is better than the housing in resistibility of abrasion or breakage.

Data transmission system and a programmable SPI controller

A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal.

DRIVING CIRCUIT CAPABLE OF ENHANCING ENERGY CONVERSION EFFICIENCY AND DRIVING METHOD THEREOF

A driving circuit includes a switch, a detecting unit, a current supply unit, and an energy storage unit. The current supply unit is used for providing a driving current for at least one series of light emitting diodes. The detecting unit is used for comparing a voltage of a first terminal of the detecting unit with a reference voltage to generate a switch control signal. When the switch is turned on according the switch control signal, a first voltage drives the series of light emitting diodes through the switch and the energy storage unit is charged according a charge current. When the switch is turned off according the switch control signal, the energy storage unit drives the series of light emitting diodes according to a discharge current. 1. A driving circuit capable of enhancing energy conversion efficiency , the driving circuit comprising:a switch having a first terminal for receiving a first voltage, a second terminal, and a third terminal for being coupled to a first terminal of at least one series of light emitting diodes;a detecting unit having a first terminal for being coupled to a second terminal of the at least one series of light emitting diodes, a second terminal coupled to the second terminal of the switch for outputting a switch control signal, and a third terminal coupled to ground, wherein the detecting unit is used for generating the switch control signal according to a voltage of the second terminal of the at least one series of light emitting diodes;a current supply unit having a first terminal for being coupled to the second terminal of the at least one series of light emitting diodes, and a second terminal coupled to the ground, wherein the current supply unit is used for providing a driving current to the at least one series of light emitting diodes; andan energy storage unit having a first terminal for being coupled to the first terminal of the at least one series of light emitting diodes, and a second terminal coupled to the ground, ...

Method of forming a high electron mobility transistor

A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

QUICKLY REKEYABLE LOCK CYLINDER AND PLUG ASSEMBLY THEREOF

A quickly rekeyable lock cylinder comprises a cylinder body and a plug assembly disposed within the cylinder body. The plug assembly comprises a plug body, a position block disposed at the plug body, a first rack group and a second rack group. The plug body has a longitudinal axis, a transverse axis vertical to the longitudinal axis and a rekeying tool opening. The first rack group has a plurality of first rack components. The second rack group may push the position block to move and has a plurality of second rack components in engagement with the first rack components and at least one tool-receiving portion pushed by the rekeying tool. The second rack components can move along transverse axis of the plug body to release engagement with the first rack components.

SOURCE/DRAINS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

SIDEWALL PASSIVATION FOR HEMT DEVICES

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Memory device with rapid word line switch

A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Sidewall passivation for HEMT devices

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

CLEANING APPARATUS FOR CONCENTRATION CONTROLLER OF COATING MACHINE

A cleaning apparatus for concentration controller of coating machine may include a pulse bubble generator and a container used for cleaning a concentration controller of a coating machine and a tube thereof. The pulse bubble generator has a bubble-generating end connected to the container through a pipe, and the container is filled with a plentiful detergent. The pulse bubble generator is configured to pump air into the detergent with a pulse per time, and a large amount of detergent bubbles are adapted to be generated in the container. The detergent bubbles are configured to be pumped by the concentration controller into the tube and the concentration controller so as to complete cleaning effect of the tube and the concentration controller.

Method of embedding semiconductor element in carrier and embedded structure thereof

A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

Method of embedding semiconductor element in carrier and embedded structure thereof

A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.

CABLE CONNECTOR ASSEMBLY ADAPTED FOR POWER AND SIGNAL TRANSMITTING

A cable connector assembly () includes a first connector () used for transmitting power, a second connector () for transmitting signal, a cover () holding the first connector and the second connector, a cable () connected with the first connector and the second connector and a ferrule () mounted to the cover. The first connector has a body portion (), the ferrule has a main portion () around the body portion of the first connector and a number of equally spaced spring tabs (), the spring tabs are extending along a transverse direction and elastically pressing onto the body portion of the first connector. 1. A cable connector assembly , comprising:a first connector used for transmitting power, the first connector having a body portion;a second connector for transmitting signal;a cover holding the first connector and the second connector;a cable connected with the first connector and the second connector; anda ferrule mounted to the cover and having a main portion around the body portion of the first connector and a plurality of equally spaced spring tabs, the spring tabs extending along a transverse direction and elastically pressing onto the body portion of the first connector.2. The cable connector assembly as claimed in claim 1 , wherein the ferrule has a plurality of retaining tabs formed at opposite ends of the main portion symmetrically claim 1 , and the retaining tabs on a same side are arranged along a front-to-back direction.3. The cable connector assembly as claimed in claim 2 , wherein the ferrule is hollow claim 2 , and the spring tabs extend into to press the first connector.4. The cable connector assembly as claimed in claim 3 , wherein the first connector has a rear flange claim 3 , and a rear end of the ferrule is adjacent to a front end of the flange.5. The cable connector assembly as claimed in claim 4 , wherein both the main portion and the body portion are substantially cylindrical claim 4 , and there is an annular gap between the main portion and ...

Wireless charger assembly mountable on different desks

A wireless charger assembly is used for transferring power to an electronic device through inductive charging. The wireless charger assembly includes a bottom case releasably mounted to an exterior flatbed, a transmitter coil, and a top case. The transmitter coil transmits power to a receiver coil of the electronic device through inductive charging. The top case has a working platform mounted around the working surface of the flatbed, a neck portion extending downwardly from the working platform, and a slot defined by the working platform and the neck portion. The neck portion releasably retained to the closed loop wall.

High electron mobility transistor and method of forming the same

A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.

Lock assembly

A lock assembly has a housing, a lock cylinder, an adjusting block and an adjusting assembly. The adjusting block is slidably on the lock cylinder and has a wedge side facing the lock cylinder and a plurality of first wedge elements formed on the wedge side. The adjusting assembly is mounted in the lock cylinder and has multiple adjustable rack assemblies mounted in the lock cylinder. Each rack assembly has a rack element and an adjusting base. The rack element selectively abuts with a corresponding one of the lock pins and has a second wedge element selectively engaging one of the first wedge elements on the adjusting block. The adjusting base selectively engages the rack element.

Piston assembly for air pump

A piston assembly of an air pump is provided herein. The piston of the piston assembly has a through exhaust channel along the direction of the piston's back-and-forth movement. The exhaust channel is made up of two aligned exhaust holes, and a space is preserved at where the two exhaust holes interface. A flexible valve piece is provided inside the space, which will flip upward and downward to block the exhaust holes when the piston moves downward and upward, respectively. When the air pump is turned off and the piston stops moving, the exhaust valve piece would be automatically restored to its un-bended state by its own flexibility, allowing the compressed air inside the cylinder to escape through the exhaust holes and around the exhaust valve piece inside the space.

III-V multi-channel FinFETs

A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

Rekeyable lock cylinder and operating method thereof

A rekeyable lock cylinder comprises a cylinder body and a plug assembly disposed within the cylinder body. The plug assembly comprises a plug body, a plurality of assembled pins and a position block. The plug body has a longitudinal axis, a transverse axis vertical to the longitudinal axis, a keyhole and a first through hole. Each of the assembled pins is movably disposed in the plug body and comprises a first rack component and a second rack component selectively engaging with the first rack component. The position block disposed at the plug body has a plurality of pin runners used for disposing the first rack components, a second through hole corresponding to the first through hole and a tool-contacting surface located within the second through hole. The position block can move along the transverse axis-direction of the plug body to make each of the first rack components reengage with each of the second rack components.

ASYMMETRIC QUANTIZATION OF MULTIPLE-AND-ACCUMULATE OPERATIONS IN DEEP LEARNING PROCESSING

A processing unit performs multiply-and-accumulate (MAC) operations on asymmetrically quantized data. The processing unit includes a MAC hardware unit to perform the MAC operations on a first data sequence and a second data sequence to generate an asymmetric MAC output. Both the first data sequence and the second data sequence are asymmetrically quantized. The processing unit further includes an accumulator hardware unit to accumulate the first data sequence concurrently with the MAC operations to generate an accumulated output. The processing unit further includes a multiply-and-add (MAD) hardware unit to multiply the accumulated output with a second offset to generate a multiplication output, and to add the multiplication output, the asymmetric MAC output and a pre-computed value calculated before runtime to generate a final output. The second offset indicates an amount of asymmetry of the second data sequence with respect to zero. 1. An apparatus for performing multiply-and-accumulate (MAC) operations on asymmetrically quantized data , comprising:a MAC hardware unit to perform the MAC operations on a first data sequence and a second data sequence to generate an asymmetric MAC output, wherein both the first data sequence and the second data sequence are asymmetrically quantized;an accumulator hardware unit to accumulate the first data sequence concurrently with the MAC operations to generate an accumulated output; anda multiply-and-add (MAD) hardware unit to multiply the accumulated output with a second offset to generate a multiplication output, wherein the second offset indicates an amount of asymmetry of the second data sequence with respect to zero, and to add the multiplication output, the asymmetric MAC output and a pre-computed value calculated before runtime to generate a final output.2. The apparatus of claim 1 , wherein the pre-computed value is calculated from at least a first offset claim 1 , the second offset and an accumulation of the second data ...

Probe head of probe card and manufacturing method of composite board of probe head

A probe head of vertical probe card and a manufacturing method of a composite board thereof are provided. The probe head includes guide plate, composite board, and probe pin. The composite board includes first board layer and second board layer which are laminated together by joining operation. The composite board further includes through hole which is made by drilling and passed all the way through the first board layer and the second board layer. The friction coefficient of the first board layer is less than that of the second board layer, and the thermal expansion coefficient of the second board layer is less than that of the first board layer. The probe pin is penetrated all the way through the through hole of the composite board. By this, friction between the probe pin and composite board is reduced so as to stabilize the position of the probe pin.

DIRECT-DOCKING PROBING DEVICE

A direct-docking probing device is provided. The probing device includes a probe interface board, a space transformer, a conductive elastic member, a fixing frame, and at least one vertical probe assembly. The space transformer includes a space transforming plate and a reinforcing plate, and the mechanical strength of the reinforcing plate is larger than that of the space transforming plate. The reinforcing plate is electrically connected with the space transforming plate. Furthermore, the conductive elastic member is electrically connected with the probe interface board and the reinforcing plate. The fixing frame includes a stiffener, a frame body, and a pressing portion. The stiffener is disposed on the probe interface board. The frame body contains the conductive elastic member. The pressing portion is pressed on the space transformer. The vertical probe assembly includes a plurality of vertical probes which are electrically connected with the space transforming plate. 1. A direct-docking probing device , comprising:a probe interface board;a space transformer, the space transformer comprising a space transforming plate and a reinforcing plate, the reinforcing plate located between the probe interface board and the space transforming plate, a plurality of circuits disposed in the reinforcing plate, the reinforcing plate electrically connected with the space transforming plate by a plurality of solders, and the mechanical strength of the reinforcing plate being larger than the mechanical strength of the space transforming plate;a conductive elastic member, the conductive elastic member located between the reinforcing plate and the probe interface board, and the conductive elastic member electrically connected with the probe interface board and the reinforcing plate;a fixing frame, the fixing frame comprising a stiffener, a frame body, and a pressing portion, the stiffener disposed on the probe interface board, the conductive elastic member contained in the frame ...

APPARATUS FOR PERFORMING TIMER MANAGEMENT REGARDING A SYSTEM TIMER SCHEDULER SERVICE, AND ASSOCIATED METHOD

An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption. 1. An apparatus for performing timer management regarding a system timer scheduler service , comprising:a processor arranged to control operations of the apparatus;an ordinary timer arranged to provide the processor with time ticks, for use of timing control; anda hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service.2. The apparatus of claim 1 , wherein with aid of the hardware-based OS timer claim 1 , the system timer scheduler service provides an event-based OS timer scheduler.3. The apparatus of claim 2 , wherein with the aid of the hardware-based OS timer claim 2 , the system timer scheduler service provides the event-based OS timer scheduler to save run-time power consumption.4. The apparatus of claim 1 , wherein with aid of the hardware-based OS timer claim 1 , the system timer scheduler service provides timer alignment in accordance with modulator/demodulator ...

Resynchronization Method for Recovering from Sleep Mode and Apparatuses Using the Same

A wireless communications device connected to a service network with a synchronized timing pattern therebetween is provided. In the wireless communications device, a wireless modem is configured to enable wireless signal transceiving from and to the service network in a non-sleep mode and disable wireless signal transceiving from and to the service network in a sleep mode. Also in the wireless communications device, a synchronization module is configured to initialize a first counter with a current time in the synchronized timing pattern in response to a first signal triggering the wireless modem to enter the sleep mode from the non-sleep mode, and enable counting of the first counter in a low-rate clock for the sleep mode. The synchronization module further provides the counted value of the first counter to the wireless modem to resynchronize with the service network in response to a second signal triggering the wireless modem to recover from the sleep mode to the non-sleep mode. 1. A wireless communications device connected to a service network with a synchronized timing pattern therebetween , comprising:a wireless modem configured to enable wireless signal transceiving from and to the service network in a non-sleep mode and disable wireless signal transceiving from and to the service network in a sleep mode; anda synchronization module configured to initialize a first counter with a current time in the synchronized timing pattern in response to a first signal triggering the wireless modem to enter the sleep mode from the non-sleep mode, enable counting of the first counter in a low-rate clock for the sleep mode, and provide the counted value of the first counter to the wireless modem to resynchronize with the service network in response to a second signal triggering the wireless modem to recover from the sleep mode to the non-sleep mode.2. The wireless communications device as claimed in claim 1 , wherein the current time in the synchronized timing pattern is ...

SILICON WAFER STRENGTH ENHANCEMENT

Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion. 1. A method , comprising:receiving a silicon wafer that contains oxygen;forming a zone in the silicon wafer, the zone being substantially depleted of oxygen;causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; andgrowing the oxygen nuclei into defects.2. The method of claim 1 , wherein:the forming the zone includes subjecting the silicon wafer to a first temperature, the first temperature being high enough to cause oxygen out-diffusion;the causing the nucleation process includes subjecting the silicon wafer to a second temperature that is less than the first temperature; andthe growing the oxygen nuclei includes subjecting the silicon wafer to a third temperature that is greater than the second temperature but less than the first temperature.3. The method of claim 2 , wherein:the first temperature is greater than about 1100 degrees Celsius;the second temperature is in a range from about 750 degrees Celsius to about 850 degrees Celsius; andthe third temperature is in a range from about 950 degrees Celsius to about 1050 degrees Celsius.4. The method of claim 2 , wherein:the forming the zone includes subjecting the silicon wafer to the first temperature for more than ...

Method and Apparatus for Forming a III-V Family Layer

Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool. 1. A method , comprising:forming a first layer over a wafer, the first layer containing a group III-V compound; andforming a second layer over the first layer, the second layer and the first layer containing different material compositions;wherein the forming the first layer and the forming the second layer are performed in a manner such that the wafer is prevented from being exposed to at least one of oxygen and silicon between the forming the first layer and the forming the second layer.2. The method of claim 1 , wherein:the forming the first layer is performed in a first deposition chamber of a cluster semiconductor fabrication tool;the forming the second layer is performed in a second deposition chamber of the cluster semiconductor fabrication tool; andthe first deposition chamber and the second deposition chamber are interconnected by a transfer chamber that is substantially free of oxygen and silicon.3. The method of claim 2 , wherein:the first deposition chamber includes a metal-organic chemical vapor deposition (MOCVD) chamber; andthe second deposition chamber includes a low-pressure chemical vapor deposition (LPCVD) chamber.4. The method of claim 1 , wherein the group III-V compound includes gallium nitride.5. The method of claim 1 , wherein the second layer ...

Probing device

A probing device includes a circuit board, a reinforcing plate, at least one space transformer and at least one probe assembly. The reinforcing plate is disposed on the circuit board, and the reinforcing plate has a plurality of inner conductive wires electrically connecting to those of the circuit board. The reinforcing plate defines a plurality of receiving space therein. The space transformer is disposed on the reinforcing plate, and the space transformer has a plurality of inner conductive wires electrically connecting to those of the reinforcing plate via a plurality of first solder balls. The probe assembly is disposed on the space transformer, and the probe assembly includes a plurality of probes. The first solder balls are disposed in the receiving spaces, and the reinforcing plate abuts against the space transformer.

PROBING DEVICE AND MANUFACTURING METHOD THEREOF

A probing device and manufacturing method thereof are provided. The manufacturing method includes first disposing a plurality of space transformers on a reinforcing plate and the space transformer includes several first pads. Then, the space transformer is fixed on the reinforcing plate. Thereafter, photoresist films having a plurality of openings is formed on the space transformer. The first pads are disposed in the openings. After that, a metal layer is formed and covered on the first pad. Later, the photoresist film is removed and the metal layer is planarized to form a second pad. Afterwards, the reinforcing plate is electrically connected with a PCB. Thereafter, a probe head having a plurality of probing area is provided and each probing area is corresponding to one of the space transformer. The probes in the probing area are electrically connected with the internal circuitry of the space transformer. 1. A manufacturing method for a probing device comprising:providing a reinforcing plate;disposing a plurality of space transformers on the reinforcing plate, wherein a plurality of first pads are disposed on a surface of each space transformer;fixing the space transformer on the reinforcing plate, for configuring the internal circuitry of the space transformer to be electrically connected to the internal circuitry of the reinforcing plate;forming a photoresist film on the space transformer, wherein the photoresist film comprises a plurality of openings and the first pad is disposed in the opening;forming a metal layer in each of the plurality of openings, wherein the metal layer covers the plurality of first pads for forming a plurality of second pads;removing the photoresist film;providing a printed circuit board and electrically connecting the internal circuitry of the reinforcing plate to the internal circuitry of the printed circuit board; andproviding a probe head, the probe head comprising a plurality of probing areas, each probing area corresponding to one ...

OPTICAL-ELECTRICAL CONNECTOR HAVING A MAGNETIC MEMBER

An optical-electrical connector () includes a housing (), a circuit board () received in the housing and having a transducer for bidirectional optical-electrical signal conversion, a lens member () mounted on the circuit board, a ferrule () receiving a number of optical channels and having a resisting face (), and a magnetic member (). The ferrule is situated behind the lens member and aligned with the lens member along a front-to-back direction. The magnetic member has a metal sheet () and at least one magnetic component () secured in the housing. The metal sheet abuts against the resisting face of the ferrule under a magnetic force provided by the at least one magnetic component, to provide a forward resilient force to the ferrule for fixing the ferrule to the lens member. 1. An optical-electrical connector comprising:a housing;a circuit board received in the housing and having a transducer for bidirectional optical-electrical signal conversion;a lens member mounted on the circuit board;a ferrule receiving a plurality of optical channels and having a resisting face, one of the lens member and the ferrule having a guide pin, and another one of the lens member and the ferrule having a guide hole, said ferrule being situated behind the lens member within the housing and aligned with the lens member along a front-to-back direction via an engagement between the guide pin and the guide hole; anda magnetic member having a metal sheet and at least one magnetic component secured in the housing, said metal sheet abutting against the resisting face of the ferrule under a magnetic force provided by the at least one magnetic component, to provide a forward resilient force to the ferrule for fixing the ferrule to the lens member.2. The optical-electrical connector as claimed in claim 1 , further comprising a cover attached to an upper portion of the housing.3. The optical-electrical connector as claimed in claim 2 , wherein there are a pair of magnetic components claim 2 , said ...

SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE

A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity. 1. A circuit structure comprising:a silicon substrate;a nucleation layer of undoped aluminum nitride over the silicon substrate;a buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant over the nucleation layer; and,a bulk layer of undoped gallium nitride over the buffer layer.2. The circuit structure of claim 1 , wherein the buffer layer comprises a graded buffer layer and an ungraded buffer layer claim 1 , said graded buffer layer further comprising aluminum.3. The circuit structure of claim 1 , wherein the p-type conductivity dopant comprises at least one of carbon claim 1 , iron claim 1 , magnesium claim 1 , and zinc.4. The circuit structure of claim 3 , wherein the p-type conductivity dopant in the graded buffer layer is an impurity having a total concentration of between about 1 E/cmand 1 E/cm.5. The circuit structure of claim 3 , wherein the p-type conductivity dopant in the ungraded buffer layer and the graded buffer layer is different with respect to composition and/or concentration.6. The circuit structure of claim 1 , wherein the buffer layer is about 1 to about 3 microns thick.7. The circuit structure of claim 1 , wherein the ungraded buffer layer is about 0.5 to about 3 microns thick.8. The circuit structure of claim 1 , further comprising an active layer over the bulk layer claim 1 , the active layer including a layer of ...

FinFET Device And Method Of Manufacturing Same

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer. 1. A semiconductor device comprising:a substratea first dielectric layer disposed over the substrate;a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer;an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer;a second dielectric layer disposed over the first dielectric layer and the insulator layer; anda fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.2. The semiconductor device of further comprising:a gate structure disposed over the fin structure, the gate structure separating source and drain regions of the semiconductor device, the source and drain regions defining a channel region therebetween.3. The semiconductor device of wherein the buffer layer is a type III/V material having a crystal structure claim 1 , and wherein insulator layer is a type III/V material having a crystal structure.4. The semiconductor device of wherein the buffer layer includes a material selected from the group consisting of AlAs claim 1 , AlAs/Ge claim 1 , InP ...

III-V Multi-Channel FinFETs

A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric. 1. A device comprising:a semiconductor substrate;insulation regions over portions of the semiconductor substrate, wherein the insulation regions comprise sidewalls substantially facing each other; a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap; and', 'a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers, wherein the second III-V compound semiconductor material has a second band gap lower than the first band gap;, 'a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between the sidewalls of the insulation regions, and wherein the III-V compound semiconductor region comprisesa gate dielectric on a sidewall and a top surface of the III-V compound semiconductor region; anda gate electrode over the gate dielectric.2. The device of claim 1 , wherein the first III-V compound ...

COIL COMPONENT AND MANUFACTURING METHOD THEREOF

A manufacturing method of a coil component comprises a forming step to form a first coil and a second coil connecting to each other, wherein the first coil is disposed at the inside of the second coil; a disposing step to dispose a part of a tail segment of the first coil on a last-loop segment of the second coil along a contour of the last-loop segment of the second coil; and a covering step to cover the first coil and the second coil. 1. A manufacturing method of a coil component , comprising:a forming step to form a first coil and a second coil connecting to each other, wherein the first coil is disposed at the inside of the second coil;a disposing step to dispose a part of a tail segment of the first coil on a last-loop segment of the second coil along a contour of the last-loop segment of the second coil; anda covering step to cover the first coil and the second coil.2. The manufacturing method of a coil component as recited in claim 1 , further comprising:a soldering step to solder the first coil and the second coil to a lead frame;a removing step to remove the lead frame to form two pins after the covering step; anda bending step to bend the pins.3. The manufacturing method of a coil component as recited in claim 1 , wherein the forming step further comprises:spirally winding a first portion of a wire toward a first direction to form the first coil; andspirally winding a second portion of the wire toward a second direction to form the second coil outside the first coil, wherein the first direction is opposite to the second direction.4. The manufacturing method of a coil component as recited in claim 1 , wherein the disposing step further comprises:stretching the tail segment from the first coil; anddisposing the tail segment along the contour of the last-loop segment.5. The manufacturing method of a coil component as recited in claim 1 , wherein the disposing step further comprises:pushing the first coil from the opposite side of the tail segment so that the ...

COIL COMPONENT AND MANUFACTURING METHOD THEREOF

A manufacturing method of a coil component comprises the steps of: providing a first permeance element; sticking a strip-like element to a first area of a first surface of the first permeance element; providing a second permeance element; disposing a winding structure between the first permeance element and the second permeance element, or around at least one of the first permeance element and the second permeance element; and connecting the first permeance element and the second permeance element by a connecting material stuck to a second area, which is without the strip-like element, of the first surface. 1. A manufacturing method of a coil component , comprising:providing a first permeance element;sticking a strip-like element into a first area of a first surface of the first permeance element;providing a second permeance element;disposing a winding structure between the first permeance element and the second permeance element or around at least one of the first permeance element and the second permeance element; andconnecting the first permeance element and the second permeance element by a connecting material stuck to a second area, which is without the strip-like element, of the first surface.2. The manufacturing method as recited in claim 1 , wherein the first area is perpendicular to the second area.3. The manufacturing method as recited in claim 1 , wherein the second permeance element comprises an edge-protruding portion facing the second area claim 1 , and the connecting material sticks the edge-protruding portion and the second area.4. The manufacturing method as recited in claim 1 , wherein the second permeance element comprises a center-protruding portion claim 1 , the winding structure is disposed around the center-protruding portion claim 1 , and the connecting material sticks the center-protruding portion and the center of the first surface.5. The manufacturing method as recited in claim 1 , further comprising:sticking another strip-like element to ...

NEW III-NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer. 1. A circuit structure comprising:a silicon substrate;a patterned dielectric layer over and in direct contact with an top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through a dielectric layer, said plurality of vias arranged in a hexagonal pattern;a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer; and,a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.2. The circuit structure of claim 1 , further comprising a graded group III-V superlattice layer.3. The circuit structure of claim 1 , wherein the patterned dielectric layer is a thermal silicon oxide layer.4. The circuit structure of claim 1 , wherein the vertical growth layer and the lateral growth layer consist essentially of a same material.5. The circuit structure of claim 1 , wherein the vias have an aspect ratio of about 2 to about 5.6. The circuit structure of claim 5 , wherein each via is separated from an adjacent via by about 2 microns to about 5 microns.7. The circuit structure of claim 5 , wherein each via is about 3000 angstroms to about 5000 angstroms deep.8. The circuit structure of claim 5 , wherein each via has a diameter of about 1000 angstroms to about 2000 angstroms.9. The circuit structure of claim 5 , wherein ...

GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer. 1. A semiconductor structure comprising:a silicon substrate;a first bulk layer of group III-V compound semiconductor over the silicon substrate;an interlayer over the first bulk layer of group III-V compound semiconductor; anda second bulk layer of group III-V compound semiconductor over the interlayer.2. The semiconductor structure of claim 1 , further comprising a graded group III-V superlattice layer.3. The semiconductor structure of claim 1 , further comprising an AlN nucleation layer.4. The semiconductor structure of claim 1 , wherein the interlayer is made of AlN.5. The semiconductor structure of claim 1 , wherein the first bulk layer of group III-V compound is GaN.6. The semiconductor structure of claim 2 , wherein the graded group III-V superlattice layer has a thickness between 500 and 1000 nm.7. The semiconductor structure of claim 3 , wherein the AlN nucleation layer has a thickness between 150 and 300 nm.8. The semiconductor structure of claim 1 , wherein a second interlayer is over the second bulk layer of group III-V compound semiconductor.9. The semiconductor structure of claim 1 , wherein a third bulk layer of group III-V compound semiconductor is over the second interlayer.10. The semiconductor structure of claim 1 , wherein more than two bulk layers of group III-V compound semiconductor are over the silicon substrate.11. The semiconductor structure of claim 10 , wherein each bulk layer of group III-V compound semiconductor is separated by an interlayer.12. The semiconductor structure of claim 1 , wherein the bulk layer is about 0.5 to about 5 microns.1318-. (canceled)19. The method of claim 1 , wherein the semiconductor structure is a light emitting diode.20. The method of claim 1 , wherein the semiconductor ...

Electrical connector assembly and method of manufacturing the same

An electrical connector assembly comprises: a metallic housing having a receiving space extending along a longitudinal and two openings respectively formed on top and bottom surfaces thereof and communicated with the receiving space; a pair of flexible printed circuit boards (FPCs) received into the receiving space and arranged in a back-to-back manner. Each of the FPC defines a protuberant portion extending into the corresponding opening. And each of the protuberant portion has a plurality of contacts formed on one side thereof and communicated with an exterior. A pair of supporting pieces are received into the receiving space and attached to another side of the protuberant portion. And a spacer is received into the receiving space and sandwiched between the pair of flexible printed circuit boards and supporting pieces.

Graded Aluminum-Gallium-Nitride and Superlattice Buffer Layer for III-V Nitride Layer on Silicon Substrate

The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlGaN/AlGaN layer pairs. 1. An integrated circuit comprising:a silicon substrate having a first lattice structure;a group III nitride layer overlying the silicon substrate and having a second lattice structure; a first buffer region', 'a second buffer region; and', {'sub': x', '1−x', 'y', '1−y, 'a superlattice structure comprising AlGaN/AlGaN repeating layer pairs.'}], 'a lattice-matching structure arranged between the silicon substrate and the group III nitride layer configured to provide an interface between the first lattice structure and the second lattice structure, comprising2. The integrated circuit of claim 1 , wherein the first buffer region of the lattice matching structure comprises a first layer of an AlN formed at a thickness from about 20 nm to about 80 nm and a second layer of an aluminum nitride formed at a thickness of from about 50 to about 200 nm.3. The integrated circuit of claim 1 , wherein the second buffer region of the lattice-matching structure comprises a plurality of graded AlGaN layers.4. The integrated circuit of claim 3 , wherein x decreases continuously from an first graded AlGaN layer to a subsequent graded AlGaN layer.5. The integrated circuit of claim 3 , wherein the plurality of graded AlGaN layers comprises three layers.6. The integrated circuit of claim 3 , wherein x comprises from about 0.9 to about 0.7 in a first layer claim 3 , x comprises from about 0.4 to about 0.6 in a second layer claim 3 , and x comprises from about 0.15 to about 0.2 in a third layer.7. The integrated circuit of claim 6 , wherein the first layer comprises a thickness of from about 50 nm to about 200 nm claim 6 , the second layer comprises a ...

Diffusion Barrier Layer for Group III Nitride on Silicon Substrate

The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and Ofrom a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise AlO. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer. 1. An integrated circuit comprising:a silicon substrate having a first lattice structure;a GaN layer disposed over the silicon substrate and having a second lattice structure that differs from the first lattice structure;a lattice-matching structure arranged between the silicon substrate and the GaN layer and arranged to interface the first lattice structure to the second lattice structure; anda diffusion-barrier layer arranged between the silicon substrate and the lattice matching structure, the diffusion-barrier layer configured to limit diffusion of silicon Of and oxygen from the silicon substrate to the lattice matching structure.2. The integrated circuit of claim 1 , wherein the barrier layer comprises a single crystal alpha or gamma crystal structure.3. The integrated circuit of claim 1 , wherein the barrier layer comprises AlO claim 1 , SiN claim 1 , ZnO claim 1 , MgO claim 1 , LaO claim 1 , or YO.4. The integrated circuit of claim 1 , wherein the silicon substrate is Si(111).5. The integrated circuit of claim 1 , wherein the lattice matching structure comprises a first region and a second region.6. The integrated circuit of claim 5 , wherein the first region of the lattice matching structure comprises a first layer of an aluminum nitride formed at a first temperature and a second layer of an aluminum nitride formed at second temperature higher than the first temperature.7. The integrated circuit of claim 6 , wherein the thickness of the first aluminum nitride layer is ...

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature. 1. A high electron mobility transistor (HEMT) comprising:a first III-V compound layer;a second III-V compound layer on the first III-V compound layer and different from the first III-V compound layer in composition;a source feature and a drain feature in contact with the second III-V compound layer;a n-type doped region underlying each source feature and drain feature in the second III-V compound layer;a p-type doped region underlying each n-type doped region in the first III-V compound layer; anda gate electrode over a portion of the second III-V compound layer between the source feature and the drain feature.2. The HEMT of claim 1 , wherein the n-type doped region comprises a Group IV element.3. The HEMT of claim 1 , wherein the n-type doped region comprises silicon or oxygen.4. The HEMT of claim 1 , wherein the p-type doped region comprises a Group II element.5. The HEMT of claim 1 , wherein the p-type doped region comprises magnesium claim 1 , calcium claim 1 , beryllium or zinc.6. The HEMT of claim 1 , wherein the source feature and the drain feature comprise Ti claim 1 , Co claim 1 , Ni claim 1 , W claim 1 , Pt claim 1 , Ta claim 1 , Pd claim 1 , Mo claim 1 , Al or TiN.7. The HEMT of further comprising a carrier channel located in the first III-V compound layer along an interface between the first III-V compound layer and the ...

PROBE CARD AND MANUFACTURING METHOD THEREOF

A probe card for being abutted against a plurality of probes is provided. The probe card includes a substrate, at least two IC boards, and a plurality of probe pads. The IC boards are located on the substrate, and a predetermined distance is formed between the IC boards. Each of the IC boards has a plurality of lead connection points. The probe pads are plated on the IC boards, and are respectively connected to the lead connection points to cover the lead connection points. A probe area is surrounded by the probe pads on each of the IC boards. The probe pads are used to abut against the probes. In addition, a method of manufacturing the probe card is provided. 1. A probe card for being abutted against a plurality of probes , the probe card comprising:a substrate;at least two IC boards located on the substrate and having a predetermined distance between the two IC boards, and each of the two IC boards having a plurality of lead connection points; anda plurality of probe pads plated on the two IC boards and respectively connected to the lead connection points to cover the lead connection points, wherein a probe area is surrounded by the probe pads on each of the IC boards, the probe pads are for respectively being abutted against the probes, and a gap between the two probe areas of the two adjacent IC boards is larger than a width of each of the two probe areas.2. The probe card of claim 1 , wherein the gap between the two probe areas of the two adjacent IC boards is twice larger than the width of each of the two probe areas.3. The probe card of claim 1 , wherein the gap between the two probe areas of the two adjacent IC boards is smaller than or equal to 40 μm.4. The probe card of claim 1 , wherein a thickness of each of the probe pads is larger than or equal to 10 μm.5. The probe card of claim 1 , wherein the substrate comprises a printed circuit board having a circuit layout claim 1 , and the lead connection points of the two IC boards are electrically connected to ...

Combining structure for shelves

A combining structure for shelves has a plurality of bearing portions, connecting rods integrally connected to the periphery of each bearing portion, and each connecting rod extends toward the storage space to form at least one joining end. Multiple vertical supporting tubes are provided having a circumferential wall and two abutting ends, wherein, on the circumferential wall of each vertical supporting tube near the abutting end, at least one avoiding groove is provided. Tubular connectors are provided inside each vertical supporting tube. At least one eccentric socket slot is vertically formed on at least one unilateral position inside each tubular connector, and corresponds to the avoiding groove of the vertical supporting tube, so that the vertical supporting tube can sheathe the joining end of the connecting rod through the eccentric socket slot of the tubular connector, and through the avoiding groove, each vertical supporting tubes can avoid the bearing portion.

ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE

Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. 1. A method for forming an isolation trench through a backside surface of a substrate , comprising:applying a pattern mask to a backside surface of a substrate, the substrate comprising a front side surface over which one or more devices are formed;performing a wet etch to form a tapered portion of an isolation trench within the substrate; andperforming a dry etch to form a non-tapered portion of the isolation trench within the substrate, the non-tapered portion having a non-tapered width that is less than a tapered width of the tapered portion.2. The method of claim 1 , the wet etch performed before the dry etch.3. The method of claim 1 , the performing a wet etch comprising applying an acid base corresponding to at least one of a hydrofluoric nitric acetic (HNA) mixture claim 1 , a hydrofluoric acid-hydrogen peroxide mixture (FPM) mixture claim 1 , or a hydrofluoric acid-ozone mixture (FOM) mixture.4. The method of claim 1 , the performing a wet etch comprising applying an alkali base corresponding to at least one of ammonium hydroxide claim 1 , tetramethylammonium hydroxide claim 1 , or ...

TRANSISTOR HAVING A BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME

A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer. 1. A transistor comprising:a substrate;a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants;a channel layer on the buffer layer;a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer, wherein the back-barrier layer has a band gap discontinuity with the channel layer;an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer, and the active layer has a first width smaller than a second width of the channel layer; anda two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.2. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum nitride (AlN).3. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum gallium nitride (AlGaN).4. The transistor of claim 3 , wherein x ranges from about 0.1 to about 0.9.5. The transistor of claim 1 , wherein the back-barrier layer comprises indium aluminum nitride (InAlN).6. The transistor of claim 5 , wherein y is equal to or greater than 0.5.7. The transistor of claim 1 , wherein a dopant concentration of the p-type dopants ...

Transistor having high breakdown voltage and method of making the same

A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×10 19 ions/cm 3 . The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.

TRANSISTOR HAVING BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME

A transistor includes a substrate, a channel layer over the substrate, a back-barrier layer over the channel layer, and an active layer over the back-barrier layer. The back-barrier layer has a band gap discontinuity with the channel layer. The band gap of the active layer is less than the band gap of the back-barrier layer. A two dimensional electron gas (2-DEG) is formed in the channel layer adjacent an interface between the channel layer and the back-barrier layer. 1. A transistor comprising:a substrate;a channel layer over the substrate;a back-barrier layer over the channel layer, the back-barrier layer having a band gap discontinuity with the channel layer;an active layer over the back-barrier layer, a band gap of the active layer being less than the band gap of the back-barrier layer;a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the back-barrier layer; anda source electrode and a drain electrode over the channel layer, wherein a portion of at least one of the source electrode or the drain electrode is embedded in the channel layer.2. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum nitride (AlN).3. The transistor of claim 1 , wherein a band gap of the back-barrier layer is at least 0.5 electron volt (eV) greater than a band gap of the active layer.4. The transistor of claim 1 , wherein a band gap of the back-barrier layer is about 1.8 eV greater than a band gap of the active layer.5. The transistor of claim 1 , further comprising a nucleation layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the nucleation layer comprises:a first seed layer having a first lattice structure; anda second seed layer on the first seed layer, the second seed layer having a second lattice structure different from the first lattice structure.7. The transistor of claim 1 , further comprising a buffer layer between the substrate and the channel layer.8. ...

TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME

A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon. 19-. (canceled)10. A method of forming a transistor , comprising:forming a channel layer over a first substrate, the first substrate having a first thickness;forming an active structure over the channel layer, the active structure being configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure;forming a gate electrode over the channel layer;forming a drain electrode over the channel layer;converting the first substrate to a second substrate, the second substrate having a second thickness less than the first thickness;removing a portion of the second substrate to form an opening, the opening being directly under a first space defined between the gate electrode and the drain electrode; andfilling the opening with a material having an electrical conductivity value lower than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon.11. The method of claim 10 , wherein the material comprises aluminum nitride (AlN) or silicon carbide (SiC).12. The method of claim 10 , further comprising:forming an interconnection structure over the active structure;mounting a supporting substrate ...

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type. 1. A semiconductor structure comprising:a substrate;a nucleation layer over the substrate;a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type; a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and', 'an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type; and', 'a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type., 'one or more sets of III-V layers over the first III-V layer, each set of the one or more sets of III-V layers comprising2. The semiconductor structure of claim 1 , further comprising a dielectric layer over the second III-V layer.3. The semiconductor structure of claim 2 , further comprising an active layer between the dielectric layer and the second III-V layer.4. The semiconductor structure of claim 2 , further comprising a gate electrode over the dielectric layer.5. The semiconductor structure of claim 1 , further comprising a pair of source/drain (S/D) electrodes claim 1 , wherein each of the pair of S/D electrodes directly contacts the second III-V layer.6. ...

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer. 1. A semiconductor structure comprising:a substrate;a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers;an active layer over the buffer layer; anda dielectric layer over the active layer.2. The semiconductor structure of claim 1 , further comprising a channel layer between the buffer layer and the active layer.3. The semiconductor structure of claim 2 , further comprising a source electrode directly contacting the channel layer.4. The semiconductor structure of claim 1 , wherein at least one of plurality of III-V layers comprises GaN.5. The semiconductor structure of claim 1 , further comprising a nucleation layer between the substrate and the buffer layer.6. The semiconductor structure of claim 5 , wherein the nucleation layer comprises AlN.7. The semiconductor structure of claim 5 , wherein the nucleation layer is configured to reduce lattice mismatch between the substrate and the buffer layer.8. The semiconductor structure of claim 1 , wherein the buffer layer directly contacts the substrate.9. A method of forming a semiconductor structure claim 1 , the method comprising:forming a nucleation layer over a substrate;growing a buffer layer over the nucleation layer, wherein growing the buffer layer comprises growing a plurality of pairs of layers, each pair of ...

Assembly method of direct-docking probing device

An assembly method of direct-docking probing device is provided. First, a space transforming plate made by back-end-of-line semiconductor manufacturing process is provided, so the thickness of the space transforming plate is predetermined by the client of probe card manufacturer. Then a reinforcing plate in which a plurality of circuits disposed is provided, which has larger mechanical strength than the space transforming plate. After that the reinforcing plate and the space transforming plate are joined and electrically connected by a plurality of solders so as to form a space transformer. Then, a conductive elastic member and a probe interface board are provided. Thereafter, the space transformer and the conductive elastic member are mounted on the probe interface board. After that, at least one vertical probe assembly having a plurality of vertical probes is mounted on the space transforming plate, and the vertical probes is electrically connected with the space transforming plate.

SEMICONDUCTOR DEVICE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF MANUFACTURING

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer. 1. A semiconductor device , comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, the active layer configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; anda barrier structure between the substrate and the channel layer, the barrier structure configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.2. The semiconductor device of claim 1 , further comprising:a buffer layer between the substrate and the channel layer, the buffer layer having a higher resistivity than a resistivity of the channel layer.3. The semiconductor device of claim 2 , wherein the barrier structure comprises a first barrier layer between the substrate and the buffer layer claim 2 , the first barrier layer configured to block diffusion of the material of the substrate to the buffer layer.4. The semiconductor device of claim 3 , wherein the barrier structure comprises a second barrier layer between the buffer layer and the channel layer claim 3 , the second barrier layer configured to block diffusion of the dopant from the buffer layer to the channel layer.5. The semiconductor device of claim 4 , wherein at least one of the first barrier layer or the second barrier layer comprises at least one material selected from the group consisting of SiC claim 4 , SiCNand BN.6. The semiconductor device of ...

SEMICONDUCTOR DEVICE HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer. 1. A semiconductor device comprising:a doped substrate; a first seed sublayer having a first lattice structure, wherein the first seed layer comprises AlN, and the first seed layer is doped with carbon, and', 'a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure;, 'a seed layer in direct contact with the substrate, wherein the seed layer comprises a first graded sublayer including AlGaN, wherein the first graded sublayer has a first Al:Ga ratio;', 'a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN, and the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and', 'a third graded sublayer over the second graded sublayer, wherein the third graded sub layer includes AlGaN, and the third graded sublayer has a third Al:Ga ratio different from the second Al:Ga ratio;, 'a graded layer in direct contact with the seed layer, wherein the graded layer comprisesa channel layer ...

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) HAVING AN INDIUM-CONTAINING LAYER AND METHOD OF MANUFACTURING THE SAME

A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain. 1. A high electron mobility transistor (HEMT) comprising:a substrate;a first semiconductor layer over the substrate;a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium;a top layer over the second semiconductor layer;a metal layer over and extending into the top layer, wherein the top layer separates the metal layer from the second semiconductor layer;a gate electrode over the top layer;a third semiconductor layer between the gate electrode and the top layer, wherein a sidewall of the third semiconductor layer is separated from a sidewall of the metal layer; anda source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.2. The HEMT of claim 1 , wherein the first semiconductor layer comprises an InGaN material.3. The HEMT of ...

TRANSISTOR HAVING AN OHMIC CONTACT BY SCREEN LAYER AND METHOD OF MAKING THE SAME

A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer. 1. A transistor comprising:a substrate;a channel layer over the substrate; a first portion;', 'a screen layer over the first portion; and', 'an interface layer over the first portion, wherein the interface layer comprises n-doped gallium nitride (n-GaN); and, 'an active layer over the channel layer, wherein the active layer comprisesa metal layer over the screen layer.2. The transistor of claim 1 , wherein the screen layer comprises aluminum nitride (AlN).3. The transistor of claim 2 , wherein a thickness of the screen layer is less than or equal to 3 angstroms (Å).4. The transistor of claim 2 , wherein the first portion comprises aluminum gallium nitride (AlGaN).5. The transistor of claim 1 , further comprising:a buffer layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the buffer layer comprises:a first aluminum gallium nitride layer having a first aluminum concentration;a second aluminum gallium nitride layer having a second aluminum concentration less than the first aluminum concentration; anda third aluminum gallium nitride layer having a third aluminum concentration less than the second aluminum concentration.7. The transistor of claim 1 , further comprising a nucleation layer between the substrate and the channel layer claim 1 , wherein the nucleation layer comprises:a first seed layer having a first lattice structure; anda second seed layer on the first seed layer, the second seed layer having a second lattice structure different from the first lattice structure.8. (canceled)9. The transistor of claim 1 , further comprising:a first electrode on the active layer, wherein the first electrode forms an ohmic contact with the first portion;a second electrode on the ...

TRANSISTOR HAVING AN OHMIC CONTACT BY GRADIENT LAYER AND METHOD OF MAKING THE SAME

A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration. 1. A transistor comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, wherein the active layer comprises a gradient layer having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration, wherein the first concentration steadily decreases from the first value at the interface to the second value at the surface opposite the channel layer.2. The transistor of claim 1 , wherein the gradient layer comprises aluminum gallium nitride (AlGaN) claim 1 , and the first material comprises aluminum.3. The transistor of claim 2 , wherein the first concentration y ranges from about 0.2 to about 0.3 claim 2 , and the second concentration y ranges from about 0.1 to about 0.4. The transistor of claim 2 , wherein y gradually decreases from a maximum value at the interface with the channel layer to a minimum value at the surface opposite the channel layer.5. The transistor of claim 1 , further comprising:a buffer layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the buffer layer comprises:a first aluminum gallium nitride layer having a first aluminum concentration;a second aluminum gallium nitride layer having a second aluminum concentration less than the first aluminum concentration; anda third aluminum gallium nitride layer having a third aluminum concentration less than the second aluminum concentration.7. The transistor of claim 1 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer. 1. A semiconductor device , comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, the active layer configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer;a gate structure over the active layer, the gate structure configured to deplete the 2DEG under the gate structure, the gate structure comprising a dopant; anda barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.2. The semiconductor device of claim 1 , wherein the barrier layer is configured to further deplete the 2DEG under the gate structure and partially deplete the 2DEG in a region surrounding the gate structure.3. The semiconductor device of claim 1 , whereinthe semiconductor device comprises a source region, a drain region, and a gate region corresponding to the gate structure,the barrier layer is continuous in the gate region, andthe barrier layer is discontinuous between (i) the gate region and (ii) at least one of the source region or the drain region.4. The semiconductor device of claim 3 , wherein claim 3 , between (i) the gate region and (ii) the at least one of the source region or the drain region claim 3 , the ...

LOCK STRUCTURE

A lock structure includes a first mounting plate and a positioning ring. The first mounting plate comprises a bottom plate and a plurality of fixing holes. The positioning ring comprises a ring body, an opening and a plurality of positioning members, and each of the positioning members comprises a positioning barrel having a body and a penetration hole. Each of the penetration holes is surrounded by each of the bodies. Each of the penetration holes corresponds to each of the fixing holes to make a fixing member passing through the fixing hole and fixedly secured at a positioning rod via guidance of each of the penetration holes. Therefore, the difficulty of assembly caused by the reason the fixing member is unable to align with the positioning member is eliminated. 1. A lock structure includes:a first mounting plate having a bottom plate and a plurality of fixing holes penetrating the bottom plate; anda positioning ring having a ring body, an opening and a plurality of positioning members, the opening is surrounded by the ring body, each of the positioning members comprises a positioning barrel having a body and a penetration hole surrounded by the body, each of the penetration holes corresponds to each of the fixing holes of the first mounting plate, each of the penetration holes is revealed by each of the fixing holes.2. The lock structure in accordance with claim 1 , wherein each of the positioning members comprises a connection rib claim 1 , one end of each of the connection ribs connects to the ring body claim 1 , and the other end of each of the connection ribs connects to each of the bodies.3. The lock structure in accordance with claim 2 , wherein the connection rib extends toward a center line of the ring body.4. The lock structure in accordance with claim 1 , wherein the first mounting plate comprises a lateral wall formed on the bottom plate claim 1 , the positioning ring comprises a plurality of protrusions formed at the ring body claim 1 , each of the ...

HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER

A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact. 1. A semiconductor device comprising:a substrate;a first layer comprising aluminum nitride over the substrate;a second layer comprising aluminum gallium nitride over the first layer;a third layer comprising indium gallium nitride over the second layer, the third layer having a first portion and a second portion, the first portion of the third layer being separated from the second portion of the third layer;a first blended region beneath the first portion of the third layer, the first blended region comprising aluminum atoms drawn from the first layer into at least the second layer;a second blended region beneath the second portion of the third layer, the second blended region comprising aluminum atoms drawn from the first layer into at least the second layer;a source contact over the first portion of the third layer; anda drain contact over the second portion of the third layer.2. The semiconductor device of claim 1 , wherein the third layer comprises between about 5% and about 20% indium.3. The semiconductor device of claim 1 , wherein the first layer is over at least one layer having 0% aluminum content.4. The semiconductor device of claim 1 , wherein the ...

DOPED BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON

Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact. 1. A semiconductor device comprising:a substrate;a seed buffer layer overlying and directly contacting the substrate, wherein the seed buffer layer comprises a group III-V material that is doped and at an interface at which the substrate and the seed buffer layer directly contact;a heterojunction structure overlying the seed buffer layer;a pair of source/drain electrodes overlying the heterojunction structure; anda gate electrode overlying the heterojunction structure, laterally between the source/drain electrodes.2. The semiconductor device according to claim 1 , wherein the seed buffer layer comprises a group III nitride claim 1 , and wherein the substrate and the seed buffer layer are doped with same doping type.3. The semiconductor device according to claim 1 , wherein the seed buffer layer comprises aluminum nitride.4. The semiconductor device according to claim 1 , wherein the seed buffer layer is p-type.5. The semiconductor device according to claim 1 , wherein the seed buffer layer has a doping ...

METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR

A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature. 1. A method of forming a high electron mobility transistor (HEMT) , the method comprising:forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition;forming a p-type doped region in the first III-V compound layer;forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region;forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; andforming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.2. The method of claim 1 , wherein the forming the second III-V compound layer on the first III-V compound layer comprises epitaxially growing the second III-V compound layer on the first III-V compound layer.3. The method of claim 1 , wherein the forming the p-type doped region comprises selectively implanting p-type dopants into the first III-V compound layer through the second first III-V compound layer.4. The method of claim 3 , wherein the p-type dopants comprise a Group II element.5. The method of claim 3 , wherein the p-type dopants comprise magnesium claim 3 , calcium claim 3 , beryllium or zinc.6. The method of ...

CABLE CONNECTOR ASSEMBLY HAVING AN ILLUMINATION FUNCTION

A cable connector assembly includes a cable and a connector electrically connected with the cable for further electrically connecting with a power source. The connector includes: a main body; a plurality of contacts retained to the main body; a light emitting element; a first printed circuit board for controlling the light emitting element to emit light; and an outer case enclosing the connector and defining a conductive area; wherein the connector further includes a conducting member mounted on the first printed circuit board, the conducting member is a shrapnel made of metal material pressing upon the conductive area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the conductive area the light emitting element is turned on to emit light through the transparent portion. 1. A cable connector assembly comprising:a cable; and a main body;', 'a plurality of contacts retained to the main body;', 'a light emitting element;', 'a first printed circuit board for controlling the light emitting element to emit light; and', 'an outer case enclosing the connector and defining a conductive area; wherein, 'a connector electrically connected with the cable for further electrically connecting with a power source, the connector includingthe connector further includes a conducting member mounted on the first printed circuit board, the conducting member is a shrapnel made of metal material pressing upon the conductive area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the conductive area the light emitting element is turned on to emit light through the transparent portion.2. The cable connector assembly as described in claim 1 , wherein the connector comprises a second printed circuit board parallel to the first printed circuit board and electrically connected between the contacts of the connector and the cable.3. The cable ...

SEMICONDUCTOR DEVICE HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. 1. A semiconductor device comprising:a substrate having a substrate lattice structure; an AlN first seed sublayer having a first lattice structure, and', 'an AlN second seed sublayer having a second lattice structure, the second lattice structure being different than the first lattice structure, wherein a portion of the AlN seed layer closest to the substrate comprises carbon dopants and has a different lattice structure from the substrate lattice structure;, 'an AlN seed layer in direct contact with the substrate, the AlN seed layer comprising a first graded sublayer including AlGaN, wherein the first graded sublayer has a first Al:Ga ratio;', 'a second graded sublayer including AlGaN, wherein the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and', 'a third graded sublayer including AlGaN, wherein the third graded sublayer has a third Al:Ga ratio different from each of the first Al:Ga ratio and the second Al:Ga ratio;, 'a graded layer in direct contact with the AlN seed layer, wherein the graded layer comprisesa channel layer over the graded layer; andan active layer over the channel ...

High Electron Mobility Transistor and Method of Forming the Same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode. 1. A method of forming a High Electron Mobility Transistor (HEMT) , the method comprising:epitaxially growing a first III-V compound layer having a first band gap;epitaxially growing a second III-V compound layer having a second band gap smaller than the first band gap over the first III-V compound layer;epitaxially growing a third III-V compound layer having a third band gap greater than the first band gap over the second III-V compound layer;forming a gate electrode over the third III-V compound layer; andforming a source region and a drain region over the third III-V compound layer and on opposite sides of the gate electrode.2. The method of claim 1 , wherein the second III-V compound layer is undoped or unintentionally doped during the step of epitaxially growing the second III-V compound layer.3. The method of further comprising:forming a dielectric passivation layer over and contacting the third III-V compound layer;patterning the dielectric passivation layer to form an opening, wherein a portion of the third III-V compound layer is exposed through the opening; anddepositing a gate dielectric layer, wherein the gate dielectric layer comprises a first portion extending into the opening, and a second portion overlapping the dielectric passivation layer.4. The method of claim 3 , wherein after the source region and the drain region are formed claim 3 , ...

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode. 1. A high electron mobility transistor (HEMT) comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition;a dielectric passivation layer disposed on the second III-V compound layer;a source feature and a drain feature disposed on the second III-V compound layer, and extending through the dielectric passivation layer;a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, the gate electrode having an exterior surface;an oxygen containing region embedded at least in the second III-V compound layer under the gate electrode; anda gate dielectric layer comprising a first portion and a second portion, wherein the first portion is under the gate electrode and on the oxygen containing region, and the second portion is on a portion of the exterior surface of the gate electrode.2. The HEMT of claim 1 , wherein the oxygen containing region is embedded in the second III-V compound layer and a ...

SIDEWALL PASSIVATION FOR HEMT DEVICES

Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer. 1. A high electron mobility transistor (HEMT) , comprising:a heterojunction structure arranged over a substrate, the heterojunction structure comprising: a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer and made of a material composition different from a material composition of the first III/V semiconductor layer;source and drain regions arranged over the substrate and spaced apart laterally from one another;a gate structure arranged over the heterojunction structure and arranged between the source and drain regions;a first passivation layer disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material; anda second passivation layer overlying the first passivation layer and made of a material composition different from a material composition of the first passivation layer;wherein the second passivation layer has a thickness greater than that of the first passivation layer.2. The HEMT of claim 1 , wherein the first passivation ...

High Electron Mobility Transistor and Method of Forming the Same

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

CABLE CONNECTOR ASSEMBLY WITH IMPROVED LUMINOUS EFFECT

A cable connector assembly () comprises: a first connector () having a main body (), a number of contacts () retained in the main body, a first circuit board () electrically connected to the contacts, and a metal shell () enclosing the first circuit board; a cable () electrically connected between the first circuit board and a power source to provide a power to the first circuit board; a second circuit board () vertically fixed on the metal shell; a cover enclosing the first and the second circuit board; a luminous element () disposed on a front side of the second circuit board and electrically connected to the first circuit board; and a translucent portion () defined on a front end of the cover to pass light emitted by the luminous element. 1. A cable connector assembly comprising:a first connector having a main body, a plurality of contacts retained in the main body, a first circuit board electrically connected to the contacts, and a metal shell enclosing the first circuit board;a cable electrically connected between the first circuit board and a power source to provide a power to the first circuit board;a second circuit board vertically fixed on the metal shell;a cover enclosing the first and the second circuit boards;a luminous element disposed on a front side of the second circuit board and electrically connected to the first circuit board; anda translucent portion defined on a front end of the cover to pass the light emitted by the luminous element.2. The cable connector assembly as recited in claim 1 , wherein the cover includes a tubular portion and a front plate portion fixed on a front end of the tubular portion claim 1 , and the translucent portion is defined on the front plate portion or forms the entire front plate portion.3. The cable connector assembly as recited in claim 2 , wherein:the tubular portion encloses the first circuit board, the main body, and the second circuit board;the cable is exposed from a rear opening of the tubular portion;the ...

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME

A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping. 1. A semiconductor structure , comprising:a substrate;a first III-V compound layer over the substrate, the first III-V compound layer having a first type doping;one or more sets of III-V compound layers over the first III-V compound layer, each of the one or more sets of III-V compound layers comprising a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer, the upper III-V compound layer having the first type doping, and the lower III-V compound layer being at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping;a second III-V compound layer over the one or more sets of III-V compound layers, the second III-V compound layer being either undoped or unintentionally doped having the second type doping; andan active layer over the second III-V compound layer.2. The semiconductor structure of claim 1 , wherein the first type doping is P-type doping claim 1 , and the second type doping is N-type doping.3. The semiconductor structure of claim 2 , wherein the first type doping is implemented by dopants including carbon claim 2 , ...

Thick ALN Inter-Layer for III-Nitride Layer on Silicon Substrate

The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device. 1. A gallium nitride (GaN) semiconductor device , comprising:a first gallium nitride (GaN) layer disposed above a semiconductor substrate;a first aluminum nitride (AlN) inter-layer disposed onto the first GaN layer;a second gallium nitride (GaN) layer disposed onto the first AlN inter-layer;an active layer disposed onto the second GaN layer;a source region abutting a top surface of the second GaN layer and further abutting a first sidewall of the active layer;a drain region abutting the top surface of the second GaN layer and further abutting a second sidewall of the active layer opposite the first sidewall; anda gate region located above the active layer at a position between the source region and the drain region.2. The GaN semiconductor device of claim 1 , further comprising:an aluminum nitride (AlN) nucleation layer disposed between the semiconductor substrate and the first GaN layer.3. The GaN semiconductor device of claim 2 , further comprising:a graded aluminum gallium nitride (AlGaN) layer disposed between the AlN nucleation layer and the first GaN layer, wherein the graded AlGaN layer has an aluminum concentration that varies as a function of position.4. The GaN semiconductor device of claim 1 , further comprising:a second aluminum nitride (AlN) inter-layer disposed onto the second gallium nitride (GaN) layer; anda third gallium nitride (GaN) ...

METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material. 1. A method of forming a semiconductor device , the method comprising:forming a III-V compound layer on a substrate;implanting a main dopant into the III-V compound layer to form source and drain regions; andimplanting a group V species within the source and drain regions.2. The method of claim 1 , further comprising performing an annealing process to activate the combination of dopants and group V species in the source and drain regions.3. The method of claim 2 , wherein performing the annealing process comprises performing the annealing process at a temperature ranging from about 800° C. to about 1200° C.4. The method of claim 1 , wherein implanting the main dopants comprises implanting at least one of silicon claim 1 , magnesium claim 1 , beryllium claim 1 , calcium claim 1 , zinc claim 1 , germanium or sulfur.5. The method of claim 1 , wherein implanting the group V species comprises implanting the group V species in a ratio of the main dopants to the group V species ranging from about 1 claim 1 ,000:1 to about 10:1.6. The method of claim 1 , further comprising forming source and drain contacts electrically connected to the source and drain regions.7. The method of claim 6 , wherein forming the source and drain contacts comprises forming an ohmic contact with the source and drain regions.8. The method of claim 1 , further comprising:forming a capping layer over the source and drain regions; andforming a gate ...

High Electron Mobility Transistor Structure

The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides. 18-. (canceled)9. A high electron mobility transistor (HEMT) , comprising:a first breakdown voltage layer comprising a first resistivity value, wherein the first breakdown voltage layer exhibits a first lattice-constant and is doped with a first dopant at a first doping concentration;a second breakdown voltage layer disposed beneath the first breakdown voltage layer and comprising a second resistivity value that is greater than, the first resistivity value, wherein the second breakdown voltage layer exhibits a second lattice-constant that is substantially equal to the first lattice-constant and is doped with a second dopant at a second doping concentration that is greater than the first doping concentration; anda crystal adaptation layer disposed beneath the second breakdown voltage layer, wherein the crystal adaptation layer exhibits a third lattice-constant which is substantially equal to each of the first and second lattice-constants; and wherein the crystal adaptation layer is doped with a third dopant at a third doping ...

WAFER TESTING PROBE CARD

A wafer testing probe card includes a printed circuit board, a flexible circuit board, an elastic piece, and a probe unit. The flexible circuit board is electrically connected to the printed circuit board. The elastic piece is disposed between the printed circuit board and the flexible circuit board. The probe unit includes a probe head and a plurality of probes. The probe head is fixed on the printed circuit board and has a plurality of through holes. The probes respectively pass through the through holes and move up and down relative to the probe head. 1. A wafer testing probe card , comprising:a printed circuit board;a flexible circuit board electrically connected to the printed circuit board;an elastic piece disposed between the printed circuit board and the flexible circuit board; and a probe head fixed on the printed circuit board and having a plurality of through holes; and', 'a plurality of probes respectively passing trough the through holes, wherein the probes move up and down relative to the probe head., 'a probe unit, comprising2. The wafer testing probe card of claim 1 , wherein lengths of the probes are the same.3. The wafer testing probe card of claim 1 , wherein lengths of the probes gradually increase from a periphery of the elastic piece to a center of the elastic piece.4. The wafer testing probe card of claim 1 , wherein a thickness of the elastic piece gradually increases from a periphery of the elastic piece to a center of the elastic piece.5. The wafer testing probe card of claim 1 , wherein the probe head comprises a holder and a plurality of screws claim 1 , wherein the holder is fixed to the printed circuit board by the screws.6. The wafer testing probe card of claim 1 , wherein the probe head comprises an insulated substrate having the through holes.7. The wafer testing probe card of claim 6 , wherein each of the probes comprises a probe body and a stopper connected to one end of the probe body claim 6 , wherein the stopper is disposed ...

LASER POINTER

A laser pointer includes a case (), a laser module (), a printed circuit board assembly () and a charging connector (). The case () includes a lighting end () at a front end thereof, a mounting port () at a rear end thereof, a receiving cavity between the lighting end and the mounting port, and an inner wall (). The laser module () and the printed circuit board assembly () are received in the receiving cavity (). The printed circuit board assembly connects with the rear side of the laser module (). The charging connector () mounted on the rear end of the printed circuit board assembly () electrically connects to the laser module () through the printed circuit board assembly (). 1. A laser pointer comprising:a case including a lighting end at a front end thereof, a mounting port at a rear end thereof, a receiving cavity between the lighting end and the mounting port, and an inner wall;a laser module received in the receiving cavity;a printed circuit board assembly received in the receiving cavity and connecting to the rear side of the laser module; anda charging connector mounted on the rear end of the printed circuit board assembly; whereinthe charging connector electrically connects to the laser module through the printed circuit board assembly and is adapted to supply an external power to the laser module.2. The laser pointer as claimed in claim 1 , wherein the laser pointer includes a touch sensing plate located between the inner wall and the printed circuit board assembly.3. The laser pointer as claimed in claim 2 , wherein the touch sensing plate includes a main board claim 2 , a contact plate upwardly extending from the main board claim 2 , and a plurality of connection pins downwardly extending from the main board claim 2 , the contact plate being curved and fitting the inner wall claim 2 , the plurality of connection pin being fixedly connected with the printed circuit board assembly.4. The laser pointer as claimed in claim 2 , wherein the printed circuit ...

WIRE-WINDING DEVICE

A wire-winding device comprising: an upper cover; a spiral spring; a rotary base having a groove to accommodate the spiral spring on the bottom surface thereof; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and a pillar, an outlet, and a wire casing formed on one side of the groove, and two spacers surrounding the peripheral edge of the groove, the pillar having a first end portion which shifts outward to the edge of rotary base, the wire casing having a smooth curved surface formed on the bottom surface thereof near the outlet to enlarge the accommodating space near the outlet and reduce the friction between the transmission line and the spacers. 1. A wire-winding device comprising:an upper cover;a spiral spring;a rotary base having a groove to accommodate the spiral spring on the bottom surface thereof;a transmission line winding around the rotary base;a lower cover assembled with the upper cover; anda pillar, an outlet, and a wire casing formed on one side of the groove, and two spacers surrounding the peripheral edge of the groove, the pillar having a first end portion which shifts outward to the edge of rotary base, the wire casing having a smooth curved surface formed on the bottom surface thereof near the outlet to enlarge the accommodating space near the outlet and reduce the friction between the transmission line and the spacers.2. The wire-winding device as claimed in claim 1 , further having a decorative piece claim 1 , and wherein the upper cover has a circular groove formed on the upper surface claim 1 , and the decorative piece is accommodated in the circular groove of the upper cover.3. The wire-winding device as claimed in claim 1 , wherein the wire-winding device further having an elastic positioning element having a base and a positioning part extruding from the lower surface of the base claim 1 , the base having an elastic part and a respective fixed part at each of two ends thereof claim 1 , the ...

WIRE-WINDING DEVICE

A wire-winding device comprising: an upper cover having a bottom surface and a slot deviating from a center of the bottom surface; a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit; a spiral spring received in the rotary base; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and an elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base to avoid the transmission line to be tied a knot. 1. A wire-winding device comprising:an upper cover having a bottom surface and a slot deviating from a center of the bottom surface;a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit;a spiral spring received in the rotary base;a transmission line winding around the rotary base;a lower cover assembled with the upper cover; andan elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base.2. The wire-winding device as claimed in claim 1 , wherein the base of the elastic positioning element is accommodated in the slot of the lower surface of the upper cover claim 1 , and the positioning part of the elastic positioning element is accommodated in the annual track of the rotary base.3. The wire-winding device as claimed in claim 1 , wherein the rotary base has a groove on the lower surface thereof for accommodating the spiral spring claim 1 , the groove having a ...

CABLE CONNECTOR ASSEMBLY WITH IMPROVED INDICATION EFFECT

A cable connector assembly () includes: a cable () having a number of inner wires; a first connector () including a main body (), plural contacts () retained in the main body, a first circuit board (), a luminous element (), and a cover; and a second circuit board () assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board. The second circuit board includes a detection contact () electrically connected to an inner wire of the cable, and a chip () electrically connected respectively to the luminous element and the detection contact. The chip detects a voltage difference between the power source and the first connector. A light is emitted by the luminous element passing through the cover to indicate a charging status of the charging device. 1. A cable connector assembly comprising:a cable having a number of inner wires, a end of the cable adapted to connect to a power source for receiving a power signal and a grounding signal;a first connector including a main body, a plurality of contacts retained in the main body, a first circuit board assembled on a rear end of the main body and electrically connected with the contacts and the cable, a luminous element, and a cover enclosing the main body and the first circuit board; anda second circuit board assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board, the second circuit board comprising a chip and a detection contact, the detection contact electrically connected to an inner wire of the cable, the chip electrically connected respectively to the luminous element and the detection contact, the chip detecting a voltage difference between the power source and the first connector when mating with a charging device and changing a lighting mode of the luminous element according to the voltage difference, a light emitted by the luminous element passing through the cover to indicate a charging status of ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED MANUFACTURING METHOD

A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other. 1. A semiconductor structure , comprising:a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side;a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side;a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; anda transparent filling over the first LED layer, the second LED layer and the third LED layer, wherein a distance between a top surface of the transparent filling and the second side of the first LED layer is greater than a distance between the top surface of the transparent filling and the second side of the second LED layer, and the distance between the top surface of the transparent filling and the second side of the second LED layer is greater than a distance between the top surface of the transparent filling and the second side of the third LED layer;wherein the first color type, the second color type, ...

High Electron Mobility Transistor and Method of Forming the Same

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode. 1. A method of forming a transistor , the method comprising:epitaxially growing a second semiconductor layer on a first semiconductor layer;forming a dielectric layer on the second semiconductor layer, a first portion of the second semiconductor layer being exposed;oxidizing the first portion of the second semiconductor layer, thereby forming an oxidized portion of the second semiconductor layer;depositing a gate dielectric layer on the oxidized portion of the second semiconductor layer;forming a gate electrode on the gate dielectric layer and over the oxidized portion of the second semiconductor layer; andafter forming the gate electrode, forming a source feature and a drain feature on the second semiconductor layer, the source feature and the drain feature extending through the dielectric layer to the second semiconductor layer.2. The method of claim 1 , wherein the first semiconductor layer is a first III-V compound.3. The method of claim 2 , wherein the second semiconductor layer is a second III-V compound.4. The method of claim 1 , wherein the gate ...

Method of Implanting Dopants into a Group III-Nitride Structure and Device Formed

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material. 1. A method comprising:depositing a first III-V compound layer on a substrate;depositing a second III-V compound layer over the first III-V compound layer, the second III-V compound layer having a higher bandgap than the first III-V compound layer; andimplanting a first dopants and a group V species into the first III-V compound layer and the second III-V compound layer to define a source/drain region extending through the second III-V compound layer into the first III-V compound layer, wherein a region of the source/drain region below a bottommost surface of the second III-V compound layer comprises the group V species.2. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises simultaneously implanting the first dopants and the group V species.3. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants before implanting the group V species.4. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants after implanting the group V species.5. The method of further comprising performing an annealing process to activate the first dopants ...

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. 1. A semiconductor structure comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;a source feature and a drain feature disposed on the second III-V compound layer;a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode;a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer; anda gate dielectric layer disposed over portions of the second III-V compound layer and over an entire top surface of the third III-V compound layer.2. The semiconductor structure of claim 1 , wherein the carrier channel under the gate electrode comprises a depletion region.3. The semiconductor ...

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon () surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method of fabricating a semiconductor device , comprising:{'b': '111', 'providing a silicon substrate having opposite first and second sides, at least one of the first and second sides including a silicon () surface;'}forming a first high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate, the first high CTE layer having a CTE greater than a CTE of silicon;forming a buffer layer over the second side of the silicon substrate, the buffer layer having a CTE greater than the CTE of silicon;forming a second high CTE layer over the second side of the silicon substrate, the second high CTE layer having a CTE greater than the CTE of silicon;removing the second high CTE layer; andafter removing the second high CTE layer, forming a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer.2. The method of claim 1 , wherein:the forming the high CTE layer is carried out in a manner so that the first high CTE layer includes a material selected from the group consisting of: silicon nitride, doped glass, and silicon carbide; andthe forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.3. The method of claim 1 , ...

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE STRUCTURE

A high electron mobility transistor (HEMT) device structure is provided. The HEMT device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The HEMT device structure also includes a gate structure formed over the active layer, and the gate structure includes: a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-GaN) layer formed over the active layer, and a portion of the p-GaN layer or p-AlGaN layer has a stepwise or gradient doping concentration. The HEMT device structure also includes a gate electrode over the p-GaN layer or p-AlGaN layer. 1. A high electron mobility transistor (HEMT) device structure , comprising:a channel layer formed over a substrate;an active layer formed over the channel layer; and 'a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-AlGaN) layer formed over the active layer, wherein a portion of the p-GaN layer or a portion of the p-AlGaN layer has a stepwise or gradient doping concentration, and the other portion of the p-GaN layer or the p-AlGaN layer has a constant concentration, and the constant concentration is higher than the gradient doping concentration; and a gate electrode over the p-GaN layer or the p-AlGaN layer.', 'a gate structure formed over the active layer, wherein the gate structure comprises2. The high electron mobility transistor (HEMT) device structure as claimed in claim 1 , wherein the gate structure further comprises:a n-doped gallium nitride (n-GaN) layer between the p-GaN layer or the p-AlGaN layer and the gate electrode.3. (canceled)4. The high electron mobility transistor (HEMT) device structure as claimed in claim 1 , wherein the gradient doping concentration is gradually decreased from a bottom surface of the p-GaN layer to a top surface of the p-GaN layer claim 1 , or a bottom surface of the p-AlGaN layer to a top surface of the p-AlGaN layer.5. The high electron mobility transistor (HEMT) device ...

MANUFACTURING METHOD OF PROBING DEVICE

A manufacturing method of a probing device is provided. The manufacturing method includes following steps. First, a plurality of space transformers is disposed on a reinforcing plate and the space transformer includes a plurality of first pads. Then, the space transformer is fixed on the reinforcing plate. Thereafter, photoresist films having a plurality of openings are formed on the space transformer. The first pads are disposed in the openings. After that, a metal layer is formed and covered on the first pad. Later, the photoresist film is removed and the metal layer planarized to form a second pad. Afterwards, the reinforcing plate is electrically connected with a PCB. Thereafter, a probe head having a plurality of probing area is provided and each probing area is corresponding to one of the space transformer. The probes in the probing area are electrically connected with the internal circuitry of the space transformer. 1. A manufacturing method for a probing device comprising:providing a reinforcing plate;disposing a plurality of space transformers on the reinforcing plate, wherein a plurality of first pads are disposed on a surface of each space transformer;fixing the space transformer on the reinforcing plate, for configuring the internal circuitry of the space transformer to be electrically connected to the internal circuitry of the reinforcing plate;forming a photoresist film on the space transformer, wherein the photoresist film comprises a plurality of openings and at least a portion of the first pad is disposed in the opening;forming a metal layer in each of the plurality of openings, wherein the metal layer is disposed on and is directly contacted with the plurality of first pads for forming a plurality of second pads;providing a printed circuit board and electrically connecting the internal circuitry of the reinforcing plate to the internal circuitry of the printed circuit board; andproviding a probe head, the probe head comprising a plurality of ...

WIRELESS CHARGER HAVING MOVEABLE TRANSIMITTER COIL

A wireless charger used for charging a portable electronic device with a receiver coil includes a wireless charging body, a transmitter coil, and a shaft. The charging body has a front body to support the portable electronic device and a rear body coordinated with the front body to form a receiving cavity for receiving transmitter coil. The rear body defines a track for the shaft disposing therein and moving the transmitter coil to align with the receiver coil. The wireless charger could align with receiver coils of different portable electronic devices. 1. A wireless charger used for charging a portable electronic device with a receiver coil , comprising:a wireless charging body having a front body to support said portable electronic device and a rear body coordinated with the front body to form a receiving cavity, said rear body defining a track;a transmitter coil received in the receiving cavity; anda shaft disposed within the track and connected with the transmitter coil, said shaft being moveable to align the transmitter coil with the receiver coil.2. The wireless charger claimed in claim 1 , wherein said rear body has an inner face and an outer face claim 1 , said track extend through the rear body along a direction perpendicular to the outer face claim 1 , and said track has a plurality of serrated structures for mating with the shaft.3. The wireless charger claimed in claim 2 , further including a moving tray connected between the transmitter coil and the shaft.4. The wireless charger claimed in claim 3 , wherein said transmitter coil has a planar magnetic core and a plurality of spiral coils retained thereon claim 3 , said planar magnetic core is retained to the moving tray claim 3 , and said shaft is engaged with the moving tray.5. The wireless charger claimed in claim 4 , wherein said shaft includes a disk-shaped main body claim 4 , a grip portion extending backwardly from the main body claim 4 , and a mating block extending forwardly from the main body ...

Wireless charger assembly mountable on different desks

A wireless charger assembly is used for transferring power to an electronic device through inductive charging. The wireless charger assembly includes a bottom case releasably mounted to an exterior flatbed, a transmitter coil, and a top case. The transmitter coil transmits power to a receiver coil of the electronic device through inductive charging. The top case has a working platform mounted around the working surface of the flatbed, a neck portion extending downwardly from the working platform, and a slot defined by the working platform and the neck portion. The neck portion releasably retained to the closed loop wall.

SEMICONDUCTOR STRUCTURE AND ASSOCIATED MANUFACTURING METHOD

A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other. 1. A method of manufacturing a semiconductor structure , comprising:receiving a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a bottom side and a top side opposite to the bottom;bonding a second LED layer to the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a bottom side and a top side opposite to the bottom side;bonding a third LED layer to the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a bottom side and a top side opposite to the bottom side; andapplying a transparent filling over the first LED layer, the second LED layer and the third LED layer, wherein a distance between a top surface of the transparent filling and the top side of the first LED layer is greater than a distance between the top surface of the transparent filling and the top side of the second LED layer, and the distance between the top surface of the transparent filling and the top side of the second LED layer is greater than a distance between the top surface of the transparent filling and the top side of the third LED layer;wherein the ...

SEMICONDUCTOR DEVICE, TRANSISTOR HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. 1. A semiconductor device comprising:a substrate;a seed layer over the substrate, wherein the seed layer comprises carbon dopants;a channel layer over the seed layer; andan active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.2. The semiconductor device of claim 1 , wherein a concentration of the carbon dopants ranges from about 2×10atoms/cmto about 1×10atoms/cm.3. The semiconductor device of claim 1 , further comprising a graded layer between the seed layer and the channel layer.4. The semiconductor device of claim 3 , wherein the graded layer comprises:{'sub': x', '1-x, 'a first graded layer including AlGaN, where x ranges from 0.7 to 0.9;'}{'sub': y', '1-y, 'a second graded layer on the first graded layer, the second graded layer including AlGaN, where y ranges from 0.4 to 0.6; and'}{'sub': z', '1-z, 'a third graded layer on the second graded layer, the third graded layer including AlGaN, where z ranges from 0.15 to 0.3.'}5. The semiconductor device of claim 1 , wherein a thickness of the first graded layer ranges from about 50 nanometers (nm) to about 200 nm.6. The semiconductor device of claim 4 , wherein a thickness of the second graded layer ranges from about 150 nm to about 250 nm.7 ...

CABLE CONNECTOR

A cable connector includes a first plug, a second plug opposite the first plug, a cable connected with the first plug and second plug, and a LED light located in the first plug or the second plug, wherein the cable is provided with a braid layer located at the outermost side of the cable, the braid layer is composed of metal enameled wire mixed fibers, and the cable causes the LED light to be illuminated by capacitive sensing through proximity. 1. A cable connector comprising:a first plug;a second plug opposite the first plug;a cable connected with the first plug and second plug; andan LED (Light Emitting Diode) light located in the first plug or the second plug, whereinthe cable is provided with a braid layer located at an outermost side of the cable, the braid layer is composed of metal enameled wire mixed fibers, and the cable causes the LED light to be illuminated by capacitive sensing through proximity.2. The cable connector as claimed in claim 1 , wherein the cable includes a power wire claim 1 , a ground wire claim 1 , a data transmission wire claim 1 , and a shielding layer covering outside of the power wire claim 1 , the ground wire claim 1 , and the data transmission wire.3. The cable connector as claimed in claim 1 , wherein the data transmission wire includes a pair of differential signal wires and an insulating layer wrapped on the outside of the differential signal wires.4. The cable connector as claimed in claim 1 , wherein the ground wire is a bare conductor.5. The cable connector as claimed in claim 1 , wherein the shielding layer is an aluminum foil Mylar layer.6. The cable connector as claimed in claim 1 , wherein the cable includes a first outer layer located outside the shielding layer.7. The cable connector as claimed in claim 6 , wherein the cable includes a metal braid layer on the outside of the first outer layer.8. The cable connector as claimed in claim 7 , wherein the cable includes a second outer layer on the outside of the metal braid ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure. 1. A semiconductor structure , comprising:a substrate;a first III-V layer having a first band gap disposed over the substrate; and a first surface proximate the first III-V layer, and', 'a second surface opposite the first surface, wherein a material of the second III-V layer includes a constituent that is graded, such that the second band gap of the second III-V layer increases from the first surface to the second surface., 'a second III-V layer having a second band gap disposed over the first III-V layer, wherein the second III-V layer includes2. The semiconductor structure of claim 1 , wherein the first band gap is less than the second band gap.3. The semiconductor structure of claim 1 , further comprising a gate structure disposed over the second surface of the second III-V layer.4. The semiconductor structure of claim 3 , wherein the gate structure includes a gate electrode and a gate dielectric disposed between the gate electrode and the second surface of the second III-V layer.5. The semiconductor structure of claim 1 , wherein the second III-V layer includes a bilayer having an upper layer and a lower layer claim 1 , wherein the upper layer and the lower layer include a same material configured such that the upper layer includes a greater aluminum concentration than the lower layer.6. The semiconductor structure of claim 5 , wherein the lower layer is thicker than the upper layer.7. The semiconductor ...

HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER

A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer. 1. A method of manufacturing a high electron mobility transistor , the method comprising:depositing a first layer comprising aluminum nitride over a substrate;depositing a second layer comprising aluminum gallium nitride over the first layer;depositing a third layer comprising indium gallium nitride over the second layer;removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer;reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer; anddepositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.2. The method of claim 1 , wherein the aluminum atoms are drawn from the first layer into the second layer beneath the first portion and the second portion of the third layer by laser annealing at least the first portion and the second portion of the third layer.3. The method of claim 1 , wherein the third layer is deposited having between about 5% and about 20% ...

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) HAVING AN INDIUM-CONTAINING LAYER AND METHOD OF MANUFACTURING THE SAME

A high electron mobility transistor (HEMT) includes a substrate, and a channel layer over the substrate, wherein and at least one of the channel layer or the active layer comprises indium. The HEMT further includes an active layer over the channel layer. The active layer has a band gap discontinuity with the channel layer. 1. A high electron mobility transistor (HEMT) comprising:a substrate;a channel layer over the substrate; andan active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer, and at least one of the channel layer or the active layer comprises indium.2. The HEMT of claim 1 , wherein the channel layer comprises an InGaN material.3. The HEMT of claim 2 , wherein x ranges from about 5 to about 15.4. The HEMT of claim 1 , wherein the active layer comprises an AlInN material.5. The HEMT of claim 4 , wherein y ranges from about 80 to about 90.6. The HEMT of claim 1 , further comprising a two-dimensional electron gas (2-DEG) in the channel layer claim 1 , wherein a charge carrier concentration in the 2-DEG is greater than about 1E13 cm.7. The HEMT of claim 1 , wherein the active layer comprise a BInN material.8. The HEMT of claim 7 , wherein w ranges from about 70 to about 95.9. A high electron mobility transistor (HEMT) comprising:a substrate;a seed layer over the substrate;a buffer layer over the seed layer;a channel layer over the buffer layer;{'sup': '−2', 'a two-dimensional electron gas (2-DEG) in the channel layer, wherein a charge carrier concentration in the 2-DEG is greater than about 1E13 cm;'}an active layer over the channel layer; anda top layer over the active layer,wherein at least one of the channel layer or the active layer comprises indium.10. The HEMT of claim 9 , wherein the channel layer comprises an InGaN material claim 9 , and the active layer comprises an AlInN material.11. The HEMT of claim 10 , wherein x ranges from about 5 to about 15.12. The HEMT of claim 10 , wherein y ranges ...

LED LAMP AND COMPONENT, HEAT DISSIPATING BASE AND LED WIRELESS DIMMING SYSTEM THEREOF

An LED lamp and a component, a heat dissipating base and an LED wireless dimming system thereof are provided. The LED lamp component comprises a heat dissipating base, a light emitting module and a lens, the heat dissipating base has a bearing surface and a back surface opposite to the bearing surface, the bearing surface is provided with a first recessed section therein, the back surface is provided with heat dissipating structures; the heat dissipating base further comprises a first joint portion; the light emitting module is disposed in the first recessed section, and the lens covering the light emitting module. 1. An LED lamp component , comprising a heat dissipating base , a light emitting module and a lens ,the heat dissipating base comprising a bearing surface and a back surface opposite to the bearing surface, the bearing surface having a first recessed section, the back surface having heat dissipating structures, and the heat dissipating base further comprising a first joint portion; andthe light emitting module being disposed in the first recessed section, and the lens covering the light emitting module.2. The LED lamp component of claim 1 , wherein the first joint portion is disposed on the bearing surface claim 1 , or disposed on a first side surface or a second side surface of the heat dissipating base that are opposite to each other claim 1 , or disposed on one or more of the heat dissipating structures.3. The LED lamp component of claim 1 , wherein the heat dissipating base further comprises a second joint portion claim 1 , and the second joint portion is disposed at a position that is the same as or different from the position where the first joint portion is disposed.4. The LED lamp component of claim 1 , wherein the heat dissipating base further comprises a plurality of second recessed sections claim 1 , and the second recessed sections are disposed within the first recessed section.5. The LED lamp component of claim 4 , wherein at least a part of ...

PROJECTION DEVICE AND DISPLAY RACK

A projection device is disposable into a display platform of a display rack having a plurality of display platforms, for directly projecting an image frame onto a projection screen of the display platform. The image frame projected to the projection screen is not reflected by any reflective mirror arranged between the projection device and the projection screen. A length of the image frame in a first direction is equal to at least ten times a length of the image frame in a second direction. Since no reflective mirror is arranged between the projection device and the projection screen, the projection device is more easily applicable to display racks. 1. A projection device being disposable into a display platform of a display rack having a plurality of display platforms , and used for directly projecting an image frame onto a projection screen of the display platform , wherein the image frame projected onto the projection screen is not reflected by any reflective mirror arranged between the projection device and the projection screen , and a length of the image frame in a first direction is greater than or equal to ten times a length of the image frame in a second direction.2. The projection device according to claim 1 , further comprising:an illumination system for providing an illumination light beam;a light valve arranged on a transmission path of the illumination light beam, for converting the illumination light beam into an image light beam; anda projection lens arranged on a transmission path of the image light beam for projecting the image light beam onto the projection screen and forming the image frame at the projection screen,wherein the projection lens includes a first lens group arranged along the first direction, a second lens group arranged along a third direction, and a first reflective element arranged between the first lens group and the second lens group, and an optical axis of the first lens group and the first direction include a first angle.311. ...

SUPPERLATTICE BUFFER STRUCTURE FOR GALLIUM NITRIDE TRANSISTORS

A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided. 1. A transistor comprising:a first strained layer superlattice (SLS) layer arranged over a substrate;a first buffer layer arranged over the first SLS layer and including dopants configured to increase a resistance of the first buffer layer;a second SLS layer arranged over the first buffer layer;a second buffer layer arranged over the second SLS layer and including dopants configured to increase a resistance of the second buffer layer;a channel layer arranged over the second buffer layer; andan active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction.2. The transistor according to claim 1 , wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers claim 1 , and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants.3. The transistor according to claim 1 , wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers claim 1 , and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants.4. The transistor according to claim 1 , wherein the first SLS layer and the first buffer layer ...

METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS

A method of forming a semiconductor structure includes depositing a first III-V layer over a substrate. The method includes depositing a first III-V compound layer over the first III-V layer. Depositing the first III-V compound layer includes depositing a lower III-V compound layer. Depositing the first III-V compound layer includes depositing an upper III-V compound layer over the lower III-V compound layer, wherein the first III-V layer has a doping concentration greater than that of the upper III-V compound layer. The method includes repeating depositing III-V compound layers until a number of III-V compound layers is equal to a predetermined number of III-V compound layers. The method includes forming a second III-V compound layer an upper most III-V compound layer, wherein the second III-V compound layer is undoped or doped. The method includes forming an active layer over the second III-V compound layer. 1. A method of forming a semiconductor structure , the method comprising:depositing a first III-V layer having a first-type doping over a substrate; depositing a lower III-V compound layer, wherein the lower III-V compound layer is undoped or has a second doping type, and', 'depositing an upper III-V compound layer over the lower III-V compound layer, wherein the upper III-V compound layer has the first type doping, and the first III-V layer has a doping concentration greater than that of the upper III-V compound layer;, 'depositing a first III-V compound layer over the first III-V layer, wherein depositing the first III-V compound layer comprisesdetermining whether a number of III-V compound layers is equal to a predetermined number of III-V compound layers;repeating depositing III-V compound layers until the number of III-V compound layers is equal to the predetermined number of III-V compound layers;forming a second III-V compound layer over an upper most III-V compound layer, wherein the second III-V compound layer is undoped or has the second type doping; ...

CHARGING BRACKET FOR CONSUMER ELECTRONIC PRODUCT

A charging bracket for charging a consumer electronic product includes a first end, a second end, a connecting portion connecting the first end, a second end, a connecting portion, a first connector located at the first end and cooperating with the consumer electronic product, a second connector connecting with the first connector electrically, a coil located on the connecting portion, a wired charging loop comprising the first connector and the second connector and a wireless charging loop comprising the first connector and the coil, wherein the connecting portion is bendable to lie on a plane different from a plane defined by the first end and the second end. 1. A charging bracket for charging a consumer electronic product , comprising:a first end;a second end;a connecting portion connecting the first end and the second end;a first connector located at the first end for charging the consumer electronic product;a second connector connecting with the first connector electrically;a coil located on the connecting portion;a wired charging loop comprising the first connector and the second connector; anda wireless charging loop comprising the first connector and the coil;wherein the connecting portion is bendable to lie on a plane different from a plane defined by the first end and the second end.2. The charging bracket as claimed in claim 1 , wherein the wired charging loop comprises a cable connected to the second connector claim 1 , a first wire claim 1 , a second wire claim 1 , and a printed circuit board claim 1 , the printed circuit board connecting with the coil electrically and located between the first wire and the second wire.3. The charging bracket as claimed in claim 2 , wherein the first wire and the second wire are integrated inside the charging bracket and are distributed to four round of the charging bracket claim 2 , and the printed circuit board is located inwardly of the second end.4. The charging bracket as claimed in claim 2 , wherein the wired ...

Probe Needle and Probe Module Using the Same

A probe needle includes a head, a tail and a body connected between the head and the tail and provided with a first flat section curvedly extending from the head towards the tail for providing sufficient deformation when the tail is pressed on a device under test, and a second flat section neighbored to the first flat section for supporting the probe needle in between upper and lower dies. When the probe needles are used in a probe module, the probe needles can be arranged with a pitch same as that of the conventional probe needles even though the probe needles are formed from posts having a relatively greater diameter than that of the posts for making the conventional probe needles, such that the probe needles may have enhanced current withstanding capacity and prolonged lifespan. 1. A probe needle comprising a head , a tail and a body connected between the head and the tail , the probe needle being characterized in that the body includes a first flat section curvedly extending from the head towards the tail and having a constant width , and a second flat section connected with an end of the first flat section; the width of the first flat section being greater than a thickness of the second flat section , a diameter of the head and a diameter of the tail; the first flat section having a thickness smaller than a width of the second flat section , the diameter of the head and the diameter of the tail; the width of the second flat section being greater than the thickness of the first flat section , the diameter of the head and the diameter of the tail; the width of the second flat section extending in a first direction and the width of the first flat section extending in a second direction in a way that the first direction is not parallel to the second direction when the first and second directions are projected on a horizontal plane.2. The probe needle as claimed in claim 1 , wherein the second flat section is connected between the first section and the tail.3. The ...

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer. 1. A method of making a semiconductor device , the method comprising:epitaxially growing a channel layer over a substrate;depositing an active layer over the channel layer;forming a gate structure over the active layer, wherein the gate structure is configured to deplete a 2DEG under the gate structure, and the gate structure comprises a dopant; andforming a barrier layer between the gate structure and the active layer, wherein the barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.2. The method of claim 1 , wherein epitaxially growing the channel layer over the substrate comprises growing the channel layer to a thickness ranging from 500 nanometers (nm) to 5000 nm.3. The method of claim 1 , wherein forming the barrier layer comprises forming the barrier layer comprising a Group III-V compound layer.4. The method of claim 1 , wherein forming the barrier layer comprises forming the barrier layer having a thickness ranging from 2 nm to 5 nm.5. The method of claim 1 , wherein forming the gate structure comprisesforming a p-doped layer over the barrier layer; andforming an n-doped layer over the p-doped layer.6. The method of claim 1 , wherein depositing the active layer over the channel layer further comprises:growing an AlN layer over the channel layer; andgrowing an AlGaN layer over the AlN layer.7. The method of claim 5 , ...