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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 19864. Отображено 100.
30-08-2012 дата публикации

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Номер: US20120218846A1
Автор: Yong Gu Kang
Принадлежит: SK hynix Inc

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

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Номер записи: 1
25-10-2012 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20120268992A1
Автор: KIM Beom Sik, Park Young Soo
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals. 1. A semiconductor memory device , comprising:a memory cell array configured to comprise a plurality of memory blocks;a voltage generator configured to output operating voltages for data input and output to global lines; anda row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals.2. The semiconductor memory device of claim 1 , wherein the row decoder supplies the ground voltage to the local lines of the plurality of memory blocks in a standby mode.3. The semiconductor memory device of claim 1 , wherein the row decoder comprises:a block select signal generator for generating block select signals for selecting one of the plurality of memory blocks in response to a row address signal of the address signals; andcoupling circuits for coupling the local lines of the selected memory block and the global lines in response to one of the block select signals and an enable signal, and coupling the local lines of the unselected memory blocks and a ground terminal.4. The semiconductor memory device of claim 3 , wherein the coupling circuits are coupled to the local lines of the plurality of respective memory blocks and are in common coupled to the global lines.5. The semiconductor memory device of claim 3 , wherein each of the coupling circuits comprises:first switching elements coupled between the respective global lines and the ...

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Номер записи: 2
01-11-2012 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20120273783A1
Автор: BYEON Sang Jin, LEE Jae Jin
Принадлежит: SK HYNIX INC.

A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another. 1. A semiconductor apparatus having first and second chips stacked therein , comprising: a first calibration unit provided in the first chip and configured to delay and output read control signals of the first chip; a first data calibration unit provided in the first chip and configured to delay and output data outputted from the first chip; a second calibration unit provided in the second chip and configured to delay and output read control signals of the second chip; and a second data calibration unit provided in the second chip and configured to delay and output data outputted from the second chip.2. The semiconductor apparatus according to claim 1 , wherein the read control signals of the first chip include a column selection signal claim 1 , an output strobe signal claim 1 , and a pipe latch control signal.3. The semiconductor apparatus according to claim 1 , wherein the first calibration unit changes delay amounts of the read control signals of the first chip in response to a test mode signal.4. The semiconductor apparatus according to claim 1 , wherein the read control signals of the second chip include a column selection signal claim 1 , an output strobe signal claim 1 , and a pipe latch control signal.5. The semiconductor apparatus according to claim 1 , wherein the second calibration unit changes delay amounts of the read control signals of the second chip in response to a test mode signal.6. The semiconductor apparatus according to claim 1 , wherein the first data calibration unit changes a delay amount of the data outputted from the first chip in response to a test mode signal.7. The semiconductor apparatus according ...

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Номер записи: 3
01-11-2012 дата публикации

SEMICONDUCTOR DEVICE AND ERASE METHODS THEREOF

Номер: US20120275232A1
Автор:
Принадлежит: SK HYNIX INC.

An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among the memory cells, performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage, and repeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage. 1. An erase method of a semiconductor device , comprising:performing an operation comprised of supplying an erase pulse to erase memory cells of a memory block;performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage;performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage; andrepeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage.2. The erase method of claim 1 , wherein the erase pulse is supplied to a well of the memory block.3. The erase method of claim 1 , wherein the pre-program operation is performed on only the memory cells having the threshold voltages ...

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Номер записи: 4
01-11-2012 дата публикации

BLANK SUBSTRATES FOR EXTREME ULTRA VIOLET PHOTO MASKS AND METHODS OF FABRICATING AN EXTREME ULTRA VIOLET PHOTO MASK USING THE SAME

Номер: US20120276475A1
Автор: CHOI Chung Seon
Принадлежит: SK HYNIX INC.

Blank substrates for an extreme ultraviolet (EUV) photo mask are provided. The blank substrate includes a substrate, a reflection layer on the substrate, an absorption layer on the reflection layer opposite to the substrate, and a critical dimension (CD) compensation layer on the absorption layer opposite to the reflection layer. Methods of forming an extreme ultraviolet (EUV) photo mask using the blank substrate are also provided. 1. A blank substrate for an extreme ultraviolet (EUV) photo mask , the blank substrate comprising:a substrate;a reflection layer formed on the substrate;an absorption layer formed on the reflection layer; anda critical dimension (CD) compensation layer formed on the absorption layer.2. The blank substrate of claim 1 , wherein the substrate is one of a silicon substrate or a glass substrate having a low coefficient of thermal expansion.3. The blank substrate of claim 1 , wherein the reflection layer is capable of reflecting an EUV light in a reflectance of at least sixty percent.4. The blank substrate of claim 1 , wherein the reflection layer comprises a plurality of first layers having a first diffractive index and a plurality of second layers have a second diffractive index claim 1 , wherein the first and second layers are repeatedly formed on another in an alternating manner claim 1 , wherein the first diffractive index is higher than the second diffractive index so as to obtain a reflectance of at least sixty percent.5. The blank substrate of claim 4 , wherein the reflection layer comprises thirty to sixty layers of first and second layers.6. The blank substrate of claim 1 , wherein the reflection layer comprises at least one molybdenum (Mo) layer and at least one silicon (Si) layer that are formed on another in an alternating manner.7. The blank substrate of claim 6 , wherein the reflection layer has a thickness of about 270 nanometer to about 290 nanometer and comprises about forty Mo layers and about forty Si layers.8. The blank ...

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Номер записи: 5
08-11-2012 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20120280325A1
Автор: Kim Chang Seob, KIM Tae Kyung
Принадлежит: SK HYNIX INC.

A semiconductor device includes first gate lines arranged at a first interval over a substrate and each configured to have a silicide layer as a highest layer, second gate lines arranged at a second interval greater than the first interval over the substrate and each configured to have the silicide layer as the highest layer, a first insulating layer formed between the first gate lines over the substrate and includes a gap; a second insulating layer formed on the sidewalls of the second gate lines, an etch-stop layer adjacent the second insulating layer, a third insulating layer located over and between the first gate lines and over and between the second gate lines, a capping layer over the third insulating layer, and a contact plug adjacent to the capping layer and the third insulating layer and coupled to a junction, the junction adjacent the substrate between the second gate lines. 1. A semiconductor device , comprising:first gate lines arranged at a first interval over a semiconductor substrate and each first gate line comprising a plurality of layers with a metal silicide layer as the top layer;second gate lines arranged at a second interval greater than the first interval over the semiconductor substrate and each second gate line comprising a plurality of layers with a metal silicide layer as the top layer;a first insulating layer formed between the first gate lines over the semiconductor substrate and configured to include an air gap;a second insulating layer formed on sidewalls of the second gate lines adjacent to each other;an etch-stop layer formed on sidewalls of the second insulating layer;a third insulating layer formed over and between the first gate lines and over and between the second gate lines;a capping layer formed over the third insulating layer; anda contact plug formed through the capping layer and the third insulating layer in the second interval so as to couple to a junction formed in the semiconductor substrate between the second gate ...

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Номер записи: 6
15-11-2012 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM

Номер: US20120286849A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal. 1. A semiconductor apparatus comprising:a plurality of electrical fuses;a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated;a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; anda shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal.2. The semiconductor apparatus according to claim 1 , wherein the shift register unit comprises a plurality of flip-flops coupled in series and the shift register unit configured to receive the input signal or the scan information.3. The semiconductor apparatus according to claim 1 , wherein claim 1 , in response to the clock signal claim 1 , the shift register unit receives the input signal in series claim 1 , then generates the rupture information and outputs the rupture information in parallel.4. The semiconductor apparatus ...

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Номер записи: 7
15-11-2012 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME

Номер: US20120287720A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed based on program characteristics of the memory cells and sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in a program operation, wherein differently classified two memory cells receive different bit line program voltages, respectively.

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Номер записи: 8
15-11-2012 дата публикации

NONVOLATILE MEMORY DEVICE

Номер: US20120287728A1
Автор: BAE Ji Hyae, TAK Jung Mi
Принадлежит: SK HYNIX INC.

A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.

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Номер записи: 9
15-11-2012 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20120287731A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes: a plurality of memory blocks; and a plurality of temperature sensors disposed adjacent to the respective memory blocks and configured to output a plurality of preliminary temperature sensing signals whose voltage levels are controlled in response to temperature change. A preliminary temperature sensing signal indicating the highest temperature among the plurality of preliminary temperature sensing signals is detected and used as a temperature sensing signal.

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Номер записи: 10
22-11-2012 дата публикации

DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE

Номер: US20120292737A1
Автор:
Принадлежит: SK HYNIX INC.

A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. 1. A diode comprising:a P-type well formed in a semiconductor substrate;a first N-type impurity doping area formed in the P-type well;a second N-type impurity doping area formed in the P-type well;a first P-type impurity doping area formed in the P-type well, and parallel to and apart from the first N-type impurity doping area;a second P-type impurity doping area formed in the P-type well, and parallel to and apart from the second N-type impurity doping area;a first isolation area formed between the first N-type impurity doping area and the first P-type impurity doping area;a second isolation area formed between the second N-type impurity doping area and the second P-type impurity doping area;first contacts formed in the first N-type impurity doping area and the first P-type impurity doping area in a single row or a plurality of rows; andsecond contacts formed in the second P-type impurity doping area and the second N-type impurity doping area in a single row or a plurality of rows,wherein a distance between the second N-type impurity doping area and the second P-type impurity doping area is greater than a distance between the first N-type impurity doping area and the first P-type impurity doping area, and a contact pitch between the second contacts is ...

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Номер записи: 11
22-11-2012 дата публикации

INTERNAL COMMAND GENERATION CIRCUIT

Номер: US20120294106A1
Автор:
Принадлежит: SK HYNIX INC.

The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command. 1. An internal command generation circuit comprising:a first shifting unit configured to receive a first burst pulse comprising a plurality of pulses with a predetermined period, and generate a second burst pulse by shifting the first burst pulse in synchronization with a clock signal, the second burst pulse being disabled when a pulse of a burst end signal is inputted; anda second shifting unit configured to generate an internal command by shifting the second burst pulse in synchronization with the clock signal, the internal command being disabled when a pulse of a burst command is inputted.2816. The internal command generation circuit of claim 1 , wherein claim 1 , when a burst mode is set to have an 8-bit burst length BL claim 1 , then the pulse of the burst end signal is generated when three cycles of the clock signal elapse from the input of the command; and when the burst mode is set to have a 16-bit burst length BL claim 1 , then the pulse of the burst end signal is generated when seven cycles of the clock signal elapse from the input of the command.3. The internal command generation circuit of claim 1 , wherein the first shifting unit comprises:a first logic unit configured to receive the first burst pulse and an inverted signal of the burst end signal and perform a logic operation thereon;a first buffer configured to buffer an output signal of the first logic unit and transfer the buffered signal as the first burst pulse in response to the clock signal;a second logic unit configured to buffer the output signal of the first logic unit in response to the clock signal; anda second buffer configured to buffer an output signal ...

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Номер записи: 12
29-11-2012 дата публикации

Stacked wafer level package having a reduced size

Номер: US20120299169A1
Автор: Jong Hoon Kim, Min Suk Suh, Seung Hyun Lee, Seung Taek Yang, Tae Min Kang
Принадлежит: SK hynix Inc

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

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Номер записи: 13
29-11-2012 дата публикации

STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE

Номер: US20120299199A1
Автор:
Принадлежит: SK HYNIX INC.

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. 1. A stacked wafer level package , comprising:an insulation member including a chip region having a through part and a peripheral region disposed at both sides adjacent to the chip region;a first semiconductor chip coupled to the through part of the insulation member and having a first bonding pad formed on a surface thereof;a second semiconductor chip disposed over the insulation member and a surface of the first semiconductor chip, and having a second bonding pad electrically connected to a connection electrode that passes through a portion of the peripheral region of the insulation member; anda redistribution structure electrically connected to the first bonding pad and the connection electrode.2. The stacked wafer level package according to claim 1 , wherein the redistribution structure includes:a first insulation layer pattern covering the first semiconductor chip and the insulation member, and having first openings for exposing the first bonding pad and the connection electrode;a first redistribution disposed over the first insulation layer pattern and electrically connected with the first bonding pad through the respective first opening of the first insulation layer;a second redistribution disposed over the first insulation layer pattern and electrically connected with the connection electrode ...

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Номер записи: 14
29-11-2012 дата публикации

AMPLIFYING CIRCUIT AND ANALOG DIGITAL CONVERSION CIRCUIT WITH THE SAME

Номер: US20120299758A1
Автор: HWANG Dong Hyun, HWANG Won Seok, LEE SEUNG HOON, SONG Jung Eun
Принадлежит: SK HYNIX INC.

An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with. 1. An analog to digital converting device , comprising:a first digital conversion (ADC) circuit configured to receive an analog signal and convert a part of the analog signal into a first digital signal having a first predetermined number of bits;a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal converted as an analog value from the first digital signal and the analog signal;a second ADC circuit configured to convert a signal amplified by the first MDAC circuit into a second digital signal having a second predetermined number of bits;a second MDAC circuit configured to amplify a difference between a second converted signal converted as an analog value from the second digital signal and the signal outputted from the first MDAC circuit;a third ADC circuit configured to convert a signal amplified by the second MDAC circuit into a third digital signal having a third predetermined number of bits; anda common amplifying circuit shared by the first MDAC circuit and the second MDAC ...

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Номер записи: 15
06-12-2012 дата публикации

SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME

Номер: US20120306550A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element. 1. A method for controlling a semiconductor apparatus comprising a master chip and a slave chip , comprising: determining whether a power-up abnormality occurs in the slave chip; and interrupting operations of the master chip and the slave chip when it is determined that the power-up abnormality occurs in the slave chip.2. The method according to claim 1 , wherein the determining whether a power-up abnormality occurs in the slave chip comprises: determining whether a power-up signal generated in the slave chip is deactivated.3. The method according to claim 1 , wherein whether the master chip and the slave chip are operated is commonly determined in response to a power-up signal generated in the master chip.4. The method according to claim 3 , wherein the interrupting operations of the master chip and the slave chip comprises: inactivating the power-up signal generated in the master chip. The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0093599, filed on Sep. 30, 2009, which is incorporated by reference in its entirety as if set forth in full.1. Technical FieldVarious aspects of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus with a multi-chip package structure and a method for controlling the same.2. Related ArtSemiconductor apparatuses are typically used in the form of multi-chip packages of at least two chips to improve integration efficiency.In the multi-chip packages, a plurality of chips are connected using signal transmission ...

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Номер записи: 16
06-12-2012 дата публикации

SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME

Номер: US20120306566A1
Автор: BYEON Sang Jin, JIN Sin Hyun
Принадлежит: SK HYNIX INC.

A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element. 1. A semiconductor apparatus including a chip , the chip comprising: a power-up signal generation section configured to generate a power-up signal; a driver configured to drive and output the power-up signal; and a main circuit block configured to perform predetermined functions in response to an output from the driver , wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.2. The semiconductor apparatus according to claim 1 , wherein the chip is a slave chip in a multi-chip package.3. The semiconductor apparatus according to claim 1 , wherein the chip is configured to receive a power-up signal from a master chip by a signal transmission element claim 1 , which is connected to the master chip in the multi-chip package.4. The semiconductor apparatus according to claim 3 , wherein the signal transmission element is selected from a group comprising a through-silicon via claim 3 , a bonding wire and a metal line. The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0093599, filed on Sep. 30, 2009, which is incorporated by reference in its entirety as if set forth in full.1. Technical FieldVarious aspects of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus with a multi-chip package structure and a method for controlling the same.2. Related ArtSemiconductor apparatuses are typically used in the form of multi-chip packages of at least two chips to improve integration efficiency.In ...

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Номер записи: 17
06-12-2012 дата публикации

Semiconductor memory apparatus

Номер: US20120307544A1
Автор: Byung Sub NAM, Go Hyun LEE, Sung Lae OH
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.

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Номер записи: 18
13-12-2012 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF PROGRAMMING THE SAME

Номер: US20120314501A1
Автор: Ahn Sung Hoon
Принадлежит: SK HYNIX INC.

A method of programming a semiconductor device includes performing a Least Significant Bit (LSB) program operation on selected memory cells, performing a soft program operation on the remaining memory cells other than memory cells on which the LSB program operation has been performed, and performing a Most Significant Bit (MSB) program operation on memory cells, selected from among the memory cells on which the LSB program operation has been performed and the memory cells on which the soft program operation has been performed. 1. A method of programming a semiconductor device , comprising:performing a Least Significant Bit (LSB) program operation on selected memory cells;performing a soft program operation on remaining memory cells other than memory cells on which the LSB program operation has been performed; andperforming a Most Significant Bit (MSB) program operation on memory cells, selected from among the memory cells on which the LSB program operation has been performed and the memory cells on which the soft program operation has been performed.2. A method of programming a semiconductor device , comprising:performing an even Least Significant Bit (LSB) program operation on an even page including even memory cells, from among memory cells coupled to a selected word line;performing an odd LSB program operation on an odd page including odd memory cells, from among the memory cells coupled to the selected word line;performing an even soft program operation comprising raising threshold voltages of memory cells having an erase state, from among the even memory cells included in the even page;performing an odd soft program operation comprising raising threshold voltages of memory cells having an erase state, from among the odd memory cells included in the odd page;performing an even Most Significant Bit (MSB) program operation on the even page; andperforming an odd MSB program operation on the odd page.3. The method of claim 2 , further comprising performing the even ...

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Номер записи: 19
13-12-2012 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20120314518A1
Автор: CHO Ho Youb, LIM Sang Oh
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address. 1. A semiconductor memory device , comprising:a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock;a column address generation unit for generating a column address in response to the count clock; anda Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.2. The semiconductor memory device of claim 1 , wherein the dummy count clock is toggled before the clock signal is received.3. The semiconductor memory device of claim 2 , wherein the count clock generation unit comprises:a normal count clock generator for generating a normal count clock in response to the clock signal;a dummy count clock generator for generating an internal dummy count enable signal and a dummy count clock in response to a dummy count enable signal; anda selector for outputting the normal count clock or the dummy count clock as the count clock in response to the internal dummy count enable signal.4. The semiconductor memory device of claim 3 , wherein the dummy count clock generator comprises:an enable signal generator configured to generate the internal dummy count enable signal and an oscillator enable signal in response to the dummy count enable signal and to disable the oscillator enable signal in response to a dummy count end signal;an oscillator configured to generate the dummy count clock having a specific cycle in response to the oscillator enable signal; andan oscillator controller enabled in response to the internal dummy count enable signal and configured to generate the dummy count end signal when the dummy count ...

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Номер записи: 20
27-12-2012 дата публикации

PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME

Номер: US20120329222A1
Автор: CHOI Mi Ra, LEE Jang Uk
Принадлежит: SK HYNIX INC.

A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element. 1. A method of fabricating a phase change memory device , the method comprising:preparing a semiconductor substrate including cell and peripheral areas separated by an isolation film;forming a word-line driving transistor in the peripheral area of the semiconductor substrate;forming a word line in the cell area and a gate of the word-line driving transistor in the peripheral area, wherein the word line and the gate formed from a first conductive layer;forming a first interlayer insulation film over the semiconductor substrate and on the word line and on the word-line driving transistor;forming a plurality of current path holes and a plurality of first plug holes such that the current path holes penetrate thought the first interlayer insulation and onto the word line and such that the first plug holes penetrate through the first interlayer insulation film onto the word-line driving transistor;filling in the current path holes to form current plugs with a second conductive layer and filling in the first plug holes to form first plugs with the second conductive layer;forming a strapping line in the cell area and first lines in the peripheral ...

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Номер записи: 21
03-01-2013 дата публикации

STACK PACKAGE HAVING FLEXIBLE CONDUCTORS

Номер: US20130001779A1
Автор: HWANG You Kyung, KANG Tae Min, Kim Yu Hwan, LEE Byoung Do, Lee Dae Woong, SON Jae-hyun
Принадлежит: SK HYNIX INC.

A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package. 1. A stack package comprising:a first package including a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip;a second package stacked on the first package, and including a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip; andflexible conductors disposed in the first encapsulation member of the first package so as to electrically connect the first package and the second package,wherein each of the flexible conductors comprises a flexible circuit board having copper patterns formed on one surface thereof,wherein the configuration of the flexible conductors is one of rolled up in the shape of a hollow cylinder with the copper patterns disposed on an outer surface of the cylinder, or formed to have a sectional shape alternately curved in opposite directions,wherein an inside part of the flexible circuit board which is rolled up in the shape of the hollow cylinder is filled up a polymer substance.2. The stack package according to claim 1 , wherein the polymer substance is any one of a polyimide claim 1 , a silicon resin or a synthetic rubber.3. The stack package according to claim 1 , wherein the first encapsulation member has holes defined therein into which the respective flexible conductors are inserted.4. The stack package according to claim 1 , further comprising: first coupling members attached to a lower surface of the first package.5. The stack package according to claim 1 , ...

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Номер записи: 22
03-01-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130003453A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor memory device is operated by, inter alia: precharging a bit line, providing a first voltage to a coupling circuit for coupling the bit lines and cell strings of a plurality of memory cells, providing a program voltage to a selected word line coupled to a memory cell on which a program operation will be performed among the plurality of memory cells, providing a pass voltage to unselected word lines, providing a second voltage lower than the first voltage to the coupling circuit, discharging the bit line by loading program data, and providing a third voltage lower than the second voltage to the coupling circuit. 1. A method of operating the semiconductor memory device , comprising:precharging a bit line;providing a first voltage to a coupling circuit for coupling the bit line and a cell string of a plurality of memory cells;providing a program voltage to a selected word line coupled to a memory cell on which a program operation is to be performed among the plurality of memory cells;providing a pass voltage to unselected word lines;providing a second voltage lower than the first voltage to the coupling circuit;discharging the bit line by loading program data; andproviding a third voltage lower than the second voltage to the coupling circuit.2. The method of claim 1 , wherein providing the program voltage to the selected word line and providing the pass voltage to the unselected word lines includes simultaneously providing the program voltage and the pass voltage.3. The method of claim 1 , wherein providing the program voltage to the selected word line and providing the pass voltage to the unselected word lines includes simultaneously providing the pass voltage to the selected word line and the unselected word lines and then providing the program voltage to the selected word line once the voltage of the selected word line reaches the pass voltage.4. A method of operating the semiconductor memory device claim 1 , comprising:precharging a bit line coupled ...

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Номер записи: 23
10-01-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130009229A1
Автор:
Принадлежит: SK HYNIX INC.

A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels. 1. A semiconductor device , comprising:memory blocks each configured to comprise channels, each channel including a pipe channel formed in a pipe gate of the memory block and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;first slits placed between the memory blocks adjacent to other memory blocks; anda second slit placed between the source-side channel and the drain-side channel of each pair of channels.2. The semiconductor device of claim 1 , further comprising third slits placed between the drain-side channels adjacent to other drain-side channels claim 1 ,wherein the channels adjacent to each other share a source-side word line, and a drain-side word line and a drain select line of the drain-side channels adjacent to other drain-side channels are separated from other drain-side channels, having a drain-side word line and a drain select line, by the third slit interposed therebetween.3. The semiconductor device of claim 1 , further comprising third slits placed between the source-side channels adjacent to other source-side channels claim 1 ,wherein the drain-side channels adjacent to each other share a drain-side word line, and the source-side word line and a source select line of the adjacent channels are separated from each other by a third slit interposed therebetween4. The semiconductor device of claim 1 , further comprising fourth slits placed between the drain-side channels adjacent to other drain-side channels and formed to generally the same depth as a select line claim 1 ,wherein the ...

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Номер записи: 24
10-01-2013 дата публикации

NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130009235A1
Автор: YOO Hyun Seung
Принадлежит: SK HYNIX INC.

A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate. 1. A non-volatile memory device , comprising:a first vertical channel layer and a second vertical channel layer, both of which, generally protrude upwardly from a semiconductor substrate substantially in parallel;a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates;a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates;a pipe channel layer configured to couple the first vertical channel layer and the second vertical channel layer; anda channel layer extension part extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe ...

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Номер записи: 25
10-01-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHODS OF OPERATING THE SAME

Номер: US20130010547A1
Автор:
Принадлежит: SK HYNIX INC.

A method of operating a semiconductor device includes programming selected memory cells by supplying a selected word line with a program voltage which increases and supplying the remaining unselected word lines with a first pass voltage which is substantially constant; and programming the selected memory cells while supplying first unselected word lines adjacent to the selected word line with a second pass voltage increasing in proportion to the program voltage, when a difference between the program voltage and the first pass voltage reaches a critical voltage difference. 1. A method of operating a semiconductor device , comprising:programming selected memory cells by supplying a selected word line with a program voltage which increases and supplying remaining unselected word lines with a first pass voltage which is substantially constant; andprogramming the selected memory cells while supplying first unselected word lines adjacent to the selected word line with a second pass voltage increasing in proportion to the program voltage, when a difference between the program voltage and the first pass voltage reaches a critical voltage difference.2. The method of claim 1 , further comprising programming the selected memory cells by supplying second unselected word lines adjacent to the first unselected word lines claim 1 , respectively claim 1 , with a third pass voltage having a voltage potential lower than the first pass voltage by the critical voltage difference claim 1 , when supplying the second pass voltage to the first unselected word lines.3. The method of claim 2 , wherein the third pass voltage increases in proportion to the program voltage.4. The method of claim 1 , further comprising:supplying the second unselected word lines adjacent to the first unselected word lines with a fourth pass voltage which decreases in voltage, when supplying the second pass voltage to the first unselected word lines; andsupplying the second unselected word lines with a fifth pass ...

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Номер записи: 26
10-01-2013 дата публикации

Method of operating semiconductor device

Номер: US20130010548A1
Автор: Seiichi Aritome
Принадлежит: SK hynix Inc

A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

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Номер записи: 27
10-01-2013 дата публикации

METHODS OF OPERATING SEMICONDUCTOR DEVICE

Номер: US20130010549A1
Автор: ARITOME Seiichi
Принадлежит: SK HYNIX INC.

A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference. 1. A method of operating a semiconductor device , comprising:programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; andprogramming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference.2. The method of claim 1 , further comprising programming the selected memory cells while applying a third pass voltage having a lower voltage level than the first pass voltage by the critical voltage difference to second unselected word lines adjacent to the first unselected word lines claim 1 , respectively claim 1 , when applying the second pass voltage to the first unselected word lines.3. The method of claim 2 , wherein the third pass voltage gradually rises in proportion to the second pass voltage.4. The method of claim 1 , further comprising:applying a fourth pass voltage, which gradually drops, to second unselected word lines adjacent to the first unselected ...

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Номер записи: 28
17-01-2013 дата публикации

IMAGE PIXEL AND IMAGE PIXEL CONTROL METHOD

Номер: US20130016088A1
Автор: LEE Woong Hee
Принадлежит: SK HYNIX INC.

An image pixel control method includes: performing an initialization process comprising initializing the light receiving unit; performing an excess value sampling process comprising sampling a voltage level corresponding to a quantity of photoelectrons in excess of a photoelectron accommodation capacity of the light receiving unit; performing an initialization level comprising sampling process sampling a voltage level applied to the light receiving unit when the light receiving unit is initialized; and performing a data level sampling process comprising sampling a voltage level corresponding to a quantity of photoelectrons accommodated in the light receiving unit. 1. An image pixel control method comprising:performing an initialization process comprising initializing a light receiving unit;performing an excess value sampling process comprising sampling a voltage level corresponding to a quantity of photoelectrons in excess of a photoelectron accommodation capacity of the light receiving unit;performing an initialization level sampling process comprising sampling a voltage level applied to the light receiving unit when the light receiving unit is initialized; andperforming a data level sampling process comprising sampling a voltage level corresponding to a quantity of photoelectrons accommodated in the light receiving unit.2. The method of claim 1 , wherein claim 1 , in the initialization process claim 1 , a voltage level for initialization is applied to the light receiving unit during a certain period of time.3. The method of claim 1 , wherein claim 1 , in the initialization level sampling process claim 1 , the voltage level for initialization is sampled in a state of making the light receiving unit independent.4. The method of claim 1 , wherein claim 1 , in the data level sampling process claim 1 , a voltage level dropped by the photoelectrons accommodated in the light receiving unit is sampled from the voltage level at the time of initialization.5. The method of ...

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Номер записи: 29
24-01-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130021853A1
Автор: YOO Byoung Sung
Принадлежит: SK HYNIX INC.

An embodiment of the present invention provides a semiconductor device, including cell string comprising a plurality of memory cells; page buffer comprising latch and switching element, wherein the switching element is coupled between the latch and the bit line which is coupled to the cell string; and a page buffer controller configured to apply a gradually rising turn-on voltage to the switching elements during a bit line setup operation of a program operation. 1. A semiconductor device , comprising:cell string comprising a plurality of memory cells;page buffer comprising latch and switching element, wherein the switching element is coupled between the latch and the bit line which is coupled to the cell string; anda page buffer controller configured to apply a gradually rising turn-on voltage to the switching element during a bit line setup operation of a program operation.2. The semiconductor device of claim 1 , wherein the turn-on voltage comprises a staircase waveform signal.3. The semiconductor device of claim 1 , wherein the page buffer controller comprises level shifter for applying the turn-on voltage to gate of the switching element.4. The semiconductor device of claim 2 , wherein the level shifter applies the turn-on voltage to the switching element claim 2 , wherein the turn-on voltage is lower than a target turn-on voltage in the beginning of the bit line setup operation of a program operation and then gradually increases up to the target turn-on voltage.5. A method of operating a semiconductor device claim 2 , comprising:applying a program permission voltage or a program inhibition voltage to latch of page buffer coupled to bit line;setting up the bit line while applying a gradually rising turn-on voltage to gate of the switching element coupled between the bit line and the latch; andperforming a program operation on cell string coupled to the bit line.6. The semiconductor device of claim 5 , wherein the turn-on voltage comprises a staircase waveform ...

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Номер записи: 30
31-01-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT HAVING RESERVOIR CAPACITOR

Номер: US20130026551A1
Автор: KIM Jong Su
Принадлежит: SK HYNIX INC.

A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other. 1. A semiconductor integrated circuit , comprising:a semiconductor substrate in which a cell area and a peripheral circuit area are defined;a metal oxide semiconductor (MOS) capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area; anda dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor,wherein one electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other, andthe other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to different voltage sources.2. The semiconductor integrated circuit of claim 1 , wherein the MOS capacitor includes an active region and a gate electrode formed on the active region on the semiconductor substrate of the peripheral circuit area.3. The semiconductor integrated circuit of claim 2 , wherein the dummy capacitor group includes:a plurality of dummy capacitors, which are connected between the dummy storage node contact unit and the dummy plate electrode in parallel; and.a dummy storage node contact unit including a dummy storage node electrode formed on the peripheral circuit area, a dielectric layer covering the surfaces of the dummy storage node electrode and the ...

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Номер записи: 31
31-01-2013 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM HAVING THE SAME

Номер: US20130031439A1
Автор: KIM Sung Wook, KWON Yong Kee, LEE Hyung Dong, MOON Young Suk, YANG Hyung Gyun
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines. 1. A semiconductor memory apparatus comprising:a memory cell area comprising a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; anda control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.2. The semiconductor memory apparatus according to claim 1 , wherein the control logic area comprises an error correcting code (ECC) circuit configured to generate the parity bits using the data signal inputted to the memory cell area and determine whether the data signal has an error or not claim 1 , using the generated parity bits.3. The semiconductor memory apparatus according to claim 2 , wherein the ECC circuit transmits the data signal inputted to the memory cell area to a data line for transmitting the data signal claim 2 , and transmits the parity bits generated by using the data signal to a data mask line for transmitting a data mask signal.4. The semiconductor memory apparatus according to claim 2 , wherein the ECC circuit comprises:a parity bit generation unit configured to generate the parity bits using the data signal inputted to the memory cell area;an error detection unit configured to compare the parity bits generated by the parity bit generation unit to a data signal outputted ...

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Номер записи: 32
07-02-2013 дата публикации

IMAGE SENSOR

Номер: US20130032693A1
Автор: SOHN Young Chul
Принадлежит: SK HYNIX INC.

Provided is an image sensor capable of supporting a high speed operation. The image sensor includes a plurality of sampling units sampling a pixel signal to output a sampled signal pair; an auxiliary amplification unit amplifying a signal of the sampled signal pair; and an amplification unit sensing a differential signal pair transmitted through the auxiliary amplification unit to generate output data. 1. An image sensor comprising:a plurality of sampling units sampling a pixel signal to output a sampled signal pair;an auxiliary amplification unit amplifying a signal of the sampled signal pair; anda sense amplification unit sensing a differential signal pair transmitted through the auxiliary amplification unit to generate output data.2. The image sensor of claim 1 , wherein the auxiliary amplification unit includes:a voltage providing portion temporarily providing a boosting voltage instead of a driving voltage when a precharging operation is inactivated;an amplifying portion increasing a voltage difference between signals of the sampled signal pair by using the boosting voltage, and thereafter, maintaining the increased voltage difference between signals of the sampled signal pair by using the driving voltage; andan operation control portion activating operation of the amplifying portion when the precharging operation is inactivated.3. The image sensor of claim 2 , wherein the voltage providing portion includes:a first switch providing the boosting voltage to the amplifying portion when a boosting activation signal is activated; anda second switch providing the driving voltage to the amplifying portion when the boosting activation signal is inactivated.4. The image sensor of claim 3 , wherein the operation control portion includes:a third switch providing an output voltage from the voltage providing portion to the amplifying portion when an operation activation signal is activated; anda fourth switch generating a driving current of the amplifying portion when the ...

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Номер записи: 33
14-02-2013 дата публикации

SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES

Номер: US20130037942A1
Автор: Hwang In Chul, KIM Jae Myun, KIM Seung Jee, LEE Jin Su
Принадлежит: SK HYNIX INC.

Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided. 1. A dual-layered structural semiconductor chip , the semiconductor chip comprising:a first semiconductor chip including a first substrate having a first bottom surface; anda second semiconductor chip including a second substrate having a second bottom surface,wherein the first bottom surface directly contacts the second bottom surface.2. The semiconductor chip of claim 1 , wherein each of the first substrate and the second substrate includes a silicon substrate.3. The semiconductor chip of claim 1 , further comprising through electrodes penetrating the first and second semiconductor chips claim 1 ,wherein the through electrodes electrically connect the first semiconductor chip to the second semiconductor chip.4. The semiconductor chip of claim 3 , further comprising:first bumps disposed on a first active layer disposed on a first top surface of the first semiconductor chip, where the first bumps cover first ends of the through electrodes; andsecond bumps disposed on a second active layer disposed on a second top surface of the second semiconductor chip, where the second bumps cover second ends of the through electrodes.5. The semiconductor chip of claim 4 , further comprising:a redistribution layer disposed on one active layer of the first and second active layers and connected to the through electrodes; andbumps disposed on the other active layer of the first and second active layers and connected to the through electrodes.6. The semiconductor chip of claim 4 , further ...

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Номер записи: 34
14-02-2013 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130037952A1
Автор: JUNG Young Berm
Принадлежит: SK HYNIX INC.

A semiconductor package includes a substrate, a driving chip module including a plurality of driving chips stacked on the substrate, and a molding part formed on the substrate by compressing a sheet type molding member in a semi-cured (B-stage) state to cover the driving chip module. 1. A semiconductor package comprising:a substrate;a driving chip module including a plurality of driving chips stacked on the substrate; anda molding part formed on the substrate by compressing a sheet type molding member in a semi-cured (B-stage) state to cover the driving chip module.2. The semiconductor package according to claim 1 ,wherein each driving chip has bonding pads which are formed on the other surface thereof facing away from one surface facing towards the substrate, andwherein the driving chips are stacked in a step-like zigzag shape such that their bonding pads are exposed.3. The semiconductor package according to claim 2 , further comprising:connection members electrically connecting the bonding pads of the respective driving chips with the substrate.4. The semiconductor package according to claim 3 , wherein the connection members comprise conductive wires.5. The semiconductor package according to claim 3 ,wherein the connection members are formed as conductive wires, andwherein the semiconductor package further comprises:an adhesive member formed on an uppermost driving chip among the driving chips that fastens the conductive wires which are connected with the bonding pads of the uppermost driving chip.6. The semiconductor package according to claim 5 , further comprising:a dummy chip attached to the adhesive member.7. The semiconductor package according to claim 6 , wherein the adhesive member comprises a penetrate spacer (P-spacer) tape.8. The semiconductor package according to claim 1 , wherein the molding part comprises of an epoxy molding compound (EMC).9. The semiconductor package according to claim 1 , further comprising a plurality of external connection ...

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Номер записи: 35
14-02-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130038368A1
Автор: Kim Yong-Hoon, Lee Hyun-woo
Принадлежит: SK HYNIX INC.

A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. 17-. (canceled)8. A semiconductor device , comprising:an input delay circuit configured to generate a first delay signal by delaying an input signal through a common delay path whose length is determined in response to a delay control code, and generate a second delay signal by delaying the first delay signal through an additional delay path whose length is determined in response to the delay control code;a first output delay circuit configured to delay the first delay signal through a first delay path whose length is determined in response to the delay control code and output a delayed first delay signal; anda second output delay circuit configured to delay either the first delay signal or the second delay signal through a second delay path whose length is determined in response to the delay control code and output a delayed first delay signal or a delayed second delay signal.9. The semiconductor device of claim 8 , further comprising:a phase mixer configured to mix a phase of an output signal outputted from the first output delay circuit with a phase of an output signal outputted from the second delay circuit.10. The semiconductor device of claim 8 , wherein the delay control code comprises:an input delay control code for controlling an operation of the input delay circuit;a first delay control code for controlling an operation of the first output delay circuit; anda second delay control code for controlling an operation of the second output delay circuit.11. The ...

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Номер записи: 36
14-02-2013 дата публикации

METHOD AND APPARATUS FOR CONTROLLING ADAPTIVE EXPOSURE AND IMAGE SENSOR HAVING THE SAME

Номер: US20130038785A1
Автор: SONG Dong Seob
Принадлежит: SK HYNIX INC.

Provided are a method and apparatus for controlling adaptive exposure, and an image sensor including the same. The method includes calculating a pixel saturation level of an entirety of pixels provided within an image frame and resetting a target brightness value according to the pixel saturation level; and controlling an exposure level of the pixels such that pixel brightness values of the pixels are within the target brightness value and a predetermined range. 1. A method of controlling adaptive exposure , the method comprising:calculating a pixel saturation level of an entirety of pixels provided within an image frame and resetting a target brightness value according to the pixel saturation level; andcontrolling an exposure level of the pixels such that pixel brightness values of the pixels are within the target brightness value and a predetermined range.2. The method of claim 1 , wherein the resetting of the target brightness value includes:initializing the pixel saturation level;determining a saturated pixel, by setting a pixel having a pixel brightness value greater than a saturation pixel threshold value among the pixels comprising the image frame, to be the saturated pixel;calculating the pixel saturation level by accumulating a weighting value corresponding to the saturated pixel to the pixel saturation level; andcontrolling the target brightness value by reducing the target brightness value by a predetermined value when the pixel saturation level is greater than that of an over-saturation rate.3. The method of claim 2 , wherein the controlling of the target brightness value includes setting a minimum target brightness value to be the target brightness value claim 2 , when the reduced target brightness value is smaller than the minimum target brightness value.4. The method of claim 2 , wherein calculating of the pixel saturation level includes dividing the image frame into two or more sub-regions claim 2 , setting a weighting value per the sub-region claim ...

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Номер записи: 37
14-02-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130039143A1
Автор: Park Jung-Hoon
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command. 128-. (canceled)29. A semiconductor system comprising:a semiconductor memory device; anda semiconductor memory device controller,wherein the semiconductor memory device and the semiconductor memory device controller between which a normal data and a recovery information data are transferred,wherein the semiconductor memory device controller compares a recovery information training data with a feedback recovery information training data to produce a comparison result, and controls a phase of the recovery information data transferred to the semiconductor memory device based on the comparison result, andwherein the semiconductor memory device receives the recovery information training data from the semiconductor memory device controller at a predetermined first moment and transfers the feedback recovery information training data to the semiconductor memory device controller at a predetermined second moment.30. The semiconductor system of claim 29 , wherein semiconductor memory device controller compares a normal training data with a feedback normal training data to produce a comparison result claim 29 , and controls a phase of the normal data transferred to the semiconductor memory device based on the comparison result.31. The semiconductor ...

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Номер записи: 38
21-02-2013 дата публикации

ON-DIE TERMINATION CIRCUIT

Номер: US20130043901A1
Автор: Choi Hae Rang, Jang Jae Min, KIM Hyung Soo, Kim Yong Ju
Принадлежит: SK HYNIX INC.

An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. 1. An on-die termination circuit comprising:a period comparison unit configured to compare a period of a first period signal with a period of a reference period signal and vary a count represented by a plurality of driving signals in response to the comparison; anda driver unit configured to drive a pad in response to the plurality of driving signals.Wherein the first period signal has a first period according to a level of a reference voltage, and the first period signal has a second period according to a voltage level of a pad.2. The on-die termination circuit of claim 1 , wherein the period of the reference period signal is shortened when the level of the reference voltage is high and is lengthened when the level of the reference voltage is low.3. The on-die termination circuit of claim 1 , wherein the reference voltage is generated by resistors that distribute a pull-up voltage.4. The on-die termination circuit of claim 1 , wherein the period of the first period signal is shortened when the voltage level of the pad is high and is lengthened when the voltage level of the pad is low.5. The on-die termination circuit of claim 1 , wherein the period comparison unit comprises:a phase frequency detection unit configured to detect a period of the first period signal and a period of the reference period signal and generate a first control signal and a second control signal;a low pass filter unit configured to output a first filtering ...

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Номер записи: 39
28-02-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130049086A1
Автор: AHN Jung Ryul, KIM Jum Soo
Принадлежит: SK HYNIX INC.

The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor. 1. A semiconductor device , comprising:a semiconductor substrate having a cell region and a peripheral circuit region defined therein;semiconductor memory elements formed over the semiconductor substrate in the cell region;an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region;first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix; andsecond conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.2. The semiconductor device of claim 1 , wherein the first conductive layers substantially have a pillar-like shape.3. The semiconductor device of claim 1 , wherein the semiconductor memory elements include a source select transistor claim 1 , memory cells claim 1 , and a drain select transistor.4. The semiconductor device of claim 1 , wherein the second conductive layers include bit lines.5. The semiconductor device of claim 4 , wherein the bit lines and the second conductive layers are formed of copper or aluminum.6. The semiconductor device of claim 1 , ...

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Номер записи: 40
28-02-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130049095A1
Автор: Kim Min Soo, Pyi Seung Ho, SHEEN Dong Sun, WHANG Sung Jin
Принадлежит: SK HYNIX INC.

A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates. 1. A semiconductor device , comprising:a vertical channel layer protruding upward from a semiconductor substrate;a tunnel insulating layer covering a sidewall of the vertical channel layer;a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween;a plurality of control gates enclosing the plurality of floating gates, respectively; andan interlayer insulating layer provided between the plurality of control gates.2. The semiconductor device of claim 1 , further comprising a dielectric layer provided between the floating gates and the control gates.3. The semiconductor device of claim 1 , wherein each of the plurality of control gates includes first conductive layers disposed over and under one of the floating gates while interposing the floating gate claim 1 , and a second conductive layer covering a sidewall of the floating gate between the first conductive layers.4. The semiconductor device of claim 3 , wherein the first and second conductive layers are formed of different materials having an etch selectivity therebetween.5. The semiconductor device of claim 3 , wherein the first conductive layers include polysilicon claim 3 , and the second conductive layers are formed of a material including ...

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Номер записи: 41
28-02-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130051152A1
Автор: LEE Jae Ho, PARK Jin Su
Принадлежит: SK HYNIX INC.

A method of operating a semiconductor memory device includes, applying a read voltage to a selected word line to which a selected memory cell is coupled and applying a pass voltage to non-selected word lines to which non-selected memory cells are coupled, reading data stored in the selected memory cell by sensing the voltage of a bit line associated with the selected memory cell and the non-selected memory cells, discharging the non-selected word lines, and discharging the selected word line after the non-selected word lines are discharged. 1. A method of operating a semiconductor memory device , comprising:applying a read voltage to a selected word line to which a selected memory cell is coupled and applying a pass voltage to non-selected word lines to which non-selected memory cells are coupled;reading data stored in the selected memory cell by sensing a voltage of a bit line associated with the selected memory cell and the non-selected memory cells;discharging the non-selected word lines; anddischarging the selected word line after the non-selected word lines are discharged.2. The method of claim 1 , wherein the applying a pass voltage to non-selected word lines comprises:applying a second pass voltage to non-selected word lines adjacent to the selected word line and applying a first pass voltage lower than the second pass voltage to non-selected word lines not adjacent to the selected word line.3. The method of claim 2 , wherein the applying a read voltage to the selected word line comprises:applying the first pass voltage to the selected word line, andchanging the voltage of the selected word line to the read voltage.4. A method of operating a semiconductor memory device claim 2 , comprising:applying a read voltage to a selected word line to which a selected memory cell is coupled and applying a pass voltage to non-selected word lines to which non-selected memory cells are coupled;reading data stored in the selected memory cell by sensing a voltage of a bit ...

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Номер записи: 42
28-02-2013 дата публикации

High voltage generation circuit and semiconductor device including the same

Номер: US20130051159A1
Автор: Je Il RYU
Принадлежит: SK hynix Inc

A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.

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Номер записи: 43
07-03-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130056884A1
Автор: EOM Dae Sung
Принадлежит: SK HYNIX INC.

A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction. 1. A semiconductor device , comprising:at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines;first contact pads coupled to respective ends of the conductive lines of two of the 4 conductive line groups in a first direction; andsecond contact pads coupled to respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.2. The semiconductor device of claim 1 , wherein the first contact pads and the second contact pads are coupled to an X decoder disposed in a peripheral region.3. The semiconductor device of claim 1 , wherein:odd-numbered conductive line groups of the 4 conductive line groups are extended in the first direction, and even-numbered conductive line groups of the 4 conductive line groups are extended in the second direction.4. The semiconductor device of claim 1 , wherein:odd-numbered conductive line groups of the 4 conductive line groups are extended into a first contact pad region disposed in the first direction of the memory cell block region, andeven-numbered conductive line groups of the 4 conductive line groups are extended into a second contact pad region disposed in the second direction of the memory cell block region.5. The semiconductor device of claim 1 , wherein end portions of the conductive lines of the 4 conductive line groups are perpendicularly extended with respect to the non-end portions.6. The ...

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Номер записи: 44
14-03-2013 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20130064020A1
Автор: Kim Jae Il, LEE Jong Chern
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. 1. A semiconductor memory apparatus comprising first and second data input/output lines coupled with a first memory bank , the semiconductor memory apparatus comprising:a first data input/output unit configured to communicate with the first memory bank through the first data input/output line based on an input/output mode; anda second data input/output unit configured to communicate with the first memory bank through the first and second data input/output lines based on the input/output mode and an address signal.2. The semiconductor memory apparatus according to claim 1 , wherein the first data input/output unit is configured not to be coupled with the first data input/output line in a first input/output mode claim 1 , and is configured to be coupled with the first data input/output line and communicate with the first memory bank in a second input/output mode.3. The semiconductor memory apparatus according to claim 2 , wherein the second data input/output unit is configured to be coupled with one of the first and second data input/output lines to communicate with the first memory bank claim 2 , in response to the address signal in the first input/output mode claim 2 , and is configured to be coupled with the second data input/output line to communicate with the first memory bank in the second input/output mode.4. The semiconductor memory apparatus according to claim 1 , further comprising:a ...

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Номер записи: 45
14-03-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20130064029A1
Автор: KIM Seung Won, PARK Kyoung Hwan
Принадлежит: SK HYNIX INC.

An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells. 1. An operating method of a semiconductor memory device , comprising:precharging a channel region of a program-inhibited cell, from among first memory cells coupled to a first word line selected from a first word line group of word line groups between a drain select line and a source select line, to a first level based on first data;performing a first program operation for storing the first data in the first memory cells;precharging a channel region of a program-inhibited cell, from among second memory cells coupled to a second word line selected from a second word line group of the word line groups, to a second level different from the first level based on second data; andperforming a second program operation for storing the second data in the second memory cells.2. The operating method of claim 1 , wherein when the channel region is precharged to the first level claim 1 , a program inhibition voltage is supplied to a bit line coupled to the program-inhibited cell claim 1 , and a first select voltage higher than the first level by a threshold voltage of a drain select transistor is supplied to the drain select line of the drain select transistor for transferring the program inhibition voltage to the program-inhibited cell.3. The ...

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Номер записи: 46
21-03-2013 дата публикации

NON-VOLATILE MEMORY DEVICE

Номер: US20130070552A1
Автор: KIM Duck Ju, RYU Je Il
Принадлежит: SK HYNIX INC.

A non-volatile memory device includes a plurality of memory blocks, first block switches configured to correspond to the respective odd-numbered memory blocks of the plurality of memory blocks and couple the word lines of the odd-numbered memory blocks and first local lines, second block switches configured to correspond to the respective even-numbered memory blocks of the plurality of memory blocks and couple the word lines of the even-numbered memory blocks and second local lines, a local line switch unit configured to selectively couple the first local lines or the second local lines and global word lines, and a high voltage generator configured to supply operating voltages to the global word lines. 1. A non-volatile memory device , comprising:a plurality of memory blocks;first block switches configured to correspond to respective odd-numbered memory blocks of the plurality of memory blocks and couple word lines of the odd-numbered memory blocks and first local lines;second block switches configured to correspond to respective even-numbered memory blocks of the plurality of memory blocks and couple word lines of the even-numbered memory blocks and second local lines;a local line switch unit configured to selectively couple the first local lines or the second local lines and global word lines; anda high voltage generator configured to supply operating voltages to the global word lines.2. The non-volatile memory device of claim 1 , wherein when the semiconductor memory device is operated claim 1 , an output terminal of the high voltage generator is coupled to the first local lines or the second local lines via the global word lines.3. The non-volatile memory device of claim 1 , wherein the local line switch unit couples the global word lines and the first local lines claim 1 , respectively claim 1 , or the global word lines and the second local lines claim 1 , respectively claim 1 , in response to a plurality of pre-decoding address signals.4. The non-volatile ...

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Номер записи: 47
28-03-2013 дата публикации

INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS

Номер: US20130076401A1
Автор: Choi Hae-Rang, Han Sung-Woo, Hwang Tae-Jin, JANG Jae-Min, Kim Hyung-Soo, Kim Yong-Ju, LEE Ji-Wang, OH Ic-Su, Park Chang-Kun, Song Hee-Woong
Принадлежит: SK HYNIX INC.

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. 1. An input buffer circuit of a semiconductor apparatus , comprising:a bias voltage level control unit configured to output a control bias voltage by decreasing a bias voltage, when a level of the bias voltage becomes higher than a target level;a first buffering unit configured to generate a compare signal by comparing a voltage level of an input signal with a level of a reference voltage, when being activated by receiving the control bias voltage; anda second buffering unit configured to generate an output signal by comparing the voltage levels of the input signal and the compare signal.2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the bias voltage level control unit outputs the bias voltage as the control bias voltage claim 1 , when the bias voltage level is lower than the target voltage level.3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the bias voltage level control unit includes:a level detector configured to generate a detection signal by detecting the bias voltage level;a voltage dropper configured to generate a down voltage by decreasing the bias voltage; anda selector configured to selectively output the bias voltage or the down voltage as the control bias voltage, in response to the detection ...

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Номер записи: 48
28-03-2013 дата публикации

SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL

Номер: US20130077376A1
Автор: KIM Sung Mook, Kim Tae Hoon
Принадлежит: SK HYNIX INC.

A semiconductor device with OTP memory cell includes a first switching unit for transferring a first bias voltage, a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit, and a second switching unit for coupling a second terminal of the first MOS transistor to a first bit line. 1. A semiconductor device including an OTP memory cell , comprising:a first switching unit for transferring a first bias voltage;a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit; anda second switching unit for coupling a second terminal of the first MOS transistor to a first bit line.2. The semiconductor device as recited in claim 1 , wherein in a program mode claim 1 , an insulating layer of the first gate is broken down by applying a high voltage to the first gate.3. The semiconductor device as recited in claim 1 , wherein the first switching unit includes a second MOS transistor having a second gate coupled to a bias enable signal and configured to provide the first bias voltage to the first terminal of the first MOS transistor.4. The semiconductor device as recited in claim 3 , wherein the second switching unit includes a third MOS transistor having a third gate coupled to a second gate signal claim 3 , a first terminal coupled to a second terminal of the first MOS transistor claim 3 , and a second terminal coupled to the bit line.5. The semiconductor device as recited in claim 3 , further comprising:a third switching unit for transferring a second bias voltage;a fourth MOS transistor having a fourth gate coupled to the first gate signal and a first terminal coupled to the second bias voltage by the fourth switching unit; anda fourth switching unit for coupling a second terminal of the fourth MOS transistor to a second bit line.6. The semiconductor device as recited in claim 5 , ...

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Номер записи: 49
28-03-2013 дата публикации

Semiconductor device with otp memory cell

Номер: US20130077377A1
Автор: Tae Hoon Kim
Принадлежит: SK hynix Inc

A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.

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Номер записи: 50
28-03-2013 дата публикации

MEMORY AND PROGRAM METHOD THEREOF

Номер: US20130077403A1
Автор: JOO Seok-Jin
Принадлежит: SK HYNIX INC.

A method of programming a nonvolatile memory includes: applying a common program pulse to program cells within each page of a memory region including two or more pages; applying one or more different program pulses to the program cells within each page of the memory region, according to target threshold voltages of the program cells; and programming each page of the memory region such that the program cells have their own target threshold voltages. 1. A method of programming a nonvolatile memory , comprising:applying a common program pulse to program cells within each page of a memory region including two or more pages;applying one or more different program pulses to the program cells within each page of the memory region, according to target threshold voltages of the program cells; andprogramming each page of the memory region such that the program cells have their own target threshold voltages.2. The program method of claim 1 , wherein the program cells have reached lower threshold voltages than their own target threshold voltages claim 1 , after the applying of the common program pulse and the applying of the one or more different program pulses are completed.3. The program method of claim 1 , wherein claim 1 , in the applying of the one or more different program pulses claim 1 , a program cell having a high target threshold voltage receives a larger variety of program pulses than a program cell having a low target threshold voltage.4. The program method of claim 1 , wherein claim 1 , in the applying of the one or more different program pulses claim 1 , a program cell having a high target threshold voltage receives a higher program pulse than a program cell having a low target threshold voltage.5. The program method of claim 1 , wherein a verification operation is not performed in the applying of the common program pulse and the applying of the one or more different program pulses.6. The program method of claim 1 , wherein the applying of the common program pulse ...

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Номер записи: 51
28-03-2013 дата публикации

IMAGE SENSING DEVICE AND IMAGE DATA PROCESSING METHOD USING THE SAME

Номер: US20130077861A1
Автор: KIM Jong Park
Принадлежит: SK HYNIX INC.

An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process. 1. An image data processing method , comprising:generating data window comprising N row and N columns using a Bayer data from a pixel array;generating a red (R), green (G), blue (B) data of a center pixel in the data window;detecting an edge region in the data window;detecting a bright region in the data window;adjusting the R, G, B data using a suppressing gain factor if both the edge region and the bright region is detected; andoutputting the adjusting R, G, B data as a result of an interpolating process.2. The method of claim 1 , wherein the step of generating an R claim 1 , G claim 1 , B data of a center pixel includes calculating average of pixels neighboring the center pixel.3. The method of claim 1 , wherein the step of detecting an edge region in the data window includes that if a difference between two contiguous pixels in the data window is higher than a predetermined threshold value claim 1 , an edge direction is determined toward the two contiguous pixels.4. The method of claim 1 , wherein the step of detecting the bright region in the data window includes that if average of two continuous pixels including at least one green pixel in the data window is higher than a predetermined threshold value claim 1 , the data window includes a bright region.5. The method of claim 4 , wherein the two continuous pixels are arranged in a horizontal direction.6. The method of claim 4 , wherein the two continuous pixels are arranged in a perpendicular direction.8. The ...

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Номер записи: 52
28-03-2013 дата публикации

WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME

Номер: US20130078807A1
Автор: CHOI Hyeong Seok, HAN Kwon Whan, KIM Seong Cheol, KIM Sung Min, LEE Ha Na, LIM Sang Joon, OH Tac Keun, PARK Chang Jun
Принадлежит: SK HYNIX INC.

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. 1. A method for fabricating a wafer level chip scale package , comprising the steps of:forming through holes passing through an upper face of a semiconductor chip and through a lower face opposite to the upper face, wherein the upper surface of the semiconductor chip is formed with bonding pads electrically connected to a circuit unit;to forming a metal seed layer over an inner surface of the semiconductor chip formed by the through holes and the upper face of the semiconductor chip;forming mask patterns having a band shape over the metal seed layer along a periphery of the redistribution regions respectively connecting the through hole and the bonding pad corresponding to the through hole;forming through electrodes inside the through holes exposed by using the mask patterns, forming redistribution units within each redistribution region and forming a dummy conductive pattern outside of each mask pattern;removing the mask patterns from the metal seed layer; andremoving the metal seed layer formed at a position corresponding to the mask pattern from the upper face of the semiconductor chip.2. The method according to claim 1 , wherein the step of forming the mask patterns over the metal seed layer includes the steps of:forming a photoresist film over the metal seed layer; andpatterning the photoresist film by exposing and developing the photoresist film.3. The ...

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Номер записи: 53
28-03-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130080718A1
Автор: HUH Hwang
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line, a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of the memory cells coupled to even word lines, and a second erase verify operation of the memory cells coupled to odd word lines, and an operation circuit, performing the erase operation of the memory cells, applying a first voltage to the odd and even word lines to form a channel in the vertical semiconductor layer between the odd and even word lines when the first and second erase verify operations are performed, respectively. 1. A semiconductor memory device , comprising:a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line;a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of even memory cells coupled to even word lines among the word lines and a second erase verify operation of odd memory cells coupled to odd word lines; andan operation circuit, controlled by the control circuit, performing the erase operation of the memory cells, applying a first voltage to the odd word lines to form channels in the odd memory cells and channels in the vertical semiconductor layer between the odd word lines and the even word lines when the first erase verify operation is performed, and applying the first voltage to the even word lines to form channels in the even memory cells and channels in the vertical semiconductor layer between the even word lines and the odd word lines when the second erase verify operation is performed.2. The semiconductor memory device of claim 1 , wherein the vertical ...

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Номер записи: 54
28-03-2013 дата публикации

Setting data storage for semiconductor devices including memory devices and systems

Номер: US20130080830A1
Автор: Sam-Kyu Won
Принадлежит: SK hynix Inc

A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.

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Номер записи: 55
04-04-2013 дата публикации

STACK PACKAGE

Номер: US20130082352A1
Автор: KIM Si Han, PARK Myung Geun
Принадлежит: SK HYNIX INC.

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. 1. A stack package comprising:a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads;a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;capacitors including first electrodes electrically connected with the third pads, second electrodes electrically connected with the first connection. pads, and dielectrics interposed between the first electrodes and second electrodes; andconnection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.2. The stack package according to claim 1 , further comprising:first ...

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Номер записи: 56
04-04-2013 дата публикации

REGULATOR AND HIGH VOLTAGE GENERATOR

Номер: US20130083573A1
Автор: RYU Je Il
Принадлежит: SK HYNIX INC.

A regulator includes a current path unit coupled between an input terminal and a ground terminal and including a first current determination unit coupled between the input terminal and a control node and configured to supply the high voltage to the control node so that a first or second current path is selected depending on a voltage of the control node, and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node depending on an input voltage, a voltage supply unit configured to supply the high voltage to an output terminal depending on the voltage of the control node, a voltage division unit configured to create a division voltage, and an amplification unit configured to amplify a difference between the division voltage and a first reference voltage. 1. A regulator , comprising:a current path unit coupled between an input terminal and a ground terminal and configured to include a first current determination unit coupled between the input terminal and a control node and configured to supply a high voltage of a high voltage generator to the control node so that a first or second current path each having a different current load is selected depending on a voltage of the control node, and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node by changing the current load depending on an input voltage;a voltage supply unit configured to supply the high voltage to an output terminal depending on the voltage of the control node;a voltage division unit configured to divide the high voltage supplied to the output terminal to create a division voltage; andan amplification unit configured to amplify a difference between the division voltage of the voltage division unit and a first reference voltage and output the amplified voltage to the second current determination unit.2. The regulator ...

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Номер записи: 57
04-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130083600A1
Автор: LEE Jin Haeng
Принадлежит: SK HYNIX INC.

A method of operating a semiconductor device includes selecting one of a plurality of memory cell blocks included in a memory cell array, programming even-numbered memory cells coupled to a selected word line among the word lines of the selected memory cell block, programming odd-numbered memory cells coupled to the selected word line, programming odd-numbered memory cells coupled to a next word line adjacent to the selected word line, and programming even-numbered memory cells coupled to the next word line, wherein the programming is repeated until programming on selected memory cells coupled to all the word lines of the selected memory cell block is completed. 1. A method of operating a semiconductor device , comprising:selecting one of a plurality of memory cell blocks included in a memory cell array;programming even-numbered memory cells coupled to a selected word line among word lines of the selected memory cell block;programming odd-numbered memory cells coupled to the selected word line;programming odd-numbered memory cells coupled to a next word line adjacent to the selected word line; andprogramming even-numbered memory cells coupled to the next word line,wherein the programming is repeated until programming on selected memory cells coupled to all the word lines of the selected memory cell block is completed.2. The method of claim 1 , wherein programming the even-numbered memory cells coupled to the selected word line comprises:supplying a program voltage to the selected word line so that threshold voltages of the even-numbered memory cells coupled to the selected word line increase;determining whether all the threshold voltages of the even-numbered memory cells coupled to the selected word line have reached a target level or not; andrepeatedly programming the even-numbered memory cells coupled to the selected word line while raising the program voltage gradually If, as a result of the determination, it is determined that all the threshold voltages have not ...

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Номер записи: 58
04-04-2013 дата публикации

Voltage supply circuit, semiconductor memory device, and operating method thereof

Номер: US20130083614A1
Автор: Duck Ju Kim, Je Il RYU, Pil Seon YOO
Принадлежит: SK hynix Inc

A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.

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Номер записи: 59
04-04-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130084696A1
Автор: Kim Hyeon Soo, KIM Suk Ki
Принадлежит: SK HYNIX INC.

A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed. 1. A method of manufacturing a semiconductor device , comprising:forming first gate lines and second gate lines over a semiconductor substrate, wherein the second gate lines are arranged at wider intervals than each of the first gate lines;forming a multi-layered insulating layer over an entire surface of the semiconductor substrate including the first and the second gate lines;etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines, and between the first and the second gate lines;forming a mask pattern on the remaining multi-layered insulating layer, wherein the mask pattern covers the multi-layered insulating layer between the second gate lines; andetching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first gate lines and the second gate lines are exposed.2. The method of claim 1 , wherein a highest layer of each of the first and the second gate lines is formed ...

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Номер записи: 60
11-04-2013 дата публикации

Semiconductor device and capacitor

Номер: US20130087843A1
Автор: Kyoung Rok HAN
Принадлежит: SK hynix Inc

The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.

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Номер записи: 61
11-04-2013 дата публикации

STACK PACKAGE

Номер: US20130087887A1
Автор: KIM Si Han, PARK Myung Geun
Принадлежит: SK HYNIX INC.

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. 1. A stack package comprising:a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads; andcapacitors interposed between the first semiconductor chip and the second semiconductor chip, and having first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes,wherein the first electrodes and the second electrodes of the capacitors directly contact the first surface of the first semiconductor chip having the first pads disposed thereon and the third surface of the second semiconductor chip having the third pads disposed thereon, respectively,the first electrode of each capacitor includes a first plate part having a plurality of first projecting parts formed thereon extending toward the second electrode, and the second electrode of ...

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Номер записи: 62
11-04-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130088284A1
Автор: JEONG Tae Seong
Принадлежит: SK HYNIX INC.

A semiconductor device includes a precharge circuit configured to precharge a voltage output node, a boosting circuit configured to boost a voltage at the voltage output node by a predetermined level after the voltage output node is precharged, and a voltage supply circuit configured to supply a pumping voltage to increase the voltage at the voltage output node to a target level. 1. A semiconductor device , comprising:a precharge circuit configured to precharge a voltage output node;a boosting circuit configured to boost a voltage at the voltage output node by a predetermined level after the voltage output node is precharged; anda voltage supply circuit configured to supply a pumping voltage to increase the voltage at the voltage output node to a target level.2. The semiconductor device of claim 1 , wherein the precharge circuit is configured to precharge the voltage output node in proportion to a power voltage.3. The semiconductor device of claim 1 , wherein the voltage supply circuit is configured to increase the voltage at the voltage output node to the target level when the voltage at the voltage output node becomes greater than an operation allowing level.4. The semiconductor device of claim 1 , wherein when the voltage output node is precharged to a level higher than an operation allowing level by the precharge circuit claim 1 , the voltage supply circuit is configured to start an operation of increasing the voltage at the voltage output node to the target level before the voltage at the voltage output node is boosted by the boosting circuit.5. The semiconductor device of claim 1 , wherein when the voltage output node is precharged to a level lower than an operation allowing level by the precharge circuit claim 1 , the voltage supply circuit is configured to start an operation of increasing the voltage at the voltage output node to the target level after the voltage at the voltage output node is boosted to a level higher than the operation allowing level by ...

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Номер записи: 63
11-04-2013 дата публикации

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130088930A1
Автор: Cho Myung, HAH Beom Seok, KIM Ji Hwan, Lee Jung Hwan, Park Seong Je
Принадлежит: SK HYNIX INC.

A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address. 1. A nonvolatile memory device , comprising:a page buffer unit configured to comprise a plurality of page buffers coupled to respective bit lines;a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing an amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to a number of allowed error correction code bits; anda masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having identical upper bits as an input column address.2. The nonvolatile memory device of claim 1 , wherein each of the plurality of page buffers temporarily stores the verify data by sensing a program state of memory cells comprising the page buffer and controls a potential of a sense node based on the verify data.3. The nonvolatile memory device of claim 2 , wherein each of the plurality of page buffers comprises:a line coupling circuit for coupling a respective bit line and the sense node;a precharge circuit for precharging the sense node;a ...

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Номер записи: 64
18-04-2013 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME

Номер: US20130093007A1
Автор: JEONG Joo Hong, Yune Hyoung Soon
Принадлежит: SK HYNIX INC.

A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region. 1. A semiconductor memory apparatus , comprising:an isolation layer defining an active region in a cell region and a peripheral region;a buried word line and a gate line disposed in the cell region and the peripheral region respectively; anda connection pad disposed in the isolation layer and coupled to the gate line.2. The semiconductor memory apparatus of claim 1 , wherein a gate pattern is disposed over the connection pad.3. The semiconductor memory apparatus of claim 1 , further comprising a dummy gate line disposed in the peripheral region and having a length substantially the same as that of the gate line.4. The semiconductor memory apparatus of claim 1 , further comprising:a bit line arranged in a direction of crossing the buried word line in the cell region; anda plurality of contacts disposed over the connection pad and the active region included in the peripheral region.5. The semiconductor memory apparatus of claim 4 , wherein a contact disposed over the connection pad has a length substantially the same as a contact disposed over the active region. Priority to Korean Patent Application No. 10-2009-0093117, filed on Sep. 30, 2009, which is incorporated herein by reference in its entirety, is claimed.Exemplary embodiments of the present invention relate to a method for fabricating a highly ...

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Номер записи: 65
18-04-2013 дата публикации

DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF

Номер: US20130093473A1
Автор: Song Ho-Uk
Принадлежит: SK HYNIX INC.

A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data. 1. A method for outputting data in a data output apparatus , comprising:generating driving signals from input data;driving an output terminal to a level corresponding to the input data in response to the enabled driving signals to generate output data; andrestricting a variation width of voltage level of the output data by forming a current path.2. The method of claim 1 , further comprising disabling the driving signals while a data output operation is not performed.3. The method of claim 1 , further comprising opening a current path from the output terminal to a ground voltage source terminal to lower a level of the output data by a predetermined level when the input data is at a logical high level.4. The method of claim 3 , further comprising opening a current path from the output terminal to a power supply voltage source terminal to raise the level of the output data by a predetermined level when the input data is at a logical low level.5. The method of claim 1 , further comprising cutting-off the current path while a data output operation is not performed.6. The method of claim 1 , further comprising:driving the output terminal to a level of a power supply voltage source according to the input data; anddriving the output terminal to a level of a ground voltage source according to the input data. The present application claims priority to and is a divisional application of U.S. patent application Ser. No. 12/ ...

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Номер записи: 66
18-04-2013 дата публикации

DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME

Номер: US20130093484A1
Автор: KIM Tae-Kyun
Принадлежит: SK HYNIX INC.

A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. 125-. (canceled)26. A delay circuit comprising:a pulse generation unit configured to synchronize an input signal with a clock, and generate a pulse signal which is activated in response to the synchronized input signal and has a pulse width corresponding to delay information; andan output unit configured to activate a final output signal in response to a deactivation of the pulse signal.27. The delay circuit of claim 26 , wherein the pulse generation unit comprises:a synchronization section configured to synchronize the input signal with the clock;at least one shift section configured to sequentially shift the synchronized input signal;a selection section configured to select one output signal of the at least one shift section in response to delay information; anda latch section configured to activate the pulse signal in response to the synchronized input signal and deactivate the pulse signal in response to an output signal of the selection section.28. The delay circuit of claim 27 , wherein the latch section comprises an SR latch.29. The delay circuit of claim 26 , wherein the output unit is configured to output the final output signal by performing a logic operation on the clock and the pulse signal.30. The delay circuit of claim 26 , wherein the output unit comprises:a pass gate configured to transfer the pulse signal in response to the clock;an inverter configured to invert the pulse signal; anda logic gate configured to perform an AND operation on an output signal of the pass gate and an output signal of the inverter and output the final output signal.31. A method for driving a delay circuit comprising first and second delay units claim 26 , which receive ...

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Номер записи: 67
18-04-2013 дата публикации

PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME

Номер: US20130094285A1
Автор: LEE Se Ho, PARK Hae Chan
Принадлежит: SK HYNIX INC.

A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. 1. A phase change memory device comprising:a cell array including a plurality of memory cells,wherein the memory cell includes:first switching elements connected to first word lines;second switching elements connected between the first switching elements and second word lines; andvariable resistors connected between the first switching elements and bit lines.2. The phase change memory device of claim 1 , wherein the first and second switching elements have a threshold voltage.3. The phase change memory device of claim 2 , wherein the first and second switching elements are diodes.4. The phase change memory device of claim 3 , wherein each variable resistor is connected to an anode of a first diode of the first switching element claim 3 ,a cathode of the first diode of the first switching element is connected to anode a second diode of the second switching element and connected to one of the first word lines, anda cathode of a second diode of the second switching element is connected to one of the second word lines.5. The phase change memory device of claim 1 , wherein the first and second word lines are configured to be selectively grounded or floated.6. The phase change memory device of claim 1 , further comprising switches configured to selectively drive the first and second word lines.7. The phase change memory device of claim 6 , wherein the switches are installed to correspond to each of the first and second word lines.8. A phase change memory device comprising:a cell array that includes a plurality of ...

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Номер записи: 68
18-04-2013 дата публикации

REFRESH CONTROL CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS

Номер: US20130094317A1
Автор: Lee Jeong Woo
Принадлежит: SK HYNIX INC.

A refresh control circuit of a semiconductor apparatus includes: a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation, a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation, a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation, and a row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals. 1. A refresh control circuit semiconductor apparatus , comprising:a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation;a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation;a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation; anda row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals.2. The refresh control circuit according to claim 1 , wherein the row selection unit generates the first row select signal according to the first refresh address signal claim 1 , when the first bank select signal is enabled.3. The refresh control circuit according to claim 2 , wherein the row selection unit disables the second row select signal according to the first refresh address signal claim 2 , when ...

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Номер записи: 69
25-04-2013 дата публикации

Multi-chip package cross-reference to related applications

Номер: US20130099256A1
Автор: Seung Yeop Lee
Принадлежит: SK hynix Inc

A multi-chip package includes a lower substrate; at least two semiconductor chips stacked over the lower substrate and each defined with a via hole; an upper substrate coupled to a semiconductor chip positioned uppermost among the semiconductor chips; a light emitting part coupled to the lower substrate corresponding to the via hole; an electrowetting liquid lens coupled to a lower surface of the upper substrate for receiving a signal transferred from the light emitting part through the via hole; a light receiving part coupled to a sidewall of the via hole of each semiconductor chip configured to receive a signal from the electrowetting liquid lens.

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Номер записи: 70
25-04-2013 дата публикации

3-d nonvolatile memory device and method of manufacturing the same

Номер: US20130099306A1
Автор: Eun Seok Choi, Hyun Seung Yoo
Принадлежит: SK hynix Inc

A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

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Номер записи: 71
25-04-2013 дата публикации

Semiconductor package and stacked semiconductor package

Номер: US20130099359A1
Автор: Sung Min Kim
Принадлежит: SK hynix Inc

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

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Номер записи: 72
25-04-2013 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130099360A1
Автор: SON Ho Young
Принадлежит: SK HYNIX INC.

A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer. 1. A semiconductor package comprising:a semiconductor chip having a front surface and a back surface facing away from the front surface;a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; anda contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.2. The semiconductor package according to claim 1 , wherein the contamination preventing layer is an impurity layer including argon (Ar).3. The semiconductor package according to claim 1 , wherein the contamination preventing layer is disposed at a depth of 1˜10 μm from the back surface of the semiconductor chip such that the contamination preventing layer is closer to the back surface than the front surface of the semiconductor chip.4. The semiconductor package according to claim 1 , further comprising:an isolation pattern formed on the back surface of the semiconductor chip into a shape which surrounds the through electrode.5. The semiconductor package according to claim 4 , wherein the isolation pattern is a groove which is defined by etching a portion of the back surface of the semiconductor chip between adjacent through electrodes and on the contamination preventing layer.6. The semiconductor package according to claim 4 , wherein the isolation pattern has the shape of a closed loop or a polygon when viewed from the top.7. The semiconductor package according to claim 1 , further comprising:is a back side bump formed on an other end of the through electrode which is disposed on the back surface ...

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Номер записи: 73
25-04-2013 дата публикации

Chip carriers, semiconductor devices including the same, semiconductor packages including the same, and methods of fabricating the same

Номер: US20130099368A1
Автор: Kwon Whan Han
Принадлежит: SK hynix Inc

Chip carriers are provided. The chip carrier includes a carrier body having a cavity therein and at least one conductive through silicon via (TSV) penetrating the carrier body under the cavity. The cavity includes an uneven sidewall surface profile. The at least one conductive through silicon via (TSV) is exposed at a bottom surface of the carrier body opposite to the cavity. Related methods are also provided.

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Номер записи: 74
25-04-2013 дата публикации

PACKAGE OF ELECTRONIC DEVICE INCLUDING CONNECTING BUMP, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME

Номер: US20130099374A1
Автор: HAN Kwon Whan
Принадлежит: SK HYNIX INC.

A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer. 1. A package of an electronic device , comprising:a substrate configured to allow a connecting contact part to be exposed on a surface thereof;a step difference layer configured to cover the substrate so as leave the connecting contact part exposed; anda connecting bump configured to be connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and have a sloped upper surface formed by a step difference formed by the step difference layer.2. The package of claim 1 , wherein the substrate is a semiconductor substrate of a semiconductor chip claim 1 , on which an integrated circuit is integrated claim 1 , a printed circuit board (PCB) on which the semiconductor chip is to be mounted claim 1 , or a package substrate including an interposer substrate.3. The package of claim 2 , wherein the semiconductor substrate comprises a through electrode providing the connecting contact part as an exposed surface.4. The package of claim 3 , further comprising a conductive layer configured to be connected to the exposed surface of the through electrode on the substrate so as to be used as a contact pad or redistribution layer (RDL).5. The package of claim 1 , wherein the step difference layer comprises an insulating layer having an opening through which the connecting contact ...

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Номер записи: 75
25-04-2013 дата публикации

SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Номер: US20130099375A1
Автор: KIM Jong Hoon
Принадлежит: SK HYNIX INC.

A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body. 1. A semiconductor package substrate comprising:a substrate body having a front surface on which a semiconductor chip is mounted and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; anda conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.2. The semiconductor package substrate of claim 1 , wherein the inclined surface of the window is formed in such a manner that the window is widened from the front surface toward the rear surface of the substrate body.3. The semiconductor package substrate of claim 1 , wherein the inclined surface of the window is formed in such a manner that the window is narrowed from the front surface toward the rear surface of the substrate body.4. The semiconductor package substrate of claim 1 , wherein the window is formed in a region corresponding to a region where a bonding structure of the semiconductor chip is disposed claim 1 , such that a path from the bonding structure provided in the semiconductor chip to a system substrate disposed under the semiconductor package substrate becomes as short as possible.5. The semiconductor package substrate of claim 1 , wherein the conductive pattern comprises an extended portion disposed on one or more of the front and rear surfaces of the ...

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Номер записи: 76
25-04-2013 дата публикации

THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

Номер: US20130100722A1
Автор: SHIN Hack Seob
Принадлежит: SK HYNIX INC.

A 3D non-volatile memory device including a substrate that includes a first region and a second region; a pipe channel film that is formed on the substrate in the first region; a pipe gate that substantially encloses the pipe channel film; and a driving gate that is formed on the substrate in the second region and has at least one dummy pattern. 1. A 3D non-volatile memory device comprising:a substrate that includes a first region and a second region;a pipe channel film that is formed on the substrate in the first region;a pipe gate that substantially encloses the pipe channel film; anda driving gate that is formed on the substrate in the second region, and has at least one dummy pattern.2. The 3D non-volatile memory device of claim 1 , wherein the driving gate and the pipe gate are formed on a same layer.3. The 3D non-volatile memory device of claim 1 , wherein the dummy pattern is made of a material having an etch selectivity with respect to the driving gate and the pipe gate.4. The 3D non-volatile memory device of claim 1 , wherein claim 1 , in a region of the driving gate excluding a region where the dummy pattern is formed claim 1 , a contact region is defined.5. The 3D non-volatile memory device of claim 4 , wherein the dummy pattern is embedded inside the driving gate excluding the contact region to thereby be substantially formed in a shape of a cylinder claim 4 , a square pillar claim 4 , a polyprism claim 4 , or an elliptic cylinder claim 4 , or includes a contact hole exposing the contact region to thereby be formed to have substantially the same size as that of the driving gate.6. The 3D non-volatile memory device of claim 1 , further comprising:a pair of vertical channel films that are connected to the pipe channel film, and protrude over the substrate; andmemory cells that are stacked along the pair of vertical channel films.7. The 3D non-volatile memory device of claim 6 , wherein each of the memory cells includes a word line that substantially ...

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Номер записи: 77
25-04-2013 дата публикации

THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES

Номер: US20130100738A1
Автор: CHOI Eun Seok
Принадлежит: SK HYNIX INC.

A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions, respectively, and well pickup lines coupled to the second junctions, respectively. 1. A three-dimensional (3-D) nonvolatile memory device , comprising:channel layers protruded from a substrate;word line structures configured to comprise word lines stacked over the substrate;first junctions and second junctions formed in the substrate between the word line structures adjacent to each other;source lines coupled to the first junctions, respectively; andwell pickup lines coupled to the second junctions, respectively.2. The 3-D nonvolatile memory device of claim 1 , further comprising subgate lines formed between the word line structures claim 1 , wherein each of the subgate lines controls a formation of a channel between the first junction and the second junction.3. The 3-D nonvolatile memory device of claim 2 , wherein an N type channel is formed in the substrate by turning on a selected subgate line when a read operation is performed.4. The 3-D nonvolatile memory device of claim 2 , wherein a P type channel is formed in the substrate by floating a selected subgate line when an erase operation is performed.5. The 3-D nonvolatile memory device of claim 1 , further comprising:at least one lower select line formed under the word line structures; andat least one upper select line formed over the word line structures.6. The 3-D nonvolatile memory device of claim 1 , further comprising:at least one lower select line formed under one of the word line structures; andat least two upper select lines formed over the word line structure.7. The 3-D nonvolatile memory device of claim 1 , wherein channel layers included in adjacent channel ...

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Номер записи: 78
25-04-2013 дата публикации

IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130102106A1
Автор: KIM Jong Hoon, YANG Seung Taek
Принадлежит: SK HYNIX INC.

An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. 1. A method of manufacturing an image sensor module , comprising the steps of:forming a plurality of recesses in a lower face of a transparent substrate;forming a light concentration member having transparent light concentration parts that are filled within each of the recesses;forming a color filter on each of the light concentration parts;forming photo diode units including a photo diodes on each of the color filters, the photo diodes generating a sensing signal corresponding to an amount of light passing through each color filter;forming an insulation member for covering the photo diode units; andforming input/output terminals on the insulation member, each electrically connected to a corresponding one of the photo diode units.2. The method according to claim 1 , wherein the step of defining the recesses comprises the steps of:forming a photoresist pattern over the lower face, the photoresist pattern having a plurality of openings arranged in a matrix configuration ; andetching the lower face of the transparent substrate using the photoresist pattern as an etching mask to form the recesses, wherein a portion of the lower surface of the transparent substrate defined by a recess has a curved surface.3. The method according to claim 1 , wherein the step of forming the light concentration member comprises the steps of:depositing a transparent semiconductor material on the lower face ...

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Номер записи: 79
25-04-2013 дата публикации

SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME

Номер: US20130102118A1
Автор: Lee Jin-Ku, Lee Mi-Ri, Lee Young-Ho
Принадлежит: SK HYNIX INC.

A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. 1. A method for fabricating a semiconductor device , comprising:forming a first conductive layer doped with a first impurity for form ng a cell junction over a semiconductor substrate;forming a second conductive layer over the first conductive layer;forming a plurality of active regions each having a first sidewall and a second sidewall, by etching the second conductive layer and the first conductive layer, wherein the plurality of the active regions are separated from one another by trenches;ion-implanting a second impurity into a portion of the first conductive layer of the active region on the side of the first sidewall;forming a side contact connected to the first conductive layer of the active region on the side of the second sidewall; andforming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.2. The method of claim 1 , wherein the ion-implanting of the second impurity into a portion of the first conductive layer of the active region on the side of the first sidewall is performed using a counter-doping process.3. The method of wherein the first impurity comprises an N-type and the second impurity includes a P-type impurity.4. The method of claim 1 , wherein the ion-implanting of the second impurity into a portion of the first conductive layer of the active region on the side of the first sidewall is performed in the ...

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Номер записи: 80
25-04-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME

Номер: US20130102146A1
Автор: BYEON Sang-Jin, CHOI Jun-Gi
Принадлежит: SK HYNIX INC.

A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. 110-. (canceled)11. A method for fabricating a semiconductor integrated circuit , comprising:determining whether or not a semiconductor chip to be fabricated is a semiconductor chip in which a conductive pattern thereof is to be cut;fabricating the semiconductor chip including the conductive pattern disposed in a formation region of a through-chip via in response to a determination that the semiconductor chip is a semiconductor chip in which a conductive pattern is to be cut; andforming a through-chip via to pass through the conductive pattern disposed in the formation region of the through-chip via and to cut the conductive pattern.12. The method of claim 11 , wherein the forming of the through-chip via comprises forming an insulation pattern for insulating the conductive pattern from the through-chip via. The present application claims priority of Korean Patent. Application No. 10-2010-0050497, filed on May 28, 2010, which is incorporated herein by reference in its entirety.Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit and a method for fabricating the same.In general, packaging technology for semiconductor integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability. Recently, as the high performance of electrical and electronic products has been demanded with the miniaturization of electrical and electronic products, a variety of technologies for a stack package have been developed.In the semiconductor industry, “stack” means vertically stacking two or more ...

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Номер записи: 81
02-05-2013 дата публикации

NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20130105883A1
Автор: Hong Kwon, JOO Moon-Sig, LEE Ki-Hong
Принадлежит: SK HYNIX INC.

A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers. 1. A non-volatile memory device comprising:a pair of columnar cell channels vertically extending from a substrate;a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels;insulation layers over the substrate in which the doped pipe channel is buried;memory layers arranged to surround side surfaces of the columnar cell channels; andcontrol gate electrodes arranged to surround the side surfaces of the memory layers.2. The non-volatile memory device of claim 1 , wherein the columnar cell channel is undoped.3. The non-volatile memory device of claim 1 , wherein the columnar cell channel includes an undoped polysilicon layer and the doped pipe channel includes a doped polysilicon layer.4. The non-volatile memory device of claim 1 , further comprising a slit arranged to separate the control gate electrodes for controlling a first one of the columnar cell channels from the control gate electrodes for controlling the other one of the columnar cell channels.5. The non-volatile memory device of claim 4 , wherein the slit is arranged to tunnel through an upper end of the doped pipe channel.6. The non-volatile memory device of claim 4 , further comprising an insulation layer arranged to fill the slit.7. The non-volatile memory device of claim 1 , wherein the doped pipe channel includes a polysilicon layer doped with an N type impurity.8. The non-volatile memory device of claim 1 , wherein the columnar cell channel includes a macaroni structure and a filled structure.925-. (canceled) The present application claims priority of ...

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Номер записи: 82
02-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130106483A1
Автор: RYU Je Il
Принадлежит: SK HYNIX INC.

A semiconductor device includes a high voltage generator for generating a high voltage by raising a power source voltage, a transfer circuit for transferring the high voltage to an internal circuit in response to a transfer signal, and a first discharge circuit for discharging the high voltage of an output node of the high voltage generator or the high voltage of an input node or output node of the transfer circuit when the power source voltage drops. 1. A semiconductor device , comprising:a high voltage generator configured to generate a high voltage by raising a power source voltage;a transfer circuit configured to transfer the high voltage to an internal circuit in response to a transfer signal; anda first discharge circuit configured to discharge the high voltage of an output node of the high voltage generator or the high voltage of an input node or output node of the transfer circuit when the power source voltage drops.2. The semiconductor device of claim 1 , wherein the first discharge circuit discharges the high voltage of the input node or the output node to a power source voltage terminal to which the power source voltage is supplied.3. The semiconductor device of claim 1 , wherein the first discharge circuit comprises:a first diode configured to receive an enable signal;a first transistor comprising a first drain and a first gate, wherein the first drain is coupled to the input node or the output node of the transfer circuit and the first gate is coupled to an output terminal of the first diode; anda second diode coupled between a source of the first transistor and a power source voltage terminal to which the power source voltage is supplied.4. The semiconductor device of claim 3 , further comprising a capacitor coupled between the gate of the first transistor and a ground terminal.5. The semiconductor device of claim 3 , wherein the first diode comprises a second transistor having a second drain and a second gate coupled to a node to which the enable ...

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Номер записи: 83
02-05-2013 дата публикации

VOLTAGE SELECT CIRCUIT AND INTERGRATED CIRCUIT INCLUDING THE SAME

Номер: US20130106491A1
Автор: RYU Je Il
Принадлежит: SK HYNIX INC.

A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals. 1. A voltage select circuit , comprising:a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal;a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals; anda control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.2. The voltage select circuit of claim 1 , wherein the control circuit comprises:a first OR gate configured to generate a result signal by performing an OR operation on the plurality of enable signals;a delay circuit configured to generate an output signal by delaying the result signal of the first OR gate for a specific time period;an inverter configured to generate an inverted signal by inverting the output signal;a voltage supply circuit configured to output a third voltage or a ground voltage to a second output terminal in response to the output signal of the delay circuit and the inverted signal of the inverter, where the third voltage is higher than the first voltage, but lower than the second voltage; anda plurality of capacitors coupled between respective first transfer elements and the second output terminal and configured to boost the first voltage, supplied to the first transfer element, to the second voltage by using the ...

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Номер записи: 84
02-05-2013 дата публикации

MULTI-REGULATOR CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME

Номер: US20130106501A1
Автор: YOO Pil Seon
Принадлежит: SK HYNIX INC.

A multi-regulator circuit comprises a regulator configured to regulate an input voltage to generate a constant voltage, and a plurality of voltage division circuits configured to output divided voltages which are obtained by dividing the constant voltage on the basis of a plurality of voltage generation codes, respectively. 1. A multi-regulator circuit , comprising:a regulator configured to regulate an input voltage to generate a constant voltage; anda plurality of voltage division circuits configured to output divided voltages which are obtained by dividing the constant voltage on the basis of a plurality of voltage generation codes, respectively.2. The multi-regulator circuit of claim 1 , wherein the regulator comprises a comparator configured to compare a feedback voltage divided from the output voltage of the regulator with a reference voltage and output a control signal according to a result of the comparison claim 1 , and the output voltage of the regulator is provided to the plurality of voltage division circuits in response to the control signal.3. The multi-regulator circuit of claim 1 , wherein each of the plurality of voltage division circuits comprises:a plurality of resistors coupled in series between an output terminal of the regulator and a ground node;at least one high voltage switch enabled by at least one digital bit included in a corresponding voltage generation code and configured to couple at least one of nodes of the resistors and an output node; andat least one transistor turned on by one or more digital bits, included in the corresponding voltage generation code, but not included in the at least one digital bit inputted to the high voltage switch, and coupled between the ground node and at least one node not coupled to the high voltage switch, from among the nodes of the resistors.4. The multi-regulator circuit of claim 3 , wherein:each of the plurality of voltage generation codes inputted to each of the plurality of voltage division circuits ...

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Номер записи: 85
02-05-2013 дата публикации

3-D NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20130107602A1
Автор: ARITOME Seiichi, LEE Sang Bum, Oh Sang Hyun
Принадлежит: SK HYNIX INC.

A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein. 1. A three-dimensional (3-D) nonvolatile memory device , comprising:a channel layer protruded from a substrate;a plurality of memory cells stacked along the channel layer;a source line coupled to an end of one side of the channel layer;a bit line coupled to an end of an other side of the channel layer;a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein; anda second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.2. The 3-D nonvolatile memory device of claim 1 , further comprising a third junction interposed between the end of one side of the channel layer and the first junction and configured to have an N type impurity doped therein.3. The 3-D nonvolatile memory device of claim 1 , further comprising:at least one first select transistor interposed between the first junction and a memory cell formed at the end of one side of the channel layer, from among the plurality of memory cells; andat least one second select transistor interposed between the second junction and a memory cell formed at the end of the other side of the channel layer, from among the plurality of memory cells.4. The 3-D nonvolatile memory device of claim 3 , wherein when a read operation is ...

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Номер записи: 86
02-05-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130107636A1
Автор: Kim Min-Su, PARK Jin-Su
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory bank configured to store data, a buffering unit including a plurality of buffers, which are disposed to extend to a X-axis of the memory bank to store data transferred from the memory bank, a plurality of data transmission lines configured to transfer the data stored in the plurality of buffers, and a path multiplexing unit configured to select one of a plurality of data transmission paths in response to addresses and transfer the data through the selected data transmission path. 1. A semiconductor memory device comprising:a memory bank configured to store data;a buffering unit including a plurality of buffers, which are disposed to extend to an X-axis of the memory bank to store data transferred from the memory bank;a plurality of data transmission lines configured to transfer the data stored in the plurality of buffers; anda path multiplexing unit configured to select one of a plurality of data transmission paths in response to addresses and transfer the data, which is transferred through the plurality of data transmission lines, through the selected data transmission path.2. The semiconductor memory device of claim 1 , wherein each of the data transmission lines has a length shorter than a total length of the buffers provided in the buffering unit.3. The semiconductor memory device of claim 1 , further comprising:a column selection unit configured to generate a selection signal for activating the buffers in response to the addresses.4. The semiconductor memory device of claim 1 , wherein the path multiplexing unit is configured to select a part of the data transmission paths in response to a part of the addresses claim 1 , and select a remaining part of the data transmission paths in response to a remaining part of the addresses.5. A semiconductor memory device comprising:a plurality of sub-buffering units configured to correspond to one memory bank and to be obtained by grouping a plurality of buffers based on a ...

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Номер записи: 87
02-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130107647A1
Автор: KANG Tai Kyu, SONG Sang Hyun
Принадлежит: SK HYNIX INC.

The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm. 1. A semiconductor device comprising:a ROM configured to store a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and to output ROM data corresponding to a selected algorithm;a program counter configured to output a ROM address to the ROM so as to operate the selected algorithm;an internal circuit configured to perform an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals according to the ROM data; anda reset circuit configured to stop progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.2. The semiconductor device of claim 1 , wherein a reset check code is stored in a first line syntax of the program algorithm claim 1 , the erase algorithm claim 1 , and the reading algorithm.3. The semiconductor device of claim 1 , wherein the reset circuit comprises a reset signal generator configured to output a program counter reset signal in response to the reset command.4. The semiconductor device of claim 3 , wherein the program counter is configured to output an initial ROM address in response to the ...

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Номер записи: 88
02-05-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF

Номер: US20130111081A1
Автор: KIM Tae-Kyun
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units. 1. A semiconductor memory device comprising:a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated;a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals;a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit; anda plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.2. The semiconductor memory device of claim 1 , wherein the information data is input at a time interval corresponding to the first storage completion time.3. The semiconductor memory device of claim 1 , wherein the path selection unit has a plurality of transmission paths corresponding to the number of the second storage units.4. The semiconductor memory device of claim 1 , wherein the number of the first storage units corresponds to the number of the second storage units.5. A semiconductor memory device comprising:a command decoding unit configured to decode an external command signals and generate ...

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Номер записи: 89
09-05-2013 дата публикации

Semiconductor devices and methods of manufacturing the same

Номер: US20130113111A1
Автор: Young Jin Lee
Принадлежит: SK hynix Inc

A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines.

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Номер записи: 90
09-05-2013 дата публикации

INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME

Номер: US20130114359A1
Автор: KIM Kwang Hyun
Принадлежит: SK HYNIX INC.

A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. 1. An output method of a semiconductor apparatus , comprising the steps of:(a) generating a first data group based on data applied to a plurality of input lines;(b) generating a second data group to be the same as the first data group, based on the data applied to the plurality of input lines;(c) outputting at least a portion of the first data group at a first timing; and(d) outputting at least a portion of the second data group at a second timing after the first timing.2. The output method according to claim 1 , further comprising the step of:(e) repeating the steps (c) and (d) until the first data group and the second data group are all outputted,wherein the steps (a), (b), (c), (d) and (e) are repeated twice.3. The output method according to claim 1 , wherein the first timing is a rising edge of an input clock claim 1 , and the second timing is a falling edge of the input clock.4. The output method according to claim 1 , wherein the at least a portion of the second data group which is outputted in the step (d) is the same as the at least a portion of the first data group which is outputted in the step (c).5. The output method according to claim 1 ,wherein the first data group and the second data ...

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Номер записи: 91
09-05-2013 дата публикации

WIRELESS SIGNAL TRANSMITTING/RECEIVING APPARATUS FOR SEMICONDUCTOR SYSTEM

Номер: US20130117477A1
Автор: Cho Sun Ki, Jung Boo Ho, Kim Hyun Seok, KIM Yang Hee, Lee Jun Ho, Oh Ic Su
Принадлежит: SK hynix, Inc.

A wireless signal transmitting/receiving apparatus for a semiconductor system is disclosed The apparatus includes a serializer/deserializer (SERDES) circuit and a coupling pad. The SERDES circuit outputs a parallel input signal as a serial signal during transmission, and outputs a serial input signal as a parallel signal during reception. The coupling pad generates an inductively coupled wireless signal according to the serial signal outputted from the SERDES circuit, and provides a signal generated by inductive coupling with an external device as the serial input signal of the SERDES circuit. 1. A wireless signal transmitting/receiving apparatus for a semiconductor system , comprising:a transmission control unit coupled to receive transmit data from a signal transmission line;a reception control unit coupled to provide received data to the signal transmission line;a serializer/deserializer (SERDES) circuit coupled to the transmission control unit and the reception control unit, the SERDES circuit serializing parallel data received from the transmission control unit and providing parallel data to the reception control unit;an input/output circuit configured to separate and amplify the serializing parallel data to provide the serializing parallel data to a coupling pad, and provide a received signal from the coupling pad to the SERDES circuit; andthe coupling pad configured to generate a wireless signal corresponding to the separated and amplified signal and to provide signals corresponding to wireless signals received from an external device to the input/output circuit.2. The apparatus according to claim 1 , wherein the input/output circuit further comprising a single-to-differential buffer for generating a single input signal as a differential output signal.3. The apparatus according to claim 1 , further comprising a path control unit coupled between the transmission control unit claim 1 , the reception control unit and the SERDES circuit configured to provide ...

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Номер записи: 92
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING A BURIED GATE AND METHOD FOR FORMING THEREOF

Номер: US20130119461A1
Автор: KIM Jaeyoung, KIM Seijin
Принадлежит: SK HYNIX INC.

A semiconductor device includes: a first interlayer insulating layer in first and second regions of a semiconductor substrate, a second interlayer insulating layer over the first interlayer insulating layer in first and second regions, a hard mask provided between the first and the second interlayer insulating layers in the second region and not extending to the first region, a first metal contact formed through the second interlayer insulating layer and the hard mask in the second region, and a first storage node contact formed through the first interlayer insulating layer in the first region. 117-. (canceled)18. A semiconductor device , comprising:a first interlayer insulating layer in first and second regions of a semiconductor substrate;{'b': '550', 'i': 'b', 'a second interlayer insulating layer () over the first interlayer insulating layer in first and second regions;'}a hard mask provided between the first and the second interlayer insulating layers in the second region and not extending to the first region;a first metal contact formed through the second interlayer insulating layer and the hard mask in the second region; anda first storage node contact formed through the first interlayer insulating layer in the first region.19. The device of claim 18 ,wherein a top surface of the a first metal contact is substantially at the same level as a top surface of the first storage node contact, andwherein a top surface of the first metal contact is substantially at the same level as a top of the second interlayer insulating layer.20. The device of claim 18 ,wherein a bottom of the first metal contact is at a higher level than a bottom of the first storage node contact.21. The device of claim 18 , the device further comprising:an interlayer insulating pad formed (i) between the first interlayer insulating layer and the hard mask in the second region and (ii) between the first and the second interlayer insulating layers in the first region.22. The device of claim 21 , ...

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Номер записи: 93
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130119463A1
Автор: PARK Hyung Jin
Принадлежит: SK HYNIX INC.

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. 1. A semiconductor device comprising:a bit line buried in a substrate;first and second gates disposed over the substrate, the substrate including the bit line;a first plug disposed in a lower portion between the first and second gates and coupled to the bit line;a silicon layer disposed on an upper surface and a sidewall of at least one of the first and second gates; anda second plug coupled to a portion of the silicon layer that is disposed over each of the first and second gates.2. The semiconductor device according to claim 1 , wherein the bit line includes tungsten.3. The semiconductor device according to claim 1 , wherein the first plug and the second plug include doped polysilicon.4. The semiconductor device according to claim 1 , wherein the first plug and the second plug correspond to source and drain regions claim 1 , respectively.5. The semiconductor device according to claim 1 , wherein the silicon layer includes a compound material including silicon.6. The semiconductor device according to claim 1 , wherein the silicon layer corresponds to a channel region.720.-. (canceled) The priority of Korean patent application No. 10-2010-0071529 filed on Jul. 23, 2010, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.The present invention relates to a semiconductor device ...

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Номер записи: 94
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME

Номер: US20130119464A1
Автор: Lee Jin-Ku, Lee Mi-Ri, Lee Young-Ho
Принадлежит: SK HYNIX INC.

A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. 1. A semiconductor device , comprising:a plurality of active regions, each configured to have a doped conductive layer pattern doped with an impurity for forming a cell junction, the plurality of the active regions being separated from one another by trenches;a side contact configured to be connected to a sidewall of the conductive layer pattern of the active region; andmetal bit lines, each configured to be connected to the side contact and fill a portion of each trench.2. The semiconductor device of claim 1 , wherein the active regions further comprise an undoped conductive layer pattern formed over the doped conductive layer pattern.3. The semiconductor device of claim 1 , wherein the doped conductive layer pattern comprises a silicon epitaxial layer.4. The semiconductor device of claim 1 , wherein the impurity is an N-type impurity.5. The semiconductor device of claim 1 , wherein the impurity is doped in a doping concentration ranging from approximately 1E19 atoms/cmto approximately 1E22 atoms/cm.6. The semiconductor device of claim 1 , wherein the active regions form line-shaped pillars claim 1 , and the side contact is formed in a line shape on a sidewall of the doped conductive layer pattern.7. The semiconductor device of claim 1 , wherein the side contact comprises a metal silicide.8. A semiconductor device claim 1 , comprising:a plurality of active regions, each ...

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Номер записи: 95
16-05-2013 дата публикации

DELAY LOCKED LOOP

Номер: US20130120042A1
Автор: Kim Yong-Hoon, Lee Hyun-woo
Принадлежит: SK HYNIX INC.

A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. 1. A delay locked loop comprising:a closed loop circuit configured to generate preliminary delay information;a control unit configured to update the preliminary delay information into delay information in response to a control signal; anda first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.2. The delay locked loop of claim 1 , wherein the control signal is activated during a period in which a system claim 1 , comprising the delay locked loop claim 1 , does not use the output clock signal.3. The delay locked loop of claim 2 , wherein the first delay unit is deactivated when the control signal is activated.4. The delay locked loop of claim 1 , wherein the preliminary delay information is periodically generated regardless of the control signal.5. The delay locked loop of claim 4 , wherein when the control signal is activated claim 4 , the preliminary delay information and the delay information have the same value claim 4 , andwhen the control signal is deactivated, the delay information maintains a value which was last updated when the control signal is activated.6. The delay locked loop of claim 1 , wherein the control unit comprises:a transfer section configured to update the preliminary delay information into the delay information in response to the control signal; anda storage section configured to store the delay information updated by the transfer section.7. The delay locked loop of claim 1 , wherein the closed loop circuit comprises:a second delay unit configured to delay the ...

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Номер записи: 96
16-05-2013 дата публикации

INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF

Номер: US20130121069A1
Автор: Shin Yoon-Jae
Принадлежит: SK HYNIX INC.

An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal. 111-. (canceled)12. A method for generating an internal voltage of a phase change memory device , comprising:generating a divided voltage by dividing an internal voltage level with first division ratio in a programming operation mode corresponding to an operation mode control signal;generating the divided voltage by dividing the fed-back internal voltage level with a second division ratio in a read/standby operation mode corresponding to the operation mode control signal wherein the second division ratio is smaller than the first division ratio;detecting the divided voltage level based on a reference voltage level and generating the internal voltage based on a charge pumping method in response to the detection result; andunder-driving an internal voltage terminal with a supply voltage for a predetermined time when the phase change memory device enters read/standby operation mode corresponding to the operation mode control signal.13. The method of claim 12 , wherein the generating of the divided voltage by dividing an internal voltage level with a first division ration in a programming operation mode includes:shifting level of the operation mode control signal to level of the internal voltage in the programming operation mode when the operation mode control ...

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Номер записи: 97
16-05-2013 дата публикации

Method of operating nonvolatile memory device

Номер: US20130121082A1
Автор: Eun Joung Lee, Won Yeol Choi
Принадлежит: SK hynix Inc

A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program operation for the even memory cells is performed, performing a program operation on the odd memory cells coupled to the odd bit lines, and coupling the odd bit line to the page buffer based on the set coupling resistance value and performing an verification operation for verifying whether threshold voltages of the odd memory cells on which the program operation is performed are a target voltage or more.

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Номер записи: 98
16-05-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE APPARATUS INCLUDING THE SAME

Номер: US20130121090A1
Автор: JEON Tae Ho, Park Won Sun
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit. 1. A semiconductor memory device comprising:a memory cell arranged at a region where a word line and a bit line cross each other;a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cell, based on a seed value, so as to generate first randomized data;a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cell; anda control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit.2. The semiconductor memory device according to claim 1 , wherein the data reading/writing circuit is configured to generate the second randomized data by inverting at least one bit of the first randomized data.3. The semiconductor memory device according to claim 1 , wherein the randomizing and de-randomizing circuit is configured to use a column address as the seed value.4. The semiconductor memory device according to claim 3 , wherein the randomizing and de-randomizing circuit comprises:a random value generator configured to generate a random value based on the column address; anda mixer configured ...

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Номер записи: 99
23-05-2013 дата публикации

SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130126956A1
Автор: LEE Kyoung Han
Принадлежит: SK HYNIX INC.

A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line, 1. A semiconductor device including a vertical transistor , the device comprising:an active region formed in a semiconductor substrate;a bit line disposed in a lower portion of the active region;a word line buried in the active region, the word line being formed inside of the active region or formed penetrating the active region; anda capacitor disposed over an upper portion of the active region and the word line, the capacitor being coupled to the bit line via the active region.2. The semiconductor device according to claim 1 , wherein to the word line and the active region are in contact and defining a step difference.3. The semiconductor device according to claim 1 , wherein the word line and the active region are in contact with substantially no step difference.4. The semiconductor device according to claim 1 , wherein the cross-sectional shape of the word line is rectangular or oval.5. The semiconductor device according to claim 1 , wherein the active region has a rectangular pillar shape or a cylindrical column shape.6. The semiconductor device according to claim 1 , further comprising a storage node contact coupled between upper portion of the active region and the lower portion of the capacitor.7. The semiconductor device according to claim 1 , wherein the word line is buried in a middle part of the active region or at one sidewall of ...

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Номер записи: 100