ЭЛЕКТРОННЫЙ БЕСКОНТАКТНЫЙ МОДУЛЬ ДЛЯ КАРТЫ ИЛИ ЭТИКЕТКИ

Изобретение относится к портативным предметам, таким, как электронные этикетки, бесконтактные карты с чипом. Техническим результатом является понижение себестоимости бесконтактных карт. Для этого в электронном модуле электронная микросхема расположена над витками антенны, антенна полностью расположена на модуле, соединительные клеммы антенны присоединены к соответствующим контактным зажимам на модуле или электронной микросхемы посредством проводов. Электронная этикетка для идентификации предметов содержит указанный выше модуль. Способ изготовления электронной этикетки содержит следующие этапы: вырезают из бесконтактной карты первый элемент, содержащий упомянутый электронный модуль, вырезают из бесконтактной карты второй элемент той же формы, что и первый элемент, собирают первый и второй элементы таким образом, чтобы электронный модуль находился между первым и вторым элементами и был защищен ими. 3 с. и 12 з.п.ф-лы, 17 ил.

СОСТАВ НА ОСНОВЕ МОДИФИЦИРОВАННОЙ РАСТВОРИТЕЛЕМ СМОЛЫ И СПОСОБЫ ЕГО ИСПОЛЬЗОВАНИЯ

Изобретение относится к вариантам прозрачного состава, применяемого, например, в качестве заполнителя под кристаллом, к твердотельному устройству и к способу производства прозрачного состава. По первому варианту прозрачный состав содержит, по меньшей мере, одну отверждаемую ароматическую эпоксидную смолу, по меньшей мере, один растворитель, наполнитель, и, по меньшей мере, один компонент, выбранный из группы, включающей циклоалифатический эпоксидный мономер, алифатический эпоксидный мономер, гидроксиароматические соединения и их комбинации и смеси. Наполнитель представляет собой коллоидную двуокись кремния, функционализированную органосилоксаном, и имеет размер частиц от 20 нм до 100 нм. При необходимости состав содержит, по меньшей мере, один компонент, выбранный из группы, включающей эпоксидные смолы, акрилатные смолы, полиимидные смолы, фторполимеры, бензоциклобутеновые смолы, бисмалеимидные триазиновые смолы, фторированные простые полиаллиловые эфиры, полиамидные смолы, полиимидоамидные ...

ЭЛЕКТРОННЫЙ МОДУЛЬ ДЛЯ ЭЛЕКТРОННОЙ КАРТОЧКИ

Изобретение относится к электронному модулю, предназначенному, в частности, для установки в электронное устройство типа чип-карты. Технический результат - изготовление электронного модуля ограниченной высоты и реализация карточки с большей толщиной на уровне модуля при использовании его в данной карточке, что повышает механическую прочность последней. Модуль содержит подложку, по меньшей мере, одну поверхность с контактными дорожками и микросхему, закрепленную на подложке и имеющую выходные контакты, каждый из которых соединен с контактной дорожкой подложки. Модуль отличается тем, что соединения между выходными контактами и контактными дорожками образованы швами из адгезивного вязкого токопроводящего вещества, нанесенного по методу раздачи из приспособления типа шприца по рельефу между упомянутыми выходными контактами и контактными дорожками. 2 с. и 4 з.п.ф-лы, 3 ил.

СПОСОБ ВСТРАИВАНИЯ КОМПОНЕНТА В ОСНОВАНИЕ

Изобретение относится к способу, согласно которому полупроводниковые компоненты, образующие часть электронной схемы, или по меньшей мере некоторые из таких компонентов, встраивают в основание, например, в печатную плату в процессе ее изготовления. Технический результат - создание способа, посредством которого бескорпусные микросхемы могут быть встроены в основание надежным, но экономичным образом. Достигается тем, что в основании выполняют сквозные отверстия для полупроводниковых компонентов, причем отверстия проходят между первой и второй поверхностями основания. После выполнения отверстий на вторую поверхность структуры основания наносят полимерную пленку, причем полимерная пленка закрывает сквозные отверстия для полупроводниковых компонентов со стороны второй поверхности структуры основания. Перед отверждением полимерной пленки или после ее частичного отверждения в отверстия вводят полупроводниковые компоненты со стороны первой поверхности. Полупроводниковые компоненты прижимают к полимерной ...

СПОСОБ ИЗГОТОВЛЕНИЯ МОДУЛЯ КАРТОЧКИ С МИКРОСХЕМОЙ, МОДУЛЬ КАРТОЧКИ С МИКРОСХЕМОЙ, ИЗГОТОВЛЕННЫЙ ЭТИМ СПОСОБОМ, И УНИВЕРСАЛЬНАЯ КАРТОЧКА С МИКРОСХЕМОЙ, СОДЕРЖАЩАЯ ЭТОТ МОДУЛЬ

Изобретение относится к способу изготовления модуля карточки с микросхемой, содержащего носитель с первой контактной плоскостью и полупроводниковым кристаллом, а также с электропроводными соединениями между полупроводниковым кристаллом и первой контактной плоскостью. Дополнительно к первой контактной плоскости модуль карточки с микросхемой содержит на другой стороне носителя вторую контактную плоскость, которая электрически соединена с полупроводниковым кристаллом. Вторая контактная плоскость может служить, например, для обеспечения контакта с катушкой индуктивности, интегрированной в корпус карточки, для бесконтактной передачи данных. Технический результат изобретения заключается в создании способа изготовления модуля карточки с микросхемой, который позволяет простым и экономичным путем присоединить антенну или иное средство к контактным элементам карточки с микросхемой, при этом в модуле карточки с микросхемой, изготовленном данным способом, в значительной степени исключается влияние ...

МОЩНАЯ ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА СВЧ-ДИАПАЗОНА

Использование: полупроводниковая микроэлектроника. Сущность изобретения: в мощной гибридной интегральной схеме СВЧ-диапазона глубина углублений в металлическом основании выбрана такой, что лицевая поверхность кристаллов и металлическое основание расположены в одной плоскости, диэлектрическая плата имеет экранную заземляющую металлизацию на обратной стороне в местах, прилегающих к металлическому основанию, металлическое основание герметично и электрически соединено с экранной заземляющей металлизацией платы, а соединяющие отверстия платы заполнены электропроводящим материалом, причем расстояние от боковых поверхностей кристаллов до боковых поверхностей углублений в основании составляет 0,001 - 0,2 мм. Техническим результатом изобретения является улучшение электрических и теплорассеивающих характеристик схемы. 2 з.п.ф-лы, 2 ил.

МНОГОКРИСТАЛЬНЫЙ КОРПУС И СПОСОБ ПРЕДОСТАВЛЕНИЯ В НЕМ ВЗАИМНЫХ СОЕДИНЕНИЙ МЕЖДУ КРИСТАЛЛАМИ

Изобретение относится к микроэлектронике, к структурам взаимного соединения в многокристальных корпусах. Сущность изобретения: многокристальный корпус включает в себя подложку, имеющую первую сторону, противоположную вторую сторону и третью сторону, которая продолжается от первой стороны до второй стороны, первый кристалл, закрепленный на первой стороне подложки, и второй кристалл, также закрепленный на первой стороне подложки, и мост, расположенный рядом с третьей стороной подложки и соединенный с первым кристаллом и со вторым кристаллом. Никакой из участков подложки не находится под мостом. Мост формирует соединение между первым кристаллом и вторым кристаллом. В качестве альтернативы мост может быть расположен в полости на подложке или между подложкой и слоем кристалла. Мост может составлять активный кристалл и может быть закреплен на подложке с использованием проводных соединений. Изобретение позволяет получить структуры взаимных соединений между кристаллами в корпусах с большой плотностью ...

СХЕМНЫЙ МОДУЛЬ И УСТРОЙСТВО СВЯЗИ ПО ЛИНИИ ЭЛЕКТРОПЕРЕДАЧИ

Использование: в области электронной техники. Технический результат заключается в повышении надежности и защиты от шума. Схемный модуль монтируется с ИС, которая модулирует и демодулирует сигнал с несколькими несущими. Схемный модуль имеет многослойную плату, которая изнутри снабжается множеством проводящих слоев, уложенных с изолирующими слоями между ними, и ИС, которая снабжается множеством выводов заземления, которые нужно заземлить. Из множества проводящих слоев проводящий слой, представленный ближайшим к ИС, формирует слой заземления, электрически соединенный с множеством выводов заземления. 2 н. и 14 з.п. ф-лы, 39 ил.

КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

КОНТАКТИРОВАНИЕ ПОЛУПРОВОДНИКОВЫХ МИКРОСХЕМ В ЧИП-КАРТАХ

... 1. Чип-карта, которая имеет корпус (1) чип-карты, полупроводниковую микросхему (3), и закрепленную в корпусе (1) чип-карты подложку (2), с которой полупроводниковая микросхема (3) связана электрически и механически, при этом корпус (1) чип-карты имеет первую полость (10) и вторую полость (20), причем вторая полость (20) выполнена в основании первой полости (10), так что первая полость (10) простирается в боковые стороны над второй полостью (20), и плоскость (15) основания первой полости (10) охватывает вторую полость (20), при этом подложка (2) размещена в первой полости (10) и на своей верхней стороне (11) имеет верхние плоские контакты (4) для считывания чип-карты, а на своей нижней стороне (12) имеет нижние плоские контакты (5), которые посредством проходящих через подложку (2) проводников (6) контактных отверстий электрически связаны друг с другом, при этом полупроводниковая микросхема (3) посредством электрических соединений (9) связана с нижними плоскими контактами (5) подложки (2 ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

СОСТАВ НА ОСНОВЕ МОДИФИЦИРОВАННОЙ РАСТВОРИТЕЛЕМ СМОЛЫ И СПОСОБЫ ЕГО ИСПОЛЬЗОВАНИЯ

... 1. Состав, содержащий, по меньшей мере, одну отверждаемую ароматическую эпоксидную смолу, по меньшей мере, один растворитель, наполнитель, представляющий собой коллоидную двуокись кремния, и, по меньшей мере, один компонент, выбранный из группы, состоящей из циклоалифатического эпоксидного мономера, алифатического эпоксидного мономера, гидроксиароматических соединений и их комбинаций и смесей, и где в указанном составе смола дополнительно содержит, по меньшей мере, один компонент, выбранный из группы, состоящей из эпоксидных смол, акрилатных смол, полиимидных смол, фторполимеров, фторированных смол, бензоциклобутеновых смол, бисмалеимидных триазиновых смол, фторированных простых полиаллиловых эфиров, полиамидных смол, полиимидоамидных смол, фенолкрезольных смол, ароматических полиэфирных смол, смол полифениленового эфира и полидиметилсилоксановых смол. 2. Состав по п.1, в котором наполнитель имеет размер частиц приблизительно от 20 нм до 100 нм. 3. Состав по п.1, в котором состав дополнительно ...

Halbleiterbauelement

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

ZUSAMMENSTELLUNGEN UND METHODEN ZUR ANORDNUNG ANISOTROPISCH LEITENDER BAHNEN UND VERBINDUNGEN ZWISCHEN ZWEI SÄTZEN VON LEITERN

Elektronische Schaltungsanordnung

Halbleiteranordnung mit einer Wärmesenke und Herstellungsverfahren der Wärmesenke

Verfahren zum Kapseln intergrierter Schaltungen und über das Verfahren hergestellte integrierte Schaltungsbausteine

Verfahren zum Kapseln integrierter Schaltungen, umfassend: Anbringen einer ersten integrierten Schaltung an einer ersten Fläche eines Substrats mit einer elektrischen Verbindung zwischen entsprechenden Kontakten des Substrats und der ersten integrierten Schaltung; Anbringen einer zweiten integrierten Schaltung an einer zweiten Fläche eines Substrats mit einer elektrischen Verbindung zwischen elektrischen Kontakten des Substrats und der zweiten integrierten Schaltung; und einen Ausformschritt, bei dem die erste und zweite integrierte Schaltung in Harz gekapselt werden.

Einkapselungsverfahren

Verfahren zum Einkapseln eines Halbleiterbauelements, mit den folgenden Schritten: Bereitstellen eines Systemträgers (12), der eine erste Chippadzone und eine zweite Chippadzone aufweist, wobei jede Chippadzone eine erste Seite (60, 62) und eine zweite Seite (70, 72) aufweist, wobei die erste Chippadzone relativ zu der zweiten Chippadzone in der Höhe versetzt ist und wobei die erste Chippadzone und die zweite Chippadzone zusammenhängend sind; Befestigen eines ersten Chips (16) an der ersten Seite (62) der ersten Chippadzone; Befestigen eines zweiten Chips (14) an der ersten Seite (60) der zweiten Chippadzone; Drahtbonden von Drähten an den ersten und zweiten Chip (16, 14); Anordnen eines Gussrahmens gegenüber dem Systemträger (12), um eine Lücke zwischen den zweiten Seiten (72, 70) der ersten und der zweiten Chippadzonen und einer Oberfläche des Gussrahmens zu bilden; und Einkapseln mit einem den ersten Chip (16) und den zweiten Chip (14) überdeckenden Einkapselungsmaterial, das in die ...

ELEKTRONIKGEHÄUSE MIT LEITERRAHMEN MIT VERBESSERTER ADHAESION

Verfahren zur Verstärkung eines Halbleiterwafers und verstärkter Halbleiterwafer

3-DIMENSIONALES GEHÄUSE FÜR MONOLITHISCHE INTEGRIERTE MIKROWELLEN/MILLIMETERWELLETERWELLEN-SCHALTUNGEN

Mit Harz eingekapseltes Halbleiterbauelement

KLEBSTOFFPASTE WELCHE EIN POLYMERES HARZ ENTHÄLT

Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis

Verbindungsverfahren zwischen einer integrierten Schaltung und einem Schaltungsträger und an dieses Verfahren angepasste, integrierte Schaltung

Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung.

Lichtempfindliche Harzzusammensetzung von Positivtyp

Lichtempfindliche Zusammensetzung vom Positivtyp, umfassend: (A) ein Alkali-lösliches Harz mit einer phenolischen Hydroxylgruppe, (B) eine Verbindung, die Säure durch Licht produziert, (C) ein thermisches Vernetzungsmittel und (D) ein Acrylharz, wobei das Alkali-lösliche Harz mit einer phenolischen Hydroxylgruppe ein Phenolharz enthält, das keine ungesättigte Kohlenwasserstoffgruppe enthält und ein modifiziertes Phenolharz, das eine ungesättigte Kohlenwasserstoffgruppe enthält.

Mounting for at least one semiconductor component

The invention relates to a low-capacitance mounting, in particular for lossy semiconductor components, for example IMPATT diodes, which can be manufactured inexpensively. This is achieved with the aid of a diamond body (heat sink) having a trench-like recess containing the connected semiconductor component.

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Leiterplatte für Plastikhalbleitergehäuse

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

VERKAPSELTE ELEKTRONISCHE ANORDNUNG.

Chip-size package production

Production of a semiconductor chip-size housing (CSP) involves (a) bonding conductive wires (45) onto bond pads on a chip (41); (b) placing the chip in an electrolysis cell (55) such that the wire ends are outside the electrolyte solution (50) of the cell; (c) fitting an electroplating electrode (60) on an inner wall of the cell; (d) placing a conductive plate (65) as common electrode on the exposed wire ends; and (e) connecting the conductive plate (65) and the outer wall of the cell (55) to a current source (70). Preferably, the wires (45) consist of gold, the conductive plate (65) consists of copper and the electroplating electrode (60) consists of nickel or gold.

Bond wire clamping and/or motion unit for semiconductor module

The unit includes a clamp (1) with axially protruding jaws (3) and a hollow base body (2). The unit is fitted to a bonding head of a wire bonding set. The jaws (3) are joined by solid hinges (6). A bonding wire (5) is led through the surrounding clamp. The clamp actuation is carried out by piezoelectric or electromagnetic force transmission in the elastic region. The clamp is movable in the longitudinal direction of the bonding wire.

Semiconductor component with chip fastened or bond island

The component has rows of inner terminals (150,152) coupled to numerous outer terminals (160), with the inner terminals electrically coupled to the chip (110) on the bond island (130) with anchoring members (140), from which the terminals are spaced. The chip, inner terminals, and bond island are embedded in a casting substance. At least on one side in the casting substance are located encapsulated blind terminals (154), set in front of the inner terminals. Preferably, the rows of inner terminals are formed at all sides of the bond island at a preset distance to the latter.

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

Metall-Basisplatte wie Wärmesenke für eine Plastikumhüllte Halbleiteranordnung mit erhöhten Teilen zum Löten von Erdschluss-Verbindungsdrähten

Herstellungsverfahren von einer Mehrschichtleiterbahn-Struktur über einer Halbleiteranordung

In ein Gehaeuse eingebauter Hochleistungsgleichrichter

Monolithisch integrierter Mikrowellenverstärker mit hoher Verstärkung

Monolithisch integrierter Mikrowellenverstärker mit hoher Verstärkung

Verfahren zum Herstellen eines Kontakts auf einem Halbleiterbauelement

Haft-Klebemittel-Zusammensetzung für Halbleiter.

Gehäuse einer integrierten Schaltung.

Gehäuse einer integrierten Schaltung.

Verfahren zur Herstellung eines blockförmigen Trägerkörpers für eine Halbleiterkomponente

Chip size semiconductor component

The semiconductor chip (21) carries several beads (22) bonded to the inner ends of the conductive wires (16), in a vertical manner. The entire chip is embedded in synthetic resin (23) such that the outer ends of the conductive wires protrude outwards. Preferably the inner end of the bonded wires, in contact with the chip beads, are shaped as irregular, oval; bonding spheres (25). Typically the outer ends of the protruding conductive vires are bent, directed against the middle of the chip, such as to form L-shaped external conductors.

Wire bonding method for semiconductor device manufacture

The method involves using a capillary driven by a wire bonding apparatus, the capillary having an opening. A distal end of a bonding wire which enters a bonding circuit through the capillary is ultrasonically bonded. The opening forms a substantial part of a nail head bonding point during nail-head bonding.

VERFAHREN ZUM HERSTELLEN EINES THERMOKOMPRESSIONSKONTAKTES

Bauelement mit einem Halbleiterchip und Verfahren zur Herstellung eines Moduls mit gestapelten Bauelementen

Bauelement (300), umfassend: einen Träger (30), ein auf dem Träger (30) abgeschiedenes erstes Material (31), wobei das erste Material (31) einen Elastizitätsmodul von unter 100 MPa aufweist, einen über dem ersten Material (31) platzierten Halbleiterchip (11), ein auf dem Träger (30) und dem Halbleiterchip (11) abgeschiedenes zweites Material (12), wobei das zweite Material (12) einen Elastizitätsmodul von unter 100 MPa aufweist, eine Metallschicht (10) umfassend eine erste Fläche (13) und eine der ersten Fläche (13) gegenüberliegende zweite Fläche (14), wobei die Metallschicht (10) über dem zweiten Material (12) platziert ist und ihre erste Fläche (13) dem zweiten Material (12) zugewandt ist, und mindestens ein Durchgangsloch (38, 39), das von der ersten Fläche (13) der Metallschicht (10) durch das zweite Material (12) und den Träger (30) verläuft.

Verfahren zur Herstellung einer Halbleiter-anordnung

UND VERFAHREN ZU SEINER HERSTELLUNG

METHOD FOR MANUFACTURING A MODULE FOR A FIBER OPTIC LINK

MIKROGEHAEUSE FUER EINEN ELEKTRONISCHEN SCHALTKREIS UND HYBRIDSCHALTKREIS, WELCHER EIN SOLCHES MIKROGEHAEUSE AUFWEIST

Connecting wires for semiconductor device - using wires of copper and tin or similar alloy and connecting to aluminium electrodes

The method of forming a connection between conductor strips (2,3) and a semiconductor device (5) such as a transistor, uses thin conductor wires (8) between the strips and the aluminium zones (6,7) forming the base and emitter electrodes. Instead of using gold conductors, a copper-tin, or a copper-tin-lead or a copper-tin-indium alloy is used. The first alloy has a 20 to 60 percent by weight of copper. The second alloy has a 50/40/10 mixture by weight, and the third alloy also has a 50/40/10 mixture.

Method of producing a semiconductor device

The invention relates to a method of producing a semiconductor device from a semiconductor wafer containing a multiplicity of semiconductor devices. According to the invention, a grid-type partitioning which corresponds to the grid-type partitioning of the front is applied to the back of the semiconductor wafer. Gold contact layers separated from one another by the grid-type partitioning are deposited inside the units of the grid. Finally, the semiconductor wafer is divided up along the gold-free grid lines between the individual elements.

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

IC-Baugruppe und Verfahren zur Herstellung einer IC-Baugruppe

IC-Baugruppe bzw. integrierter Schaltungsbaustein, umfassend: eine integrierte Schaltung mit einer Oberfläche bzw. -fläche, die wenigstens teilweise von einer Metallschicht bedeckt ist; wenigstens einen Verbindungspunkt; wenigstens einen Verbinder, der die integrierte Schaltung mit dem oder jedem Verbindungspunkt elektrisch verbindet; ein Verkapselungsmaterial, das den oder jeden Verbinder, wenigstens einen Teil der integrierten Schaltung und wenigstens einen Teil des oder jedes Verbindungspunktes derart verkapselt, dass eine Kontaktoberfläche bzw. -fläche des oder jedes Verbindungspunktes und die Metallschicht auf der integrierten Schaltung außerhalb des Verkapselungsmaterials freiliegen.

Anschlussrahmen für ein Halbleiterbauelement

Anschlussrahmen für ein Halbleiterbauelement mit: einem Anschlussrahmenkörper; und mehreren Metallbeschichtungen, die eine Silber- oder Silberlegierungsbeschichtung aufweisen und die auf den Anschlussrahmenkörper aufgebracht sind, wobei die Silber- oder Silberlegierungsbeschichtung eine äußerste Metallbeschichtung eines vorbestimmten Teiles des Anschlussrahmens ist, und wobei der vorbestimmte Teil von einem Gehäuse des Halbleiterbauelements zu umschließen ist.

Verfahren zum Erreichen einer selektiven Adhäsionshemmung und -steuerung in Dickschicht-Leitern.

Anschlussrahmen für Harz-Halbleiterverpackungen

Verfahren zur Befestigung einer metallischen Kontakt-Elektrode an dem Koerper aus halbleitendem Material einer Halbleiteranordnung

ELEKTRONISCHE INTEGRIERTE SCHALTUNG MIT MINDESTENS EINEM ELEKTRONISCHEN BAUELEMENT

Bauelement mit empfindlichen Bauelementstrukturen und Verfahren zur Herstellung

Elektrisches Bauelement,- mit einem Substrat, das ein Material mit pyroelektrischen oder piezoelektrischen Eigenschaften umfasst- mit auf der Oberfläche des Substrats angeordneten elektrischen Leiterbahnen (LB) und zumindest drei elektrisch leitenden Bauelementstrukturen (BS1, BS2, BS3), die gegenüber einer Spannung empfindlich oder durch einen elektrischen Überschlag gefährdet sind,- bei dem in einer Vorstufe des Bauelements die zumindest drei Bauelementstrukturen (BS1, BS2, BS3) jeweils über zumindest eine der elektrischen Leiterbahnen (LB) mit einer von zumindest drei elektrischen Anschlussflächen (AF1, AF2, AF3), die von außen zugänglich sind, verbunden sind- bei dem je zwei der Anschlussflächen mittels einer der zumindest zwei Shuntleitungen (SL1, SL2) kurzgeschlossen sind, wobei jede der zumindest zwei Shuntleitungen (SLi, SL2) mindestens einen Abschnitt mit verringertem Querschnitt gegenüber den elektrischen Leiterbahnen aufweist.

MIKROWELLEN-/MILLIMETERWELLEN-SCHALTUNGSSTRUKTUR MIT EINZELN MONTIERTEN ELEMENTEN VOM FLIPCHIPTYP UND HERSTELLUNGSVERFAHREN DAFÜR

Verfahren zur Bildung eines Metallfilms

Verfahren zur Bildung eines Metallfilms auf einer nicht durch einen Schaltkreis gebildeten Oberfläche eines Halbleiter-Wafers, das folgende Schritte umfasst: (i) Aufbringen einer Klebefolie auf eine durch einen Schaltkreis gebildete und nicht durch einen Metallfilm gebildete Oberfläche eines Halbleiter-Wafers, wobei die Klebefolie einen Basisfilm und eine auf einer Oberfläche davon aufgebrachte Klebstoffschicht umfasst, und der Basisfilm wenigstens eine Filmschicht aufweist, die ausgewählt ist aus einer Metall-Filmschicht, einer Metalloxid-Filmschicht und einem flüssigkristallinen Polymerfilm, und die eine Gastransmissionsrate von 49,35 ml/m2·Tag/MPa (5,0 cm3/m2Tagatm) aufweist; und (ii) Ausbilden eines Metallfilms auf der Oberfläche des Halbleiter-Wafers, auf der die Klebefolie nicht aufgebracht ist.

Leiterplatten mit selbsttragender Verbindung zwischen den Seiten.

Elektrischer Schaltungsapparat

Rechteckiger Torustransformator für integrierte Hybridschaltungen

Verfahren zur automatischen Bandmontage.

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Herstellungsverfahren für ein Deckelmaterial für eine Verpackung für elektronische Komponente

System und Verfahren zur Verstärkung einer Anschlussfläche

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

Halbleiteranordnung mit Leiterrahmen

Mehrschichtige keramische Platine, Verfahren zu ihrer Herstellung und ihre Anwendung.

Verfahren zum Herstellen einer Halbleiteranordnung.

Verfahren zum Montieren von Halbleiterelementen

HERSTELLUNG EINER MEHRSCHICHTIGEN LEISTUNGSHALBLEITERSCHALTUNG MIT MEHRFACHEN PARALLELEN KONTAKTFINGERN.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Vorrichtung und Verfahren zum Verbinden von Komponenten

Vorrichtung zum Verbinden von mindestens zwei Komponenten, wobei die Vorrichtung ein Ober- (96) und ein Unterwerkzeug (95) aufweist, wobei das Unterwerkzeug (95) die mindestens zwei Komponenten (3, 2, 21, 22, 23, 1, 11, 12, 13) umfasst, wobei eine erste Komponente (3) die mindestens eine zweite Komponente (2, 21, 22, 23, 1, 11, 12, 13) mit einem zumindest teilweisen Überlapp relativ zur ersten Komponente (3) trägt; das Unterwerkzeug (95) und das Oberwerkzeug (96) relativ zueinander bewegt werden können; das Oberwerkzeug (96) mindestens zwei heizbare Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) umfasst, die so verbunden sind, dass sie sich relativ zueinander über ein abgedichtetes Druckkissen (5) bewegen können; wobei die Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) und das Druckkissen (5) zwischen sich eine erste flexible Schicht (6) aufweisen; dadurch gekennzeichnet, dass zwischen dem Oberwerkzeug (96) und dem Unterwerkzeug...

Electronic component used as a semiconductor wafer comprises a semiconductor chip having contact surfaces of an integrated circuit on its active surface, and a bimetallic strip arranged on the contact surfaces

Electronic component comprises: a semiconductor chip (2) having contact surfaces (4) of an integrated circuit on its active surface (3); and a bimetallic strip (5) arranged on the contact surfaces and having a fixed end (6) connected to the contact surface and a flexible free end (7) protruding from the active surface of the chip. Preferred Features: An angled bimetallic strip is arranged on the contact surfaces. The free end of the bimetallic strip has a coating made from gold or a gold alloy, or silver alloy. The bimetallic strip is made from a copper alloy and an aluminum alloy.

Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Modul für elektronische Komponente

Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung

Halbleiterchip (1) mit einer haftvermittlungsschichtfreien Dreischichtmetallisierung (2) bestehend aus einer Aluminiumschicht (4), die direkt auf dem Halbleiterchip (1) aufgebracht ist, einer Diffusionssperrschicht (5), die direkt auf der Aluminiumschicht (4) aufgebracht ist, einer Lotschicht (6), die direkt auf die Diffusionssperrschicht (5) aufgebracht ist, wobei, die Diffusionssperrschicht (5) Ti, Ni, Pt oder Cr ist, und die Lotschicht (6) eine Diffusionslotschicht ist, die AuSn, AgSn oder CuSn aufweist, und wobei der Halbleiterchip (1) eine aktive Oberseite (16) und eine passive Rückseite (3) aufweist, und wobei alle drei Schichten in einer Prozessabfolge auf der passiven Rückseite (3) aufgesputtert sind.

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

Halbleiterbauteil mit einem vertikalen Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Halbleiterbauteil (1; 25) weist ein vertikales Halbleiterbauelement (2), eine erste Metallisierung (8) und eine zweite Metallisierung (13) auf. Die zweite Metallisierung (13) weist eine einstückige Folie mit einem ersten Ende (14) mit einer ersten Kontaktfläche (17), einem Zwischenbereich (15) und einem zweiten Ende (16) mit einer zweiten Kontaktfläche (19) auf. Die erste Kontaktfläche (17) ist auf der Rückseite (6) des Halbleiterbauelements (2) angeordnet und die zweite Kontaktfläche (19) ist im Wesentlichen in der Ebene der Außenkontaktfläche (12) der ersten Metallisierung (8) angeordnet und sieht eine Außenkontaktfläche (12) vor. Die erste Kontaktfläche (17) und die zweite Kontaktfläche (19) sind auf gegenüberliegenden Oberflächen der Folie der zweiten Metallisierung (13) angeordnet.

Mehrchipgehäuse und Verfahren zum Bilden von Mehrchipgehäusen für eine ausgeglichene Leistung

Ein Verfahren zum Bilden von Mehrchipgehäusen, mit folgenden Schritten: Positionieren einer ersten integrierten Schaltung (202) in einer mit der Vorderseite nach oben zeigenden Position über einem Substrat (204), das eine erste Substratoberfläche definiert und eine Mehrzahl von Kontaktbereichen (216, 218) aufweist, wobei in der mit der Vorderseite nach oben zeigenden Position eine erste Oberfläche der ersten integrierten Schaltung (202) und die erste Substratoberfläche in einer einander zugewandten Beziehung sind und eine zweite Oberfläche der ersten integrierten Schaltung (202) von dem Substrat (204) abgewandt ist; wobei die erste integrierte Schaltung (202) eine erste Mehrzahl von Anschlussflächen (312) aufweist, die auf der zweiten Oberfläche der ersten integrierten Schaltung (202) angeordnet sind; Positionieren zumindest eines Abschnitts einer zweiten integrierten Schaltung (206) über zumindest einem Abschnitt der ersten integrierten Schaltung (202), so dass die zweite Oberfläche der ...

Verfahren zum Herstellen von Leitungsverbindungen an elektronischen schaltelementen

Electronic power package for e.g. diode, has two non-planar insulating substrates connected in connection regions, so that mechanical separation between substrates is controlled by number, arrangement, design and material of regions

The package (100) has two non-planar insulating substrates (1, 2) with high thermal conductivity. Electronic components e.g. semiconductor power transistor chip (20) and diode chip (30), are attached on each of the substrates. The substrates are connected with each other in connection regions, so that a mechanical separation between the substrates is controlled by the number of connection regions, an arrangement of connection regions, and design and material of the connection regions. The mechanical separation supplies an axially directed net compression force into the electronic components.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle und zugehöriges Herstellungsverfahren

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle, mit - einem Halbleitersubstrat (200), - einer auf dem Halbleitersubstrat ausgebildeten Substruktur (205), - einer dielektrischen Zwischenebenenschicht (208) auf der Substruktur, wobei die dielektrische Zwischenebenenschicht eine darin ausgebildete Kontaktöffnung (210) beinhaltet, und - einem Kontaktstift (214), der in der Kontaktöffnung ausgebildet ist, dadurch gekennzeichnet, dass - die Kontaktöffnung (210) aus einer Mehrzahl von separaten Punkten gebildet ist, die miteinander verbunden werden.

Elektronisches Bauelement und Verfahren zur Herstellung eines elektronischen Bauelements

Es handelt sich um ein elektronisches Bauelement (100a, 100b, 200), insbesondere ein optoelektronisches Bauelement. Das elektronische Bauelement weist ein Substrat (124, 224) mit mindestens einer Halbleiterchip-Kontaktschicht (110a, 110b, 210) auf. Auf der Halbleiterchip-Kontaktschicht (110a, 110b, 210) ist ein Halbleiterchip (102, 202) angeordnet. Zwischen der Halbleiterchip-Kontaktschicht (110a, 110b, 210) und einer dem Substrat (124, 224) zugewandten Kontaktfläche (104, 204) des Halbleiterchips (102, 202) ist eine Poren aufweisende Verbindungsschicht (106, 206) angeordnet.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Resin-Encapsulated Semiconductor Device

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Stacked semiconductor package and method of fabricating the same

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Leadframe for ic package and method of manufacture

A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

Semiconductor device

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

Chip having a driving integrated circuit

A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Semiconductor device

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Electronic component mounting method and electronic component mount structure

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Anti-tamper microchip package based on thermal nanofluids or fluids

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Composite alloy bonding wire and manufacturing method thereof

A manufacturing method for a composite alloy bonding wire and products thereof. A primary material of Ag is melted in a vacuum melting furnace, and then a secondary metal material of Pd is added into the vacuum melting furnace and is co-melted with the primary material to obtain an Ag—Pd alloy solution. The obtained Ag—Pd alloy solution is drawn to obtain an Ag—Pd alloy wire. The Ag—Pd alloy wire is then drawn to obtain an Ag—Pd alloy bonding wire with a predetermined diameter.

Light emitting diode package

An exemplary light emitting diode (LED) package includes a substrate, an LED chip mounted on the substrate, and a wire. The LED chip includes a semiconductor structure and an electrode disposed on the semiconductor structure. The wire electrically connects the electrode of the LED chip to an electrical portion of the substrate. The wire has a first joint and a second joint connected to the substrate. The wire forms a first curved portion between the electrode and the first joint and a second curved portion between the first joint and the second joint.

Bond pad for wafer and package for cmos imager

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Chip package and manufacturing method thereof

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Method for manufacturing semiconductor device

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Laser ashing of polyimide for semiconductor manufacturing

A method for laser ashing of polyimide for a semiconductor manufacturing process using a structure, the structure comprising a supporting material attached to a semiconductor chip by a polyimide glue, includes releasing the supporting material from the polyimide glue, such that the polyimide glue remains on the semiconductor chip; and ashing the polyimide glue on the semiconductor chip using an ablating laser.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Semiconductor device with nested rows of contacts

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

Display Device and Method of Fabricating the Same

A driver circuit for use with a passive matrix or active matrix electro-optical display device such as a liquid crystal display is fabricated to occupy a reduced area. A circuit (stick crystal) having a length substantially equal to the length of one side of the matrix of the display device is used as the driver circuit. The circuit is bonded to one substrate of the display device, and then the terminals of the circuit are connected with the terminals of the display device. Subsequently, the substrate of the driver circuit is removed. The driver circuit can be formed on a large-area substrate such as a glass substrate, while the display device can be formed on a lightweight material having a high shock resistance such as a plastic substrate.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Method for semiconductor leadframes in low volume and rapid turnaround

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Semiconductor device and method of forming the same

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Brace for long wire bond

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Mold release film and process for producing light emitting diode

To provide a mold release film for producing a light emitting diode by a mold, which is less susceptible to formation of pin holes or rupture and which is applicable to mass production of a light emitting diode by means of a mold having a plurality of cavities, and a process for producing a light emitting diode by means of such a mold release film. A mold release film to be disposed on the cavity surface of a mold to form a substantially hemispherical lens portion by encapsulating a light emitting element of a light emitting diode with an encapsulation resin, which release film has a thickness of from 16 to 175 μm and a tensile rupture elongation of from 600 to 3,000% at 110° C. as measured in accordance with JIS K7127, and a process for producing a light emitting diode by means of such a mold release film.

Packaged semiconductor chips with array

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Semiconductor package and manufacturing method therefor

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Substrate bonding method and semiconductor device

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Wiring board and method of producing the same

A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.

Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts

A test fixture ( 120 ) is disclosed for electrically testing a device under test ( 130 ) by forming a plurality of temporary mechanical and electrical connections between terminals ( 131 ) on the device under test ( 130 ) and contact pads ( 161 ) on the load board ( 160 ). The test fixture ( 120 ) has a replaceable membrane ( 150 ) that includes vias ( 151 ), with each via ( 151 ) being associated with a terminal ( 131 ) on the device under test ( 130 ) and a contact pad ( 161 ) on the load board ( 160 ). In some cases, each via ( 151 ) has an electrically conducting wall for conducting current between the terminal ( 131 ) and the contact pad ( 161 ). In some cases, each via ( 151 ) includes a spring ( 152 ) that provides a mechanical resisting force to the terminal ( 131 ) when the device under test ( 130 ) is engaged with the test fixture ( 120 ).

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Adhesive film for light emitting device and method of manufacturing led package using the same

Provided is an adhesive film for an LED chip, including: a double-sided adhesive layer having the LED chip adhered to an upper surface thereof and a lead frame adhered to a lower surface thereof; an ultraviolet (UV) cured layer adhered to one surface of the double-sided adhesive layer; and upper and lower cover layers respectively adhered to faces exposed to the exterior of the double-sided adhesive layer and the UV cured layer.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure

A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Ohmic connection using widened connection zones in a portable electronic object

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Chip package structure

The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

Reprogrammable circuit board with alignment-insensitive support for multiple component contact types

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Semiconductor package and method for manufacturing the same

Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member.