Integrierter Schaltkreis mit implementierter, FeRAM-basierender RFID

Integrierter Schaltkreis (IC), enthaltend: einen Festkörperschaltungsbereich hoher Kapazität, der dazu konfiguriert ist, vorbestimmte Operationen auszuführen; einen RFID-Block mit einem FeRAM-Block zum Speichern von Daten; eine Schnittstelleneinheit, die dazu konfiguriert ist, eine von außen bereitgestellte eindeutige ID zum drahtlosen Identifizieren des IC zum RFID-Block zu übertragen, wobei die eindeutige ID im FeRAM-Block gespeichert wird, und eine Leiterbahn, die sich durch vorbestimmte Bereiche des IC erstreckt und als eine Antenne für den RFID-Block gestaltet ist, wobei der RFID-Block dazu konfiguriert ist, über die Antenne Information zu empfangen und zu einer äußeren Quelle zu senden.

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Organisches Antireflex-Beschichtungspolymer, Antireflex-Beschichtungszusammensetzung und Verfahren zur Herstellung derselben

Verbindung mit der Struktur der folgenden Formel 1: wobei gilt: R, R' und R'' sind jeweils unabhängig aus der Gruppe ausgewählt, die aus Wasserstoff und Methyl besteht; Ra bis Rd und R1 bis R18 sind jeweils unabhängig aus der Gruppe ausgewählt, die aus -H, -OH, -OCOCH3, -COOH, -CH2OH oder Alkyl mit 1 bis 5 Kohlenstoffatomen und Alkoxy-Alkyl mit 1 bis 5 Kohlenstoffatomen besteht; m und n stellen eine ganze Zahl dar, die aus der Gruppe ausgewählt ist, die aus l, 2, 3, 4 und 5 besteht; x, y und z stellen jeweils einen Molenbruch im Bereich von 0,01 bis 0,99 dar.

Einschaltsignalgenerator für Halbleiterspeichereinrichtungen

Einschaltsignalgenerator für eine Halbleiterspeichereinrichtung, welcher aufweist: einen Einschaltdetektor zum Erzeugen eines Einschaltdetektiersignals durch eine externe Versorgungsspannung; einen Einschaltsignalgenerator für einen Tiefenabschaltvorgang zum Erzeugen eines Tiefenabschaltvorgangs-Einschaltsignals als Antwort auf das Einschaltdetektiersignal; einen Einschaltsignalgenerator zum Erzeugen eines Einschaltsignals als Antwort auf das Einschaltdetektiersignal; und ein Einschaltsteuergerät zum Bestimmen, ob das Einschaltsignal beim Eintritt in einen Tiefenabschaltvorgang freigegeben wird oder nicht, wobei der Einschaltsignalgenerator für den Tiefenabschaltvorgang das Tiefenabschaltvorgangs-Einschaltsignals erzeugt, welches immer beim Eintritt in den Tiefenabschaltvorgang und beim Austritt aus dem Tiefenabschaltvorgang durch die externe Versorgungsspannung freigegeben wird, wobei das Einschaltsteuergerät die externe Versorgungsspannung beim Eintritt in den Tiefenabschaltvorgang blockiert ...

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements mit den Schritten: Bilden einer ersten Zwischenschichtisolationsschicht auf einem Halbleitersubstrat, in welchem eine Verbindungsregion und eine Gate-Elektrodenstruktur für SSL einer Zellenregion gebildet werden; Strukturieren der ersten Zwischenschichtisolationsschicht, um ein Source-Kontaktloch zu bilden, durch welches die Verbindungsregion für die SSL auf einer Seite der Gate-Elektrodenstruktur für SSL exponiert wird; Bilden einer Schicht auf der gesamten Oberfläche, einschließlich des Source-Kontaktlochs; Ausführen eines Polierprozesses bis die erste Zwischenschichtisolationsschicht exponiert ist, um einen Source-Kontakt zu bilden; Bilden einer zweiten Zwischenschichtisolationsschicht auf der gesamten Oberfläche einschließlich des Source-Kontakts; Strukturieren der zweiten Zwischenschichtisolationsschicht, um die in einer peripheren Region des Halbleitersubstrats gebildeten ersten Verbindungsregionen zu exponieren ...

METHOD FOR MANUFACTURING A CAPACITOR CAPABLE OF PREVENTING THE NOT-OPEN OF A HOLE AND THE LOSS OF A SEPARATION FILM

PURPOSE: A method for manufacturing a capacitor is provided to prevent the bridge of a storage node by eliminating the bowing of a hole using a capping layer. CONSTITUTION: A first separation film, a supporting member, and a second separation film are laminated at the upper part of a substrate(21). The second separation film, the supporting member, and the first separation film are successively etched by an etching barrier wall and a hole(29) is formed in a hard mask film pattern(27). A capping layer(30A) is formed for covering the sidewall of the hole and the surface of the hard mask film pattern. A conductive film is formed for filling the hole on the capping layer. The conductive film is etched back and a storage node(32A) is formed. COPYRIGHT KIPO 2012 ...

SEMICONDUCTOR DEVICE AND A FORMING METHOD THEREOF CAPABLE OF IMPROVING INTERFACE RESISTANCE BETWEEN A POLY SILICON LAYER AND A CONDUCTIVE LAYER

PURPOSE: A semiconductor device and a forming method thereof are provided to prevent metal from being spread from an interface resistance improving layer and a poly silicon layer by making the poly silicon layer amorphous before the interface resistance improving layer is deposited. CONSTITUTION: A gate insulating layer(103) is formed on a semiconductor substrate(101). A poly silicon layer(105) for a gate electrode is formed on the upper side of the gate insulating layer. A poly silicon layer becomes amorphous. An interface resistance improving layer and a conductive layer are laminated on the amorphous poly silicon layer. A hard mask layer and a photoresist pattern are laminated on the conductive layer. COPYRIGHT KIPO 2012 ...

INTERNAL VOLTAGE GENERATOR AND A SEMICONDUCTOR APPARATUS USING THE SAME, CAPABLE OF REDUCING CURRENT CONSUMPTION

PURPOSE: An internal voltage generator and a semiconductor apparatus using the same are provided to reduce unnecessary current consumption by including a voltage control signal generator. CONSTITUTION: In an internal voltage generator and a semiconductor apparatus using the same, a first internal voltage generating unit(100) generates a first internal voltage. The voltage level of the first internal voltage is controlled by a voltage control signal. A second internal voltage generating unit(200) regulates a first internal voltage. The second internal voltage generating unit generates a plurality of second internal voltages. A voltage control signal generating unit(300) generates the voltage control signal. COPYRIGHT KIPO 2011 ...

THERMAL CODE OUTPUT CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCURATELY MEASURING A THERMAL CODE

PURPOSE: A thermal code output circuit and a semiconductor memory device are provided to accurately measure a thermal code by outputting a strobing signal capable of strobing the thermal code through a pad. CONSTITUTION: A thermal code output circuit includes a pulse signal generating part(2), a thermal code output part(3), and a strobing signal output part(4). The pulse signal generating part generates a pulse signal after receiving a plurality of period signals in response to a test mode signal. The thermal code output part outputs a plurality of thermal codes in response to the pulse signal. The strobing signal output part selectively outputs a pulse signal or a reference voltage as a strobing signal in response to a test mode signal. COPYRIGHT KIPO 2010 ...

INTERNAL VOLTAGE GENERATOR FOR A SEMICONDUCTOR IC, CAPABLE OF IMPROVING THE RELIABILITY AND STABILITY OF THE SEMICONDUCTOR

PURPOSE: An internal voltage generator for a semiconductor IC is provided to generate a stable negative internal voltage by offsetting a non-linear region in which an internal voltage is generated. CONSTITUTION: In an internal voltage generator for a semiconductor IC, a first feedback(212) divides a positive internal voltage by a first division ratio. A first feedback unit feeds back a first division voltage. A first voltage drive unit(214) decides the level of the feedback division voltage. The first voltage drive unit drives a positive internal voltage terminal. A second feedback unit(222) feeds back a second division voltage by a second division ratio. A second voltage drive unit(224) decides the level of the second division voltage feedback. The second voltage drive unit drives a negative internal voltage terminal. COPYRIGHT KIPO 2011 ...

METHOD FOR FORMING A NONVOLATILE MEMORY DEVICE CAPABLE OF PREVENTING THE DETERIORATION OF A THRESHOLD VOLTAGE DISTRIBUTION PROPERTY

PURPOSE: A method for forming a nonvolatile memory device is provided to improve the density of impurity ions lost in a charge storing layer by diffusing impurity ions to a charge trapping layer. CONSTITUTION: A tunnel insulation layer(103) is formed on the upper side of a semiconductor substrate(101). A charge trapping layer(105) including impurity ions is formed on the upper side of the tunnel insulation layer. A compensation layer(113) including an impurity ion of higher density than the impurity ions of the charge trapping layer is formed on the upper side of the charge trapping layer. The impurity ion of the compensation layer is diffused to the charge trapping layer. The compensation layer is removed. A dielectric layer is formed on the surface of the charge trapping layer. COPYRIGHT KIPO 2011 ...

METHOD FOR SEPARATING A MASK LAYOUT CAPABLE OF INCREASING ETCHING BIAS UNIFORMITY

PURPOSE: A method for separating a mask layout is provided to increase DOF(Depth of Focus), EL(Energy Latitude), and MEF(Mask Error Factor) process margins, thereby enhancing the properties and reliability of a device. CONSTITUTION: A design pattern layout is divided into first and second backup mask layouts(S100). The first backup mask layout is combined with an under-sized second backup mask layout to determine a first mask layout(S110). The second backup mask layout is combined with an under-sized first backup mask layout to determine a second mask layout(S120). Stitching, OPC(Optical Proximity Correction), and MRC(Mask Rule Check) are performed on the first and second mask layouts. The first and second mask layouts are verified(S140). COPYRIGHT KIPO 2012 ...

NEGATIVE VOLTAGE GENERATION CIRCUIT CAPABLE OF REGULARLY MAINTAINING CURRENT SUPPLY CAPABILITY OF NEGATIVE VOLTAGE, AND A SEMICONDUCTOR MEMORY DEVICE USING THE SAME

PURPOSE: A negative voltage generation circuit and a semiconductor memory device using the same are provided to improve operational stability by constantly guaranteeing current supply capability of negative voltage. CONSTITUTION: A cycle variable oscillator(100) generates an oscillator signal in response to a sensing signal. The cycle variable oscillator decides a cycle of the oscillator signal in response to a control signal. The cycle variable oscillator generates the oscillator signal of a short cycle in an enable state of the control signal. A pump(200) performs a pumping operation in response to the oscillator signal. The pump generates negative voltage by the pumping operation. A negative voltage sensing portion(300) generates the sensing signal by sensing a negative voltage level. A gate organic current sensor(400) generates the control signal by measuring the amount of gate organic currents. COPYRIGHT KIPO 2010 ...

NON-VOLATILE MEMORY DEVICE FOR IMPROVING DATA MAINTAINING CHARACTERISTICS BY PREVENTING A UNIT CELL BEING DETERIORATED AND A FORMING METHOD THEREOF

PURPOSE: A non-volatile memory device and a forming method thereof are provided to secure safe cell operation using a metal layer which is the same affiliation with a ferroelectric layer. CONSTITUTION: A metal layer(10) includes a source area(S) and a drain area(D) which is formed in a channel area(CN) and the both ends of the channel area. A supporting substrate which supports the metal layer is formed in the lower part of the metal layer. A ferroelectric layer(11) is formed in the upper part of the channel area on the metal layer. A plate line(12) is formed on the top of the ferroelectric layer. The widths of the both sides of the metal layer are formed to be broader than that of a plate line on the ferroelectric layer. COPYRIGHT KIPO 2012 ...

Method for manufacturing semiconductor device

Memory device capable of changing data output mode

Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output mode. As such, two kinds of output mode circuits can be tested in one test equipment. Accordingly, test efficiency can be enhanced and costs can be saved.

Module substrate that allows replacement of faulty chips, semiconductor module having the same, and method for manufacturing the semiconductor module

Semiconductor device including ruthenium electrode and method for fabricating the same

Digital dll apparatus for correcting duty cycle and method thereof

Semiconductor package and method for manufacturing the same

Method of forming a micro pattern of a semiconductor device

Method for forming fine pattern of semiconductor device

Locking state detector and DLL circuit having the same

A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Method for operating page buffer of nonvolatile memory device

A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is carried out using one among several latch circuits included in the page buffer. The method activates a first latch circuit while inactivates a second latch circuit, in a copy-back programming operation, and activates the first and second latch circuits in programming, reading, and verifying operations.

3-dimensional substrate for embodying multi-packages and method of fabricating the same

A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Reset signal generator and a method for generating reset signal of a semiconductor integrated circuit

A reset signal generator of a semiconductor integrated circuit includes a counter that counts a clock signal in response to activation of a power-up signal and activates a count-result signal when the counted value reaches a target value, and a reset signal generating unit that activates a reset signal in response to the activation of the count result signal.

Semiconductor device having an under stepped gate for preventing gate failure and method of manufacturing the same

A semiconductor device and a method of manufacturing the same capable of preventing a not open fail of a landing plug contact caused by the leaning of a gate. The method includes the steps of preparing a semiconductor substrate, forming first recesses by etching an active area of the semiconductor substrate, filling a conductive layer in the first recesses, forming a second recess by etching a predetermined part of the active area, forming under stepped gates, forming a gate insulating layer on a surface of the semiconductor substrate, forming a channel layer on the gate insulating layer, forming source/drain areas in the semiconductor substrate, forming an interlayer insulating film on an entire surface of the semiconductor substrate, and forming a landing plug in the interlayer insulating film such that the landing plug makes contact with the source/drain areas, respectively.

Flash Memory Device And A Method Of Fabricating The Same

The invention relates to a flash memory device and its method of fabrication. The method includes the steps of: forming gate protection patterns over a peripheral region of a semiconductor substrate; forming a tunnel insulating film over the semiconductor substrate; forming a first conductive film over the tunnel insulating film between adjacent gate protection patterns; forming a dielectric film over the first conductive film and the gate protection patterns; etching a portion of the dielectric film in the peripheral region to expose a portion of the first conductive film between adjacent gate protection patterns; forming a second conductive film over the dielectric film and the first conductive film; and etching the second conductive film, the dielectric film the first conductive film, the tunnel insulating film and the gate protection patterns to form a gate, wherein the gate protection patterns remain on the sidewalls of the first conductive film and the tunnel insulating film in the ...

Blank Mask and Method for Fabricating Photomask Using the Same

A photomask is formed on an etch target layer of a transparent substrate using a blank mask that includes a carbon layer and an oxide layer. The carbon layer and the oxide layer are disposed on the etch target layer. The oxide layer is formed into an oxide layer pattern by photolithography for selectively exposing the etch target layer. A carbon layer pattern is formed by etching the carbon layer using the oxide layer pattern. An etch target layer pattern is formed by etching the etch target layer using the carbon layer pattern as a hard mask. Therefore, a sufficient thickness of the carbon layer can be etched using a thin oxide layer pattern employing the etch selectivity characteristics of the oxide layer and the carbon layer. Furthermore, the etch target layer pattern can have a predetermined vertical profile. The carbon layer pattern can be removed using oxygen plasma without damaging the underlying etch target layer pattern.

Address Path Circuit with Row Redundant Scheme

An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address, a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection, an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address, and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address.

Semiconductor device

A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state.

Circuit for controlling pulse width

Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Method of Fabricating Semiconductor Device

This patent relates to a method of fabricating a semiconductor device. Gate insulating layer patterns and gate electrode layer patterns may be formed over a semiconductor substrate. A photoresist pattern through which part of a region between the gate electrode layer patterns is exposed may be formed over the semiconductor substrate including the gate electrode layer patterns. A passivation film, having an etch rate slower than that of the semiconductor substrate, may be formed on the photoresist pattern. A first trench may be formed in the semiconductor substrate using an etch process by employing the passivation film and the photoresist pattern as an etch mask. An ion implantation process may be performed on the semiconductor substrate in which the first trench is formed.

Semiconductor memory device capable of controlling tAC timing and method for operating the same

A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.

Semiconductor memory device with advanced refresh control

A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank; and a bank refresh block for supporting a refresh operation performed in sequence to each bank in response to the refresh information of each bank.

Semiconductor memory device

A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second local lines is connected to the pair of first local lines by a second switching unit. A writing driver drives the second local lines using a normal-driving voltage in response to a data signal through a global line. The writing driver drives the second local lines using an over-driving voltage having a higher level than that of the normal-driving voltage during a predetermined period.

BINARY MASK, METHOD FOR FABRICATING THE BINARY MASK, AND METHOD FOR FABRICATING FINE PATTERN OF SEMICONDUCTOR DEVICE USING BINARY MASK

Provided are a binary mask, a method for fabricating the binary mask, and a method for fabricating a fine pattern of semiconductor device. In the method for fabricating the fine pattern, a binary mask including phase shift layer patterns is prepared on a transparent substrate. A semiconductor substrate including an etch objective layer and a resist layer is prepared. An exposure operation using the binary mask and a light source of a short wavelength is performed to transfer the phase shift layer patterns of the binary mask onto the resist layer of the semiconductor substrate. The resist layer to which the patterns have been transferred is developed to form resist layer patterns selectively exposing the etch objective layer. Exposed portions of the etch objective layer are etched using the resist layer patterns as an etch mask to form etch objective layer patterns. The resist layer patterns are removed.

Method for fabricating SRAM cell

A method of fabricating the SRAM cell is disclosed. The method includes forming a gate on a substrate, forming an oxidation barrier film on side portions of the gate, oxidizing the resultant structure by using an oxidation process to form an oxide film on a top surface of the gate, implanting high density impurity ions to the substrate to form a lightly doped region and a highly doped region in the substrate at side portions of the gate, forming an insulating layer over the substrate to define a contact hole that exposes portions of the gate and the highly doped region, and forming an interconnect in the contact hole to connect the gate and the highly doped region.

Low power type Rambus DRAM

Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

Semiconductor memory device and method for operating the same

A semiconductor device includes a plurality of input units configured to receive a plurality of data, a plurality of latching units configured to latch output signals of the plurality of input units in response to a plurality of synchronization clock signals, and a synchronization clock generating unit configured to delay a source clock signal by a time corresponding to each of signal transmission times taken between the plurality of input units and the plurality of latching units, thereby generating the plurality of synchronization clock signals.

Internal voltage generating circuit

An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Apparatus and method for controlling refresh operation of semiconductor integrated circuit

A semiconductor memory integrated circuit for controlling a refresh operation includes: a first period generating unit that generates a first periodic signal having an uniformed period; a second period generating unit that generates a second periodic signal according to a first control signal; a period generation control unit that generates a timing signal for every predetermined period; a frequency dividing unit that divides the frequency of the first periodic signal into at least one frequency-divided periodic signals; and a period selection control unit that controls the operation of the second period generating unit according to the at least one frequency-divided periodic signals and the second periodic signal, determines temperature, and outputs one of the frequency-divided periodic signals corresponding to the determined temperature as a refresh signal.

Method of fabricating a flash memory device

In a method of fabricating a flash memory device, a lower capping conductive layer of a peri region is patterned. A step formed between a cell gate and a gate for a peri region transistor is decreased by controlling a target etch thickness of a hard mask. Thus, an impurity does not infiltrate into the bottom of the gate for the peri region transistor through a lost portion of a SAC nitride layer. Accordingly, a hump phenomenon of the transistor formed in the peri region can be improved. Furthermore, a leakage current characteristic of the transistor formed in the peri region can be improved.

DLL driver control circuit

A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.

Semiconductor device and method for fabricating the same

A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Method of manufacturing a capacitor in a semiconductor device

There is disclosed a method of manufacturing a capacitor in a semiconductor device. The present invention forms a Ru film as a lower electrode of the capacitor in which a Ta2O5 film is used as a dielectric film by introducing Ru of a raw material, oxygen and NH3 in order to reduce oxygen or a NH3 plasma process as a subsequent process is performed in order to remove oxygen existing on the surface of the Ru film. Therefore, the present invention can prevent oxidization of a diffusion prevention film due to oxygen existing in a Ru film during annealing process performed after deposition of a Ta2O5 film and thus improve reliability of the device.

Method of forming bit line of semiconductor device

A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Method for forming capacitor of ferroelectric random access memory

Methods for forming capacitor of FeRAM are disclosed. The disclosed methods can prevent the step difference from an etch-back process and scratch on a Pt layer in a CMP process using a basic slurry by performing a CMP process using an acidic slurry including an organic acid when isolating a storage electrode in a formation process of a FeRAM capacitor.

Method for fabricating a MOSFET device

Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.

Flash memory device being programmed and verified using voltage higher than target/read threshold voltage to achieve uniform threshold voltage characteristic

A program operation and a program verification operation are repeatedly performed. The program verification operation is performed on memory cells including pass cells to obtain a uniform distribution characteristic of a threshold voltage. Furthermore, the program verification operation is performed with a compare voltage being set higher than a target voltage initially so that a threshold voltage of a memory cell is sufficiently higher than the target voltage. The program verification operation is again performed lowering the compare voltage according to the repetition number. Thus, normally programmed cells are prevented from being again excessively programmed.

Method for fabricating capacitor of semiconductor device

The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

Multi-finger type electrostatic discharge protection circuit

A multi-finger type electrostatic discharge protection circuit is disclosed. In an NMOS type ESD protection circuit, a pair of gates are formed in parallel with each other in one of multiple active regions so as to enable all the gate fingers in the active regions to perform npn bipolar operations uniformly. The present invention discharges an ESD pulse effectively by forming one or more additional n+ (or p+) type active regions, which are connected to Vcc (or Vss), between respective active regions.

Reference voltage generating circuit for outputting multi-level reference voltage using fuse trimming

A reference voltage generating circuit includes voltage outputting means for outputting a reference voltage corresponding to a difference between a band gap reference voltage and an input voltage; a first resistor having one end that is coupled to the output of the voltage outputting unit; first variable resistor unit having a plurality of second resistors that are serially coupled between the first resistor and a ground voltage, for providing the input voltage of the voltage outputting unit with a first trimming voltage that is inputted to one end of selected one of the plurality of the second resistors in response to decoded signals for trimming the reference voltage; second variable resistor having a plurality of third resistors coupled serially between the first resistor and the ground voltage, the third resistors having different resistances from the second resistors, for providing the input voltage of the voltage outputting unit with a second trimming voltage that is inputted to one ...

Dynamic semiconductor memory with improved refresh mechanism

Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed.

Vertical floating body cell of a semiconductor device and method for fabricating the same

A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel.

Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh

A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.

Method for manufacturing semiconductor package having improved bump structures

A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

RFID device having nonvolatile ferroelectric memory device

A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

BURIED GATE IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A buried gate in a semiconductor device and a method for fabricating the same are presented. The method includes: forming a gate trench in an active region of a semiconductor substrate; filling the gate trench with a barrier metal film and a metal film; recessing the metal film and the barrier metal film to form buried gate electrodes that partially fill the gate trench; recessing the barrier metal film of the buried gate electrode below the surface of the metal film; and filling an exposed part of the buried gate electrode and the gate trench with a capping film.

Differential amplifier with a feedback unit

A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Semiconductor integrated circuit for generating clock signals

A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

Semiconductor package

A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate.

Method for forming isolation layer of semiconductor device

A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench having a second size, which is larger than the first size of the first trench, in the peripheral circuit region; forming a sidewall oxide layer on surfaces of the first trench and the second trench; sequentially depositing a liner nitride layer and a liner oxide layer on a resultant substrate inclusive of the sidewall oxide layer; performing a plasma pre-heating process using O₂+He with respect to the resultant substrate in an HDP CVD process chamber and selectively oxidizing a portion of the liner nitride layer remaining on a bottom of the second trench in the peripheral circuit region; continuously depositing an HDP oxide layer on the resultant substrate having been subjected to the plasma pre-heating ...

Method of forming a contact hole for a semiconductor device

Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable of being chemically bonded to the reaction pattern. A coating layer is then formed on substantially all of the structure that includes the self-assembled monolayer. Afterwards, the contact holes are formed on the semiconductor substrate by performing an etching process.

Mask layout and method for forming vertical channel transistor in semiconductor device using the same

A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

Cleaning solution for removing photoresist

Cleaning solutions for removing photoresist resins and a method of forming patterns using the same are disclosed. The cleaning solution includes water (H2O) as main component, one or more surfactants as additive selected from the group consisting of polyoxyalkylene compounds, a salt of alcohol amine of Formula 1 and hydrocarbon compounds having carboxylic acid (-COOH) group, a salt of alcohol amine of Formula 1 and hydrocarbon compounds having sulfonic acid (-SO3H) group, polyethylene glycol compounds, compounds of Formula 3, compounds having a molecular weight ranging from 1000 to 10000 including repeating unit of Formula 4, polyether denatured silicon compounds and alcohol compounds. wherein R1, R2, R3, R4, R5, A, l and n are defined in the specification.

Method of controlling operation of flash memory device

According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to check an operating characteristic of the reference block, a threshold voltage level of the programmed memory cell is read. Parameters for performing an operation of the flash memory device are determined based on the operating characteristic of the reference block. The parameters are stored in the reference block.

Self refresh operation of semiconductor memory device

A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Semiconductor memory device and method for driving the same

The present invention intends to provide a semiconductor memory device including a delay locked loop (DLL) circuit capable of generating a duty-corrected delay locked clock. A semiconductor memory device includes: a DLL circuit for generating a delay locked clock through a delay locked operation; and a duty-correction circuit for correcting a duty ratio of the delay locked clock by using the delay locked clock and a divided clock generated by dividing the delay locked clock by an even value.

Apparatus for dividing bank in flash memory

The present invention relates to an apparatus for dividing a bank in a flash memory. A block of the flash memory is divided into two banks and each page buffer is located between the two banks to share an input/output line. Therefore, it is possible to shorten the length of a bit line, improve a data sensing rate, and allow one bank to perform one operation while the other bank performs a read, write or erase operation.

Method of programming nonvolatile memory device

A method of programming a nonvolatile memory device includes sequentially programming first to (n1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.

SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT AND OUTPUT METHOD THEREOF

A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data.

Structure and method for transferring column address

The present invention relates to a structure and method for transferring a column address. In transferring an external column address to the inside of a memory cell, a latch control unit controls the operation of a latch unit for latching the external column address signal. It is thus possible to prohibit consumption of current by controlling the operation of the latch unit when a read or write command signal is inputted.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Semiconductor device having a fin transistor and method for fabricating the same

A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

Electronic system modules and method of fabrication

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are ...

Internal Voltage Generation Circuit

An internal voltage generation circuit includes a driving control signal generation unit configured to receive a temperature signal enabled when the internal temperature is below a preset temperature and generate first and second driving control signals, and an internal voltage generation unit configured to receive the first and second driving control signals and generate an internal voltage.

Semiconductor device with SEG film active region

A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.

Square pillar-shaped switching element for memory device and method of manufacturing the same

A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions.

Flexible semiconductor package and method for fabricating the same

A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Phase change memory apparatus and test circuit therefor

A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.

Address synchronous circuit capable of reducing current consumption in DRAM

An address synchronous circuit includes an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of an address which is buffered in accordance with a clock enable signal, in response to the control signal.

Circuit for controlling pulse width

Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Method for fabricating DRAM cell transistor having trench isolation structure

The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film. Thus, a back bias is applied to the well region, and at the same time, also applied to the electrode formed within the field oxide film, so that the electric potential at the edge portion of the field oxide film is ...

Signal delay control circuit in a semiconductor memory device

A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.

Three dimensional pipe gate nonvolatile memory device

A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.

Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same

An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an output control unit that outputs the first column selecting signal or the second column selecting signal in response to the input of a predetermined voltage detecting signal.

Method for fabricating semiconductor device

The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.

Method of programming non-volatile memory device

A method of programming a non-volatile memory device includes, a bit line, to which a program-inhibited cell is connected, being precharged. After precharging the bit line, a program voltage is applied to a first word line selected for program. When a memory cell connected to a second word line, which is adjacent to the first word line in a direction of a drain select line, is a cell to be programmed, a first pass voltage is applied to the second word line and a second pass voltage is applied to the remaining word lines other than the first and second word lines.

TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME

A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with SiH and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.

Method for reading flash memory cell, NAND-type flash memory apparatus, and NOR-type flash memory apparatus

A method of reading a flash memory cell, a NAND-type flash memory apparatus, and/or a NOR-type flash memory apparatus improves the resolution capability and reduces the determination time by using different voltages applied at the read operation of the flash device. As a result, it is possible to reduce sizes of circuits such as a page buffer as well as the memory cell of the flash device.

MEMORY SYSTEM

A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure.

METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME

A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W-N-B ternary layer, and a Ti-N-B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.

SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME

A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other.

Method for Fabricating a Semiconductor Device

An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the first line width. In the second portion, elements of the recess gate pattern are separated.

Semiconductor Device and Method for Fabricating the Same

A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.

On-DRAM termination resistance control circuit and method thereof

An on-DRAM termination resistance control circuit is capable of controlling resistance of an IC termination and minimizing area for the resistance control circuit by using a simplified circuit scheme. The on-DRAM termination resistance control circuit includes a push-up resistance adjusting unit, a pull-down resistance adjusting unit and resistance adjustment control unit. The push-up resistance adjusting unit adjusts resistances of a first and a second inner resistors based on an external reference resistor. The pull-down resistance adjusting unit adjusts a resistance of a third resistor based on the second inner resistor that is adjusted by adjustment of the push-up resistance control unit. The resistance adjustment control unit controls to alternatively repeat the operation of the push-up resistance adjusting unit and the pull-down resistance adjusting unit for a predetermined number of adjustment times.

Manufacturing method of transistor structure having a recessed channel

A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Capacitor with oxidation barrier layer and method for manufacturing the same

This invention provides a capacitor and a method for manufacturing of the same, which are adaptable to preventing a lower electrode from being oxidized at a following thermal process. The capacitor includes: a lower electrode; an oxidation barrier layer formed on the lower electrode, wherein the oxidation barrier layer is formed of at least double nitridation layers; a dielectric layer formed on the oxidation barrier layer; and an upper electrode formed on the dielectric layer.

RAMP SIGNAL GENERATOR AND IMAGE SENSOR

Disclosed are a ramp signal generator and an image sensor. The ramp signal generator includes: a comparator comparing a first bias voltage input to a first input terminal and a second bias voltage input to a second input terminal and outputting a ramp signal from an output terminal; a ramp signal adjustment unit including a plurality of switched capacitors made up of switches and capacitors connected in series, and connected in parallel between a first input terminal of the comparator and an output terminal of the comparator; and a controller switching the switches of the plurality of switched capacitors to adjust the ramp signal output from the comparator such that the ramp signal becomes nonlinear over time. 1. A ramp signal generator comprising:a comparator operative to output a ramp signal;a ramp signal adjustment unit connected in parallel between a first input terminal of the comparator and an output terminal of the comparator; anda controller operatively coupled to the ramp signal adjustment unit, operative to adjust the comparator ramp signal output such that the ramp signal includes a nonlinear interval.2. The ramp signal generator of claim 1 , wherein the controller is operative to adjust the ramp signal to include a gentle slope interval and a steep slope interval.3. The ramp signal generator of claim 1 , further comprising a buffer connected to the output terminal of the comparator claim 1 , operative to buffer the ramp signal.4. The ramp signal generator of claim 1 , wherein the ramp signal adjustment unit comprises a plurality of switched capacitors connected in parallel; andwherein the controller is further operative to sequentially switch the plurality of switched capacitors.5. The ramp signal generator of claim 4 , wherein the ramp signal adjustment unit comprises:a reset switch connected in parallel to the plurality of switched capacitors, operative to reset the ramp signal adjustment unit in response to a control signal from the controller; anda ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to a semiconductor device including a vertical type gate and a method of forming the same. According to the present invention, a semiconductor device includes a vertical pillar which is protruded from a semiconductor substrate, has a vertical channel, and has a first width; an insulating layer which has a second width smaller than the first width, provided in both sides of the vertical pillar which is adjacent in a first direction; and a nitride film provided in a side wall of the insulating layer. 1. A semiconductor device , comprising:a vertical pillar protruded from a semiconductor substrate, the vertical pillar having a first width and defining a vertical channel;an insulating layer having a second width smaller than the first width, the insulating layer provided at first and second sidewalls of the vertical pillar, the first and second sidewalls arranged along a first direction and facing each other; anda nitride film provided over the insulating layer.2. The semiconductor device of claim 1 , wherein the insulating layer includes an oxide film.3. The semiconductor device of claim 1 , wherein the nitride film has a width that is substantially the same as the first width.4. The semiconductor device of claim 1 , wherein the nitride film has an etch selectivity different from that of the insulating layer.5. The semiconductor device of claim 1 , further comprising a bit line formed between the vertical pillars and extending along a second direction orthogonal to the first direction.6. The semiconductor device of claim 1 , further comprising an interlayer insulating film filling in a space between neighboring vertical pillars arranged along the first direction.7. The semiconductor device of claim 6 , wherein the interlayer insulating film includes an oxide film.8. The semiconductor device of claim 6 , wherein the interlayer insulating film has substantially the ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film. 1. A semiconductor device , comprising:a first metal wiring provided over a substrate;a plurality of first contact plugs coupled to the first metal wiring and passing through a first interlayer insulating film provided over the substrate;a second metal wiring provided over the first interlayer insulating film and coupled to the plurality of first contact plugs;a plurality of second contact plugs coupled to the second metal wiring and passing through a second interlayer insulating film provided over the first interlayer insulating film;a fuse pattern coupled to a first one of the second contact plugs and provided over the second interlayer insulating film; anda data read fuse pattern coupled a second one of the second contact plugs and provided over the second interlayer insulating film.2. The semiconductor device of claim 1 , wherein a signal of the fuse pattern is sensed by the data read fuse pattern through the first contact plug and the first metal wiring.3. The semiconductor device of claim 1 , wherein the first metal wiring includes a gate.4. The semiconductor device of claim 1 , wherein the second metal wiring includes a bit line.5. The semiconductor device of claim 1 , wherein the first metal wiring is a line type.6. The semiconductor device of claim 5 , wherein the plurality of ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. 1. A semiconductor device comprising:a substrate having a junction region;a conductive pattern formed over the substrate;a nitride pattern formed over the substrate, the nitride pattern intersecting the word line to define a region; anda contact plug provided within in the region by the conductive pattern and the nitride pattern, the contact plug coupled to the junction region.2. The semiconductor device of claim 1 , further comprisingan oxide pattern formed over the substrate except the areas where the conductive pattern and the nitride pattern are formed.3. The semiconductor device of claim 2 , wherein the conductive pattern claim 2 , the nitride pattern claim 2 , and the oxide pattern have substantially the same height.4. The semiconductor device of claim 1 , wherein the nitride pattern is a low pressure (LP) nitride.5. The semiconductor device of claim 1 , further comprising:a first spacer that is formed on sidewalls of the conductive pattern and sidewalls of the nitride pattern.6. The semiconductor device of claim 1 , wherein the conductive pattern comprises:a polysilicon layer;a barrier metal layer formed over the polysilicon layer;a tungsten layer formed over the barrier metal layer; anda gate hard disk mask layer formed over the tungsten layer.7. The semiconductor device of claim 5 , further comprising:a second spacer formed over the sidewalls and top of the word line.8. The semiconductor device of claim 1 , wherein the ...

VOLTAGE REGULATION CIRCUIT

A voltage regulation circuit includes: a first voltage divider that divides a regulation voltage with a predetermined division ratio to generate a division voltage; a first current driving force control unit configured to compare a reference voltage with the division voltage and generate a first control signal; a current driving unit configured to generate a driving current with a variable driving force based on the first control signal and a second control signal, and generate the regulation voltage; and a second current driving force control unit configured to generate the second control signal in accordance with a level variation of the regulation voltage. 1. A voltage regulation circuit comprising:a first voltage divider that divides a regulation voltage with a predetermined division ratio to generate a division voltage;a first current driving force control unit configured to compare a reference voltage with the division voltage and generate a first control signal;a current driving unit configured to generate a driving current with a variable driving force based on the first control signal and a second control signal, and generate the regulation voltage; anda second current driving force control unit configured to generate the second control signal in accordance with a level variation of the regulation voltage.2. The voltage regulation circuit according to claim 1 , wherein the second current driving force control unit is configured to divide a voltage level between a power supply voltage and the regulation voltage with a preset division ratio and generate the second control signal.3. The voltage regulation circuit according to claim 1 , wherein the second current driving force control unit comprises a second voltage divider which is coupled between a terminal of the power supply voltage and a ground terminal claim 1 , and the second voltage divider comprises a plurality of diode-connected transistors.4. The voltage regulation circuit according to claim 1 , ...

Nonvolatile memory apparatus

A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE

A method of programming a non-volatile memory device includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a program operation, wherein the word lines do not include a second word line adjacent to the first word line in a direction of the source select line; and applying a first voltage, a program voltage and a second pass voltage when the first pass voltage reaches a given level. The first voltage is applied to the second word line, the program voltage is provided to the first word line, and the second pass voltage is applied to word lines in a direction of a drain select line on the basis of the first word line. 1. A method of programming a non-volatile memory device , the method comprising:applying a program voltage to a first word line selected for a program operation;applying a first voltage to a second word line adjacent to the first word line in a direction of a source select line;applying a first pass voltage to a third set of word lines in a direction of the source select line relative to the first word line;applying a second pass voltage to a fourth set of word lines in a direction of a drain select line relative to the first word line; andapplying a voltage to a bit line in accordance with data to be programmed in a memory cell, and performing the program operation.2. The method of claim 1 ,wherein the first voltage is applied so that a memory cell coupled to the second word line is turned off by a channel voltage boosted by the first pass voltage; andwherein programming of the memory cell coupled to the second word line is inhibited.3. The method of claim 1 , further comprising:applying a voltage of about 0V to a bit line coupled to a memory cell to be programmed; andapplying a power supply voltage to a bit line coupled to a memory cell inhibited from being programmed.4. The method of claim 1 , wherein a voltage of about 0V is applied to the source select line.5. The method of ...

NONVOLATILE MEMORY APPARATUS AND METHOD FOR PROCESSING CONFIGURATION INFORMATION THEREOF

A nonvolatile memory apparatus includes a memory device including a configuration information storage block for storing configuration data groups. A configuration information processing circuit is configured to determine majorities of configuration data groups, which are outputted from the memory device during a first period as an initial stage of a power-up operation, under the control of a first control clock signal. The configuration information processing circuit is also configured to determine majorities of configuration data groups, which are outputted from the memory device during a second period after the first period, under the control of a second control clock signal having a cycle shorter than the first control clock signal. 1. A nonvolatile memory apparatus comprising:a memory device including a configuration information storage block for storing a plurality of configuration data groups; anda configuration information processing circuit configured to determine majorities of configuration data groups received from the memory device during a first period of a power-up operation, under the control of a first control clock signal, and determine majorities of configuration data groups received from the memory device during a second period after the first period, under the control of a second control clock signal having a cycle shorter than the first control clock signal.2. The nonvolatile memory apparatus according to claim 1 , wherein the configuration information storage block is divided into a plurality of pages claim 1 , and each page includes a plurality of nonvolatile memory cells.3. The nonvolatile memory apparatus according to claim 1 , wherein each of the plurality of configuration data groups includes any one of internal bias information claim 1 , internal logic configuration information claim 1 , failed address information claim 1 , and redundancy information.4. The nonvolatile memory apparatus according to claim 1 , wherein the memory device ...

NONVOLATILE MEMORY APPARATUS AND METHOD FOR PROCESSING CONFIGURATION INFORMATION THEREOF

A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period. 1. A nonvolatile memory apparatus comprising:a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group; anda configuration information processing circuit configured to determine a majority of the first configuration data group received from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group received from the memory device, during a second period after the first period.2. The nonvolatile memory apparatus according to claim 1 , wherein the configuration information storage block is divided into a plurality of pages claim 1 , and each page comprises a plurality of nonvolatile memory cells.3. The nonvolatile memory apparatus according to claim 1 , wherein the first configuration data group includes internal bias information and internal logic configuration information claim 1 , and the second configuration data group includes failed address information and redundancy information.4. The nonvolatile memory apparatus according to claim 1 , wherein the memory device comprises:main storage blocks; anda page buffer configured to detect and output data stored in the configuration information storage block and the main storage blocks.5. The nonvolatile memory apparatus ...

TEST SIGNAL GENERATING DEVICE, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND MULTI-BIT TEST METHOD THEREOF

A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed. 1. A semiconductor memory apparatus , comprising:a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed.2. The semiconductor memory apparatus according to claim 1 , wherein the multi-bit test signal generating device includes:an address driving unit configured to drive the address signal in response to a write signal;an address latch unit configured to latch an output of the address driving unit; andan output unit configured to generate the multi-bit test signal in response to a test mode signal and an output of the address latch unit.3. The semiconductor memory apparatus according to claim 2 , wherein the write signal is configured to be enabled in the write operation.4. The semiconductor memory apparatus according to claim 2 , wherein the test mode signal informs the semiconductor memory apparatus to perform the multi-bit test operation.5. A semiconductor memory apparatus comprising:a multi-bit test signal generating unit configured to receive an address signal to generate a multi-bit test signal; anda write driver unit configured to receive a first data signal, a second data signal and the multi-bit test signal to generate a first input data signal and a second input data signal.6. The semiconductor memory apparatus according to claim 5 , wherein the multi-bit test signal generating unit is configured to generate the multi-bit test signal based on the address signal in a multi-bit test write operation.7. The semiconductor memory apparatus according to claim 6 , wherein the address signal is configured to be used in an active operation of the semiconductor memory apparatus but not used ...

DATA TRANSFER CIRCUIT OF SEMICONDUCTOR APPARATUS

Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal. 1. A semiconductor apparatus including a data transfer unit , the data transfer unit comprising:a first data line;a second data line;a first transfer unit configured to amplify data on the first data line in response to a first control signal, and transfer amplified data to the second data line; anda second transfer unit configured to connect the first data line to the second data line in response to a second control signal.2. The semiconductor apparatus according to claim 1 , the data transfer unit further comprises a control unit configured to generate the first control signal and the second control signal according to a result obtained by determining an operation speed of the semiconductor apparatus.3. The semiconductor apparatus according to claim 2 , wherein the control unit is configured to determine the operation speed of the semiconductor apparatus based on CAS latency signals.4. The semiconductor apparatus according to claim 2 , wherein the control unit is configured to determine that the semiconductor apparatus operates at two speeds based on CAS latency signals claim 2 , and selectively activate the first control signal and the second control signal according to a determination result.5. The semiconductor apparatus according to claim 2 , wherein the control unit is configured to determine that the semiconductor apparatus operates at a high speed and a low speed based on CAS latency signals claim 2 , and activate the first control signal when it is determined ...

Output enable signal generation circuit of semiconductor memory

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

IMPEDANCE CALIBRATION CIRCUIT

Various embodiments of an impedance calibration circuit are disclosed. In one exemplary embodiment, the impedance calibration circuit may include a control unit configured to generate a plurality of first internal commands for defining an impedance calibration operation in response to an external signal, a temperature-adaptive control unit configured to generate a second internal command for defining an impedance calibration operation by detecting a temperature change, a timer counter configured to generate an operation control signal that prescribes a duration of time for an impedance calibration operation in response to the plurality of first internal commands and the second internal command, and an impedance calibration signal generation unit configured to operate for a predetermined time defined by the operation control signal and generate impedance calibration signals. 1. An impedance calibration circuit comprising:a control unit configured to generate a plurality of first internal commands for defining an impedance calibration operation in response to an external signal;a temperature-adaptive control unit configured to generate a second internal command for defining an impedance calibration operation by detecting a temperature change;a timer counter configured to generate an operation control signal that prescribes a duration of time for an impedance calibration operation in response to the plurality of first internal commands and the second internal command; andan impedance calibration signal generation unit configured to operate for a predetermined time defined by the operation control signal and generate impedance calibration signals.2. The impedance calibration circuit according to claim 1 , wherein the external signal is an impedance calibration command inputted from an outside signal and an address signal.3. The impedance calibration circuit according to claim 1 , wherein the plurality of first internal commands include a command for defining a short ...

ISOLATION METHOD IN SEMICONDUCTOR DEVICE

The present invention discloses an isolation process in a semiconductor device. In the present invention, when a SPT process is used for isolation, ISO cut patterns for cutting spacers for SPT in the unit of a specific length are first formed, and ISO partition patterns defining partition regions for forming the spacers are then formed over the ISO cut patterns. Accordingly, there are advantages in that the SPT process can be simplified and costs can be reduced according to the simplified process because the isolation process is simplified. 1. An isolation method in a semiconductor device , the method comprising:forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a peripheral region;forming a first hard mask layer, a second hard mask layer, and a third hard mask layer over the pad nitride layer;etching the third hard mask layer to form isolation (ISO) cut patterns defining a length of active regions in the cell region;forming ISO partition patterns over the ISO cut patterns;forming first and second spacers using Spacer Pattern Technology (SPT) at first and second longitudinal sidewalls of the ISO partition patterns respectively, wherein the first spacer is formed over the second hard mask layer with interposing the ISO cut patterns and the second spacer is formed over the second hard mask layer without interposing the ISO cut pattern;forming ISO peripheral patterns over the third hard mask layer of the peripheral region, the ISO peripheral patterns defining isolation regions in the peripheral region;etching the third hard mask layer using the first and the second spacers and the ISO peripheral patterns as an etch barrier;removing the first and the second spacers to form ISO patterns formed of the third hard mask layer; andetching the second hard mask layer, the first hard mask layer, the pad nitride layer, the pad oxide layer, and the semiconductor substrate using the ISO patterns to form trenches for ...

SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation. 1. A sense amplifier configured to transfer data on first data I/O lines to second data I/O lines or to transfer data on the second data I/O lines to the first data I/O lines , wherein the first data I/O line is coupled to the second data I/O line continuously during an active operation.2. The sense amplifier of claim 1 , wherein the sense amplifier is configured to couple the first and second data I/O lines in response to an I/O switch signal enabled to select the second data I/O line.3. The sense amplifier of claim 2 , wherein the I/O switch signal is generated from an active signal or a row selection signal.4. A sense amplifier comprising:a data line connecting unit configured to couple first data I/O lines to second data I/O lines in response to an I/O switch signal; anda hybrid data transfer unit configured to amplify the first data I/O line in response to a sense amplifier enable signal.5. The sense amplifier of claim 4 , wherein the I/O switch signal is generated from an active signal or a row selection signal.6. The sense amplifier of claim 4 , wherein the sense amplifier enable signal is generated from a read or write command.7. The sense amplifier of claim 6 , wherein the sense amplifier enable signal is generated from a column decoder block.8. The sense amplifier of claim 4 , wherein the hybrid data transfer unit is configured to differentially amplify data on the first data I/O lines to transfer the data to the second data I/O lines or differentially amplify the first data I/O lines based on data transferred from the second data I/O lines claim 4 , when the sense amplifier enable signal is enabled.9. A semiconductor apparatus comprising:a sense amplifier configured ...

SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a data selection unit, a first data processing unit, and a second data processing unit. The data selection unit is configured to select one of the first and second transfer lines to be coupled to a data pad in response to address signals. The first data processing unit is connected to the first transfer line and a first memory bank of a plurality of memory banks, and performs a data input/output (I/O) operation between the first transfer line and the first memory bank. The second data processing unit is connected to the second transfer line and a second memory bank of the plurality of memory banks, which is different from the first memory bank, and performs a data input/output (I/O) operation between the second transfer line and the second memory bank. 1. A semiconductor memory apparatus comprising:a data selection unit configured to select one of the first and second transfer lines to be coupled to a data pad in response to address signals;a first data processing unit which is coupled to the first transfer line and a first memory bank of a plurality of memory banks and performs a data input/output (I/O) operation between the first transfer line and the first memory bank; anda second data processing unit which is coupled to the second transfer line and a second memory bank of the plurality of memory banks and performs a data input/output (I/O) operation between the second transfer line and the second memory bank.2. The semiconductor memory apparatus according to claim 1 , wherein the data selection unit includes:a multiplexer unit configured to output data inputted through the data pad to one of the first and second transfer lines in response to the address signals; anda demultiplexer unit configured to output data inputted through one of the first and second transfer lines in response to the address signals to the data pad.3. The semiconductor memory apparatus according to claim 1 , wherein the first data processing unit is ...

PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. 1. A method of fabricating a phase-change memory device , said method comprising:forming a lower electrode comprising a PN diode structure on an active region of a substrate;forming a heating layer on the PN diode structure;forming a phase-change material layer on the heating layer; andforming an upper electrode on the phase-change material layer;wherein a contact area between the phase-change material layer and the heating layer is formed to be smaller than that between the heating layer and the PN diode structure.2. The method of claim 1 , wherein the heating layer is formed to have a cup shape byforming an insulating layer having an open region that exposes the top of the PN diode structure;depositing a conductive layer of a predetermined thickness over the insulating layer including the open region; andremoving the conductive layer outside the open region while leaving the conductive layer of the predetermined thickness in the open region.3. The method of claim 1 , wherein the heating layer is formed on the PN diode structure to have an exposed top surface claim 1 , and the phase-change material layer is formed to be in electrical contact with only a part of the exposed top surface of the heating layer.4. A phase-change memory device claim 1 , comprising:a substrate having thereon an active region;a lower electrode comprising a PN diode structure on the active region of the substrate;a heating layer on the PN diode structure;a phase-change material layer on the heating layer; andan upper electrode on the phase-change material layer;wherein a contact area between the phase-change material layer and the heating layer is smaller than that between the heating ...

METHOD OF FORMING SEMICONDUCTOR DEVICES

A semiconductor device includes an insulating layer and an undoped polysilicon layer that are stacked over a semiconductor substrate. The semiconductor substrate is exposed by removing the portions of the undoped polysilicon layer and the insulating layer. The trenches are formed by etching the exposed semiconductor substrate. Isolation layers are formed in the trenches, and a doped polysilicon layer is formed by implanting impurities into the undoped polysilicon layer. 1. A method of forming semiconductor devices , comprising:forming an insulating layer over a semiconductor substrate;forming an undoped polysilicon layer over the insulating layer;removing a portion from each of the undoped polysilicon layer, the insulating layer, and the semiconductor substrate so as to form a trench;forming an isolation layer in the trench; andimplanting impurities into the undoped polysilicon layer so as to convert a portion of the undoped polysilicon layer into a doped polysilicon layer.2. The method of claim 1 , wherein forming the isolation layer in the trench comprises:filling the trench with an insulating substance; andhardening the insulating substance in an annealing process.3. The method of claim 2 , wherein the insulating substance comprises polysilazane (PSZ).4. The method of claim 2 , wherein temperature applied to the semiconductor substrate after the annealing process is lower than temperature applied in the annealing process.5. The method of claim 1 , wherein forming undoped polysilicon layer comprises:forming a first undoped polysilicon layer having a first grain on the insulating layer; andforming a second undoped polysilicon layer having a second grain greater in size than the first grain on the first undoped polysilicon layer.6. The method of claim 5 , wherein the impurities are implanted into the second undoped polysilicon layer so as to convert the second undoped polysilicon layer into the doped polysilicon layer.7. The method of claim 1 , wherein the ...

SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME

A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region. 1. A semiconductor memory device comprising:an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate;a first impurity region formed at an upper portion of the active region;a second impurity region formed at a lower portion of the active region;a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region;a gate electrode layer formed on the gate dielectric layer;a buried bit line formed at a lower portion of the trench; anda polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.2. The semiconductor memory device of claim 1 , wherein the liner layer includes an oxide layer.3. The semiconductor memory device of claim 2 , wherein the oxide layer has a thickness of approximately 10 Å to approximately 200 Å.4. The semiconductor memory device of claim 1 , wherein the buried bit line includes a titanium nitride (TiN) layer claim 1 , a tungsten nitride (WN) layer claim 1 , a tantalum (Ta) layer claim 1 , a tantalum nitride (TaN) layer claim 1 , a tungsten silicide (WSi2) layer claim 1 , a tungsten (W) layer or a combination thereof ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by α° (where 0°<α°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased. 1. A semiconductor device comprising:an active region formed sloped by α° (where 0°<α°<90°) with respect to the bottom of a semiconductor substrate;a gate formed in the sloped active region and having a surface parallel to the bottom of the semiconductor substrate; anda landing plug coupled to the active region at a side of the gate.2. The semiconductor device according to claim 1 , wherein the gate includes a recess gate.3. The semiconductor device according to claim 1 , the device further comprising:a junction region formed in the active region at a side of the gate, and coupled to the landing plug.4. The semiconductor device according to claim 1 , wherein the active region includes:a first end; anda second end formed at a higher level than that of the first end.5. The semiconductor device according to claim 4 , wherein the gate is formed to a greater depth at the first end than at the second end.6. The semiconductor device according to claim 1 , wherein the gate includes:a gate polysilicon;a gate electrode formed over the gate polysilicon; anda hard mask formed over the gate electrode.7. The semiconductor device according to claim 6 , wherein the gate polysilicon is formed in the sloped active region in such a manner that the surface of the gate polysilicon is arranged parallel to the bottom of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate including a cell area and a peripheral circuit area, a first trench for device isolation formed in the cell area of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit area to be deeper than the first trench, a device isolation layer buried within the first and second trenches for device isolation and having the same surface level as the semiconductor substrate in the cell area, a buried gate buried in the semiconductor substrate of the cell area, and a peripheral circuit gate which is in contact with the semiconductor substrate of the peripheral circuit area, is buried within the device isolation layer of the peripheral circuit area, and has the same surface level as the buried gate. It can prevent the same effect from affecting the cell area and the peripheral circuit area so that the number of masks is reduced and the process is simplified so that cost can be reduced and characteristics of the semiconductor device can be improved. 1. A semiconductor device , comprising:a semiconductor substrate including a cell region and a peripheral circuit region;a first trench for device isolation formed in the cell region of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit region, the second trench being deeper than the first trench;a device isolation layer filling the first and second trenches and being substantially flushed to an upper surface of the semiconductor substrate in the cell region;a buried gate buried in the semiconductor substrate of the cell region; anda peripheral circuit gate provided in the peripheral circuit region and being in contact with the semiconductor substrate, the peripheral circuit gate being formed within the device isolation layer and having an upper surface that is at substantially the same surface level as that of ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased. 1. A semiconductor device , comprising:a gate electrode disposed over a substrate;a plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope;a capping layer disposed between the gate electrode and the plug; anda gate hard mask layer whose sidewall disposed over the gate electrode extending to a top surface of the capping layer.2. The semiconductor device of claim 1 , further comprising a recess pattern formed in the substrate under the gate electrode.3. The semiconductor device of claim 2 , wherein the recess pattern has one shape selected from the group consisting of rectangle claim 2 , polygon claim 2 , a bulb type claim 2 , a fin type and a saddle-fin type.4. The semiconductor device of claim 1 , wherein a sidewall of the gate electrode has a vertical profile or a positive slope.5. The semiconductor device of claim 1 , wherein a sidewall of the capping layer has a negative slope.6. The semiconductor device of claim 1 , wherein the capping layer includes one of an oxide layer claim 1 , a nitride layer claim 1 , an oxynitride layer claim 1 , and a stack structure thereof.7. The semiconductor device of claim 1 , wherein the plug is formed of the same material as that of the gate electrode.8 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a first gate electrode buried within a semiconductor substrate, a second gate electrode buried within a silicon growth layer disposed on the semiconductor substrate, and a bit line disposed on an interlayer insulating layer disposed on the semiconductor substrate between the first gate electrode and a second gate electrode. Therefore, the number of gates disposed in an active region is increased so that a total memory capacity of the semiconductor device, thereby reducing fabrication cost and improving productivity. 1. A semiconductor device , comprising:a first gate electrode formed in a semiconductor substrate;a second gate electrode formed in a silicon growth layer provided over the semiconductor substrate;a bit line disposed between the semiconductor substrate and the silicon growth layer; anda first insulating layer formed over the first gate electrode and a second insulating layer formed over the second electrode.2. The semiconductor device of claim 1 , wherein the first gate electrode and second gate electrode extend perpendicular to the bit line.3. The semiconductor device of claim 2 , the device further comprising a storage node contact plug diagonally disposed while being spaced apart from the second gate electrode and the bit line.4. The semiconductor device of claim 3 , the device further comprising a metal contact plug coupled to a bottom of the storage node contact plug and formed in the silicon growth layer and the semiconductor substrate.5. The semiconductor device of claim 4 , the device further comprising a polysilicon layer coupled to a bottom of the metal contact plug.6. The semiconductor device of claim 5 , wherein the polysilicon layer is coupled to the semiconductor substrate.7. The semiconductor device of claim 5 , wherein a bottom of the polysilicon layer is formed at substantially the same level as a bottom of the first gate electrode.8. The semiconductor device of claim 5 , the device further comprising an ...

Semiconductor chip and method for fabricating the same

A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug. 1. A semiconductor device , comprising:a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer;a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer;a storage node contacting a top surface of the second storage node contact plug; anda second interlayer insulation layer formed over the first interlayer insulation layer, the second interlayer insulation layer surrounding an outer sidewall at a bottom region of the storage node, the second storage node contact plug, and the first storage node contact plug protruding above the first interlayer insulation layer.2. The semiconductor device of claim 1 , wherein the first interlayer insulation layer comprises an oxide layer.3. The semiconductor device of claim 1 , wherein the second interlayer insulation layer comprises a nitride layer.4. The semiconductor device of claim 1 , wherein the first interlayer insulation layer comprises an oxide layer and the second interlayer insulation layer comprises a nitride layer.5. The semiconductor device of claim 1 ...

Semiconductor device and package

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a substrate, a pattern including a conductive layer and a hard mask layer stacked over the substrate, a capping layer surrounding sidewalls of the pattern, and a stress buffer layer disposed between the hard mask layer and the capping layer. The stress buffer layer is configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer. 119-. (canceled)20. A semiconductor device , comprising:a substrate;a pattern including a conductive layer and a hard mask layer stacked over the substrate;a capping layer surrounding sidewalls of the pattern; anda stress buffer layer disposed between the hard mask layer and the capping layer, the stress buffer layer being configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer.21. The semiconductor device of claim 20 , wherein the capping layer and the hard mask layer comprise a nitride layer and the stress buffer layer comprises an oxide layer.22. The semiconductor device of claim 20 , wherein the capping layer and the hard mask layer comprise a nitride layer and the stress buffer layer comprises an oxide layer formed by oxidizing the hard mask layer.23. The semiconductor device of claim 20 , wherein the conductive layer comprises a tungsten layer.24. The semiconductor device of claim 20 , wherein the pattern is used as a gate line claim 20 , a bit line claim 20 , or a metal line. The present invention claims priority of Korean patent application number 10-2007-0111182, filed on Nov. 1, 2007, which is incorporated by reference in its entirety.The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device capable of preventing a leaning effect and a method for fabricating the same.In the case of a dynamic random access memory (DRAM) device ...

SEMICONDUCTOR CHIP AND STACK PACKAGE HAVING THE SAME

A semiconductor chip includes a semiconductor substrate with a top surface and a bottom surface. An active layer may be formed on the top surface of the semiconductor substrate and may comprise one or more signal pads and one or more chip selection pads on an upper surface of the active layer. First and second through electrodes may be formed to pass through the semiconductor substrate and the active layer, with the first through electrodes being electrically connected with the signal pads and the second through electrodes being electrically connected with the chip selection pads. A side electrode may be formed on a side surface of the semiconductor chip in such a way as to be connected with a second through electrode. 1. A semiconductor chip comprising:an active layer formed on a top surface of a semiconductor substrate, the active layer comprising one or more signal pads and one or more chip selection pads disposed on an upper surface of the active layer;first and second through electrodes formed to pass through the semiconductor substrate and the active layer; anda side electrode formed on a side surface of the semiconductor chip.2. The semiconductor chip according to claim 1 , wherein the first through electrodes are electrically connected with the signal pads and the second through electrodes are electrically connected with the chip selection pads3. The semiconductor chip according to claim 2 , wherein the side electrode is connected with one of the second through electrodes.4. The semiconductor chip according to claim 1 , wherein the side electrode is formed in the semiconductor substrate.5. The semiconductor chip according to claim 4 , wherein the side electrode is at a depth of substantially 10 μm to substantially 25 μm when measured from the top surface of the semiconductor substrate.6. The semiconductor chip according to claim 1 , wherein the side electrode is formed in the active layer.7. The semiconductor chip according to claim 1 , wherein the side ...

Semiconductor device with side-junction and method for fabricating the same

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

CALIBRATING RESISTANCE FOR INTEGRATED CIRCUIT

An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code. 1. An integrated circuit comprising:a first on-die termination (ODT) configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value; andan input buffer configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.2. The integrated circuit of claim 1 , wherein the first on-die termination (ODT) unit comprising:a pull-up driving section configured to pull-up drive a first line according to a resistance value which is set depending on the pull-up code; anda pull-down driving section configured to pull-down drive the first line according to a resistance value which is set depending on the pull-down code.3. The integrated circuit of claim 1 , wherein the input buffer comprises:a voltage supply unit configured to supply a power supply voltage through a plurality of switches which are selectively turned on in response to the pull-up code;a current mirror unit configured to be supplied with the power supply voltage from the voltage supply unit and operate as a constant current source;a signal input unit coupled to the constant current source and configured to receive the reference voltage and the data and determine a level of the input data; anda discharge unit configured to determine an amount of charge discharged from ...

DLL CIRCUIT HAVING ACTIVATION POINTS

A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal. 1. A delay locked loop (DLL) circuit , comprising:a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal;a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time;a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; anda delay control unit configured to generate the delay control signal in response to the phase detection signal such that the delay control signal sets a delay value of the delay line to any one of a minimum value and an intermediate value, wherein the delay value is set according to an initial value of the phase detection signal.2. The DLL circuit of claim 1 , wherein the delay line comprises a plurality of unit delayers that are connected to each other in series claim 1 , and the delay line is configured to have activation points corresponding to the minimum value and the intermediate value of the delay value claim 1 , respectively claim 1 , wherein the activation points are selectively activated according to an initial delay control signal ...

Apparatus and method for determining dynamic voltage scaling mode, and apparatus and method for detecting pumping voltage using the same

A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal.

MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME

A multi-chip package includes a plurality of memory chips for performing a content addressable memory (CAM) read operation in response to a command signal for the CAM read operation and an address signal for selecting the memory chips and a controller for outputting the command signal and the address signal to the memory chips and controlling the sequence of the CAM read operations for the memory chips. 1. A multi-chip package , comprising:a plurality of memory chips configured to perform a code access memory (CAM) read operation in response to a command signal for the CAM read operation and an address signal for selecting the memory chips; anda controller configured to output the command signal and the address signal to the memory chips and controlling a sequence of the CAM read operations for the memory chips.2. The multi-chip package of claim 1 , wherein each of the memory chips comprises:a chip address output unit configured to select a chip address signal for the corresponding memory chip from the address signal and outputting the chip address signal;a chip selection signal generator configured to generate a selection signal, indicating that the corresponding memory chip for which the CAM read operation will be performed has been selected, in response to the chip address signal;a CAM read controller configured to generate a CAM read operation signal, instructing the CAM read operation to be performed in the relevant memory chip, based on the selection signal and the command signal; anda CAM read execution unit configured to perform the CAM read operation in response to the CAM read operation signal.3. The multi-chip package of claim 2 , wherein the chip selection signal generator receives a signal indicative of a sequence of the relevant memory chip within the multi-chip package.4. The multi-chip package of claim 2 , wherein the CAM read controller comprises a logic element configured to generate the CAM read operation signal in response to the selection signal ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines for the memory cells, and metal lines coupled to the select transistors through contacts. 1. A semiconductor memory device , comprising:cell gate lines disposed over a semiconductor substrate a first select gate line disposed over the semiconductor substrate adjacent to an outermost one of the cell gate lines; anda first metal line coupled to the first select gate line through a plurality of contacts.2. The semiconductor memory device of claim 1 , further comprising;a second select gate line disposed over the semiconductor substrate adjacent to another outermost one of the cell gate lines.3. The semiconductor memory device of claim 2 , further comprising;a second metal line coupled to the second select gate line through a plurality of contacts.4. The semiconductor memory device of claim 1 , further comprising;a third metal line coupled to the first metal line through a plurality of upper contacts.5. The semiconductor memory device of claim 3 , further comprising;a fourth metal line coupled to the second metal line through a plurality of upper contacts.6. The semiconductor memory device of claim 2 , wherein the first select gate line is a source select gate line and the second select gate line is a drain select gate line.7. A semiconductor memory device comprising first and second memory blocks sharing a common source line claim 2 , each of the first and the second memory blocks comprising:cell gate lines disposed over a semiconductor substrate; anda source select gate line disposed over the semiconductor substrate adjacent to an outermost one of the cell gate lines;first metal lines, wherein each of the first metal line is coupled to the source select gate line of the first memory block and the second ...

Nonvolatile Memory Device and Method of Operating the Same

A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage. 1. A nonvolatile memory device , comprising:memory cell blocks each configured to include memory cells to be erased by an erase voltage supplied to a word line and a bulk voltage supplied to a bulk;a bias voltage generator configured to generate a first erase voltage having a first pulse width and a first amplitude, in order to perform an erase operation of the memory cells, and a second erase voltage having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed; anda bulk voltage generator configured to generate the bulk voltage.2. The nonvolatile memory device of claim 1 , wherein the bias voltage generator is configured to generate the first erase voltage and the second erase voltage of a level higher than 0 V and to additionally lower the second amplitude of the second erase voltage whenever the additional erase operation is performed.3. The nonvolatile memory device of claim 2 , wherein the bias voltage generator is configured to lower the second amplitude of the second erase voltage by a certain value whenever the additional erase operation is performed.4. The nonvolatile ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A method of operating a semiconductor memory device includes performing an LSB program operation for selected memory cells while raising a program voltage, when the threshold voltages of some of the selected memory cells reach a target level, storing data, corresponding to a relevant program voltage, in a first flag cell, performing the LSB program operation for some of the selected memory cells, having threshold voltages not reached the target level, until the threshold voltages of all the selected memory cells reach the target level, and after the LSB program operation is completed, performing an MSB program operation for the selected memory cells by using a program voltage, set based on the data stored in the first flag cell, as a start program voltage. 1. A method of operating a semiconductor memory device , the method comprising:performing an LSB program operation for selected memory cells while raising a program voltage;storing data, corresponding to a program voltage, in a first flag cell when a threshold voltage of a set number of memory cell among the selected memory cells reach a target level;performing the LSB program operation for some of the selected memory cells, having threshold voltages not reached the target level, until the threshold voltages of all the selected memory cells reach the target level; andperforming an MSB program operation for the selected memory cells by using a program voltage, set based on the data stored in the first flag cell, as a start program voltage after the LSB program operation is completed.2. The method of claim 1 , wherein performing the LSB program operation for the selected memory cells comprises:supplying a program voltage to a word line coupled to the selected memory cells; andperforming the LSB program operation while gradually raising the program voltage until a threshold voltage of any one of the selected memory cells reaches a target level.3. The method of claim 1 , wherein storing the data claim 1 , ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME

A method of programming a semiconductor memory device includes a first program step for performing a program by supplying a first program voltage, having a specific amount, to a selected word line of the semiconductor memory device for a set time and a second program step for performing a program by supplying, to the selected word line, a second program voltage which is a step pulse gradually rising from a start voltage lower than the first program voltage. 1. A method of programming a semiconductor memory device , comprising:a first program step for performing a program by supplying a first program voltage, having a specific amount, to a selected word line of the semiconductor memory device for a set time; anda second program step for performing a program by supplying, to the selected word line, a second program voltage which is a step pulse gradually rising from a start voltage lower than the first program voltage.2. The method of claim 1 , wherein the second program step includes performing the program operation by supplying each of the step pulses and then performing each of program verifications using a program verification voltage.3. The method of claim 1 , wherein a degree that the step pulse of the second program voltage is increased is gradually increased.4. The method of claim 1 , further comprising setting voltage claim 1 , supplied to a specific word line of the semiconductor memory device when programming at least one of memory cells coupled to the specific word line in a test mode claim 1 , as the first program voltage claim 1 , before the first program step is performed.5. The method of claim 3 , wherein setting the first program voltage comprises:supplying a gradually rising step voltage program voltage to a specific word line of the semiconductor memory device; andsetting, as the first program voltage, a step voltage when programming at least one of memory cells coupled to the specific word line.6. The method of claim 1 , wherein each of the step ...

NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING THE SAME

A method of erasing a nonvolatile memory device includes the steps of supplying an erase voltage to the P well of a semiconductor substrate having a memory cell block disposed therein; performing a first erase verification operation for verifying the erase state of memory cells coupled to the even bit lines of the memory cell block; making a determination of success or failure for the first erase verification operation; and if, as a result of the determination for the first erase verification operation, all the memory cells coupled to the even bit lines are determined to be erased, performing a second erase verification operation for verifying the erase state of memory cells coupled to odd bit lines of the memory cell block. 1. A method of erasing a nonvolatile memory device , the method comprising the steps of:supplying an erase voltage to a P well of a semiconductor substrate having a memory cell block disposed therein;performing a first erase verification operation for verifying an erase state of memory cells coupled to even bit lines of the memory cell block;making a determination of success or failure for the first erase verification operation; andif, as a result of the determination for the first erase verification operation, all the memory cells coupled to the even bit lines are determined to be erased, performing a second erase verification operation for verifying an erase state of memory cells coupled to odd bit lines of the memory cell block.2. The method of claim 1 , further comprising the steps of:if, as a result of the determination for the first erase verification operation, one or more of all the memory cells coupled to the even bit lines are determined not to be erased, raising the erase voltage by a step voltage; andperforming the steps from the step of supplying the erase voltage to the P well by using the raised erase voltage.3. The method of claim 1 , further comprising the steps of:if, as a result of the determination for the first erase ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING THE SAME

A method of erasing a semiconductor memory device includes precharging a channel of a selected memory cell of a selected string including memory cells; boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; and erasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell. 1. A method of erasing a semiconductor memory device , comprising:precharging a channel of a selected memory cell of a selected string including memory cells;boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; anderasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell.2. The method of claim 1 , wherein the channel of the selected memory cell is precharged by supplying an erase permission voltage to a selected bit line coupled to the selected string.3. The method of claim 2 , wherein the erase permission voltage is a positive voltage.4. The method of further comprising claim 2 , supplying an erase inhibition voltage to an unselected bit line claim 2 , which is coupled to an unselected string including a plurality of memory cells claim 2 , during supplying the erase permission voltage to the selected bit line.5. The method of claim 4 , wherein the erase permission voltage is higher than the erase inhibition voltage.6. The method of claim 4 , wherein the erase inhibition voltage is a zero voltage.7. The method of claim 1 , wherein the positive voltage is supplied to an unselected word line during supplying the erase voltage to the selected word line.8. The method of claim 1 , wherein the erase voltage comprises a negative voltage.9. A semiconductor memory device claim 1 , comprising:strings, each including memory cells coupled ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation. 1. A semiconductor memory device , comprising:a memory cell array comprising a plurality of cell strings; anda page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines,wherein each of the page buffers comprises a latch unit configured to store data to be programmed into memory cells included in the cell string or store data read from the memory cells, and wherein each of the page buffers is coupled to the pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.2. The semiconductor memory device of claim 1 , wherein the page buffer further comprises:a bit line sense unit configured to couple the bit line and a sense node of the page buffer in response to a bit line sense signal; anda sense node coupling unit configured to couple the sense node to the pad for the test operation according to the data of the latch unit in the test operation.3. The semiconductor memory device of claim 2 , wherein the sense node coupling unit comprises a first switching element configured to couple the sense node to the pad according to the data of the latch unit.4. The semiconductor memory device of claim 3 , wherein the sense node coupling unit further comprises a second switching element coupled between the sense node and the first switching element claim 3 , and wherein the second switching element is configured to couple the sense node ...

Semiconductor memory device

A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines, and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines.

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission circuit for transferring the data of the first sense node to a bit line, a sense circuit for transferring the data of the first sense node to a second sense node, and a discharge circuit for changing a voltage level of the common node based on the data of the second sense node. 1. A nonvolatile memory device , comprising:a plurality of latches for storing data;a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node;a transmission circuit for transferring the data of the common node to a first sense node;a bit line transmission circuit for transferring the data of the first sense node to a bit line;a sense circuit for transferring the data of the first sense node to a second sense node; anda discharge circuit for changing a voltage level of the common node based on the data of the second sense node.2. The nonvolatile memory device of claim 1 , wherein the sense circuit comprises an NMOS transistor for coupling the first sense node and the second sense node in response to a sense signal.3. The nonvolatile memory device of claim 1 , wherein the precharge circuit comprises an NMOS transistor for discharging the second sense node by coupling the second sense node and a terminal of a variable voltage node claim 1 , in response to a precharge signal.4. The nonvolatile memory device of claim 3 , wherein the variable voltage of the variable voltage node is a power supply voltage or a ground voltage.5. The nonvolatile memory device of claim 1 , wherein the discharge circuit comprises an NMOS transistor for discharging the common node based on a voltage level of the second sense node.6. The nonvolatile memory device of claim 1 , wherein ...

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

INTEGRATED CIRCUIT USING METHOD FOR SETTING LEVEL OF REFERENCE VOLTAGE

An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode. 1. An integrated circuit comprising:a reference voltage level setting circuit configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode; anda reference voltage generation circuit configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.2. The integrated circuit of claim 1 , wherein the reference voltage level setting circuit is configured to set the level of the input reference voltage to a middle level between the power supply voltage and a ground voltage.3. The integrated circuit of claim 1 , wherein the reference voltage level setting circuit comprises:a pull-up signal generation unit configured to receive a power-up signal and a self-refresh signal and generate a pull-up signal;a pull-up driving unit configured to pull-up drive a middle node in response to the pull-up signal;a pull-down driving unit configured to pull-down drive the middle node in response to a pull-down signal which is generated by buffering the pull-up signal; anda transfer element configured to transfer a signal of the middle node as the input reference voltage in response to the pull-up signal and the pull-down signal.4. The integrated circuit of claim 1 , wherein the reference voltage generation circuit comprises:an enable ...

Semiconductor memory device

A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME

A semiconductor device according to an aspect of the present disclosure includes a test mode signal generator configured to generate a test mode setup signal, and a controller configured to set a separated test operation in response to the test mode setup signal. 1. A semiconductor device , comprising:a test mode signal generator configured to generate a test mode setup signal; anda controller configured to set a separated test operation in response to the test mode setup signal.2. The semiconductor device of claim 1 , wherein the test mode setup signals comprise a test mode enable signal claim 1 , a test mode disable signal claim 1 , a user test mode signal claim 1 , a test mode restart signal claim 1 , and a pump command signal.3. The semiconductor device of claim 2 , wherein the test mode restart signal is used to switch a user test mode to a test mode.4. The semiconductor device of claim 2 , wherein the pump command signal is supplied at the same time with the user test mode signal claim 2 , and used to keep a power source of a memory cell area turned on when the user test mode is operated.5. The semiconductor device of claim 1 , wherein while the separated test operation is performed claim 1 , a power source of the memory chip keeps turned on.6. A method of testing a semiconductor device claim 1 , comprising:selecting one mode from among a test mode and a user test mode; andperforming a separated test operation in response to signals inputted by a user when the user test mode is selected.7. The method of claim 6 , wherein the separated test operation comprises a program operation claim 6 , a read operation claim 6 , or an erase operation on the basis of a value inputted by a user when the user mode is selected.8. The method of claim 7 , wherein the separated test operation comprises a portion of the program operation.9. The method of claim 7 , wherein the separated test operation comprises a portion of the read operation.10. The method of claim 7 , wherein the ...

Precharging circuit and semiconductor memory device including the same

A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.

Anti-fuse circuit and semiconductor integrated circuit including the same

An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND

The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. 1. A semiconductor integrated circuit comprising:a command decoder configured to provide a write command and to provide a read command;a read/write command controller configured to provide a write-read clock in synchronization with a first edge of a clock when the write command is activated, and provide the write-read clock in synchronization with a second edge of the clock when the read command is activated; anda command generator configured to provide a write-read command synchronized with the write-read clock;a column address latch unit configured to latch a column address in response to the write-read command.2. The semiconductor integrated circuit of claim 1 , wherein the read/write command controller comprises a burst signal generator which is configured to provide a burst signal in response to a burst length provided from an MRS (mode register set) claim 1 , and the command generator generates the write-read command in response to the burst signal.3. The semiconductor integrated circuit of claim 1 , further comprising a shift register unit claim 1 , the shift register unit comprising:a command shift register configured to shift the write command by the write latency by synchronizing the write command with the rising clock ...

COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME

A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a -bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. 1. A counting circuit , comprising:a first flip-flop (FF), a second FF, a third FF and a fourth FF, wherein each of the first to fourth FFs has an initial value decided according to a preset control signal input through a 4-bit set terminal, each of the first to fourth FF receiving a signal at a corresponding input terminal, and outputting the signal at a corresponding output terminal based on a clock signal;a fifth FF coupled to the output terminal of the fourth FF and configured to output the output signal of the fourth FF synchronously with the clock signal; anda logic operation unit for logically combining the output signals of the second to fourth FFs and for outputting first and second counting signals.2. The counting circuit of claim 1 , wherein the output terminal of each of the first to fourth FFs is coupled to an input terminal of a neighboring FF.3. The counting circuit of claim 1 , wherein the logic operation unit comprises:a first logic gate for performing an OR operation on the output signal of the second FF and the output signal of the fourth FF and for outputting the first counting signal; anda second logic gate for performing an OR operation on the output signal of the third FF and the output signal of the fourth FF and for outputting the second ...

Method of Forming Fine Patterns

A method of forming fine patterns comprises forming a first auxiliary layer having an acid diffusion rate on an underlying layer, forming a light-transmitting second auxiliary layer having a slower acid diffusion rate than the first auxiliary layer on the first auxiliary layer, exposing respective regions of the first and second auxiliary layers to generate acid in the exposed regions of the first and second auxiliary layers, diffusing the acid using a baking process so that diffusion of the acid is faster in the first auxiliary layer than in the second auxiliary layer, removing acid diffusion regions in the first and second auxiliary layers to form first and second auxiliary patterns, the second auxiliary pattern being wider width than the first auxiliary pattern, filling the removed regions of the first auxiliary layer with material for a hard mask, and removing the material for a hard mask exposed between the second auxiliary patterns to form hard mask patterns on sidewalls of the first auxiliary patterns. 1. A method of forming fine patterns , comprising:forming a first auxiliary layer having an acid diffusion rate on an underlying layer;forming a light-transmitting second auxiliary layer having a slower acid diffusion rate than the first auxiliary layer on the first auxiliary layer;exposing respective regions of the first and second auxiliary layers to generate acid in the exposed regions of the first and second auxiliary layers;diffusing the acid using a baking process so that diffusion of the acid is faster in the first auxiliary layer than in the second auxiliary layer;removing acid diffusion regions in the first and second auxiliary layers to form first and second auxiliary patterns, the second auxiliary pattern being wider width than the first auxiliary pattern;filling the removed regions of the first auxiliary layer with material for a hard mask; andremoving the material for a hard mask exposed between the second auxiliary patterns to form hard mask ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip. 1. A method for manufacturing a semiconductor package , comprising the steps of:defining a plurality of via-holes in at least two semiconductor chips in which each semiconductor chip has a plurality of bonding pads on upper surfaces thereof;forming first wiring lines on the upper surfaces of each of the semiconductor chips and on surfaces of the via-holes to be respectively connect to the bonding pads;forming second wiring lines on lower surfaces of the semiconductor chips so that the second wiring lines on lower surfaces are respectively connected with the first wiring lines on the respective upper surfaces; andstacking the semiconductor chips so that first wiring lines formed on an upper surface of an upwardly positioned semiconductor chip are respectively joined together with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.2. The method according to claim 1 , wherein the first wiring lines located on the upper surfaces and second wiring lines ...

PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. 1. A method of fabricating a phase-change memory device , the method comprising:forming a lower electrode comprising a PN diode structure including a junction of an N-type conductive layer and a P-type conductive layer;forming a plurality of heating elements on an upper one of the P-type conductive layer and the N-type conductive layer;selectively etching the upper one of the P-type conductive layer and the N-type conductive layer between the heating elements;forming a separated phase-change material layer on each of the heating elements; andforming a separated upper electrode on each phase-change material layer.2. The method of claim 1 , wherein each heating element is formed in a plug type claim 1 , a cup type or a cylinder type.3. The method of claim 2 , wherein the heating element is formed in the plug type by:forming an insulating layer having an open region that exposes the top of the upper one of the P-type conductive layer and the N-type conductive layer; andfilling the open region with a conductive material to obtain the heating element.4. The method of claim 2 , wherein the heating element is formed in the cup type by:forming an insulating layer having an open region that exposes the top of the upper one of the P-type conductive layer and the N-type conductive layer;forming a conductive layer over the insulating layer including the open region; andremoving the conductive layer outside the open region.5. The method of claim 2 , wherein the phase-change material layer is formed to cover only a portion of the respective heating element.6. The method of claim 1 , wherein each of the N-type conductive layer and the P-type conductive layer is formed of a ...

PHASE CHANGE MEMORY DEVICE TO PREVENT THERMAL CROSS-TALK AND METHOD FOR MANUFACTURING THE SAME

A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including to the lower electrodes having holes for exposing the respective lower electrodes. Heaters are formed on the surfaces of the respective holes to contact the lower electrodes. A second insulation layer is formed to fill the holes in which the heaters are formed. A mask pattern is then formed on the first and second insulation layers, including the heaters, to have openings that expose portions of the respective heaters having a constant pitch. A phase change layer is formed on the mask pattern including the exposed portions of the heaters and the first and second insulation layers and subsequently, upper electrodes are formed on the phase change layer. 1. A method for manufacturing a phase change memory device , comprising the steps of:forming an interlayer dielectric on a semiconductor substrate;etching the interlayer dielectric to form contact holes in a plurality of phase change cell regions of the semiconductor substrate;forming lower electrodes respectively in the plurality of phase change cell regions of the semiconductor substrate;forming a first insulation layer on the interlayer dielectric including the lower electrodes to have holes which expose the respective lower electrodes;forming a material layer for heaters on the first insulation layer including the holes;forming a second insulation layer on the material layer for heaters to fill the holes in which the material layer for heaters is formed;polishing chemically and mechanically the second insulation layer and the material layer for heaters to expose the first insulation layer, and thereby forming heaters on surfaces of the holes to be brought into contact with the lower electrodes;forming a mask pattern on the first and second insulation layers ...

METHOD FOR FABRICATING ETCHING BARRIER BY USING SHADOW EFFECT AND METHOD FOR FABRICATING ONE SIDE CONTACT OF VERTICAL TRANSISTOR USING THE SAME

A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies. 1. A method for fabricating an etching barrier , comprising:forming wall bodies on both sides of a trench in a semiconductor substrate; andforming an etching barrier over a first of two bottom edge portions of the trench by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein a second of the two bottom edge portions of the trench is selectively uncovered by the deposition due to a shadow effect by upper portions of the wall bodies.2. The method of claim 1 , wherein the forming of the wall bodies comprises:performing a selective etching process on the semiconductor substrate to form the trench so that the wall bodies are on both sides of the trench;forming a liner on surfaces of the wall bodies;filling available portions of the trench with a sacrificial layer; andreforming the trench by recessing the liner and the sacrificial layer so that an upper portion of the liner is exposed to the bottom edge portion of the reformed trench.3. The method of claim 1 , wherein the etching barrier is formed by sputtering deposition.4. The method of claim 3 , wherein the forming of the etching barrier comprises:mounting the semiconductor substrate on a chuck facing a target for the sputtering deposition; andtilting the chuck so that the surface of the semiconductor substrate is sloped with respect to the surface of the target.5. The method of claim 1 , wherein the etching barrier is formed by plasma-enhanced chemical vapor deposition (PECVD).6. A ...

Method of Forming Conductive Lines of Semiconductor Memory Device

A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns. 1. A method of forming conductive lines of a semiconductor memory device , the method comprising:forming a first polysilicon layer over an underlying layer;forming first polysilicon patterns by patterning the first polysilicon layer;filling a space between the first polysilicon patterns with an insulating layer;etching a top portion of the first polysilicon patterns to form recess regions;forming spacers on sidewalls of the recess regions;filling the recess regions with a second polysilicon layer to form second polysilicon patterns; andperforming a silicidation process to convert the second polysilicon patterns to metal silicide patterns.2. The method of claim 1 , wherein the spacers comprise materials that are different from materials of the insulating layer.3. The method of claim 1 , wherein the spacers comprise a nitride layer.4. The method of claim 1 , wherein the insulating layer comprises an oxide layer.5. The method of claim 1 , wherein a silicon concentration of the second polysilicon layer is lower than a silicon concentration of the first polysilicon layer.6. The method of claim 1 , comprising forming each of the second polysilicon layer and the first polysilicon layer using a silicon (Si) gas and a dopant gas.7. The method of claim 6 , comprising using a smaller amount of silicon (Si) gas when forming the second ...

SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME AND THICKNESS AND CAPABLE OF HIGH SPEED OPERATION AND METHOD FOR FABRICATING THE SAME

A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance. 1. A method for fabricating a semiconductor package , comprising the steps of:fabricating a semiconductor chip having a bonding pad in a portion of a first surface thereof;forming a through electrode passing through the semiconductor chip from the first surface to a second surface opposing the first surface, the through electrode being connected electrically to the bonding pad; andforming a redistribution pattern in the second surface of the semiconductor chip, the redistribution pattern being connected electrically to the through electrode.2. The method for fabricating a semiconductor package according to claim 1 , further comprising the step of:before the step of forming the through electrode, forming a first insulation pattern over the first surface, the first insulation pattern having an opening for exposing the bonding pad.3. The method for fabricating a semiconductor package according to claim 1 , wherein the step of forming the through electrode includes the steps of:forming a via hole passing through the bonding pad and formed at a predetermined depth in the semiconductor chip;forming a preliminary through electrode connected electrically to the bonding pad within the via ...

METHOD FOR FABRICATING STORAGE NODE OF SEMICONDUCTOR DEVICE

A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer. 1. A method for fabricating a storage node of a semiconductor device , comprising:forming a sacrificial dielectric pattern with a storage node hole on a substrate;forming a support layer on the sacrificial dielectric pattern;forming a storage node, supported by the support layer, in the storage node hole;performing a full dip-out process to expose the outer wall of the storage node; andperforming a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.2. The method of claim 1 , wherein the sacrificial dielectric pattern comprises an oxide layer containing carbon components.3. The method of claim 2 , wherein the oxide layer comprises a phosphosilicate (PSG) layer or a tetraethyl orthosilicate (TEOS) layer.4. The method of claim 2 , wherein the support layer comprises a nitride layer.5. The method of claim 1 , wherein the storage node comprises a titanium nitride layer.6. The method of claim 1 , wherein the storage node comprises a titanium layer/a titanium nitride layer.7. The method of claim 1 , wherein the bridge-causing material comprises a metal-carbon cluster that is a combination of the metal in the storage node and the carbon in the sacrificial dielectric pattern.8. The method of claim 7 , wherein the metal-carbon cluster comprises a titanium-carbon cluster.9. The method of claim 8 , wherein the cleaning process comprises:{'sub': 4', '2', '2', '2, 'a first cleaning process using a mixed solution of NHOH ...

SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME

A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. 1. A multi-chip package , comprising:a plurality of semiconductor memory apparatuses stacked on a substrate in stair-type configuration, each having a plurality of pads exposed along first edges thereof;a plurality of bonding wires, each electrically connecting the plurality of pads to the substrate;an encapsulant material formed on the substrate and molding the semiconductor memory apparatuses and the bonding wires; anda pad control section configured in each of the plurality of semiconductor memory apparatuses to control signal transmission between the plurality of pads and a corresponding one of the plurality of semiconductor memory apparatuses.2. The multi-chip package according to claim 1 , wherein the plurality of semiconductor memory apparatuses are stacked in a manner such that an upwardly positioned semiconductor memory apparatus and a downwardly positioned semiconductor memory apparatus are brought into direct contact to overlap with each other.3. The multi-chip package according to claim 1 , wherein each of the plurality of semiconductor memory apparatuses include first and second pad groups provided along opposing edges when viewed along a direction in which the substrate extends.4. The multi-chip package according to claim 3 , wherein the first and second pad groups receive signals from the pad control section.5. The multi-chip package according to claim 4 , wherein the pad control section is configured to provide first and second bonding signals for controlling signals from the first and second pad ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region. 1. A semiconductor device comprising:a semiconductor substrate including a cell region and a peripheral region;a mask pattern formed over the semiconductor substrate;a bit line contact hole extending through the mask pattern to expose the semiconductor substrate in the cell region;a bit line contact plug formed within the bit line contact hole and electrically coupling the semiconductor substrate; anda bit line formed over the bit line contact plug, the bit line and the bit line contact plug having substantially the same width.2. The semiconductor device according to claim 1 , wherein the mask pattern is a gate mask pattern used to define the recess claim 1 , the gate mask pattern including oxide or nitride claim 1 , or both.3. The semiconductor device according to claim 1 , further comprising a spacer provided at sidewalls of the bit line contact hole claim 1 , the spacer including oxide claim 1 , nitride claim 1 , or both.4. The semiconductor device according to claim 1 , wherein the mask pattern has a thickness ranging from 50 Å to 100 Å.5. The semiconductor device according to claim 1 , wherein the bit line includes:a barrier metal layer formed over the bit line contact plug;a bit line conductive layer formed over the barrier metal layer;a hard mask layer formed ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current. 1. A semiconductor device comprising:a semiconductor substrate including an active region defined by a device isolation film;a bit line hole disposed over the semiconductor substrate;a spacer disposed at sidewalls of the bit line hole, the bit line spacer including oxide and being free of nitride; anda bit line conductive layer formed in the bit line hole including the oxide film.2. The semiconductor device according to claim 1 , further comprising:a storage node contact hole formed to be adjacent to the bit line hole and exposing the semiconductor substrate; anda storage node contact plug formed in the storage node contact hole.3. The semiconductor device according to claim 2 , wherein the storage node contact plug includes:a lightly doped contact plug disposed in a lower portion of the storage node contact hole; anda highly doped contact plug disposed in an upper portion of the storage node contact hole and over the lightly doped contact plug.4. The semiconductor device according to claim 3 , wherein the spacer is disposed at sidewalls of the storage node contact plug claim 3 , the spacer contacting the storage node contact plug and the bit line conductive layer claim 3 , andwherein a thickness of the spacer formed proximate the lightly doped contact plug is thicker than that of the spacer formed proximate the highly doped ...

SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line. 1. A semiconductor device including a vertical transistor , the device comprising:an active region formed in a semiconductor substrate;a bit line disposed in a lower portion of the active region;a word line buried in the active region; anda capacitor disposed over an upper portion of the active region and the word line and being coupled to the bit line via the active region.2. The semiconductor device according to claim 1 , wherein to the word line and the active region are in contact and defining a step difference.3. The semiconductor device according to claim 1 , wherein the word line and the active region are in contact with substantially no step difference.4. The semiconductor device according to claim 1 , wherein the cross-sectional shape of the word line is rectangular or oval.5. The semiconductor device according to claim 1 , wherein the active region has a rectangular pillar shape or a cylindrical column shape.6. The semiconductor device according to claim 1 , further comprising a storage node contact coupled between upper portion of the active region and the lower portion of the capacitor.7. The semiconductor device according to claim 1 , wherein the word line is buried in the middle part of the active region or at one sidewall of the active region.8. The semiconductor device according to claim 1 , wherein an upper side end portion of the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method of manufacturing the same are provided. Upon forming source or drain at a lower part of the pillar pattern, a silicon oxide layer (barrier layer) is formed inside the pillar pattern to prevent the pillar pattern from being electrically floated. Furthermore, impurities are diffused to a vertical direction (longitudinal direction) of the pillar pattern to overlay junction between the semiconductor substrate and source or drain formed at a lower part of the pillar pattern that leads to improvement of a current characteristic. 1. A method for manufacturing a semiconductor device , comprising:forming a pillar pattern over a semiconductor substrate;forming a contact opening at one sidewall of the pillar pattern;etching a portion of the pillar pattern that is exposed by the contact opening;performing an oxidation process on the exposed portion of the pillar pattern to form an oxide layer in the pillar pattern;providing impurities into the pillar pattern through the contact opening to form a first electrode layer in the pillar pattern;forming a poly silicon layer pattern by filling the etched portion of the pillar pattern;forming a bit line at a lower portion of a space between the pillar pattern and an adjacent pillar pattern, the bit line being coupled with the poly silicon layer pattern; andforming a second electrode layer at an upper portion of the pillar pattern.2. The method of claim 1 , wherein the forming-a-pillar-pattern comprises:forming a hard mask layer over the semiconductor substrate; andetching the hard mask layer and the semiconductor substrate using a mask to form the pillar pattern.3. The method of claim 1 , wherein the forming-a-contact-opening comprises:forming a liner oxide layer and a liner nitride layer over the whole surface of a structure including the pillar pattern; andetching the liner oxide layer and the liner nitride layer until the semiconductor substrate at the one sidewall of the pillar pattern is exposed. ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The present invention relates to a semiconductor device and a method for forming the same. The semiconductor device includes: a vertical pillar protruded from a semiconductor substrate; a first junction region provided at an upper part of the vertical pillar; a second junction region provided in a lower part of the vertical pillar to be separated apart from the first junction region; and a gate oxidation layer in which a thickness thereof in a surface of the vertical pillar in which the first junction region is provided being thicker than that in a surface of the vertical pillar in which the first junction region is not provided. The present invention forms a gate oxidation layer using the oxidation rate difference without a mask process to minimize GIDL that leads to improvement in the characteristic of a semiconductor device. 1. A semiconductor device , comprising:a vertical pillar protruded from a semiconductor substrate;a first junction region provided at an upper portion of the vertical pillar;a second junction region provided proximate a lower portion of the vertical pillar and apart from the first junction region; and 'wherein a thickness of the gate oxidation layer in a surface of the vertical pillar in which the first junction region is provided is thicker than that on a surface of the vertical pillar in which the first junction region is not provided.', 'a gate oxidation layer,'}2. The semiconductor device of claim 1 , further comprising:a barrier metal pattern provided over a sidewall of the vertical pillar to be overlapped with the first junction region; anda gate pattern provided over the barrier metal pattern.3. The semiconductor device of claim 2 , further comprising a bit line metal layer spaced apart from the gate pattern and filling in a portion between the vertical pillars perpendicular to the gate pattern.4. The semiconductor device of claim 3 , further comprising a barrier metal layer provided on a sidewall and a bottom of the bit line metal ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing the same are provided. The method etches a gate metal material of a sidewall of the active region connected to the storage node contact deeper than a gate metal material of a sidewall of the active region connected to the bit line contact in a buried gate structure to prevent GILD and to reduce resistance of a buried gate, thereby improving refresh characteristics of the semiconductor device. 1. A method for manufacturing a semiconductor device , comprising:providing a conductive material below a surface of a semiconductor substrate;etching the conductive material provided below the surface of the semiconductor substrate;forming a first insulation layer over the conductive material and the semiconductor substrate;etching the first insulation layer and partially etching the conductive material to form a gate having a step profile; andforming a second insulation layer over the gate having the step profile.2. The method of claim 1 , further comprising:forming a device isolation region defining an active region at the semiconductor substrate;etching the semiconductor substrate using a gate mask; andforming a gate oxide layer over the etched semiconductor substrate.3. The method of claim 2 , wherein the active region includes a first active region coupled to a bit line contact and a second active region coupled to a storage node contact.4. The method of claim 3 , wherein a height of a conductive material coupled to the bit line contact and contacting with the active region is greater than that of a conductive material connected to the storage node contact and contacting with the active region.5. The method of claim 2 , wherein etching the semiconductor substrate comprises an anisotropic etching process.6. The method of claim 1 , wherein etching the conductive material comprises an etch-back process.7. The method of claim 1 , wherein the conductive material includes any of poly silicon claim 1 , aluminum (Al) claim 1 , ...

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed.

ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention provides an anti-fuse of a semiconductor device and a method of manufacturing the same, which has a stable current level and a stable operation. According to the present invention, in order for the anti-fuse to be stably operated, a region in which a gate and an active region partially overlap with each other is formed, and the overlapped region is destroyed when voltage is supplied. Accordingly, a current level can be stabilized, and stable operation is possible. 1. An anti-fuse of a semiconductor device comprising:an isolation layer defining an isolation region over a semiconductor substrate;a junction disposed in an active region;a gate pattern disposed over the semiconductor substrate and formed to partially overlap with the active region;a first contact plug coupled to the gate pattern; anda second contact plug coupled to the active region and the junction.2. The anti-fuse according to claim 1 , wherein the gate pattern includes a stack structure of a gate oxide layer and a gate electrode layer.3. The anti-fuse according to claim 1 , wherein each of the first and the second contact plugs is formed of a tungsten (W) layer claim 1 , a titanium (Ti) layer claim 1 , a titanium nitride (TiN) layer or a combination thereof.4. The anti-fuse according to claim 1 , wherein the active region overlaps with a corner of the gate pattern.5. An anti-fuse for a semiconductor device comprising:a gate patternformed in a device isolation region of a substrate and extending to an active region of the substrate;a junction formed in the active region;a first anti-fuse configured to insulate the gate pattern from the active region in a normal state, and further configured to couple the gate pattern to the active region in a repair state; anda second anti-fuse configured to insulate the gate pattern from the junction in the normal state, and further configured to couple the gate pattern to the junction in the repair state.6. The anti-fuse for a semiconductor ...

Semiconductor device and method for fabricating the same

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized. 1. A semiconductor device , comprising:a capacitor configured to include a lower electrode, a dielectric layer, and an upper electrode over a semiconductor substrate; anda first contact plug coupled to a sidewall of the upper electrode,wherein the upper electrode comprises a first region and a second region.2. The semiconductor device according to claim 1 , wherein the first region and the second region are formed at levels different from each other.3. The semiconductor device according to claim 1 , wherein the first region is in contact with the semiconductor substrate and includes a region where the lower electrode and the dielectric layer are not formed.4. The semiconductor device according to claim 1 , wherein the second region is disposed over the lower electrode.5. The semiconductor device according to claim 1 , wherein the first contact plugs are coupled to the sidewall of the upper electrode and the first region.6. The semiconductor device according to claim 1 , further comprising a second contact plug coupled to the second region.7. A semiconductor device claim 1 , comprising:an upper storage electrode pattern; anda first connection pattern extending ...

BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME

A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed. 1. A bonding pad , comprising:dummy patterns;an insulation layer that covers the dummy patterns;a recess pattern formed by selectively etching the insulation layer, wherein upper portions of the dummy patterns are protruded from the etched insulation layer, and wherein the etched insulation layer remains between lower portions of the dummy patterns; anda conductive pattern that covers the dummy patterns to fill spaces between the protruding upper portions of the dummy patterns to form the conductive pattern and the dummy patterns in direct physical contact,wherein the conductive pattern is later used in a bonding process.2. The bonding pad of claim 1 , further comprising an adhesion layer formed on sidewalls of the recess pattern.3. The bonding pad of claim 2 , wherein the adhesion layer is formed to have a spacer shape.4. The bonding pad of claim 1 , wherein the dummy patterns has are formed in a matrix shape claim 1 , the matrix shape having a plurality of slits therein.5. The bonding pad of claim 1 , wherein the dummy patterns protrude approximately 25% to approximately 75% of a vertical height of the dummy patterns above the surface of the etched insulation layer disposed between the dummy patterns.6. The bonding pad of claim 1 , wherein each of the conductive pattern claim 1 , the dummy patterns and the adhesion layer includes a metal layer.7. The bonding pad of claim 1 , wherein each of the conductive pattern claim 1 , the dummy patterns and the adhesion layer includes one selected from a group consisting of an aluminum (Al) layer claim 1 , a copper (Cu) layer claim 1 , and a tungsten (W) layer. The present invention is a Divisional Application of U.S. patent application Ser. No. 12/164,773, filed Jun. 30, 2008, which claims priority of Korean patent ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption. 1. A semiconductor device comprising:a first metal line buried in an interlayer insulation layer formed over a semiconductor substrate;a first insulating pattern formed over the interlayer insulating layer so that the first metal line is exposed, the first insulating pattern having a first portion and a second portion;a second insulating pattern formed between the first and second portions of the first insulating pattern so that the first metal line is exposed; anda third insulating pattern formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed.2. The semiconductor device according to claim 1 , wherein the first insulating pattern and the third insulating pattern are arranged in directions perpendicular to each other.3. The semiconductor device according to claim 1 , wherein the first metal line is exposed by the first insulating pattern claim 1 , the second insulating pattern claim 1 , and the third insulating pattern claim 1 ,wherein the first metal line is exposed by ⅔˜1 times a width of the first metal line.4. The semiconductor device according to claim 1 , wherein the first metal line is exposed in a form of a square.5. The semiconductor device according to claim 1 , wherein the second insulating ...

VOLTAGE DOWN CONVERTER

A voltage down converter includes a voltage comparator for comparing a first reference voltage and an internal voltage to provide a first driving signal; a driving signal controller coupled with the voltage comparator, the driving signal controller configured to generate a second driving signal in response to an external voltage and selectively providing any one of the first and second driving signals; and a voltage supply coupled with the driving signal controller, the voltage supply configured to receive the selectively provided first and second driving signals, wherein the voltage supply is activated in accordance with the first or second driving signal, thereby providing the internal voltage. 1. A voltage down converter , comprising:a voltage comparator for comparing a first reference voltage and an internal voltage to provide a first driving signal;a driving signal controller for sensing an external voltage to provide an output path of the first driving signal if the external voltage is a second reference voltage or more, and to provide an output path of a second driving signal if the external voltage is less than the second reference voltage; anda voltage supply that is controlled in accordance with the first driving signal or the second driving signal,wherein the first reference voltage and the second reference voltage have different level.2. The voltage down converter of claim 1 , wherein the driving signal controller comprises:a switching signal generator for sensing the external voltage and generating a switching signal;a first switching unit is turned on in response to a first voltage level of the switching signal;a second switching unit is turned on in response to a second voltage level of the switching signal; anda current source is connected to the second switching unit to provide the second driving signal to the second switching unit.3. The voltage down converter of claim 2 , wherein the first switching unit is connected to the voltage comparator ...

APPARATUS AND METHOD FOR COMPENSATING FOR BLACK LEVEL

An apparatus and method for compensating for a black level in order to solve a screen flickering phenomenon and a problem of convergence speed of a black level value. The apparatus for compensating for a black level includes: a black pixel average value extraction unit averaging black pixel values of a current frame to determine a black pixel average value; a luminance value extraction unit extracting a luminance value from an analog gain and concentration time information of an image sensor; a black level extraction unit calculating a frame weight by using the luminance value and acquiring a black level value of a current frame by using the frame weight, the black pixel average value, and a black level value of a previous frame; and a black level compensation unit compensating for valid pixel values of the current frame by using the black level value of the current frame. 1. An apparatus for compensating for a black level , the apparatus comprising:a black pixel average value extraction unit, operative to determine a black pixel average value of a current frame by averaging black pixel values of the current frame;a luminance value extraction unit, operative to extract a luminance value from an analog gain and concentration time information of an image sensor;a black level extraction unit, connected to the black pixel average value extraction unit and the luminance value extraction unit, operative to calculate a frame weight by using the luminance value and determine a black level value of a current frame by using the frame weight, the black pixel average value, and a black level value of a previous frame; anda black level compensation unit, connected to the black level extraction unit, operative to compensate for valid pixel values of the current frame by using the black level value of the current frame.2. The apparatus of claim 1 , wherein the luminance value extraction unit is operative to determine the luminance value by multiplying the analog gain by the ...

SEMICONDUCTOR MEMORY APPARATUS

A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering to an external data in accordance with the second external reference voltage. 1. A semiconductor memory apparatus comprising:a clock cycle detecting unit configured to enable a detection signal when a cycle of a clock signal is shorter than a predetermined cycle;a voltage selecting unit configured to selectively output a first voltage and a second voltage as a selection voltage in response to the detection signal;a first internal circuit configured to receive the first voltage; anda second internal circuit configured to receive the selection voltage.2. The semiconductor memory apparatus according to claim 1 , wherein the first voltage and the second voltage are at a same voltage level claim 1 , but are outputted from different power sources.3. The semiconductor memory apparatus according to claim 2 , wherein the clock cycle detecting unit includes:a pulse generating unit configured to generate a pulse that is enabled for a predetermined time, when a power-up signal is enabled;a counting unit configured to generate a counting signal by counting the clock signal for an enable section of the pulse; anda detection signal generating unit configured to enable the detection signal when a counted value of the counting signal is more than a predetermined value.4. The semiconductor memory apparatus according to claim 3 , wherein the counting unit initializes the counting signal in response to the power-up signal.5. The semiconductor memory apparatus ...

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS

A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. 15.-. (canceled)6. A method of fabricating a semiconductor device , the method comprising:forming a mask pattern for defining a region on a semiconductor substrate, wherein a field stop dopant layer will be formed in the defined region; andimplanting dopant ions into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.7. The method according to claim 6 , wherein the mask pattern is formed to expose the region in which the field stop dopant layer of an NMOS transistor will be formed claim 6 , and wherein implanting the dopant ions further comprises implanting Bions at a concentration of approximately 0.5×10atoms/cmto 1×10atoms/cmand at an energy of approximately 70 to 120 KeV.8. The method according to claim 6 , wherein the mask pattern is formed to expose the region in which the field stop dopant layer of a PMOS transistor will be formed claim 6 , and wherein implanting the dopant ions further comprises implanting Pions at a dose of approximately 0.8×10atoms/cmto 1.2×10atoms/cmand at an energy of approximately 200 to 300 KeV.914.-. (canceled) The present application claims priority to Korean patent application number 10-2006-0137138, filed on Dec. 28, 2006, which is incorporated by reference in its entirety.The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of ion implantation and a method of fabricating a semiconductor device which increases the production yield of the semiconductor device.A semiconductor memory device such as a dynamic random access memory (DRAM) stores data in and reads data from a plurality of memory cells. The semiconductor ...

ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoOlayer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer. 1. A method for forming a electrical conductor line of a semiconductor device , comprising the steps of:forming a metal line forming region in an insulation layer on a semiconductor substrate;{'sub': x', 'y, 'forming a multi-layered diffusion barrier on the metal line forming region of the insulation layer, the diffusion barrier comprising a TaN layer, an MoOlayer and an Mo layer; and'}forming a metal line on the diffusion barrier to substantially fill in the metal line forming region.2. The method according to claim 1 , wherein the step of forming the diffusion barrier comprises the steps of:forming a TaN layer on the metal line forming region of the insulation layer;depositing a first Mo layer on the TaN layer;{'sub': x', 'y, 'forming an MoOlayer by oxidating the first Mo layer; and'}{'sub': x', 'y', 'x', 'y, 'depositing a second Mo layer on the MoOlayer wherein the diffusion barrier is multi-layered having the TaN layer, the MoOlayer and the Mo layer.'}3. The method according to claim 2 , wherein the TaN layer has a thickness of about 5˜50 Å.4. The method according to claim 2 , wherein the first Mo layer has a thickness of about 5˜25 Å.5. The method according to claim 2 , wherein the step of forming the MoOlayer by oxidating the first Mo layer is implemented by utilizing a Oplasma process or by utilizing Ostuffing procedure.6. The method according to claim 5 , ...

NONVOLATILE MEMORY APPARATUS FOR PERFORMING WEAR-LEVELING AND METHOD FOR CONTROLLING THE SAME

Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages. 1. A nonvolatile memory apparatus comprising:a host interface;a memory controller coupled to the host interface; anda memory area comprising a plurality of chips controlled by the memory controller,wherein the memory controller is configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on a total erase count (TEC) of each logical group, and perform wear-leveling in a stepwise manner.2. The nonvolatile memory apparatus according to claim 1 , wherein the memory controller stores deviation information among erase counts (EC) of chips that are included in different logical groups but physically correspond to the same channel.3. The nonvolatile memory apparatus according to claim 2 , wherein the memory controller is configured to set a target logical group on which wear-leveling is to be performed by using the TEC of each logical group claim 2 , and trace a target chip within the target logical group by using the deviation information.4. The nonvolatile memory apparatus according to claim 3 , wherein claim 3 , when the target logical group is set claim 3 , the memory controller is configured to control the scan range of chips included in the corresponding logical group to vary according to a threshold value of the logical group.5. The ...

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier. 1. A method for manufacturing a semiconductor memory device , comprising:depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer;etching the mask layer and forming a mask pattern;etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier;etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier; andetching the bottom electrode layer by using the first top electrode layer as an etch barrier.2. The method according to claim 1 , wherein claim 1 , a magnetization reversal characteristic improvement layer is additionally formed between the MTJ layer and the first top electrode layer in the deposition of a bottom electrode layer claim 1 , a magnetic tunnel junction (MTJ) layer claim 1 , a first top electrode layer claim 1 , a second top electrode layer and a mask layer and undergoes the same subsequent processes after the deposition as the first top electrode layer.3. The method according to claim 2 , wherein the magnetization reversal characteristic improvement layer is formed of any one selected from the group consisting of Ru claim 2 , W claim 2 , Pt claim 2 , TIN and Ta.4. The method according to claim 1 , wherein the first top electrode layer is formed of a substance which has a high ...

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME

A method of forming semiconductor devices includes stacking an insulating layer and a polysilicon layer over a semiconductor substrate, forming a region where nitrogen (N) is scattered in a place adjacent to a surface of the polysilicon layer within the polysilicon layer using a plasma method, and depositing a doped polysilicon layer on the polysilicon layer including the region where nitrogen (N) is scattered. 1. A method of forming semiconductor devices , comprising:stacking an insulating layer and a polysilicon layer over a semiconductor substrate;forming a region where nitrogen (N) is scattered in a place adjacent to a surface of the polysilicon layer within the polysilicon layer; anddepositing a doped polysilicon layer on the polysilicon layer including the region where nitrogen (N) is scattered.2. The method of claim 1 , wherein the region where nitrogen(N) is scattered is formed to prevent a nitride layer from being formed in the polysilicon layer.3. The method of claim 1 , wherein the forming of the region where nitrogen (N) is scattered is performed using a plasma method.4. The method of claim 2 , wherein the plasma method is performed for 3 to 10 seconds.5. The method of claim 1 , further comprising:after forming the doped polysilicon layer,removing portions of the doped polysilicon layer, the polysilicon layer, and the insulating layer to expose the semiconductor substrate;forming trenches by etching the exposed semiconductor substrate; andforming isolation layers in the respective trenches.6. The method of claim 4 , further comprising additionally implanting impurities into the doped polysilicon layer claim 4 , after forming the isolation layers.7. The method of claim 5 , further comprising performing a rapid thermal process (RTP) for diffusing and activating the impurities within the doped polysilicon layer claim 5 , after additionally implanting the impurities.8. The method of claim 1 , wherein the doped polysilicon layer is deposited using an impurity ...

Pillar type capacitor of semiconductor device and method for forming the same

An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

DATA STROBE SIGNAL GENERATING DEVICE AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME

A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first dock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal. 1. A data strobe signal generating device , comprising:a preamble controller configured to generate a preamble signal enabled in synchronization with a first dock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled; anda data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal.2. The data strobe signal generating device as claimed in claim 1 , wherein the preamble controller includes:a first enable time adjusting unit configured to receive the output enable signal and the first dock signal to generate a first enable signal;a second enable time adjusting unit configured to receive the first enable signal and the second dock signal to generate a second enable signal; anda preamble pulse generator configured to receive the first and second enable signals to generate the preamble signal.3. The data strobe signal generating device as claimed in claim 2 , wherein the first enable time adjusting unit is configured to enable the first enable signal in synchronization with a rising edge of the first clock signal after the output enable signal is enabled.4. The data strobe signal generating device as claimed in claim 2 , wherein the second enable time adjusting unit is configured to enable the second enable signal in synchronization with a rising edge of the second dock signal after the first enable signal is enabled.5. The data strobe signal generating device as claimed in claim 2 , wherein the preamble signal is enabled from a time point at which the first enable signal is enabled to a time ...

METHOD AND SYSTEM FOR PROCESSING A REPAIR ADDRESS IN A SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair addresses stored in the repair address latch unit and a first plane address and a second plane address which are sequentially inputted. A repair processing unit is configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit under the control of a first plane signal, a second plane signal and a start pulse signal. 1. A semiconductor memory apparatus comprising:a memory device having a first plane and a second plane;a repair address latch unit configured to store a plurality of repair addresses corresponding to the first plane and the second plane;an address comparison unit configured to compare the plurality of repair addresses from the repair address latch unit and a first plane address and a second plane address which are sequentially inputted, and output a comparison result; anda repair processing unit configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit, under the control of a first plane signal, a second plane signal, and a start pulse signal.2. The semiconductor memory apparatus according to claim 1 , wherein the repair latch unit is configured to store the repair addresses for the first plane and the repair addresses for the second plane.3. The semiconductor memory apparatus according to claim 1 , wherein the first plane signal is asserted when the first plane address is inputted claim 1 , the second plane signal is asserted when the second plane address is inputted claim 1 , and the start pulse signal is a ...

DIFFUSING IMPURITY IONS INTO PILLARS TO FORM VERTICAL TRANSISTORS

A method for manufacturing a semiconductor device comprises: forming a pillar pattern including a sidewall contact over a semiconductor substrate; forming a silicon layer in a lower portion disposed between the pillar patterns; implanting ions into the silicon layer; diffusing the implanted impurity ions into the inside of the pillar pattern to form an ion-implanting region; removing the silicon layer; and burying a conductive material in the lower portion disposed between the pillar patterns. The method can prevent a floating body effect by adding a process of a vertical channel transistor. 1. A method for manufacturing a semiconductor device , the method comprising:forming pillar patterns, each including a sidewall contact hole in a first diffusion barrier layer, over a semiconductor substrate, the pillar patterns including first and second pillar patterns;forming a silicon layer between the first and second pillar patterns, wherein the silicon layer is an epitaxially grown silicon layer formed using a Silicon Epitaxial Growth (SEG) method;implanting impurity ions into the silicon layer;diffusing the implanted impurity ions from the silicon layer through the sidewall contact holes into the pillar patterns to form ion implanted regions;removing substantially all of the silicon layer after forming the ion implanted regions; andforming a conductive pattern between the first and second pillar patterns, the conductive pattern coupled to the ion implanted region, wherein the conductive pattern is formed of material other than the silicon layer.2. (canceled)3. The method according to claim 1 , wherein the pillar patterns each include silicon claim 1 , andwherein the SEG method is performed using the pillar patterns exposed by the sidewall contact holes as a seed.4. The method according to claim 1 , wherein the implanting-impurity-ions-into-the-silicon-layer is performed by a plasma doping process or a diffusion furnace process.5. The method according to claim 1 , wherein ...

VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME

A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. 1. A method for forming a vertical transistor , comprising the steps of:etching a semiconductor substrate and thereby defining grooves;forming screening layers on sidewalls of the grooves;forming a first epitaxial layer to fill the grooves;forming pillar type active patterns which is made of a second epitaxial layer, on the screening layers and portions of the semiconductor substrate which are positioned between portions of the first epitaxial layer;forming first junction regions and second junction regions in the first epitaxial layer and upper surfaces of the active patterns, respectively; andforming gates on sidewalls of the active patterns including the second junction regions, to overlap with at least portions of the first junction regions.2. The method according to claim 1 , wherein the step of defining grooves comprises the steps of:etching anisotropically a semiconductor substrate; andetching isotropically etched portions of the semiconductor substrate to increase a width of the etched portions of the semiconductor substrate.3. The method according to claim 1 , wherein the step of forming screening layers comprises the steps of:forming an insulation layer on the semiconductor substrate including surfaces of the grooves; andspacer etching the insulation layer such that the insulation layer remains only on sidewalls of the grooves.4. The method according to claim 3 , wherein the ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contract plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench. 19-. (canceled)10. A method of manufacturing a semiconductor memory device , the method comprising:providing a semiconductor substrate having junction regions and contact plugs formed thereon, the junction regions being formed between gate patterns and the contact plugs being connected to the corresponding junction regions in a first insulation layer with which the gate patterns are covered;forming a second insulating layer including first and second pad holes, wherein the first and second pad holes extend in different directions, the first and second pad holes exposing the contact plugs;forming first and second conductive pads in the first and second pad holes, respectively;forming a third insulating layer including dual damascene patterns and pad contact holes, wherein the dual damascene pattern exposes an extended portion of the first conductive pad, the pad contact hole exposing an extended portion of the second conductive pad;forming a first pad contact plug and a first bit line in the dual damascene pattern;forming a second pad contact plug in the pad contact ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device comprises: forming a plurality of first pillar patterns each of which includes a sidewall contact by selectively etching a semiconductor substrate; forming a buried bit line at a lower portion of a region between two neighboring first pillar patterns; forming a plurality of second pillar patterns by selectively etching upper portions of the first pillar patterns; and forming a gate coupling second pillar patterns arranged in a direction crossing the bit line, the gate enclosing the second pillar patterns. 1. A semiconductor device comprising:a plurality of first pillar patterns each of which includes a sidewall contact;a buried bit line disposed in a first direction at a lower portion of a region between two neighboring first pillar patterns; anda gate coupling second pillar patterns arranged in a second direction that intersects the first direction, the gate enclosing the second pillar patterns, wherein a plurality of second pillar patterns is disposed on a corresponding one of the first pillar patterns.2. The semiconductor device according to claim 1 , wherein the bit line includes tungsten or polysilicon.3. The semiconductor device according to claim 1 , wherein the bit line and the gate are perpendicular to each other.4. The semiconductor device according to claim 1 , wherein the gate is disposed over the bit line.5. The semiconductor device according to claim 1 , wherein the gate includes titanium nitride (TiN) claim 1 , tungsten claim 1 , or a combination thereof.6. A method for manufacturing a semiconductor device claim 1 , the method comprising:forming a plurality of first pillar patterns each of which includes a sidewall contact by selectively etching a semiconductor substrate;forming a buried bit line at a lower portion of a region between two neighboring first pillar patterns;forming a plurality of second pillar patterns by ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics. 1. A semiconductor device comprising:first and second buried gates;a landing plug formed between the first and second buried gates; anda damascene bit line coupled to the landing plug, the damascene bit line including a glue layer formed at a lower surface of the damascene bit line and an insulation layer formed over sidewalls of the damascene bit line.2. The semiconductor device according to claim 1 , wherein the insulation layer is disposed on the entire sidewalls of the damascene bit line or an upper portion of the sidewalls of the damascene bit line.3. The semiconductor device according to claim 1 , wherein the insulation layer includes an oxide film claim 1 , a nitride film claim 1 , or a combination thereof.4. The semiconductor device according to claim 1 , wherein the insulation layer includes an air layer or a vacuum layer.5. The semiconductor device according to claim 1 , wherein the glue layer includes a titanium nitride (TiN) film.6. The semiconductor device according to claim 1 , wherein the damascene bit line includes tungsten.7. The semiconductor device according to claim 1 , further comprising:a protection film formed over the ...

Semiconductor memory apparatus having sense amplifier

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

SEMICONDUCTOR APPARATUS AND METHOD FOR TRANSFERRING CONTROL VOLTAGE

A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the select signal transmission line; and a voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level. 1. A semiconductor apparatus comprising:a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines to second transmission lines in response to a select signal transmitted through a select signal transmission line;a select signal driving unit configured to drive the select signal to the select signal transmission line; anda voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level.2. The semiconductor apparatus according to claim 1 , further comprising:a boosting voltage generation unit configured to generate a boosting voltage by performing charge pumping,wherein the select signal driving unit drives the select signal by using the boosting voltage as a driving voltage.3. The semiconductor apparatus according to claim 1 , wherein the control voltage transfer unit comprises voltage transfer transistors which are electrically connected between the first transmission lines and the second transmission lines and are controlled by the select signal.4. The semiconductor apparatus according to claim 1 , wherein the select signal driving unit comprises at least one transistor which drives the select signal using a voltage of a driving voltage terminal under the control of a driving enable signal.5. The semiconductor apparatus according to ...

SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DISCHARGING WORDLINE THEREOF

Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a level lower than the first control voltage. The apparatus may also include a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; and a common discharge unit configured to discharge current flowing through the discharge current path. 1. A semiconductor apparatus comprising:a plurality of lines having a selected line and an unselected line, the selected line being driven by a first control voltage, the unselected line being driven by a second control voltage, the second control voltage being lower than the first control voltage;a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; anda common discharge unit configured to discharge current flowing through the discharge current path.2. The semiconductor apparatus according to claim 1 , wherein the unselected line comprises a plurality of unselected lines claim 1 , and the number of unselected lines is greater than the number of selected line.3. The semiconductor apparatus according to claim 2 , wherein the selected line comprises a plurality of selected lines.4. The semiconductor apparatus according to claim 1 , wherein the discharge control unit comprises:a diode connected between the discharge node and a first node; anda connecting part connected between the first node and the common ...

DATA INPUT CIRCUIT

A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation. 1. A data input circuit comprising:a valid strobe signal generation circuit configured to remove a pulse in an internal strobe signal and generate a valid strobe signal, wherein the pulse is generated during a preamble period; anda data strobe signal counter configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.2. The data input circuit of claim 1 , wherein the valid strobe signal generation circuit comprises:a transmission control signal generation block configured to generate a transmission control signal in response to a level of a data strobe signal before the preamble period; anda valid strobe signal extraction block configured to generate the valid strobe signal in response to a first internal strobe signal, a second internal strobe signal, and the transmission control signal.3. The data input circuit of claim 2 , wherein the transmission control signal generation block comprises:a signal generation unit configured to generate a first duration signal and generate a selection signal by comparing the data strobe signal with a reference voltage;an enable shifting unit configured to generate a second duration signal by shifting an enable time point of the first duration signal in response to the first internal strobe signal;a selection output unit configured to selectively transmit the first duration signal or the second duration signal as the ...

SEMICONDUCTOR MEMORY CHIP AND INTEGRATED CIRCUIT

A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line. 1. A semiconductor memory chip provided with a power supply voltage and a ground voltage comprising:a first data driving unit provided with the power supply voltage and the ground voltage and configured to drive first data to output the driven first data through a first data line;a second data driving unit provided with the power supply voltage and the ground voltage and configured to drive second data to output the driven second data through a second data line; anda MOS transistor coupled between the first data line and the second data line.2. The semiconductor memory chip of claim 1 , further comprising a driving voltage reception unit configured to receive the power supply voltage and the ground voltage and provide the power supply voltage and the ground voltage to the first and second data driving units.3. The semiconductor memory chip of claim 2 , wherein the driving voltage reception unit comprises a capacitor coupled between a power supply voltage transmission medium including a terminal and a ground voltage transmission medium including a terminal.4. The semiconductor memory chip of claim 2 , wherein components comprising the driving voltage reception unit and the first and second data driving units are packaged claim 2 , and wherein the power supply voltage and the ground voltage are provided to the first and second data driving units through power lines provided in the ...

MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS

A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode. 1. A multi-bit test circuit for a semiconductor memory , which is configured to cause an active command to activate active signals , wherein at least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.2. The multi-bit test circuit according to claim 1 , wherein the multi-bit test circuit comprises:a first active signal generation unit configured to input the active signals to even banks; anda second active signal generation unit configured to input delayed active signals acquired by delaying the active signals by a predetermined time, to odd banks.3. The multi-bit test circuit according to claim 2 , wherein the first active signal generation unit comprises a plurality of even bank address generation sections configured to generate even bank address signals by combining the active signals and even bank enable signals.4. The multi-bit test circuit according to claim 3 , wherein the second active signal generation unit comprises:an active delay section configured to output the delayed active signals acquired by delaying the active signals by the predetermined time;an active mode selection section configured to select any one signals of the delayed active signals inputted from the active delay section and the active signals in response to a test mode signal; andan odd bank address generation section configured to generate odd bank address signals by combining the delayed active signals or the active signals outputted from the active mode selection section with odd bank enable signals.5. The multi-bit test circuit according to claim 4 , wherein the active mode selection section comprises:a first active mode selection part configured to output the delayed active ...

SEMICONDUCTOR SYSTEM AND DATA TRAINING METHOD THEREOF

A semiconductor system includes a semiconductor memory configured to determine whether an error has occurred in a data pattern and generate an error signal, and a memory controller configured to provide the data pattern to the semiconductor memory and perform data training with respect to the semiconductor memory using the error signal. 1. A semiconductor system comprising:a semiconductor memory configured to determine whether an error has occurred in a data pattern and generate an error signal; anda memory controller configured to provide the data pattern to the semiconductor memory and perform data training with respect to the semiconductor memory using the error signal.2. The semiconductor system according to claim 1 , wherein the semiconductor memory includes an error detection circuit which is configured to generate the error signal by comparing an internal error check value generated by performing error check with respect to the data pattern with an external error check value provided by the memory controller.3. The semiconductor system according to claim 1 , wherein the semiconductor memory comprises:an error check logic configured to generate an internal error check value by performing an error check operation with respect to the data pattern; anda comparison unit configured to generate the error signal by comparing the internal error check value with an external error check value.4. The semiconductor system according to claim 1 , wherein the memory controller is configured to perform the data training with respect to the semiconductor memory using a variation in a shift time point of the error signal.5. The semiconductor system according to claim 1 , wherein the memory controller is configured to perform the data training by shifting the data pattern from an activation time point of the error signal to detect a deactivation duration of the error signal.6. A semiconductor system comprising:a plurality of semiconductor memories configured to generate an error ...

SEMICONDUCTOR PACKAGE FOR SELECTING SEMICONDUCTOR CHIP FROM A CHIP STACK

A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type. 1. A semiconductor package comprising:a plurality of semiconductor chips stacked while each having an arrangement of chip selection vias;a first connection unit provided between a first semiconductor chip and a second semiconductor chip stacked adjacent to each other, and configured to mutually connect some of the chip selection vias of the first and second semiconductor chips and disconnect the others of the chip selection vias of the first and second semiconductor chips; anda second connection unit provided between the first semiconductor chip and a third semiconductor chip stacked under the first semiconductor chip, and configured to connect chip selection vias of the first and third chip selection vias in inverse order of arrangement.2. The semiconductor package of claim 1 , wherein the semiconductor chips are the same type of chips.3. The semiconductor package of claim 1 , wherein the semiconductor chips comprise the chip selection vias having the same arrangement.4. The semiconductor package of claim 1 , wherein the semiconductor chips comprise as many chip selection vias as the stacked semiconductor chips.5. The semiconductor package of claim 1 , further comprising a third connection unit provided between the second semiconductor chip and a fourth semiconductor chip stacked on the second semiconductor chip claim 1 , and configured to connect chip selection vias of the second and fourth ...

CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME

A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node. 1. A circuit for generating a pumping voltage , comprising:a voltage applying unit configured to supply an external voltage to a first node in response to a first transmission signal;a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal; anda first outputting unit comprising a plurality of connection units.2. The circuit according to claim 1 , wherein each of the plurality of connection units is configured to interconnect the first node with a second node.3. The circuit according to claim 2 , wherein the plurality of connection units are driven to interconnect the first node and the second node when a second transmission signal is enabled.4. The circuit according to claim 1 , further comprising a control signal generation block configured to generate a plurality of control signals obtained by level-shifting a voltage level of a plurality of test signals to a plurality of driving voltage levels respectively claim 1 , wherein the plurality of control signals are operable to enable the ...