СВЯЗУЮЩАЯ СТРУКТУРА С ПРИМЕНЕНИЕМ ПРОЕАГИРОВАВШЕЙ БОРОСИЛИКАТНОЙ СМЕСИ

... 1. Смонтированная в корпусе система, содержащая окисляемую подложку (4), объект (16), прикрепляемый к указанной подложке, и прореагировавшую боросиликатную смесь (ПБС) (18, 20), закрепляющую указанный объект относительно указанной подложки посредством оксидного граничного с подложкой слоя (22). 2. Система по п.1, в которой указанная ПБС простирается между указанным объектом и указанной подложкой. 3. Система по п.1 или 2, в которой указанный объект является окисляемым, и оксидный граничный слой (24) прикрепляет указанную ПБС к указанному объекту. 4. Система проводников, содержащая подложку (4), по меньшей мере один электрический проводник (36) и прореагировавшую боросиликатную смесь (ПБС) (38), закрепляющую каждый из указанных проводников относительно указанной подложки на протяжении по меньшей мере части их длин. 5. Система, чувствительная к состоянию окружающей среды и содержащая подложку (4), датчик (16) состояния окружающей среды и прореагировавшую боросиликатную смесь (ПБС) (18, 20) ...

Halbleiteranordnung mit Metallplatte

Verfahren zum Kapseln intergrierter Schaltungen und über das Verfahren hergestellte integrierte Schaltungsbausteine

Verfahren zum Kapseln integrierter Schaltungen, umfassend: Anbringen einer ersten integrierten Schaltung an einer ersten Fläche eines Substrats mit einer elektrischen Verbindung zwischen entsprechenden Kontakten des Substrats und der ersten integrierten Schaltung; Anbringen einer zweiten integrierten Schaltung an einer zweiten Fläche eines Substrats mit einer elektrischen Verbindung zwischen elektrischen Kontakten des Substrats und der zweiten integrierten Schaltung; und einen Ausformschritt, bei dem die erste und zweite integrierte Schaltung in Harz gekapselt werden.

EPOXYHARZZUSAMMENSETZUNGEN UND DAMIT UMHUELLTE HALBLEITERVORRICHTUNGEN

EPOXIDHARZMASSEN UND DAMIT EINGEKAPSELTE HALBLEITERBAUTEILE

HALBLEITERBAUTEIL

Ein Halbleiterbauteil A1 der vorliegenden Offenbarung beinhaltet: ein Halbleiterelement 10 (Halbleiterelemente 10A und 10B), das eine Elementvorderfläche und eine Elementrückfläche hat, die in einer z-Richtung in einander entgegengesetzte Richtungen weisen; ein Trägersubstrat 20, das das Halbleiterelement 10 lagert; einen leitfähigen Block 60 (erster Block 61 und zweiter Block 62), der über ein erstes leitfähiges Bond-Material (Block-Bond-Materialien 610 und 620) an die Elementvorderfläche gebondet ist; und ein Metallelement (Anschlusselement 40 und Eingangs-Terminal 32), das über den leitfähigen Block 60 elektrisch mit dem Halbleiterelement 10 verbunden ist. Der leitfähige Block 60 weist einen Wärmeausdehnungskoeffizienten auf, der kleiner ist als jener des Metallelementes. Der leitfähige Block 60 und das Metallelement sind durch einen Schweißabschnitt (Schweißabschnitte M4 und M2), bei dem ein Abschnitt des leitfähigen Blocks 60 und ein Abschnitt des Metallelementes aneinander geschweißt ...

Epoxidharzzusammensetzung und Kunststoffumhüllte Halbleiteranordnung

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Verfahren zur Herstellung einer Harzvergossenen elektronischen Anordnung

Verfahren zur Herstellung einer Harzvergossenen elektronischen Anordnung

Halbleitervorrichtung, Verfahren zu deren Herstellung, und Leistungswandler

Eine Halbleitervorrichtung 100 umfasst eine Metallgrundplatte 1P, eine Gehäusekomponente 2, und eine Metallkomponente 3P. Die Metallkomponente 3P ist an der Gehäusekomponente 2 befestigt. Eine Teilregion der Metallkomponente 3P ist von der Gehäusekomponente 2 freigelegt. Die Teilregion ist mit der Grundplatte 1P in einem Verbindungsabschnitt 13P verbunden. Im Verbindungsabschnitt 13P stehen eine Fläche der Teilregion und eine Fläche der Grundplatte 1P in direktem Kontakt miteinander und sind integriert.

VERKAPSELTE ELEKTRONISCHE ANORDNUNG.

Halbleiteranordnung mit Filmträger.

Prüfen von Leitungen.

HALBLEITERBAUELEMENT MIT PASSIVIERENDER SCHUTZSCHICHT

Laminatpackung von Chip auf Träger und in Kavität

Eine Packung (100), umfassend einen Chipträger (102), hergestellt aus einem ersten Material, einen Körper (104), hergestellt aus einem zweiten Material, das sich vom ersten Material unterscheidet, und angeordnet auf dem Chipträger (102) zum Bilden einer Kavität (106), einen Halbleiterchip (108), mindestens teilweise in der Kavität (106) angeordnet, und ein Laminat (110), einkapselnd mindestens eines von mindestens einem Teil des Chipträgers (102), mindestens einem Teils des Körpers (104) und mindestens einem Teil des Halbleiterchips (108).

Vergossenes Leiterrahmengehäuse und Verfahren zu dessen Herstellung

Ein Halbleitervorrichtungsgehäuse beinhaltet einen Leiterrahmen und einen an dem Leiterrahmen montierten Halbleiterchip. Das Halbleitervorrichtungsgehäuse beinhaltet ferner einen Vergussverkapselungsstoff, der ausgelegt ist, den Leiterrahmen in Position zu vergießen. Ein Oberflächenbereich des Leiterrahmens verbleibt von dem Verkapselungsstoff freiliegend. Eine elektrisch isolierende Deckschicht erstreckt sich über einem Teil des Oberflächenbereichs und ist ausgelegt, den Oberflächenbereich in wenigstens zwei Zonen zu unterteilen.

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

UND VERFAHREN ZU SEINER HERSTELLUNG

Verfahren zur Passivierung einer schnellen Leistungsdiode durch eine Passivierungsschicht aus amorphem Kohlenstoff

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

IC-Baugruppe und Verfahren zur Herstellung einer IC-Baugruppe

IC-Baugruppe bzw. integrierter Schaltungsbaustein, umfassend: eine integrierte Schaltung mit einer Oberfläche bzw. -fläche, die wenigstens teilweise von einer Metallschicht bedeckt ist; wenigstens einen Verbindungspunkt; wenigstens einen Verbinder, der die integrierte Schaltung mit dem oder jedem Verbindungspunkt elektrisch verbindet; ein Verkapselungsmaterial, das den oder jeden Verbinder, wenigstens einen Teil der integrierten Schaltung und wenigstens einen Teil des oder jedes Verbindungspunktes derart verkapselt, dass eine Kontaktoberfläche bzw. -fläche des oder jedes Verbindungspunktes und die Metallschicht auf der integrierten Schaltung außerhalb des Verkapselungsmaterials freiliegen.

Kunststoffzusammensetzung

Es wird eine Kunststoffzusammensetzung zum Herstellen eines gehärteten Kunststoffmaterials zur Verfügung gestellt, das eine verbesserte Wärmefestigkeit und eine höhere Glasübergangstemperatur zeigt. Die Kunststoffzusammensetzung der vorliegenden Erfindung enthält Folgendes: einen Kunststoff, der aus a) einem hitzehärtbaren Kunststoff und einem Härter oder b) einem thermoplastischen Kunststoff gewählt ist; und einen anorganischen Füller mit einem mittleren Teilchendurchmesser von 1000 nm oder weniger.

Halbleitervorrichtung und Leistungsumsetzungsvorrichtung, die diese verwendet

Halbleitervorrichtung, die umfasst:ein Halbleiterelement; undeine Schichtstruktur, die eine erste Harzschicht, eine zweite Harzschicht und eine dritte Harzschicht enthält, die in dieser Reihenfolge geschichtet sind, um eine auf einer Seite des Halbleiterelements angeordnete Hauptelektrode zu bedecken,wobei die Schichtstruktur einen ersten Bereich (201) mit der ersten Harzschicht in Kontakt mit der zweiten Harzschicht und einen zweiten Bereich (202) mit der ersten Harzschicht in Kontakt mit der dritten Harzschicht enthält, wobei die beiden Bereiche um die Mitte des Halbleiterelements angeordnet sind,wobei zumindest ein Teil des zweiten Bereichs (202) näher zu der Mitte des Halbleiterelements als der erste Bereich (201) angeordnet ist,die erste Harzschicht durch Photolithographie gemustert ist undeine Begrenzung von zumindest einem Teil des zweiten Bereichs (202) als Muster für die Bilderkennung im Konfektionierungsprozess verwendet wird.

Bondpads mit unterschiedlich dimensionierten Öffnungen

Integrierter-Schaltkreis-Die (400), der Folgendes umfasst:mehrere Bondpads (401); undeine Die-Passivierungsschicht mit mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441), die mehrere der Bondpads (401) freilegen, wobei die mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441) zwei oder mehr Gruppen von Öffnungen umfassen, wobei jede Gruppe relativ zu der/den anderen Gruppe(n) eine unterschiedliche durchschnittliche Öffnungsgröße aufweist; und wobei Größen der mehreren unterschiedlich dimensionierten Öffnungen auf eine solche Weise variieren, dass Spannungen auf dem Die (400) aufgrund einer asymmetrischen Verteilung der mehreren Bondpads (401) wenigstens teilweise kompensiert werden.

Farbstrahldruckkopf mit ionischer Passivierung der elektrischen Schaltungen.

VERFAHREN UND APPARAT ZUM PACKEN INTEGRIERTER SCHALTUNGSCHIPS MIT EINER POLYMERFILM-BEDECKUNGSSCHICHT.

Flammhemmende Harzzusammensetzung und die daraus hergestellte Halbleitervorrichtung

VERFAHREN ZUR HERSTELLUNG EINES DIGITALEN FINGERABDRUCKSENSORS UND ENTSPRECHENDER SENSOR

Verfahren zum Erzeugen einer Schutzschicht auf einer Halbleiteranordnung mit mindestens einem p-n-UEbergang

Giessharzzusammensetzung, Verfahren zum Vergiessen eines elektronischen Bauelementes und vergossenes elektronisches Bauelement.

Halbleiteranordnung mit Leiterrahmen

STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Leistungshalbleitervorrichtung und Verfahren zum Herstellen einer Leistungshalbleitervorrichtung

Die Erfindung betrifft eine Leistungshalbleitervorrichtung, die ein Substrat (12) mit einer ersten Seite (14) und einer zweiten Seite (16) umfasst, wobei sich die erste Seite (14) und die zweite Seite (16) einander gegenüberliegend befinden, wobei die erste Seite (14) eine Kathode (18) umfasst und wobei die zweite Seite (14) eine Anode (20) umfasst, wobei ein Übergangsabschluss eines p/n-Übergangs bei wenigstens einer Oberfläche des Substrats bereitgestellt ist, bevorzugt bei wenigstens einer der ersten Seite (14) und der zweiten Seite, dadurch gekennzeichnet, dass der Übergangsabschluss durch eine Passivierungsbeschichtung (26) beschichtet ist, wobei die Passivierungsbeschichtung (26) wenigstens ein Material umfasst, das aus der Gruppe ausgewählt ist, die aus einem Anorganisch-Organisch-Verbundmaterial, Parylen und einem Phenolharz, das Polymerpartikel umfasst, besteht. Eine Vorrichtung (10), wie oben beschrieben, behandelt dementsprechend Probleme einer Passivierung von Übergangsabschlüssen ...

HALBLEITERELEMENT UND HALBLEITERBAUTEIL

Ein Halbleiterelement beinhaltet einen Hauptkörper und eine Vorderseitenelektrode. Der Hauptkörper beinhaltet eine Vorderseite, die in eine Dickenrichtung weist. Die Vorderseitenelektrode ist elektrisch mit dem Hauptkörper verbunden. Die Vorderseitenelektrode beinhaltet eine erste Sektion und eine Vielzahl von zweiten Sektionen. Die erste Sektion ist auf der Vorderseite vorgesehen. Die Vielzahl von zweiten Sektionen stehen in Kontakt mit der ersten Sektion und sind voneinander in einer Richtung beabstandet, die senkrecht ist zu der Dickenrichtung. Ein Gesamtflächenbereich der Vielzahl von zweiten Sektionen ist kleiner als ein Flächenbereich der ersten Sektion, einschließlich von Abschnitten, die mit der Vielzahl von zweiten Sektionen überlappen, und zwar in einer Ansicht in der Dickenrichtung.

Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zu seiner Herstellung

Elektrisches Bauelement,insbesondere Halbleiterbauelement,mit einer aus isolierendemStoff bestehenden Huelle

HALBLEITERBAUELEMENT MIT EINEM UEBERZUG AUS BLEIHALTIGEM ISOLIERSTOFF AM PN UEBERZUG

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Elektronisches Bauteil mit Halbleiterchip und Kunststoffgehäuse

Elektronisches Bauteil, das einen Halbleiterchip (1) mit einer Oberseite (2), mit einer Rückseite (3) und mit Randseiten (4, 5) und ein Kunststoffgehäuse (6) aufweist, wobei der Halbleiterchip (1) in dem Kunststoffgehäuse (6) derart eingebettet ist, dass die Rückseite (3) und die Randseiten (4, 5) des Halbleiterchips (1) von einer Kunststoffmasse (7) umgeben sind, wobei die Randseiten (4, 5) und die Rückseite (3) des Halbleiterchips (2) mindestens einen Verankerungsbereich (10) aufweisen, über den der Halbleiterchip (1) mit der umgebenden Kunststoffmasse (7) formschlüssig in Eingriff steht, dadurch gekennzeichnet, dass die Randseiten (4, 5) Ausbuchtungen (12) aufweisen, wobei die Ausbuchtungen mit Abrundungen versehen sind und die der Oberfläche am nächsten kommende Abrundung derart gestaltet ist, dass sich die Kunststoffmasse mit abnehmender Dicke an das Niveau der Oberseite des Halbleiterchips angleicht.

Integrated circuit manufacturing method of chip scale package, involves attaching solder balls in area that is uncovered by resist element, of patterned rewriting element, in patterned form

Integrated circuit (14) is mounted upside down on carrier (10), such that connection element (15) contacts with insulator (17), through the hole of carrier. Patterned rewriting elements (18, 19) attached in insulator, are internally connected by patterned solder resist element (20). Solder balls (22) are attached in area that is uncovered by resist element, of rewriting element, in patterned form. An Independent claim is also included for integrated circuit.

Production process for sensor chips in standard plastic housings, involves packing chip with sensor element into the housing and exposing sensor element using a laser

A process for producing a packaged sensor chip (2) having an integrated sensor element (3) in a housing (4) involves packing the chip in a plastic housing formed by injection molding and exposing the sensor element, preferably using a laser (7). An Independent claim is also included for a packaged sensor chip formed as above.

Plastics encapsulated semiconductor with surface terminals - on side edges and opposite sides of plastics encapsulation

The areal surface terminals cover each a side edge and contact surfaces of two opposite sides of the plastics encapsulation. The surface contacts are planar relative to these sides, or may possibly protrude over these sides in a slight manner. Preferably the terminals are in the form of U-shaped stirrups of flat strips, fitting into depressions in the plastics encapsulation. Originally straight strips may be used and subsequently bent from one side to the other. A two-layer metal band is stamped to obtain the metal strips which are connected each to one electrode of the semiconductor. This is followed by encapsulation of the assembly in plastics, preferably by injection moulding. Finally the individual strips are bent round the two sides.

HERSTELLUNG EINES BAUTEILS FÜR EINE HALBLEITERSCHALTUNG

GITTERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

VERBESSERTE POLYARYLENETHERZUSAMMENSETZUNGEN UND VERFAHREN ZU IHRER HERSTELLUNG

Gehäuseanordnung für elektronische Bauelemente und Verfahren zum Verpacken elektronischer Bauelemente

Gehäuseanordnung für mindestens ein elektronisches Bauelement, mit: – einem Substrat mit einer ersten und einer zweiten Oberfläche, wobei die erste Oberfläche mehrere erste und zweite Kontaktanschlüsse aufweist, die zweite Oberfläche mehrere Verbindungsanschlüsse aufweist und die ersten Kontaktanschlüsse mit den Verbindungsanschlüssen über Durchgangslöcher verbunden sind, – einer elastischen Pufferschicht zwischen der ersten Substratoberfläche und elektronischen Bauelement, wobei eine Oberfläche des elektronischen Bauelementes mit Elektroden gegenüber der ersten Oberfläche des Substrats angeordnet ist, die Pufferschicht mindestens eine Öffnung aufweist, um die mehreren ersten Kontaktanschlüsse freizulassen, die Pufferschicht den Rand des elektronischen Bauelementes umgibt und die einander zugewandten Befestigungsseiten des Randes des elektronischen Bauelementes und der Pufferschicht Schultern und Ecken/Zacken aufweisen und der Rand des elektronischen Bauelementes in die Pufferschicht eingedrückt ...

Verfahren und Anordnung zur Durchfuehrung des Verfahrens zur digitalen Auswertung der relativen Phase zweier Vergleichssignale,vorzugsweise zur Frequenznachstellung von Traegerfrequenz-Grundgeneratoren

GEKAPSELTES HALBLEITERBAUELEMENT

Kratzfeste Beschichtung für Halbleiterbauelemente

The aim of the invention is to increase the scratchproofness of a surface passivation, especially for fingerprint sensors. To this end, a sliding layer made of fat, oil, surfactants and/or wax is applied. Said layer reduces shearing forces. In a preferred embodiment, an emulsion made of water, paraffin oil, propyl glycol, lactarimic acid, cetylic acid, TEA, beeswax, carbomer 954, methylparaben, propylparaben and optionally perfume is used.

Charge carrier inversion layer prevention - by treating after etching with specified mixt. to remove surface defects

Charge carrier inversion layers are prevented on the surface of silicon thyristor modules by treating it after the etching operation with a mixture to remove any surface defects. The moisture contains 1 -20 wt.% phosphoric acid and 0.5 to 10wt.% hydrogen peroxide. The preferred composition is 4 parts by weight of 3% orthophosphoric acid and 1 part by weight of 30% hydrogen peroxide. This ensures that the pn-junctions between n-base, and p-base, and between n-base and p-emitter do not lose their efficiency.

Verfahren zur Herstellung eines elektronischen Bauelements und elektronisches Bauelement

Die Anmeldung betrifft ein Verfahren zur Herstellung eines elektronischen Bauelements (2). Bei dem vorgeschlagenen Verfahren wird zunächst eine Passivierungsschicht (3), die ein Polymer aufweist, auf einen Träger (1) aufgebracht. Anschließend wird ein Halbleiterchip (5) auf der Passivierungsschicht (3) so angeordnet, dass elektrisch aktive Bereiche des Halbleiterchips (5) der Passivierungsschicht (3) zugewandt sind. In einem weiteren Schritt wird der Halbleiterchip (5) mit der Passivierungsschicht (3) durch ein Aushärten des Polymers stoffschlüssig verbunden zum Fixieren des Halbleiterchips (5) auf der Passivierungsschicht (3). Daraufhin wird der Halbleiterchip (5) in eine Vergussmasse (8) vergossen. In einem weiteren Schritt wird eine Umverdrahtungslage (15) hergestellt, welche die Passivierungsschicht (3) und Leiterbahnen (14) umfasst. Dieser Schritt kann vor dem Anordnen des Halbleiterchips (15) auf der Passivierungsschicht (3) oder nach dem Vergießen des Halbleiterchips (5) durchgeführt ...

Vergußkapselung für einen auf einer Leiterbahnstruktur aufgesetzten Halbleiterbaustein sowie Halbleiterbaustein mit einer solchen Vergußkapselung

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

Mikrosensor mit Steckeranschluss

VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG

Anschlussleiterloses Package (100) mit:- einem zumindest teilweise elektrisch leitenden Träger (102), der einen Aufbaubereich (104) und einen Anschlussleiterbereich (106) aufweist;- einem elektronischen Chip (108), der an dem Aufbaubereich (104) angebracht ist,- einer Verkapselung (110), die zumindest teilweise den elektronischen Chip (108) verkapselt und teilweise den Träger (102) verkapselt, so dass zumindest ein Teil einer Innenseitenwand (112, 130, 132) des Anschlussleiterbereichs (106) freiliegt, die nicht einen Teil einer Außenseitenwand (115) des Packages (100) bildet, wobeider Anschlussleiterbereich (106) eine Mehrzahl von beabstandeten Anschlussleiterkörpern (118) aufweist, von denen zumindest einer eine zumindest teilweise freiliegende Innenseitenwand (112, 130, 132) hat, die nicht einen Teil der Außenseitenwand (115) des Packages (100) bildet, undeine Bodenfläche (116') der Verkapselung (110) zumindest eine Ausnehmung (198) hat, die zumindest teilweise zumindest eine der Innenseitenwände ...

HALBLEITERBAUELEMENT IM CHIP-FORMAT UND VERFAHREN ZU SEINER HERSTELLUNG

VERFAHREN ZUR HERSTELLUNG VON EINGEBETTETEN ELEKTRONISCHEN BAUTEILEN

INFO-POP-STRUK'I'UREN MIT HOHLRÄUME AUFWEISENDEN TIVS

Ein Verfahren beinhaltet ein Aufdosieren einer Opferregion über einem Träger und Bilden eines Metallstabs über dem Träger. Der Metallstab überlappt zumindest einen Abschnitt der Opferregion. Das Verfahren beinhaltet ferner ein Einkapseln des Metallstabs und der Opferregion in einem Einkapselungsmaterial, Abnehmen des Metallstabs, der Opferregion und des Einkapselungsmaterials vom Träger und Entfernen zumindest eines Abschnitts der Opferregion, um eine sich von einem Niveau einer Fläche des Einkapselungsmaterials aus in das Einkapselungsmaterial hinein erstreckende Vertiefung zu bilden.

Halbleitermodul mit Gehäusedurchkontakten

Die Erfindung betrifft ein Halbleitermodul (10) mit einem Gehäuse (52) einer Kunststoffmasse (43) und Gehäusedurchkontakten (44) von einer Gehäuseunterseite (45) zu einer Gehäuseoberseite (46). Dazu ist das Gehäuse (52) aus mindestens zwei Kunststoffschichten (9) und (19) aufgebaut, wobei die erste Kunststoffschicht (9) Außenkontakte (48) und Schichtdurchgangskontakte (50) aufweist. Eine Umverdrahtungsstruktur (4) trägt die zweite Kunststoffschicht (19), die Halbleiterchips (3) und (5) in einer Kunststoffmasse (43) umgibt, wobei in den Randbereichen des Halbleitermoduls (10) die Gehäusedurchkontakte (44) angeordnet sind.

Semiconductor component especially for low voltage power components has chip with contact bumps surrounded by conductive adhesive and electrodes shorted to a metal contact layer

A semiconductor component comprises housing (2) and chip (3) with a large surface contact between contact metal (5) on the chip and external contacts (6). Many small chip electrodes (7) are shorted to the contact metal and a transition layer (9) has contact bumps (11) surrounded by electrically conductive adhesive (12) on the contact metal.

Mesa semiconductor device with insulating surface film - has at least one pn-junction provided at chip surface and support element on one main surface

The chip of the mesa semiconductor device has one main surface, with at least one p-n junction (12) reaching the surface. The latter is coated by an insulating film (18). A supporting element is fastened to the other main surface. The insulating film (18) thickness increases with the distance from the chip main surface. Preferably, the semiconductor chip has two opposite mesa sections, succh as grooves and the insulating film covers a peripheral or edge surface of each mesa section. The insulating film may be of low melting point glass.

HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

TESTSYSTEM VON INTEGRIERTEN SCHALTUNGEN

Halbleitervorrichtung

Eine Halbleitervorrichtung kann ein erstes isoliertes Substrat, einen ersten Halbleiterchip sowie einen zweiten Halbleiterchip, die auf dem ersten isolierten Substrat angeordnet sind, ein zweites isoliertes Substrat, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der erste Halbleiterchip dazwischen angeordnet ist, und ein drittes isoliertes Substrat umfassen, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der zweite Halbleiterchip dazwischen angeordnet ist, und Seite an Seite mit dem zweiten isolierten Substrat angeordnet ist.

HALBLEITERBAUELEMENT MIT PASSIVIERTEM HALBLEITERKOERPER

HALBLEITERVORRICHTUNG

Halbleitereinrichtung

Halbleitereinrichtung, aufweisend:eine Radiatorplatte (1);eine auf der Radiatorplatte (1) angeordnete Harzisolierungsschicht (2);ein Gehäuse (8); undein Versiegelungsmaterial (10), das in ein Inneres des Gehäuses (8) gefüllt ist,gekennzeichnet durch einen Harzblock (11), der aus Harz besteht und ringförmig angeordnet ist, um einen Endteil der Radiatorplatte (1) und einen Endteil der Harzisolierungsschicht (2) zu bedecken;wobei das Gehäuse (8) angeordnet ist, um den Harzblock (11) zu bedecken;wobei das Gehäuse (8) über ein Haftmaterial (6) an den Harzblock (11) oder die Harzisolierungsschicht (2) gebondet ist; undwobei das Versiegelungsmaterial (10) und der Harzblock (11) durch das Haftmaterial (6) voneinander getrennt sind.

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Leistungshalbleitermodul und Verfahren zum Herstellen eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul umfasst ein erstes Substrat, wobei das erste Substrat Aluminium umfasst, eine auf dem ersten Substrat angeordnete erste Aluminiumoxidschicht, eine auf der ersten Aluminiumoxidschicht angeordnete leitende Schicht, einen ersten Halbleiterchip, wobei der erste Halbleiterchip auf der leitenden Schicht angeordnet und mit dieser elektrisch verbunden ist und ein elektrisches Isolationsmaterial, das den ersten Halbleiterchip umschließt, wobei die erste Aluminiumoxidschicht dazu ausgebildet ist, den ersten Halbleiterchip von dem ersten Substrat elektrisch zu isolieren.

Hochfrequenz-Halbleitervorrichtung

Verfahren zum Verkapseln von elektrischen oder elektronischen Bauelementen oder Baugruppen und Verkapselung von elektrischen oder elektronischen Bauelementen oder Baugruppen

Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier

The arrangement has the semiconductor chip (1) mounted on the chip carrier (2) and enclosed by a resin mass (3) or an insulation layer, before application of a conductive coating (4) to the opposite side of the semiconductor chip to the chip carrier, in the form of a conductive layer applied to the resin mass or insulation layer and connected to a metal layer (7) applied to the chip carrier, e.g. a low-pass filter layer. Also included are Independent claims for the following: (a) a chip card; (b) a chip module ...

Halbleiterbauteil

Halbleiterbauteil, mit: einem Substrat, das eine Hauptfläche aufweist; einem Halbleiterelement, das auf der Hauptfläche montiert ist und das eine Hauptflächenelektrode beinhaltet, die in der gleichen bzw. in die gleiche Richtung orientiert ist wie die Hauptfläche; einem Verbindungs-Pad, das aus Cu gebildet ist, das in einer ersten Richtung, die parallel ist zu der Hauptfläche, von dem Substrat getrennt ist, und das eine Verbindungsfläche beinhaltet, die in der gleichen Richtung orientiert ist wie die Hauptfläche; einer plattierten Schicht, die aus Ni gebildet ist und die die Verbindungsfläche teilweise bedeckt; einem Draht, der aus Al gebildet ist und der ein erstes Ende, das an die Hauptflächenelektrode gebondet ist, und ein zweites Ende aufweist, das an die plattierte Schicht gebondet ist; und einem Verkapselungsharz, das das Halbleiterelement, das Verbindungs-Pad, die plattierte Schicht und den Draht verkapselt.

GLASVERSIEGELTE HALBLEITERANORDNUNG BESTEHEND AUS EINEM HALBLEITERKÖRPER MIT EINER SILBER-KUPFER-VERBINDUNGSSCHICHT ZWISCHEN SENKE UND VERBINDUNGSLEITERN

Protective coating for electronic device contg. fluorinated acrylate] - and/or fluorinated polyurethane and opt. acrylic] resin, applied as organic soln.

Protective surface coating material for electronic devices consists of (a) 0.01-2 (wt.)% fluorinated acrylate (IA) and/or fluorinated polyurethane ((B) and 99.99-98% completely or partly fluorinated hydrocarbon cpd. (II); or (b) 0.01-2% (I), 1.5-35% acrylic resin (III) and 98.49-63% organic solvent (IV). Pref. (IA) is an N-lower alkyl-perfluoroalkylsulphonamido-acrylic acid, -acrylamide, -acrylonitrile or -alkyl (meth)acrylate; ((B) a reaction prod. of an N-lower alkyl-perfluoroalkylsulphonamidoalkanol and isocyanate; (III) a resin from acrylic acid, alkyl acrylate, methacrylate, acrylonitrile, N-vinylpyrrolidone, styrene or 2-chloro-styrene; and (IV) a mixt. of MEK and butyl acetate. USE/ADVANTAGE - The compsn. is claimed for coating circuit boards and laminated substrates. Good protection is obtd. and selective coating is unnecessary, which improves the efficiency and quality.

Bonding wire protecting device, has bonding sites provided on circuitry carrier e.g. circuit board, and plug connector, where bend protection units are provided on regions of bonding wire

The device has bonding sites provided on a circuitry carrier (20) e.g. circuit board, and a plug connector (22). Bend protection units e.g. medium-soft or medium-hard silicone cappings, are provided on regions of a bonding wire (16). The silicone cappings are provided with hardness of 20-80 shore and vulcanized by UV-radiation. The silicone cappings comprise an elastic module region that lies between 0.5 to 10 Newton per square millimeter. The circuitry carrier is arranged in a sensor housing (12).

Protecting wiring on wafers/chips comprises covering wafer with wiring on its whole surface with organic layer to protect wiring from corrosion and oxidation and form sealed coating

Protecting the wiring on wafers/chips comprises covering the wafer (1) with the wiring on its whole surface with an organic layer (12) to protect the wiring from corrosion and oxidation and form a sealed coating of the metal surface of the wiring.

Verfahren zum Schutz einer Umverdrahtung auf Wafern/Chips

Verfahren zum Schutz der Seitenkanten einer Umverdrahtung auf Wafern oder Chips, die aus einer Seed-Layer, einer auf dieser befindlichen Kupferschicht, einer darauf angeordneten Nickel-Schicht, und einer diese abdeckenden Goldschicht besteht, wobei der mit der Umverdrahtung (1) versehene Wafer (4) leicht angeätzt wird, dass der Wafer (4) oder ein Flüssigkeitsvorrat eines organischen Materials zunächst auf eine Temperatur von ca. 30 °C erwärmt wird und dass der Wafer (4) anschließend auf seiner gesamten Oberfläche mit einer organischen Schutzschicht (12) dieses organischen Materials versehen wird und dass durch chemische Bindung eine dichte Belegung der Metalloberfläche der Umverdrahtung (1) erzeugt wird.

Halbleiterpackung und Herstellungsverfahren hierfür

Die Erfindung bezieht sich auf eine Halbleiterpackung und ein Verfahren zur Herstellung einer solchen. DOLLAR A Erfindungsgemäß beinhaltet die Halbleiterpackung einen Halbleiterchip (100) mit je einem integrierten Schaltungsaufbau auf beiden Seiten (A, B), ein Substrat (110), erste und zweite Bonddrähte (130, 132), ein erstes und zweites Abdichtungsmaterial (140, 142) und eine Mehrzahl von Lotkugeln (150). DOLLAR A Verwendung in der Halbleiterpackungstechnologie.

Integrated component, especially for use in motor vehicle, has protective medium with edge- and corner-free surface; protective medium has essentially square surface with rounded edges and corners

The integrated component (1) has a number of internal components with a number of connection contacts (2) and a protective medium (3) enclosing the internal components. The protective medium has an edge- and corner-free surface. The protective medium has an essentially square surface with rounded edges and corners.

Compact semiconductor element comprises a wafer having a chip region, a substrate arranged on the chip region, conducting bodies, a distancing device between the wafer and the substrate and component contacts

Compact semiconductor element comprises a wafer having a chip region, a substrate arranged on the chip region, conducting bodies, a distancing device between the wafer and the substrate and component contacts. Compact semiconductor element comprises a wafer having a chip region (10) with a dielectric contacting assembly surface (101) provided with several contacting spots (100) for the access to the inner circuits of the chip region; a substrate arranged on the chip region of the wafer and having a switching arrangement lying over the assembly surface; conducting bodies (30) arranged between the assembly surface and the switching arrangement surface to connect contacting spots to soldering points; a distancing device between the wafer and the substrate; and component contacts formed on another surface of the substrate opposite the switching arrangement. An Independent claim is also included for a process for the production of the semiconductor element. Preferred Features: The distancing ...

Semiconductor chip arrangement for flip chip; has base plate metallized rear surface and source and gate contacts connected to contacts of connection frame and has casing with window near rear surface

The arrangement (10) has a connection frame with a number of contacts (20). A base plate with a metallized rear surface (14) and source and gate connectors is connected to the connection frame, so that the contacts are connected directly to the connectors. A casing with windows surrounds at least part of the connection frame and the base plate. The base plate is positioned with respect to the casing, so that the rear surface is near a window. An Independent claim is included for a method for manufacturing the arrangement.

IMPROVEMENTS IN OR RELATING TO METHODS OF MOUNTING ELECTRONIC COMPONENTS ON SHEET-LIKE SUPPORTS

... 1,216,827. Moulding plastic substances. HONEYWELL Inc. 25 April, 1969 [6 May, 1968], No. 21150/69. Heading B5A. [Also in Division H1] An electronic component is mounted on a sheet-like support by forming a perforation in the support, placing one face of the support against a surface composed of a "mould-release" material, inserting the component in the perforation so that its terminals lie against the mould-release surface, filling the remainder of the perforation with a hard-cure plastics material to secure the component and removing the support from the mould release surface when the plastics material has cured. As shown, Fig. 3, a ceramic circuit board 1 is placed on a plate 5 the upper surface 7 of which is coated with a mould-release material such as P.T.F.E., an integrated circuit chip 2 is arranged in a perforation in the circuit board and is retained by a positioning device 6 while the perforation is filled with epoxy resin 3 which is cold or hot cured. The assembly is then removed ...

Method of depositing oxide film

Al, B or Al-B silicate glass film is deposited on a substrate by sputtering Si in an atmosphere containing A, O2 and volatile alkoxides or alkyds e.g. B isopropylate, Al ethoxide and Al isopropoxide. In a vacuum chamber 10 the substrate 13 e.g. a semi-conductor is mounted on a steel, water cooled, grounded anode 12 beneath a cathode 11 attached to a heat sink 15 and shielded by screen 14. The sputtering rate may be increased by a magnetic field. The volatile compounds are introduced by bubbling A and O2 through B isopropylate and A ethoxide in tank 23 or over the frozen liquid.ALSO: Al, B or Al-B silicate glass film is deposited on a substrate by sputtering Si in an atmosphere containing A, O2 and volatile alkoxides or alkyds e.g. B isopropylate, Al ethoxide and Al isopropoxide. In a vacuum chamber 10 the substrate 13 e.g. a semi-conductor is mounted on a steel, water-cooled, grounded anode 12 beneath a cathode 11 attached to a heat sink 15 and ...

Semiconductor rectifier devices

... 1,079,197. Semi-conductor diodes. SIEMENS-SCHUCKERTWERKE A.G. June 27, 1966 [June 25, 1965], No. 28786/66. Heading H1K. A monocrystalline semi-conductor wafer containing a PN junction 4 has one major face completely covered by a first electrode 5 of which the outer face is covered by a first contact plate 6, a central region of the other major face being covered by a second electrode 7 which is of smaller area than the first and which has a second contact plate 8 thereon; the inner face of this second contact plate 8 is larger than the outer face of the smaller electrode 7 (with which it is in contact) and extends beyond it all round its periphery through less than 1 mm., whereas the PN junction 4 emerges at the surface of the wafer in a line which is nowhere less than 1 mm. from the smaller electrode 7. A channel (10, Fig. 2) surrounding the smaller electrode 7 may be etched or sand-blasted in the wafer to a sufficient depth to cut through the PN junction 4, and the wafer and/or the second ...

Semiconductor devices

... 1,104,515. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. 9 Aug., 1965 [8 Aug., 1964], No. 34085/65. Heading H1K. A semi-conductor body is clamped between pressure members via members the expansion coefficient of which matches that of the body. The members are bonded to the body and a synthetic resin covering extends around the periphery of the member-body assembly on to opposite end faces of the members. In an embodiment the semi-conductor body is of lightlydoped P-type silicon with heavily doped P and N type surface zones. The members are mushroom-shaped and after their attachment, by alloying or soldering, to the surface zones the silicon body is peripherally etched and the resulting recess between the heads of the members filled with alizarin in a synthetic resin. The resin covering, e.g. of epoxy, polyester or silicone which is then applied to form a U-section ring about the device may be keyed to the outer faces of the mushroom heads with the aid of grooves, elevations or depressions ...

Process for Packaging Multilead Semiconductor Devices and Resulting Product.

... 1,197,751. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 18 July, 1967 [29 July, 1966], No. 33023/67. Heading H1K. A semi-conductor body 48 containing an integrated circuit is positioned in an aperture in an insulating support 42 so that contact pads on the body 48 engage the ends 46a of conductive strips 46 on the support 42, which ends 46a overlap the aperture. The outer ends 46b, which extend to or almost to the periphery of the support 42, are at least as far apart as the inner ends 46a and, in the embodiment shown, comprise lands to which are attached terminal pins 50 extending through the support 42 to enable the assembly to be plugged into a socket. Plastics encapsulant 52 encloses the assembly. In another embodiment tapering conductive strips (86), Fig. 8 (not shown), extend radially from a semi-conductor body (88) situated in a circular aperture (84) in the insulating support (82), and terminate at the four outer edges of the support (82). A heatconducting metal plate (90) is ...

SEMICONDUCTOR PACKAGE

ENCAPSULATED MICROCIRCUIT DEVICE

... 1,269,341. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORP. 18 March, 1969 [21 March, 1968], No. 14105/69. Heading H1K. A semi-conductor device comprising a wafer of semi-conductor material having a contact pattern surrounded by a layer of alumina is provided with at least one film of silica glass doped with an oxide of at least one of the elements boron, arsenic and phosphorus. In a first embodiment, Fig. 1 (not shown), an integrated circuit having a surface layer of Al 2 O 3 over which extend conductors is encapsulated by a glass layer through which are formed windows to expose areas of the conductors. In a second embodiment, Fig. 2 (not shown), a silicon dioxide layer is covered with a layer of alumina over which first level connections are formed. A glass layer is deposited, windows are formed, and second level connections are formed, which are themselves covered with a glass layer. The glass layer may be produced by thermal decomposition of tetraethoxysilane, Si(OC 2 H 5 ) 4 , in ...

Semiconductor fabrication with contact processing for wrap-around flange interface

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Leadframe for ic package and method of manufacture

A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Circuit Board Packaged with Die through Surface Mount Technology

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Semiconductor device package with electromagnetic shielding

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

Method for semiconductor leadframes in low volume and rapid turnaround

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Semiconductor device and method of forming the same

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Method of post-mold grinding a semiconductor package

A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Semiconductor package and method for manufacturing the same

Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Component built-in module, and manufacturing method for component built-in module

A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Package structure of transient voltage suppressor

A package structure of transient voltage suppressor is disclosed. The package structure comprises a package housing with a bottom thereof having a first contact pin, a second contact pin, and a third contact pin, wherein the third contact pin is positioned between the first contact pin and the second contact pin. A first diode is positioned in the package housing, and an anode and a cathode of the first diode are respectively connected with the third contact pin and the first contact pin. A second diode is installed in the package housing, and an anode and a cathode of the second diode are respectively connected with the third contact pin and the second contact pin.

Fabrication method of semiconductor integrated circuit device

Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.

Method for manufacturing a semiconductor device having a heat spreader

A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, the resin sealing body including a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader, wherein the cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board, wherein the shaving the resin sealing body from the side of the wiring board is carried out after the shaving from the side of the heat spreader, and wherein the resin sealing body is completely cut off by the shaving from the side of the wiring board, and mounting a group of ball-like electrodes at a back side of the wiring board.

Semiconductor device

According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

Conductive chip disposed on lead semiconductor package and methods of making the same

In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

Semiconductor device and method of packaging same

A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad.

Semiconductor device and communication method

A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.

Multiple die in a face down package

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Die package including encapsulated die and method of manufacturing the same

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized

Method Of Manufacturing Package-On-Package (Pop)

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

Radiation-shielded semiconductor device

A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Apparatus for integrated circuit packaging

Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

Packages and Method of Forming the Same

A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Protective layers in semiconductor packaging

A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads.

Method of forming an electronic package and structure

In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side. 1. A method of manufacture of an integrated circuit packaging system comprising:providing a substrate;mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; andforming an under-fill between the integrated circuit and the substrate having a cast side.2. The method as claimed in wherein forming the under-fill includes forming the cast side having chemical etchant traces claim 1 , etching marks claim 1 , pitting claim 1 , stress lines claim 1 , deformation lines claim 1 , surface degradation or a combination thereof.3. The method as claimed in wherein:providing the substrate includes providing the substrate having an opening traversing the height of the substrate; andforming the under-fill includes dispensing the under-fill through the opening with the cast side formed between the integrated circuit and the substrate.4. The method as claimed in further comprising forming an encapsulation encapsulating the cast side.5. The method as claimed in wherein forming the under-fill includes forming the cast side vertical and planar.6. A method of manufacture of an integrated circuit packaging system comprising: borderproviding a substrate;forming a flow restrictor on the substrate;mounting an integrated circuit above the substrate and adjacent to the flow restrictor with an interconnect directly connecting between the substrate and the integrated circuit;forming an under-fill between the integrated circuit and the substrate, and the under-fill in direct contact with the flow restrictor; andcreating a cast side of the under-fill by removing the flow restrictor.7. ...

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Integrated circuit packaging system with terminals and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

Device

A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.

Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Method for producing a component and device comprising a component

A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Semiconductor device and method of packaging a semiconductor device with a clip

A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Methods of manufacturing semiconductor devices including terminals with internal routing interconnections

A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages.

Conductive chip disposed on lead semiconductor package and methods of making the same

In one implementation, a method of forming a conductive device can include depositing a non-conductive epoxy on a first portion of a lower surface of a semiconductor die, and can include depositing a conductive epoxy on a second portion of the lower surface of the semiconductor die.

Semiconductor package and fabrication method thereof

A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.

Substrate for semiconductor package and method of manufacturing thereof

Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Package with Passive Devices and Method of Forming the Same

An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance

Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

Method for plating a semiconductor package lead

A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

Methods of making packages using thin cu foil supported by carrier cu foil

In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Wiring board and method for manufacturing wiring board

A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.

Semiconductor package and method of manufacturing the same

A semiconductor package is provided with a package on package (PoP) configuration, and which may be implemented having a fine pitch. The semiconductor package can include a lower printed circuit board (PCB) having a top surface onto which at least one lower semiconductor chip is attached; an upper printed circuit board (PCB) disposed on the lower printed circuit board (PCB) and having a top surface onto which at least one upper semiconductor chip is attached; and a lower mold layer formed on the top surface of the lower printed circuit board (PCB) so as to be disposed between the lower printed circuit board (PCB) and the upper printed circuit board (PCB). A through via hole, including a first section formed in the lower mold layer and a second section formed on the first section can also be provided. The through via hole extends through the lower mold layer, and a solder layer is formed in the through via hole to electrically connect the upper printed circuit board (PCB) and the lower printed circuit board (PCB). A horizontal cross-sectional area of the first section of the through via hole varies over substantially an entire height of the first section, and a horizontal cross-sectional area of the second section gradually decreases from a top surface thereof toward an inner portion of the lower mold layer.

Electronic devices including emi shield structures for semiconductor packages and methods of fabricating the same

An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant over the semiconductor die;forming a recess in the encapsulant;forming an interconnect structure over the semiconductor die; andremoving a first portion of the encapsulant.2. The method of claim 1 , wherein forming the recess further includes removing a second portion of the encapsulant while leaving the first portion of the encapsulant.3. The method of claim 1 , further including:disposing a support structure within the recess prior to forming the interconnect structure; andremoving the support structure after forming the interconnect structure.4. The method of claim 1 , further including forming the recess over the first semiconductor die and outside a footprint of the semiconductor die.5. The method of claim 1 , further including:providing a second semiconductor die; andforming the recess over the first and second semiconductor die.6. The method of claim 1 , further including disposing a support member ...

Semiconductor Device Having a Clip Contact

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Resin-encapsulated semiconductor device and method of manufacturing the same

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

Method for producing multi-layer substrate and multi-layer substrate

A mounting-completed core parent substrate in which surface mount devices are mounted on both principal surfaces of the core parent substrate including a plurality of the core individual substrates and having a through hole formed in each core individual substrate so as to extend therethrough is formed. Then, resin layers in a partially cured state are formed on both the principal surfaces of the core parent substrate and the resin layers on both the principal surfaces are joined through the through holes so that the resin layers on both principal surfaces of each core individual substrate are joined and integrated to each other at a predetermined region, each core individual substrate being obtained by dividing the core parent substrate. After that, the resin layers are subjected to main curing. Thereafter, the core parent substrate is divided at a predetermined position and separated into the core individual substrates.

Integrated circuit package

An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner.

Semiconductor package

Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE USED THEREFOR

A semiconductor module includes a first heat sink member, a semiconductor device, a second heat sink member, a lead frame, a second sealing member. The semiconductor device includes a semiconductor element, a first sealing member for covering the semiconductor element, a first wiring and a second wiring electrically connected to the semiconductor element, and a rewiring layer on the semiconductor element and the sealing member. The second heat sink member is disposed on the semiconductor device. The lead frame is electrically connected to the semiconductor device through a bonding member. The second sealing member covers a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member. A surface of the second heat sink member faces the semiconductor device. The semiconductor device has a portion protruded from an outline of the second surface sink member. 1. A semiconductor module comprising:a first heat sink member; a semiconductor element,', 'a first sealing member covering the semiconductor element,', 'a first wiring and a second wiring electrically connected to the semiconductor element, and', 'a rewiring layer disposed on the semiconductor element and the sealing member;, 'a semiconductor device including'}a second heat sink member disposed on the semiconductor device;a lead frame electrically connected to the semiconductor device through a bonding member; anda second sealing member covering a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member,wherein the second heat sink member has a first surface and a second surface,wherein the second surface of the second heat sink member faces the semiconductor device,wherein the semiconductor device has a portion protruded from an outline of the second surface of the second heat sink member, andwherein the second wiring has an end extending to the portion of the semiconductor device protruded from the outline of the second surface of ...

THERMALLY CONDUCTIVE SHEET, CURED PRODUCT THEREOF, AND SEMICONDUCTOR DEVICE

A thermally conductive sheet includes a thermosetting resin (A) and an inorganic filler material (B) which is dispersed in the thermosetting resin (A). In the thermally conductive sheet, when a pore diameter distribution is measured through mercury intrusion technique for the inorganic filler material (B) that is included in an incineration residue after a cured product of the thermally conductive sheet is heated at 700° C. for four hours and is incinerated, a pore diameter distribution curve, that is measured through the mercury intrusion technique and is plotted with a pore diameter R as a horizontal axis and a logarithmic derivative of a pore volume (dV/d log R) as a vertical axis, has a peak (P) in the range where the pore diameter R is greater than or equal to 1.0 μm and is less than or equal to 10.0 μm, and the peak (P) is configured of two or more overlapping peaks. 1. A thermally conductive sheet that includes a thermosetting resin and an inorganic filler material which is dispersed in the thermosetting resin ,wherein when a pore diameter distribution is measured through mercury intrusion technique for the inorganic filler material that is included in an incineration residue after a cured product of the thermally conductive sheet is heated at 700° C. for four hours and is incinerated,a pore diameter distribution curve, that is measured through the mercury intrusion technique and is plotted with a pore diameter R as a horizontal axis and a logarithmic derivative of a pore volume (dV/d log R) as a vertical axis,has a peak (P) in the range where the pore diameter R is greater than or equal to 1.0 μm and is less than or equal to 10.0 μm, andthe peak (P) is configured of two or more overlapping peaks.2. The thermally conductive sheet according to claim 1 ,wherein a cumulative pore volume V1 in the range where the pore diameter R is greater than or equal to 1.0 μm and less than or equal to 10.0 μm is greater than or equal to 0.1 mL/g and less than or equal to 2.0 ...

Method of Manufacturing a Semiconductor Device

A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate. 1. A semiconductor package comprising:a package substrate;a semiconductor chip on the package substrate;an interposer substrate on the semiconductor chip, the interposer substrate comprising a first surface facing the semiconductor chip and a trench in the first surface, the trench located to vertically overlap the semiconductor chip; andan insulating filler between the semiconductor chip and the interposer substrate, the insulating filler at least partially filling the trench of the interposer substrate.2. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a first side wall and a second side wall opposite to and facing each other, andwherein the trench extends from the first side wall of the interposer substrate to the second side wall of the interposer substrate.3. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a base insulating layer, and a lower protection insulating layer on a lower surface of the base insulating layer facing the semiconductor chip, andwherein the trench is provided in the lower protection insulating layer.4. The semiconductor package of claim 3 ,wherein the interposer substrate comprises a conductive pattern disposed in the trench, andwherein the conductive pattern comprises an upper surface in contact with the base insulating layer, a lower surface in contact with the lower protection insulating layer and a side wall in contact with the lower protection insulating layer.5. The semiconductor ...

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first die, a second die, a semiconductor frame, and a reinforcement structure. The first die has a first surface and a second surface opposite to the first surface. The first die includes grooves on the first surface. The second die and the semiconductor frame are disposed side by side over the first surface of the first die. The semiconductor frame has at least one notch exposing the grooves of the first die. The reinforcement structure is disposed on the second surface of the first die. The reinforcement structure includes a first portion aligned with the grooves. 1. A package , comprising:a first die having a first surface and a second surface opposite to the first surface, wherein the first die comprises grooves on the first surface;a second die and a semiconductor frame disposed side by side over the first surface of the first die, wherein the semiconductor frame has at least one notch exposing the grooves of the first die; anda reinforcement structure disposed on the second surface of the first die, wherein the reinforcement structure comprises a first portion aligned with the grooves.2. The package of claim 1 , wherein a projection of the grooves along a direction perpendicular to the first surface of the first die is overlapped with the first portion of the reinforcement structure.3. The package of claim 1 , wherein the reinforcement structure further comprises a second portion connected to the first portion claim 1 , wherein the second portion is disposed along at least one edge of the first die.4. The package of claim 3 , wherein the first portion of the reinforcement structure extends along a first direction and the second portion of the reinforcement structure extends along a second direction perpendicular to the first direction.5. The package of claim 3 , wherein the second portion of the reinforcement structure is disposed along four edges of the first die.6. The package of claim 1 , wherein the reinforcement structure is ...

PACKAGE STRUCTURES HAVING UNDERFILLS

A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view. 1. A package structure , comprising:a lower substrate;substrate connection terminals on the lower substrate;a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, respectively, as viewed in a plan view, and covering at least one of the substrate connection terminals; anda second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view.2. The package structure as claimed in claim 1 , wherein each of the first underfills includes:an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering the substrate connection terminals; andan outer portion not overlapping the semiconductor package in the vertical direction.3. The package structure as claimed in claim 2 , wherein the outer portion covers side surfaces of the package substrate and the first encapsulant.4. The package structure as claimed in claim 3 , wherein a height of a portion of the semiconductor package covered by the ...

Exposed die clip bond power package

In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Matrix Lid Heatspreader for Flip Chip Package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids (). 110-. (canceled)11. A semiconductor package , comprising:a substrate having first and second surfaces;a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; anda heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.12. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.13. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.14. The semiconductor package of claim 11 , where the heat spreader lid is formed with a thermally conductive layer of copper claim 11 , nickel or an alloy thereof.15. The semiconductor package of claim 11 , where the exposed heat dissipation surface layer has a thermal contact surface that is at ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. 1. A semiconductor device , comprising:a die pad; a first surface,', 'a second surface opposite to said first surface,', 'a first end face located between said first surface and said second surface in cross-section view,', 'a second end face located between said first surface and said second surface in cross-section view, and also located closer to said die pad than said first end face, and', 'a third surface located between said first surface and said second surface in cross-section view, and also located between said first end face and said second end face in cross-section view;, 'a die-pad-support lead supporting said die pad, said die-pad-support lead includinga semiconductor chip mounted over said die pad, said semiconductor chip including a plurality of bonding pads;a plurality of leads electrically connected with said bonding pads via a plurality of wires, respectively; anda resin-sealing-body sealing said semiconductor chip, said wires and a part of each of said leads,wherein said first end face of said die-pad-support lead is exposed from said resin-sealing-body, andwherein said first surface, said second surface, said second end face and said ...

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another. 1. A wiring substrate comprising:a wiring component adapted to connect a first semiconductor element and a second semiconductor element, wherein the first semiconductor element includes a first electrode terminal and a second electrode terminal, and the second semiconductor element includes a third electrode terminal and a fourth electrode terminal, wherein a first connection terminal exposed on an upper surface of the wiring component and connected to the first electrode terminal of the first semiconductor element,', 'a second connection terminal exposed on the upper surface of the wiring component and connected to the third electrode terminal of the second semiconductor element, and', 'an internal connection terminal formed on a lower surface of the wiring component, and, 'the wiring component includes'}the wiring component electrically connects the first electrode terminal of the first semiconductor element and the third electrode terminal of the second semiconductor element;a third connection terminal connected to the second electrode terminal of the first semiconductor element;a fourth connection terminal connected to the fourth ...

ELECTRONIC COMPONENT DEVICE, METHOD OF MOUNTING ELECTRONIC COMPONENT DEVICE ON CIRCUIT BOARD, AND MOUNTING STRUCTURE OF ELECTRONIC COMPONENT DEVICE ON CIRCUIT BOARD

An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface, at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by joining the terminal electrode to the mount electrode, and a sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted. The sealing resin layer includes a region with a large thickness, and a top surface including an inclination. 1. An electronic component device comprising:a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface;at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by the terminal electrode being joined to the mount electrode; anda sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted; whereinthe sealing resin layer includes an increased thickness region, and a top surface including an inclination.2. The electronic component device according to claim 1 , wherein when viewed in a planar direction:the mount substrate includes a region with a reduced formation density of the outer electrode; andthe region of the sealing resin layer with the increased thickness and the region of the mount substrate with the reduced formation density of the outer electrode overlap each other.3. The electronic component device according to claim 1 , whereina plurality of the outer electrodes are provided;the outer electrodes include a signal outer electrode and a ground outer electrode; andwhen viewed in a planar direction:the mount substrate includes a region with an increased formation density of the ground outer electrode; andthe increased thickness region of the sealing resin layer and the region of the mount ...

Semiconductor Package and Method of Manufacturing a Semiconductor Package

A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths. 116-. (canceled)17. A semiconductor package , comprising:a semiconductor die comprising a semiconductor device, a first contact pad arranged on a first surface of the semiconductor die and a second contact pad arranged on a second surface of the semiconductor die that opposes the first surface, the semiconductor die being embedded in a dielectric layer; andone or more first package contact pads and one or more second package contact pads arranged on a first major surface of the dielectric layer, wherein the dielectric layer has a lateral extent that is greater than the area occupied by the first and second package contact pads, the first contact pad of the semiconductor die being coupled to the one or more first package contact pads and the second contact pad of the semiconductor die being coupled to the one or more second package contact pads,wherein in operation, the semiconductor device causes a current path between the first contact pad and the second contact pad,wherein the one or more first package contact pads and the one or more second package contact pads are arranged on the first major surface of the dielectric layer to ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising: a device top surface;', 'a device bottom surface opposite to the device top surface; and', 'a device side surface extending between the device top surface and the device bottom surface;, 'an electronic device comprising a first region that extends from the device top surface in an upward direction; and', 'a second region coupled to the first region, wherein the second region extends from the first region in a lateral direction; and, 'an interconnect directly attached at the device top surface comprising a first portion of the second region is exposed from a first surface of the encapsulant;', 'a second portion of the second region is exposed from a second surface of the encapsulant; and', 'the encapsulant covers a third portion of the second region., 'an encapsulant that covers the device top surface, the device side surface, and a periphery of the first region, wherein2. The semiconductor device of claim 1 , wherein:the interconnect comprises a severed leadframe lead;the lateral direction is substantially parallel to the device top surface; andthe second portion extends to overlap the device side surface so as to extend outside a perimeter of the electronic device.3. The semiconductor device of ...

Metallization Patterns in Semiconductor Packages and Methods of Forming the Same

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die. 1. A package comprising:an integrated circuit die comprising a die connector;an encapsulant disposed around the integrated circuit die;a polymer material over at least a portion of the encapsulant;an impurity disposed at a top surface of the polymer material, a material of the impurity being different than the polymer material; anda conductive line over the polymer material, the conductive line electrically connecting the die connector to a conductive feature, and a portion of the encapsulant is disposed between the die connector and the conductive feature.2. The package of claim 1 , further comprising a polymer layer disposed between the conductive line and the polymer material claim 1 , the impurity is disposed at an interface between the polymer material and the polymer layer.3. The package of claim 2 , wherein the polymer layer further forms an interface with the encapsulant.4. The package of claim 2 , wherein the polymer layer covers an entire top surface of the encapsulant.5. The package of claim 1 , wherein the impurity is disposed at an interface between the conductive line and the polymer material.6. The package of claim 1 , wherein a top surface of the die connector is disposed below a top surface of the encapsulant claim 1 , the polymer material extending from the top surface of the encapsulant to the top surface of the die connector.7. The package of claim 1 , wherein the impurity comprises silicon claim 1 , aluminum claim 1 , or a combination thereof.8. A package comprising:a semiconductor die;a molding material ...

Heat Dissipation Device, Semiconductor Packaging System and Method of Manufacturing Thereof

A heat dissipation device includes a first part having a first material and a surface portion, and a second part on the surface portion. The second part has a second material and a porosity. 1. A heat dissipation device , comprising:a first part comprising a first material and having a surface portion; anda second part directly coupled to the surface portion and comprising a second material,wherein the second part has a porosity,wherein the first part further comprises a barrier layer and/or an adhesion layer and/or an adhesion promotion layer.2. The heat dissipation device of claim 1 , wherein the porosity of the second part is in a range between 0.1% and 30%.3. The heat dissipation device of claim 1 , wherein the first material comprises aluminum claim 1 , aluminium alloy claim 1 , magnesium claim 1 , and/or magnesium alloy.4. The heat dissipation device of claim 1 , wherein the second material is different from the first material.5. The heat dissipation device of claim 1 , wherein a thermal conductivity of the second material is higher than a thermal conductivity of the first material.6. The heat dissipation device of claim 1 , wherein the second material comprises copper claim 1 , copper alloy claim 1 , silver claim 1 , silver alloy claim 1 , bronze and/or brass.7. The heat dissipation device of claim 1 , wherein the second part is a material layer having thermal properties different from thermal properties of the first part.8. The heat dissipation device of claim 7 , wherein the material layer is a patterned material layer.9. The heat dissipation device of claim 1 , wherein the barrier layer comprises nickel claim 1 , titanium claim 1 , titanium nitride claim 1 , and/or chromium.10. The heat dissipation device of claim 1 , wherein the adhesion promotion layer comprises aluminum claim 1 , titanium claim 1 , nickel claim 1 , gold and/or an alloy of aluminum claim 1 , titanium claim 1 , nickel and/or gold.11. A packaging system claim 1 , comprising:a package ...

Manufacturing method of semiconductor package

There is provided a manufacturing method of a semiconductor package in which plural semiconductor chips different in the thickness are mounted. In the manufacturing method, the back surface of a package board in which the plural semiconductor chips on a wiring base are collectively sealed by a sealant is held by a holding tape and a resin layer is thinned by a shaping abrasive stone. Then, a dividing unit is caused to cut to the middle of the holding tape along planned dividing lines to divide the package board into individual semiconductor packages.

SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS

A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame. 1. A semiconductor package structure , comprising:a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure;a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure;a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner;a molding material surrounding the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material; andan annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die, wherein the annular frame comprises a retracted region at an outer corner of the annular frame.2. The semiconductor package structure according to claim 1 , wherein the annular frame has ...

METHOD AND APPARATUS FOR WAFER LEVEL PACKAGING

Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer. 1. A apparatus for use in wafer package processing , comprising:a substrate;a plurality of die cavities formed through the substrate; anda plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity,wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.2. The substrate of claim 1 , wherein the substrate is a printed circuit board.3. The substrate of claim 1 , wherein the substrate is a glass wafer.4. The substrate of claim 1 , wherein the plurality of conductive through vias are filled with one of copper or solder.5. An electronics package comprising:a substrate consisting of an array of die cavities formed in the substrate, wherein each die cavity is surrounded by one or more rows of through vias having conductive materials disposed therein;a plurality of dies disposed in a cavity in the array of die cavities;an encapsulating material disposed on the top surface of the substrate for ...

PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS

According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step. 112-. (canceled)13. A semiconductor die package , comprising:a lead frame made of a first metal, the lead frame having a first side and a second side;a die pad that is a part of the lead frame;a plurality of leads that are part of the lead frame;a semiconductor die positioned on a first side of the die pad;a plurality of conductive wires that extend from the die to a first side of each respective lead;a molding compound that encapsulates the die, the plurality of conductive wires, and the first side of each respective lead;an electrically conductive coating layer overlying the second side of the lead frame and positioned on the second side of each respective lead, the electrically conductive coating layer being made of a different material than the lead frame;an electrically conductive line that extends from a lead, on a bottom side of the package to an edge of the package, the lead being exclusively on the bottom side of the package and not having any portion thereof on a sidewall of the package; anda portion of molding compound that directly overlays the electrically conductive line.14. The semiconductor die package of wherein a width of the electrically conductive coating layer in a region between the lead and a side of the package is greater than a width of the lead.15. The semiconductor die package of wherein the lead that the electrically conductive line extends from is at least three times thicker than the electrically conductive line.16. The ...

Enhanced Thermal Transfer in a Semiconductor Structure

A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment. 1. A method for fabricating a semiconductor device have enhanced thermal transfer , the method comprising:providing at least one die including a device layer formed on a front side of a semiconductor substrate, the device layer including one or more functional circuit elements formed therein;attaching the die to a support structure such that the front side of the die is disposed on at least a portion of the support structure; andtexturing a back side of the substrate so as to increase a surface area of the back side of the substrate thereby enhancing thermal transfer between the substrate and an external environment.2. The method of claim 1 , wherein the die is attached to the support structure using at least one connection structure coupled between the device layer and the support structure.3. The method of claim 1 , wherein texturing the back side of the substrate comprises at least one of forming periodic structures in or on the back side of the substrate and forming non-periodic structures in or on the back side of the substrate.4. The method of claim 1 , wherein texturing comprises forming a plurality of trenches in the back side of the substrate claim 1 , a portion of the substrate remaining between adjacent trenches forming periodic fingered structures claim 1 , a surface area of the back side of the substrate being controlled as a function of an aspect ratio of the fingered structures.5. The method of ...

MOLDED INTELLIGENT POWER MODULE FOR MOTORS

An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RJC) compared to a conventional IPM. 1. An intelligent power module (IPM) for driving a motor , the IPM comprising:a first, second, third and fourth die supporting elements;a first transistor attached to the first die supporting element;a second transistor attached to the second die supporting element;a third transistor attached to the third die supporting element;a fourth, fifth, and sixth transistors attached to the fourth die supporting element;a connection member;a low voltage integrated circuit (IC) attached to the connection member; the low voltage IC being electrically connected to the first, second and third transistors;a high voltage IC attached to the connection member, the high voltage IC being electrically connected to the fourth, fifth, and sixth transistors;a first plurality of leads;a second plurality of leads;a first dummy bar; anda molding encapsulation enclosing the first, second, third, and fourth die supporting elements, the first, second, third, fourth, fifth, and sixth transistors, the connection member, the low voltage IC, and the high voltage IC ...

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE USING THE SAME

A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads. 1. A printed circuit board (PCB) comprising:a base substrate comprising a top surface comprising an electronic device mounting region;chip connection pads that are provided on the electronic device mounting region;a conductive pattern group that is provided on the top surface of the base substrate and comprises an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; anda solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads.2. The PCB of claim 1 , wherein the solder resist layer comprises:a first solder resist layer that covers a part of the electronic device mounting region on the top surface of the base substrate; anda second solder resist layer that covers at least a part of a region excluding the electronic device mounting region on the top surface of the base substrate.3. The PCB of claim 2 , wherein the second solder resist layer is spaced apart from the first solder resist layer.4. The PCB of claim 2 , wherein the conductive pattern group protrudes from the top surface of the base substrate claim 2 , andthe first solder resist layer covers both a part of a side surface and a ...

SEMICONDUCTOR DEVICE, POWER CONVERTER, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING POWER CONVERTER

There is provided a semiconductor device including an insulating substrate provided with a circuit surface, and an external terminal bonded to the circuit surface. The circuit surface has an upper surface that is in contact with and bonded to a part of a lower surface of the external terminal. In at least a part of a portion where the upper surface of the circuit surface and the lower surface of the external terminal are in contact with each other, a melted portion of the circuit surface and the external terminal is formed. A gap between the upper surface of the circuit surface and the lower surface of the external terminal has a size of 20 μm or less. The circuit surface and the external terminal are each made of copper or copper alloy. 1. A semiconductor device comprising:a metal plate;a semiconductor element disposed on an upper surface of the metal plate via a bonding material; andan external terminal bonded to the upper surface of the metal plate,whereinthe upper surface of the metal plate and a lower surface of the external terminal are in contact with each other via a conductive material,in at least a part of a portion where the upper surface of the metal plate and the lower surface of the external terminal are in contact with each other, a melted portion of the metal plate, the external terminal, and the conductive material is formed, andthe metal plate and the external terminal are each made of copper or copper alloy.2. The semiconductor device according to claim 1 , further comprising a sealing material formed covering the metal plate claim 1 , the semiconductor element claim 1 , and a part of the external terminal.3. The semiconductor device according to claim 1 , wherein the conductive material is formed beyond a range where the metal plate and the external terminal overlap with each other in plan view.4. The semiconductor device according to claim 1 , wherein a plurality of the melted portions is formed.5. A power converter comprising: a metal plate;', ...

PACKAGE SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Provided are a package substrate and a method of fabricating a semiconductor package. The package substrate includes: a base substrate having a plurality of packaging unit regions arranged along rows and columns on one surface thereof; and a sink portion penetrating at least a portion of the base substrate from the one surface, in which the packaging unit regions may be disposed adjacent to a first side of the one surface and the sink portion may be disposed adjacent to a second side of the one surface. 1. A package substrate comprising:a base substrate having a plurality of packaging unit regions arranged along rows and columns on one surface thereof; anda sink portion oriented toward the other surface of the base substrate opposed to the one surface,wherein the packaging unit regions are disposed adjacent to a first side of the one surface, the sink portion is disposed adjacent to a second side of the one surface, and the second side is opposed to the first side and is parallel to a direction of the rows.2. The package substrate according to claim 1 , wherein a distance from the packaging unit regions of a first row to the first side of the one surface is shorter than a distance from the packaging unit regions of a last row to the second side of the one surface.3. The package substrate according to claim 1 , wherein a total number of the columns is greater than a total number of the rows.4. The package substrate according to claim 1 , wherein the sink portion penetrates the base substrate and connects the one surface and the other surface.5. The package substrate according to claim 1 , wherein the sink portion is recessed from the one surface without penetrating the base substrate.6. The package substrate according to claim 1 , wherein the sink portion comprises a plurality of sink portions claim 1 , and the sink portions are offset-arranged in a direction of the rows with respect to the packaging unit regions of a last row.7. The package substrate according to ...

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability. 1. A package structure , comprising:an electronic element having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;an encapsulant encapsulating the electronic element and having a first surface exposing the active surface of the electronic element and a second surface opposite to the first surface;a plurality of conductive elements penetrating the first and second surfaces of the encapsulant, wherein the conductive elements are metal balls; anda redistribution layer formed on the first surface of the encapsulant and the active surface of the electronic element and electrically connected to the electrode pads of the electronic element and the conductive elements.2. The structure of claim 1 , wherein the metal balls are solder balls.3. The structure of claim 1 , wherein the first surface of the encapsulant is flush with the active surface of the electronic element.4. The structure of claim 1 , wherein the redistribution layer has: a dielectric layer ...

Microelectronic packages and methods for the fabrication thereof

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads, a passivation layer disposed on the connection member, and an under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. 1. A semiconductor device comprising:a semiconductor chip having an active surface having connection pads disposed thereon;an encapsulant encapsulating at least portions of the semiconductor chip;a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads;a passivation layer disposed on the connection member; andan under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member,wherein the UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.2. The semiconductor device of claim 1 , further comprising a connection terminal connected to the UBM layer claim 1 ,wherein the connection terminal fills the recess portion.3. The semiconductor device of claim 1 , wherein the UBM pad includes additional one or more recess portions.4. The semiconductor device of ...

Package Lead Design with Grooves for Improved Dambar Separation

A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad. 1. A lead frame , comprising:a die pad;a first lead extending away from the die pad;a peripheral structure mechanically connected to the first lead and the die pad; anda first groove in an outer surface of the first lead, the first groove extending longitudinally along the first lead away from the die pad.2. The lead frame of claim 1 , wherein the outer surface of the first lead comprises first and second surfaces that are generally planar and extend longitudinally along the first lead claim 1 , wherein the first and second surfaces are angled relative to one another claim 1 , and wherein the first groove forms a transition between the first and second surfaces.3. The lead frame of claim 2 , wherein the outer surface of the first lead further comprises a third surface that is generally planar and extends longitudinally along the first lead between the first and second ends claim 2 , wherein the second and third surfaces are angled relative to one another claim 2 , wherein the lead frame further comprises a second groove in an outer surface of the first lead claim 2 , the second groove extending longitudinally along the first lead away from the die pad claim 2 , and wherein the second groove forms a transition between the second and third surfaces.4. The lead frame of claim 3 , wherein the outer surface of the first lead further comprises a fourth surface that is generally planar and extends longitudinally along the first lead between the first and second ends claim 3 , wherein the third and fourth surfaces are angled relative to one another claim 3 , wherein the fourth and first surfaces are angled relative to one another claim 3 , wherein the lead frame further ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

In one example, a semiconductor device comprises a substrate and an electronic device on a top side of the substrate, a lead frame on the top side of the substrate over the electronic device, wherein the lead frame comprises a connection bar and a lead, a component mounted to the connection bar and the lead on a top side of the lead frame, and an encapsulant on the top side of the substrate, wherein the encapsulant contacts a side of the electronic device and a side of the component. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate and an electronic device on a top side of the substrate;a lead frame on the top side of the substrate over the electronic device, wherein the lead frame comprises a connection bar and a lead;a component mounted to the connection bar and the lead on a top side of the lead frame; andan encapsulant on the top side of the substrate, wherein the encapsulant contacts a side of the electronic device and a side of the component.2. The semiconductor device of claim 1 , wherein the lead frame comprises a paddle claim 1 , and a downset from the paddle to the connection bar claim 1 , wherein the component is mounted to the connection bar and the lead at a level lower than a top side of the paddle.3. The semiconductor device of claim 2 , further comprising an additional component on the top side of the substrate under the paddle.4. The semiconductor device of claim 3 , wherein the additional component is thermally coupled with the paddle.5. The semiconductor device of claim 1 , wherein the electronic device is below the component.6. The semiconductor device of claim 1 , wherein a top side of the encapsulant is coplanar with a top side of the lead frame.7. The semiconductor device of claim 1 , wherein the connection bar and the lead have a gap therebetween claim 1 , and the component is mounted to span the gap.8. The semiconductor device of claim 1 , wherein the substrate comprises a pre- ...

METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar. 1. A method of forming packaged semiconductor devices , comprising:providing a first conductive frame having joined conductive portions;attaching semiconductor components to the first conductive frame;providing a second conductive frame comprising interconnected conductive clips;attaching the second conductive frame to the first conductive frame to provide a first sub-assembly, wherein the interconnected conductive clips are coupled to the first conductive frame;encapsulating the first sub-assembly with an encapsulant to provide an encapsulated sub-assembly; andseparating the encapsulated sub-assembly to provide the packaged semiconductor devices, wherein the step of separating disconnects the interconnected conductive clips from the second conductive frame.2. The method of claim 1 , further comprising:removing the joined conductive portions of the first conductive frame to form conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly; and 'the step of separating comprises providing each of the packaged semiconductor devices having portions ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture;an electronic device having an interconnect electrically coupled to the first conductor; andan encapsulant on a top side of the substrate contacting a side of the electronic device.2. The semiconductor device of claim 1 , wherein the substrate comprises a third conductor on the top side of the dielectric claim 1 , and a fourth conductor on the bottom side of the dielectric claim 1 , wherein the dielectric has an additional aperture claim 1 , and the third conductor comprises a partial via contacting a pad of the fourth conductor through the additional aperture.3. The semiconductor device of claim 2 , further comprising a trace on the dielectric between the partial via of the first conductor and the partial via of the third conductor.4. The semiconductor device of claim 2 , wherein an end of the partial vial of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.5. The semiconductor device of claim 2 , wherein:the first conductor comprises a first trace on the top side of the dielectric and ...

MICROELECTRONIC ASSEMBLIES

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly. 1. A method of forming a microelectronic assembly , comprising:bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate;applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate;processing the microelectronic substrate; andsingulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.2. The method of forming a microelectronic assembly of claim 1 , further comprising planarizing the first surface of the microelectronic substrate and/or the surface of the carrier in preparation for the direct bonding technique.3. The method of forming a microelectronic assembly of claim 1 , wherein bonding the microelectronic substrate to the surface of the carrier comprises facing the plurality of conductive interconnections away from the surface of the ...

Hybrid package

A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Semiconductor Package

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material. 1. A semiconductor package , comprising:a semiconductor chip including a body having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a passivation film disposed on the active surface of the body and covering at least a portion of the connection pad, a first connection bump disposed on the passivation film and electrically connected to the connection pad, and a first coating layer disposed on the passivation film and covering at least a portion of a side surface of the first connection bump;an encapsulant covering at least a portion of the semiconductor chip; anda connection structure including an insulating layer disposed on the first coating layer of the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via passing through the insulating layer and electrically connecting the first connection bump to the redistribution layer,wherein the first connection bump includes a low melting point metal,the redistribution layer and the connection via include a conductive material, andthe low melting point metal has a melting point lower than a melting point of the conductive material.2. The semiconductor package of claim 1 , wherein the low melting point metal includes a solder claim 1 , andthe conductive material includes copper (Cu).3. The semiconductor package of claim 1 , wherein a ...

METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. 1. (canceled)2. A semiconductor chip package , comprising:a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;a contact pad on the front surface of the semiconductor chip;a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;a dielectric layer on the front surface of the mold material and on the front surface of the semiconductor chip, the dielectric layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;an electrical conductor in the dielectric layer, the electrical conductor in contact with the contact pad, and the electrical conductor having a width; anda conductive contact area in the dielectric layer, the conductive contact area in contact with the electrical conductor, the electrical contact area having a width greater than a width of the electrical conductor, and the conductive contact area having a surface co-planar with the dielectric layer.3. The semiconductor chip package of claim 2 , wherein the dielectric layer comprises an additive.4. The semiconductor chip package of claim 2 , wherein the mold material layer ...

INTEGRATED POWER MODULE AND MANUFACTURING METHOD THEREOF

An integrated power module comprising a power board including at least one power switching device, a driver board including at least one driver for driving a gate of the at least one power switching device, and an interconnection extending across the power board and the driver board mechanically connecting the power board and the driver board together. Included are a lead frame to which the power board and the driver board are mounted, and a package encapsulating the power board and the driver board mounted on the lead frame. Also disclosed is a method for manufacturing the integrated power module. 1. An integrated power module comprising:a power board including at least one power switching device;a driver board including at least one driver for driving a gate of the at least one power switching device;an interconnection extending across the power board and the driver board mechanically connecting the power board and the driver board together;a lead frame to which the power board and the driver board are mounted; anda package encapsulating the power board and the driver board mounted on the lead frame.2. The integrated power module as claimed in claim 1 , whereinthe power board includes a substrate that is a thermally conducting and electrically insulating material, and includes directly bonded copper,the driver board includes a printed circuit board, andthe interconnection comprises at least one of the directly bonded copper and the printed circuit board.3. The integrated power module as claimed in claim 2 , whereinthe interconnection comprises the printed circuit board, andthe printed circuit board includes an aperture in which the substrate is located.4. The integrated power module as claimed in claim 3 , wherein the directly bonded copper covers and extends beyond the aperture.5. The integrated power module as claimed in claim 2 , wherein the directly bonded copper extends from the substrate reaches claim 2 , and is connected to the printed circuit board claim 2 ...

Semiconductor Package and Method for Fabricating a Semiconductor Package

A semiconductor package includes a semiconductor die, an encapsulation encapsulating the semiconductor die, the encapsulation having a first side and an opposing second side, a plurality of contact pads for electrically contacting the semiconductor die, the contact pads being arranged on the first side of the encapsulation, and a plurality of inspection holes arranged in communication with the contact pads and extending from the first side to the second side, such that solder joints on the first side of the encapsulation are optically inspectable using the inspection holes viewed from the second side of the encapsulation. 1. A semiconductor package , comprising:a semiconductor die;an encapsulation encapsulating the semiconductor die, the encapsulation comprising a first side and an opposing second side;a plurality of contact pads for electrically contacting the semiconductor die, the contact pads being arranged on the first side of the encapsulation; anda plurality of inspection holes arranged in communication with the contact pads and extending from the first side to the second side, such that solder joints on the first side of the encapsulation are optically inspectable using the inspection holes viewed from the second side of the encapsulation.2. The semiconductor package of claim 1 , further comprising:a plating layer arranged in the inspection holes.3. The semiconductor package of claim 2 , wherein the plating layer in each inspection hole is contiguous with the respective contact pad.4. The semiconductor package of claim 2 , wherein the encapsulation comprises a molded body.5. The semiconductor package of claim 4 , wherein the molded body comprises a laser-activatable polymer composition claim 4 , and wherein the plating layer is arranged on laser-activated regions on the molded body.6. The semiconductor package of claim 4 , wherein the encapsulation further comprises a laminate claim 4 , wherein the contact pads are arranged on the laminate claim 4 , and ...

Semiconductor Device Package Comprising Side Walls Connected with Contact Pads of a Semiconductor Die

A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad. 1. A semiconductor device package , comprising:a printed circuit board comprising a first central area, a second lateral area, and a third lateral area;a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, the semiconductor die being disposed in the first central area of the printed circuit board;a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board;a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board;wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad of the semiconductor die.2. The semiconductor device package according to claim 1 , wherein one of the first metallic side wall and the second metallic side wall is electrically connected to the first contact pad of the semiconductor die claim 1 , and ...

PACKAGE INCLUDING A SUBSTRATE WITH HIGH RESOLUTION RECTANGULAR CROSS-SECTION INTERCONNECTS

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold. 1. A package comprising:an integrated device; and at least one dielectric layer; and', 'a plurality of interconnects located in the at least one dielectric layer, wherein at least one interconnect has a cross-sectional thickness that varies along a length of the interconnect by no more than 3 micrometers., 'a substrate coupled to the integrated device, the substrate comprising2. The package of claim 1 , wherein the at least one interconnect has a surface roughness that is in a range of approximately 1-3 micrometers.3. The package of claim 1 , wherein the at least one interconnect has a side cross-section having at least one corner with a corner radius that is in a range of approximately 0.5-2 micrometers.4. The package of claim 1 , wherein a side cross-section of the at least one interconnect has an effective shape that is one or more of a rectangle claim 1 , square claim 1 , or oval.5. The package of claim 1 ,wherein the plurality of interconnects includes a thickness, a pitch, a spacing and a width, andwherein one or more of the thickness, pitch, spacing, and/or width is 30 micrometers or less.6. The package of claim 1 , wherein the at least one interconnect has a height to width aspect ratio of approximately 1:2 or less.7. The package of claim 1 , wherein the at least one dielectric layer comprises a ceramic claim 1 , a low temperature co-fired ceramic (LTCC) claim 1 , high temperature co-fired ceramic (HTCC) claim 1 , aluminum nitride (AlN) claim 1 , zinc oxide (ZnO) claim ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device A disclosed includes: a semiconductor element having an element obverse face and element reverse face that face oppositely in a thickness direction z, with an obverse-face electrode (first electrode ) and a reverse-face electrode respectively formed on the element obverse face and the element reverse face; a conductive member A opposing the element reverse face and conductively bonded to the reverse-face electrode ; a conductive member B spaced apart from the conductive member A and electrically connected to the obverse-face electrode ; and a lead member having a lead obverse face facing in the same direction as the element obverse face and connecting the obverse-face electrode and the conductive member B. The lead member , bonded to the obverse-face electrode via a lead bonding layer , includes a protrusion protruding in the thickness direction z from the lead obverse face . The protrusion overlaps with the obverse-face electrode as viewed in the thickness direction z. This configuration suppresses deformation of the connecting member to be pressed during sintering treatment. 1. A semiconductor device comprising:a semiconductor element having an element obverse face and an element reverse face that face toward mutually opposite sides in a first direction, the semiconductor element being formed with an obverse-face electrode and a reverse-face electrode on the element obverse face and the element reverse face, respectively;a first conductor opposing the element reverse face and conductively bonded to the reverse-face electrode;a second conductor spaced apart from the first conductor and electrically connected to the obverse-face electrode; anda connecting member having a connecting member obverse face facing in a same direction as the element obverse face, the connecting member connecting the obverse-face electrode and the second conductor to each other,wherein the connecting member includes a first protrusion protruding in the first direction ...

SEMICONDUCTOR PACKAGE

A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion. 1. A semiconductor package comprising:a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer,wherein each of the redistribution patterns comprises a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion,the via portion, the pad portion, and the line portion are connected to each other to form a single object,a level of a bottom surface of the pad portion is lower than a level of a bottom surface of the line portion, anda width of the line portion has a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.2. The semiconductor package of claim 1 , wherein a difference in the level between the bottom surface of the pad portion and the bottom surface of the line portion ranges from 0.2 μm to 0.5 μm.3. The semiconductor package of claim 1 , wherein a diameter of the pad portion has a largest value at a level between a top surface of the pad portion and the bottom surface of the pad portion.4. The semiconductor package of claim 1 , wherein a difference between the largest value of the width of the line portion and a width of the top surface of the line portion is greater than 0 nm and is smaller than 300 nm.5. ...

Selective Plating of Semiconductor Package Leads

A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating. 1. A method of forming a semiconductor device , comprising:providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body;coating outer portions of the leads that are exposed from the mold compound body with a metal coating; and exposed from the mold compound body; and', 'substantially devoid of the metal coating., 'after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is2. The method of claim 1 , wherein the planar metallic heat sink interface surface and the electrically conductive leads are each formed from a first metal claim 1 , and wherein the metal coating comprises a second metal having higher solderability than the first metal.3. The method of claim 2 , wherein the planar metallic heat sink interface surface and the electrically conductive leads are each formed from copper claim 2 , and wherein the metal ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a first structure including a plurality of stacked first semiconductor chips and electrically connected to a first redistribution layer through connection vias having different heights; and a second structure including a second semiconductor chip electrically connected to a second redistribution layer. The first and second redistribution layers are electrically connected to each other through an electrical connection member formed on the second structure. 1. A semiconductor package comprising:a plurality of first semiconductor chips each having a first active surface on which a first connection pad is disposed and a first inactive surface, opposing the first active surface, the first semiconductor chips being stacked such that the first connection pads are respectively exposed;a first encapsulant covering at least a portion of each of the plurality of first semiconductor chips;a first connection member disposed in a position lower than a position of the plurality of first semiconductor chips and in a lower portion of the first encapsulant, and including one or more first redistribution layers, and a plurality of connection vias electrically connecting the first connection pads of each of the first semiconductor chips to the one or more first redistribution layers, each of the connection vias penetrating into the first encapsulant, and heights of the connection vias being different from each other;a second semiconductor chip disposed in a position lower than a position of the first connection member, and having a second active surface on which a second connection pad is disposed, and a second inactive surface opposing the second active surface;a second encapsulant disposed in a position lower than a position of the first connection member, and covering at least a portion of the second semiconductor chip;a second connection member disposed in a position lower than positions of the second semiconductor chip and in a lower portion of ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, an encapsulation layer encapsulating the electronic component, and a passivation layer stacking with the encapsulation layer. The passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface. The first sidewall inclines with respect to the second surface, and a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer. 1. A semiconductor device package , comprising:an electronic component;an encapsulation layer encapsulating the electronic component; anda passivation layer stacking with the encapsulation layer, wherein the passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface, the first sidewall inclining with respect to the second surface, wherein a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer.2. The semiconductor device package of claim 1 , wherein the second surface is smaller than the first surface.3. The semiconductor device package of claim 1 , wherein the encapsulation layer has a third surface facing the passivation layer claim 1 , a fourth surface opposite to the third surface claim 1 , and a second sidewall connecting the third surface and the fourth surface.4. The semiconductor device package of claim 3 , wherein the encapsulation layer hangs over the passivation layer.5. The semiconductor device package of claim 3 , wherein a surface roughness of the second sidewall of the encapsulation layer is larger than a surface roughness of the first sidewall of the passivation layer.6. The semiconductor device package of claim 3 , wherein the third surface is larger than the fourth surface.7. The semiconductor ...