MEMRISTIVE ARRAY WITH PARALLEL RESET CONTROL DEVICES

In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

MEMRISTIVE CONTROL CIRCUITS WITH CURRENT CONTROL COMPONENTS

In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

Disposable blunt anastomat of cutting of foreskin

The utility model discloses a disposable blunt anastomat of cutting of foreskin, this anastomat cover establish at the penis outsidely, including parts such as inner rings, sword ring, power ring, cover on the endocyclic horn mouth of anastomat after package skin external turns over, the foreskin inner panel exposes outside, through the blunt foreskin of cutting of sword ring extrusion that has a truncated edge that can reciprocate, accomplish preputial passivity pincers surely, identical operation, the postoperative generally need not be sewed up, it can to paint medical adhesive. Circular cutting, the anastomosis of real meaning can have been realized effectively to this anastomat, and simple, the easy operation of operation technique reduces art person and bleeds, alleviates the misery, and the healing is fast, guarantees the circular cutting quality.

Method for extracting bacteria plasmid DNA

The invention relates to molecular biology, which particularly relates to an extracting method of bacterial plasmid DNA. The extracting method comprises the following steps: jolting and overnight culturing microbial thallus in fluid medium under the temperature which is 25 DEG C-30 DEG C, adding buffer solution in bacterial liquid which is overnight cultured, centrifuging to gather and wash to get cracking thallus, separating and purifying plasmid DNA, directly using plasmid DNA which is got in various molecular biology tests such as restriction enzyme, PCR and the like. The extracting method has the advantages of simple and convenient operation and high quality, and meanwhile, the invention is suitable for the extraction of Gram-negative bacteria and Gram-negative bacteria plasmid DNA, therefore, the extracting method has wide adaptability.

Multiply-Acumulate Circuits

In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both. 1. A multiply-accumulate circuit comprising:a set of row driver circuits, wherein each row driver receives an input vector bit of an input vector;a set of memristor circuits linked to the set of row driver circuits to form a set of rows, each row having a row driver which activates the row and a corresponding memristor circuit, wherein each memristor stores a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;a sense amplifier linked to the set of memristor circuits to apply an output voltage based on a current output from a memristor of the set of memristor circuits, the current output representative of the weight value bit stored by the memristor; andcounter circuitry to store a counter value and to adjust the counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier, or both.2. The circuit of claim 1 , wherein a particular row driver and a corresponding memristor are active at a particular time; andwherein the counter circuitry adjusts the counter value by incrementing, decrementing, or taking no ...

Neuron circuits

Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor.

Finite state machines

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Finite state machines

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Comparator associated with dictionary entry

Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

TERNARY CONTENT ADDRESSABLE MEMORY

An exemplary ternary content addressable memory is disclosed. The bit cell of the memory includes first and second memristors. The first terminal of the first memristor is connected to the first terminal of the second memristor via a node. The second terminal of the first memristor is switchably connected to a first data line. The second terminal of the second memristor is switchably connected to a second data line. The bit cell also includes a match line transistor coupled between a first rail and a match line. The gate of the match line transistor is coupled to the node. It is possible to provide better flexibility and speed in operation. COPYRIGHT KIPO 2018 ...

Stubble removing mechanism and rice stubble cutting no-tillage arid hole direct seeding machine

The invention discloses a stubble removing mechanism and a rice stubble cutting no-tillage arid hole direct seeding machine. The stubble removing mechanism comprises a stubble removing support and a V-shaped plate, wherein the V-shaped plate is arranged on the stubble removing support. After the V-shaped plate is installed on the machine frame, the sharp corner of the V-shaped plate faces the advancing direction, foreign matter such as straw is moved to two sides by means of the outward driving force generated when the V-shaped plate moves, so that a flat and clean ditching working surface is formed, and a good foundation is laid for subsequent work. The invention further discloses the rice stubble cutting no-tillage arid hole direct seeding machine. The rice stubble cutting no-tillage arid hole direct seeding machine can achieve rice stubble cutting, rice stubble removing, ground profiling, seeding ditch digging, precision hole seeding and earthing pressing at the same time, and no-tillage ...

Multiply-accumulate with voltage tracking modulation

An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.

TCAM-driven RRAM

According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

MEMRISTIVE ARRAYS WITH A WAVEFORM GENERATION DEVICE

In one example in accordance with the present disclosure a memristive array is described. The memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

Epoxy resin composition and processing equipment thereof

The invention discloses an epoxy resin composition which comprises epoxy resin, polyurethane, modified nano silicon dioxide filler and a curing agent. According to the epoxy resin composition provided by the invention, the epoxy resin composition with good dispersibility and better surface roughness is obtained through setting of the composition; the invention further provides processing equipment of the epoxy resin composition, through the arrangement of the processing equipment, when the epoxy resin composition is produced and manufactured, materials adhered to the feeding opening can be cleaned into the reaction kettle, and deviation of material adding is prevented.

MAF-based evaluation method and device

The invention discloses an evaluation method and device based on MAF. The evaluation method comprises a data preprocessing step, a comparison step, an assignment step, a reference value determination step, a normalization step and an MAFScore judgment step. According to the invention, a special logic algorithm is established through analysis of detection results of 20 genes of an endometrial cancer control group, an ovarian cancer control group and a non-cancer control group, and is used for early diagnosis of the endometrial cancer and the ovarian cancer. The overall performance, sensitivity and specificity of the detection system all exceed 90%.

MEMRISTOR BASED CONTENT ADDRESSABLE MEMORY

An exemplary memristor based content addressable memory. A bit cell of a memory may include a memristor and a switching transistor connected in series between a first data line and a second data line. Also, the bit cell may also include a match line transistor connected between a match line and a rail. The gate of the match line transistor may be connected to the common node of the memristor and the switching transistor. The size of the switching transistor can be set so that a channel resistance value at an on state is between a resistance value associated with the low resistance state of the memristor and a resistance value associated with the high resistance state of the memristor. Power consumption can be reduced. COPYRIGHT KIPO 2018 ...

FINITE STATE MACHINES

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Resistance trigger type vacuum arc ion source device

The invention discloses a resistance trigger type vacuum arc ion source device. The resistance trigger type vacuum arc ion source device comprises a positive electrode (1), a negative electrode (2), a trigger electrode (3), a negative electrode-trigger electrode insulator (4), a trigger resistor (5) and a negative electrode fixing conductive connector (6) connected to the lower end of the negative electrode (2), the positive electrode (1) is composed of a hollow cylindrical positive electrode supporting body (11) and an annular positive electrode (12) connected to the upper end of the positive electrode supporting body (11), and the trigger resistor (5), the trigger electrode (3), the negative electrode-trigger electrode insulator (4) and the negative electrode (2) are arranged in the positive electrode supporting body (11) from exterior to interior in sequence. The trigger resistor is arranged in the vacuum arc ion source device, the structure is compact, the size is small, the installing ...

Adjusting target values of resistive memory devices

Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

Arrays of bit-cells

An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.

Method for reducing organic pollution in environment by using black carbon

The invention provides a method for reducing organic pollution in the environment by using black carbon. The black carbon mainly comprises biomass black carbon, fly ash black carbon, and automobile tail gas black carbon; in the method, the black carbon is directly added to adsorb organic pollutants in soil, sediments and water bodies, the black carbon is added to the waste water to be treated in a weight ratio of the black carbon to the waste water to be treated of 1:100-10,000 and uniformly stirred so as to remove the organic pollutants in the waste water, and the black carbon is added to the soil or sediments to be treated in a weight ratio of the black carbon to the soil or sediments to be treated of 1:20-200 and uniformly stirred so as to remove the organic pollutants in the soil or sediments; and for the preparation of the black carbon, the various black carbon raw materials undergo dioic acid treatment to remove salt and oxides so as to obtain the black carbon. The method has the ...

DBD (Dielectric Barrier Discharge) low temperature plasma generating device and polymer film surface treatment method

The invention relates to the technical field of material surface treatment and particularly discloses a DBD (Dielectric Barrier Discharge) low temperature plasma generating device and a polymer film surface treatment method. The DBD low temperature plasma generating device comprises a power source and a DBD plasma reactor; at least three layers of dielectric slabs are arranged in a reaction chamber of the DBD plasma reactor; a gap is formed between every two adjacent layers of dielectric slabs. The polymer film surface treatment method comprises performing treatment through the DBD low temperature plasma generating device. Discharge can be formed between every two layers of dielectric slabs to form uniform good low temperature plasma, the polymer film treatment can be performed on the bilateral sides of every layer of dielectric slab which is located in the middle, the treatment of one layer of polymer film can be performed through the dielectric slab which cover two electrodes, and accordingly ...

MULTIPLY-ACCUMULATE CIRCUIT

In some embodiments, a method may be performed by a multiply-accumulate circuit. As part of the method, a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to an input vector bit. The corresponding memristor stores a weight value bit of a weight to which the input vector is to be applied for a multiply-accumulate operation. The method further includes a sense amplifier that generates an output voltage based on a current outputted from the corresponding memristor and a counter circuit which adjusts a counter value indicating the total of a multiply-accumulate operation based on a low value line, an output voltage generated from the sense amplifier, or a combination of the low value line and the output voltage. It is possible to reduce power costs. COPYRIGHT KIPO 2018 (602) Driving a row value to a row value line based on an ...

Memristive arrays with offset elements

In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.

Method for extracting bacteria plasmid DNA

The invention relates to molecular biology, which particularly relates to an extracting method of bacterial plasmid DNA. The extracting method comprises the following steps: jolting and overnight culturing microbial thallus in fluid medium under the temperature which is 25 DEG C-30 DEG C, adding buffer solution in bacterial liquid which is overnight cultured, centrifuging to gather and wash to getcracking thallus, separating and purifying plasmid DNA, directly using plasmid DNA which is got in various molecular biology tests such as restriction enzyme, PCR and the like. The extracting methodhas the advantages of simple and convenient operation and high quality, and meanwhile, the invention is suitable for the extraction of Gram-negative bacteria and Gram-negative bacteria plasmid DNA, therefore, the extracting method has wide adaptability.

CONTENT ADDRESSABLE MEMORY WITH BANK

In one aspect, provided is a technique for providing a bank-type content addressable memory (CAM) with a counter. A dictionary word can be divided into a plurality of banks. The counter may be associated with each of the banks. The counter may count the number of mismatching of the segment of an aligned input word with the bank. A scheduler may schedule a comparison of the bank having higher mismatching probability with a bank having lower mismatching probability. The mismatching probability can be based on a counter. The bank-type content addressable memory includes a dictionary entry and a scheduler. COPYRIGHT KIPO 2018 (120) Dictionary entry (132a) Bank 0 (132b) Bank 1 (132c) Bank 2 (134a) B0 match counter (134b) B1 match counter (134c) B2 match counter (140) Bit cell (142,AA) Input word segment (144) Scheduler (BB) Input word ...

Photocatalysis method for removing PAHs in soil

Ternary content addressable memories

An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.

SVG negative damping effect suppression device and method based on current feedback

An SVG negative damping effect suppression method based on current feedback comprises the following steps that SVG high-frequency impedance is modeled, and a single-input single-output SVG high-frequency impedance model ZSVG (s) is constructed; designing a current feedback control structure and a control function expression according to the SVG controller structure; and designing control parameters according to the control structure. The SVG current feedback additional damping control with robustness is designed, the periodic negative damping effect of the SVG is eliminated, a clear parameter design method is given, and the phase margin of interaction between the SVG and a new energy power station at high frequency is enhanced. Simulation results show that the SVG negative damping suppression method can significantly improve the operation stability of the new energy power system.

Method of operating and apparatus of memristor arrays with diagonal lines interconnect between memristor cells

A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.

PERFORMING COMPLEX MULTIPLY-ACCUMULATE OPERATIONS

In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

Method for checking voltages

The invention discloses a method for checking voltages and relates to the technical field of power system control. The method comprises the following steps: S1, measuring the real-time voltage, current, active power and reactive power of each bus node in a power system and configuring an automatic gain control (AGC) command; S2, according to the real-time data and network parameters of the power system measured in the S1, calculating the voltage amplitude of each selected bus node at an existing moment; and S3, comparing the set voltage amplitude of each selected bus node with the voltage amplitude of each selected bus node calculated in the S2, determining that the AGC command meets voltage requirements of the power system if the absolute value of the difference value is less than a set voltage offset index, and determining that the AGC command does not meet the voltage requirements of the power system if the absolute value of the difference value is more than or equal to the set voltage ...

Content addressable memory with banks

In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.

Memristive arrays with a waveform generation device

A memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

Preparation method of hericium erinaceus active polysaccharide

The invention discloses a preparation method of hericium erinaceus active polysaccharide, and belongs to the technical field of hericium erinaceus processing. The invention provides a preparation method of hericium erinaceus active polysaccharide, which comprises the following steps: crushing, soaking and grinding dried hericium erinaceus sporocarp to obtain slurry, then carrying out microwave-ultrasonic wave wall breaking, then fermenting with a compound probiotic agent, centrifuging to obtain a hericium erinaceus active polysaccharide crude extract, and carrying out alcohol precipitation to obtain the hericium erinaceus active polysaccharide. According to the preparation method of the hericium erinaceus active polysaccharide, the extraction rate of the hericium erinaceus polysaccharide can be increased to 30% or above, and the method is simple, easy to implement and suitable for large-scale industrial production.

Multi-chamber integrated foot bath device for preventing and treating diabetic foot

The invention discloses a multi-chamber integrated foot bath device for preventing and treating diabetic foot, and relates to the technical field of foot bath equipment. The multi-chamber integrated foot bath device is characterized by comprising a shell, a foot bath box body and a main controller, the foot bath box body is arranged in the shell, a lifting assembly is arranged on the inner wall of the shell, and the lifting assembly is electrically connected with the main controller; two foot bath openings are formed in the top end of the shell, the shell is fixedly connected with an elastic air bag and a bearing foot plate through a telescopic air cylinder, the elastic air bag is located above the bearing foot plate, and the telescopic air cylinder is electrically connected with the main controller; the interior of the foot bath box body is sequentially divided into a water bath chamber, a cleaning chamber and a medicated bath chamber from bottom to top through partition plates; and the ...

ARRAYS OF BIT-CELLS

An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node. 1. A device comprising: a first switch element;', 'a second switch element coupled to the first switch element at a node; and', 'a memory element coupled to the first switch element and the second switch element at the node; and, 'a plurality of bit-cells coupled as an array, wherein a bit-cell includeswherein the plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.2. The device of claim 1 , wherein the memory element is polarized claim 1 , and wherein the array includes a plurality of memory elements that are to alternate in polarity between bit-cells.3. The device of claim 1 , wherein the bit-cell further includes a first voltage rail node coupled to the first switch element claim 1 , and a second voltage rail node coupled to the second switch element; and wherein a set current path and a reset current path of the bit-cell includes first and second voltage rail nodes of different bit-cells.4. The device of claim 1 , wherein the plurality of bit-cells include a first type of bit-cell including a first polarity memory element claim 1 , and a second type of bit-cell including a second polarity memory element;wherein the first type of bit-cell includes a first voltage rail node coupled to the first type of bit-cell's first switch element, and a second voltage rail node coupled to the first type of bit-cell's second switch element;wherein the second type of bit-cell includes a third voltage rail node coupled to the second type of bit-cell's first switch element, and a fourth voltage rail node coupled to the second type of ...

Coffee bean hot air drying equipment and drying method

The invention discloses coffee bean hot air drying equipment and a drying method, and relates to the technical field of coffee bean processing. The coffee bean hot air drying equipment comprises a drying box, a feeding assembly, a turnover discharging assembly and a hot air assembly, breathable drying plates are fixedly installed on the inner walls of the two sides of the drying box, the feeding assembly is arranged on the drying box and used for protecting the breathable drying plates, and the turnover discharging assembly is arranged on the drying box and used for protecting the breathable drying plates. The overturning discharging assembly comprises a gear motor and a scraping plate, the gear motor can drive the scraping plate to rotate in the drying box, and the scraping plate is used for discharging coffee beans on the breathable drying plate. According to the hot air drying equipment and method for the coffee beans, the drying uniformity of the coffee beans can be improved, the time ...

Substrate integrated waveguide coupling feed structure of spherical pin grid array

The invention provides a substrate integrated waveguide coupling feed structure of a spherical pin grid array, which is characterized in that a through groove is formed in a surface metal layer of a substrate integrated waveguide, and the spherical pin grid array is arranged at the top of the substrate integrated waveguide corresponding to the through groove; the top of the spherical pin grid array is correspondingly provided with a radar chip. According to the invention, the substrate integrated waveguide is used as a transmission line, and compared with a microstrip line, the line width advantage is better, and the antenna is more suitable in a thick-medium low-loss scene; compared with a microstrip line, the isolation degree is higher, and the isolation requirement of the chip BGABall outgoing line position is ensured; and meanwhile, the arrangement processing of the shielding cover is more flexible.

Inplanatable analysis method for association relationship between characteristic quantity and transient power angle stability

The invention discloses an interpretability analysis method for a characteristic quantity and transient power angle stability association relationship, and belongs to the field of alternating-current and direct-current hybrid systems. Selecting the new energy characteristic quantity and the direct current characteristic quantity as the input of a transient power angle stability evaluation model, and evaluating the transient power angle stability; the characteristic quantity interpretable analysis method based on the SHAP globally and locally clarifies the incidence relation between the characteristic quantity and the transient power angle stability.

Hardware accelerators for calculating node values of neural networks

Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

Single profiling type rice and wheat dual-purpose precision hill seeder

The invention discloses a single profiling type rice and wheat dual-purpose precision hill seeder. The single profiling type rice and wheat dual-purpose precision hill seeder comprises a profiling mechanism, a ditching mechanism, a hill seeding type seeding mechanism, a soil covering and suppressing mechanism and a power system which provides power for the hill seeding type seeding mechanism; the profiling mechanism comprises a main body frame and a connecting frame; the main body frame is a parallelogram frame structure; connecting positions are hinged; one end of the connecting frame is connected with the main body frame; the other end of the connecting frame is connected with the hill seeding type seeding mechanism; the ditching mechanism, the hill seeding type seeding mechanism and the soil covering and the compressing mechanism are sequentially connected. The single profiling type rice and wheat dual-purpose precision hill seeder has the advantages of achieving synchronous soil crushing ...

Combined portable magnetic substance detector and use method thereof

The invention relates to a combined portable magnetic substance detector and a use method thereof. The combined portable magnetic substance detector comprises a magnetic substance content detector and a handheld spectrometer, the content of magnetic substances and the content of non-magnetic substances in a sample as well as element components in an original sample, the magnetic substances and the non-magnetic substances can be rapidly detected; the contents of the magnetic substances and the non-magnetic substances obtained by the magnetic substance content detector and the elemental composition results of the original sample, the magnetic substances and the non-magnetic substances obtained by the handheld spectrometer are combined and then calculated to obtain recovery rate data of various elements in the magnetic substances and the non-magnetic substances under different equivalent magnetic induction intensities; the device is reasonable and compact in structural design and convenient ...

Memristive bit cell with switch regulating components

In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

Memristor Spiking Architecture

A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

Method and device for manufacturing metal hydride electrode and using method of device

The invention relates to the technical field of electrode manufacturing, and particularly discloses a method and device for manufacturing a metal hydride electrode and a using method of the device. The method for manufacturing the metal hydride electrode comprises the steps that the metal hydride electrode is manufactured through metal hydride powder hot press molding, and compression molding is carried out on metal hydride powder with the high pressure of 0.5 GPa to 5 GPa; the high pressure is kept, the molded electrode is heated to 300 DEG C to 900 DEG C, the high pressure is kept for more than 0.5 min within the temperature range, internal stress is eliminated, and the hydrogen storage electrode meeting shape, size and strength needs is manufactured. The electrode with more even components can be obtained, internal defects, such as stress, caused by molding in the prior art can be overcome, the strength of the manufactured electrode is high, electrode manufacturing time is short, and ...

Connecting device for seed box of seed-metering device

The invention discloses a connecting device for a seed box of a seed-metering device. The connecting device comprises a cylinder and at least two seed guide plates, wherein the seed guide plates are arranged on the inner wall of the cylinder in an up and down manner, two adjacent seed guide plates are opposite, and the upper seed guide plate inclines downwards toward the lower opposite seed guide plate. According to the connecting device, a plurality of seed guide plates are arranged in the cylinder in a staggered manner so that seeds flow in a 'Z' shape, cannot directly reach a seed supplementing chamber due to the effect of the seed guide plates in the flowing process, are layered through the effect of the seed guide plates for a plurality of times, and reach the seed supplementing chamber in a layering manner so as to achieve the layering effect.

Series feed directional diagram forming patch antenna

The invention discloses a series feed directional diagram forming patch antenna which is compact, low in cost, high in gain and capable of achieving any wave beam shape, and the purpose of miniaturization of the forming antenna is achieved. The antenna comprises a dielectric substrate, a feeder line, a plurality of radiation patches and a metal grounding plate. The dielectric substrate comprises a top surface and a bottom surface which are oppositely arranged; the feeder line and the radiation patch are attached to the top surface of the dielectric substrate; the metal grounding plate is attached to the bottom surface of the dielectric substrate. The plurality of radiation patches are distributed along the feeder line, and the radiation patches are provided with groove structures I; a second groove structure is arranged at a set position on the feeder line. According to the invention, accurate control of unit amplitude and phase is realized through special design of the series-fed antenna ...

Seed sowing and metering device

The invention provides a seed sowing and metering device, and relates to the technical field of sowing devices. The seed metering wheel is mounted on the seeding surface of the box body and is used for discharging seeds out of the box body; the seed metering wheel is in interference fit with the transmission shaft; the seed guide working curved surface is mounted on the seeding surface of the box body, and the mounting height of the seed guide working curved surface is lower than that of the seed metering wheel; the splitter plate is mounted at the tail end of the seed guide working curved surface, so that the performance disadvantages of high operation energy consumption, high cost, low operation benefit, influence on final operation energy efficiency and insufficient control accuracy on unit seeding rate and seeding position due to the fact that most of current seeding equipment is suitable for ditching and drilling are solved; by optimizing the structure and the operation mechanism of ...

Method for association of appeal events, acquisition and summarization of data and quality inspection of user appeal

The embodiment of the invention discloses an appeal event association method and device, an appeal event data acquisition method and device, a user appeal quality inspection method and device, an appeal event summarization method and device, a computer readable storage medium and electronic equipment. The method comprises the following steps that: a fourth server side obtains a quality inspection request aiming at the appeal of a user to be subjected to quality inspection, wherein the appeal of the user to be subjected to quality inspection comprises at least one appeal event related to user consultation; according to the quality inspection configuration information, quality inspection is carried out on the data of the appeal event associated with the appeal of the user to be subjected to quality inspection, quality inspection result information is obtained, the quality inspection configuration information comprises quality inspection rules associated with different quality inspection points ...

Multiply-accumulate circuits

In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

Data quality scoring method and device, storage medium and electronic device

The invention discloses a data quality scoring method and device, a storage medium and an electronic device, and relates to the technical field of smart homes.The data quality scoring method comprises the steps that a text list associated with a data warehouse is obtained, the weight relation between different texts in the text list is determined, and the text list comprises multiple target texts; establishing an association relationship between the text list and a data table stored in a data warehouse according to a preset corresponding relationship between the data table and the text; and under the condition that a health degree score corresponding to the data table is calculated by using a preset target evaluation process, constructing a target graph network based on the text list, the weight relationship, the data table and the health degree score corresponding to the data table, so as to perform data quality scoring on the to-be-evaluated text selected by the target object through ...

Coordination control method

The invention discloses a coordination control method and relates to the technical field of control of power systems. The coordination control method comprises the following steps: S1. measuring real-time voltage, current, active power and reactive power of all bus bar nodes, and setting an AGC (automatic gain control) command; S2. performing voltage check according to the AGC command, and outputting voltage predicted value and check result of the selected bus bar node; S3. outputting the AGC command if the AGC command meets the voltage requirement, otherwise, implementing the step S4; S4. performing AVC (automatic voltage control) according to the voltage predicted value of the selected bus bar node, and calculating voltage adjusting value of the selected bus bar node after performing the AVC; S5. performing power check according to the voltage adjusting value of the selected bus bar node, and outputting power predicted value and the check result of a call wire; and S6. outputting anAVC ...

Grain seeder with safety protection device

The invention discloses a grain seeder with a safety production device, which comprises a seeder shell and a cell wheel and a seeding shaft arranged on the seeder shell, wherein a transmission hole is formed in the cell wheel. The grain seeder also comprises a safety protection device arranged in the transmission hole of the cell wheel and in transmission connection with the seeding shaft, wherein the safety protection device comprises a cylindrical body, a spring and a power pull block; the body is in transmission connection with the seeding shaft; a blind hole is formed in the body; the spring and the power pull block are sequentially arranged in the blind hole, and the power pull block protrudes out of the blind hole; an overload protection block protrudes on the hole wall of the transmission hole; the overload protection block is provided with a power transmission surface, an inner ring arc surface and an inner ring transition curved surface in sequential connection; the power pull ...

Method and device of moving plate detecting platform and detecting system

The invention provides a method and a device of moving a plate detecting platform and a detecting system, belonging to the electronic field. Thee method of moving the plate detecting platform comprises the following steps: receiving the input of the user or detecting the operation of the user; generating the pulse of corresponding frequency according to the received input or the detected operationof the user; and controlling the plate detecting platform to move correspondingly by using the generated pulse. In the steps of receiving the input of the user or detecting the operation of the userand generating the pulse of corresponding frequency according to the received input or the detected operation of the user, the rotating speed of a servo motor is controlled by the frequency of the generated pulse, and accordingly the moving speed of the plate detecting platform is controlled. The invention realizes the method of moving the plate detecting platform according to the requirements ofthe ...

Double-shovel type adjustable punching and fertilizing mixing device

The invention provides a double-shovel type adjustable punching, fertilizing and mixing device, and relates to the technical field of agricultural machinery automation. The punching and fertilizing mixing mechanism comprises a punching shovel which is fixedly connected to the punching and fertilizing mixing mechanism for punching; the fertilization mechanism is driven by the movement mechanism to complete the fertilization action; when the movement mechanism moves in the forward direction, the punching shovel, the fertilizing mechanism and the mixing shovel are sequentially driven to act, and punching, fertilizing and mixing actions are sequentially executed; the supporting and adjusting mechanism is used for adjusting the distance between the punching, fertilizing and mixing mechanism and the ground, and the technical problems that the equipment has functional limitation, needs human intervention for regulation and control, is insufficient in control flexibility, cannot be subjected to ...

Power checking method

The invention discloses a power checking method, which relates to the technical field of power system control. The method comprises the following steps of: 1, measuring the real-time voltage, current, active power and reactive power of each bus node of a power system, and setting an automatic voltage control (AVC) instruction; 2, calculating the active power of each connecting line of the power system according to real-time data measured by the step 1 and network parameters of the power system; and 3, comparing the set active power of each connecting line with the active power, calculated by the step 2, of each connecting line, determining that the AVC instruction meets the power requirements of the power system if an absolute value of a difference value between the set active power of any connecting line and the active power calculated by the step 2 is less than a set power offset index, and determining that the AVC instruction does not meet the power requirements of the power system if ...

Ternary content addressable memories having a bit cell with memristors and serially connected match-line transistors

An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

Redundant column or row in resistive random access memory

Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Content addressable memories

An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.

Composite polymethacrylimide foam wave absorption material

The invention discloses a composite polymethacrylimide foam wave absorption material which is prepared by the following steps: (1) performing surface treatment on a wave absorber, namely uniformly mixing the wave absorber and a surfactant with a solvent, ultrasonically processing, drying to remove the solvent, and breaking and grinding to obtain a wave absorber subjected to surface treatment; (2) preparing expandable polymethacrylimide resin particles; (3) preparing the composite polymethacrylimide foam wave absorption material. The material is good in wave absorption performance, heat resistance and mechanical property, can be used for avoiding the defects of complex process, material waste and the like caused by a process that the material is machined to obtain a complex shape, can absorb electromagnetic waves to prevent electromagnetic wave interference, can be applied to the aspects of medical appliances, household appliances, electronic products, high-rise buildings, communication ...

Method of the degradation of polycyclic aromatic hydrocarbon compounds in soil combining TiO2 and ultraviolet light

Dual-power output clutch cover assembly

The invention discloses a dual-power output clutch cover assembly and belongs to the manufacturing technology field of an automobile clutch. The purpose of the invention is to disclose a dual-power output clutch cover assembly to transmit engine torque during synchronous rotation of the cover assembly and a flywheel. The dual-power output clutch cover assembly is provided with a diaphragm spring rivet and a torsion damper, and the diaphragm spring and the cover assembly both adjacent to the rivet and the diaphragm spring and the torsion damper both adjacent to the rivet are respectively provided with a support ring. During synchronous rotation of the cover assembly and the flywheel, the engine torque is synchronously output by an added torsion vibration reduction system, so that the engine torsion isn't solely output by a driven plate assembly. The cover assembly realizes the dual-power output of the clutch, so that the power performance of the complete vehicle is greatly prompted. The ...

Method of the degradation of polycyclic aromatic hydrocarbon compounds in soil combining TiO2 and ultraviolet light

Subsynchronous oscillation suppression method of photovoltaic grid-connected system based on data driving

A photovoltaic grid-connected system subsynchronous oscillation suppression method based on data driving comprises the following steps: identifying a dynamic model of a photovoltaic grid-connected system in a rolling manner based on data driving, and selecting a control signal through small signal analysis; designing a photovoltaic grid-connected system controller based on model predictive control; the operation of the controller is realized through the digital-analog hybrid simulation system, and the subsynchronous oscillation of the photovoltaic grid-connected system is suppressed. According to the invention, system identification of the photovoltaic grid-connected system is realized; according to the invention, the selection of the control parameters of the photovoltaic grid-connected system is researched, and the strongly correlated control parameters of the photovoltaic grid-connected system can be found out; through model prediction control, the oscillation problem existing in the ...

Method for discriminating excitation of isolated net

The invention discloses a method for discriminating the excitation of an isolated net, which mainly relates to the field of a power system. The method disclosed by the invention comprises the following steps: measuring the real-time frequency f of an isolated net system; computing the criteria capacity SN of the isolated net system according to the system parameters and real-time frequency f of the isolated net system; if the rated capacity SN of the generator of the isolated net system is larger than the criteria capacity SN, judging that the isolated net system does not generate the excitation and if not, determining that the isolated net system generates the excitation; and outputting the judgment result. The discriminating method disclosed by the invention only utilizes the inherent electric parameters of the isolated net system and the real-time frequency value of the isolated net system, can rapidly prejudge whether the isolated net system generates the excitation or not and caneffectively ...

Stable and efficient polymerized high-cost-performance polymethacrylamide foam and preparation method thereof

The invention discloses stable and efficient polymerized polymethacrylamide foam with high cost performance and a preparation method of the stable and efficient polymerized polymethacrylamide foam, and belongs to the technical field of foam materials. Comprising the following raw material components: 20-200 parts of acrylonitrile, 10-100 parts of methacrylic acid, 5-25 parts of acrylic acid, 1-6 parts of a stabilizer, 0.1-6 parts of a third monomer, 0.04-5 parts of an initiator, 1-20 parts of a cross-linking agent, 0.5-25 parts of a foaming agent, 0.5-15 parts of a heat-resistant agent, 0.3-5 parts of a release agent and 0.1-2 parts of a secondary additive. The low-cost and high-performance small-aperture polymethacrylimide foam is prepared by using a stable, uniform and efficient polymerization technology, and the small-aperture foam product can completely avoid the problems of implosion and non-uniform reaction products in the preparation process, so that the foam is uniform in aperture ...

Ion gate controller for ion mobility spectrometer and control method thereof

The invention relates to the technical field of ion gate control for an ion mobility spectrometer, specifically an ion gate controller for the ion mobility spectrometer and a control method thereof. The ion gate controller comprises a high voltage power supply, a divider resistance circuit for supplying power to an electrode ring, and two adjustable power supplies. One end of the divider resistance circuit is connected with the high voltage power supply, and the other end of the divider resistance circuit is grounded. The divider resistance circuit comprises a plurality of divider resistors, which are in series connection with each other. The output ends of the two adjustable power supplies are each connected with one ion gate electrode. The electric potential of two electrodes of the ion gate can be freely adjusted, symmetrically or asymmetrically controlling over the ion gate can be achieved, and an excellent control effect is provided. Because the signal control over the whole circuit ...

Single machine alone net self-excitation judging method

The invention discloses a single machine alone net self-excitation judging method, which mainly relates to the field of power systems. The method comprises the following steps of: measuring the real-time frequency of a single machine alone net system; calculating the equivalent ground capacitive reactance of the single machine alone net system, and ultimate direct axis reactance and ultimate quadrature axis reactance of a generator according to system parameters and real-time frequency of the single machine alone net system; when excitation regulation is not performed, judging the single machine alone net system may not produce self-excitation if the equivalent ground capacitive reactance is greater than the ultimate straight axis reactance,, otherwise judging the single machine alone netsystem may produce the self-excitation; and when the excitation regulation is performed, judging the single machine alone net system may not produce the self-excitation if the equivalent ground capacitive ...

Hole digging and fertilizing device based on ball spline

The invention discloses a punching and fertilizing device based on a ball spline, and relates to the technical field of agricultural punching and fertilizing. The fertilizer amount regulator is positioned in the fertilizer box and is used for quantitatively controlling the conveying amount of the fertilizer in the fertilizer box; the ball spline shaft is connected with the fertilizer amount regulator; the ball spline sleeve is combined with the ball spline shaft through a ball, and the ball spline shaft is controlled by the ball spline sleeve to rotate and descend; the motor is rotationally connected with the ball spline housing and is used for driving the ball spline housing to rotate; the drill bit adjusting device is in threaded connection with the ball spline shaft; the drill bit is located below the drill bit adjusting device, and the punching radius of the drill bit is adjusted through the drill bit adjusting device. The technical effect of improving controllability and adjustability ...

Novel electric power system wide area prediction damping control method based on data driving

A novel electric power system wide-area prediction damping control method based on data driving comprises the following steps that in consideration that electric power system sampling measurement data is in a discrete form and comprises control input of different stable controllers, a wide-area monitoring system collects measurement data from a controlled novel electric power system, and the measurement data are transmitted to a control system; constructing a past state quantity measurement matrix and a current state measurement matrix control measurement matrix pi, and obtaining a discrete time state equation of the novel power system through the constructed matrix; according to a discrete time system state equation obtained through measurement data identification, carrying out continuous conversion on the discrete time system state equation to obtain a system matrix of a continuous system, and further selecting an installation position and a control signal of a controller through modal ...

Redundant column or row in resistive random access memory

Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

TERNARY CONTENT ADDRESSABLE MEMORIES HAVING A BIT CELL WITH MEMRISTORS AND SERIALLY CONNECTED MATCH-LINE TRANSISTORS

An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor. 1. A ternary content addressable memory , comprising: a first memristor that has a first terminal that is connected to a first data line and a second terminal that is connected to a first switching transistor that is to selectively connect the first memristor to a second data line;', 'a second memristor that has a first terminal that is connected to a third data line and a second terminal that is connected to a second switching transistor that is to selectively connect the second memristor to a fourth data line;', 'a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line,, 'a bit cell that includeswherein a gate of the first match-line transistor is connected to the second terminal of the first memristor, anda gate of the second match-line transistor is connected to the second terminal of the second memristor,wherein the first switching transistor is sized such that its channel resistance when on is between a resistance associated with a low resistance state of the first memristor and a resistance associated with a high ...

NEURON CIRCUITS

Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor. 1. A neuron circuit , comprising:a first current mirror to source a first current through a memristor;a second current mirror to sink a second current through the memristor; andthe memristor to generate a voltage output for the neuron circuit as a function of the sourced first current and the sunk second current through the memristor.2. The neuron circuit of claim 1 , wherein the memristor is to generate a voltage output substantially similar to a sigmoid function.3. The neuron circuit of claim 1 , wherein:the first current mirror is to generate the first current based on a first input current provided by a first dot product engine; andthe second current mirror is to generate the second input current based on a second input current provided by a second dot product engine.4. The neuron circuit of claim 3 , comprising:a third current mirror between the first current mirror and the first dot product engine, the third current mirror to generate an intermediate input current from the first input current provided by the first dot product engine;wherein the first current mirror is to generate the first input current based on the intermediate input current.5. The neuron circuit of claim 1 , wherein the memristor is to provide the generated voltage output to a dot product engine.6. The neuron circuit of claim 1 , wherein the generated voltage output is a non-linear voltage output.7. The neuron circuit of claim 1 , wherein the memristor includes a tantalum oxide switching material ...

Multiply-Accumulate Circuits

In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both. 1. A multiply-accumulate circuit comprising:a set of row driver circuits, wherein each row driver receives an input vector bit of an input vector;a set of memristor circuits linked to the set of row driver circuits, wherein each memristor stores a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;a sense amplifier linked to the set of memristor circuits to apply an output voltage based on a current output from a memristor of the set of memristor circuits, the current output representative of the weight value bit stored by the memristor; andcounter circuitry to store a counter value and to adjust the counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier, or both.2. The circuit of claim 1 , wherein a particular row driver and a corresponding memristor are active at a particular time; andwherein the counter circuitry adjusts the counter value by incrementing, decrementing, or taking no action based on the row value output from the particular row driver and the output voltage applied by the sense ...

MULTIPLY-ACCUMULATE WITH VOLTAGE TRACKING MODULATION

An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network. 1. A device , comprising:multiply-accumulate circuitry that is to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals; andvoltage-tracking modulator circuitry that is to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal.2. The device of claim 1 , comparing the accumulation voltage to a modulation voltage and outputting the output signal as a result of the comparison, and', 'increasing the modulation voltage when the output signal is at a first binary level and decreasing the modulation voltage when the output signal is at a second binary level., 'wherein the voltage-tracking modulator circuitry is to generate the output signal by3. The device of claim 1 , a capacitor that holds a modulation voltage;', 'a differential amplifier to which the accumulation voltage and the modulation voltage are input and from which the output signal is output; and', 'charge injection circuitry that adds charge to the capacitor in response to the output signal being at a first binary level and removes charge from the capacitor in response to the output signal being at a second binary level., 'wherein the voltage-tracking modulator circuitry includes4. The device of claim 3 ,wherein the charge injection ...

HARDWARE ACCELERATORS FOR CALCULATING NODE VALUES OF NEURAL NETWORKS

Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current. 1. A hardware accelerator , comprising: the memory cells are programmed according to a weight matrix;', 'each row line of the plurality of row lines is to receive an input voltage according to an input vector of node values; and', 'each column line of the plurality of column lines is to deliver an output current representing a dot-product current of the input vector and a column line; and, 'a crossbar array programmed to calculate node values of a neural network, the crossbar array comprising a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, whereina current comparator to compare each output current to a threshold current according to an update rule to generate a new input vector of new node values.2. The hardware accelerator of claim 1 , wherein:a new node value corresponding to a particular output current is set to a first value if the particular output current is greater than or equal to the threshold current; andthe new node value corresponding to the particular output current is set to a second value if the particular output current is less than the threshold current.3. The hardware ...

COMPARATOR ASSOCIATED WITH DICTIONARY ENTRY

Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete. 1. A circuit comprising:a dictionary entry storing a dictionary word;a register storing an input word; anda comparator associated with the dictionary entry to compare the dictionary word and the input word, based on a bit by bit comparison, the comparator to output a signal, the signal indicating if the dictionary word is less than the input word, equal to the input word, greater than the input word, or indeterminate, wherein indeterminate means the comparison is not yet complete.2. The circuit of wherein the comparator is further to:iteratively compare each bit of the dictionary word with a corresponding bit of the input word to determine if the dictionary word is smaller, equal to, or greater than the input word, the comparison proceeding from a most significant bit to a least significant bit of the dictionary word.3. The circuit of further comprising:setting the output signal based on the comparison.4. The circuit of wherein setting the output signal further comprises:setting the output signal to its current value when the output signal is not currently set to indeterminate.5. The circuit of wherein setting the output signal further comprises:setting the output signal to indicate the dictionary word and the input word are equal when the comparison indicates the bits being compared are equal and the current bit being compared is the least significant bit of the dictionary word.6. The circuit of wherein setting the output signal further ...

Memristive bit cell with switch regulating components

In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

Adjusting target values of resistive memory devices

Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

Two-step code generator for phase coded frequency modulated continuous wave (fmcw) multi input multi output (mimo) radar

A two-step optimization method for scheduling transmissions in an MIMO (multi-input multi-output) includes determining a first phase code for each transmission according to a first equation, placing each first phase code in a set of first phase codes, and determining a cost function of the set of first phase codes, determining a second phase code for each transmission according to a second equation, determining an updated cost function corresponding to replacing each of the first phase codes with a corresponding one of the second phase codes, and determining which set of phase codes has a smaller cost function.

SPATIAL TOPIC REPRESENTATION OF MESSAGES

A method, computer program product and computer system to generate a spatial visualization of topics contained in messages data is provided. A processor retrieves message data associated with a user. A processor determines one or more topics represented by the message data. A processor generates a spatial visualization of one or more user interface elements, where the spatial visualization includes a size and a location for the one or more user interface elements. A processor displays one or more user interface elements corresponding to the one or more topics. 17-. (canceled)8. A computer program product comprising: program instructions to retrieve message data associated with a user;', 'program instructions to determine one or more topics represented by the message data;', 'program instructions to generate a spatial visualization of one or more user interface elements, wherein the spatial visualization includes a size and a location for the one or more user interface elements; and', 'program instructions to display one or more user interface elements corresponding to the one or more topics., 'one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising9. The computer program product of claim 8 , the program instructions further comprising:program instructions to determine one or more popularity scores corresponding to the one or more topics.10. The computer program product of claim 9 , wherein program instructions to display the one or more user interface elements further comprises:program instructions to determine a respective size for display of the one or more user interface elements based, at least in part, on the one or more popularity scores.11. The computer program product of claim 8 , the program instructions further comprising:program instructions to determine one or more relevance scores corresponding to the one or more topics.12. The computer program ...

Spatial topic representation of messages

A method, computer program product and computer system to generate a spatial visualization of topics contained in messages data is provided. A processor retrieves message data associated with a user. A processor determines one or more topics represented by the message data. A processor generates a spatial visualization of one or more user interface elements, where the spatial visualization includes a size and a location for the one or more user interface elements. A processor displays one or more user interface elements corresponding to the one or more topics.

Charge metering circuit for memristor

A charge metering circuit for a memristor includes a switch connected between a stimulus voltage and the memristor. The switch is pulsed on to apply the stimulus voltage to the memristor. The circuit includes a current mirror connected between a low-rail voltage and the memristor and having a primary leg and a secondary leg, and a capacitor connected between a capacitor voltage and the secondary leg. The primary leg pulls a voltage at the memristor to a virtual ground voltage upon pulsing on of the switch, and the secondary leg pulls a current through the capacitor from the capacitor voltage.

Radar system with modified orthogonal linear antenna subarrays

This document describes techniques and systems of a radar system with modified orthogonal linear antenna subarrays and an angle-finding module. The described radar system includes a first one-dimensional (1D) (e.g., linear) subarray; a second 1D subarray positioned orthogonal to the first 1D subarray; and a two-dimensional (2D) subarray. Using electromagnetic energy received by the first 1D subarray and the second 2D subarray, azimuth angles and elevation angles associated with one or more objects can be determined. The radar system associates, using electromagnetic energy received by the 2D subarray, pairs of an azimuth angle and an elevation angle to the respective objects. In this way, the described systems and techniques can reduce the number of antenna elements while maintaining the angular resolution of a rectangular 2D array with similar aperture sizing.

Resolving Return Signals Among Pixels in Frequency-Modulated Continuous-Wave (FMCW) Lidar Systems

This document describes techniques and systems to resolve return signals among pixels in lidar systems. The described lidar system transmits signals with different waveforms for consecutive pixels to associate return signals with their corresponding pixels. During a detection window, the lidar system receives a return signal and compares it in the frequency domain to at least two template signals. The template signals include the waveform of an initial pixel and a subsequent pixel of two consecutive pixels, respectively. The lidar system then determines, based on the comparison to the template signals, the pixel to which the return signal corresponds and determines a characteristic of an object that reflected the return signal. In this way, the lidar system can confidently resolve detections to reduce the time between pixels. This improvement allows the described lidar system to operate at faster scanning speeds and realize a faster reaction time for automotive applications.

Radar System with Modified Orthogonal Linear Antenna Subarrays

This document describes techniques and systems of a radar system with modified orthogonal linear antenna subarrays and an angle-finding module. The described radar system includes a first one-dimensional (1D) (e.g., linear) subarray; a second 1D subarray positioned orthogonal to the first 1D subarray; and a two-dimensional (2D) subarray. Using electromagnetic energy received by the first 1D subarray and the second 2D subarray, azimuth angles and elevation angles associated with one or more objects can be determined. The radar system associates, using electromagnetic energy received by the 2D subarray, pairs of an azimuth angle and an elevation angle to the respective objects. In this way, the described systems and techniques can reduce the number of antenna elements while maintaining the angular resolution of a rectangular 2D array with similar aperture sizing.

Performing complex multiply-accumulate operations

In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

Asymmetrical frequency-division multiplexing for radar systems

Techniques and systems for asymmetrical frequency-division multiplexing, FDM, for radar systems (100). In some examples, a radar system (100) includes multiple transmitters (112), multiple receivers (114), multiple polyphase shifters (116), and a processor (118). The transmitters can transmit electromagnetic, EM, signals in an FDM scheme. The receivers can receive EM signals reflected by one or more objects (110) that include multiple channels. The polyphase shifters can introduce at least four potential phase shifts. The processor can control the polyphase shifters to introduce phase shifts asymmetrically spaced in a frequency spectrum. The processor can determine, using residue estimation and subtraction, potential detections of the objects. In this way, the described asymmetrical FDM for radar systems can support many simultaneous MIMO channels, increase the dynamic range of the radar system, resolve Doppler ambiguities, and provide an efficient processing scheme.

P-direction adjusting structure and dome camera

The present application discloses a P-direction adjustable structure and a hemispherical camera. Wherein, the P-direction adjustable structure is applied to a hemispherical camera and includes: an upper cover component, a pin, a base, and a wire hidden case; the base is rotatably connected to the wire hidden case ; the upper cover component is installed on the base; the upper cover component is provided with a raised part, which can drive the pin to switch between a releasing position and a locking position; wherein, when the pin is switched to the locking position, the rotational degree of freedom of the base and the wire hidden case is locked; when the pin is switched to the releasing position, the locking is released. The P-direction adjustable structure of the present application has a simple structure and is easy to operate. The tightening operation in the P-direction is very simple, as long as the upper cover is normally shut and fastened, without a redundant operation.

Two-step code generator for phase coded frequency modulated continuous wave (fmcw) multi input multi output (mimo) radar

A two-step optimization method for scheduling transmissions in an MIMO (multi-input multi-output) includes determining a first phase code for each transmission according to a first equation, placing each first phase code in a set of first phase codes, and determining a cost function of the set of first phase codes, determining a second phase code for each transmission according to a second equation, determining an updated cost function corresponding to replacing each of the first phase codes with a corresponding one of the second phase codes, and determining which set of phase codes has a smaller cost function.

Asymmetrical Frequency-Division Multiplexing for Radar Systems

This document describes techniques and systems for asymmetrical frequency-division multiplexing (FDM) for radar systems. In some examples, a radar system includes multiple transmitters, multiple receivers, multiple polyphase shifters, and a processor. The transmitters can transmit electromagnetic (EM) signals in an FDM scheme. The receivers can receive EM signals reflected by one or more objects that include multiple channels. The polyphase shifters can introduce at least four potential phase shifts. The processor can control the polyphase shifters to introduce phase shifts asymmetrically spaced in a frequency spectrum. The processor can determine, using residue estimation and subtraction, potential detections of the objects. In this way, the described asymmetrical FDM for radar systems can support many simultaneous MIMO channels, increase the dynamic range of the radar system, resolve Doppler ambiguities, and provide an efficient processing scheme.

[UNK]

P-direction adjusting structure and dome camera

Memristive array with parallel reset control devices

In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

Two-step code generator for phase coded frequency modulated continuous wave (fmcw) multi input multi output (mimo) radar

Structure of reinforced mobile jack

De-aliased imaging for a synthetic aperture radar

This document describes techniques for enabling de-aliased imaging for a synthetic aperture radar. Radar signals processed by a synthetic aperture radar (SAR) system may include false detections in the form of aliasing induced by grating lobes. The techniques described herein can reduce the adverse effects of grating lobes by obtaining an initial SAR image using a backprojection algorithm. Aliasing effects (e.g., false detections) in this initial image may be common due to the limitations of an SAR system moving at non-uniform speeds. A refined image is produced from the initial image by applying a de-aliasing filter to the initial image. The refined image may have reduced or eliminated false detections that attribute to aliasing effects, resulting in a better representation of the environment of the vehicle.

一种氢气管路

本实用新型提供一种氢气管路，氢气管路包括多根直管道和多根弯曲管道，弯曲管道包括第一部分和第二部分，每根弯曲管道的第一部分和第二部分均与直管道连接，每根弯曲管道的第一部分和第二部分呈一角度，每根弯曲管道的第一部分和第二部分相对于彼此在该弯曲管道的第一部分和第二部分所确定的平面内转动，以使管路在X方向、Y方向和Z方向中的任一方向上延伸，X方向、Y方向和Z方向相互垂直。本实用新型能解决现有氢系统70MPa管路由于尺寸偏差导致报废率高的问题，在实际安装时可以根据实际情况在一定范围内对进行管路进行细微调整，从而适应误差，降低管路报废率。

Content addressable memory with banks background

In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.

Content addressable memory

De-Aliased Imaging for a Synthetic Aperture Radar

This document describes techniques for enabling de-aliased imaging for a synthetic aperture radar. Radar signals processed by a synthetic aperture radar (SAR) system may include false detections in the form of aliasing induced by grating lobes. The techniques described herein can reduce the adverse effects of grating lobes by obtaining an initial SAR image using a back-projection algorithm. Aliasing effects (e.g., false detections) in this initial image may be common due to the limitations of an SAR system moving at non-uniform speeds. A refined image is produced from the initial image by applying a de-aliasing filter to the initial image. The refined image may have reduced or eliminated false detections that attribute to aliasing effects, resulting in a better representation of the environment of the vehicle.

Resolving return signals among pixels in frequency-modulated continuous-wave (FMCW) lidar systems

This document describes techniques and systems to resolve return signals among pixels in lidar systems. The described lidar system transmits signals with different waveforms for consecutive pixels to associate return signals with their corresponding pixels. During a detection window, the lidar system receives a return signal and compares it in the frequency domain to at least two template signals. The template signals include the waveform of an initial pixel and a subsequent pixel of two consecutive pixels, respectively. The lidar system then determines, based on the comparison to the template signals, the pixel to which the return signal corresponds and determines a characteristic of an object that reflected the return signal. In this way, the lidar system can confidently resolve detections to reduce the time between pixels. This improvement allows the described lidar system to operate at faster scanning speeds and realize a faster reaction time for automotive applications.

Summary generation based on comparison objects

Summary generation based on comparison objects can include receiving text descriptions of a target object and at least one comparison object. Semantic vectors from the text descriptions can be obtained, using a deep learning based semantic extraction model. The semantic vectors can be input to a generator model trained using an adversarial machine learning technique, the generator model outputting a text summary of the target object describing only unique characteristics of the target object different from characteristics of the at least one comparison object and excluding the characteristics of the at least one comparison object.

Resolving return signals among pixels in frequency-modulated continuous-wave (fmcw) lidar systems

Resolving return signals among pixels in frequency-modulated continuous-wave (fmcw) lidar systems

A lidar system comprises a transmitter that is configured to: transmit, for a first pixel of three consecutive pixels, a first transmit signal, the first transmit signal having a first modulation, the first modulation including a first phase modulation, a first frequency modulation, a first amplitude modulation, or a combination thereof; transmit, for a second pixel of the three consecutive pixels, a second transmit signal, the second transmit signal having a second modulation, the second modulation being different from the first modulation, the second modulation including a second phase modulation, a second frequency modulation, a second amplitude modulation, or a combination thereof; and transmit, for a third pixel of the three consecutive pixels, a third transmit signal, the third transmit signal having a third modulation, the third modulation being different from the second modulation, the third modulation including a third phase modulation, a third frequency modulation, a third amplitude modulation, or a combination thereof.