Method for cleaning wafer edge

Semiconductor device and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Tunneling field effect transistor and method of fabricating the same

METHOD FOR CONTROLLING POLISHING WAFER

OF THE INVENTION[0036] A method for controlling polishing a wafer includes the following step.Firstly, a database storing a number of status data of a polished film of a waferand a number of polishing parameters corresponding to the status data isestablished. Each of the polishing parameters includes a head sweep of apolishing head along a redial direction of a polishing platen. The head sweeprefers to a movement distance range from a center of the polishing head to acenter of the polishing platen during a polishing process. Subsequently, a firstwafer having a predetermined status data is provided. Thereafter, thepredetermined status data is compared with the status data in the database so as tofind out the polishing parameter corresponding to the predetermined status data,thereby determining a first polishing parameter of the first wafer. Afterward, afirst polishing process using the first polishing parameter is applied to the firstwafer. The method can control the status of a polished ...

Semiconductor device having metal gate and method for manufacturing semiconductor device having metal gate

Manufacturing method of flash memory

A manufacturing method of flash memory, that includes at least a semiconductor substrate which comprises a gate oxide, a floating gate that is formed on the gate oxide and separated by an oxidation layer; the said floating gate having a wordline and a dielectric to separate the wordline from the floating gate; performing a first ion implantation on the substrate to form a source region and collector region on the wordline side; applying photoresist to cover at least the source region and collector region and the covered field oxide; and performing a second ion implantation on the substrate to form a common region.

Method of manufacturing high-voltage component substrates

A method of manufacturing high-voltage component substrates, including the forming on the substrate accordingly cushioned oxide layer and mask layer. Definition of the first ion doped area to be formed, and the rest of the area being oxidized to form field oxide layer. Then, removal of the mask layer for the first ion distribution, with removal of part of the field oxide layer. Then, with removal of the oxidized layer area, with carrying out the second ion distribution and forming a shared oxide layer on the surface of the substrate. Then, introduction of high temperature and oxidization process, making the ions in the first ion distribution area and the second ion distribution area diffuse toward the inside of the substrate, while making substrate of the first ion distribution area and the second ion distribution areas oxidize. Removal of all the oxide layer from the surface of the substrate and forming crystal layer on the surface of the substrate.

Gate structure and method for trimming spacer

Method for fabricating semiconductor device

Non-volatile memory

Probe insertion auxiliary and method of probe insertion

Inductor formed on a semiconductor substrate

Buffer circuit with regulating function and regulating circuit thereof

Mask inspecting method

STACKED ALIGNMENT MARK AND ALIGNMENT METHOD OF PHOTOLITHOGRAPHY PROCESS

Method of manufacturing mental oxide semiconductor and complementary mental oxide semiconductor

Semiconductor device and method of fabricating the same

Semiconductor device and method of fabricating the

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE SAME

A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Test circuit for testing a device-under-test by using a voltage-setting unit to pull an end of the device-under-test to a predetermined voltage

A test circuit includes a pull-up device, a pull-down device, a switch circuit and a voltage-setting unit. The pull-up device is used to receive a first control signal and coupled to a first end of the device-under-test. The pull-down device is used to receive a second control signal and coupled to the first end of the device-under-test. The switch unit is controlled by a switch signal, used to receive a testing signal and coupled to a second end of the device-under-test. The voltage-setting unit is controlled by a third control signal, used to pull the second end of the device-under-test to a predetermined voltage.

Method of forming non-planar FET

A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Image device having color filter array

An image device includes a substrate having a die region defined thereon, a layout pattern positioned in the die region, and a color filter array including a plurality of color filters arranged in a matrix in the die region. The die region includes at least a die corner. The color filter array further includes at least a color filter array corner, and at least two apexes of the color filters arranged in the color filter array corner are separated from the corresponding layout pattern by a shortest distance.

Method of fabricating nitrogen-containing gate dielectric layer and semiconductor device

A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.

Method of fabricating high voltage device

A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.

Nanowire structure and manufacturing method thereof

A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire.

METHOD FOR FORMING PATTERNED PHOTORESIST LAYER

A method for forming a patterned photoresist is provided, which is applicable to a substrate. The method includes: performing an implantation process over the substrate; next, performing a surface treatment process; then, forming a photoresist layer over the substrate; and thereafter, patterning the photoresist layer.

MULTI-STEP PLANARIZING AND POLISHING METHOD

A multi-step planarizing and polishing method includes performing a first and a second polishing steps, wherein one of the two polishing steps is performed using a silica abrasive based slurry, while the other one of the two polishing steps is performed using a CeO2 abrasive based slurry. A third polishing step is further performed using a fixed abrasive pad. Further, the thickness deviation of wafers entering the third polishing step is controlled.

NON-VOLATILE MEMORY

A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control gate and a cap layer. Next, a plurality of spacers is formed on the sidewalls of the stack structures. Thereafter, a gate dielectric layer is formed over the substrate. A word line is formed between two neighboring stack structures. After that, the cap layers in the stack structures are removed. A source and a drain are formed in the substrate beside the stack structures adjacent to the sides of each word line.

METHOD OF PREVENTING COLOR STRIATION IN FABRICATING PROCESS OF IMAGE SENSOR AND FABRICATING PROCESS OF IMAGE SENSOR

A fabricating process of an image sensor is provided. A substrate having thereon a circuit of the image sensor and an insulating layer is provided, wherein the insulating layer has therein a pad opening exposing a metal pad of the circuit. A filling layer is formed in the pad opening, and a color filter array is formed over the insulating layer. A planarization layer is formed over the substrate covering the color filter array, and a microlens array is formed on the planarization layer. The filling layer is then removed.

SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device is provided. First, a substrate is provided. The substrate includes a high-voltage device region and a low-voltage device region. The high-voltage device region has a source/drain predetermined region, a pick-up predetermined region and a channel predetermined region. A first dielectric layer is formed on the substrate. Then, the first dielectric layer in the low-voltage device region is removed along with the first dielectric layer in the source/drain predetermined region and the pick-up predetermined region. Afterwards, a second dielectric layer is formed in the low-voltage device region. The thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer. Then, gates are formed in the channel predetermined region and the low-voltage device region respectively. Next, a source/drain region is formed in the substrate of the source/drain predetermined region.

Transistor and method for forming the same

A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

Method for forming a capacitor having selective hemispherical grained polysilicon

A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.

Non-volatile memory with induced bit lines

An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

Self-aligned silicide process

A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.

Etching method for doped polysilicon layer

A method for etching a doped polysilicon layer. A first doped polysilicon layer of a first conductive type and a second doped polysilicon layer of a second conductive type are formed. An etching process is performed to pattern the first doped polysilicon layer and the second doped polysilicon layer. The etching process includes a first main etching step and a second main etching step. The etching pressure of the first main etching step is lower than the etching pressure of the second main etching step.

Method of manufacturing metal-oxide-semiconductor transistor

A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

Method for forming three dimensional semiconductor structure and three dimensional capacitor

A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

Method of testing electromigration lifetime

A method of testing EM lifetime has following steps. First, a pre-characterizing step is performed to obtain parameters such as TC(the critical temperature,), Wc (the critical line width), QGB(the activation energy of grain boundary diffusion) and QL(the activation energy of lattice diffusion) of a metal prior to the use of the test methodology for a new technology. Next, whether a real line width (W) of the metal is narrower or wider than WC is determined. For the narrower line widths, the diffusion mechanism is dominated by the Lattice diffusion only and corresponds to single activation energy (QL). A WLR isothermal test with a relatively high temperature, such as 400° C., can be implemented to reduce the test time to as short as a few seconds. The EM lifetime (t50) under normal operating condition can be directly obtained by conversion from Ttest to TC by using QL.

Half-tone phase shift mask for fabrication of poly line

A half-tone phase shift mask is formed from the composite structure of a mask substrate and a half-tone phase shifting layer. The half-tone phase shifting layer induces a 180° phase shift to light passing through the mask. The half tone phase shifting layer further includes a main pattern having a first width and a first length, and an assist feature having a second width and a second length. The assist feature is parallel to the main pattern and disposed at both sides of the main pattern while being separated therefrom by a distance. Using deep ultraviolet light as the exposure source, a wafer scale of the first width is about 0.1-0.15 mum, a wafer scale of the second width is about 0.055-0.09 mum and the distance between the main pattern and the assist feature is about 0.22-0.27 mum.

Method of forming borderless contact

A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Cylindrical capacitor structure and method of manufacture

A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited ...

CMOS sensor and method of manufacture

A CMOS sensor and a method of manufacturing a CMOS sensor. One major aspect of this invention is the use of a high-energy ion implantation to form a silicon nitride layer underneath the sensing region. Then, N-type dopants are implanted to form an N-type region above the silicon nitride layer within the substrate. Thereafter, a P-type epitaxial layer is formed above the substrate, thereby forming an intrinsic depletion region between the epitaxial layer and the N-doped region. The intrinsic depletion region is a light-sensitive area where light energy is converted into electrical signal. Height of the intrinsic depletion region can be adjusted through controlling the depth of the implant in the N-doped region.

Polysilicon thin film transistor structure

A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Method for improving non-uniformity of chemical mechanical polishing by over coating

A method for improving non-uniformity of chemical mechanical polishing by over coating layer is disclosed. The essential point of the invention is that an over coating layer is formed over a surface before the surface is planarized by a chemical mechanical polishing process. Note that polishing rate of the over coating layer must be less than the polishing rate of the surface, where the ratio of polishing rate is called as selectivity. Because the topography of the surface is not uniform, the topography of the over coating layer also is non-uniform and then the polishing probability in different parts of the over coating layer is different. Obviously, when the over coating layer on the higher area part of the surface is totally consumed, these are residual over coating layer on the lower area part of the surface. Thus, over polishing in the lower area part is prevented by residual over coating layer. Before total over coating layer is polished, the polished account of the surface is higher ...

Method for fabricating a buried vertical split gate memory device with high coupling ratio

A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.

Method for forming different patterns using one mask

A method for forming different patterns using one phase shifting mask. The phase shifting mask has a bit line contact pattern and a node contact pattern thereon. The exposure pattern is changed by using different defocus conditions. In a first defocus situation, the bit line contact pattern and the node contact pattern of the PSM are simultaneously transferred to a photoresist layer. However, in a second defocus situation, only the bit line contact pattern is transferred to the photoresist layer. A phase shifting mask thus can be used in two different photolithography processes.

Method for forming different types of MOS transistors on a semiconductor wafer

A semiconductor wafer has a substrate, a first region in the substrate that is used for a logic circuit, and a second region in the substrate that is used for a memory cell. A first gate in the first region and a second gate in the second region are simultaneously formed on the substrate. The first gate and the second gate both include a gate dielectric layer, a polysilicon layer, a tungsten silicide layer and a cap layer, in ascending order. The cap layer and the tungsten silicide layer are then removed from the first gate. A spacer around each gate is then formed. This completes the second type MOS transistor in the memory cell of DRAM. A titanium silicide layer on the surface of the substrate adjacent to the first gate and on the surface of the polysilicon layer of the first gate is formed so as to complete the formation of the first type MOS transistor.

Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

Method for fabricating air gap adjacent to two sides of bit line

A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

Manufacturing method for semiconductor structure

A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.

Process monitoring circuit and method

A process monitoring circuit may be used to determine appropriate voltage for integrated circuits including a non-volatile memory. The process monitoring circuit includes a bandgap reference, a clock generator, a negative bias circuit, a temperature insensitive oscillator, a low dropout voltage regulator, a counter, a comparison circuit, and a charge. The process monitoring circuit may also include a pulse width generator. The process monitoring circuit is able to determine the process corner of which a monitored circuit belongs to and generate an output voltage according to the process corner of the monitored circuit.

Method of manufacturing semiconductor device

The present invention provides a method of manufacturing a semiconductor device including using a first photomask to form a sacrificial block on a hard mask layer in a first region, a first dummy pattern on the sacrificial block, a first spacer on sidewalls of the sacrificial block and a second spacer in a second region; using a second photomask to form a feature mask on the first dummy pattern and a fin cutting mask on the second spacer; and performing a fin cutting process to remove a portion of the first dummy pattern, a portion of the sacrificial block underlying the portion of the first dummy pattern and the first spacer to form a feature spacer and to remove a portion of the second spacer without being covered with the fin cutting mask to form a fin spacer.

Method for fabricating metal-oxide semiconductor transistors

A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

Manufacturing method of semiconductor structure

A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.

Semiconductor structure and a fabricating method thereof

A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.

Through silicon via structure

A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

Insulating structure and method of forming the same

A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

Non-planar FET and manufacturing method thereof

The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Semiconductor structure capable of improving row hammer effect in dynamic random access memory and fabrication method thereof

A semiconductor substrate of first conductivity type is provided. At least one active area is formed on the semiconductor substrate. A major axis of the active area extends along a first direction. A first oblique ion implantation process is performed to form a first doped region of second conductivity type above a first depth on an end surface of the active area. A second oblique ion implantation process is performed to form a second doped region of third conductivity type above a second depth on the end surface of the active area. The third conductivity type and the second conductivity types are opposite to each other, so that a localized doped region having the second conductivity type is formed between the first depth and the second depth. A trench isolation structure is formed around the active area and adjacent to the end surface of the active area.

Automatic detecting method and automatic detecting apparatus using the same

An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.

Network server for servicing articles of wear

A network server provides continuous laundry services for articles of wear. Each article has a unique article identifier. The server has a customer database for associating each customer with a unique customer identification; a message server for sending electronic messages to customers; an article database; a service catalog for indicating available article-related services to the customer; an order database for tracking a process status of the article according to the article identifier, and a last-serviced database for tracking a regular service requirement of the article according to the article identifier. The network server uses the last-serviced database, the customer database, and the message server to send an electronic reminder message to the customer when a service time for the article is exceeded. The customer can use the server to inquire about the current process status of an article, and place a new order for the cleaning of an article.

Semiconductor MOS transistor device and method for making the same

A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Metal-oxide-semiconductor transistor and method of forming the same

A method of forming a metal-oxide-semiconductor (MOS) transistor device is provided. First, a semiconductor substrate is prepared. Subsequently, a gate structure is formed on the semiconductor substrate. The gate structure includes a first strip portion and a second strip portion that is not parallel to the first strip portion. The gate structure further includes a junction between the first strip portion and the second strip portion. Thereafter, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure. Next, a portion of the stressed cap layer is removed to expose the junction between the first strip portion and the second strip portion.

Method of fabricating transistors

A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Method of correcting overlay error

A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Power array with staggered arrangement for improving on-resistance and safe operating area

A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Layout pattern for 8T-SRAM and the manufacturing method thereof

The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second diffusion region and a third diffusion region disposed on a substrate, a critical dimension region being disposed between the first diffusion region and the third diffusion region. The critical dimension region directly contacts the first diffusion region and the third diffusion region, a first extra diffusion region, a second extra diffusion region and a third extra diffusion region disposed surrounding and directly contacting the first diffusion region, the second diffusion region and the third diffusion region respectively. The first, the second and the third extra diffusion region are not disposed within the critical dimension region.

Method of fabricating a metal layer

A method of fabricating a metal layer includes performing a first re-sputtering to remove a metal compound formed on a conductive layer. The first re-sputtering includes bombarding the metal compound and a dielectric layer on the conductive layer by inert ions and metal atoms. Then, a barrier is formed on the dielectric layer and the conductive layer. Later, a bottom of the barrier is removed. Subsequently, a metal layer is formed to cover the barrier.

Method for fabricating a hybrid orientation substrate

A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

PATTERNING METHOD

A patterning method of the present invention is described as follows. A mask layer and a patterned photoresist layer are formed on a target layer in sequence, wherein an etching rate of the mask layer is different from an etching rate of the target layer. A plurality of spacers is formed on sidewalls of the patterned photoresist layer respectively, wherein an etching rate of the spacers is different from the etching rate of the mask layer. The patterned photoresist layer is removed to form an opening between any two adjacent spacers. A portion of the mask layer is removed by using the spacers as a mask so as to form a patterned mask layer. A portion of the target layer is removed by using the patterned mask layer as a mask.

Transistor with strained channel and fabrication method thereof

A semiconductor device includes a substrate having a top surface, a source region in the substrate, a drain region in the substrate, a recessed trench extending from the top surface into the substrate and between the source region and the drain region, a stress-inducing material layer in the recessed trench, a channel layer on the stress-inducing material layer, and a gate structure on the channel layer. The recessed trench has a hexagonal cross-sectional profile.

Semiconductor device of electrostatic discharge protection

A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

Semiconductor device for electrostatic discharge protection

A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Semiconductor structure and fabrication method thereof

A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Forming contact holes using litho-etch-litho-etch approach

The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.

Non-volatile memory which can increase the operation window

A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Dual damascene structure and fabrication thereof

A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Device with reinforced metal gate spacer and method of fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench.

INTERPOSER AND METHOD OF FABRICATING THE SAME

The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.

MONITORING METHOD OF EXPOSURE APPARATUS

In a monitoring method of an exposure apparatus, a top critical dimension (TCD) and a bottom critical dimension (BCD) of the test pattern formed on a photo-sensitive material layer are measured. A dose deviation (ΔE) and a focus deviation (ΔF) are calculated by following equations: TCD+BCD=αΔE+(TCD0+BCD0) TCD−BCD=β1ΔF+β2ΔF3 Here, α, β1 and β2 are constants, ΔE=E−E0, ΔF=F−F0, E represents a real exposure dose, F represents a real exposure focus, E0 represents a dose defined when a middle critical dimension of the test pattern is equal to a predetermined value, F0 represents a focus defined when TCD of the test pattern is equal to BCD thereof, and TCD0 and BCD0 are theoretical values in case of E0 and F0.

Method of forming opening on semiconductor substrate

The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

MOS device

A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.

Semiconductor device with integrated memory devices and MOS devices and process of making the same

A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

Method of forming at least an opening using a tri-layer structure

A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.

Semiconductor device and method for manufacturing the same

A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

Method of using an e-fuse device

A method of using an e-fuse device is provided. The e-fuse device includes a poly-fuse having one end connected to a source/drain region of a MOS transistor and the other end biased to a voltage (V_FS). In operation, a gate of the MOS transistor receives a step waveform pulse signal. The step waveform pulse signal encompasses a pre-heat voltage (V_p) at a first level during time period (T₁-T_p) and a maximum input voltage (V_IH) at a second level during time period (T_p-T₂). The pre-heat voltage (V_p) is smaller than the maximum input voltage (V_IH). The step waveform pulse signal is confined to a minimum input voltage (V_IL) before T₁ and after T₂. Preferably, the time period (T₁-T_p) is longer than 5 mus.

Semiconductor device having epitaxial layer

A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Photoresist removal method and patterning process utilizing the same

A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.

Poly-insulator-poly capacitor and fabrication method thereof

A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FABRICATING THE SAME

A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.

Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Manufacturing method of isolation structures for semiconductor devices

A manufacturing method a semiconductor device includes the following steps. A first mask pattern and a second mask pattern are formed on a first region and a second region of a substrate respectively. The second region is located adjacent to the first region. A top surface of the first mask pattern is lower than a top surface of the second mask pattern in a thickness direction of the substrate. A trench is formed in the substrate. The trench is partly located in the first region and partly located in the second region. A first etching process is performed for reducing a thickness of the second mask pattern and reducing a height difference between the top surface of the first mask pattern and the top surface of the second mask pattern in the thickness direction of the substrate. An isolation structure is formed in the trench after the first etching process.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

METHOD OF ETCHING SACRIFICIAL LAYER

An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process. 1. A method of etching a sacrificial layer , adapted for an integrated circuit process and comprising:providing a substrate formed with a sacrificial layer, and defined with a first region and a second region, wherein the sacrificial layer disposed in both the first region and the second region;forming a hard mask covering the first region while exposing the second region;performing a first etching process on the sacrificial layer on the substrate by using the hard mask as an etch mask to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer;performing a second etching process on the byproduct film to remove a portion of the byproduct film for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sides of the thinned sacrificial layer being remained; andperforming a third etching process on the thinned sacrificial layer having the remained byproduct film disposed on the sides thereof, to remove the portion of the thinned sacrificial layer exposed in the second ...

BACKSIDE ILLUMINATED IMAGE SENSOR

A backside illuminated (BSI) image sensor including a substrate, a plurality of photosensitive regions, a back-end-of-line (BEOL), a pad, a color filter array, a plurality of micro-lenses and a protection layer is provided. The substrate has a first surface and a second surface. The substrate has a pad opening therein through the first surface and the second surface. The photosensitive regions are disposed in the substrate. The BEOL is disposed on the first surface of the substrate. The pad is disposed in the BEOL and exposed by the pad opening. The color filter array is disposed on the second surface of the substrate. The micro-lenses are disposed on the color filter array. The protection layer at least covers the top corner and the sidewall of the pad opening. 1. A backside illuminated (BSI) image sensor , comprising:a substrate, having a first surface and a second surface, wherein the substrate has a pad opening therein through the first surface and the second surface;a plurality of photosensitive regions, disposed in the substrate;a back-end-of-line (BEOL), disposed on the first surface of the substrate;a pad, disposed in the BEOL and exposed by the pad opening;a color filter array, disposed on the second surface of the substrate;a plurality of micro-lenses, disposed on the color filter array; anda protection layer, at least covering a top corner and a sidewall of the pad opening.2. The BSI image sensor of claim 1 , the protection layer comprises an inorganic dielectric material claim 1 , an organic material or a combination thereof.3. The BSI image sensor of claim 2 , wherein the inorganic dielectric material comprises silicon oxide claim 2 , silicon nitride claim 2 , silicon oxynitride or a combination thereof.4. The BSI image sensor of claim 2 , wherein the organic material comprises a positive photoresist material or a negative photoresist material.5. The BSI image sensor of claim 1 , further comprising an anti-reflection layer disposed between the substrate ...

CLEANING SOLUTION, CLEANING METHOD AND DAMASCENE PROCESS USING THE SAME

A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NHF); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance. 1. A cleaning solution , comprising:(a) 0.01-0.1 wt % of hydrofluoric acid (HF);(b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid;{'sub': '4', '(c) 0.05-0.5 wt % of ammonium fluoride (NHF);'}(d) a chelating agent containing a carboxylic group;(e) triethanolamine (TEA);(f) ethylenediaminetetraacetic acid (EDTA); and(g) water for balance.2. The cleaning solution of claim 1 , wherein the strong acid comprises sulfuric acid (HSO) or hydrochloric acid (HCl).3. The cleaning solution of claim 1 , wherein the chelating agent containing the carboxylic group comprises oxalic acid.4. The cleaning solution of claim 1 , which consists of (a) to (g).5. A damascene process claim 1 , comprising:providing a substrate having a conductive layer and a cap layer sequentially thereon;sequentially forming a dielectric layer and a metal hard mask layer on the cap layer;sequentially etching the metal hard mask layer, the dielectric layer and the cap layer, so as to form an opening exposing the conductive layer; (a) 0.01-0.1 wt % of hydrofluoric acid (HF);', '(b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid;', {'sub': '4', '(c) 0.05-0.5 wt % of ammonium fluoride (NHF);'}, '(d) a chelating agent containing a carboxylic group;', '(e) triethanolamine (TEA);', '(f) ethylenediaminetetraacetic acid (EDTA); and', '(g) water for balance;, 'performing a post-etch cleaning process with a cleaning solution, the cleaning solution comprisingfilling a conductive material in the opening; andremoving the metal hard mask layer.6. The damascene process of claim 5 , wherein the ...

NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF

A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening. 1. A non-volatile memory comprising:a substrate;a gate dielectric layer, disposed on the substrate and having a cavity formed on two end sides of the gate dielectric layer;a gate conductive layer, disposed on the gate dielectric layer, wherein a bottom width of the gate conductive layer is greater than a width of the gate dielectric layer, the gate conductive layer, the substrate and the gate dielectric layer cooperatively constitute a symmetrical opening thereamong;a nitride layer, disposed on a sidewall of the gate conductive layer and extending into the opening;a first oxide layer, disposed on a sidewall and bottom of the gate conductive layer and among the gate conductive layer, the nitride layer and the gate dielectric layer; anda second oxide layer, disposed on the substrate and among the gate dielectric layer, the nitride layer and the substrate.2. The non-volatile memory as claimed in claim 1 , further comprising:two lightly-doped regions, symmetrically disposed in the substrate at two sides of the nitride layer;a spacer, disposed on the substrate as well as the nitride layer on the side of the gate ...

Method and pattern carrier for optimizing inspection recipe of defect inspection tool

A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively. 1. A method of fabricating a semiconductor device , comprising:forming a polysilicon layer on a substrate;doping an N-type dopant into the polysilicon layer;removing a portion of the polysilicon layer to form a plurality of dummy patterns, each of the plurality of dummy patterns having a top, a bottom, and a neck arranged between the top and the bottom, wherein a width of the neck is narrower than a width of the top;forming a dielectric layer on the substrate, the dielectric layer covering the substrate disposed between two adjacent dummy patterns and exposing the top of each dummy pattern;removing the plurality of dummy patterns to form a plurality of trenches in the dielectric layer; andforming a plurality of gate structures in the trenches respectively.2. The method of fabricating the semiconductor device as claimed in claim 1 , wherein a depth of the polysilicon layer doped with a highest concentration of the N-type dopant and the neck are substantially located on the same horizontal level of height.31. The method of fabricating the semiconductor device as claimed in claim claim 1 , wherein a concentration of the N-type dopant doped in a bottom of the polysilicon layer is greater than a concentration of the N-type dopant doped in a top of ...

Semiconductor process

A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted. 1. A semiconductor process , comprising:providing a substrate;depositing a material layer on the substrate in the presence of a plasma treatment with a plasma generated from a gas source comprising a reactant gas and a carrier gas;continuously conducting the plasma treatment immediately after depositing the material layer, while stopping to introduce the reactant gas; andconducting a pump-down step.2. The semiconductor process according to claim 1 , further comprising conducting a purge step between the plasma treatment and the pump-down step.3. The semiconductor process according to claim 1 , wherein the reactant gas comprises a organic precursor claim 1 , and the organic precursor comprises an organosiloxane-based precursor.4. The semiconductor process according to claim 3 , wherein the organosiloxane-based precursor is selected from the group consisting of tetraethyl orthosilicate (TEOS; Si(OC2H5)4) claim 3 , 1 claim 3 ,3 claim 3 ,5 claim 3 ,7-tetramethylcyclotetrasiloxane (TMCTS; C4H16O4Si4) claim 3 , dimethyldimethoxysilane (DMDMOS; C4H12O2Si) and octamethylcyclotetrasiloxane (OMCTS; C8H24O4Si4).5. The semiconductor process according to claim 1 , wherein the reactant gas comprises a organic precursor claim 1 , and the organic precursor is supplied from a liquid system through gasification.6. The semiconductor process according to claim 1 , wherein the gas source comprises inert gas or oxygen or hydrogen.7. The semiconductor process according to claim 1 , wherein a flow rate of the gas source is within a range of 1000 sccm to 40000 sccm.8. The semiconductor ...

Cleaning Method for Wafer

A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.

Cleaning solution and damascene process using the same

A cleaning solution is provided. The cleaning solution includes a fluorine containing compound, an inorganic acid, a chelating agent containing a carboxylic group and water for balance. The content of the fluorine containing compound is 0.01-0.5 wt % of. The content of the inorganic acid is 1-5 wt %.

Adjusting method of channel stress

An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region.

REMOVING METHOD OF A HARD MASK

A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate. 1. A removing method of a hard mask , comprising:providing a substrate;forming at least two MOSFETs on the substrate and an isolating structure between the at least two MOSFETs, each of the two MOSFETs comprising a gate insulating layer, a gate, a spacer and a hard mask on the gate;forming either a photoresist layer or a bottom anti-reflective coating layer on the substrate to cover the at least two MOSFETs and the isolating structure;etching back either the photoresist layer or the bottom anti-reflective coating layer without a mask till the hard masks of the at least two MOSFETs are exposed, wherein the remained photoresist layer or the remained bottom anti-reflective coating layer forms a protecting structure located on and directly contacted with the isolating structure; andremoving the exposed hard masks of the at least two MOSFETs.2. The removing method of the hard mask as claimed in claim 1 , wherein the isolating structure is either a shallow trench isolation or a field oxide isolation.3. The removing method of the hard mask as claimed in claim 1 , wherein the gate is either a metal gate or a poly-silicon gate.4. The removing method of the hard mask as claimed in claim 1 , wherein the gate insulating layer comprises a silicon oxide layer and a high-K insulating layer.5. The removing method of the hard mask as claimed in claim 1 , wherein the spacer at least comprises a first spacer and a second spacer.6. The removing method of the hard mask as claimed in claim ...

STRESS-ADJUSTING METHOD OF MOS DEVICE

A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. 1. A stress-adjusting method for use in a manufacturing system of a MOS device , comprising:forming a first stress layer onto a substrate with at least two MOSFETs formed thereon, the first stress layer overlying at least a gate region of the MOSFETs and an inter-gate region between two adjacent gate regions of the MOSFETs;thinning the first stress layer in the inter-gate region with a dry etching process to obtain a thinned first stress layer; andforming a second stress layer onto the substrate, overlying the thinned first stress layer in the inter-gate region.2. The method according to claim 1 , wherein a thickness of the first stress layer is 100˜150 A.3. The method according to claim 1 , wherein 50˜150 A of the first stress layer is removed in the dry etching process.4. The method according to wherein a thickness of the second stress layer is 100˜500 A.5. (canceled)6. The method according to claim 1 , wherein each of the first stress layer and the second stress layer is selected from a single silicon nitride layer or a multiple layer composed of silicon oxide and silicon nitride.7. The method according to claim 1 , further comprising thinning the second stress layer in the inter-gate region claim 1 , and forming a third stress layer onto the substrate claim 1 , overlying the thinned second stress layer in the inter-gate region.8. A Stress Memorization ...

METHOD OF SELECTIVELY REMOVING PATTERNED HARD MASK

A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask. 1. A method of selectively removing a patterned hard mask , comprising:providing a substrate with a patterned target layer thereon, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern;forming a first photoresist layer covering the first mask pattern;covering a sidewall of the at least one second target pattern by a second photoresist layer; andremoving the second mask pattern using the first photoresist layer and the second photoresist layer as a mask.2. The method of claim 1 , wherein each of the first target pattern and the at least one second target pattern is disposed with a spacer structure on its sidewall.3. The method of claim 2 , wherein the spacer structure comprises a first spacer and a second spacer disposed on the first spacer.4. The method of claim 3 , wherein the spacer structure further comprises an L-shaped liner layer partially between the first or second target pattern and the first spacer and partially under the first spacer.5. The method of claim 1 , wherein the step of covering the sidewall of the at least one second target pattern by the second photoresist layer comprises:forming ...

CLEANING METHOD FOR SEMICONDUCTOR WAFER AND CLEANING DEVICE FOR SEMICONDUCTOR WAFER

A cleaning method of a semiconductor wafer includes the following steps. A semiconductor wafer is provided. A cleaning solution is sprayed to the semiconductor wafer. The semiconductor wafer is driven to spin along a first direction for a first time. The semiconductor wafer is driven to spin along a second direction for a second time. The cleaning method can effectively clean the semiconductor wafer. A cleaning device for cleaning a semiconductor wafer is also provided. 1. A cleaning method of a semiconductor wafer , comprising:providing a semiconductor wafer;spraying a cleaning solution to the semiconductor wafer;driving the semiconductor wafer to spin along a first direction for a first time; anddriving the semiconductor wafer to spin along a second direction for a second time.2. The cleaning method of the semiconductor wafer as claimed in claim 1 , wherein the semiconductor wafer comprises a dual damascene groove structure.3. The cleaning method of the semiconductor wafer as claimed in claim 2 , wherein the cleaning solution is a chemical cleaning solution and is configured for removing a byproduct in a dry process of forming the dual damascene groove structure.4. The cleaning method of the semiconductor wafer as claimed in claim 3 , wherein the chemical solution is either an organic acid or an inorganic acid.5. The cleaning method of the semiconductor wafer as claimed in claim 1 , wherein either the first direction is a clockwise direction and the second direction is an anti-clockwise direction or the first direction is an anti-clockwise direction and the second direction is a clockwise direction.6. A cleaning device for cleaning a semiconductor wafer claim 1 , the cleaning device comprising:a nozzle for spraying a cleaning solution to the semiconductor wafer;a spinning device for supporting the semiconductor wafer and driving the semiconductor wafer to spin along a first direction for a first time and driving the semiconductor wafer to spin along a second ...

CMOS STRUCTURE AND LATCH-UP PREVENTING METHOD OF SAME

A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants. 1. A CMOS structure , comprising a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion , an insulation layer overlying at least the N-well region , and a pad structure disposed over the N-well region , the pad structure further comprising:a pad body disposed on the insulation layer; andat least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region;wherein the contact zone interfaces the N-well region with P-type dopants.2. The CMOS structure according to wherein the insulation layer overlies the PMOS portion claim 1 , the NMOS portion claim 1 , the P-well region and the N-well region.3. The CMOS structure according to wherein the insulation layer is an inter-layer dielectric layer.4. The CMOS structure according to wherein the at least one contact plug further penetrates through a field oxide layer disposed between the insulation layer and the N-well region.5. The CMOS structure according to wherein the contact zone includes an inner dopant area formed with N-type dopants and an outer dopant area formed with the P-type dopants.6. The CMOS structure according to ...

ANTI PUNCH-THROUGH LEAKAGE CURRENT METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND MANUFACTURING METHOD THEREOF

An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate. 1. A manufacturing method of anti punch-through leakage current MOS transistor , comprising:providing a second type substrate;forming a high voltage deep first type well region in the second type substrate;forming a first type light doping region in the high voltage deep first type well region in the second type substrate to form a drain structure, a doping concentration of a first type dopant of the first type light doping region is greater than a doping concentration of the first type dopant of the high voltage deep first type well region;forming a mask with a dopant implanting opening on the second type substrate;forming an anti punch-through leakage current structure in the high voltage deep first type well region by implanting the first type dopant through the dopant implanting opening, a doping concentration of the first type dopant of the anti punch-through leakage current structure being greater than a doping concentration of the first type dopant of the high voltage deep first type well region;forming a second type body by implanting a second type dopant through the dopant implanting opening so as to form a source structure and a body ...

Method of forming silicide for contact plugs

A metal layer structure includes a substrate, a metal layer and a composite passivation. The metal layer is disposed in the substrate. The composite passivation includes a first material layer covering the substrate, an opening disposed in the first material layer and exposing the metal layer as well as a second material layer. The second material layer surrounds the sidewall of the opening, covers part of the bottom of the opening and exposes the metal layer.

METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS

A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd Подробнее

Patterning method and method for fabricating dual damascene opening

A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.

METHOD FOR MANUFACTURING THROUGH-SILICON VIA

A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed. 1. A method for manufacturing a through-silicon via (TSV) , the method comprising:providing a stack structure having a substrate, an internal layer dielectric (ILD) layer and a dielectric stop layer, wherein an opening is formed in the stack structure penetrating through the ILD layer, the dielectric stop layer and further extending into the substrate;providing a insulator layer and a metal barrier sequentially on the stack structure and the and the sidewalls of the opening;providing a top metal layer formed on the stack structure to fill the opening;conducting a first planarization process stopping on the metal barrier to remove a portion of the top metal layer, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer;conducting a second planarization process stopping on the dielectric stop layer to remove portions of the top metal layer, the metal barrier and the insulator layer, wherein the second planarization process has a polishing rate for removing the ...

METHOD FOR MANUFACTURING IMAGE SENSOR

A method for manufacturing an image sensor, wherein the method comprises several steps as follows: A semiconductor base doped with dopants having a first-type electrical conductivity is provided, wherein the semiconductor base comprises a handle wafer, an oxide insulator disposed on the handle wafer, and a silicon layer disposed on the oxide insulator. A front end process is then conducted, to form at least one imaging pixel disposed in the silicon layer and at least one metal layer disposed on the imaging pixel, whereby the first-type electrical dopants can be driven into the silicon layer to form a doping layer with the first-type electrical conductivity over the oxide insulator. 1. A method for manufacturing an image sensor , the method comprising:providing a semiconductor base comprises a handle wafer doped with dopants having a first-type electrical conductivity, an oxide insulator disposed on the handle wafer, and a silicon layer disposed on the oxide insulator; andconducting a front end process to form at least one imaging pixel with the silicon layer and at least one metal layer above the imaging pixel, whereby the first-type electrical dopants initially doped in the handle wafer of the semiconductor base can be diffused into the silicon layer to form a doping layer having the first-type electrical conductivity.2. (canceled)3. The method of claim 1 , wherein the first-type electrical dopants are doped in the oxide insulator of the semiconductor base.4. The method of for manufacturing the image sensor claim 1 , wherein the front end process comprises at least one thermal step for driving the first-type electrical dopants into the silicon layer to form the doping layer.5. The method of for manufacturing the image sensor claim 4 , wherein the thermal step has an processing temperature substantially ranged from 800° C. to 1200° C.6. The method of for manufacturing the image sensor claim 1 , wherein the front end process comprises at least one ion implantation ...

Method and system for processing semiconductor wafer

In a method for processing a semiconductor wafer formed with a copper conductor, the semiconductor wafer is etched in an etching chamber to expose the copper conductor. The etched semiconductor wafer is transmitted from the etching chamber to a buffer zone, where a gas inert to the semiconductor wafer is introduced for a period of time. Then the semiconductor wafer is moved out of the buffer zone to a loading module. Nitrogen is one of the suitable options as the gas, and argon is another option.

Silicon dioxide film fabricating process

A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.

CLEANING METHOD OF SEMICONDUCTOR PROCESS

The present invention is to provide a cleaning method to a process for fabricating a semiconductor. The method comprises steps as follows: A semiconductor substrate is first provided. An atomized spray are then continually supplied for a first time interval to clean the semiconductor substrate; and a water film is formed on the surface of the semiconductor substrate at or before a start point of the first time interval to buffer the impact imposed by the atomized spray, wherein the water film is preserved for a second time interval at least partially overlaps the first time interval. 1. A method for cleaning a semiconductor wafer , comprising:providing a semiconductor substrate;supplying an atomic spray continually for a first time interval to clean the semiconductor substrate;forming a water film on a surface of the semiconductor substrate at or before a start point of the first time interval to buffer a impact imposed on the surface of the semiconductor substrate by the atomized spray, wherein the water film is preserved for a second time interval at least partially overlaps the first time interval.2. The method as claimed in claim 1 , wherein the semiconductor substrate is a wafer.3. The method as claimed in claim 1 , wherein the semiconductor substrate can be rotated with a rotation rate ranges from 2000 rpm to 30 rpm during the cleaning process.4. The method as claimed in claim 1 , wherein the cleaning process is started at a position departs from the center of the semiconductor substrate claim 1 , and the cleaning process is conducted backwards and forwards between the center of the semiconductor substrate and an area where departs from the edge of the semiconductor substrate for about 30 mm.5. The method as claimed in claim 1 , wherein the atomized spray is made of a first deionized water (DI water) atomized by a nitrogen (N) gas source.6. The method as claimed in claim 5 , wherein the Ngas source has a flow rate ranges from 5 to 100 l/min.7. The method as ...

METHOD FOR EVALUATING FAILURE RATE

A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips. 1. A method for evaluating failure rate , which is applied to a plurality of semiconductor chips with error checking and correcting function , the method comprising:applying a first read-write test operation to the semiconductor chips with error checking and correcting function, thereby obtaining a plurality of first failure bit counting values corresponding to the semiconductor chips, the error checking and correcting function of each of the semiconductor chips being off;applying an aging test to the semiconductor chips;applying a second read-write test operation as the first read-write test operation to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values corresponding to the semiconductor chips; andcalculating the number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient to obtaining a failure rate of the semiconductor chips.2. The method as claimed in claim 1 , wherein each of the semiconductor chips comprises a random access memory unit.3. The method as claimed in claim 1 , ...

PLANARIZATION METHOD APPLIED IN PROCESS OF MANUFACTURING SEMICONDUCTOR COMPONENT

A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer. 1. A planarization method applied in a process of manufacturing a semiconductor component , comprising:providing a substrate;forming a dielectric layer above the substrate, the dielectric layer defining a trench therein;forming a barrier layer and a metal layer on the dielectric layer in sequence and filled in the trench;applying a first planarization process to the metal layer by using a first reactant so that a portion of the metal layer is removed to expose a portion of the barrier layer, an etching rate of the first reactant to the metal layer being greater than an etching rate of the first reactant to the barrier layer; andapplying a second planarization process to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and a portion of the metal layer are removed to expose the dielectric layer, an etching rate of the second reactant to the barrier layer being greater than an etching rate of the second reactant to the metal layer.2. The planarization method as claimed in claim 1 , further comprising forming a gate dielectric layer below the dielectric layer.3. The planarization method as claimed in claim 1 , ...

METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF REPAIRING OPTICAL PROXIMITY CORRECTION

A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data. 1. An integrated circuit , comprising:a plurality of patterned layers and a plurality of contact plugs, wherein at least one contact plug among the plurality of contact plugs has an elliptic shape in a top view.2. The integrated circuit of claim 1 , wherein the plurality of patterned layers includes an upper patterned layer and a lower patterned layer that are respectively over and under the at least one contact plug and both relate to the at least one contact plug.3. The integrated circuit of claim 2 , wherein the upper patterned layer and the lower patterned layer each comprises a plurality of conductive lines.4. The integrated circuit of claim 3 , wherein the at least one contact plug is connected with a first conductive line in the upper patterned layer and with a second conductive line in the lower patterned layer claim 3 , and a major axis of the elliptic shape of the at least one contact plug is parallel or perpendicularly to the first conductive line or the second conductive line.5. The integrated circuit of claim 2 , wherein the at least one contact plug is located in a dielectric layer as a first patterned layer among the plurality of patterned layers claim 2 , and the plurality of patterned layers also includes a second patterned layer at the same level of the at least one contact plug.6. The integrated circuit of claim 5 , whereinthe lower patterned layer includes a plurality ...

Method to compensate optical proximity correction

A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.

MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE STRUCTURE

A microelectromechanical system microphone package structure includes a base plate and a plurality of chips is provided. The plurality of chips are disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are not parallel to each other. 1. A microelectromechanical system microphone package structure , comprising:a base plate; anda plurality of chips, disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are not parallel to each other.2. The microelectromechanical system microphone package structure according to claim 1 , wherein the normal lines extend toward the same point.3. The microelectromechanical system microphone package structure according to claim 1 , further comprising at least one holder claim 1 , disposed between the base plate and a chip claim 1 , so as to adjust an inclination angle of the chips. The present application is a divisional application claiming benefit from a parent U.S. patent application bearing a Ser. No. 12/211,650 and filed Sep. 16, 2008, contents of which are incorporated herein for reference.1. Field of the InventionThe present invention generally relates to a semiconductor device, in particular, to a microelectromechanical system microphone package structure.2. Description of Related ArtMicroelectromechanical System Device (MEMS device) refers to a microelectromechanical device manufactured in a miniaturized package structure with a technology extremely similar to a technology for manufacturing an integrated circuit (IC). However, the MEMS device interacts with a surrounding environment in more manners than a conventional IC, such as interaction in mechanics, optics, or magnetic force. The MEMS ...

Polysilicon layer and method of forming the same

The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

MONITOR APPARATUS AND METHOD FOR DETECTING MOVEMENT BEHAVIOR OF OBJECT IN CYLINDER

An object is set to move back and forth between a first position and a second position in a cylinder. A measurement point between the first position and the second position is preset. A counted period indicating a duration that the object moves from the first position to the first measurement point is obtained. Then a movement behavior parameter is obtained according to the counted period. Whether the movement behavior parameter of the object matches a specified condition is determined. If matching occurs, a warning message is generated. 1. A monitoring method for monitoring a movement behavior of an object in a cylinder , the object being set to move back and forth between a first position and a second position in the cylinder , and the monitoring method comprising steps of:setting a first measurement point between the first position and the second position;obtaining a first counted period indicating a duration that the object moves from the first position to the first measurement point;obtaining a movement behavior parameter according to the first counted period; anddetermining whether the movement behavior parameter of the object matches a first condition, and generating a first warning message if matching occurs.2. The monitoring method according to claim 1 , further comprising a step of obtaining a first reference period indicating a duration that the object moves at a specified constant speed from the first position to the first measurement point.3. The monitoring method according to claim 2 , the movement behavior parameter is a first time difference between the first reference period and the first counted period.4. The monitoring method according to claim 3 , wherein the first condition is matched if the first time difference lies beyond a specified range.5. The monitoring method according to claim 1 , further comprising steps of:setting a second measurement point between the first position and the second position;obtaining a second counted period indicating ...

METHOD FOR FABRICATING FIN FIELD EFFECT TRANSISTOR

A method for fabricating a fin-FET, wherein the method comprises several steps as follows: A substrate is first provided, and a silicon fin is then formed in the substrate. Next a dielectric layer is formed on the silicon fin and the substrate. A poly silicon layer is subsequently formed on the dielectric layer, and the poly silicon layer is then planarized. Subsequently, a poly silicon gate is formed and a portion of the silicon fin is exposed by patterning the planarized poly silicon layer. A source and a drain are separately formed on two opposite sides of the exposed silicon fin adjacent to the poly silicon gate. 1. A method for fabricating a fin field effect transistor (fin-FET) , the method comprising:providing a substrate;forming a silicon fin in the substrate;forming a dielectric layer on the silicon fin and the substrate;forming a poly silicon layer on the dielectric layer;planarizing the poly silicon layer;patterning the planarized poly silicon layer to form a poly silicon gate and expose a portion of the silicon fin; andforming a source and a drain separately on two opposite sides of the exposed silicon fin adjacent to the poly silicon gate.2. The method of for fabricating the fin-FET claim 1 , wherein the substrate is a Silicon-on-Insulator (SOI) substrate.3. The method of for fabricating the fin-FET claim 2 , wherein the SOI substrate comprises a silicon base claim 2 , an insulator layer and an epitaxial silicon layer.4. The method of for fabricating the fin-FET claim 3 , wherein the formation of the silicon fin comprises a step of patterning the epitaxial silicon layer to form a three dimensional silicon fin and expose a portion of the insulator layer.5. The method of for fabricating the fin-FET claim 1 , wherein the dielectric layer comprises a high dielectric constant layer.6. The method of for fabricating the fin-FET claim 1 , further comprising a step of forming a gate material layer on the dielectric layer before the poly silicon layer is formed ...

STRESS ADJUSTING METHOD

An stress adjusting method includes the following steps. A substrate is provided. A first gate structure and a second gate structure adjacent to the first gate structure are formed on the substrate. Each of the first gate structure and the second gate structure includes a spacer. A source/drain implantation process is applied to the substrate by using the first gate structure with the spacer and the second gate structure with the spacer as a mask. After the source/drain implantation process, the spacers are thinned so as to increase a distance between the first gate structure and the second gate structure. A stress film is formed. A first annealing process is applied to the substrate having the stress film. 1. A stress adjusting method , comprising:providing a substrate;forming a first gate structure and a second gate structure adjacent to the first gate structure on the substrate, each of the first gate structure and the second gate structure comprising a spacer;applying a source/drain implantation process to the substrate by using the first gate structure with the spacer and the second gate structure with the spacer as a mask;after the source/drain implantation process, thinning the spacers so as to increase a distance between the first gate structure and the second gate structure;forming a stress film to cover the first gate structure with the thinned spacer, the second gate structure with the thinned spacer and a surface of the substrate exposed from the first gate structure with the thinned spacer and the second gate structure with the thinned spacer; andapplying a first annealing process to the substrate having the stress film.2. The stress adjusting method as claimed in claim 1 , wherein the substrate is a silicon substrate claim 1 , and the spacer comprises a first spacer and a second spacer.3. The stress adjusting method as claimed in claim 2 , wherein the first spacer is either a composite layer structure comprising a silicon oxide layer and a silicon ...

METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved. 1. A metal oxide semiconductor field effect transistor , comprising:a substrate;a gate structure, disposed on the substrate;a spacer, disposed on a side wall of the gate structure; a source/drain layer, disposed in the substrate and outside of the spacer, wherein the depth of the source/drain layer is larger than the depth of the source/drain extension layer; and', 'a dopant diffusion barrier layer, disposed directly under the source/drain extension layer and in a side of the source/drain extension layer near the gate structure;', 'wherein an entire of the source/drain layer is comprised of a strained material comprising two different atoms., 'a source/drain extension layer, disposed in the substrate and below the spacer;'}2. The metal oxide semiconductor field effect transistor of claim 1 , wherein the strained material is silicon germanium.3. The metal oxide semiconductor field effect transistor of claim 1 , wherein the source/drain extension layer is comprised of the strained material.4. The metal oxide semiconductor field effect transistor of claim 3 , wherein the ...

METHOD OF MANUFACTURING IMAGE SENSOR

A method of manufacturing image sensor includes the following steps. A substrate having a first region and a second region is provided. A plurality of image sensing components and a periphery circuit are formed on the substrate in the first region and the second region respectively. A first conductive layer and a first dielectric layer are formed on the substrate. An etch stop layer is formed on the first dielectric layer. A second conductive layer is formed on the etch stop layer in the second region. A second dielectric layer is formed on the substrate. The second dielectric layer on the etch stop layer in the first region is etched to be removed. The etch stop layer in the first region is removed to form a space. A color filter array is disposed in the space. 1. A method of manufacturing image sensor , comprising:providing a substrate, the substrate having a first region and a second region;forming a plurality of image sensing components on the substrate in the first region;forming a periphery circuit on the substrate in the second region;forming a first conductive layer on the substrate in the first region and the second region and forming a first dielectric layer on the substrate to cover the first conductive layer and directly contacted with the first conductive layer;forming an etch stop layer on the first dielectric layer and directly contacted with the first dielectric layer;forming a second conductive layer on the etch stop layer in the second region;forming a second dielectric layer on the substrate to cover the second conductive layer and the etch stop layer;etching the second dielectric layer to remove the second dielectric layer on the etch stop layer in the first region;entirely removing the etch stop layer in the first region to form a space; anddisposing a color filter array in the space.2. The method of manufacturing image sensor as claimed in claim 1 , wherein the substrate is a silicon substrate claim 1 , and each of the image sensing components ...

Semiconductor machine and cleaning process thereof

A semiconductor machine and a cleaning process are provided. The semiconductor machine includes a chamber and a cleaning module. The cleaning process includes the following steps. Firstly, the semiconductor machine is used to perform a semiconductor manufacturing process, wherein a titanium-based material is etched in the semiconductor manufacturing process. Then, a cleaning task is activated to clean the semiconductor machine by using a cleaning agent including a gas mixture of a fluoride compound and oxygen.

SEMICONDUCTOR CHIP PACKAGE STRUCTURE AND SEMICONDUCTOR CHIP

A semiconductor chip package structure including a first semiconductor chip, a second semiconductor chip and a supporting substrate is provided. The first semiconductor chip includes at least a first conductor unit. The first conductor unit has a first bonding surface and a second bonding surface exposed from the first semiconductor chip. The second semiconductor chip includes at least a second conductor unit. The second conductor unit has a third bonding surface and a fourth bonding surface exposed from the second semiconductor chip. The third bonding surface is contacted with and electrically connected to the first bonding surface. The supporting substrate includes a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface. A semiconductor chip and a semiconductor chip group are also provided. 1. A semiconductor chip package structure , comprising:a first semiconductor chip comprising at least a first conductor unit, the first conductor unit having a first bonding surface and a second bonding surface, the first bonding surface and the second bonding surface being exposed from the first semiconductor chip;a second semiconductor chip comprising at least a second conductor unit, the second conductor unit having a third bonding surface and a fourth bonding surface, the third bonding surface and the fourth bonding surface being exposed from the second semiconductor chip, wherein the third bonding surface is contacted with and electrically connected to the first bonding surface; anda supporting substrate comprising a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface.2. The semiconductor chip package structure as claimed in claim 1 , wherein the first semiconductor chip and the second semiconductor chip are selected from a group consisting of a memory chip claim 1 , a logic circuit chip and a light emitting diode chip.3. The semiconductor chip ...

MEMS and Protection Structure Thereof

A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.

METHOD OF FABRICATING CONTIGUOUS MICROLENS ARRAY

A method of fabricating a contiguous microlens array is disclosed. First, an array of photoresist patterns is formed, wherein each photoresist pattern has a substantially circular or polygonal shape in a top view and neighboring photoresist patterns are connected with each other or close to each other. Then a reflow step is performed to heat the photoresist patterns thereby rounding a surface of each photoresist pattern and connecting the neighboring photoresist patterns that are close to each other. Finally, a fixing step is performed to fix a shape of each photoresist pattern. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto. 1. A method of fabricating a contiguous microlens array , comprising:forming an array of photoresist patterns, wherein each photoresist pattern has a substantially circular or polygonal shape in a top view and neighboring photoresist patterns are connected with each other or close to each other;performing a reflow step that heats the photoresist patterns to round a surface of each photoresist pattern and connect the neighboring photoresist patterns that are close to each other as formed; andperforming a fixing step to fix a shape of each photoresist pattern.2. The method of claim 1 , wherein the fixing step comprises irradiating the photoresist patterns with UV-light.3. The method of claim 1 , wherein the fixing step comprises further heating the photoresist patterns at a temperature higher than a temperature set in the reflow step.4. The method of claim 1 , wherein a surface of each photoresist pattern as formed has a non-uniform height distribution and a height of the surface decreases from inner to outer.5. The method of claim 4 , wherein the array of photoresist patterns is defined by a single photomask on which a photomask pattern corresponding to a photoresist pattern has a transparency distribution such ...

Contiguous microlens array

The present disclosure provides a contiguous microlens array, which consists of a plurality of touching microlenses, wherein the adjacent microlenses are connected to each other to form a contiguous microlens array and curvatures of every angle cross section of each microlens are the same. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto.

METAL LINE STRUCTURE AND MANUFACTURING METHOD FOR TRENCH

Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench. 1. A metal line structure comprising:a substrate;a target layer formed on the substrate; anda trench formed in the target layer, wherein the trench has a micro-trench formed at the bottom of the trench and a depth of the micro-trench is not more than 50 angstroms; anda conductor line inlaid into the trench.2. The metal line structure as claimed in claim 1 , wherein the substrate comprises a silicon substrate claim 1 , and the target layer comprises an ultra-low dielectric constant material.3. The metal line structure as claimed in claim 1 , wherein the conductor line is a gate electrode claim 1 , and the gate electrode is made of poly-silicon or metal.4. The metal line structure as claimed in claim 1 , wherein the conductor line is an interconnect line claim 1 , and the interconnect line is a copper line.5. The metal line structure as claimed in claim 1 , wherein the micro-trench is formed in a region defined by a first photo-mask partially overlying a second photo-mask.6. The metal line structure as claimed in claim 1 , wherein the micro-trench is formed in a region defined by a first photo-mask overlying and partially mis-aligned with a second photo-mask.7. The metal line structure as claimed in claim 5 , wherein the conductor line in the micro-trench is an I-shaped connecting portion claim 5 , a T-shaped connecting portion claim 5 , an L-shaped bending portion claim 5 , a Π-shaped connecting portion or an S-shaped bending portion.8. A manufacturing method for a trench claim 5 , comprising steps of:providing a substrate;sequentially ...

METHOD FOR FABRICATING IMAGE SENSOR

A method for fabricating an image sensor is provided. A substrate is provided, and then a plurality of photoresist patterns is formed on the substrate. The photoresist patterns are arranged in a first array, wherein a top view of each photoresist pattern has a substantially square shape and a distance between two neighboring photoresist patterns decreases from a center of the first array toward an edge of the first array. Then, a thermal reflow step is performed to convert the photoresist patterns into a plurality of microlenses arranged in a second array. 1. A method of fabricating an image sensor , comprising:providing a substrate of the image sensor;forming on the substrate a plurality of photoresist patterns arranged in a first array, wherein a top view of each photoresist pattern has a substantially square shape and a distance between two neighboring photoresist patterns decreases from a center of the first array toward an edge of the first array; andperforming a thermal reflow step to convert the photoresist patterns into a plurality of microlenses arranged in a second array.2. The method of claim 1 , wherein a height of the photoresist pattern decreases from the center of the first array toward an edge of the first array.3. The method of claim 2 , wherein the photoresist patterns are defined by a plurality of photomask patterns arranged in a third array claim 2 , and a transparency of the photomask pattern increases from a center of the third array toward an edge of the same.4. The method of claim 3 , wherein each photomask pattern includes a transparent portion and an opaque portion claim 3 , and an area proportion of the transparent portion in the photomask pattern increases from the center of the third array toward the edge of the same.5. The method of claim 4 , wherein the transparent portion includes a plurality of transparent line regions.6. The method of claim 4 , wherein the transparent portion includes a plurality of transparent dot regions.7. The ...

GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME

A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure. 1. A method for fabricating a gate structure , comprising:providing a substrate;forming a gate dielectric layer on the substrate, comprising:depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas; andforming a gate on the gate dielectric layer.2. The method according to claim 1 , wherein the method of forming the gate dielectric layer comprises forming a silicon oxide layer on the substrate before depositing the silicon nitride layer.3. The method according to claim 2 , wherein the silicon nitride layer is thicker than the silicon oxide layer.4. The method according to claim 2 , further comprising performing a soft annealing process before depositing the silicon nitride layer but after forming the silicon oxide layer.5. The method according to claim 4 , wherein the soft annealing process is performed using the nitrogen-containing gas.6. The method according to claim 1 , further comprising performing a soft annealing process after depositing the silicon nitride layer but before forming the gate.7. The method according to claim 6 , wherein the soft annealing process is performed using the nitrogen-containing gas.8. The method according to claim 1 , further comprising performing a thermal annealing process after depositing the silicon nitride layer but before forming the gate.9. The method according to claim 8 , wherein the thermal annealing process is performed at a temperature of 600° C. to 800° C.10. The method according to claim 1 , wherein a process temperature for ...

MARK STRUCTURE AND METHOD FOR MEASURING ALIGNMENT ACCURACY BETWEEN FORMER LAYER AND LATTER LAYER

A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure. 1. A mark structure for measuring alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) , comprising:a plurality of divisions, each of which comprises a first region that comprises a plurality of parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer, whereinin each first region, all the parts have the same distance in a first direction between the pattern of the former layer and the pattern of the latter layer, andthe distance in the first direction is varied over the first regions of the divisions.2. The mark structure of claim 1 , wherein the divisions are arranged in a numeric order of the distance in the first direction.3. The mark structure of claim 1 , wherein the first direction is X- or Y-direction.4. The mark structure of claim 1 , wherein in each first region claim 1 , the patterns of the former layer and the patterns of the latter layer are arranged as in a product that is to be monitored using the mark structure.5. The mark structure of claim 1 , wherein the former layer comprises a layer of gates and the latter layer comprises a layer of contact plugs.6. The mark structure of claim 5 , wherein the contact plugs in the mark structure are disposed on a plurality of doped regions in a well of the same conductivity type.7. The mark structure of claim 6 , wherein the ...

FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF

A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced. 1. A manufacturing process of a fin field-effect transistor structure , the manufacturing process comprising steps of:providing a substrate;forming a fin channel on the substrate;forming a polysilicon pseudo gate layer on a surface of the fin channel;forming a polysilicon pseudo gate structure by defining the polysilicon pseudo gate layer;performing a first implantation process by using the polysilicon pseudo gate structure as a mask, so that a source/drain region is formed in the fin channel;successively forming a contact etch stop layer and a first dielectric layer over the fin channel having the source/drain region, the polysilicon pseudo gate structure and the substrate;performing a first planarization process on the substrate having the first dielectric layer and the contact etch stop layer until the polysilicon pseudo gate structure is exposed;removing the polysilicon pseudo gate structure to form a receiving space;successively forming a high-k dielectric layer and a metal gate layer on the substrate having the receiving space; andperforming a second planarization process on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k ...

Method and apparatus of electrical device characterization

A method of electrical device characterization comprises: providing an array of electrical devices arranged in rows and columns, wherein each electrical device has a first terminal, a second terminal and a third terminal; clamping a first voltage at a first terminal of a selected electrical device via a first buffer or an first external voltage source; clamping a second voltage at a second terminal of a selected electrical device via a second buffer or a second external voltage source; controlling a third buffer to couple the third terminal of the selected electrical device to a first terminal or a second terminal of at least one non-selected column of electrical devices; and deriving a characterization result via the third terminal of the selected electrical device; wherein the array of electrical devices, the first buffer, the second buffer and the third buffer are on a same die or a same module.

Method of unifying device performance within die

A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped.

Image sensor

An image sensor is disclosed. The image sensor includes a substrate, at least a color filter, and a microlens disposed on the color filter. The substrate includes a passivation layer thereon, and the color filter is disposed on the passivation layer, in which the color filter is truncated.

Backside-illuminated image sensor and fabricating method thereof

A backside-illuminated image sensor and a fabricating method thereof are provided. The fabricating method includes the following steps. Firstly, a first substrate having a first side and a second side is provided, wherein a sensing structure is formed on the first side of the first substrate, and the sensing structure includes an alignment mark. Then, a second substrate is provided and bonded to the first side of the first substrate. Then, a light-transmissible structure is formed on the second side of the first substrate at a location corresponding to the alignment mark. Afterwards, an optical structure is positioned on the second side of the first substrate by referring to the light-transmissible structure and the alignment mark.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening. 1. a method for fabricating a semiconductor device comprising:providing a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure;performing a chemical mechanical polishing (CMP) to planrizing the ILD layer and expose the ESL;conducting an in-situ etching process to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure; andfilling a metal material into the opening.2. The method for fabricating the semiconductor device according to claim 1 , wherein the ESL comprises silicon nitride or silicon oxynitride.3. The method for fabricating the semiconductor device according to claim 1 , wherein the in-situ etching process comprises:a first dry etching step for removing a portion of the ESL in order to expose the silicon layer; anda second dry etching step for removing the silicon layer.4. The method for fabricating the semiconductor device according to claim 3 , further comprising a wet chemical ...

METHOD FOR CREATING VIA IN IC MANUFACTURING PROCESS

In a method for creating a via in an IC manufacturing process, a substrate is provided and a circuitry structure is formed over the substrate. Then, a dielectric layer is formed over the circuitry structure; a hard mask is formed on and a trench is created through the dielectric layer; a coating layer is formed on the hard mask, filling the trench; an etch opening is defined in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; and the bottom of the trench exposed from the etch opening is etched off with the hard mask, thereby creating a via for conductors. 1. A method for creating a via in an IC manufacturing process , comprising steps of:providing a substrate formed thereon a circuitry structure, a dielectric layer and a hard mask, wherein the circuitry structure includes a conductor and an etch stop layer directly on the conductor;creating a trench in the dielectric layer without penetrating the entire dielectric layer;forming a coating layer on the hard mask, filling the trench;defining an etch opening in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; andcreating a via to expose the conductor by etching the dielectric layer and the etch stop layer exposed from the etch opening with the hard mask.2. The method according to wherein the substrate is a silicon substrate claim 1 , the dielectric layer is made of a composite material and configured as multiple layers or the dielectric layer is single-layered claim 1 , the hard mask is made of composite material and configured as multiple layers or the hard mask is single-layered claim 1 , and the coating layer includes a bottom anti-reflective layer and a photoresist layer.3. The method according to claim 1 , further comprising:removing the coating layer;forming a metal conductor on the hard mask, filling the via and the trench; andperforming a ...

Chemical mechanical polishing process

A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.

HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICE WITH LOW ON-STATE RESISTANCE

A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced. 1. A high voltage metal oxide semiconductor device , comprising:a substrate;a multi-segment first isolation structure formed in the substrate, and comprising plural segments;a source region and a drain region respectively arranged at bilateral sides of the multi-segment first isolation structure; anda gate structure disposed over at least a portion of the multi-segment first isolation structure.2. The high voltage metal oxide semiconductor device according to claim 1 , further comprising plural second isolation structures claim 1 , which are formed in the substrate.3. The high voltage metal oxide semiconductor device according to claim 2 , wherein the multi-segment first isolation structure and the plural second isolation structure are shallow trench isolation (STI) structures.4. The high voltage metal oxide semiconductor device according to claim 2 , wherein the aspect ratio of each segment of the multi-segment first isolation structure is greater than the aspect ratio of each of the second isolation structures.5. The high voltage metal oxide semiconductor device according to claim 2 , further comprising a first body region claim 2 , which is arranged between the source region and one of the plural second isolation structures.6. The high voltage metal oxide semiconductor device according to claim 2 , further comprising a second body region claim 2 , which is arranged under the gate structure and surrounds the source region.7. The high voltage metal oxide semiconductor device according ...

METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE AND OF METAL NITRIDE LAYER THEREOF

A method for manufacturing a metal nitride layer including the following steps is provided. Firstly, a substrate is provided. Then, a physical vapor deposition process is performed at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate. Also, the physical vapor deposition process can be performed on a pressure between 21 mTorr and 91 mTorr. The method can be used in the manufacturing process of an interconnection structure for decreasing the film stress of the metal nitride layer. Therefore, the interconnection structure can be prevented from line distortion and film collapse. 1. A method for manufacturing a metal nitride layer , comprising the following steps:providing a substrate; andperforming a physical vapor deposition process at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate.2. The method for manufacturing a metal nitride layer as claimed in claim 1 , wherein the physical vapor deposition process is performed on a pressure between 21 mTorr and 91 mTorr.3. The method for manufacturing a metal nitride layer as claimed in claim 1 , wherein the physical vapor deposition process comprises reactive sputtering.4. The method for manufacturing a metal nitride layer as claimed in claim 1 , wherein gases used in the physical vapor deposition process comprising argon and nitrogen.5. The method for manufacturing a metal nitride layer as claimed in claim 1 , wherein the material of a target used in the physical vapor deposition process comprising titanium.6. A method for manufacturing a metal nitride layer claim 1 , comprising the steps:providing a substrate; andperforming a physical vapor deposition process on a pressure between 21 mTorr and 91 mTorr to form a metal nitride layer on the substrate.7. The method for manufacturing a metal nitride layer as claimed in claim 6 , wherein the physical vapor deposition process comprises reactive sputtering.8. The method for manufacturing a metal nitride ...

GATE STACK STRUCTURE WITH ETCH STOP LAYER AND MANUFACTURING PROCESS THEREOF

A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer. 1. A gate stack structure with an etch stop layer , the gate stack structure being formed over a substrate , a spacer being formed on a sidewall of the gate stack structure , the gate stack structure comprising:a gate dielectric layer formed on the substrate;a barrier layer formed on the gate dielectric layer, wherein the barrier layer and an inner sidewall of the spacer collectively define a trench;a repair layer formed on the barrier layer and an inner wall of the trench; andthe etch stop layer formed on the repair layer.2. The gate stack structure according to claim 1 , wherein the gate dielectric layer has a dielectric constant greater than 4.3. The gate stack structure according to claim 1 , wherein the barrier layer is made of titanium nitride (TiN).4. The gate stack structure according to claim 1 , wherein the barrier layer has a thickness in the range between 15 angstroms and 25 angstroms.5. The gate stack structure according to claim 1 , wherein the repair layer is made of titanium nitride (TiN) or titanium (Ti).6. The gate stack structure according to claim 1 , wherein the repair layer has a thickness in the range between 7 angstroms and 15 angstroms.7. The gate stack structure according to claim 1 , wherein the etch stop layer is made of tantalum nitride (TaN).8. The gate stack structure according to claim 1 , wherein the etch stop layer has a ...

PICKUP DEVICE AND LITHOGRAPHY APPARATUS USING THE SAME

A pickup device disposed on a base includes a driving unit, a pickup arm, a control unit, a passive arm and a control line. The control unit is disposed on the pickup arm and electrically connects to the pickup arm for controlling that. The passive arm is connected with the pickup arm. The control line is electrically connected between the driving unit and the control unit and embedded in the passive arm. Therefore, the passive arm can protect the control line from damage by suffering external force. Further, the times of being bent to broken of the control line can be reduced to elongate the life thereof. A lithography apparatus using the pickup device is also provided. 1. A pickup device disposed on a base comprising:a driving unit;a pickup arm;a control unit disposed on the pickup arm and electrically connecting thereto;a passive arm connecting with the pickup arm; anda control line electrically connecting between the driving unit and the control unit and embedded in the passive arm.2. The pickup device as claimed in claim 1 , wherein the pickup arm comprises:a plurality of driving arms;a carrying arm connected with one of the driving arms; anda plurality of joints disposed between the driving arms connected with each other and between the carrying arm and the driving arm connected thereto.3. The pickup device as claimed in claim 1 , wherein the joints comprise pivots and sliding elements.4. The pickup device as claimed in claim 1 , wherein the passive arm comprises a first linking rod and a second linking rod claim 1 , the first linking rod connecting between the pickup arm and the second linking rod claim 1 , and the second linking rod connecting between the first linking rod and the base.5. The pickup device as claimed in claim 4 , wherein the second linking rod is pivoted between the base and the first linking rod.6. The pickup device as claimed in claim 1 , wherein the passive arm has a sliding portion claim 1 , the base has a guiding trough the sliding ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ENHANCED CHANNEL STRESS

A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.

METHOD FOR FORMING DAMASCENE TRENCH STRUCTURE AND APPLICATIONS THEREOF

A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence is firstly provided, in which a trench extends from the patterned hard mask downwards into the ILD. Subsequently, the patterned hard mask is etched in an atmosphere essentially consisting of nitrogen (N) and carbon-fluoride compositions (CF). 1. A method for fabricating a damascene trench structure comprising:providing a semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence, in which a trench extends from the patterned hard mask downwards into the ILD; andetching the patterned hard mask in an atmosphere essentially consisting of nitrogen (N2) and carbon-fluoride compositions (CxFy).2. The method according to claim 1 , wherein the atmosphere is a non-oxygen (O) atmosphere.3. The method according to claim 1 , wherein the atmosphere is a non-argon (Ar) atmosphere.4. The method according to claim 1 , wherein the atmosphere essentially consists of nitrogen (N) and carbonteraflouride (CF).5. The method according to claim 1 , wherein the atmosphere further comprises helium (He).6. The method according to claim 1 , wherein the step for providing the semiconductor structure further comprises:providing a substrate;forming a conducted layer on the substrate;forming a bottom layer on the conductive layer;forming the ILD on the bottom layer;forming a buffer layer on the ILD; andforming the patterned hard mask on the buffer layer to make the patterned hard mask having a trench opening exposing a portion of the buffer layer.7. The method according to claim 6 , wherein the step for providing the semiconductor structure further comprises:forming a photo-resist layer on the patterned hard mask so as to fill the trench opening;patterning the photo-resist layer to form a via opening aligning to the trench opening and ...

PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE

A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface. 1. A process for manufacturing a stress-providing structure in fabrication of a semiconductor device , the process comprising steps of:providing a substrate with a channel structure;forming a silicon nitride layer over the substrate by chemical vapor deposition in a halogen-containing environment;performing an etching process to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure;etching the exposed surface of the substrate to form a recess in the substrate;thermally treating the substrate at a temperature between 750° C. and 820° C. after the recess is formed in the substrate; andfilling a stress-providing material in the recess to form a stress-providing structure within the recess after the substrate is thermally treated.2. The process according to claim 1 , further comprising a step of forming a gate structure over the channel structure.3. The process according to claim 1 , wherein the halogen-containing environment is a chlorine-containing environment claim ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench. 1. A method of fabricating a semiconductor device , comprising:providing a substrate, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench;performing a first physical vapor deposition process to form a Ti-containing metal layer in the trench;performing a second physical vapor deposition process to form an Al layer on the Ti-containing metal layer in the trench;performing a thermal process to anneal the Ti-containing metal layer and the Al layer, so as to form a work function metal layer; andforming a metal layer to fill the trench.2. The method of fabricating the semiconductor device as claimed in claim 1 , wherein the second dielectric layer is formed before the first dielectric layer is formed or after the trench in the first dielectric layer is formed.3. The method of fabricating the semiconductor device as claimed in claim 1 , wherein the second dielectric layer comprises a high dielectric constant material.4. The method of fabricating the semiconductor device as claimed in claim 1 , wherein the Ti-containing metal layer comprises a TiAl layer or a Ti layer.5. ...

Double patterning mask set and method of forming thereof

A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.

Semiconductor device and method for fabricating the same

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Finfet transistor structure and method for making the same

A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

GATE STRUCTURE AND A METHOD FOR FORMING THE SAME

A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure. 1. A method for forming a gate structure , comprising:providing a substrate;forming a silicon oxide layer on the substrate;applying a decoupled plasma-nitridation process to the silicon oxide layer so as to form a silicon oxynitride layer;forming a first polysilicon layer on the silicon oxynitride layer;applying a thermal process to the silicon oxynitride layer having the first polysilicon layer; andforming a second polysilicon layer on the first polysilicon layer after the thermal process.2. The method as claimed in claim 1 , wherein the silicon oxide layer is formed on the substrate by using an in-situ steam generation method.3. The method as claimed in claim 1 , wherein a thickness of the silicon oxide layer is in a range from 10 angstroms to 20 angstroms.4. The method as claimed in claim 1 , wherein an operating pressure of the decoupled plasma-nitridation process is in a range from 5 millitorrs to 25 millitorrs.5. The semiconductor chip package structure as claimed in claim 1 , wherein a total operating time of the decoupled plasma-nitridation process is in a range from 70 seconds ...

Method for manufacturing semiconductor integrated circuit

A method for manufacturing a semiconductor integrated circuit includes providing a substrate having at least a metal hard mask formed thereon. Subsequently a patterning step is performed to the metal hard mask to form a patterned metal hard mask and followed by performing a H 2 O plasma treatment to the patterned metal hard mask.

PROCESS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE

A process for forming a shallow trench isolation structure is provided. Firstly, a semiconductor substrate is provided. Then, a hard mask is formed over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening. Then, a trench is formed in the semiconductor substrate according to the opening Then, a pull-back process is performed to treat the silicon nitride layer at a sidewall of the opening, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution. After the pull-back process is performed, an insulating material is filled in the trench, thereby forming the shallow trench isolation structure. 1. A process for forming a shallow trench isolation structure , the process comprising steps of:providing a semiconductor substrate;forming a hard mask over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening;defining a trench in the semiconductor substrate according to the opening;performing a pull-back process to treat the silicon nitride layer at a sidewall of the opening, thereby forming a bulge on the sidewall of the pad oxide layer, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution;performing a first pre-clean process so as to embellish the bulge; andfilling an insulating material in the trench after the first pre-clean process is performed, thereby forming the shallow trench isolation structure.2. The process for forming the shallow trench isolation structure according to claim 1 , wherein the semiconductor substrate is a silicon substrate claim 1 , and the insulating material is silicon oxide.3. The process for forming the shallow trench isolation structure according to claim 1 , wherein the wet etching process is carried out in the phosphoric acid solution at a temperature of 155° C. for an etching time of 30 seconds.4. The process for forming the shallow ...

STRESS FILM FORMING METHOD AND STRESS FILM STRUCTURE

A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film. 1. A stress film forming method for use in a fabrication process of a semiconductor device , the stress film forming method comprising steps of:providing a substrate, wherein a first-polarity-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second-polarity-channel MOSFET are formed on the substrate;performing at least one deposition-curing cycle process to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET; andperforming an additional deposition process to form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.2. The stress film forming method according to claim 1 , wherein the substrate is a silicon substrate claim 1 , and the cured stress film and the non-cured stress film are made of silicon nitride claim 1 , wherein the first-polarity-channel MOSFET is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) claim 1 , and the second-polarity-channel MOSFET is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).3. The stress film forming method according to claim 1 , wherein the deposition-curing processes are performed by steps of:performing a deposition process to form a stress film over the first-polarity-channel MOSFET and the second- ...

Pinhole inspection method of insulator layer

A pinhole inspection method of an insulator layer, wherein the pinhole inspection method comprises steps as following: A dry etching process is firstly performed to remove a contiguous layer adjacent to the insulator layer. Subsequently an etching endpoint is determined and the dry etching process is then stopped in accordance with a second electron energy variation triggered by the dry etching process. Afterward, a cross-sectional morphology or topography of the insulator layer is inspected.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

METHOD FOR FABRICATING HIGH VOLTAGE TRANSISTOR

A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor. 1. A method for fabricating a high voltage transistor , the method comprising steps of:providing a substrate;sequentially forming a first sacrificial oxide layer and a hard mask layer over the substrate;removing the hard mask layer, thereby exposing the first sacrificial oxide layer;forming a second sacrificial oxide layer on the first sacrificial oxide layer; andperforming an ion-implanting process to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor.2. The method according to claim 1 , wherein the substrate is a P-type silicon substrate claim 1 , the first sacrificial oxide layer is a pad oxide layer claim 1 , and the hard mask layer is a silicon nitride layer.3. The method according to claim 2 , wherein the step of removing the hard mask layer is performed by treating the silicon nitride layer with a hot phosphoric acid solution.4. The method according to claim 1 , wherein the step of forming the second sacrificial oxide layer is performed by a low-temperature deposition process.5. The method according to claim 4 , wherein the low-temperature deposition process is performed by carrying out a low-pressure tetraethylorthosilicate chemical vapor deposition to form a silicon ...

THROUGH-SILICON VIA FORMING METHOD

A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor. 1. A through-silicon via forming method , comprising steps of:providing a semiconductor substrate;forming a through-silicon via conductor in the semiconductor substrate, and allowing a topside of the through-silicon via conductor to be at the same level as a surface of the semiconductor substrate; andremoving a portion of the through-silicon via conductor, and allowing the topside of the through-silicon via conductor to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor;wherein the method is implemented by a via-first through-silicon via technology only or a via-middle through-silicon via technology only.2. The through-silicon via forming method according to claim 1 , wherein the step of allowing the topside of the through-silicon via conductor to be at the same level as the surface of the semiconductor substrate is performed by a chemical mechanical polishing process or an etching process.3. The through-silicon via forming method according to claim 1 , wherein the step of removing the portion of the through-silicon via conductor is performed by an etching process.4. The through-silicon via forming method according to claim 1 , wherein the through-silicon via conductor is made of copper claim 1 , tungsten claim 1 , polysilicon or molybdenum.5. (canceled)6. The through-silicon via forming method ...

POLY OPENING POLISH PROCESS

A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit. 1. A poly opening polish process , comprising: a substrate;', 'a gate disposed on the substrate; and', 'a dielectric layer disposed on the substrate and covering the gate;, 'providing a semi-finished semiconductor component comprisingapplying a first polishing process onto the dielectric layerapplying a second polishing process to the gate, the second polishing process utilizing a wetting solution comprising a water soluble polymer surfactant, an alkaline compound and water.2. The poly opening polish process as claimed in claim 1 , wherein the gate is a poly silicon gate.3. The poly opening polish process as claimed in claim 1 , wherein the first polishing process comprises a chemical mechanical polishing process.4. The poly opening polish process as claimed in claim 3 , wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer claim 3 , the first dielectric layer is disposed on the substrate and covers the gate claim 3 , the second dielectric layer is disposed on the first dielectric layer claim 3 , and applying the first polishing process onto the dielectric layer comprises applying a first chemical mechanical polishing process onto the second dielectric layer by using a first ...

PROCESS FOR FORMING REPAIR LAYER AND MOS TRANSISTOR HAVING REPAIR LAYER

A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer. 1. A repair layer forming process , comprising steps of:providing a substrate, and forming a gate structure on the substrate, wherein the gate structure at least comprises a gate dielectric layer and a gate conductor layer;performing a nitridation process to form a nitrogen-containing superficial layer on a sidewall of the gate structure;performing a thermal oxidation process to convert the nitrogen-containing superficial layer into a repair layer;forming a first spacer on a sidewall of the repair layer; andforming an additional spacer on a sidewall of the first spacer,wherein the first spacer is a silicon nitride layer with a thickness in a range of 50 angstroms to 100 angstroms, the additional spacer is a multi-layered structure comprising a silicon oxide layer with a thickness in a range of 25 angstroms to 75 angstroms and a silicon nitride layer with a thickness in a range of 200 angstroms to 400 angstroms.2. The repair layer forming process according to claim 1 , wherein the substrate is made of silicon claim 1 , the gate dielectric layer is made of silicon oxide claim 1 , silicon nitride or silicon oxynitride claim 1 , and the gate conductor ...

METHOD FOR FABRICATING METAL-OXIDE- SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed. 1. A method for fabricating a metal-oxide-semiconductor field-effect transistor , the method comprising steps of:providing a substrate, wherein a gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate, and the second spacer comprises an inner layer and an outer layer;thinning the second spacer, thereby retaining the inner layer of the pacer;forming a stress film on the inner layer of the second spacer and the source/drain structure, and then performing an annealing process; andremoving the stress film.2. The method according to claim 1 , wherein the substrate is a silicon substrate claim 1 , and the gate structure comprises a gate dielectric layer claim 1 , a barrier metal layer claim 1 , a polysilicon dummy gate and a hard mask layer claim 1 , wherein the first spacer is a silicon nitride layer or a multi-layered structure including a silicon dioxide layer and a silicon nitride layer claim 1 , the inner layer of the second spacer is made of silicon dioxide claim 1 , and the outer layer of the second spacer is made of silicon nitride.3. The method according to claim 2 , wherein the gate dielectric layer comprises an interlayer and a high-K dielectric layer claim 2 , and the hard mask layer comprises a silicon nitride layer and a silicon dioxide layer claim 2 , wherein the high-K dielectric layer ...

Gate dielectric layer forming method

A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.

Fabricating method of mos transistor, fin field-effect transistor and fabrication method thereof

A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM

In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation. 1. A hidden refresh method for a pseudo SRAM , comprising:receiving a system clock signal, wherein a duty-on period of the system clock signal is adapted for performing a data access operation;generating a refresh clock signal subjected to the control of the system clock signal, wherein a duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal; andtriggering a refresh control pulse by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.2. The hidden refresh method as claimed in claim 1 , further comprising:triggering a sense amplifier enable pulse by a starting edge of the refresh control pulse to activate a sense amplifier, for performing the refresh operation.3. The hidden refresh method as claimed in claim 1 , wherein the ending edge of the refresh control pulse is prior to the ending edge of the sense amplifier enable pulse.4. An operating method for a pseudo SRAM claim 1 , comprising:activating a first word line subjected to the control of a system clock signal cooperative with a data access enable signal to perform a data access operation;generating a refresh clock pulse non-overlapping with any clock pulse of the system clock signal, immediately following the data access operation;triggering a first refresh control pulse by a starting edge of the refresh ...

METHOD FOR FORMING CONTACT HOLES

In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer. 1. A method for forming contact holes , comprising:providing a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order;performing a first etching process to form at least a first contact opening in the interlayer dielectric layer;forming a first carbon-containing dielectric layer overlying the interlayer dielectric layer and filling into the first contact opening;forming a first anti-reflective layer and a first patterned photo resist layer in that order overlying the first carbon-containing dielectric layer; andperforming a second etching process by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.2. The method as claimed in claim 1 , wherein the formations of the first anti-reflective layer and the first patterned photo resist layer comprises a photo resist rework step.3. The method as claimed in claim 1 , wherein the formation of the first anti-reflective layer comprises:forming a first bottom anti-reflective coating overlying the carbon-containing dielectric layer; andforming a first dielectric anti-reflective coating overlying the first bottom anti- ...

INTEGRATED CIRCUIT MODULE AND MANUFACTURING METHODS AND APPLICATION THEREOF

An exemplary integrated circuit module includes a first transistor and a second transistor. The first transistor has a first channel length and a first threshold voltage. The second transistor is electrically coupled to the first transistor and has a second channel length and a second threshold voltage. The second channel length is greater than the first channel length, the absolute value of the second threshold voltage is smaller than the absolute value of the first threshold voltage, and the first transistor and the second transistor have a same threshold voltage implant concentration. Moreover, a manufacturing method of such integrated circuit module, and an application of such integrated circuit module to computer aided design of logic circuit also are provided. 1. An integrated circuit module comprising:a first transistor, having a first channel length and a first threshold voltage; and 'wherein the second channel length is greater than the first channel length, the absolute value of the second threshold voltage is smaller than the absolute value of the first threshold voltage, and the first transistor and the second transistor have a same threshold voltage implant concentration.', 'a second transistor, electrically coupled to the first transistor, having a second channel length and a second threshold voltage,'}2. The integrated circuit module as claimed in claim 1 , wherein a source of the second transistor is grounded.3. The integrated circuit module as claimed in claim 1 , wherein the integrated circuit module is operated in sub-threshold region.4. The integrated circuit module as claimed in claim 3 , wherein the integrated circuit module has an operation voltage of no more than about 0.5V.5. The integrated circuit module as claimed in claim 1 , wherein the integrated circuit module has an operation voltage higher than claim 1 , lower than or fall in the range of 0.9V˜1.2V.6. The integrated circuit module as claimed in claim 1 , wherein the second channel ...

BEAM LINE SYSTEM OF ION IMPLANTER

A beam line system includes a hollow tube and a plurality of protruding structures. The hollow tube has an inlet and an outlet. An ion beam emitted by the ion implanter is introduced into the hollow tube through the inlet and exited from the hollow tube through the outlet. The protruding structures are formed on an inner wall of the hollow tube. Each of the protruding structures has a reflective surface for reflecting a portion of the ion beam. 1. A beam line system of an ion implanter , the beam line system comprising:a hollow tube having an inlet and an outlet, wherein an ion beam emitted by the ion implanter is introduced into the hollow tube through the inlet and exited from the hollow tube through the outlet; anda plurality of protruding structures formed on an inner wall of the hollow tube, wherein each of the protruding structures has a reflective surface for reflecting a portion of the ion beam.2. The beam line system according to claim 1 , wherein the hollow tube is a collimator tube.3. The beam line system according to claim 1 , wherein the hollow tube is made of graphite.4. The beam line system according to claim 1 , wherein the protruding structures are contiguous wedge-shaped structures on the inner wall of the hollow tube.5. The beam line system according to claim 1 , wherein the reflective surface of the protruding structure is substantially vertical to a traveling direction of the ion beam.6. The beam line system according to claim 1 , wherein a ratio of a height of the reflective surface of the protruding structure to a length of the protruding structure along a traveling direction of the ion beam is about 1:5.7. The beam line system according to claim 1 , wherein the portion of the ion beam which is not reflected by the protruding structures is exited from the outlet of the hollow tube.8. The beam line system according to claim 7 , wherein an end analyzer is positioned at a terminal of the beam line system to detect the portion of the ion beam ...

Test pad structure on wafer

A test pad structure on a wafer includes at least a scribe line positioned on a wafer, a pad region defined in the scribe line, and a metal pad positioned in the pad region. An area of the metal pad and an area of the pad region include a ratio, and the ratio is lower than equal to 50%.

OPTICAL MICRO STRUCTURE, METHOD FOR FABRICATING THE SAME AND APPLICATIONS THEREOF

An image sensor comprises a plurality of color filtering elements, a plurality of lenses and an image sensing device, wherein the lenses are correspondingly formed over the color filtering elements, and the image sensing device having a sensing area engaged with the color filtering elements. 1. An image sensor , comprising:a plurality of color filtering elements;a plurality of lenses correspondingly formed over the color filtering elements; andan image sensing device having a sensing area engaged with the color filtering elements.2. The image sensor of claim 1 , wherein the color filtering elements are buried in a dielectric layer of the sensing area and with a deepness extending beyond a bottom metal which is disposed in the dielectric layer and adjacent to the sensing area.3. The image sensor of claim 1 , further comprising a planarization layer disposed between the plurality of lenses and the plurality of color filtering elements.4. The image sensor of claim 1 , wherein the color filtering elements are contiguously disposed on a backside of the image sensing device.5. The image sensor of claim 1 , wherein the image sensor has a wafer-scale structure which can be cut into a plurality of image sensing chips.6. The image sensor of claim 1 , further comprising:a working substrate; anda transparent substrate disposed on the working substrate, wherein the transparent substrate has a plurality of recesses allowing the lenses correspondingly embedded in the recesses.7. The image sensor of claim 1 , wherein the image sensor further comprises a passive layer disposed on the transparent substrate opposite to the lenses.8. A method for fabricating an image sensor claim 1 , comprising:forming a transparent substrate on a working substrate;forming pluralities of micro lens in the transparent substrate, wherein the lenses have a refraction ratio differing from that of the transparent substrate;forming a color filter on the lenses; andengaging the color filter with an image ...

METHOD FOR MANUFACTURING THROUGH-SILICON VIA

A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current. 1. A method for manufacturing a through-silicon via (TSV) , the method comprising:providing a stack structure having a substrate and an internal layer dielectric (ILD) layer, wherein an opening is formed in the stack structure penetrating through the ILD layer and further extending into the substrate;providing a insulator layer and a metal barrier layer sequentially formed on the stack structure and the sidewalls of the opening;providing a top metal layer formed on the stack structure and filling the opening;conducting a first planarization process stopping on the metal barrier layer to remove a portion of the top metal layer, andconducting a second planarization process stopping on the ILD layer to remove portions of the top metal layer, the metal barrier layer and the insulator layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.2. The method of claim 1 , wherein the first planarization process comprises a chemical mechanical polishing (CMP) process having a polishing rate ...

CLEANING METHOD OF SEMICONDUCTOR MANUFACTURING PROCESS

A cleaning method of a semiconductor manufacturing process is provided. The cleaning method is applied to a semiconductor component including a plurality of material layers formed thereon. An opening is defined in the material layers, and a side wall is exposed from the opening The side wall at least includes a first material layer and a second material layer. At first, a first cleaning process is performed till a lateral etched thickness of the first material layer is equal to a lateral etched thickness of the second material layer. Then, a byproduct formed in the first cleaning process is removed.

SUSPENDED BEAM FOR USE IN MEMS DEVICE

A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body. 1. A suspended beam , comprising:a substrate;a main body, wherein a first end of the main body is fixed onto the substrate, and a second end of the main body is suspended; anda first metal line structure embedded in the main body, wherein the width of the first metal line structure is smaller than the width of the main body.2. The suspended beam according to claim 1 , wherein the substrate is a silicon substrate.3. The suspended beam according to claim 1 , wherein the main body is constituted by a dielectric layer or a multi-layered structure including two or more dielectric layers.4. The suspended beam according to claim 3 , wherein the dielectric layer is made of silicon oxide.5. The suspended beam according to claim 1 , wherein the first metal line structure is partially embedded in a top surface of the main body and exposed outside the main body.6. The suspended beam according to claim 1 , wherein the first metal line structure is embedded in a periphery of a top surface of the main body and exposed outside the main body.7. The suspended beam according to claim 1 , wherein the first metal line structure is embedded within the main body and not exposed to the main body.8. The suspended beam according to claim 1 , further comprising a second metal line structure claim 1 , wherein the second metal line structure is embedded in the main body claim 1 , and electrically connected with the first metal line structure through at least one contact hole conductor.9. A circuit chip claim 1 , comprising:a substrate;an integrated circuit device formed over the substrate, and comprising a multi-layered structure; and a main body, wherein a first ...

FABRICATING METHOD OF SEMICONDUCTOR DEVICE

A fabricating method of a semiconductor device includes the following actions. A substrate having a silicon gate structure formed thereon is provided, and then a modification process is performed on a surface of the silicon gate structure to render the surface from being hydrophobic to be hydrophilic. After that, a mask is formed on the substrate. In succession, a dopant implantation process is performed using the silicon gate structure after the modification process and the mask. After the dopant implantation process, a cleaning process which includes a wet cleaning process is performed to remove the mask. In the above fabricating method, because the surface of the silicon gate structure is modified into a hydrophilic surface, therefore it is easy to remove the residues after the dopant implantation process using the wet cleaning process. 1. A fabricating method of a semiconductor device , comprising:providing a substrate having a silicon gate structure formed thereon;performing a modification process on a surface of the silicon gate structure to render the surface from being hydrophobic to be hydrophilic;forming a mask on the substrate;performing a dopant implantation process using the silicon gate structure after the modification process and the mask; andperforming a cleaning process, which includes a wet cleaning process, to remove the mask.2. The fabricating method of a semiconductor device as claimed in claim 1 , wherein the substrate is a silicon substrate claim 1 , the substrate has a shallow trench isolation structure formed thereon claim 1 , and a gate insulator layer is formed between the silicon gate structure and the silicon substrate.3. The fabricating method of a semiconductor device as claimed in claim 1 , wherein the modification process comprises:processing the silicon gate structure with a oxidation process; andforming a silicon oxide layer on a surface of the silicon gate structure, wherein a thickness of the silicon oxide layer is less than 20 ...

MANUFACTURING METHOD AND STRUCTURE OF NON-VOLATILE MEMORY

A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer. 1. A method for manufacturing a non-volatile memory , comprising:providing a substrate formed thereon a poly gate structure;forming a contact etching stop layer over the poly gate structure, which includes at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; andforming an inter-layer dielectric layer over the contact etching stop layer;wherein the first silicon oxide layer is disposed adjacent to the inter-layer dielectric layer and has a density higher than that of the inter-layer dielectric layer.2. The method according to claim 1 , wherein the poly gate structure includes at least one polysilicon conductor.3. The method according to claim 2 , wherein the poly gate structure is formed by:forming a dielectric layer on the substrate;forming the polysilicon conductor on the dielectric layer;forming a sidewall structure around the polysilicon conductor; andforming a metal silicide on the polysilicon conductor.4. The method according to claim 1 , wherein the contact etching stop layer is formed by:forming a second silicon oxide layer over the poly gate structure;forming the silicon nitride layer on the second silicon oxide layer; andforming the first silicon oxide layer on the silicon nitride layer.5. The method according to claim 1 , wherein the first silicon oxide layer is formed of tetraethyl orthosilicate by plasma enhanced chemical vapor deposition to a thickness ranged between 300 and 2000 angstroms.6. The method according to claim 1 , wherein the inter-layer ...

METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. 1. A method for manufacturing a MOS transistor , comprising:forming a substrate, the substrate defining a first transistor region and a second transistor region and having a first opening and a second opening formed by removing a dummy gate, the substrate comprising a high-k dielectric layer and a barrier on the high-k dielectric layer in each of the first opening and the second opening;forming a dielectric barrier layer on the substrate to fill into the first opening and the second opening and to cover the barrier layers;removing a portion of the dielectric barrier layer in the first transistor region so as to expose the barrier layer in the first opening;forming a first work function metal layer on the substrate after removing the portion of the dielectric barrier layer in the first transistor region to fill into the first opening and the second opening;removing the first work function metal layer in the second transistor region;removing a portion of the dielectric barrier layer in the second transistor region so as to expose the barrier layer in the second opening; andforming a second work function metal layer ...

EMBEDDED CAPACITOR STRUCTURE AND THE FORMING METHOD THEREOF

A method for forming an embedded capacitor structure is provided. Firstly, a first dielectric layer having a trench therein on a substrate is provided. A capacitor structure is formed on the bottom surface of the trench. The capacitor structure includes a first metal layer, a capacitance-insulating layer and a second metal layer and the portion surface of the first metal layer on the bottom surface of the trench is exposed. A cap layer is formed on the top surface and the inner surface of the trench and on the capacitor structure. A second dielectric layer is formed on the cap layer. The portion of second dielectric layer and the portion of the cap layer are removed to form a plurality of contact windows therein, and the portion surface of the first metal layer and the portion surface of the second metal layer are exposed by the plurality of contact windows. 1. A method for forming an embedded capacitor , comprising steps of:providing a first dielectric layer having a trench therein on a substrate;forming a capacitor structure on a bottom surface of the trench, the capacitor structure comprises a first metal layer, a capacitance-insulating layer and a second metal layer, and the portion surface of the first metal layer on the bottom surface in the trench is exposed;forming a cap layer on a top surface and an inner surface of the trench, and on the capacitor structure;forming a second dielectric layer on the cap layer; andremoving the portion of second dielectric layer and the portion of cap layer to form a plurality of contact windows, the portion surface of the first metal layer and the portion surface of second metal layer are exposed by the plurality of contact windows.2. The method according to claim 1 , wherein the material of the first dielectric layer is made of silicon dioxide (SiO) or Fluorinated Silica Glass (FSG).3. The method according to claim 1 , wherein the forming capacitor structure comprising:forming the first metal layer on the top surface, the ...

METHOD FOR FABRICATING INTEGRATED CIRCUIT

A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed. 1. A method for fabricating an integrated circuit , comprising:providing a conductive substrate with a logical circuit region and a MEMS region;forming a first interconnect structure comprising a plurality of first dielectric layers and a plurality of first conductive patterns on the MEMS region of the conductive substrate, the first dielectric layers and the first conductive patterns alternately stacked on the MEMS region of the conductive substrate;forming an interlayer to cover the first conductive patterns on the first interconnect structure;forming a poly-Si mask layer corresponding to the first conductive patterns and exposing a portion of the interlayer on the interlayer;removing the portion of the interlayer exposed by the poly-Si mask layer and corresponding portions of the first dielectric layers through using the poly-Si mask layer as a mask for forming a plurality of openings within the first interconnect structure; and removing a portion of the conductive substrate in the MEMS region.2. The method as claimed in claim 1 , further comprises the step of forming a plurality of shallow trench isolations in the conductive substrate.3. The method as claimed in claim 2 , wherein the ...

Manufacturing method for metal gate

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Method for fabricating semiconductor device by using stress memorization technique

A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.

SONOS NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF

A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening. 1. A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell comprising:forming a pad oxide layer and a first hard mask layer sequentially stacked on a substrate;etching through the pad oxide layer and the first hard mask layer so as to form an opening exposing a portion of the substrate; andforming an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening to coincide with the portion of the substrate exposed by the opening.2. The method for fabricating the SONOS non-volatile memory cell according to claim 1 , wherein the first hard mask layer is a nitride layer.3. The method for fabricating the SONOS non-volatile memory cell according to claim 1 , wherein the first hard mask layer has a thickness substantially greater than that of the ONO structure.4. The method for fabricating the SONOS non-volatile memory cell according to claim 3 , wherein the thickness of the first hard mask layer ranges from 450 Å to 600 Å.5. The method for fabricating the SONOS non-volatile memory cell according to claim 1 , wherein the formation of the opening comprises following steps:etching through the first hard mask layer, to expose a portion of the pad oxide;performing an ion implant process on the exposed pad oxide; andremoving the exposed pad oxide layer to expose the substrate.6. The method for fabricating the SONOS non-volatile memory cell according to claim ...

CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE

A conductor contact structure includes a conductor line, a dielectric layer and a contact hole. The conductor line includes a first zone and a second zone. The first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis. The second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis. A distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis. A contact hole is formed in the dielectric layer and in communication with the second zone. A diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone. 1. A conductor contact structure , comprising:a conductor line comprising a first zone and a second zone, which are connected with each other, wherein the first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis, and the second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis, wherein a distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis;a dielectric layer formed over the conductor line; anda contact hole formed in the dielectric layer and in communication with the second zone, wherein a diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone.2. The conductor contact structure according to claim 1 , wherein a first side of the second zone further comprises an enlarged portion claim 1 , wherein a border of the enlarged portion is the first edge of the second zone.3. The conductor contact structure according to claim 2 , wherein the second edge of the second zone is close to a nearby conductor line claim 2 , wherein a spacing interval between the second edge of the second zone and the nearby ...

CHARGE PUMP

A charge pump includes a first current source unit and a second current source unit. The first current source unit is connected between a first voltage terminal and the control node. The second current source unit is connected between the control node and a second voltage terminal. According to a phase comparing signal, the first current source unit provides a first switching current to the control node. The second current source unit includes a first sub-switching current generator, a second sub-switching current generator and a select circuit. According to a voltage level of the phase comparing signal, the first sub-switching current generator generates a first sub-switching current. According to the voltage level of the phase comparing signal, the second sub-switching current generator generates a second sub-switching current. By the select circuit, the first sub-switching current or the second sub-switching current is provided to the control node. 1. A charge pump for providing a current to a control node according to a phase comparing signal , the charge pump comprising:a first current source unit, electrically connected between a first voltage terminal and the control node, wherein the first current source unit provides a first switching current to the control node according to the phase comparing signal; and a first sub-switching current generator, electrically connected to the control node and the second voltage terminal, wherein the first sub-switching current generator generates a first sub-switching current according to the phase comparing signal;', 'a second sub-switching current generator electrically connected to the control node and the second voltage terminal, wherein the second sub-switching current generator generates a second sub-switching current according to the phase comparing signal; and', 'a select circuit electrically connected to the first sub-switching current generator and the second sub-switching current generator, wherein according to a ...

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch. 1. An electrostatic discharge protection circuit located between a first voltage terminal and a second voltage terminal , the electrostatic discharge protection circuit comprising:a first semiconductor switch electrically connected to the first voltage terminal, wherein if a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch; anda second semiconductor switch electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.2. The electrostatic discharge protection circuit according to claim 1 , wherein the first semiconductor switch is a first transistor claim 1 , and the second semiconductor switch is a second transistor claim 1 , wherein a first terminal and a second terminal of the first transistor are respectively connected to the first voltage ...

METHOD OF FORMING TRENCH ISOLATION

A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure. 1. A method of forming trench isolation of a semiconductor device , comprising:providing a semiconductor substrate formed thereon a first mask layer;performing a first etching process with the first mask layer as an etching mask to form a shallow trench structure;applying a first dielectric material to fill the shallow trench structure while forming a first dielectric layer on the semiconductor substrate;patterning the first dielectric layer to form a second mask layer;performing a second etching process with the second mask layer as an etching mask to form a deep trench structure; andapplying a second dielectric material to fill the deep trench structure.2. The method as claimed in claim 1 , further comprising forming a second dielectric layer on the semiconductor substrate while filling the deep trench structure with the dielectric material.3. The method as claimed in further comprising performing a chemical mechanical polishing (CMP) process for planarization.4. The method as claimed in wherein the shallow trench structure is formed in an area of the semiconductor substrate corresponding to a logic region and the deep trench structure is formed in another area of the semiconductor substrate corresponding to a pixel region.5. The method as claimed in wherein the deep trench structure is configured to isolate sensor devices in the ...

Trench-gate metal oxide semiconductor device and fabricating method thereof

A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

A fabricating method of semiconductor structure is provided. First, a substrate with a dielectric layer formed thereon is provided. The dielectric layer has a first opening and a second opening exposing a portion of the substrate. Further, a gate dielectric layer including a high-k dielectric layer and a barrier layer stacked thereon had been formed on the bottoms of the first opening and the second opening. Next, a sacrificial layer is formed on the portion of the gate dielectric layer within the second opening. Next, a first work function metal layer is formed to cover the portion of the gate dielectric layer within the first opening and the sacrificial layer. Then, the portion of the first work function metal layer and the sacrificial layer within the second opening are removed. 1. A fabricating method of semiconductor structure , comprising the steps of:providing a substrate with a dielectric layer and a gate dielectric layer formed thereon, and a plurality of first doped regions and a plurality of second doped regions formed therein, wherein the dielectric layer has a first opening and a second opening exposing a portion of the substrate, the first doped regions are respectively formed in the substrate at two sides of the first opening and the second doped regions are respectively formed in the substrate at two sides of the second opening, the gate dielectric layer comprising a high-k dielectric layer and a barrier layer sequentially stacked on bottoms of the first opening and the second opening;forming a sacrificial layer on a portion of the gate dielectric layer within the second opening;forming a first work function metal layer on a portion of the gate dielectric layer within the first opening and the sacrificial layer; andremoving the first work function metal layer and the sacrificial layer within the second opening.2. The method recited in claim 1 , further comprises the step of forming a second work function metal layer on the portion of the gate ...

Probe Calibration Device and Calibration Method

A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.