Method for fabricating metal-oxide semiconductor transistors

A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

MANUFACTURING METHOD FOR METAL GATE

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

RAPID THERMAL PROCESS METHOD AND RAPID THERMAL PROCESS DEVICE

A rapid thermal process method contains providing a substrate, performing a pre-heating process to at least a first portion of the substrate by means of a first laser beam, and performing a rapid heating process to the pre-heated first portion of the substrate by means of a second laser beam.

Method for fabricating metal-oxide semiconductor transistors

A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle. 1. A manufacturing method of semiconductor device , comprising:providing a semiconductor substrate;performing a first annealing process on the semiconductor substrate by emitting a first laser along a first scanning direction; andperforming a second annealing process on the semiconductor substrate by emitting a second laser along a second scanning direction, wherein the first scanning direction and the second scanning direction have an incident angle.2. The manufacturing method of semiconductor device according to claim 1 , wherein the first laser scans along a plurality of first scanning paths.3. The manufacturing method of semiconductor device according to claim 1 , wherein the second laser scans along a plurality of second scanning paths.4. The manufacturing method of semiconductor device according to claim 2 , wherein the first scanning paths have edges arranged with an arc shape claim 2 , such that the area covered by all of the first scanning paths completely overlaps the surface area of the semiconductor substrate.5. The manufacturing method of semiconductor device according to claim 3 , wherein the second scanning paths have edges arranged with an arc shape claim 3 , such that the area covered by all of the second scanning paths completely overlaps the surface area of the semiconductor substrate.6. The manufacturing method of semiconductor device according to claim 1 , wherein the first annealing process has a first temperature claim 1 , the second annealing ...

Method of forming FinFET device

A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

P-type field effect transistor and method for fabricating the same

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Lower dose rate ion implantation using a wider ion beam

In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece.

Rapid thermal process method and rapid thermal process device

A rapid thermal process method contains providing a substrate, performing a pre-heating process to at least a first portion of the substrate by means of a first laser beam, and performing a rapid heating process to the first portion of the substrate by means of a second laser beam.

Forming punch-through stopper regions in finfet devices

Methods for using isotopically enriched levels of dopant gas compositions in an ion implantation process

A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified ...

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING STRESS MEMORIZATION TECHNIQUE

A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.

Method for fabricating semiconductor device by using stress memorization technique

一種利用應力記憶技術之半導體元件製造方法，半導體元件製造方法包含下列步驟：提供一基板，基板上方已形成一閘極結構；利用閘極結構為一遮罩來對基板進行一前非晶化佈植製程，而於基板中一預定區域形成一非晶化區域，其中基板的溫度受控制而低於常溫；於閘極結構與非晶化區域表面上形成一應力層；對完成有應力層之基板進行一熱處理，使基板中之非晶化區域重新結晶；以及去除應力層。

P-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion. 1. A p-type field effect transistor (pFET) , comprising:a gate structure on a substrate;a channel region in the substrate directly under the gate structure, wherein the channel region comprises a top portion and a bottom portion; anda source/drain region adjacent to two sides of the gate structure.2. The p-type field effect transistor of claim 1 , wherein a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion.3. The p-type field effect transistor of claim 1 , wherein a depth of the top portion is equal to a depth of the bottom portion. This application is a division of U.S. application Ser. No. 15/893,681 filed Feb. 11, 2018, and incorporated herein by reference in its entirety.The invention relates to a method for fabricating metal-oxide-semiconductor (MOS) transistor, and more particularly to a method of using ion implantation process to form channel layer in a substrate.In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode ...

Method of fabricating an NMOS transistor

A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Semiconductor structure and method for making the same

A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess.

Thermal process

A thermal process is disclosed. The thermal process preferably includes the steps of: providing a semiconductor substrate ready to be heated; and utilizing at least a first heating beam and a second heating beam with different energy to heat the semiconductor substrate simultaneously. Accordingly, the present invention no only eliminates the need of switching between two different thermal processing equipments and shortens the overall fabrication cycle time, but also improves the pattern effect caused by the conventional front side heating.

P-type field effect transistor and method for fabricating the same

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure

A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

Semiconductor process

A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Forming punch-through stopper regions in finFET devices

In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Method for fabricating MOS transistors

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided. A spacer is formed surrounding the gate structure and an ion implantation process is performed to implant a molecular cluster containing boron in to the semiconductor substrate for forming a source / drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. A millisecond annealing process is performed thereafter to activate the molecular cluster within the source / drain region.

SEMICONDUCTOR STRUCTURE WITH DOPED FIN-SHAPED STRUCTURES AND METHOD OF FABRICATING THE SAME

A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Multi-tilt angles and multi-twist angles ion implantation processes

本發明提出的離子佈植製程係於離子佈植室中承載晶圓，並於晶圓維持於離子佈植室的期間，依照一且唯一事先載入的程式，或依照包含多數組製程參數的一程式，或調整掃描參數或調整離子束，或調整晶圓的不同傾斜角度或不同旋轉角度，藉以依序以不同掃描參數或不同調整過離子束或不同晶圓傾斜角度或不同晶圓旋轉角度來佈植晶圓。

Applications of low density ion implantation

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME

A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess. 1. A semiconductor structure , comprising:a substrate;a gate structure disposed on said substrate;a source disposed in said substrate and adjacent to said gate structure; and a recess disposed in said substrate;', 'a non-doped epitaxial layer disposed on the inner surface of said recess and substantially consisting of Si and an epitaxial material, said non-doped epitaxial layer having a sidewall and a bottom which together cover the inner surface, wherein the bottom thickness is not greater than 120% of the sidewall thickness; and', 'a doped epitaxial layer comprising Si, said epitaxial material and a dopant and filling said recess, where said doped epitaxial layer does not contact said substrate at all due to the presence of said non-doped epitaxial layer., 'a drain disposed in said substrate and adjacent to said gate structure, wherein at least one of said source and said drain comprises;'}2. The semiconductor structure of claim 1 , wherein a ratio of the bottom thickness to the sidewall thickness is between 0.83 and 1.20.3. The semiconductor structure of claim 1 , wherein a doping concentration of said doped epitaxial layer is at least 100 times greater than that of said non-doped epitaxial layer.4. The semiconductor structure of claim 1 , wherein the surface of said doped epitaxial layer is higher than that of said substrate.5. The semiconductor structure of claim 1 , wherein said substrate comprises Si.6. The semiconductor structure of claim 1 , ...

Manufacturing method for metal gate

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Method of fabricating an NMOS transistor

A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.

Semiconductor process

一種半導體製程，首先提供包含凹穴之基材。其次，在基材中形成嵌入矽鍺層。此嵌入矽鍺層包含填滿凹穴之矽鍺磊晶材料。然後，對於嵌入矽鍺層進行一預非晶化摻雜步驟，而形成一非晶化區域。繼續，對於嵌入矽鍺層進行源極/汲極摻雜步驟，而形成源極摻雜區與汲極摻雜區。再來，進行一源極/汲極退火步驟，而在基材中形成源極與汲極。此預非晶化摻雜步驟與源極/汲極摻雜步驟其中之至少一者，係在低於零下30度之低溫下進行。

PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE

A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

Rapid thermal process method and rapid thermal process device

A rapid thermal process method contains providing a substrate, performing a pre-heating process to at least a first portion of the substrate by means of a first laser beam, and performing a rapid heating process to the pre-heated first portion of the substrate by means of a second laser beam.

METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTORS

A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

FORMING PUNCH-THROUGH STOPPER REGIONS IN FINFET DEVICES

In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device. 1. A method for forming a punch-through stopper region in a fin field effect transistor (finFET) device , the method comprising:etching a substrate to form a pair of trenches, the pair of trenches defining a fin structure, wherein a cap layer is disposed on a top surface of the fin structure;implanting a first dose of ions such that a portion of the first dose of ions is implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions in the substrate, wherein each first dopant region extends at least partially under a channel region of the fin structure; andetching the substrate at the bottom wall of each trench to increase a depth of each trench, wherein etching the substrate at the bottom wall of each trench removes a portion of each first dopant region under each trench, and wherein a remaining portion of the pair of first dopant regions under the fin structure at least partially defines the punch-through stopper region; and wherein the pair of first dopant regions is not subjected to a thermal anneal process after implanting the first dose of ions and prior to etching the substrate at the bottom wall of each trench.2. (canceled)3. The method of claim 1 , ...

Multifunctional tracheostomy sounder

FinFET device and method of forming the same

A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

Applications of low density ion implantation

To enhance the performance of some semiconductor structures and some semiconductor processes, it is preferable to focus the distribution of implanted ions (i.e., the dopant profile) close to the surface of these semiconductor structures or the workpiece. That is to say, the precise material modification (PMM) may be achieved if the depth of the dopant profile may be precisely and flexibly adjusted, wherein some examples of the PMM are the formation of the ultra-shallow junction and the fin structure and the adjustment of the non-uniform ion implantation. The invention uses the low density ion implantation to reduce the depth of the dopant profile. To compare with the conventional skills that reduce the ion beam energy for reducing the depth of the dopant profile, the invention may avoid some difficulties induced by the generation and transportation of the low energy ion beam.

Forming punch-through stopper regions in finFET devices

In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Method for manufacturing fins

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

Method for fabricating metal-oxide semiconductor transistors

A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTORS

A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

THERMAL PROCESS

A thermal process is disclosed. The thermal process preferably includes the steps of: providing a semiconductor substrate ready to be heated; and utilizing at least a first heating beam and a second heating beam with different energy density to heat the semiconductor substrate simultaneously. Accordingly, the present invention no only eliminates the need of switching between two different thermal processing equipments and shortens the overall fabrication cycle time, but also improves the pattern effect caused by the conventional front side heating.

THERMAL PROCESSING METHOD

A thermal processing method is provided. First, a semiconductor substrate is provided. The semiconductor substrate has a metal-oxide-semiconductor transistor formed thereon. The metal-oxide-semiconductor transistor includes a gate and source and drain regions on two sides of the gate. Dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate. Next, a first thermal process is performed, and then a second thermal process is performed. Next, the cap layer is removed. The thermal processing method is capable of uniformly heating a semiconductor substrate and reducing the pattern effect in the fabrication of a CMOS and to improve the performance of the CMOS.

Semiconductor process

First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below 30° C.

Method for ion implantation

A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam.

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. The manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

Image sensor and formation method thereof

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region having a first doping type. A deep well region is disposed within the semiconductor substrate, where the deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a first dopant having a second doping type opposite the first doping type, where the first dopant comprises gallium.

METHOD OF FORMING FINFET DEVICE

A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%. 1. A method of forming a FinFET device , comprising:providing a substrate, wherein the substrate has a first region and a second region;forming first fins and second fins on the substrate respectively in the first region and the second region, wherein a number of the first fins is different from a number of the second fins;forming a first dummy gate and a second dummy gate respectively across the first fins and the second fins;forming a first spacer and a second spacer sequentially on a sidewall of each of the first fins and the second fins;partially removing the first fins and the second fins, so as to form first recesses in the first fins aside the first dummy gate and form second recesses in the second fins aside the second dummy gate;performing an oxidizing step to the first spacers and the second spacers;removing upper portions of the first spacers and the second spacers;forming first epitaxial layers and second epitaxial layers respectively in the first recesses and the second recesses; andreplacing the first dummy gate and the second dummy gate respectively with a first gate and a second gate.2. The method of claim 1 , ...

SEMICONDUCTOR PROCESS

A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating. 1. A semiconductor process , comprising:forming a polysilicon layer on a substrate;cryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.; andperforming an asymmetric dual-side heating treatment to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.2. The semiconductor process according to claim 1 , wherein the power for the backside heating is greater than the power for the front-side heating.3. The semiconductor process according to claim 2 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1.4. The semiconductor process according to claim 3 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1.5. A semiconductor process claim 3 , comprising:forming an isolation structure in a substrate;forming a polysilicon layer on the isolation structure; andcryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.6. The semiconductor process according to claim 5 , wherein the step of cryo-implanting the polysilicon layer is performed with liquid nitrogen or at a temperature of −100° C.7. The semiconductor process according to claim 5 , wherein the ...

Method for manufacturing fins

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

P-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure. 1. A method for fabricating a p-type field effect transistor (pFET) , comprising:providing a substrate;forming a pad layer on the substrate;performing an ion implantation process to implant germanium (Ge) into the substrate through the pad layer to form a channel region, wherein a concentration of Ge closer to a boundary between the pad layer and the channel region is greater than a concentration of Ge closer to a boundary between the channel region and the substrate;performing an anneal process while the pad layer is disposed on a top surface of the channel region; andforming a gate structure on the substrate.2. The method of claim 1 , further comprising:forming a well in the substrate before performing the ion implantation process.3. The method of claim 1 , wherein the pad layer comprises silicon oxide.4. The method of claim 1 , further comprising removing the pad layer after performing the anneal process.5. The method of claim 4 , further comprising:forming the gate structure on the substrate after removing the pad layer; andforming a lightly doped drain adjacent to two sides of the gate structure.6. The method of claim 1 , further comprising forming a well in the substrate after performing the ion implantation process.7. The method of claim 1 , further comprising performing the anneal process to separate the channel region into a top portion and a bottom portion.8. The method of claim 7 , wherein a ...

METHOD FOR MAKING SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess. 1. A method for forming a semiconductor structure , comprising:providing a substrate;forming a plurality of recesses in said substrate;providing a precursor mixture to form a non-doped epitaxial layer on the inner surface of said recesses, said precursor mixture comprising a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound, wherein the flow rate ratio of said silicon precursor to said epitaxial material precursor is greater than 1.7; andforming a doped epitaxial layer comprising Si, said epitaxial material and a dopant to substantially fill said recesses.2. The method for forming a semiconductor structure of claim 1 , further comprising:forming a source contact plug disposed above said source; andforming a drain contact plug disposed above said drain, wherein one of said source contact plug and said drain contact plug is in a shape of a slot and the other is a shape of a single square.3. The method for forming a semiconductor structure of claim 1 , wherein said non-doped epitaxial layer has a sidewall and a bottom and a ratio of the bottom thickness to the sidewall thickness is between 0.83 and 1.20.4. The method for forming a semiconductor structure of claim 1 , wherein a doping concentration of said doped epitaxial layer is at least 100 times greater than that of said non-doped epitaxial layer.5. The method for forming a semiconductor structure of claim 1 , wherein ...

SEMICONDUCTOR PROCESS

First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C. 1. A semiconductor process , comprising:providing a substrate with at least one recess;forming an embedded semoconductive epitaxial layer comprising an epitaxial SiGe material which fills up said recess in said substrate;performing a pre-amorphization implant (PAI) procedure on said embedded semoconductive epitaxial layer to form an amorphous region;performing a source/drain implanting procedure on said embedded semoconductive epitaxial layer to form a source doping region and a drain doping region; andperforming a source/drain annealing procedure to form a source and a drain in said substrate, wherein at least one of said pre-amorphization implant procedure and said source/drain implanting procedure is performed in a cryogenic procedure below −30° C.2. The semiconductor process of claim 1 , wherein said embedded semoconductive epitaxial layer comprises a plurality of said epitaxial SiGe materials of different concentrations.3. The semiconductor process of claim 1 , performing said pre-amorphization implant (PAI) procedure before performing said source/drain implanting procedure.4. The semiconductor process of claim 2 , wherein said pre-amorphization implant (PAI) procedure is performed to reach different depths in the embedded semoconductive ...

SEMICONDUCTOR PROCESS

A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating. 1. A semiconductor process for mitigating sheet resistance variation of a polysilicon resistor , comprising:forming a polysilicon layer on a substrate;cryo-implanting the polysilicon layer with a first species, a second species and a third species at a temperature ranging between −40° C. and −120° C. to form the polysilicon resistor, wherein the first species comprises a germanium species, the second species comprises a carbon species, and the third species comprises a p-type species or an n-type species; andperforming an asymmetric dual-side heating treatment to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.2. The semiconductor process according to claim 1 , wherein the power for the backside heating is greater than the power for the front-side heating.3. The semiconductor process according to claim 2 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1.4. The semiconductor process according to claim 3 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1.5. A semiconductor process for mitigating sheet resistance variation of a polysilicon resistor claim 3 , comprising:forming an isolation structure in a substrate;forming a polysilicon layer on the isolation structure; andcryo-implanting the polysilicon layer with a first species, a second species and a third species at a temperature ranging between −40° C. and −120° C. to form the polysilicon resistor, wherein the first species comprises a germanium species, the second species comprises a carbon species, and the third species comprises a p-type species or an n-type species.6. The ...

Semiconductor device with stress-providing structure

A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface.

SEMICONDUCTOR PROCESS

A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating. 1. A semiconductor process , comprising:forming a polysilicon layer on a substrate;cryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.; andperforming an asymmetric dual-side heating treatment to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.2. The semiconductor process according to claim 1 , wherein the power for the backside heating is greater than the power for the front-side heating.3. The semiconductor process according to claim 2 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1.4. The semiconductor process according to claim 3 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1.5. A semiconductor process claim 3 , comprising:forming an isolation structure in a substrate;forming a polysilicon layer on the isolation structure; andcryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.6. The semiconductor process according to claim 5 , wherein the step of cryo-implanting the polysilicon layer is performed with liquid nitrogen or at a temperature of −100° C.7. The semiconductor process according to claim 5 , wherein the third species comprises a boron species.8. The semiconductor process according to claim 5 , wherein the third species is cryo-implanted into the polysilicon layer after cryo-implanting the first species and ...

Semiconductor device

A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Multilayer Isolation Structure for High Voltage Silicon-On-Insulator Device

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron. 1. A device comprising:a semiconductor-on-insulator substrate that includes a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer; and a first insulator sidewall spacer,', 'a second insulator sidewall spacer, and', 'a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer, wherein the multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion., 'an isolation structure that surrounds an active region of the semiconductor-on-insulator substrate, wherein the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate, and further wherein the isolation structure includes2. The device of claim 1 , wherein the top polysilicon portion has a first thickness claim 1 , the bottom silicon portion ...

SOLAR CELL WAFER

A solar cell wafer is provided. It is a silicon wafer, and a surface of the silicon wafer has a plurality of pores, wherein based on a total amount of 100% of the plurality of pores, 60% or more of the pores has a circularity greater than 0.5. Therefore, the reflectance of the solar cell wafer can be efficiently reduced. 1. A solar cell wafer made of silicon , wherein:a surface of the silicon wafer has a plurality of pores, whereinbased on a total amount of 100% of the pores, 60% or more of the pores has a circularity greater than 0.5.2. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 40% or more of the pores has a circularity greater than 0.6.3. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 20% or more of the pores has a circularity greater than 0.7.4. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 70% or more of the pores has a diameter of pore less than 2.0 μm.5. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 50% or more of the pores has a diameter of pore less than 1.5 μm.6. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 25% or more of the pores has a diameter of pore less than 1.0 μm.7. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 90% or more of the pores has an aspect ratio less than 2.5 μm.8. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 80% or more of the pores has an aspect ratio less than 2.0 μm.9. The solar cell wafer of claim 1 , wherein based on a total amount of 100% of the plurality of pores claim 1 , 60% or more of the pores has an aspect ratio less than 1.5 μm.10. The solar cell wafer of claim 1 , wherein a pore ...

POLYCRYSTALLINE SILICON COLUMN AND POLYCRYSTALLINE SILICON WAFER

A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%. 1. A polycrystalline silicon column having a crystal-growing direction , wherein the polycrystalline silicon column comprises:a plurality of silicon grains growing along a crystal-growing direction, wherein in the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends.2. The polycrystalline silicon column of claim 1 , wherein the average grain size of the silicon grains is increased progressively along the crystal-growing direction claim 1 , and the resistivity of the polycrystalline silicon column is decreased progressively along the crystal-growing direction.3. The polycrystalline silicon column of claim 1 , further comprising an available section claim 1 , wherein the minority carrier lifetime of the available section is greater than or equal to 2.0×10seconds claim 1 , and the available section comprises a bottom section.4. The polycrystalline silicon column of claim 3 , wherein the silicon grains comprise at least three crystal orientations claim 3 , the at least three crystal orientations comprising {112} claim 3 , {113} and {115}; and wherein in the bottom section claim 3 , the volume percent of the silicon grains ...

POLYCRYSTALLINE SILICON COLUMN AND POLYCRYSTALLINE SILICON WAFER

A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 Ω-cm. 1. A polycrystalline silicon wafer , comprising:a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 Ω-cm.2. The polycrystalline silicon wafer of claim 1 , wherein the silicon grains comprise at least three crystal orientations claim 1 , the at least three crystal orientations comprise {112} claim 1 , {113} and {115}; and wherein the volume percent of the silicon grains having the crystal orientations {112} claim 1 , {113} and {115} is greater than 45%.3. The polycrystalline silicon wafer of claim 2 , wherein the volume percent of the silicon grains having the crystal orientation {112} is between 25% and 30%.4. The polycrystalline silicon wafer of claim 1 , wherein the polycrystalline silicon wafer has a width claim 1 , and the ratio of the average grain size of the silicon grains to the width of the polycrystalline silicon wafer is less than or equal to 0.061.5. The polycrystalline silicon wafer of claim 1 , wherein the average grain size of the silicon grains is less than or equal to 1.0 cm.6. The polycrystalline silicon wafer of claim 1 , wherein the average defect area ratio of the polycrystalline silicon wafer is less than or equal to 1.5%.7. The polycrystalline silicon wafer of claim 1 , wherein the oxygen content of the polycrystalline silicon wafer is greater than or equal to 5.5 ppma.8. The polycrystalline silicon wafer of claim 1 , wherein the carbon content of the polycrystalline silicon wafer is greater than or equal to 5 ppma.9. A polycrystalline silicon wafer claim 1 , comprising:a plurality of ...

P-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

SEED USED FOR CRYSTALLINE SILICON INGOT CASTING

The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone. 1. A seed , comprising:a crystal, constituted by at least one grain; andan impurity diffusion-resistant layer, formed to overlay an outer surface of the crystal.2. The seed of claim 1 , wherein the impurity diffusion-resistant layer is formed of one selected from the group consisting of BaO claim 1 , Tetraethyl orthosilicate (TEOS) claim 1 , silicon powders claim 1 , BaCO/TEOS mixture claim 1 , BaCO/SiOmixture claim 1 , SiN/TEOS mixture claim 1 , SiN/SiOmixture claim 1 , BaO/SiN mixture claim 1 , metal salt oxide/SiN mixture claim 1 , metal salt oxide/SiOmixture claim 1 , metal salt oxide/TEOS mixture claim 1 , BaO/SiOmixture claim 1 , BaO/TEOS mixture claim 1 , SiC claim 1 , SiO2 claim 1 , graphite claim 1 , AlN claim 1 , BN claim 1 , SiN claim 1 , GaN claim 1 , AlP claim 1 , GaP claim 1 , AlOand metal salt oxide.3. The seed of claim 2 , wherein a metal element of the metal salt oxide is one selected from the group consisting of Be claim 2 , Mg claim 2 , Sr claim 2 , Ca and Ba.4. The seed of claim 2 , further comprising a hetero-nucleation promoting layer claim 2 , formed to overlay the impurity diffusion-resistant layer.5. The seed of claim 4 , wherein the hetero-nucleation promoting layer is formed of SiN or BN.6. The seed of claim 2 , wherein the at least one grain is formed of one selected from the group consisting of Si claim 2 , SiC claim 2 , SiO claim 2 , SiN and graphite. This utility application claims priority to Taiwan Application Serial Number 101150738, filed Dec. 28, 2012, which is ...

Method for manufacturing fins

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

MANUFACTURING METHOD FOR SILICON CARBIDE CRYSTAL

A silicon carbide crystal and a manufacturing method for same are provided. A silicon carbide crystal seed used for the silicon carbide crystal has a crystal-growing surface with a surface roughness (Ra) less than 2.0 nm, and a thickness of the silicon carbide crystal seed is less than 700 μm. Therefore, the silicon carbide crystal grown from the silicon carbide crystal seed by sublimation method (which is also a PVT method) may have low basal plane dislocation (BPD) and low micropipe density (MPD). 1. A silicon carbide crystal seed , for growing silicon carbide crystal , wherein the silicon carbide crystal seed is featured in that:a crystal-growing surface of the silicon carbide crystal seed has a surface roughness (Ra) less than 2.0 nm; anda thickness of the silicon carbide crystal seed is less than 700 μm.2. The silicon carbide crystal seed as recited in claim 1 , wherein the crystal-growing surface of the silicon carbide crystal seed has a surface roughness (Ra) less than 0.5 nm.3. The silicon carbide crystal seed as recited in claim 1 , wherein the crystal-growing surface of the silicon carbide crystal seed has a surface roughness (Ra) less than 0.3 nm.4. The silicon carbide crystal seed as recited in claim 1 , wherein the silicon carbide crystal seed has a total thickness variation (TTV) less than 2 μm.5. The silicon carbide crystal seed as recited in claim 1 , wherein the silicon carbide crystal seed has a warpage less than 30 μm.6. The silicon carbide crystal seed as recited in claim 1 , wherein the silicon carbide crystal seed has a bow less than 20 μm.7. A silicon carbide crystal claim 1 , which is grown from the silicon carbide crystal seed as recited in by a sublimation method claim 1 , which is featured in that the silicon carbide crystal has basal plane dislocation (BPD) of 2200/cmor less.8. The silicon carbide crystal as recited in claim 7 , wherein the silicon carbide crystal has a micropipe density (MPD) of 22/cmor less.9. The silicon carbide ...

SILICON CARBIDE WAFER AND METHOD FOR PRODUCTION THEREOF

A method for producing a silicon carbide wafer includes: providing a silicon carbide wafer having an unpolished surface; in which the unpolished surface has a first crystal face and a second crystal face; polishing one face of the first crystal face and the second crystal face of the unpolished surface in a first polishing solution by using a polisher; in which the polisher includes a polishing pad and a plurality of abrasive particles fixed on the polishing pad; and polishing the other face of the first crystal face and the second crystal face of the unpolished surface in a second polishing solution by using the polisher; in which a pH value of the first polishing solution is less than or equal to 7, and a pH value of the second polishing solution is greater than or equal to 7. The present disclosure also provides a silicon carbide wafer. 1. A method for producing a silicon carbide wafer , comprising:providing a silicon carbide wafer having an unpolished surface; wherein the unpolished surface has a first crystal face and a second crystal face; wherein the first crystal face is a carbon face and the second crystal face is a silicon face;polishing the first crystal face of the unpolished surface in a first polishing solution by using a polisher; wherein the polisher includes a polishing pad and a plurality of abrasive particles fixed on the polishing pad; andpolishing the second crystal face of the unpolished surface in a second polishing solution by using the polisher after polising the first crystal face; wherein a pH value of the first polishing solution is less than or equal to 7, and a pH value of the second polishing solution is greater than or equal to 7.2. The method for producing the silicon carbide wafer according to claim 1 , wherein the pH value of the first polishing solution is less than or equal to 2 claim 1 , and the pH value of the second polishing solution is greater than or equal to 8.3. The method for producing the silicon carbide wafer according ...

METHOD FOR ION IMPLANTATION

A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam. 1. A method for an ion implantation , comprising:providing a non-parallel ion beam; andgenerating a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively;wherein the non-parallel ion beam is a divergent ion beam or a convergent ion beam.2. The method as claimed in claim 1 , wherein at least one three-dimensional structure is located on the upper surface of the workpiece claim 1 , wherein both the top surface and the side surface of the three-dimensional structure should be implanted.3. The method as claimed in claim 2 , wherein the direction of the relative motion intersects with the top surface and the side surface of the three-dimensional structure.4. The method as claimed in claim 2 , wherein each of the top surface and the side surface of the three-dimensional structure is implanted by different portions of the non-parallel ion beam successively.5. The method as claimed in claim 1 , wherein the step for providing the non-parallel ion beam ...

ISOLATION EPITAXIAL BI-LAYER FOR BACKSIDE DEEP TRENCH ISOLATION STRUCTURE IN AN IMAGE SENSOR

In some embodiments, the present disclosure relates to an integrated chip, including a substrate, a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type, and a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and including a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type, a second isolation epitaxial layer arranged along inner sidewalls of the first isolation epitaxial layer and having a second doping type different than the first doping type, and an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer. 1. An integrated chip , comprising:a substrate;a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type; and a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type;', 'a second isolation epitaxial layer arranged along an inner sidewall of the first isolation epitaxial layer and having a second doping type different than the first doping type; and', 'an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer., 'a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and comprising2. The integrated chip of claim 1 , wherein the first doping type is n-type claim 1 , and wherein the second doping type is p-type.3. The integrated chip of claim 1 , wherein the isolation filler structure comprises a dielectric material.4. The integrated chip of claim 1 , wherein the first isolation epitaxial layer is thicker than the second isolation ...

Wafer surface defect inspection method and apparatus thereof

A wafer surface defect inspection method and a wafer surface defect inspection apparatus are provided. The method includes the following steps. Scanning information of a wafer is received, and the scanning information includes multiple scanning parameters. At least one reference point of the scanning information is determined, and path information is generated according to the at least one reference point and a reference value. Multiple first scanning parameters corresponding to the path information in the scanning parameters are obtained according to the path information to generate a curve chart. According to the curve chart, it is determined whether the wafer has a defect, and a defect type of the defect is determined.

CRUCIBLE ASSEMBLY AND METHOD OF MANUFACTURING CRYSTALLINE SILICON INGOT BY USE OF SUCH CRUCIBLE ASSEMBLY

The invention provides a crucible assembly and method of manufacturing a crystalline silicon ingot by use of such crucible assembly. The crucible assembly of the invention includes a crucible body and a fiber textile article. The fiber textile article is made of a plurality of carbon fibers, and is loaded on a bottom of the crucible body. The fiber textile article has a plurality of intrinsic pores randomly arranged. 1. A crucible assembly , comprising:a crucible body having a bottom; anda first fiber textile article binge made of a plurality of first carbon fibers, being loaded on the bottom of the crucible body, and having a plurality of intrinsic first pores randomly arranged.2. The crucible assembly of claim 1 , wherein each intrinsic first pore has an aperture in a range of from 0.05 mm to 2 mm.3. The crucible assembly of claim 2 , wherein each first carbon fiber has a diameter in a range of from 1 μm to 500 μm.4. The crucible assembly of claim 2 , wherein first fiber textile article has a compressible deformation in a range of from 20% to 80%.5. The crucible assembly of claim 1 , wherein the crucible body also has an inner sidewall claim 1 , the crucible assemble further comprises a second fiber textile article which is made of a plurality of second carbon fibers claim 1 , is loaded on the inner sidewall of the crucible body claim 1 , and has a plurality of intrinsic second pores randomly arranged.6. A method of manufacturing a crystalline silicon ingot claim 1 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'preparing the crucible assembly as claimed in ;'}loading a silicon feedstock on the first fiber textile article in the crucible assembly;heating the crucible assembly until the silicon feedstock is melted into a silicon melt completely;based on a directional solidification process, cooling the crucible assembly such that a plurality of silicon grains from the silicon melt nucleate at the intrinsic first pores and grow in a ...

SILICONE CARBIDE CRYSTALS AND MANUFACTURING METHOD THEREOF

A silicon carbide crystal and a manufacturing method thereof are provided. The silicon carbide crystal includes an N-type seed layer, a barrier layer, and a semi-insulating ingot, which are sequentially stacked and are made of silicon carbide. The N-type seed layer has a resistivity within a range of 0.01-0.03 Ω·cm. The barrier layer includes a plurality of epitaxial layers sequentially formed on the N-type seed layer by an epitaxial process. The C/Si ratios of the epitaxial layers gradually increase in a growth direction away from the N-type seed layer. A nitrogen concentration of the silicon carbide crystal gradually decreases from the N-type seed layer toward the semi-insulating ingot by a diffusion phenomenon, so that the semi-insulating crystal has a resistivity larger than 10Ω·cm. 1. A silicon carbide (SiC) crystal , comprising:an N-type seed layer made of a silicon carbide and having a resistivity within a range of 0.01-0.03 Ω·cm;a barrier layer having a plurality of epitaxial layers sequentially and epitaxially formed on the N-type seed layer, wherein each of the epitaxial layers is made of a silicon carbide and has a C/Si ratio, and the C/Si ratios of the epitaxial layers gradually increase in a forming direction away from the N-type seed layer; and{'sup': '7', 'a semi-insulating ingot made of a silicon carbide and formed from one of the epitaxial layers that is arranged away from the N-type seed layer, wherein a nitrogen concentration of the silicon carbide crystal gradually decreases from the N-type seed layer toward the semi-insulating ingot by a diffusion phenomenon, so that the semi-insulating ingot has a resistivity larger than 10Ω·cm.'}2. The SiC crystal according to claim 1 , wherein the number of the epitaxial layers of the barrier layer is three claim 1 , and the C/Si ratios of the epitaxial layers distributed in the forming direction are sequentially 1.2-1.4 claim 1 , 1.4-1.6 claim 1 , and 1.7-1.9.3. The SiC crystal according to claim 1 , wherein ...

MONO-CRYSTALLINE SILICON GROWTH APPARATUS

A mono-crystalline silicon growth apparatus includes a furnace, a support base, a crucible, a heating module disposed outside of the crucible, and a heat adjusting module above the crucible. The heat adjusting module includes a diversion tube, a plurality of heat preservation sheets, and a hard shaft. The diversion tube includes a tube body and a carrying body connected to the tube body. The heat preservation sheets are sleeved around the tube body and are stacked and disposed on the carrying body. The hard shaft passes through the tube body and does not rotate. The hard shaft includes a water flow channel disposed therein and a clamping portion configured to clamp a seed crystal. Therefore, a fluid injected into the water flow channel takes away the heat near the clamping portion. A heat adjusting module and a hard shaft of the mono-crystalline silicon growth apparatus are provided. 1. A mono-crystalline silicon growth apparatus , comprising:a furnace;a support base disposed in the furnace;a crucible disposed on the support base, wherein the support base and the crucible do not rotate relative to the heating module; and a diversion tube including a tube body and a carrying body, wherein one end of the tube body is disposed on the furnace and another end of the tube body is connected to the carrying body, and the carrying body surrounds the tube body, and wherein a projection area formed by orthogonally projecting the tube body along an axial direction of the tube body onto the crucible falls on an inner bottom surface of the crucible;', 'a plurality of heat preservation sheets which are annular and sleeved around the tube body, wherein the heat preservation sheets are stacked and disposed on the carrying body; and', 'a hard shaft passing through the tube body, wherein the hard shaft does not rotate relative to the furnace, and wherein a water flow channel is disposed in the hard shaft, the hard shaft includes a clamping portion and at least a part of the clamping ...

Mono-crystalline silicon growth method

A mono-crystalline silicon growth method includes: providing a furnace, a supporting base and a crucible which do not rotate relative to the furnace, and a heating module disposed at an outer periphery of the supporting base. After solidifying a liquid surface of a silicon melt in the crucible to form a crystal, the heating power of the heating module is successively reduced to appropriately adjust the temperature around the crucible to effectively control a temperature gradient of a thermal field around the crucible, so as to form a mono-crystalline silicon ingot by solidifying the silicon melt.

METHODS FOR USING ISOTOPICALLY ENRICHED LEVELS OF DOPANT GAS COMPOSITIONS IN AN ION IMPLANTATION PROCESS

A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels. 1. A method of using an enriched dopant gas , comprising:introducing the enriched dopant gas at a flow rate sufficient to maintain stability of the ion source, wherein the enriched dopant gas has an enrichment level in an isotope therein of 90% or greater than natural abundance levels;operating at a reduced total power level of the ion source in comparison to a total power level utilized for a correspondingly lesser enriched or non-enriched dopant gas; andionizing the enriched dopant gas to generate and maintain a beam current as produced using the correspondingly lesser enriched or non-enriched dopant gas at the flow rate.2. The method of claim 1 , further comprising:operating the ion source at a reduced temperature in comparison to the correspondingly lesser enriched or non-enriched dopant gas at the flow rate; andoperating at the reduced total power level by reducing arc voltage, arc bias, filament power or a combination thereof.3. The method of claim 1 , further ...

Mono-crystalline silicon growth apparatus

A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.

Crystal growth apparatus and thermal insulation cover of the same

A crystal growth apparatus includes a crucible, a heating device, a thermal insulation cover, and a driving device. The crucible contains materials to be melted, wherein the heating device heats the crucible to melt the materials; the thermal insulation cover is provided upon the materials, wherein the thermal insulation cover includes a main body, which has a bottom surface facing an interior of the crucible, and a insulating member being provided at the main body; the driving device moves the thermal insulation cover towards or away from the materials, whereby, the thermal insulation cover effectively blocks heat conduction and heat convection, which prevents thermal energy from escaping out of the crucible.

SILICON WAFER CLEANER AND METHOD FOR CLEANING SILICON WAFER

A cleaner for silicon wafer and a method for cleaning silicon wafer are provided. The cleaner for silicon wafer is essentially consisted of 1-3 wt % of citric acid, 2.5-5 wt % of sodium bicarbonate, limonene, potassium hydroxide and water. The cleaning efficiency may be improved by using the cleaner for silicon wafer to clean the silicon wafer. 1. A silicon wafer cleaner , which is essentially consisted of:1 wt % to 3 wt % of citric acid;2.5 wt % to 5 wt % of sodium bicarbonate;limonene;potassium hydroxide; anda solvent.2. The silicon wafer cleaner according to claim 1 , wherein a content of limonene is 0.2 wt % to 1 wt %.3. The silicon wafer cleaner according to claim 1 , wherein a content of potassium hydroxide is 0.25 wt % to 0.75 wt %.4. The silicon wafer cleaner according to claim 1 , wherein a pH value of the silicon wafer cleaner is 10 or less.5. The silicon wafer cleaner according to claim 4 , wherein the pH value of the silicon wafer cleaner is 7.0 to 10.0.6. The silicon wafer cleaner according to claim 1 , wherein the solvent comprises water.7. A method for cleaning a silicon wafer claim 1 , comprising:soaking a silicon wafer in a silicon wafer cleaner at a normal temperature, wherein the silicon wafer cleaner is essentially consisted of:1 wt % to 3 wt % of citric acid;2.5 wt % to 5 wt% of sodium bicarbonate;limonene;potassium hydroxide; and a solvent.8. The method for cleaning the silicon wafer according to claim 7 , wherein claim 7 , wherein a time of the soaking is 600 seconds (sec) to 1200 sec.9. The method for cleaning the silicon wafer according to claim 7 , wherein a content of limonene is 0.2 wt % to 1 wt %.10. The method for cleaning the silicon wafer according to claim 7 , wherein a content of potassium hydroxide is 0.25 wt % to 0.75 wt %.11. The method for cleaning the silicon wafer according to claim 7 , wherein a pH value of the silicon wafer cleaner is 10 or less.12. The method for cleaning the silicon wafer according to claim 11 , wherein ...

Semiconductor device

A semiconductor device includes a substrate, an initial layer, and a buffer stack structure. The initial layer is located on the substrate and includes aluminum nitride (AlN). The buffer stack structure is located on the initial layer and includes a plurality of base layers and at least one doped layer positioned between two adjacent base layers. Each of the base layers includes aluminum gallium nitride (AlGaN), and the doped layer includes AlGaN or boron aluminum gallium nitride (BAlGaN). In the buffer stack structure, concentrations of aluminum in the base layers gradually decrease, concentrations of gallium in the base layers gradually increase, the base layers do not contain carbon substantially, and dopants in the doped layer include carbon or iron.

Method for collecting dust from single crystal growth system and dust collecting system thereof

A dust collecting system for single crystal growth system includes an air compressor, a dust collecting device, a first inert gas source, a rotary pump and a scrubber. The air compressor is fluidly connected to an exit pipe of the single crystal growth system. The exit pipe is used to exhaust unstable dust from the single crystal growth system. The dust collecting device is fluidly connecting to the exit pipe to collect the dust oxide. The first inert gas source is fluidly connected to the exit pipe to blow a first inert gas into the exit pipe to compel the dust oxide toward the dust collecting device. The rotary pump is fluidly connected to the dust collecting device. The scrubber is fluidly connected to the rotary pump. The rotary pump transports the residual dust oxide toward the scrubber. The present disclosure further provides a method for collecting dust.

STIRRING APPARATUS OF INGOT CASTING FURNACE

A stirring apparatus of an ingot casting furnace includes a rotating shaft and at least one fin. The fin is provided onto the rotating shaft, and has a first edge, a second edge of unequal length provided correspondingly, and a third edge connecting the first and the second edges. The rotating shaft can be driven to rotate, which consequently drives the at least one fin to stir materials in a crucible. The length of the first edge is different from that of the second edge in order for the materials in the crucible can be mixed with dopants more uniformly during the stirring process to produce ingots of stable quality. 1. A stirring apparatus of an ingot casting furnace , comprising:a rotating shaft;at least one fin provided on the rotating shaft, wherein the at least one fin has a first edge and a second edge which correspond to each other, and have unequal lengths.2. The stirring apparatus of claim 1 , wherein the at least one fin has a third edge away from the rotating shaft; two ends of the third edge are respectively connected to the first edge and the second edge; the first edge and the second edge are parallel to each other claim 1 , and the length of the first edge is greater than the length of the second edge.3. The stirring apparatus of claim 1 , wherein the at least one fin has a third edge away from the rotating shaft; two ends of the third edge are respectively connected to the first edge and the second edge; the first edge and the second edge are parallel to each other claim 1 , and the length of the first edge is less than the length of the second edge.4. The stirring apparatus of claim 2 , wherein the third edge has at least one straight segment.5. The stirring apparatus of claim 3 , wherein the third edge has at least one straight segment.6. The stirring apparatus of claim 2 , wherein the third edge has at least one curved segment.7. The stirring apparatus of claim 3 , wherein the third edge has at least one curved segment. 1. Technical FieldThe ...

Semiconductor device

A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films and a plurality of second films, and the first films and the second films are alternately stacked on the initial layer. If the first films are doped films having dopants selected from a group consisting of carbon, iron, and the combination thereof, the second films do not include dopants substantially; if the second films are doped films having dopants selected from a group consisting of carbon, iron, and the combination thereof, the first films do not include dopants substantially.

LOWER DOSE RATE ION IMPLANTATION USING A WIDER ION BEAM

In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece. 1. A method for implanting ions into a work piece at lower dose rates , the method comprising:generating an ion beam using an ion source and an extraction manipulator, wherein the ion beam includes an x-dimension that is perpendicular to a y-dimension of the ion beam, and wherein the x-dimension and the y-dimension are perpendicular to a direction of travel of the ion beam;positioning the extraction manipulator at a gap distance from an exit aperture of the ion source, wherein a current of the ion beam exiting the extraction manipulator is maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture, and wherein the gap distance differs from the optimal gap distance by at least 10 percent;applying a first potential to a first set of electrodes, wherein the x-dimension of the ion beam is increased as the ion beam passes through the first set of electrodes; andpositioning the work piece in the ion beam to implant ions into the work piece.2. The method of claim 1 , wherein the extraction manipulator includes a suppression electrode claim 1 , and wherein a suppression current of the suppression ...

SILICON CARBIDE WAFER AND POSITIONING EDGE PROCESSING METHOD THEREOF

A silicon carbide (SiC) wafer and a positioning-edge processing method thereof are provided. The SiC wafer has a first flat and a second flat. A first rounded corner is respectively disposed at a connection between two ends of the first flat and an edge of the SiC wafer, wherein the first rounded corner has a radius of 1-10 mm. A second rounded corner is respectively disposed at a connection between two ends of the second flat and the edge of the SiC wafer, wherein the second rounded corner has a radius of 1-10 mm. Since the rounded corners at the connections between two ends of the flats and the wafer edges have optimum radii, the yield and quality of the wafer processing may be improved. 1. A silicon carbide (SiC) wafer having a first flat and a second flat , wherein:a first rounded corner, disposed at a connection between one end of the first flat and an edge of the SiC wafer and between another end of the first flat and the edge of the SiC wafer, wherein the first rounded corner has a radius of 1-10 mm; anda second rounded corner, disposed at a connection between one end of the second flat and the edge of the SiC wafer and between another end of the second flat and the edge of the SiC wafer, wherein the second rounded corner has a radius of 1-10 mm.2. The silicon carbide wafer of claim 1 , wherein the radius of the first rounded corner is equal to the radius of the second rounded corner.3. The silicon carbide wafer of claim 1 , wherein the radius of the first rounded corner is larger than the radius of the second rounded corner.4. The silicon carbide wafer of claim 1 , wherein a width of the first flat is larger than a width of the second flat.5. The silicon carbide wafer of claim 1 , wherein the first flat is disposed at 90° to the second flat.6. The silicon carbide wafer of claim 1 , wherein a diameter of the SiC wafer is 50-200 mm.7. A positioning-edge processing method of a silicon carbide (SiC) wafer claim 1 , comprising:inspecting an original specification ...

碳化矽晶片

一種碳化矽晶片包括位於相反側的兩個表面，並且兩個表面的至少其中一個表面為拋光面且包括：基準面及微結構模組。基準面未形成有長度大於5微米的刮痕。微結構模組形成於基準面，微結構模組包含凹設於基準面的多個微凹陷以及突出於基準面的多個微凸起，並且微結構模組的三維算數平均偏差(Sa)小於2.5奈米，而微結構模組的三維輪廓高低差(Sz)小於20奈米。

Material analysis method

A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

LIGHT ABSORBING LAYER TO ENHANCE P-TYPE DIFFUSION FOR DTI IN IMAGE SENSORS

In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

Cleaning device

Methods for using isotopically enriched levels of dopant gas compositions in an ion implantation process

Wafer inspection method and apparatus thereof

The disclosure provides a wafer inspection method and wafer inspection apparatus. The method includes: receive scanning information of at least one wafer, wherein the scanning information includes a plurality of haze values; the scanning information is divided into a plurality of information blocks according to the unit block, and the feature value of each the plurality of information blocks is calculated according to the plurality of haze values included in each the plurality of information blocks; and converting the feature value into a color value according to the haze upper threshold and the haze lower threshold, and generating the color value corresponding to the at least one wafer according to the converted color value according to the feature value, the color graph displays the texture content of the at least one wafer.

Single sign-on system and method and computer readable medium thereof

System and method for integrating and transmitting data

A system for integrating and transmitting data comprises a request receiving module, which receives download requests from first heterogeneous databases by a main server; a list establishing module, which establishes corresponding download lists according to the download requests; a data selecting module, which selects download data from second heterogeneous databases and receives the download data by the main sever according to the download lists; and a data transmitting module, which transmits the download data to the first heterogeneous databases according to the download lists.

Metal-insulator-metal capacitor and methods of manufacturing

Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include a photodiode device electrically connected to a metal-insulator-metal deep-trench capacitor. The metal-insulator-metal deep-trench capacitor includes a layer of an amorphous material between an insulator layer stack of the deep-trench capacitor structure and a capacitor bottom metal layer of the metal-insulator-metal deep-trench capacitor. The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the capacitor bottom metal electrode layer to the insulator layer stack. In this way, leakage associated with grain boundaries, crystal defects, and interfaces of a bottom layer of the insulator layer stack may be overcome to improve a lag performance of the semiconductor device including the metal-insulator-metal deep-trench capacitor.

Photolithography alignment process for bonded wafers

Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Pre-cleaning for a deep trench isolation structure in a pixel sensor

A cyclic pre-cleaning technique may be used to clean the surfaces of a recess in which a deep trench isolation (DTI) structure is to be formed. The cyclic pre-cleaning technique may include performing one or more deposition and etch cycles to remove oxygen from the surfaces of the recess to reduce the oxygen concentration in the surfaces of the recess. A passivation layer may be formed in the recess after the cyclic pre-cleaning technique is used to clean the surfaces. The cyclic pre-cleaning technique may include the use of germanium (Ge) to bond with oxygen in the surfaces of the recess, which results in the formation of germanium oxide (GeO). The germanium oxide is removed, resulting in reduced oxygen concentration in the surfaces of the recess. The reduced oxygen concentration increases the quality of epitaxial growth of the passivation layer in the recess.

Method for collecting dust from single crystal growth system

A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.

Wafer inspection method and apparatus thereof

The disclosure provides a wafer inspection method and wafer inspection apparatus. The method includes: receive scanning information of at least one wafer, wherein the scanning information includes a plurality of haze values; the scanning information is divided into a plurality of information blocks according to the unit block, and the feature value of each of the plurality of information blocks is calculated according to the plurality of haze values included in each of the plurality of information blocks; and converting the feature value into a color value according to the haze upper threshold and the haze lower threshold, generating the color value corresponding to the at least one wafer according to the converted color value according to the feature value, whereby the color graph displays the texture content of the at least one wafer.

Enhanced trench isolation structure

The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Passivation for a deep trench isolation structure in a pixel sensor

A boron layer may be formed as a passivation layer in a recess in which a deep trench isolation structure (DTI) structure is to be formed. The boron layer results in formation of a boron-silicon interface between the DTI structure and a photodiode of a pixel sensor included in a pixel array. The boron-silicon interface functions as a diode junction, which resists penetration of photons into the DTI structure. This reduces and/or minimizes photon transmission through the DTI structure, which reduces and/or minimizes optical crosstalk between pixel sensors of the pixel array.

Photodiode structure for image sensor

The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped photodiode layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second photodiode as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.

Back-side deep trench isolation structure for image sensor

The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Enhanced trench isolation structure

The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Full well capacity for image sensor

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

Light absorbing layer to enhance p-type diffusion for dti in image sensors

In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

Light absorbing layer to enhance P-type diffusion for DTI in image sensors

In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

Ion implantation system

A plasma flood gun includes a filament to emit first electrons based on a first filament current induced in the filament to heat the filament to a first temperature at a first time. The first electrons interact with an inert gas in an arc plasma chamber to generate a first plasma. A filament resistance meter measures a first filament resistance of the filament, in-situ, during generation of the first plasma. A filament current source adjusts, based on the first filament resistance, the first filament current induced in the filament at the first time to a second filament current induced in the filament at a second time to generate a second plasma in the arc plasma chamber at the second time.

Method for collecting dust from single crystal growth system and dust collecting system thereof

A dust collecting system for single crystal growth system includes an air compressor, a dust collecting device, a first inert gas source, a rotary pump and a scrubber. The air compressor is fluidly connected to an exit pipe of the single crystal growth system. The exit pipe is used to exhaust unstable dust from the single crystal growth system. The dust collecting device is fluidly connecting to the exit pipe to collect the dust oxide. The first inert gas source is fluidly connected to the exit pipe to blow a first inert gas into the exit pipe to compel the dust oxide toward the dust collecting device. The rotary pump is fluidly connected to the dust collecting device. The scrubber is fluidly connected to the rotary pump. The rotary pump transports the residual dust oxide toward the scrubber. The present disclosure further provides a method for collecting dust.

Semiconductor bonding tool and method of operating the same

A bag is filled with liquid, instead of an airbag filled with gas, to deform a bottom wafer toward a top wafer during a wafer bonding process. As a result, the liquid is less susceptible to temperature changes, which reduces run-out variation across wafer bonding processes. Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced. Additionally, in some implementations, the liquid may be pre-heated before the bag is filled with the liquid. As a result, the bottom wafer (and, to some extent, the top wafer) experiences some thermal deformation and less mechanical deformation, which further increases yield and reduces a quantity of non-functioning devices that are produced.

Single sign-on system and method and computer readable medium thereof

System and method for integrating and transmitting data

用於製造矽晶鑄錠之晶種

一種用於製造矽晶鑄錠之晶種。根據本發明之一較佳具體實施例之晶種包含晶體以及雜質擴散阻障層。晶體係由至少一晶粒所構成。雜質擴散阻障層係被覆在晶體之外表面上。利用本發明之晶種製造的矽晶鑄錠，其紅區與黃區明顯減少。

Material analysis method

A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

非晶質相改質装置及び単結晶材料の加工方法

【課題】改質層の厚さを数十ミクロン以下に減少させる効果的なレーザー光適用方法、及び改質層を効果的に生成する単結晶材料加工方法を欠いている。【解決手段】単結晶材料の加工方法は下記ステップを含む。単結晶材料を改質すべき物体として提供する。改質すべき物体の内部を加工するためにフェムト秒レーザビームを放射するため、非晶質相改質装置を用いる。加工は、改質すべき物体の内部に複数の加工線を形成するためフェムト秒レーザビームを用いることを含み、各加工線はジグザグパターン加工を含み、複数の加工線の間の加工線間隔は２００μｍ～６００μｍの範囲であり、改質すべき物体が加工された後、改質すべき物体中に改質層が形成される。改質すべき物体の改質層を含む部分をスライス又は分離する。【選択図】図４Ａ

Trapping layer for a radio frequency die and methods of formation

An insulator layer of a trap-rich silicon-on-insulator (SOI) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. The silicon layer of the trap-rich SOI wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. The second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. Accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. Thus, operations to form the trap-rich SOI wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich SOI wafer to be formed to a lesser thickness.

Photolithography alignment process for bonded wafers

Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Semiconductor device

A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Backside leakage prevention

A package structure according to the present disclosure includes a bottom substrate, a bottom interconnect structure over the bottom substrate, a top interconnect structure disposed over the bottom interconnect structure and including a metal feature, a top substrate over the top interconnect structure, and a protective film disposed on the top substrate. The protective film includes an interfacial layer on the top substrate, at least one dipole-inducing layer on the interfacial layer, a moisture block layer on the at least one dipole-inducing layer, and a silicon oxide layer over the moisture block layer. The at least one dipole-inducing layer includes aluminum oxide, titanium oxide or zirconium oxide.

Photolithography alignment process for bonded wafers

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Deep trench isolation structure and methods for fabrication thereof

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

Method for forming semiconductor-on-insulator (SOI) substrate by cleaving a multilayer structure along voids to separate a substrate

A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

Photolithography alignment process for bonded wafers

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

半導体デバイス

【課題】AlGaN製のバッファ層全体中にドーパントを連続的にドープする従来技術による、結晶化度及び粗さの劣化による半導体デバイス全体の反りの問題を解決する。【解決手段】半導体デバイスが基板、初期層、及びバッファ積層構造を含む。初期層は基板上に位置し、窒化アルミニウム（AlN）を含む。バッファ積層構造は初期層上に位置し、複数のベース層、及び隣接する２つのベース層間に配置された少なくとも１つのドープ層を含む。ベース層の各々が窒化アルミニウムガリウム（AlGaN）を含み、ドープ層はAlGaNまたは窒化ホウ素アルミニウムガリウム（BAlGaN）を含む。バッファ積層構造内では、ベース層内のアルミニウムの濃度が次第に減少し、ベース層内のガリウムの濃度は次第に増加し、ベース層は炭素を実質的に含有せず、ドープ層内のドーパントは炭素または鉄を含む。【選択図】図１

Passivation for a vertical transfer gate in a pixel sensor

A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.

Multilayer isolation structure for high voltage silicon-on-insulator device

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Mehrschicht-isolationsstruktur fürhochspannungs-silizium-auf-isolator-vorrichtung

Im vorliegenden Text werden Tiefgrabenisolationsstrukturen für Hochspannungs-Halbleiter-auf-Isolator-Vorrichtungen offenbart. Eine beispielhafte Tiefgrabenisolationsstruktur umgibt eine aktive Region eines Halbleiter-auf-Isolator-Substrats. Die Tiefgrabenisolationsstruktur umfasst einen ersten Isolator-Seitenwand-Abstandshalter, einen zweiten Isolator-Seitenwand-Abstandshalter und eine mehrschichtige, Silizium umfassende Isolationsstruktur, die zwischen dem ersten Isolator-Seitenwand-Abstandshalter und dem zweiten Isolator-Seitenwand-Abstandshalter angeordnet ist. Die mehrschichtige, Silizium umfassende Isolationsstruktur weist einen oberen Polysiliziumabschnitt auf, der über einem unteren Siliziumabschnitt angeordnet ist. Der untere Polysiliziumabschnitt wird durch einen selektiven Abscheidungsprozess gebildet, während der obere Polysiliziumabschnitt durch einen nicht-selektiven Abscheidungsprozess gebildet wird. In einigen Ausführungsformen wird der untere Siliziumabschnitt mit Bor dotiert.

高電圧シリコンオンインシュレータ装置用の多層分離構造

【課題】深トレンチ分離構造の素子分離構造を有する高電圧半導体オンインシュレータ装置及びその製造方法を提供する。【解決手段】半導体オンインシュレータ基板のアクティブ領域を囲む深トレンチ分離構造は、第１の絶縁体側壁スペーサと、第２の絶縁体側壁スペーサと、第１の絶縁体側壁スペーサと第２の絶縁体側壁スペーサとの間に配置された多層シリコン含有分離構造と、を有する。多層シリコン含有分離構造は、ボトムシリコン部の上に配置されたトップポリシリコン部を有する。ボトムシリコン部は、選択堆積プロセスにより形成される。トップポリシリコン部は、非選択堆積プロセスにより形成される。ボトムシリコン部は、ボロンによりドープされる。【選択図】なし

Multilayer isolation structure for high voltage silicon-on-insulator device

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.