Memory Circuit, Pixel Circuit, and Data Accessing Method Thereof

A pixel circuit includes a pixel unit and a memory circuit. The memory circuit includes a first switch, a switch unit, a second switch, and a plurality of memory units. Each of the memory units includes a third switch and a capacitor, where the capacitors of the memory units have a same capacitance. A data accessing method applied on the pixel circuit includes determining an order of writing a plurality of first voltages, which are loaded from a data line, according to weights of bits within a first bit string, where the bits are respectively corresponding to the first voltages, and includes determining an order and loading durations of loading a plurality of second voltages, which are previously stored in the memory units, according to weights of bits within a second bit string, where the bits are respectively corresponding to the second voltages. 1. A memory circuit comprising:a first switch coupled to a pixel unit, the first switch turned on when reading data from the pixel unit for receiving a plurality of first voltages from the pixel unit, wherein the first voltages individually correspond to a plurality of bits comprised by a first bit string;a switch unit coupled to the first switch for controlling switching of a data read mode or a data write mode of the pixel unit;a second switch coupled to the pixel unit, the second switch turned on when writing data to the pixel unit for receiving a plurality of second voltages from the switch unit, wherein the second voltages individually correspond to a plurality of bits comprised by a second bit string; and a third switch turned on when the memory unit is utilized for storing the first voltage or reading the second voltage; and', 'a capacitor comprising a first terminal coupled to a first terminal of the third switch, and a second terminal coupled to ground, wherein capacitances of the capacitors comprised by the plurality of memory units are essentially equal., 'a plurality of memory units coupled to the switch unit, ...

Bidirectional silicon-controlled rectifier

A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.

INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor. 1. A semiconductor device for electrostatic discharge (ESD) protection , comprising:a semiconductor substrate;an n-type well formed in the substrate;a p-type metal-oxide-semiconductor (PMOS) transistor formed in the n-type well including a gate, the PMOS including a first diffused region and a second diffused region separated apart from the first diffused region;a first n-type region formed in the n-type well and electrically connected to the first diffused region of the PMOS transistor; anda second n-type region formed in the n-type well and electrically connected to the first diffused region of the PMOS transistor, wherein the first n-type region is separated apart from the second n-type region by the second diffused region of the PMOS;wherein the gate of the PMOS transistor is kept at a reference voltage level to keep the PMOS transistor at an on state before an ESD event occurs.2. The device of further comprising a p-type region formed in the substrate and electrically connected to the second diffused region of the PMOS transistor.3. The device of claim 2 , wherein the second diffused region of the PMOS transistor formed in the n-type well and ...

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region. 1. An electrostatic discharge (ESD) protection device , comprising:a substrate comprising a first conductive type;a first doped region formed in the substrate and comprising a second conductive type;a second doped region formed in the substrate and comprising the second conductive type;a third doped region formed in the substrate, comprising the first conductive type and located between the first and the second doped regions;a gate formed on the substrate, located between the first and the second doped regions and comprising a first through hole; anda plurality of contacts passing through the first through hole to contact with the third doped region.2. The ESD protection device as claimed in claim 1 , wherein the first through hole is a closed region.3. The ESD protection device as claimed in claim 1 , wherein the gate further comprises a second through hole claim 1 , and the size of the second through hole is equal to the size of the first through hole.4. The ESD protection device as claimed in claim 1 , wherein the gate further comprises a second through hole claim 1 , and the size of the second through hole is not equal to the size of the first through hole.5. The ESD protection device as ...

CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF

A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor. 1. A charge pump circuit comprising:an input end;an output end; andat least one stage coupled between the input end and the output end, the at least one state comprising a first complementary metal-oxide-semiconductor (CMOS) transistor pair configured to electrically connect to a first timing signal, a first capacitor coupled with the first CMOS transistor pair, a second CMOS transistor pair configured to connect to a second timing signal, and a second capacitor coupled with the second CMOS transistor pair,a first transistor having a first gate being coupled with the first CMOS transistor pair and a source coupled with a gate of an n-type metal-oxide-semiconductor (NMOS) transistor of the first CMOS transistor pair,wherein the first transistor is configured to connect to a third timing signal;a second transistor having a second gate being coupled with the second CMOS transistor pair and a source coupled with a gate of an NMOS transistor of the second CMOS transistor pair,wherein the second transistor is configured to connect to a fourth timing signal, andthe first timing signal, the second timing signal, the third timing signal and the fourth timing signal have an amplitude substantially equal to an ...

ELECTROSTATIC DISCHARGE CIRCUIT FOR RADIO FREQUENCY TRANSMITTERS

A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line. 1. A radio frequency (RF) transmitter comprising:a power amplifier having an input that receives RF signals and an output that transmits the amplified RF signals to an antenna; andan electrostatic discharge (ESD) protection circuit that is electrically coupled to the output of the power amplifier, wherein the ESD protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of the power amplifier, an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus, and an ESD clamp circuit that is coupled to the first voltage line.2. The RF transmitter of claim 1 , wherein the SCR comprises:an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.3. The RF transmitter of claim 1 , wherein the first P-type and first N-type semiconductor materials are implanted in an N-well and the second P-type claim 1 , second N-type and third P-type semiconductor materials are implanted in a P-well claim 1 , ...

LOAD-ADAPTIVE BIOELECTRIC CURRENT STIMULATOR

The disclosure relates to a load-adaptive bioelectrical current stimulator, which comprises a current output module, an adaptation module and a control module. The current output module generates a stimulus current to an electrode. The adaptation module detects the electrical status of the stimulus current passing through the electrode and generates a feedback signal to the control module. According to the feedback signal, the control module controls the current output module to stabilize the output status of the stimulus current adaptively. Thereby, the load-adaptive bioelectrical current stimulator can use the feedback control mechanism to regulate the value of the stimulus current to adapt to variation of load impedance. 1. A load-adaptive bioelectric current stimulator comprising:a current output module generating a stimulus current to an electrode;an adaptation module detecting an electric status of said stimulus current when said stimulus current passes through said electrode, and generating a feedback signal; anda control module controlling said current output module according to said feedback signal to stabilize output of said stimulus current adaptively.2. The load-adaptive bioelectric current stimulator according to claim 1 , wherein said adaptation module is an analog/digital conversion circuit claim 1 , and said analog/digital conversion circuit provides a digital voltage signal for said control module as said feedback signal according to an output voltage generated by said stimulus current when said stimulus current passes through said electrode.3. The load-adaptive bioelectric current stimulator according to claim 2 , wherein said control module is a digital control device claim 2 , and according to said digital voltage signal claim 2 , said digital control device provides said current output module with an operating signal in a PFM (Pulse Frequency Modulation) way to regulate said stimulus current.4. The load-adaptive bioelectric current stimulator ...

ESD PROTECTION CIRCUIT

ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate. 1. An electro-static discharge (ESD) protection circuit comprising:at least a protection transistor serially coupled between an internal node and a voltage node; each said protection transistor comprising a gate, a source and a drain with the gate being coupled to the drain; anda resistor coupled between the internal node and a signal node.2. The ESD protection circuit of claim 1 , wherein each said protection transistor further comprises a bulk coupled to the voltage node.3. The ESD protection circuit of claim 1 , wherein each said protection transistor further comprises a bulk coupled to the source.4. The ESD protection circuit of claim 1 , wherein each said protection transistor further comprises a bulk coupled to a second voltage node claim 1 , and the second voltage node is isolated from the voltage node.5. The ESD protection circuit of further comprising:at least a second protection transistor serially coupled between the internal node and the voltage node along with each said protection transistor; each said second protection transistor comprising a second source, a second gate and a second drain with the second gate being coupled to the second drain.6. The ESD protection circuit of claim 5 , wherein the drain of a said protection transistor is coupled to the second drain of a said second protection transistor claim 5 , such that each said protection transistor and each said second protection transistor are serially coupled between the internal node and the voltage node.7. The ESD protection circuit of further comprising at least a diode serially coupled between the internal node and the voltage node.8. The ESD ...

ESD PROTECTION CIRCUIT

An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor. 1. An ESD protection circuit including:a silicon controlled rectifier;a first CMOS inverter electrically connected with the silicon controlled rectifier;a first transistor having a first end, a second end and a third end, wherein the first end is electrically connected with the silicon controlled rectifier and the first CMOS inverter;a current mirror electrically connected with the third end of the first transistor;a PMOS capacitor electrically connected with the current mirror; anda resistor electrically connected with first CMOS inverter, the second end of the first transistor and the PMOS capacitor.2. The ESD protection circuit in accordance with claim 1 , wherein the first end of the first transistor is a gate electrode claim 1 , the second end is a drain electrode claim 1 , and the third end is a source electrode.3. The ESD protection circuit in accordance with claim 1 , wherein the current mirror comprises a third transistor and a fourth transistor claim 1 , a gate electrode of the third transistor electrically connects with a drain electrode of the third transistor claim 1 , a gate electrode of the fourth transistor and the PMOS capacitor claim 1 , and a drain electrode of the fourth transistor electrically connects ...

Electrostatic discharge protection apparatus

An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.

INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor. 127-. (canceled)28. A method of providing electrostatic discharge (ESD) protection , comprising:providing a silicon controlled rectifier (SCR) including a semiconductor substrate and a well formed in the substrate;providing a p-type metal-oxide-semiconductor (PMOS) transistor formed in the well of the SCR including a gate, a first diffused region and a second diffused region spaced apart from the first diffused region;providing an n-type region formed in the well being electrically connected to the first diffused region of the PMOS transistor;providing a p-type region formed in the substrate being electrically connected to the second diffused region of the PMOS transistor; andkeeping the PMOS transistor at an on state before an ESD event occurs.29. The method of claim 28 , further comprising triggering a first current in the well in response to an ESD event.30. The method of claim 29 , further comprising triggering a second current in the substrate in response to the first current.31. The method of claim 28 , further comprising keeping the gate of the PMOS transistor at a reference voltage level before an ESD event occurs.32. A method of providing ...

SELF-RESET TRANSIENT-TO-DIGITAL CONVERTOR AND ELECTRONIC PRODUCT UTILIZING THE SAME

A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node. 1. A self-reset transient-to-digital convertor , comprising: at least one voltage drop unit configured to be conducted to pass through an ESD current when an ESD event occurs;', 'a current amplifier unit coupled between the voltage drop unit and a first node, wherein the current amplifier unit is conducted by the ESD current to set the level of the first node; and', 'a time control unit coupled between the first node and the second power line and configured to gradually drain the ESD current away;, 'at least one transient detection circuit coupled between a first power line and a second power line, comprisingwherein, each of the transient detection circuit generates a digital code according to the level of the first node.2. The self-reset transient-to-digital convertor of claim 1 , wherein the time control unit comprises:a resistor coupled between the first node and the second power line to gradually drain the ESD current to the second power line, so as to reset the level of the first node automatically; anda capacitor connected to the resistor in parallel.3. The self-reset transient-to-digital convertor of claim 2 , wherein the current amplifier unit comprises:a first transistor ...

ESD PROTECTION CIRCUIT

An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other. 1. An electrostatic discharge protection circuit comprising:an input node coupled to receive an input signal;an output node coupled to output the input signal to an internal circuit;a first inductor coupled to the input node and to the output node;a second inductor coupled to the output node and to a first power supply node through a resistance; anda plurality of protection devices coupled to the first and second inductors and disposed in parallel with each other.2. The electrostatic discharge circuit of claim 1 , wherein the plurality of protection devices includes at least one of a diode claim 1 , a transistor claim 1 , and a silicon-controlled rectifier.3. The electrostatic discharge circuit of claim 2 , wherein the transistor includes a gate-grounded NMOS transistor.4. The electrostatic discharge circuit of claim 1 , wherein the plurality of protection devices include:a first protection device coupled to the input node and to the first power supply node;a second protection device coupled to the output node and to the first power supply node; anda third protection device coupled to the first power supply node and to a first node to which the second inductor and the resistance are coupled.5. The electrostatic discharge circuit of claim 4 , wherein a first diode having an anode coupled to the first power supply node and a cathode coupled to the input node, and', 'a second diode having an anode coupled to the input node and a cathode coupled to a second power supply line;, 'the first ...

CURRENT STIMULATOR

The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation. 1. A current stimulator comprisinga high voltage output module including a plurality of transistors stacked together, receiving an input control signal and a first voltage, wherein voltages output by all said transistors are added to said first voltage to form a second voltage;a voltage control module electrically connected with said high voltage output module and outputting a voltage control signal for providing a stable stimulus current for a load according to said second voltage and variation of impedance of said load; anda charge pump electrically connected with said high voltage output module and said voltage control module, receiving said voltage control signal, and regulating said first voltage supplied to said high voltage output module.2. The current stimulator according to claim 1 , wherein said high voltage output module further comprises a driving unit and a high voltage output unit claim 1 , which are electrically connected claim 1 , and wherein said high voltage output unit includes a plurality of voltage division resistors and said ...

PLANAR MIRCO-TUBE DISCHARGER STRUCTURE AND METHOD FOR FABRICATING THE SAME

The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability. 1. A planar micro-tube discharger structure comprisinga substrate;two patterned electrodes formed on said substrate and separated by a gap;at least one separating block formed on said substrate and arranged in said gap; anda first insulating layer formed over said patterned electrodes and said separating block and filled into said gap to create at least two discharge paths via which said patterned electrodes discharge electricity.2. The planar micro-tube discharger structure according to claim 1 , wherein said first insulating layer further comprisesa first sub-insulating layer formed over said patterned electrodes and said separating block, filled into said gap, and having a groove formed inside said gap and interconnecting said patterned electrodes; anda second sub-insulating layer formed over said first sub-insulating layer and filled into said groove to create said discharge paths.3. The planar micro-tube discharger structure according to further comprising a second insulating layer formed on said substrate claim 1 , wherein said patterned electrodes claim 1 , said separating block and said first insulating layer are formed over said second insulating layer.4. The planar micro-tube discharger structure according to claim 1 , wherein each said patterned electrode has at least one cavity thereinside.5. The planar micro-tube discharger ...

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event. 1. An electrostatic discharge (ESD) protection circuit , suitable for an input stage circuit including a first N-channel metal oxide semiconductor (NMOS) transistor , the ESD protection circuit comprising:a P-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor; andan impedance device, coupled to the gate of the PMOS transistor directly and a first power rail.2. The ESD protection circuit according to claim 1 , wherein the drain of the PMOS transistor is directly coupled to a heavily doped N-type (N+) diffusion region used to form the source of the first NMOS transistor claim 1 , and coupled to a first ground rail through the N+ diffusion region.3. The ESD protection circuit according to claim 1 , wherein the impedance device is a resistor.4. The ESD protection circuit according to claim 1 , further comprising a capacitor coupled to the impedance device and a first ground rail claim 1 , wherein the gate of the PMOS transistor is coupled to a common node between the impedance device and the capacitor.5. The ESD protection circuit according to claim 4 , further ...

POWER-RAIL ELECTRO-STATIC DISCHARGE (ESD) CLAMP CIRCUIT

A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation. 1. A power-rail Electro-Static Discharge (ESD) clamp circuit comprising:{'sub': DD', 'SS, 'a silicon controlled rectifier, connected to a high voltage level Vand a low voltage level Vfor bearing a current flow; and'}{'sub': DD', 'SS, 'a control module, connected to said silicon controlled rectifier in parallel, said control module connecting between said high voltage level V, said low voltage level Vand a trigger node of said silicon controlled rectifier.'}2. The power-rail ESD clamp circuit of claim 1 , wherein said silicon controlled rectifier is a P+ triggered silicon controlled rectifier claim 1 , and said control module comprises:{'sub': 'DD', 'a PMOS, connected to said high voltage level V;'}{'sub': 'SS', 'a NMOS, connected to said low voltage level V;'}at least one output diode, connected between said PMOS and said NMOS, wherein said trigger node of said P+ triggered silicon controlled rectifier is connecting to said at least one output diode, and said PMOS, said NMOS and said at least one output diode are connecting serially together;{'sub': 'DD', 'a resistor, parallelly connected to said P+ triggered silicon controlled rectifier, said PMOS and said NMOS, one end of said resistor connecting to said high voltage level V; and'}{'sub': 'SS', 'a conducting string, comprising at least one conducting element connected to ...

METHOD FOR FABRICATING A PLANAR MICRO-TUBE DISCHARGER STRUCTURE

A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability. 1. A method for fabricating a planar micro-tube discharger structure , comprising steps:forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in said gap; andforming a first insulating layer over said patterned electrodes and said separating block and filling said first insulating layer into said gap to create at least two discharge paths interconnecting said patterned electrodes.2. The method for fabricating a planar micro-tube discharger structure according to claim 1 , wherein said step of forming said first insulating layer over said patterned electrodes and said separating block and filling said first insulating layer into said gap to create said discharge paths further comprises steps:forming an inner insulating layer over said patterned electrodes and said separating block and completely filling said gap with said inner insulating layer;removing a portion of said inner insulating layer located inside said gap to form on said patterned electrodes and said separating block a first sub-insulating layer having a groove interconnecting said patterned electrodes; andforming a second sub-insulating layer over said first sub-insulating layer and filling said second sub-insulating layer into said groove to create said discharge paths, whereby said first insulating layer is formed over said patterned electrodes and said separating block.3. The method for ...

Active surge protection structure and surge-to-digital converter thereof

An active surge protection structure is provided between a power line and a core circuit, comprising a surge-to-digital converter and a clamp circuit. The surge-to-digital converter comprises a plurality of surge detection circuit. Each surge detection circuit detects a surge event occurring on the power line and generates a digital signal. The clamp circuit is disposed adjacent to the core circuit and electrically connected with the surge-to-digital converter and the power line where the core circuit is connected for dissipating surge energy. The clamp circuit receives and is driven by the digital signals from the surge-to-digital converter such that its protection flexibility can be achieved according to the digital signals. By employing the present invention, it is extraordinarily advantageous of improving system stability and achieving comprehensive surge protection with configuration of driving capability dependent on surge levels.

SELF-BALANCED DIODE DEVICE

A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval. 1. A self-balanced diode device comprising:a substrate;a doped well arranged in said substrate;at least one first conductivity type heavily doped fin arranged in said doped well, arranged in a line along a first direction, and protruded up from a surface of said substrate;at least two second conductivity type heavily doped fins arranged in said doped well, arranged in a line along a second direction intersecting said first direction, respectively arranged at two opposite sides of said first conductivity type heavily doped fin, and protruded up from said surface of said substrate, and each said second conductivity type heavily doped fin and said first conductivity type heavily doped fin are spaced at a fixed interval, and said doped well, said first conductivity type heavily doped fin and said second conductivity type heavily doped fins form at least two diodes, and said first conductivity type heavily doped fin is coupled to a first voltage terminal, and said second conductivity type heavily doped fins are coupled to a second voltage terminal, and voltages of said first voltage terminal and said second voltage terminal forward bias said diodes to ...

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint. 1. An electrostatic discharge (ESD) protection circuit , comprising:a detection circuit, coupled between a first power rail and a second power rail, detecting an ESD stress from the first power rail or the second power rail, and outputting a detection signal according to the ESD stress;a triggering circuit, coupled to the detection circuit, receiving the detection signal and outputting a triggering signal according to the detection signal; anda dual-directional silicon controlled rectifier (DSCR) device, comprising a first terminal coupled to the first power rail, a second terminal coupled to the second power rail, a third terminal coupled to the triggering circuit to receive the triggering signal, and at least two transistors of a first type, and configured to discharge the ESD stress according to the triggering signal, wherein the third terminal is coupled to a common node between at least two transistors of the first type.2. The ESD protection circuit of claim 1 , wherein the at least two transistors of ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device. 1. A semiconductor device , comprising:a substrate;a well region disposed in the substrate and having a first conductive type;an isolation structure disposed in the substrate and surrounding an active region in the well region;a source region disposed in the active region and in the well region;a drain region disposed in the active region and in the well region;a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region, wherein the first conductive type is different from the second conductive type, and the isolation structure surrounds the second conductive type first doped region, and wherein the isolation structure has a first depth, the second conductive type first doped region has a second depth, and the first depth is greater than the second depth;a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region;a source ...

INTEGRATED CIRCUITS AND METHODS OF THE SAME

An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss. 1. An integrated circuit , comprising:a T-coil circuit coupled to an input/output (I/O) pad and an internal circuit;a silicon-controlled rectifier (SCR) coupled to the T-coil circuit and the internal circuit; anda signal-loss prevention circuit coupled to the T-coil circuit and the SCR.2. The integrated circuit of claim 1 , wherein the signal-loss prevention circuit comprises:a resistor coupled to the T-coil circuit and the SCR,wherein the resistor is configured to provide a current path for an electrostatic current to flow through and turn on the SCR when the electrostatic current occurs.3. The integrated circuit of claim 1 , wherein the signal-loss prevention circuit comprises:a diode circuit coupled to the T-coil circuit and the SCR, and configured to prevent signal loss.4. The integrated circuit of claim 1 , further comprising:a power-rail electrostatic discharge (ESD) clamp circuit coupled to a first power rail and a second power rail,wherein the internal circuit is coupled to the first and second power rails.5. The integrated circuit of claim 1 , further comprising:an electrostatic discharge (ESD) circuit coupled to a node between the SCR and the internal circuit.6. The integrated circuit of claim 5 , wherein the ESD circuit is configured to not turn on by a signal of a ...

Power Rail Clamp Circuit

A power rail clamp circuit is coupled between a system power supply and a ground for alleviating an electrostatic discharge effect. The power rail clamp circuit includes a first conduction circuit, a second conduction circuit, an AND gate module and a switch module. The AND gate module receives a first conduction signal generated by the first conduction circuit and a second conduction signal generated by the second conduction circuit to generate an enabling signal. The switch module conducts the power rail clamp circuit according to the enabling signal, to process an electrostatic discharge operation. The first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply. 1. A power rail clamp circuit , coupled between a system power supply and a ground , the power rail clamp circuit comprising:a first conduction circuit, coupled to the system power supply, configured to generate a first conduction signal;a second conduction circuit, coupled to the system power supply, configured to generate a second conduction signal;an AND gate module, coupled to the system power supply, the first conduction circuit and the second conduction circuit, configured to receive the first conduction signal and the second conduction signal for generating an enabling signal; anda switch module, coupled to the system voltage source and the AND gate module, configured to conduct the power rail clamp circuit according to the enabling signal for processing an electrostatic discharge operation;wherein the first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply.2. The power rail clamp circuit of claim 1 , wherein the first conduction circuit comprises a first resistor unit and a conduction unit claim 1 , and ...

THREE-DIMENSION (3D) INTEGRATED CIRCUIT (IC) PACKAGE

A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate. 1. A three-dimension (3D) integrated circuit (IC) package comprising:a package substrate having a surface, and at least one integrated circuit (IC) chip and at least one transient voltage suppressor (TVS) chip are arranged on said surface and electrically connected with each other, and said IC chip is independent from said TVS chip.2. The 3D IC package according to claim 1 , further comprises:a plurality of conduction plugs arranged in said TVS chip;a plurality of first conduction bumps arranged on conduction areas of said surface and respectively arranged under said conduction plugs, and said TVS chip is electrically connected with said conduction areas through said first conduction bumps and said conduction plugs; anda plurality of second conduction bumps respectively arranged on said conduction plugs, and said IC chip is electrically connected with said conduction areas and said TVS chip through said first and second conduction bumps and said conduction plugs.3. The 3D IC package according to claim 2 , wherein said first conduction bumps and said second conduction bumps comprise Pb or Sn claim 2 , and said conduction plugs comprise Cu.4. The 3D IC package according to claim 2 , wherein one conduction plug is connected with a high-voltage pin claim 2 , another said conduction plug is connected with a low-voltage terminal claim 2 , and other said conduction ...

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND OPERATION METHOD THEREOF

An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element. 1. An electrostatic discharge (ESD) protection device comprising:a first ESD current rail;a first ESD protection element string, a first end and a second end of the first ESD protection element string being electrically connected to the first ESD current rail and a signal pad, respectively, wherein the first ESD protection element string comprises a first ESD protection element and a second ESD protection element serially connected to each other; anda first bias circuit electrically connected to the first ESD protection element string to provide a first bias voltage to a first common connection node between the first ESD protection element and the second ESD protection element.2. The ESD protection device of claim 1 , wherein the first ESD current rail is a supply voltage rail or a ground voltage rail.3. The ESD protection device of claim 1 , wherein an anode of the first ESD protection element is electrically connected to the signal pad claim 1 , a cathode of the first ESD protection element and an anode of the second ESD protection element are electrically connected to the first common connection node claim 1 , and a cathode of the second ESD protection element is electrically connected to the first ESD current rail.4. The ESD protection device of ...

DEFIBRILLATOR DEVICE

A defibrillator device is provided. The defibrillator device includes a first electrode, a second electrode, a readout module, a USB interface, a voltage converter and a stimulation module. When the first and second electrodes contact the chest of a patient, the readout module obtains a physiologic rhythm signal of the patient and provides a heart rhythm signal according to the first physiologic rhythm signal. According to a first voltage from a portable electronic device, the voltage converter generates a second voltage when the first USB interface is coupled to the portable electronic device, wherein the second voltage is larger than the first voltage. When the physiologic rhythm signal indicates that cardiac arrhythmia is present in the patient, the stimulation module provides an electric shock energy to the chest of the patient via the first and second electrodes according to the second voltage. 1. A defibrillator device , comprising:a first electrode;a second electrode;a readout module coupled to the first and second electrodes, obtaining a first physiologic rhythm signal of a patient when the first and second electrodes contact a chest of the patient, and providing a heart rhythm signal according to the first physiologic rhythm signal;a first USB interface;a voltage converter coupled to the first USB, wherein according to a first voltage from a portable electronic device via the first USB interface, the voltage converter generates a second voltage when the first USB interface is coupled to the portable electronic device, wherein the second voltage is higher than the first voltage;a stimulation module coupled to the first and second electrodes and the voltage converter, providing an electric shock energy to the chest of the patient via the first and the second electrodes according to the second voltage when the first physiologic rhythm signal indicates that cardiac arrhythmia is present in the patient;a memory, storing an application; anda controller coupled to ...

Test device for eliminating electrostatic charges

In a test device for eliminating electrostatic charges, an elimination integrated circuit (IC) has a plurality of first pins, a second pin and a third pin. The first pins are respectively connected with a plurality of fourth pins of at least one tested integrated circuit (IC), and electrostatic charges are on a surface of the tested IC. The third pin is connected with ground. The fourth pins respectively contact a plurality of probes of a tester. The second pin receives a turn-on signal, the elimination IC uses the turn-on signal to form conduction paths between the tested IC and ground and to discharge the electrostatic charges to ground through the first pins and the third pin. Then, the second pin receives a turn-off signal, the elimination IC uses the turn-off signal to cut off the conduction paths and the tester tests the tested IC.

TEST METHOD FOR ELIMINATING ELECTROSTATIC CHARGES

In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC. 1. A test method for eliminating electrostatic charges , which uses a test equipment comprising a tester and a platform; said test method comprising steps of: said tester contacting and testing at least one tested integrated circuit (IC) on a test area of said platform; and', 'removing said tested IC from said tester and said test area;, 'performing at least one test process, and electrostatic charges are generated on said test equipment in said test process, and said test process further comprises steps ofmoving a conduction device which is grounded to said test area;said tester contacting said conduction device to discharge said electrostatic charges to ground;removing said conduction device from said tester and said test area; andreturning to said test process to test next said tested IC.2. The test method for eliminating electrostatic charges according to claim 1 , wherein said electrostatic charges are generated by a human body or said tested IC contacting and separating said tester.3. The test method for eliminating electrostatic charges according to claim 1 , wherein said tester has a plurality of probes claim 1 , and in said step of said tester contacting said tested IC claim 1 , said probes of said tester ...

Robust ESD Protection with Silicon-Controlled Rectifier

Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane. 1. A silicon controlled rectifier (SCR) that includes a current path to carry current from an SCR anode to an SCR cathode; wherein the current path comprises:a first vertical current path component coupled to the SCR anode;a second vertical current path component coupled to the SCR cathode;a horizontal current path component arranged under the first and second vertical current path components, wherein the horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane, wherein the first and second well regions cooperatively span a distance separating the first and second vertical current path components;at least one first well region contact electrically coupled to the first well region; andat least one second well region contact electrically coupled to the second well region and shorted to the at least one first well region contact.2. The SCR of claim 1 , wherein the first and second vertical current path components mirror one another symmetrically about the first plane.3. The SCR of claim 1 , further comprisingat least one first vertical current path component recess extending inwardly from a sidewall of the first vertical current path component; andat least one second vertical current path component recess that extends ...

WIRELESS CHARGING DEVICE

A wireless charging device includes a wireless charging transmitter transmitting a charging signal to a signal gain module to generate at least one gain signal. The signal gain module includes an insulation substrate with an upper surface thereof provided with a first conductive wire. The first conductive wire makes at least one turns arranged along the inner edge of the insulation substrate. The lower surface of the insulation substrate is provided with a second conductive wire whose position corresponds to the position of the first conductive wire. A connecting element is arranged between the first conductive wire and the second conductive wire, such that the first conductive wire is electrically connected to the second conductive wire through the connecting element. The present invention provides a charging signal with high intensity to avoid the low charging efficiency caused by deflection and too long a distance. 1. A wireless charging device comprising:a wireless charging transmitter, provided with a transmitting terminal, using the transmitting terminal to emit at least one charging signal; and an insulation substrate having an upper surface and a lower surface, a center of the upper surface is provided with a first buffer portion, and a center of the lower surface is provided with a second buffer portion;', 'a first conductive wire, arranged on the upper surface of the insulation substrate, outwardly making at least one turns around the first buffer portion;', 'a second conductive wire whose position corresponds to a position of the first conductive wire, arranged on the lower surface of the insulation substrate, outwardly making at least one turns around the second buffer portion; and', 'a connecting element electrically connected to the first conductive wire and the second conductive wire, and the first conductive wire is electrically connected to the second conductive wire through the connecting element., 'at least one signal gain module, arranged at the ...

Programmable quick discharge circuit and method thereof

A programmable power discharge circuit and a method of discharging power are provided. The programmable power discharge circuit includes a programmable voltage controller, a detect circuit, and a discharge circuit. The programmable voltage controller selects and provides a threshold voltage by a voltage divider including a plurality of impedance components. The detect circuit detects a difference between the threshold voltage and a working voltage to decide whether the working voltage is discharged.

ACTIVE GUARD RING STRUCTURE TO IMPROVE LATCH-UP IMMUNITY

An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active guard ring structure comprises an I/O circuit and an active protection circuit, wherein the I/O circuit receives a trigger current via an input pad and generates a corresponding bulk current since being triggered. The active protection circuit, connected between the I/O circuit and a core circuit, detects whether the trigger current is a positive or negative current pulse. When an intensity of the trigger current is larger than a threshold value, the active protection circuit controls the I/O circuit to provide a sink or compensation current so as to neutralize the bulk current and to reduce the net current flowing into or sourced from the core circuit, thereby increasing the latch-up resistance and immunity of the core circuit. 1. An active guard ring structure to improve latch-up immunity , which is connected between an input pad and a core circuit , comprising:an I/O circuit, connected to said input pad and receiving a trigger current, said I/O circuit generating a bulk current after being triggered by said trigger current; andan active protection circuit, connected between said I/O circuit and said core circuit, wherein said active protection circuit detects said trigger current and when intensity of said trigger current is higher than a threshold value, said active protection circuit controls said I/O circuit to provide a corresponding current so as to neutralize said bulk current and to prevent said core circuit from encountering latch-up.2. The active guard ring structure to improve latch-up immunity of claim 1 , wherein when said trigger current is a positive current pulse claim 1 , said corresponding current is a sink current so as to reduce a net current flowing into said core circuit claim 1 , or when said trigger current is a negative current pulse claim 1 , said corresponding current is a ...

SILICON CONTROLLED RECTIFIER

A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance. 1. A silicon controlled rectifier comprising:a semiconductor substrate comprising silicon of a first conductivity type;first and second semiconductor wells formed in the semiconductor substrate, and respectively comprising silicon of a second conductivity type and silicon of the first conductivity type;first and second semiconductor regions respectively formed in the first and the second semiconductor wells in spaced apart relation, and respectively comprising silicon of the first conductivity type and silicon of the second conductivity type;third and fourth semiconductor regions respectively formed in the first and the second semiconductor wells, and respectively comprising silicon of the second conductivity type and silicon of the first conductivity type, wherein the third semiconductor region contacts with the fourth semiconductor region; anda silicide layer formed on the third and the fourth semiconductor regions.2. The silicon controlled rectifier according to claim 1 , wherein the third and the fourth semiconductor regions locate in a neighboring region of the first and the ...

COCHLEAR IMPLANT DEVICE AND STIMULATING METHOD THEREOF

A cochlear implant device comprises a receiver, a processing device, a first electrode and a second electrode. The receiver is configured to receive outside voice signal. The processing device is coupled to the receiver, configured to receive and transfer the voice signal to an electrical stimulation signal. The first electrode connects to the processing device, disposed on stapes footplate ligament or oval window. The second electrode connects to the processing device, disposed on round window. Wherein the electrical stimulation signal is applied to stapes footplate ligament, oval window or round window to stimulate acoustic nerve through the first electrode or the second electrode. 1. A cochlear implant device , comprising:a receiver, configured to receive outside voice signal;a processor is coupled to the receiver, configured to receive and transfer the voice signal to an electrical stimulation signal;a first electrode connects to the processor, disposed on stapes footplate ligament or oval window; anda second electrode connects to the processor, disposed on round window;wherein the electrical stimulation signal is applied to stapes footplate ligament, oval window or round window to stimulate acoustic nerve through the first electrode or the second electrode.2. The device as claimed in claim 1 , wherein the first electrode is attached to the stapes footplate ligament or the oval window through gel claim 1 , and the second electrode is attached to the round window through gel.3. The device as claimed in claim 1 , wherein the first electrode and the second electrode are partially covered by a biocompatible layer claim 1 , respectively.4. The device as claimed in claim 1 , wherein the electrical stimulation signal is transferred between the stapes footplate ligament and the round window claim 1 , or between the oval window and the round window.5. The device as claimed in claim 1 , the other one of the first electrode and the second electrode is configured to be a ...

DIODE, DIODE STRING CIRCUIT, AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE

A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region. 1. A diode , comprising:a substrate;a first insulating layer disposed on the substrate;a second insulating layer disposed on the substrate, wherein the second insulating layer is configured to define a cell region with the first insulating layer;a well disposed on the substrate and beneath the cell region;a deep doped region disposed in the well and beneath the cell region;a first doped region having a first conductivity type, wherein the first doped region is disposed in the cell region and on the deep doped region; anda second doped region having a second conductivity type, wherein the second doped region is disposed adjacent to the first doped region;wherein the second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.2. The diode of claim 1 , further comprising:a spacing region disposed on the deep doped region and between the first doped region and the second doped region.3. The diode of claim 1 , further comprising:a gate electrode disposed on the cell region and between the first doped region and the second doped region.4. The diode of claim 1 , wherein the conductivity type of ...

Circuit for electrostatic discharge (ESD) protection

A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.

Electrostatic discharge protection circuit

An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

ESD bus lines in CMOS IC's for whole-chip ESD protection

In this invention, a new whole-chip ESD protection scheme with the ESD buses has been proposed to solve the ESD protection issue of the CMOS IC having a large number of separated power lines. Multiple ESD buses, which are formed by the wide metal lines, have been added into the CMOS IC having a large number of separated power lines. The bi-directional ESD-connection cells are connected between the separated power lines and the ESD buses, but not between the separated power lines. The ESD current on the CMOS IC with more separated power lines are all conducted into the ESD buses, therefore the ESD current can be conducted by the ESD buses away from the internal circuits and quickly discharged through the designed ESD protection devices to ground. By using this new whole-chip ESD protection scheme with the ESD buses, the CMOS IC having more separated power lines can be still safely protected against ESD damages.

ESD protection circuit with active triggering

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

Method and apparatus for automatic recovery of microprocessors/microcontrollers during electromagnetic compatibility (EMC) testing

A combined hardware/firmware device and method for automatic recovery of an integrated circuit avoids a disruptive power-on reset after occurrence of an electrostatic discharge which may occur during normal operations or during electromagnetic compatibility testing. The device is incorporated into the chip of the IC and includes an electromagnetic discharge sensor, a flag, and firmware to execute the recovery and reset procedures. The sensor is located between the VDD and VSS lines of the IC which itself includes one or both of a microprocessor and a microcontroller. In a power-on reset sequence, the sensor output and the flag are both set to logic 0. After an electrical transient voltage occurs, the sensor output is set to logic 1. The logic 1 output of the sensor sets the flag, which may be a D flip-flop, to a value of logic 1. When either a power-on reset operation begins or the sensor output is set to logic 1 due to an electrical transient voltage on the VDD-VSS lines, firmware begins a reset subroutine in which (1) the sensor output is reset to logic 0, (2) the status of the flag is checked, (3) if the flag is at logic 1, the firmware performs a recovery procedure to restore predetermined functions of the IC and resets the flag to logic 0 (the recovery procedure being performed on the order of nanoseconds), and (4) if the flag is at logic 0, a general reset procedure is performed. The reset procedure includes a first set of operations and the recovery procedure includes a second set of operations which is different from the first set of operations (for example, a subset or overlapping set). The reset procedure will be disruptive to a user, whereas the recovery procedure involves smooth restoration not noticeable to the user. The apparatus and method permit higher levels of electrostatic discharge to be absorbed by a device without causing permanent damage and/or corrupted data. One particular embodiment for the present invention is for personal computer ...

Schmitt Trigger made of the low-voltage-devices and capable of withstanding high voltage inputs

Bipolar transistor device

A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique

Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface

An low-voltage triggered PNP device for input signals with voltage level larger than VDD or less than VSS. The ESD protection device provides an ESD path from a first to a second node for protection of an internal circuit. The device comprises a substrate of a first conductivity type coupled to the first node, a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated, a second doped region of the first conductivity type in the first doped region coupled to the second node, and a third doped region in the substrate, adjacent to the first doped region, to have a low trigger voltage.

Power-rail ESD protection circuit with ultra low gate leakage

An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.

ESD detection circuit and related method thereof

Diode, diode string circuit, and electrostatic discharge protection device having doped region and well isolated from each other

A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.

2×VDD-tolerant logic circuits and a related 2×VDD-tolerant I/O buffer with PVT compensation

A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Two - way PNPN silicon - controlled rectifier

Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

ESD protection circuitry with multi-finger SCRS

Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N−1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N−1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N−1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit.

Polydiode structure for photo diode

An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

High voltage device with ESD protection

A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

Active surge protection structure and surge-to-digital converter thereof

An active surge protection structure is provided between a power line and a core circuit, comprising a surge-to-digital converter and a clamp circuit. The surge-to-digital converter comprises a plurality of surge detection circuit. Each surge detection circuit detects a surge event occurring on the power line and generates a digital signal. The clamp circuit is disposed adjacent to the core circuit and electrically connected with the surge-to-digital converter and the power line where the core circuit is connected for dissipating surge energy. The clamp circuit receives and is driven by the digital signals from the surge-to-digital converter such that its protection flexibility can be achieved according to the digital signals. By employing the present invention, it is extraordinarily advantageous of improving system stability and achieving comprehensive surge protection with configuration of driving capability dependent on surge levels.

Initial-on SCR device for on-chip ESD protection

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Electrostatic discharge protection apparatus

An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

Self-reset transient-to-digital convertor and electronic product utilizing the same

A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.

Charge pump circuit suitable for low-voltage process

The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.

Electrostatic discharge protection device and fabrication method thereof

An electrostatic discharge (ESD) protection device and a fabrication method thereof are provided. The ESD protection device with an embedded high-voltage P type SCR (EHVPSCR) structure of the present invention is employed to guide the ESD current/voltage to a system voltage trace VDD via a pad.

On-chip ESD protection circuit with a substrate-triggered SCR device

An ESD (electrostatic discharge) protection circuit is electrically connected to an I/O buffering pad, an internal circuit (IC), a V SS power terminal and a V DD power terminal. The ESD protection circuit comprises a first ESD-detection circuit electrically connected between the I/O pad and the V SS power terminal, a second ESD-detection circuit electrically connected between the I/O pad and the V DD power terminal, a P-STSCR comprising a first lateral SCR and a P trigger node, and an N-STSCR comprising a second lateral SCR and an N trigger node. When a positive-to-V SS ESD event occurs on the I/O buffering pad, the first ESD-detection circuit generates a first trigger current to the P-trigger node of the P-STSCR to trigger the first lateral SCR. The P-STSCR is thus quickly turned on, and current incurred from the positive voltage pulse is discharged to the V SS power terminal. When a negative-to-V DD ESD event occurs on the I/O buffering pad, the second ESD-detection circuit generates a second trigger current to the N-trigger node of the N-STSCR to trigger the second lateral SCR. The N-STSCR is quickly turned on, and current incurred from the negative voltage pulse is discharged to the V DD power terminal. In contrast to the prior method of making an on-chip ESD protection circuit, the present invention uses a substrate-triggered SCR device with a much lower switching voltage in the protection circuit, and applies the protection circuit to input ESD protection circuits, output ESD protection circuits, and power-rail ESD clamp circuits. ESD robustness of the IC product in the deep submicron CMOS processes is improved, and the total layout area of the on-chip ESD protection circuit is reduced.

Electrostatic discharge protection circuit

An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Power-rail ESD clamp circuits with well-triggered PMOS

A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.

ESD protection circuit with active triggering

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

Esd protection circuit and electronic apparatus

Low-voltage-triggered SOI-SCR device and associated ESD protection circuit

A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region. A third first-type doped region is formed within the first and the second-type well around their junction between the first and second-type well. The second-type well further includes a second second-type doped region and a fourth first-type doped region within the second-type well between the second second-type doped region and the second gate adjacent to the second second-type doped region. The second second-type doped region and the fourth first-type doped region together form an anode of the SOI-SCR device.

Turn-on-efficient bipolar structures for on-chip esd protection

A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Automatic transmission line pulse system

A system for measuring electrostatic discharge (ESD) characteristics of a semiconductor device that comprises at least one pulse generator generating ESD-scale pulses, a first point of the semiconductor device receiving a first ESD-scale pulse from the at least one pulse generator, a second point of the semiconductor device receiving the first ESD-scale pulse from the at least one pulse generator, at least a third point of the semiconductor device receiving a second ESD-scale pulse from the at least one pulse generator, and a data collector to collect data on the ESD characteristics of the semiconductor device.

Output buffer with process and temperature compensation

An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.

On-chip noise filter circuit

A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.

Simulated 3D View of 2D Background Images and Game Objects

Device layout to improve ESD robustness in deep submicron CMOS technology

A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.

Electrostatic discharge protection device for mixed voltage interface

An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation

A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

Silicon-controlled rectifier with dynamic holding voltage for on-chip electrostatic discharge protection

Automatic transmission line pulse system

Level shifter with body-biased circuit

Low-capacitance bonding pad for semiconductor device

A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Electrostatic discharge protection for power amplifier in radio frequency integrated circuit

A circuit for protecting a power amplifier from electrostatic discharge (ESD) that comprises a clamp circuit connected between a first power line and a connection line, and a detecting circuit connected between the connection line and a second power line for detecting whether an ESD event occurs at a conductive pad coupled to the power amplifier and activating the clamp circuit in response to an ESD event, wherein an ESD current due to the ESD event is conducted by the clamp circuit to the first power line.

Protection circuit against electrostatic discharge containing a capacitor circuit

ESD protection circuit with active triggering

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

Transient noise detection circuit

A transient noise detection circuit for detecting a level of a transient noise voltage is disclosed. The transient noise detection circuit comprises a triggering circuit, a rectifying circuit, and a controller. The triggering circuit is coupled between a power rail and a ground node. When the triggering circuit receives a transient noise, the triggering circuit generates a triggering signal. The rectifying circuit comprises a rectifying unit and a current-limiting unit coupled in series. When the rectifying unit receives the triggering signal from the triggering circuit, the rectifying unit will be triggered by the triggering signal. The controller is coupled to a detection node between the rectifying unit and the current-limiting unit. The controller is used for determining the level of the transient noise voltage based on the voltage of the detection node.

Electrostatic discharge (ESD) protection circuit

Electrostatic discharge protection device and electrostatic discharge protection circuit

ESD protection circuit for mixed mode integrated circuits with separated power pins

An ESD protected circuit is provided for protecting first and second internal circuits against ESD failure. The first and second internal circuits are respectively connected to either a first or a second power supply bus. The first and second power supply busses are mutually isolated from each other and are of the same polarity. The ESD protected circuit includes a first ESD protection circuit connected to the first power supply bus. A second ESD protection circuit is also provided which is connected to the second power supply bus. A third ESD protection circuit is connected between the first and second power supply busses. The third ESD protection circuit is for selectively connecting the first and second power supply busses only during an ESD event so that ESD energy applied to one of the first or second power supply busses couples to a second one of the first or second power supply busses. ESD energy coupled between the first and second power supply busses is also coupled through at least one of the first or second ESD protection circuits to ground.

Output ESD protection using dynamic-floating-gate arrangement

A dynamic-floating-gate arrangement is used to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, by suitably dynamically floating the gates of the NMOS/PMOS buffers using a small-dimension CMOS device having its drain connected to the gate of an unused CMOS buffer, its source connected to one of two voltage sources, and its gate connected between a resistance, that is connected between the two voltage sources, and a capacitance connected between the resistance and the same one of the two voltage sources as the source of the small-dimension CMOS device.

CIRCUIT FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES OF TRIGGERING SUBSTRATE ON AN INTEGRATED CIRCUIT WITH DEPTH OF INTEGRATION

Circuit de protection contre les décharges électrostatiques de déclenchement de substrat destiné à être utilisé sur un circuit intégré à profondeur d'intégration inférieure au micron pour la protection contre les décharges électrostatiques du circuit intégré. Le circuit de protection contre les décharges électrostatiques est compris entre une extrémité d'entrée (IP) et le circuit interne (40) du circuit intégré formé sur un substrat. Le circuit de protection contre les décharges électrostatiques utilise une opération de déclenchement de substrat pour déclencher les transistors de protection contre les décharges électrostatiques, formés dans les puits N du substrat, dans l'état de conduction afin de dériver le courant de décharge électrostatique à la masse. Le circuit de protection contre les décharges électrostatiques permet de fabriquer une structure de semi-conducteur simplifiée, tout en fournissant néanmoins un niveau accru de capacité de protection contre les décharges électrostatiques pour le circuit intégré à profondeur d'intégration inférieure au micron. Circuit for protection against electrostatic discharges triggering the substrate intended to be used on an integrated circuit with integration depth less than one micron for protection against electrostatic discharges of the integrated circuit. The ESD protection circuit is between an input end (IP) and the internal circuit (40) of the integrated circuit formed on a substrate. The ESD protection circuit uses a substrate tripping operation to trip the ESD transistors, formed in the N wells of the substrate, in the conduction state to derive the electrostatic discharge current at the mass. The ESD protection circuit enables a simplified semiconductor structure to be fabricated, while still providing an increased level of ESD protection capability for the integrated circuit with an integration depth of less than one micron.

ESD protection circuit with active triggering

Liquid crystal display apparatus and bandgap reference circuit thereof

Power-rail esd clamp circuit for mixed-voltage i/o buffer

A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.

Output buffer with process and temperature compensation

An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.

ESD protection design with turn-on restraining method and structures

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

Turn-on-efficient bipolar structures with deep n-well for on-chip esd protection

A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Mixed voltage input/output buffer having low-voltage design

A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

ESD protection for open drain I/O pad in integrated circuit with parasitic field FET devices

An open drain FET driver circuit at an input-output pad of a semiconductor chip and a frame of the same conductivity type as the drain and source diffusions of the driver is formed around the driver (or partly around the driver). The frame is connected to Vdd and forms the diffusion for the Vdd end of a field FET. The drain of the driver forms the diffusion for the pad end of this field FET and the pad to Vdd FET breaks down in response to an ESD voltage between the pad and Vdd and provides a path for ESD current that the open drain driver itself does not provide. Optionally, a second field FET is formed between the source of the driver FET and the frame and this FET conducts an ESD current between the pad and Vdd in series with the driver. With this cell array structure, the junction capacitance which the ESD protection devices contribute to the pad can be significantly reduced for high speed I/O applications.

Transient voltage detection circuit

The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation

A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

2xvdd-tolerant logic circuits and a related 2xvdd-tolerant i/o buffer with pvt compensation

Latchup protection circuit for integrated circuits on chip

Silicon controlled rectifier for the electrostatic discharge protection

The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.