ANCESTRAL DENGUE VIRUS ENVELOPE PROTEIN SEQUENCE

Disclosed is a dengue virus envelope protein sequence derived via ascertainment of a most recent common ancestor of the three dengue serotype variants, DENV-I, DENV-2, DENV-3 and DENV-4. This synthetic dengue virus envelope protein can be used as a tetravalent vaccine in the preventinon of dengue fever, dengue hemorrhagic fever and dengue septic shock.

Microcurrent controlled capillary tube electrophoresis liquid core waveguide fluorescence testing apparatus

A micro flow control capillary electrophoresis liquid core waveguide fluorescence detector includes a liquid core waveguide capillary, a laser light source, a photodetector, a high-voltage power supply, an electrode, a liquid storage container, a sample tube, a pinhole diaphragm, a filter and a shadow shield; the device makes use of a liquid core waveguide phenomenon and uses the same liquid core waveguide capillary as a capillary electrophoresis separation channel and for fluorescence signal transduction. In the invention, the light given out by the laser light source can be not focused by a lens but directly radiates on the liquid core waveguide capillary through the pinhole diaphragm; the fluorescence led out by the outlet port of the liquid core waveguide capillary can not be collected by the lens but directly enters into the photodetector through the filter. The liquid core waveguide capillary is taken as a micro flow control capillary electrophoresis separation channel and an optical ...

Novel input shaft clamping groove opposite side detection tool

The utility model discloses a novel tool for detecting opposite sides of an input shaft clamping groove. The device comprises a scale plate, a carrying table, a connecting mechanism and a fixing mechanism, the connecting mechanism is located on the surface of one side of the scale plate. The connecting mechanism comprises a fixed button; one side of the fixed button is positioned outside the scaleplate; a first mounting groove is formed in the scale plate, a second mounting groove is formed in the carrying table, a first clamping groove is formed in the surface of one side of the second mounting groove, a first connecting plate is arranged in the first mounting groove, and the surface of one side of the first connecting plate is fixedly connected with the surface of one side of a fixing button; according to the utility model, through the arrangement of the fixing button, the situation that the scale plate is not firmly connected with the carrying table and is likely to deviate is effectively ...

Lockbox for mitigating same origin policy failures

Systems and methods to manage same-origin-policy (SOP) failures that occur in a computing environment are provided. In an illustrative implementation, an exemplary computing environment comprises a lockbox module, and an instruction set comprising at least one instruction directing the lockbox module to process data and/or computing application execution commands representative of and a request for a selected operation/feature according to a selected SOP management paradigm. In the illustrative implementation, the SOP management paradigm comprises one or more instructions to deploy a lockbox computing application element allowing for the management, monitoring, and control of computing application features/operations operable under a same origin policy.

Method and apparatus providing shared pixel architecture

Methods and apparatuses using pixels with shared readout circuits are used to increase pixel fill factor and operation efficiency.

Online AD serving

Dual isolation for image sensors

HYBRID IMAGE SENSOR

A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors.

Method and apparatus for reducing dark current and hot pixels in CMOS image sensors

Methods and apparatuses for reducing dark current and hot pixels in CMOS image sensors. A pixel apparatus includes a photosensor capable of generating dark current, a floating diffusion region coupled to the photosensor by way of a charge transfer transistor, a rest transistor connected between the floating diffusion region and an array pixel supply voltage. The array supply voltage varies between first and second voltages when sampling pixel signals from the pixel.

Electronic blood pressure gauge adopting 4G communication

The utility model discloses an electronic blood pressure gauge adopting a 4G communication, which comprises a blood pressure measuring unit module and a TD-LTE (Time Division Long Term Evolution) sending module connected with the blood pressure measuring unit module, wherein the blood pressure measuring unit module transmits a blood pressure signal to the TD-LTE module, and the TD-LTE module sends data wirelessly. Meanwhile, blood pressure measurement data can be sent to mobile terminals of private doctors, families, community services and the like in a short message mode, and users can directly carry out video medical service with a medical mechanism by the 4G communication technology. The users can check the blood pressure measurement data in a mode of receiving the short message or logging in a WEB website by terminal equipment, such as mobile phones, PCs (Personal Computers) and the like to check the blood pressure data and an analysis result.

Combustion enhancement method for stamping mode plasma assisted kerosene cracking

The invention discloses a combustion enhancement method for ramjet mode plasma assisted kerosene cracking, a ramjet mode plasma assisted kerosene cracking combustion enhancement engine is adopted, the ramjet mode plasma assisted kerosene cracking combustion enhancement engine comprises a ramjet combustion chamber, a kerosene cooling channel and a plasma generator, the kerosene cooling channel is arranged in a shell of the ramjet combustion chamber, and the plasma generator is arranged in the shell of the ramjet combustion chamber. The inlet of each group is used for being connected with a liquid kerosene pipeline, and the outlet end of each group is connected with a connecting pipe arranged outside the stamping combustion chamber; an outlet of the connecting pipe is divided into a plurality of circulation pipelines in parallel, the outlet end of each circulation pipeline communicates with the ramjet combustion chamber, and each circulation pipeline is provided with a plasma generator used ...

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from atop surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Vertically Stacked Image Sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. 1. (canceled)2. An image sensor , comprising: a first photodetector; and', 'a first trigger gate operably connected between the first photodetector and a first storage node;, 'a first pixel comprising a second photodetector; and', 'a second trigger gate operably connected between the second photodetector and a second storage node; and, 'a second pixel comprisinga mixing gate operably connected to the first photodetector and to the second photodetector and configured to selectively connect the first and the second photodetectors together to balance charge between the first and the second photodetectors.3. The image sensor as in claim 2 , wherein the first storage node and the second storage node comprise one storage node and the image sensor further comprises:a reset gate operably connected to the storage node; anda readout gate operably connected to the storage node.4. The image sensor as in claim 2 , wherein the mixing gate comprises a first mixing gate and the image sensor further comprises: a third photodetector; and', 'a third trigger gate operably connected between the third photodetector and the storage node; and, 'a third pixel comprisinga second mixing gate operably connected to the second photodetector and to the third photodetector and ...

WEBSITE LOGIN METHOD AND APPARATUS

The present application provides example website login methods and apparatuses. One example method includes identifying a website jump trigger indication to jump from a first website to a second website. A first token is then obtained from a cookie store of the web browser, the first token associated with a website identifier of the second website and a device fingerprint indicating a running environment at a time when the password-free proxy login was previously set. In response to determining that a current running environment corresponds to the device fingerprint, a second token corresponding to the first token is obtained, wherein the second token comprises an access token indicating that the second website grants password-free login permissions. A password-free login request is sent to the second website including the second token. In response to the second website verifying the second token, the second website is logged into without a password.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip 5 stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Vertically stacked image sensor

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a 5 transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row 0 select gate.

Creating arbitrary patterns on a 2-D uniform grid VCSEL array

An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

Website login method and apparatus

The present application provides example website login methods and apparatuses. One example method includes identifying a website jump trigger indication to jump from a first website to a second website. A first token is then obtained from a cookie store of the web browser, the first token associated with a website identifier of the second website and a device fingerprint indicating a running environment at a time when the password-free proxy login was previously set. In response to determining that a current running environment corresponds to the device fingerprint, a second token corresponding to the first token is obtained, wherein the second token comprises an access token indicating that the second website grants password-free login permissions. A password-free login request is sent to the second website including the second token. In response to the second website verifying the second token, the second website is logged into without a password.

Vertically Stacked Image Sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. 1. An image sensor , comprising: a photodiode for receiving light; and', 'a first transfer gate operably connected between the photodiode and a transfer channel shared by the two or more pixels;, 'two or more pixels, each pixel including, 'a plurality of pixels grouped into pixel cells, a pixel cell comprising, 'a photodiode chip comprising a second transfer gate operably connected between the shared transfer channel and a storage node; and', 'a storage transfer gate operably connected to the storage node;, 'multiple communication paths in communication with the pixel cell, each communication path comprising, 'a transistor array chip stacked vertically on the photodiode chip, the transistor array chip comprisingwherein the shared transfer channel extends vertically from the photodiode chip to the transistor array chip and transfers charge from at least one photodiode in the pixel cell to a respective communication path.2. The image sensor as in claim 1 , further comprising an anti-blooming gate operably connected to each photodiode in the pixel cell.3. The image sensor as in claim 1 , further comprising an anti-blooming and reset gate operably connected to the shared transfer channel claim 1 , wherein the anti-blooming and reset gate extends vertically ...

Vertically stacked image sensor

An image sensor, comprising: a photodiode having a full well capacity; a storage node configured with a charge storage capacity at least twice the full well capacity; a first transfer 5 gate linking the photodiode and the storage node; a storage gate linking the photodiode and the storage node, in series with the first transfer gate; a floating diffusion node; a second transfer gate linking the storage node and the floating diffusion node; and control circuitry operable to: activate the first transfer gate to transfer a first charge acquired in the photodiode during a first integration period to the storage node; deactivate the first transfer 10 gate to acquire a second charge in the photodiode during a second integration period, the second integration period beginning after an end of the first integration period; activate the first transfer gate to transfer the second charge acquired in the photodiode to the storage node; and activate the second transfer gate at an end of an image exposure ...

IDENTIFICATION OF MULTIVALENT VIRAL ENVELOPE PROTEIN EPITOPES

The present invention provides methods for identifying multivalent vaccin e antigens derived from envelope proteins.

OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS

Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. 1. An apparatus , comprising:a first circuit configured to protect a protected circuit from an over-voltage condition, the first circuit having a trigger circuit coupled to a first node and confirmed to trigger a shunt circuit to conduct current from the first node to a second node responsive to a voltage applied to the first node exceeding a trigger voltage, the trigger circuit matching circuits of the protected circuit.2. The apparatus of claim 1 , wherein the trigger circuit is further configured to trigger the shunt circuit at a plurality of trigger voltages.3. The apparatus of claim 2 , wherein the trigger circuit is configured to trigger the shunt circuit responsive to the voltage applied to the first node exceeding a first trigger voltage during claim 2 , power-up and further configured to trigger the shunt circuit responsive to the voltage applied to the first node exceeding a second trigger voltage during normal operation claim 2 , wherein the second trigger voltage is greater than the first trigger voltage.4. The apparatus of claim 1 , wherein the shunt circuit is configured to include a threshold condition for maintaining the shunt circuit in a low-impedance state.5. The apparatus of claim 4 , ...

Method and apparatus providing shared pixel straight gate architecture

A pixel array (550) has a plurality of pixels arranged in a set of four pixels, each having respective photosensors (501, 502, 503, 504). Each set of pixels shares a readout circuit (710); the readout circuit (710) includes a linearly-extending trunk located within the area between the first pair of photosensors (501, 503) and the second pair of photosensors (502, 504). Each pixel has a transfer gate (505, 506, 507, 508), at least a portion thereof being at an angle with respect to the photosensors (501, 502, 503, 504). The transfer gates (505), (506, 507, 508) are shared among two adjacent pixels in a row. This readout circuit layout increases the pixel fill factor.

Hybrid image sensor

A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors.

Over-limit electrical condition protection circuits and methods

Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Electric heating cable running control method

The invention provides an electric heating cable running control method which improves a control and power supply system on the basis that the PTC material of the electric heating cable has the capability of adjusting the temperature. The starting current is reduced and the service life of the electric heating cable can be prolonged by adopting the delayed starting and soft development technology; and the control precision can be improved by adopting a temperature acquiring and controlling technology of a singlechip. Compared with the prior art, in the electric heating cable running control method, since a digital temperature sensor is used, the temperature acquiring and controlling technology of the singlechip has the advantages of high temperature-measuring precision, favorable control performance and high reliability; and the requirement on the power supply capacity can be remarkably reduced by using the soft development starting technology and the time-shared control technology. The ...

Treatment method for collapse of steel sheet pile supporting structure

The invention discloses a treatment method for collapse of a steel sheet pile supporting structure, which comprises the following steps of: 1, carrying out foundation pit excavation on an area with serious collapse, judging whether the bottom of a first steel sheet pile is skirted and whether a second supporting structure is deformed, and if the skirting and the deformation are confirmed, judging whether the second supporting structure is deformed; the earthwork is backfilled to the position of the second supporting structure, and the damaged second supporting structure is reinforced; thirdly, a groove is excavated in the bottom of the foundation pit; fourthly, concrete is poured into the groove, a pipe pile is arranged, and the damaged second supporting structure is replaced; fifthly, the next section of groove is constructed, and the second step to the fourth step are repeated; sixthly, whether the protruding height of the concrete surface in the groove is abnormal or not is observed, ...

Refueling method and system for gas station

The invention relates to a refueling security technology of a gas station and discloses a refueling method and system for a gas station. The refueling method comprises the following steps: detecting whether a car has stalled according to a sensor arranged in a refueling region; if the car has not stalled is detected, forbidding an oil gun to refuel the car. Safe refueling of the refueling system for the gas station is realized by judging whether a car to be refueled has stalled or not, so that the refueling security of the gas station is greatly improved.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a 5 transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row 0 select gate.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip 5 stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Flowers stereoscopic cultivate device

The utility model provides a flowers stereoscopic cultivate device, including frame, cultivation frame, injection spray pipe and drowning groove, the frame is frame construction, and the frame both sides respectively set up a sprocket from top to bottom, and the frame below is provided with gear motor, is provided with the chain between two sprockets, is provided with on the chain to cultivate the frame, the frame is inside to be provided with one row of injection spray pipe, injection spray pipe one end and the water piping connection that advances who sets up in the frame outside, and one end is sealed in addition, is provided with one row of shower nozzle on the injection spray pipe, the frame below is provided with drowning groove, and the bottom of gullet is provided with the drain pipe falling. The device utilizes the mechanical equipment automation mechanized operation, realizes the three -dimensional cultivation, and area is little, and equipment operation is simple, and greatly ...

Contacts for CMOS imagers and method of formation

Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

Exposure control for image sensors

A method of operating an image sensor. Charge accumulated in a photodiode during a first sub-exposure may be selectively stored in a storage node responsive to a first control signal. Charge accumulated in the photodiode during a first reset period may be selectively discarded responsive to a second control signal. Charge accumulated in the photodiode during a second sub-exposure may be selectively stored responsive to the first control signal. Charge stored in the storage node from the first and second sub-exposures may be transferred to a floating diffusion node responsive to a third control signal.

Vertically stacked image sensor

An image sensor, comprising: a photodiode having a full well capacity; a storage node configured with a charge storage capacity at least twice the full well capacity; a first transfer 5 gate linking the photodiode and the storage node; a storage gate linking the photodiode and the storage node, in series with the first transfer gate; a floating diffusion node; a second transfer gate linking the storage node and the floating diffusion node; and control circuitry operable to: activate the first transfer gate to transfer a first charge acquired in the photodiode during a first integration period to the storage node; deactivate the first transfer 10 gate to acquire a second charge in the photodiode during a second integration period, the second integration period beginning after an end of the first integration period; activate the first transfer gate to transfer the second charge acquired in the photodiode to the storage node; and activate the second transfer gate at an end of an image exposure ...

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Online AD serving

Online ad hosting (e.g., hosting ads from one domain on a webpage from a different domain) is accomplished using a cross-domain frame (e.g., an inline frame (IFrame)), a secure inter-frame communications channel, and a source code interface (e.g., a set of application program interfaces (APIs)). That is, a cross-domain IFrame may be created in a host webpage, which can isolate an ad from the host webpage. An inter-frame communications channel may be utilized to communicate between the contents of the cross-domain frame and the host webpage. Further, a source code interface may be used to communicate a host's preferences for an ad's parameters and restrictions.

Modular electrostatic discharge (ESD) protection

In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

Imaging method, apparatus, and system providing improved imager quantum efficiency

A method, apparatus, and system that provides one or more charge collecting protection regions in a pixel array, each formed below a storage region of a pixel cell, but not below at least one photosensor of one pixel of the array. The storage region includes a floating diffusion region and/or a storage gate in the pixel cell of the imaging device. The protection regions can keep stray charges from reaching the storage regions.

HYDROGEN GAS PRODUCING DEVICE

According to the present invention, a hydrogen gas producing device comprises: an electrolyte storage body storing an electrolyte which is a plasma electrolytic oxidation (PEO) surface treatment solution; an anode, made by inserting a magnesium alloy material or aluminum alloy material into the electrolyte, as well as a cathode, made by inserting an electrode bar into the electrolyte, with electricity applied between the anode and cathode; a hydrogen collector placed to surround an upper opening of the electrolyte storage body; a filter installed near an outlet of an opening of the hydrogen collector; a condenser connected to an outlet of the filter to compress and transfer hydrogen gas going through the filter; a condensing distributor connected to an outlet of the condenser to recompress and distribute the hydrogen gas transferred by the condenser; and a plurality of hydrogen storage containers connected to an outlet of the condensing distributor to store the hydrogen gas. As such, since ...

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Image sensor having full well capacity beyond photodiode capacity

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Stacked backside illuminated SPAD array

A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

EXPOSURE CONTROL FOR IMAGE SENSORS

A method of operating an image sensor. Charge accumulated in a photodiode during a first sub-exposure may be selectively stored in a storage node responsive to a first control signal. Charge accumulated in the photodiode during a first reset period may be selectively discarded responsive to a second control signal. Charge accumulated in the photodiode during a second sub-exposure may be selectively stored responsive to the first control signal. Charge stored in the storage node from the first and second sub-exposures may be transferred to a floating diffusion node responsive to a third control signal.

Medical rescue system

The utility model discloses a medical rescue system. The system comprises a time acquisition device, a time reminding device and a server, the time acquisition device comprises a time acquisition unitand a control unit, rFID recognizer, wherein the identification module is used for identifying an RFID wrist strap identifier worn by a target patient when the target patient carries out each medicallink, taking a time point at which the RFID wrist strap identifier is identified as node time when the target patient carries out each corresponding medical link, and uploading the wrist strap identifier and the node time to the server; the server is used for sending the node time corresponding to the wristband identifier to the time reminding device; and the time reminding device is used for outputting the received node time corresponding to the wrist strap identifier to remind medical staff, so that the rescue time of the patient is refreshed automatically in real time to remind the medicalstaff ...

Ancestral Hepatitis C virus envelope protein sequence

The present invention provides ancestral sequences for hepatitis C virus (HCV) envelope proteins, as well as uses for such sequences in inducing protective immune responses in subjects infected or at risk of infection with HCV.

Image Sensor with a Cross-Wafer Capacitator

One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.

Image sensor with buried light shield and vertical gate

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.

Contacts for CMOS imagers and method of formation

Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

DUEL PLASMA ELECTROLYTIC OXIDATION SURFACE TREATMENT METHOD OF MAGNESIUM ALLOY PRODUCT

The present invention relates to a duel plasma electrolytic oxidation (PEO) surface treatment method of a magnesium alloy product. According to the present invention, the dual PEO surface treatment method for treating a surface of a magnesium alloy product comprises: a first etching step of immersing a magnesium alloy product in a nitric acid-based weak acidic first electrolyte to perform primary etching; a first washing step of primary washing the primarily etched magnesium alloy product with water; a second etching step of immersing the primarily washed magnesium alloy product in a phosphoric acid-based weak acidic second electrolyte to perform secondary etching; a second washing step of primarily washing the secondarily etched magnesium alloy product with water; a first surface treatment step of immersing the secondarily washed magnesium alloy product in a first surface treatment solution to perform PEO surface treatment so as to primarily form an oxide film of a surface of the magnesium ...

Image sensor with buried light shield and vertical gate

Image sensor having pixels with different integration periods

An image sensor includes pixels that accumulate charge during a first integration period and pixels that accumulate charge during shorter second integration periods when an image is captured. The pixels having the shorter second integration period accumulate charge at two or more different times during the first integration period. Charge is read out of the pixels associated with the first integration period at the end of the first integration period, while charge is read out of the pixels having the second integration period at the end of each second integration period.

COMPOSITION OF DUEL PLASMA ELECTROLYTIC OXIDATION SURFACE TREATMENT SOLUTION FOR MAGNESIUM ALLOY PRODUCT

The present invention relates to a composition of a duel plasma electrolytic oxidation (PEO) surface treatment solution for a magnesium alloy product. According to the present invention, in a composition for dual PEO surface treatment of the magnesium alloy product, a first surface treatment solution used for primary PEO surface treatment is formed by mixing 100 parts by weight of water with 1 to 20 parts by weight of KOH, 1 to 10 parts by weight of Na_3PO_4, 1 to 5 parts by weight of NaF, and 1 to 10 parts by weight of NH_4F with respect to 100 parts by weight of water. Moreover, a second surface treatment solution used for secondary PEO surface treatment is formed by mixing 100 parts by weight of water with 1 to 30 parts by weight of NaOH, 1 to 10 parts by weight of Na_3PO_4, and 1 to 10 parts by weight of NH_4F with respect to 100 parts by weight of water. Accordingly, since the dual PEO surface treatment is sequentially performed by the first and second surface treatment solutions, ...

Image sensor with buried light shield and vertical gate

一影像感測器中之一像素可包括安置於一個基板中之一光電偵測器及一儲存區，或安置於一個基板中之一光電偵測器及安置於另一基板中之一儲存區。一內埋光屏蔽件安置於該光電偵測器與該儲存區之間。諸如一浮動擴散區之一感測區可鄰近於該儲存區，其中該內埋光屏蔽件安置於該光電偵測器與該儲存區及該感測區之間。當該光電偵測器及該儲存區安置於單獨基板中時，一垂直閘可穿過該內埋光屏蔽件而形成且用以起始電荷自該光電偵測器及該儲存區之轉移。鄰近於或圍繞該垂直閘形成之一轉移通道提供該電荷自該光電偵測器轉移至該儲存區之一通道。

USER INTERFACE FOR ONLINE ADS

A user interface may be utilized to allow a user to control display properties of online ad content on a hosting webpage (e.g., hosting ads from one domain on a webpage from a different domain). This may be accomplished by creating a cross-domain frame in the hosting webpage, which can contain the ad content. An instantiation of a user interface may be created on the hosting webpage that has an ability to control display properties of the cross-domain frame, thereby controlling display properties of the ad content in the cross-domain frame. Further, a task manager may be utilized as part of the user interface to facilitate a host of the hosting webpage to manage ad content.

Hot oil-circulating automatic heating device of large-size transformer

The invention relates to a hot oil-circulating automatic heating device of a large-size transformer, comprising a circulating part, a heating device and an electric control part, wherein the circulating part comprises a high-speed centrifugal pump and a circulating pipeline, and the high-speed centrifugal pump is arranged at the inlet end of the circulating pipeline in which the heating device is arranged; the electric control part comprises a power supply control device and an oil temperature control device, wherein the power supply control device comprises a main power supply air switch, a heating device control switch, an alternating-current contactor and an outlet terminal, the main power supply air switch is connected with the heating device control switch through a working bus, the heating device control switch is connected with the alternating-current contactor, and the alternating-current contactor is connected with the heating device through the outlet terminal; and the oil temperature ...

Stability maintaining system for bored pile construction and construction method thereof

The invention provides a stability maintaining system for bored pile construction and a construction method thereof. The stability maintaining system for drilling pile construction comprises a pile casing and a soil layer reinforcing assembly. The pile casing and the soil layer reinforcing assembly extend in the vertical direction, the soil layer reinforcing assembly surrounds the radial outer side of the pile casing, and a limiting space is formed between the soil layer reinforcing assembly and the pile casing; the soil layer reinforcing assembly comprises a plurality of reinforcing pieces arranged in the circumferential direction of the pile casing, and all the reinforcing pieces extend in the vertical direction. According to the stability maintaining system for drilling pile construction, usability can be improved, construction efficiency is improved, construction cost is reduced, a thickened steel casing does not need to be specially manufactured, and waste of concrete can be reduced ...

Apparatus providing shared pixel straight gate architecture

Hybrid image sensor

A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors.

Four-axis four-linkage vertical machining centre

The invention belongs to the field of numerical control machines and particularly relates to a four-axis four-linkage vertical machining centre. The four-axis four-linkage vertical machining centre comprises a workbench and a stand column which are respectively and fixedly arranged on a lathe bed; the upper side of the stand column is provided with a vertical milling head extending out toward one side of the workbench; the stand column is provided with an axis-Z driving device for driving the vertical milling head to move up and down along the stand column; an axis-X driving device and an axis-Y driving device for respectively driving the workbench to slide along the upper part of the lathe bed are arranged between the lathe bed and the workbench; and the workbench is provided with a numerical control dividing head for clamping, rotating and positioning workpieces. As the four-axis four-linkage vertical machining centre comprises the axis-X driving device, the axis-Y driving device, the ...

AUTOMATION-RESISTANT, ADVERTISING-MERGED INTERACTIVE SERVICES

Systems and methodologies for implementing automation-resistant interactive computing services are provided herein. Function invocation mechanisms can be utilized as described herein to facilitate invocation and/or activation of one or more functions of an interactive service upon performance of an interaction falling within a predefined class of interaction with selected multimedia content. The described functionality invocation mechanisms can operate similarly to a traditional captcha image by requiring interaction that is easily understandable and performable by a human user but is prohibitively difficult for an automated program to carry out. Techniques such as masking relationships between user interaction and function invocation and varying elements of the selected multimedia content for respective accesses can be utilized to provide additional resistance to automation. Described invocation mechanisms can additionally be merged with advertising, which can optionally be targeted to ...

Method and apparatus providing shared pixel straight gate architecture

A pixel array (550) has a plurality of pixels arranged in a set of four pixels, each having respective photosensors (501, 502, 503, 504). Each set of pixels shares a readout circuit (710); the readout circuit (710) includes a linearly-extending trunk located within the area between the first pair of photosensors (501, 503) and the second pair of photosensors (502, 504). Each pixel has a transfer gate (505, 506, 507, 508), at least a portion thereof being at an angle with respect to the photosensors (501, 502, 503, 504). The transfer gates (505), (506, 507, 508) are shared among two adjacent pixels in a row. This readout circuit layout increases the pixel fill factor.

Image sensor with a cross-wafer capacitor

One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.

VERTICALLY STACKED IMAGE SENSOR

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. 1. An image sensor for an electronic device , comprising: at least one photodiode for receiving light;', 'a transfer gate extending vertically from a top surface of the photodiode chip;, 'a photodiode chip comprising a floating diffusion node in communication with the at least one photodiode;', 'a reset gate in communication with the at least one photodiode;', 'a source follower gate in communication with the floating diffusion node; and', 'a row select gate in communication with the source follower gate and the floating diffusion node; and, 'a transistor array chip in communication with the photodiode chip and vertically stacked on the photodiode chip, the transistor array chip comprisinga logic chip operably vertically stacked on the transistor array chip and in communication therewith; wherein a semiconductor transfer channel;', 'an oxide layer surrounding an outer perimeter surface of the transfer channel;', 'a polysilicon layer at least partially surrounding an outer perimeter surface of the oxide layer; and', 'a metal layer in communication with the transfer channel, wherein the transfer channel extends vertically from the to surface of the photodiode chip and the metal layer communicatively connects the transfer gate to the transistor array chip; ...

ONLINE AD SERVING

Online ad hosting (e.g., hosting ads from one domain on a webpage from a different domain) is accomplished using an insulator cross-domain frame (e.g., an inline frame (IFrame)), into which a third party may load content, source code to detect events associated with the third party content (e.g., detecting if ad content wishes to expand), and a communicator same-domain IFrame for sending requests to the host webpage associated with detected events. That is, a cross-domain IFrame may be created in a host webpage, which can isolate an ad from the host webpage. A communicator frame may be utilized to communicate text messages between the contents of the cross-domain frame and the host webpage. Further, an API can be used to apply parameters, restrictions and allowable events to the third party content in the insulator IFrame.

Exposure control for image sensors

Method and apparatus providing imager pixels with shared pixel components

The disclosed embodiments employ shared pixel component architectures that arrange the shared pixel components for a group of pixels within different pixels of the group.

Image Sensor Having Pixels with Different Integration Periods

An image sensor includes pixels that accumulate charge during a first integration period and pixels that accumulate charge during shorter second integration periods when an image is captured. The pixels having the shorter second integration period accumulate charge at two or more different times during the first integration period. Charge is read out of the pixels associated with the first integration period at the end of the first integration period, while charge is read out of the pixels having the second integration period at the end of each second integration period. 1. An imaging system , comprising:an image sensor having a plurality of pixels, wherein a first portion of the pixels accumulate charge for a first integration period and a second portion of the pixels accumulate charge for a shorter second integration period, wherein the second portion of the pixels having the shorter second integration period accumulate charge two or more times during the first integration period.2. The imaging system as in claim 1 , further comprising readout circuitry operatively connected to the plurality of pixels.3. The imaging system as in claim 2 , further comprising a processor operatively connected to the readout circuitry claim 2 , wherein the processor is adapted to enable the readout circuitry to read charge out of the second portion of the pixels at two or more different times.4. The imaging system as in claim 3 , wherein the processor is adapted to enable the readout circuitry to read charge out of the first portion of the pixels at the end of the first integration period.5. The imaging system as in claim 3 , wherein the processor is adapted to adjust which pixels are associated with the first and second integration periods.6. The imaging system as in claim 3 , wherein the processor is adapted to determine an amount of time for each second integration period.7. A method for capturing an image claim 3 , the method comprising:beginning a first integration period for a ...

Communication method with Socket server and online transaction management system

The invention discloses a communication method with a Socket server and an online transaction management system. The management system comprises an online transaction port main control module, a long connection transmission defending module and a long connection receipting defending module, wherein the online transaction port main control module is used for putting a first message with a pre-set format into a transmit queue and recording a serial number of the first message; the long connection transmission defending module is used for reading the first message from the message transmit queue, converting the format of the first message into a message format used in Socket server communication and sending the first message to a Socket server; the long connection receipting defending module is used for receiving a second message which has the same serial number with the first message and is generated after the first message is processed through the Socket server, converting the format of ...

Frequency converter control cabinet

The utility model discloses a frequency converter control cabinet, which comprises a cabinet body, one side of the cabinet body is movably connected with a sealing door, the interior of the cabinet body is fixedly connected with two groups of mounting racks, the mounting racks are provided with a plurality of mounting holes, the mounting racks are connected with sliding rails through mounting hole bolts, the sliding rails are connected with sliding blocks in a sliding manner, and the sliding blocks are fixedly connected with the cabinet body. According to the utility model, the two groups of mounting racks are mounted inside the cabinet body, the mounting racks are provided with a plurality of groups of mounting holes for mounting the slide rails at different heights, and then the height of the mounting plate is adjusted and mounted, the slide blocks on the slide rails can slide horizontally, and when the mounting plate is used for mounting a frequency converter, the mounting plate can ...

COMPOSITION OF PLASMA ELECTROLYSING OXIDATION SURFACE TREATMENT SOLUTION FOR ALUMINUM ALLOY PRODUCTS

The present invention relates to a composition of a plasma electrolyzing oxidation (PEO) surface treatment solution for aluminum alloy products. The composition of a PEO surface treatment solution for aluminum alloy products is formed by mixing potassium hydroxide (KOH) of 1 to 35 parts by weight, sodium hydroxide (NaOH) of 1 to 20 parts by weight, ammonium hydroxide (NH4OH) of 1 to 10 parts by weight, potassium fluoride (KF) of 1 to 10 parts by weight, sodium fluoride (NaF) of 1 to 5 parts by weight, sodium pyrophosphate (Na4P2O7) of 1 to 5 parts by weight, and alumina (Al2O3) powder of 1 to 5 parts by weight in water with respect to water of 100 parts by weight. Therefore, the composition of a PEO surface treatment solution for aluminum alloy products can form a firm, compact and uniform oxide film on the surface of the aluminum alloy product since securing solidity and compactness of the film and forming pores of a fine size. COPYRIGHT KIPO 2018 ...

OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS

Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

Multifunctional web camera

The invention belongs to the technical field of security and protection, and discloses a multifunctional web camera with the functions of snapshoting, alarm recording, information push and remote control over protection deployment and protection withdrawal, the function of a doorbell and the like. The multifunctional web camera comprises a camera system, an Ethernet interface, a wireless communication module and a sensor. Both the Ethernet interface and the wireless communication module are connected with the camera system, and the wireless communication module is in communication with the sensor. The camera system is used for acquiring monitoring information and transmitting the monitoring information to the Ethernet interface. The Ethernet interface is used for remotely transmitting the information received from the camera system. The wireless communication module is used for receiving and processing sensor signals and sending the sensor signals to the camera system. The sensor is used ...

Image sensor with buried light shield and vertical gate

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.

APPLICATION ACTIVATION METHOD AND APPARATUS AND ELECTRONIC EQUIPMENT

Embodiments of the present invention provide an application activation method and apparatus and electronic equipment. The activation method includes: determining one or more recommended application(s) according to information on practice of use of applications; and activating the one or more recommended application(s). With the embodiments of the present invention, many applications expected to be used need not to be looked for, thereby reducing a large quantity of repeated operations, and obtaining better user experience. 1. An application activation method , comprising:determining one or more recommended application(s) according to information on a use habit for applications; andactivating the one or more recommended application(s).2. The activation method according to claim 1 , wherein the one or more recommended application(s) is(are) determined according to the information on a use habit for applications in case of receiving triggering information inputted by a user claim 1 , or in case of receiving triggering information transmitted by other equipment claim 1 , or in case of satisfying a predefined condition.3. The activation method according to claim 1 , wherein the predefined condition comprises one piece of the following information or any combination thereof: detection information detected by a sensor reaching a predefined threshold value claim 1 , reaching a predefined time claim 1 , being positioned at a predefined location claim 1 , a startup order of two or more applications claim 1 , accessing to a predefined network and using a predefined ID card.4. The activation method according to claim 1 , wherein after the determining one or more recommended application(s) according to the information on a use habit for applications claim 1 , the activation method further comprises:displaying discriminatively icons of two or more applications;receiving input information of the user for selecting an application from the two or more applications; andstarting up ...

Image sensor with flexible pixel summing

Over-limit electrical condition protection circuits for integrated circuits

Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit ...

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Vertical 4-way shared pixel in a single column with internal reset and no row select

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Methods of forming a conductive interconnect in a pixel of an imager and in other integraed circiutry

COMPOSITION OF ELECTROLYTE SOLUTION TO GENERATE HYDROGEN GAS

The present invention relates to a composition of an electrolyte solution to generate hydrogen gas, which is an electrolyte solution used for a plasma electrolytic oxidation (PEO) surface treatment process for a magnesium or aluminum alloy material, and generates hydrogen. According to the present invention, the composition of an electrolyte solution to generate hydrogen gas is formed by mixing 100 parts by weight of water with 0.1 to 23 parts by weight of NaOH, 0.1 to 10 parts by weight of Na_3PO_4, 0.1 to 20 parts by weight of KOH, 0.1 to 5 parts by weight of Na_4P_2O_7, 0.1 to 2 parts by weight of aqueous ammonia solution, and 0.1 to 10 parts by weight of Ca(OH)_2 based on 100 parts by weight of water. Accordingly, electrolysis is promoted by the aqueous ammonia solution and the Ca(OH)_2, and hydrogen is generated during the PEO surface treatment process for a magnesium or aluminum alloy material by a volume ratio of 110 to 120 in comparison with a conventional electrolysis method, thereby ...

COMBINATION ESD PROTECTION CIRCUITS AND METHODS

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node. 1. An integrated circuit , comprising:a thyristor formed from a plurality of doped regions; anda transistor with a source;wherein one of the plurality of doped regions of the thyristor is shared with the source of the transistor.2. The integrated circuit of claim 1 , wherein none of the plurality of doped regions of the thyristor is shared with a drain of the transistor.3. The integrated circuit of claim 1 , wherein the thyristor is configured as a protection circuit claim 1 , the transistor is a protected transistor claim 1 , and a drain of the protected transistor is not used as part of the protection circuit.4. The integrated circuit of claim 1 , wherein a second doped region of the plurality of doped regions of the thyristor is also the body of the transistor.5. The integrated circuit of claim 4 , wherein the second doped region of the plurality of doped regions is coupled to a power node through a variable resistance.6. The integrated circuit of claim 4 , wherein the thyristor is configured to be triggered responsive to an increased voltage of the second doped region of the plurality of doped regions.7. An integrated circuit claim 4 , comprising:a thyristor formed from a plurality of doped regions; anda transistor with a drain;wherein none of the ...

CONTACTS FOR CMOS IMAGERS AND METHOD OF FORMATION

Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

Intelligent wireless voltage collecting instrument

The invention discloses an intelligent wireless voltage collecting instrument. A sixteen-analog-signal collecting module is connected with a sixteen-switch circuit module through a circuit, and each analog signal is controlled by one analog switch. The sixteen-switch circuit module is connected with a sixteen-bit A/D converting module through a circuit. The collected analog signals are converted into digital signals through the sixteen-bit A/D converting module. The sixteen-bit A/D converting module is connected with a single-chip microcomputer through a circuit. The single-chip microcomputer is connected with a first Bluetooth module through a circuit. The first Bluetooth module is connected with a second Bluetooth module in a wireless Bluetooth mode, receives data in a Bluetooth wireless mode or transmits data to the second Bluetooth module in a Bluetooth wireless mode. The second Bluetooth module is connected with an upper computer through a circuit. The upper computer is connected with ...

Combination ESD protection circuits and methods

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.

TDSCDMA wireless alarming telephone

The invention discloses a TDSCDMA wireless alarming telephone, which comprises a TD-SCDMA wireless communication module, wherein the TD-SCDMA wireless communication module is externally connected with an alarm detecting module; and the alarm detecting module comprises a connected external sensor, a signal receiving circuit used for receiving a singlechip signal, and a signal processing circuit, and wherein the signal processing circuit is electrically connected with the TD-SCDMA wireless communication module. The invention not only has the specific functions of the existing TD-SCDMA telephone, but also can receive alarming signals sent by external sensor probes such as an external wireless infrared detector, a wireless gate magnet, a wireless help button, a wireless gas sensor, a wirelesssmoke sensing fire detector and the like, and the invention gives an alarm by the method that the TD-SCDMA wireless module sends short messages to and call an appointed user cell phone or a platform server ...

Detouring in scripting systems

A system described herein includes a receiver component that receives third party code for execution in a host environment, wherein the third party code corresponds to a dynamic programming language, and wherein the third party code has at least one object reference to a first object that is used by the third party code. A detouring component automatically replaces the first object referenced by the third party code with a proxy object such that the third party code at runtime calls the proxy object instead of the first object.

Automatic processing system of banking business state and automatic information state switching method

The invention discloses an automatic processing system of banking business state and an automatic information state switching method. The automatic processing system comprises a state table maintaining unit, a state detecting unit, a record searching unit and a state updating unit. The state table maintaining unit can prestore records of current state and the next state corresponding to all kinds of banking business in a state table. The state detecting unit can automatically detect the current state of the banking business when the banking business arrives. The record searching unit can search the corresponding record in the state table according to the detected current state of the banking business so as to acquire the next state of the records. The state updating unit can revise the current state of the banking business to the next state in the records. The system and the method provided here can enable the state to be transparent to programs, on-line programs will not show specific ...

Methods of Forming a Conductive Interconnect in a Pixel of an Imager and in Other Integrated Circuitry

A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first ...

Dual isolation for image sensors

Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are formed in the periphery. Array isolation regions are disposed around at least a portion of at least some of the array devices and periphery isolation regions are disposed around at least a portion of at least some of the periphery devices. Within the semiconductor imager, the periphery isolation regions are configured differently from the array isolation regions. The semiconductor image sensor may be included in as part of an imaging system that includes a processor.

High-efficiency vertical emitters with improved heat sinking

A method for production of an optoelectronic device includes fabricating a plurality of vertical emitters on a semiconductor substrate. Respective top surfaces of the emitters are bonded to a heat sink, after which the semiconductor substrate is removed below respective bottom surfaces of the emitters. Both anode and cathode contacts are attached to the bottom surfaces so as to drive the emitters to emit light from the bottom surfaces. In another embodiment, the upper surface of a semiconductor substrate is bonded to a carrier substrate having through-holes that are aligned with respective top surfaces of the emitters, after which the semiconductor substrate is removed below respective bottom surfaces of the emitters, and the respective bottom surfaces of the emitters are bonded to a heat sink.

Vertically stacked image sensor

ELECTRO-STATIC DISCHARGE AND ELECTRIC OVERSTRESS PROTECTION STRATEGY FOR MICRO-CHIP ARRAY ON PANEL

A display system includes an array of light emitting diodes (LEDs), first and second driver chips, and one or more protection chips on a display substrate. The first and second driver chips are to drive a first group of LEDs of the array of LEDs and a second group of LEDs of the array of LEDs, respectively. Each protection chip includes one or more electro-static discharge (ESD) protection devices to assist with protecting the driver chips from damage caused by an ESD event. In one embodiment, each ESD protection device is connected between one or more signal lines, one or more power supply voltage lines, and an electrical ground line of the display substrate. In one embodiment, at least one protection chip comprises one or more electric overstress (EOS) protection devices to assist with protecting the driver chips from damage caused by an EOS event. 1. A display system comprising:a display substrate;an array of light emitting diodes (LEDs) on the display substrate;a first driver chip bonded to the display substrate, the first driver chip to drive a first group of LEDs of the array of LEDs;a second driver chip bonded to the display substrate, the second driver chip to drive a second group of LEDs of the array of LEDs;a first protection chip bonded to the display substrate, the first protection chip including one or more electro-static discharge (ESD) protection devices, wherein:the one or more ESD protection devices are connected through one or more signal lines of the display substrate, one or more power supply voltage lines of the display substrate, and an electrical ground line of the display substrate to the first and second driver chips, andthe first protection chip is to assist with protecting the first and second driver chips from damage caused by an ESD event.2. The display system of claim 1 , wherein:at least one of the first driver chip, the second driver chip, the first protection chip, or one or more of the LEDs in the array of LEDs is a micro device.3. ...

Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry

A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first ...

Image sensor with flexible pixel summing

An image sensor can include pixels that are grouped into subsets of pixels, with each subset including three or more pixels. A method for asymmetrical high dynamic range imaging can include capturing an image of a subject scene using a single integration time for all of the pixels. In a subset of pixels, charge in N pixels is read out and summed together. N represents a number that is between two and one less than a total number of pixels in the subset. Un-summed charge is read out from one pixel in the subset. The un-summed charge and the summed charge are combined when producing a high dynamic range image.

Many rings roof beam combination supporting construction

The utility model relates to a many rings roof beam combination supporting construction, its characterized in that: include interior ring roof beam, excircle ring beam, well ring roof beam, radiate the roof beam and enclose the purlin, interior ring roof beam, excircle ring beam and well ring position of sill in the same centre of a circle, radiation position of sill in interior ring roof beam with enclose between the purlin, radiate the roof beam with interior ring roof beam, excircle ring beam, well ring roof beam with enclose the purlin and link into an integrated entity. The utility model relates to a rationally, the atress is clear and definite, arrange nimble, stability is good, the stiffness big, control movement capability is strong, cubic metre of earth excavation is convenient, can save the time limit for a project greatly, under the prerequisite of assurance foundation ditch safety, has improved economy and social.

Rotating micro-example auto-introducing device

The invention relates to a rotary type micro-sample automatic leading-in device which comprises an integral sample tray, a capillary sampling probe, a step motor, a high-voltage power supply, an electrode, and a liquid storage pipe and is characterized in that the integral sample tray takes a shape of gear, specifically, liquid storage pools are evenly distributed on the outer edge of the circular tray body, and each of the liquid storage pools is opened with a hole; the outer wall of the sample inlet end of the capillary sampling probe is plated with a metal layer or a plurality of metal layers and the sample inlet end can be inserted into the hole of a liquid storage pool of the integral sample tray. When the integral sample tray rotates, the probe does not contact the body of the integral sample tray. The invention can realize automatic sample introduction and change without using any pump or valve, with the time of sample change being less than 0.2s and the rate of consumption of the ...

Electronic blood glucose meter adopting TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) communication

The utility model discloses the following technical scheme that: an electronic blood glucose meter adopting TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) communication, which comprises a blood glucose measuring module and a TD-SCDMA module; the TD-SCDMA module is connected with the blood glucose measuring module; and a blood glucose signal is input to the TD-SCDMA module by the blood glucose measuring module, and then the data is transmitted by the TD-SCDMA module in a wireless manner. In the utility model, the quantity and the time of stored blood glucose information are not limited, so that manual record is omitted, and storage and analysis for the stored data can be better achieved; and the data can be analyzed according to ages and clinical histories of users, thereby effectively and conveniently providing data for doctors or patients in analysis by stages in the future.

OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS

Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. 1. An apparatus , comprising:a trigger circuit coupled to a first node and to a protected circuit, the trigger circuit further configured to provide a leakage current responsive to a voltage provided to the first node exceeding a trigger condition; anda shunt circuit configured to conduct current from the first node to a second node responsive to the provided leakage current.2. The apparatus of wherein the shunt circuit comprises a circuit having a snapback electrical characteristic.3. The apparatus of wherein the shunt circuit comprises a silicon controlled rectifier.4. The apparatus of wherein the trigger circuit comprises a circuit that is matched to the protected circuit.5. The apparatus of wherein the trigger circuit comprises a transistor claim 1 , the transistor of the trigger circuit formed in a semiconductor doped well region in which at least a portion of the shunt circuit is formed.6. The apparatus of wherein the trigger condition comprises a voltage being applied to the first node exceeding a trigger voltage of the trigger circuit.7. The apparatus of wherein the trigger circuit comprises at least one transistor coupled to the first node and the second node.8. The apparatus of claim 1 , further ...

Combination esd protection circuits and methods

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.

EDGE BASED TEMPLATE MATCHING

A system for image processing includes determining edge pixels of a model image using an edge based technique, and an angular orientation for each of the edge pixels of the model image. The system determines a lower spatial resolution model image based upon the model image and determining respective angular orientations for the lower spatial resolution model image, and determines edge pixels of an input image using an edge based technique, and an angular orientation for each of the edge pixels of the input image. The system determines a lower spatial resolution input image based upon the input image and determining respective angular orientations for the lower spatial resolution input image, and matches the lower spatial resolution model image with the lower spatial resolution input image to determine candidate locations of an object within the image and based upon the candidate locations matching the input image with the model image. 1. A method for image processing comprising:(a) determining edge pixels of a model image using an edge based technique;(b) determining an angular orientation for each said edge pixels of said model image;(c) determining a lower spatial resolution model image based upon said model image and determining respective angular orientations for said lower spatial resolution model image;(d) determining edge pixels of an input image using an edge based technique;(e) determining an angular orientation for each of said edge pixels of said input image;(f) determining a lower spatial resolution input image based upon said input image and determining respective angular orientations for said lower spatial resolution input image;(g) matching said lower spatial resolution model image with said lower spatial resolution input image to determine candidate locations of an object within said input image;(h) based upon said candidate locations matching said input image with said model image; (a) wherein said matching is performed at a plurality of different ...

WEB-BASED WORKFLOW SERVICE VISUALIZATION AND NAVIGATION

Web workflow service information may include implementations, contracts, addresses, bindings, and other information that is sprinkled throughout source files, configuration files, and other locations. A service explorer extracts service information, and visualizes service information in a form that supports navigation, thereby helping developers understand and use workflow service information. A workflow service structure underlying the visualization is constructed with the extracted service information. A hierarchical node visualization of the service structure is displayed in a service explorer GUI. A developer navigates by expanding/contracting nodes, searching nodes, selecting nodes, and running tools with node-specific information, e.g., for testing, tracing, publication, workflow design, and so on. The visualization is automatically updated after service configuration changes. Node-specific source code is displayed for contract and implementation classes, and pertinent sections of configuration files are displayed for bindings and addresses. Derivation of endpoints, bindings, and addresses are displayed for implicitly set endpoints. 1. A computer-readable non-transitory storage medium configured with data and with instructions that when executed by at least one processor causes the processor(s) to perform a process for transforming web application workflow information , the process comprising the steps of:obtaining web application project files which include at least one workflow implementation source file and at least one workflow configuration file;extracting workflow service information from the web application project files, namely, extracting at least three of the following pieces of workflow service information: service class name, service contract name, service operation contract name, service endpoint address, service endpoint binding type, service implementation class name; andconstructing a workflow service structure based on the extracted workflow ...

VERTICAL 4-WAY SHARED PIXEL IN A SINGLE COLUMN WITH INTERNAL RESET AND NO ROW SELECT

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor. 110-. (canceled)11. A method of reading from a pixel circuit comprising a plurality of 4-way shared pixels in a column of a pixel array where each pixel circuit has a plurality of different colored pixels , said method comprising:applying a logic high signal on a reset control line to turn on a reset transistor, the reset transistor, when turned on, causing a reset voltage to be applied on a column line;applying a logic low signal on the reset control signal to turn off the reset transistor;applying a logic high signal to enable readout of the column line;reading out a pixel reset signal from the pixel circuit; andreading out a pixel image signal from the pixel circuit.12. The method of claim 11 , wherein said step of reading out the pixel reset signal further comprises:applying a logic high pulse on a sample and hold reset signal control line.13. The method of claim 12 , wherein said step of reading out the pixel reset signal further comprises:applying a logic high pulse on a transfer control line after the step of applying a logic high pulse on the sample and hold reset signal control line.14. The method of reading from a pixel circuit of claim 13 , wherein said step of reading out the pixel image signal further comprises:applying a logic high pulse on a sample and hold signal control line after the step of applying a logic high pulse on the transfer control line.1524-. (canceled)25. A method of reading from a pixel circuit comprising a plurality of at least four pixels in a first column of a pixel array claim 13 , each pixel including a photosensor and commonly electrically coupled to a storage region claim 13 ...

CALIBRATED IMAGE-SENSOR-BASED AMBIENT LIGHT SENSOR

An electronic device may be provided with an image sensor for capturing digital images. The image sensor may be used as part of image-sensor-based ambient light sensing circuitry for producing ambient light sensor readings. The image-sensor-based ambient light sensing circuitry may include a reference array. The reference array may be formed from an array of light sensor elements that are matched to elements in the image sensor but that are covered with a light blocking material. Control circuitry can measure current flow into the reference array and the image sensor array and can use current measurements from these arrays in producing a calibrated ambient light sensor reading. The control circuitry may make current measurements by measuring a decay time associated with the voltage of a discharging capacitor. A comparator, pulse generator, and switch may be used in periodically recharging the capacitor. The capacitor may be adjusted to ensure accurate readings. 1. Image-sensor-based ambient light sensing circuitry , comprising:an image sensor array;an optically-black reference sensor array; andcontrol circuitry that produces an ambient light sensor reading based on data from the image sensor array and the reference sensor array.2. The image-sensor-based ambient light sensing circuitry defined in wherein the control circuitry is configured to measure current flow into the image sensor array and the reference light sensor array and is configured to produce the ambient light sensor reading based at least partly on how much current flows into the reference sensor array and how much current flows into the image sensor array.3. The image-sensor-based ambient light sensing circuitry defined in wherein the control circuitry includes a capacitor and wherein the control circuitry is configured to discharge the capacitor into the image sensor array during to measure current flow into the image sensor array and is configured to discharge the capacitor into the reference sensor ...

DETOURING IN SCRIPTING SYSTEMS

A system described herein includes a receiver component that receives third party code for execution in a host environment, wherein the third party code corresponds to a dynamic programming language, and wherein the third party code has at least one object reference to a first object that is used by the third party code. A detouring component automatically replaces the first object referenced by the third party code with a proxy object such that the third party code at runtime calls the proxy object instead of the first object. 1. A method comprising the following computer-executable acts:receiving a web page that is to be displayed on a display screen of a computing device in a web browser, the web page comprising a reference to third party code that is desirably executed by the web browser;retrieving the third party code responsive to receiving the web page, the third party code comprising a reference to an object that corresponds to the web page;prior to executing the third party code in the web browser, replacing the reference to the object with a reference to a proxy object in the third party code; andsubsequent to replacing the reference to the object with the reference to the proxy object, executing the third party code, wherein the third party code, when executing, calls the proxy object rather than the object.2. The method of executed by the web browser.3. The method of claim 1 , wherein the object is a document object model object.4. The method of claim 1 , wherein the third party code is written in a dynamic programming language.5. The method of claim 4 , wherein the third party code pertains to an advertisement that is desirably executed in the web browser and displayed on the web page.6. The method of claim 1 , wherein the third party code comprises a plurality of references to a respective plurality of objects claim 1 , the method further comprising replacing the plurality of references to the respective plurality of objects with a plurality of ...

Top-emission VCSEL-array with integrated diffuser

A radiation source includes a semiconductor substrate, an array of vertical-cavity surface-emitting lasers (VCSELs) formed on the substrate, which are configured to emit optical radiation, and a transparent crystalline layer formed over the array of VCSELs. The transparent crystalline layer has an outer surface configured to diffuse the radiation emitted by the VCSELs. 1. A radiation source , comprising:a semiconductor substrate;an array of vertical-cavity surface-emitting lasers (VCSELs) formed on the substrate, which are configured to emit optical radiation; anda crystalline layer formed over the array of VCSELs and having an outer surface patterned to define microlenses arrayed in an irregular pattern and having different, respective optical powers so as to diffuse the radiation emitted by the VCSELs.2. The radiation source according to claim 1 , wherein the crystalline layer is transparent.34-. (canceled)5. The radiation source according to claim 1 , wherein the outer surface of the crystalline layer is randomly roughened.6. The radiation source according to claim 1 , wherein the crystalline layer comprises an epitaxial layer of a semiconductor material.7. The radiation source according to claim 6 , wherein the array of VCSELs comprises multiple epitaxial layers formed on the substrate claim 6 , and wherein the epitaxial layer of the semiconductor material matches one of the epitaxial layers of the VCSELs.8. The radiation source according to claim 6 , and comprising anode contacts electrically connected to the VCSELs through the crystalline layer.9. The radiation source according to claim 1 , wherein the crystalline layer comprises a dielectric material.10. A method of manufacturing a radiation source claim 1 , the method comprising:forming an array of vertical-cavity surface-emitting lasers (VCSELs) on a semiconductor substrate;forming a crystalline layer over the VCSEL array; andetching an outer surface of the crystalline layer to create a surface structure ...

Electrostatic Discharge (ESD) Diode in FinFET Technology

In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

VCSEL STRUCTURE WITH EMBEDDED HEAT SINK

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter. 1. An optoelectronic device , comprising:a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side;at least one optoelectronic emitter formed on the front side of the semiconductor substrate in proximity with the at least one cavity; anda heat-conducting material at least partially filling the at least one cavity and configured to serve as a heat sink for the at least one optoelectronic emitter.2. The optoelectronic device according to claim 1 , wherein the heat-conducting material comprises an electrically-conducting material claim 1 , which serves the at least one optoelectronic emitter as an electrical contact.3. The optoelectronic device according to claim 1 , wherein the at least one cavity is filled with at least two fill materials.4. The optoelectronic device according to claim 3 , wherein the at least two fill materials comprise an electrically-conductive film deposited over an interior surface of the at least one cavity in ohmic contact with the semiconductor substrate claim 3 , and a thermally-conductive material deposited over the electrically-conductive film.5. The optoelectronic device according to claim 1 , wherein the at least one optoelectronic emitter comprises an array of emitters on the front side of the semiconductor substrate claim 1 , and the at least one cavity comprises an array of cavities on the back ...

Image Sensor with Buried Light Shield and Vertical Gate

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region. 1. An image sensor including a plurality of pixels , at least one pixel comprising:a photodetector disposed in a substrate adjacent to a first surface of the substrate;a storage region disposed in the substrate adjacent to a second surface of the substrate opposite the first surface; anda buried light shield disposed between the photodetector and the storage region.2. The image sensor as in claim 1 , wherein the buried light shield divides the substrate into a first substrate layer and a second substrate layer claim 1 , the photodetector being disposed in the first substrate layer and the storage region being disposed in the second substrate layer.3. The image sensor as in claim 2 , further comprising:a vertical gate formed through the second substrate layer and through the buried light shield; anda transfer channel disposed adjacent to the vertical gate, the transfer channel being operable to provide a channel for charge to transfer from the photodetector to the storage region.4. The image sensor as in claim 3 , further comprising a sense region in the second substrate layer adjacent to the storage region claim 3 , wherein the ...

MULTIMEDIA READING CONTROL DEVICE, GRAPH ACQUISITION DEVICE, ELECTRONIC EQUIPMENT, GRAPH SUPPLY DEVICE AND METHODS THEREOF

Embodiments of the invention provide a multimedia reading control device, a graph acquisition device, an electronic equipment, a graph supply device and a method thereof, wherein the multimedia control device includes a reception unit which receives a graph of physiological parameters that varies with the progress of reading a multimedia file, a display unit which displays the graph of physiological parameters, and a response unit which reads the multimedia file in response to the progress selected according to the graph of physiological parameters. The graph of physiological parameters varying with the progress of reading the multimedia file is displayed when the multimedia file is read, so that a user selects the progress of the multimedia file according to the graph of physiological parameters, so as to read the part in the multimedia file in which the user is interested conveniently and efficiently. 1. A multimedia reading control device , comprising:a reception unit configured to receive a graph of physiological parameters that varies with the progress of reading a multimedia file;a display unit configured to display the graph of physiological parameters;a response unit configured to read the multimedia file in response to the progress selected according to the graph of physiological parameters.2. The multimedia reading control device according to claim 1 , wherein the response unit comprises:an instruction receiving unit configured to receive an instruction for selecting the progress according to the graph of physiological parameters;a determination unit configured to determine the selected progress according to the instruction;a reading unit configured to read the multimedia file according to the selected progress.3. The multimedia reading control device according to claim 1 , wherein the physiological parameters comprise at least one of heartbeat claim 1 , pulse claim 1 , blood pressure claim 1 , body temperature claim 1 , a respiration parameter claim 1 , ...

VERTICALLY STACKED IMAGE SENSOR

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. 1. An image sensor , comprising: two or more photodiodes; and', 'a transfer transistor operably connected each photodiode;, 'a photodiode chip comprising at least one pixel cell, each pixel cell comprisinga shared transfer channel operably connected to each transfer transistor; and a first communication path operably connected to the shared transfer channel, the first communication path comprising a first floating diffusion node operably connected to control circuitry in the first communication path; and', 'a second communication path operably connected to the shared transfer channel, the second communication path comprising a second floating diffusion node operably connected to control circuitry in the second communication path, wherein', 'a capacitance associated with the first floating diffusion node differs from a capacitance associated with the second floating diffusion node; and', 'the shared transfer channel is configured to transfer charge from at least one of the first or second photodiodes to a respective communication path., 'a transistor array chip stacked vertically on the photodiode chip, the transistor array chip comprising2. The image sensor as in claim 1 , wherein the shared transfer channel comprises:a semiconductor transfer channel;an ...

Curved Light Sensor

An optical system can include a curved light sensor and an optical system positioned in front of the curved light sensor. The curved light sensor includes a substrate and a patterned stress film formed over at least surface of the substrate. 1. A curved light sensor , comprising:a light sensor comprising a light receiving surface and a non-light receiving surface; anda patterned stress film formed over at least one surface of the light sensor.2. The curved light sensor as in claim 1 , wherein the curved light sensor comprises a light emitting sensor.3. The curved light sensor as in claim 1 , wherein the curved light sensor comprises a light detection sensor.4. The curved light sensor as in claim 3 , wherein the light detection sensor comprises an image sensor.4. The curved light sensor as in claim 1 , wherein the patterned stress film is formed over the non-light receiving surface.5. The curved light sensor as in claim 4 , wherein the patterned stress film is formed over the light receiving surface.6. The curved light sensor as in claim 1 , wherein the patterned stress film is formed over the light receiving surface.7. The curved light sensor as in claim 1 , wherein the patterned stress film comprises a single layer of a stress film.8. The curved light sensor as in claim 1 , wherein the patterned stress film comprises multiple layers of stress films.9. The curved light sensor as in claim 8 , wherein at least one layer of a stress film in the multiple layers of stress films is a different type of stress film than another layer of a stress film in the multiple layers of stress films.10. The curved light sensor as in claim 8 , wherein at least one layer of a stress film in the multiple layers of stress films is patterned differently than another layer of a stress film in the multiple layers of stress films.11. A method for producing a curved light sensor claim 8 , comprising:attaching a support wafer to a first surface of a sensor wafer, wherein the sensor wafer ...

VCSEL structure with embedded heat sink

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter. 118-. (canceled)19. An optoelectronic device , comprising:a semiconductor substrate, having front and back sides;at least one optoelectronic emitter formed on the front side of the semiconductor substrate;an electrically-conductive film deposited over the back side of the semiconductor substrate in ohmic contact with the semiconductor substrate; anda heat-conducting material deposited over the electrically-conductive film and configured to serve as a heat sink for the at least one optoelectronic emitter.20. The optoelectronic device according to claim 19 , wherein the electrically-conducting film serves the at least one optoelectronic emitter as an electrical contact.21. The optoelectronic device according to claim 19 , wherein the back side of the semiconductor substrate is thinned in a vicinity of the at least one optoelectronic emitter.22. The optoelectronic device according to claim 21 , wherein the semiconductor substrate contains a cavity extending through the back side into proximity with the at least one optoelectronic emitter claim 21 , and wherein the electrically-conductive film and the heat-conducting material are deposited in the cavity.23. The optoelectronic device according to claim 19 , wherein the at least one optoelectronic emitter comprises an array of emitters on the front side of the semiconductor substrate.24. The optoelectronic device according to claim 19 , wherein the at least one optoelectronic emitter comprises a vertical- ...

Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) with Lateral Gated Section

In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared. 1. An electrostatic discharge (ESD) protection circuit comprising:a shallow trench isolation (STI)-bound silicon controlled rectifier (SCR) coupled between an input/output conductor and a voltage rail; anda gated SCR coupled between the input/output conductor and the voltage rail.2. The ESD protection circuit as recited in wherein the STI-bound SCR and the gated SCR are formed on a semiconductor substrate claim 1 , and wherein the STI-bound SCR is formed to be perpendicular to the gated SCR in a plane of the semiconductor substrate.3. The ESD protection circuit as recited in wherein the STI-bound SCR is formed between two adjacent regions of fins in the semiconductor substrate.4. The ESD protection circuit as recited in wherein the gated SCR is formed within one of the two adjacent regions of fins.5. The ESD protection circuit as recited in wherein a first node of the STI-bound SCR and a second node of the gated SCR are in a same diffusion area in the semiconductor substrate.6. The ESD protection circuit as recited in wherein a first node of the STI-bound SCR and a second node of the gated SCR are in a same N-well in the semiconductor substrate.7. The ESD protection circuit as recited in further comprising a trigger diode configured to trigger the STI-bound SCR and the gated SCR.8. The ESD protection circuit as recited in wherein the trigger diode is in a same region of fins as the STI-bound SCR and the gated SCR.9. The ...

Single Junction Bi-Directional Electrostatic Discharge (ESD) Protection Circuit

In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs. 1. A FinFET electrostatic discharge (ESD) protection circuit comprising:an N-type (N)-well formed in a semiconductor substrate wherein an area around the N-well is a P-type (P)-well forming a PN junction with the N-well;a highly-doped P (P+) region formed in the N-well, forming a second PN junction;a highly-doped N (N+) region formed in the P-well, forming a third PN junction, wherein the first PN junction, the second PN junction, and the third PN junction form a silicon-controlled rectifier (SCR); anda diode formed at another boundary of the P-well and the N-well, wherein the SCR and the diode form a bi-directional ESD protection circuit.2. The FinFET ESD protection circuit as recited in wherein the P+ region in the N-well is coupled to a pin of an integrated circuit including the ESD protection circuit and the N+ region in the P-well is coupled to a ground conductor claim 1 , and wherein the SCR is forward biased when triggered for an ESD event.3. The FinFET ESD protection circuit as recited in wherein the diode is reverse biased when triggered for an ESD event.4. The FinFET ESD protection circuit as recited in further comprising a second P+ region in the P-well adjacent to the N+ region claim 1 , wherein the second P+ region provides a floating contact for a trigger input to the SCR.5. The FinFET ESD protection circuit as recited in wherein the second P+ region is isolated from one or more other P+ regions that are coupled to ground contacts.6. The FinFET ESD protection circuit as recited in wherein the floating contact is shared by a ...

METHOD FOR TEMPLATE-DEPENDENT MULTIPLE DISPLACEMENT AMPLIFICATION

Provided herein are methods for template-dependent multiple displacement amplification (tdMDA) that preferably use 5′ blocked pentamer primers. 1. A composition comprising a population of pentamer oligonucleotides with blocked 5′ ends.2. The composition of claim 1 , wherein the oligonucleotides each comprise at least one phosphothioate linkage.3. The composition of claim 2 , wherein the oligonucleotides each comprises at least two phosphothioate linkages.4. The composition of claim 1 , wherein the blocked 5′ ends comprise a dSpacer claim 1 , a 5′ inverted dideoxynucleotide claim 1 , a 5′ carbon chain spacer claim 1 , a C3 spacer claim 1 , a C18 spacer claim 1 , or a 5′ ethyleneglycol spacer.5. The composition of claim 1 , wherein the population is homogeneous.6. The composition of claim 1 , wherein the population is heterogeneous.79-. (canceled)10. The composition of claim 1 , wherein the oligonucleotides each comprise at least one adenine claim 1 , one guanidine claim 1 , one cytidine claim 1 , and one thymidine.11. A method of amplifying a target nucleic acid comprising:(a) obtaining the target nucleic acid;(b) adding at least one polymerase, 5′-blocked random pentamer oligonucleotides, and deoxynucleotide triphosphates (dNTPs) to the target nucleic acid; and(c) incubating the target nucleic acid under isothermal conditions to allow for amplification of the target nucleic acid.12. The method of claim 1 , wherein the at least one polymerase comprises a strand displacing nucleic acid polymerase.13. (canceled)14. The method of claim 11 , wherein the target nucleic acid is genomic DNA or cDNA.15. (canceled)16. The method of claim 11 , wherein the target nucleic acid is a viral genome.17. The method of claim 11 , wherein the viral genome comprises about 0.01% of the nucleic acid in the sample.18. The method of claim 11 , wherein the target nucleic acid is RNA.1920-. (canceled)21. The method of claim 11 , wherein the target nucleic acid is extracted from a clinical ...

PIXEL ARRAY WITH SHARED PIXELS IN A SINGLE COLUMN AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region. 1. An imager , comprising: a floating diffusion region,', 'a source follower transistor having a gate coupled to the floating diffusion region,', 'a plurality of first pixels associated with a first color and configured to transfer charge to the floating diffusion region, and', 'a plurality of second pixels associated with a second color different than the first color, configured to transfer charge to the floating diffusion region, and arranged in a single column with the first pixels; and, 'a pixel array, including—'}control circuitry operably coupled to the pixel array, wherein the control circuity is configured to successively read out onto a column line image signals corresponding to the charge transferred to the floating diffusion region via each of the first and second pixels.2. The imager of wherein the floating diffusion region is a first floating diffusion region claim 1 , the source follower transistor is a first source follower transistor claim 1 , and the column line is a first column line claim 1 , and wherein the pixel array further includes:a second floating diffusion region;a second source follower transistor having a gate coupled to the second floating diffusion region;a plurality of third pixels associated with a third color different than the first and second colors; anda plurality of fourth pixels associated with the first color, configured to transfer charge to the ...

Transistor Integration with Stacked Single-Photon Avalanche Diode (SPAD) Pixel Arrays

Disclosed herein are photodetectors using arrays of pixels with single-photon avalanche diodes (SPADs). The pixel arrays may have configurations that include one or more control transistors for each SPAD collocated on the same chip or wafer as the pixels and located on a surface of the wafer opposite to the light gathering surface of the pixel arrays. The control transistors may be positioned or configured for interconnection with a logic chip that is bonded to the wafer of the pixel array. The pixels may be formed in a substrate having doping gradient. The control transistors may be positioned on or within the SPADs, or adjacent to, but isolated from, the SPADs. Isolation between the individual SPADs and the respective control transistors may make use of shallow trench isolation regions or deep trench isolation regions. 1. A pixel of a pixel array , the pixel comprising:isolation walls forming sides of the pixel and extending at least partially through a semiconductor substrate of the pixel array between a top surface of the pixel array and a light gathering surface of the pixel array opposite the top surface;{'claim-text': ['a cathode layer adjacent to the top surface; and', 'an anode layer within the semiconductor substrate and adjoining a side of the cathode layer opposite the top surface;'], '#text': 'a single-photon avalanche diode (SPAD) comprising:'}a control transistor adjacent to the top surface and electrically connected with the SPAD.2. The pixel of claim 1 , wherein:the control transistor is a first control transistor;the pixel further comprises a second control transistor;the first control transistor is a gating transistor;the second control transistor is a quenching transistor electrically connected to the SPAD.3. The pixel of claim 2 , further comprising shallow trench isolation material extending from the top surface at least partially into the semiconductor substrate; wherein:the shallow trench isolation material separates a first region of the ...

Stacked Backside Illuminated SPAD Array

A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

Stacked Backside Illuminated SPAD Array

A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions. 1. A back-illuminated single-photon avalanche diode (SPAD) image sensor , comprising: [ an anode gradient layer comprising a first dopant type;', 'a cathode region positioned adjacent to a front surface of the SPAD region and comprising a second dopant type; and', 'an anode avalanche layer positioned over the cathode region and comprising the first dopant type;, 'an SPAD region, comprising, the cathode region has a first area and the anode avalanche layer has a second area that is less than the first area; and', 'a dopant concentration of the first dopant type in the anode gradient layer is higher at a back surface of the sensor wafer and lower at a front surface of the anode gradient layer to produce a dopant concentration gradient in the anode gradient layer that guides a photon-generated charge carrier through the anode gradient layer to the anode avalanche layer; and, 'wherein], 'a sensor wafer, comprisinga circuit wafer positioned below and attached to the sensor wafer.2. The back-illuminated SPAD image sensor of claim 1 , wherein the circuit wafer comprises:a voltage supply coupled to the SPAD region through a first inter-wafer connector; andan output circuit coupled to the cathode region through a second inter-wafer connector;wherein the voltage supply is configured to supply a high voltage to the SPAD region to provide a reverse bias across the cathode ...

Creating arbitrary patterns on a 2-D uniform grid VCSEL array

An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS

Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. 1. An apparatus , comprising:a snap-back circuit coupled to a node and configured to discharge a first over-voltage condition when triggered responsive to a first trigger condition and further configured to discharge a second over-voltage condition when triggered responsive to a second trigger condition;a first circuit to modulate the first trigger condition of the snap-back circuit; anda second circuit to modulate the second trigger condition of the snap-back circuit, wherein the second trigger condition is different than the first trigger condition.2. The apparatus of claim 1 , wherein a first hold condition is associated with the first trigger condition and a second hold condition is associated with the second trigger condition claim 1 , and wherein the second hold condition is different than the first hold condition.3. The apparatus of claim 1 , wherein the snap-back circuit comprises a thyristor and an n-channel transistor.4. The apparatus of claim 3 , wherein a portion of the thyristor is formed in an isolated p-well region of a semiconductive ...

EXPOSURE CONTROL FOR IMAGE SENSORS

A method of operating an image sensor. Charge accumulated in a photodiode during a first sub-exposure may be selectively stored in a storage node responsive to a first control signal. Charge accumulated in the photodiode during a first reset period may be selectively discarded responsive to a second control signal. Charge accumulated in the photodiode during a second sub-exposure may be selectively stored responsive to the first control signal. Charge stored in the storage node from the first and second sub-exposures may be transferred to a floating diffusion node responsive to a third control signal. 1. A method of operating an image sensor , comprising:selectively storing, responsive to a first control signal, charge accumulated in a photodiode during a first sub-exposure in a storage node;selectively discarding, responsive a second control signal, charge accumulated in the photodiode during a first reset period;selectively storing, responsive to the first control signal, charge accumulated in the photodiode during a second sub-exposure in the storage node; andtransferring, responsive to a third control signal, charge stored in the storage node from the first and second sub-exposures to a floating diffusion node.2. The method of claim 1 , wherein the first control signal comprises a transfer signal provided to a storage gate coupled between the photodiode and the storage node.3. The method of claim 2 , wherein the second control signal comprises an anti-blooming signal provided to an anti-blooming gate coupled to the photodiode.4. The method of claim 2 , wherein the second control signal is the transfer signal provided to the storage gate.5. The method of claim 2 , wherein the third control signal comprises a transfer signal provided to a transfer gate coupled between the storage node and the floating diffusion node.6. The method of claim 1 , further comprising selectively storing claim 1 , responsive to the first control signal claim 1 , charge accumulated in the ...

CHARGE TRANSFER IN IMAGE SENSORS

Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, and the transfer circuit may have a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node.

Image sensor with flexible pixel summing

An image sensor can include pixels that are grouped into subsets of pixels, with each subset including three or more pixels. A method for asymmetrical high dynamic range imaging can include capturing an image of a subject scene using a single integration time for all of the pixels. In a subset of pixels, charge in N pixels is read out and summed together. N represents a number that is between two and one less than a total number of pixels in the subset. Un-summed charge is read out from one pixel in the subset. The un-summed charge and the summed charge are combined when producing a high dynamic range image.

HYBRID IMAGE SENSOR

A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors. 1. An image sensor for an electronic device , comprising:a light sensitive element configured to produce a charge corresponding to a light parameter;a transfer gate in communication with the light sensitive element;a floating diffusion node in communication with the light sensitive element;a storage gate in communication with the floating diffusion node;a reset gate in communication with the light sensitive element;a source follower gate in communication with the storage gate; anda row select gate in communication with the source follower gate and the storage gate; anda logic chip operably connected to the transistor array chip and in communication therewith; whereinthe transfer gate communicates data from the light sensitive element to floating diffusion node;the logic chip selectively activates the transfer gate, the reset gate, the source follower gate, the row select gate, and the storage gate; andthe storage gate has a variable potential.2. The image sensor of claim 1 , wherein the transfer gate has a set potential.3. The image sensor of claim 1 , wherein the charge is transferrable from the floating diffusion node to the storage gate and from the storage gate to the floating diffusion node.4. The image sensor of claim 1 , wherein the potential of the storage gate is related to a voltage applied to the storage gate.5. The image sensor of claim 1 , wherein the ...

VCSEL structure with embedded heat sink

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter. 1a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side;at least one optoelectronic emitter formed on the front side of the semiconductor substrate in proximity with the at least one cavity; anda heat-conducting material at least partially filling the at least one cavity and configured to serve as a heat sink for the at least one optoelectronic emitter.. An optoelectronic device, comprising: This application is a continuation of U.S. patent application Ser. No. 15/641,244, filed Jul. 4, 2017, which is a continuation of U.S. patent application Ser. No. 15/011,562 (now U.S. Pat. No. 9,735,539), filed Jan. 31, 2016, which claims the benefit of U.S. Provisional Patent Application 62/194,298, filed Jul. 20, 2015, which is incorporated herein by reference.The present invention relates generally to semiconductor devices, and particularly to optoelectronic devices and their manufacture.Effective heat dissipation is one of the major challenges in design of high-power optoelectronic emitters, such as VCSELs. Such devices generate large amounts of heat in the emitter active regions, resulting in high emitter junction temperatures, which tend to reduce VCSEL efficiency and lead to a reduced optical power output at a given drive current, shift the emission wavelength, degrade the quality of the laser modes, and reduce operating lifetime ...

CLAMP CIRCUIT FOR ELECTRICAL OVERSTRESS AND ELECTROSTATIC DISCHARGE

An apparatus includes a device, a comparison circuit, and a switch. The device includes a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference. The comparison circuit is configured to compare a first voltage level on the first power supply signal to a second voltage level of a second power supply signal, and enable the device in response to a determination that the first voltage level is greater than the second voltage level. The switch circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to determining that the first voltage level is greater than the second voltage level, and to couple the power supply terminal to the second power supply signal in response to determining that the first voltage level is less than the second voltage level. 1. An apparatus comprising:a device including a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference, wherein the device is configured to couple the first terminal to the second terminal in response to an assertion of an enable signal; compare a first voltage level of the first power supply signal to a second voltage level of a second power supply signal; and', 'assert the enable signal in response to a determination that the first voltage level is greater than the second voltage level; and, 'a comparison circuit coupled to the device, wherein the comparison circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to a determination that the first voltage level is greater than the second voltage level; and', 'couple the power supply terminal of the comparison circuit to the second power supply signal in response to a determination that the first voltage level is less than the second voltage level., 'a switch circuit configured to2. The apparatus of claim 1 , wherein the comparison ...

TARGET ENRICHMENT VIA ENZYMATIC DIGESTION IN NEXT GENERATION SEQUENCING

Provided herein are methods of preparing a template nucleic acid for next-generation sequencing. The methods comprise performing primer extension using cdGTP instead of dGTP, which then allows for the input nucleic acids to be selectively digested by cdGTP-resistant restriction enzymes, thereby enriching the template nucleic acid prior to next-generation sequencing library preparation. 1. A method of preparing a nucleic acid template for next-generation sequencing , the method comprising:{'sup': '7', '(a) incubating a population of nucleic acid molecules comprising the template nucleic acid with a primer, cdGTP, dCTP, dATP, dTTP, and a DNA polymerase;'}(b) incubating the product of step (a) with a splinter oligonucleotide and T4 DNA ligase under conditions to allow for the self-ligation of the extension product of step (a); and{'sup': '7', '(c) incubating the product of step (b) with cdGTP-resistant restriction enzymes, Exonuclease I, and Exonuclease III under conditions to allow for the digestion of non-target and background nucleic acid.'}2. The method of claim 1 , wherein the template nucleic acid is DNA.3. The method of claim 2 , wherein the DNA polymerase used in step (a) is a DNA-dependent DNA polymerase.4. The method of claim 1 , wherein the template nucleic acid is RNA.5. The method of claim 4 , wherein the DNA polymerase used in step (a) is an RNA-dependent DNA polymerase.6. The method of claim 1 , wherein the cdGTP-resistant restriction enzymes are AluI claim 1 , HaeIII claim 1 , and/or HpyCH4V.7. The method of claim 1 , wherein the primer comprises a phosphate on the 5′ end.8. The method of claim 1 , wherein the 3′ end of the primer has a sequence that hybridizes to the template nucleic acid claim 1 , a degenerate sequence claim 1 , or a poly-T sequence.9. The method of claim 1 , wherein step (a) comprises 5-10 cycles of primer extension.10. The method of claim 1 , wherein the splinter oligonucleotide hybridizes to the rare restriction site at the 5′ end ...

PREVENTING ARTIFACTS DUE TO UNDERFILL IN FLIP CHIP IMAGER ASSEMBLY

A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC. 1. A computer system , comprising:a printed circuit board;an integrated circuit device comprising an image sensor pixel array;a plurality of electrically conductive interconnect structures; anda composite underfill material comprising a polymer and one or more fillers;wherein the integrated circuit device is coupled to the printed circuit board by the interconnect structures at respective points on the integrated circuit device and the printed circuit board such that the image sensor pixel array faces the printed circuit board;wherein the composite underfill material envelopes at least a portion of each of the interconnect structures in a space between the integrated circuit device and the printed circuit board; andwherein a chemical or physical discontinuity on the integrated circuit device surrounds the image sensor pixel array and prevents the composite underfill material from extending over the image sensor pixel array.2. The computer system of claim 1 , wherein the discontinuity comprises metal or metal oxide that forms a dam-type structure on the integrated circuit ...

Optimized ESD Clamp Circuitry

ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event. 1. A apparatus comprising:a first sensor circuit;a second sensor circuit, wherein each of the first and second sensor circuits are configured to detect an electro-static discharge (ESD) event; andfirst and second clamp transistors configured to be activated by the first and second ESD sensor circuits, respectively, responsive to detection of the ESD event;wherein a resistive-capacitive (RC) time constant of the first sensor circuit is greater than an RC time constant of the second sensor circuit.2. The apparatus as recited in claim 1 , wherein the first and second sensor circuits are implemented in a global power domain claim 1 , and wherein the first and second clamp transistors are implemented in a gated power domain.3. The apparatus as recited in claim 2 , further comprising first and second power switches coupled between the global power domain and the gated power domain claim 2 , wherein the first and second sensor circuits are configured to cause activation of the first and second power switches claim 2 , respectively claim 2 , responsive to the ESD event.4. The apparatus as recited in claim 1 , wherein the first sensor circuit is a first type of sensor circuit and the second sensor circuit is a second type of sensor circuit claim 1 , wherein the circuit further comprises multiple ...

Modular Electrostatic Discharge (ESD) Protection

In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

Creating arbitrary patterns on a 2-D uniform grid VCSEL array

An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

Image Sensor Having Full Well Capacity Beyond Photodiode Capacity

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Protection and communication abstractions for web browsers

Systems and methodologies for accessing resources associated with a Web-based application in accordance with one or more embodiments disclosed herein may include a browser that obtains at least first resources from a first domain and second resources from a second domain and a resource management component that facilitates controlled communication between the first resources and the second resources and prevents the first resources and the second resources from accessing other resources that the first resources and the second resources are not permitted to access. The resource management component may be further operable to contain restricted services in a sandbox containment structure and/or to isolate access-controlled resources in a service instance. In addition, the resource management component may be operable to facilitate the flexible display of resources from disparate domains and/or controlled communication therebetween.

Back-Illuminated Single-Photon Avalanche Diode

A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions. 1. A back-illuminated single-photon avalanche diode (SPAD) , comprising: a SPAD region configured to receive photons of light entering through the back surface of the sensor wafer;', 'a deep trench isolation (DTI) region surrounding the SPAD region and extending from the front surface to the back surface of the sensor wafer; and', 'a passivation layer extending between the DTI region and the SPAD region., 'a sensor wafer having a back surface opposite a front surface, the sensor wafer comprising2. The back-illuminated SPAD of claim 1 , wherein: an anode region; and', 'a cathode region adjacent the front surface of the sensor wafer., 'the SPAD region comprises3. The back-illuminated SPAD of claim 2 , wherein:the anode region comprises an anode gradient layer; andthe passivation layer and the anode gradient layer have a same doping.4. The back-illuminated SPAD of claim 1 , further comprising:a light shield disposed on the back surface of the sensor wafer, over the DTI region.5. The back-illuminated SPAD of claim 1 , further comprising:a light reflector disposed adjacent the front surface of the sensor wafer, under at least a portion of the SPAD region, and configured to reflect photons of light that have passed through the SPAD region back toward the SPAD region.6. The back-illuminated SPAD of claim 1 , further comprising:a lateral shield disposed adjacent the ...

High-efficiency vertical emitters with improved heat sinking

A method for production of an optoelectronic device includes fabricating a plurality of vertical emitters on a semiconductor substrate. Respective top surfaces of the emitters are bonded to a heat sink, after which the semiconductor substrate is removed below respective bottom surfaces of the emitters. Both anode and cathode contacts are attached to the bottom surfaces so as to drive the emitters to emit light from the bottom surfaces. In another embodiment, the upper surface of a semiconductor substrate is bonded to a carrier substrate having through-holes that are aligned with respective top surfaces of the emitters, after which the semiconductor substrate is removed below respective bottom surfaces of the emitters, and the respective bottom surfaces of the emitters are bonded to a heat sink. 1. A method for production of an optoelectronic device , comprising:fabricating a plurality of vertical emitters on a semiconductor substrate;bonding respective top surfaces of the emitters to a heat sink;after bonding the top surfaces, removing the semiconductor substrate below respective bottom surfaces of the emitters; andattaching both anode and cathode contacts to the bottom surfaces so as to drive the emitters to emit light from the bottom surfaces.2. The method according to claim 1 , and comprising:testing the emitters by applying currents between the anode and cathode comments; andafter testing the emitters, dicing the heat sink along with the emitters bonded thereto.3. The method according to claim 1 , wherein bonding the top surfaces comprises soldering the top surfaces to a conducting layer at a lower surface of the heat sink.4. The method according to claim 3 , wherein fabricating the plurality of the vertical emitters comprises depositing epitaxial layers on the semiconductor substrate claim 3 , and wherein attaching the anode contact comprises etching a via through the epitaxial layers claim 3 , and extending the anode contact through the via to the conducting ...

PIXEL ARRAY WITH SHARED PIXELS IN A SINGLE COLUMN AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region. 1. An imager , comprising: a floating diffusion region,', 'a source follower transistor having a gate coupled to the floating diffusion region,', 'a plurality of pixels associated with a plurality of colors and configured to transfer charge to the floating diffusion region, the plurality of pixels arranged in a first column, the plurality of pixels including at least two pixels associated with a first one of the plurality of colors; and, 'a pixel array, including—'}control circuitry operably coupled to the pixel array, wherein the control circuitry is configured to successively read out onto a column line image signals corresponding to the charge transferred to the floating diffusion region via each of the plurality of pixels.2. The imager of wherein the floating diffusion region is a first floating diffusion region claim 1 , the source follower transistor is a first source follower transistor claim 1 , the plurality of pixels is a first plurality of pixels claim 1 , and the column line is a first column line claim 1 , and wherein the pixel array further includes:a second floating diffusion region;a second source follower transistor having a gate coupled to the second floating diffusion region;a second plurality of pixels associated with a second plurality of colors including a second color different than the first one of the plurality of colors, the second plurality of pixels configured to ...

Image Sensor with Buried Light Shield and Vertical Gate

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.

CHARACTER STRING DISTANCE CALCULATION METHOD AND DEVICE

Techniques for determining character string differences between a target character string and one or more candidate character strings are provided. In some implementations, a target bitmap is produced for the target character string and a target bitmap weight is calculated. A candidate bitmap and a candidate bitmap weight associated with a candidate character string is obtained. In response to determining that the candidate bitmap weight differs from the target bitmap weight by less than a first threshold value, an exclusive OR operation is performed between the target bitmap and the candidate bitmap. In response to determining that number of ones in the result of the exclusive OR is less than a second threshold value, the candidate character string is included in a character set that includes one or more character strings that are close to the target character string. 1. A computer-implemented method executed by a system of one or more computers , the method comprising:receiving a target character string;comparing characters in the target character string to characters in a model character string that includes a sequence of a plurality of characters to produce a target bitmap indicating characters that are common between the target character string and the model character string, the target bitmap including a plurality of first flag bits, each first flag bit being associated with a respective character of the target character string and having a first value or a second value, wherein a first flag bit having the first value indicates that a respective character in the target character string matches a corresponding character in the model character string, and the first flag bit having the second value indicates that a respective character in the target character string does not match a corresponding character in the model character string;calculating a target bitmap weight associated with the target character string, the target bitmap weight indicating a number of ...

ESD Protection for Advanced CMOS Processes

Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit. 1. A circuit comprising:a driver comprising a first transistor coupled between a power node and an output node and a second transistor coupled between the output node and a reference node;a first electrostatic discharge (ESD) protection circuit configured to provide protection for the driver responsive to detection of an ESD event; anda second ESD protection circuit configured to provide protection exclusively to the first transistor responsive to detection of the ESD event.2. The circuit as recited in claim 1 , wherein the first transistor is a p-channel metal oxide semiconductor (PMOS) transistor and wherein the second transistor is a first n-channel metal oxide semiconductor (NMOS) transistor.3. The circuit as recited in claim 2 , wherein the second ESD protection circuit comprises one or more series-coupled diodes connected in parallel with the first transistor between the power node and the output node.4. The circuit as recited in claim 3 , wherein the second ESD protection circuit comprises a plurality of series-coupled diodes shared among a plurality of additional drivers and at least one additional diode coupled in series between the output node of the driver and the plurality of series-coupled diodes claim 3 , wherein the at least one additional diode is dedicated to the driver.5. The circuit as recited in claim 2 , wherein the second ESD protection circuit comprises a trigger circuit configured to activate the first transistor responsive to detecting the ESD event.6 ...

Top-emission VCSEL-array with integrated diffuser

A radiation source includes a semiconductor substrate, an array of vertical-cavity surface-emitting lasers (VCSELs) formed on the substrate, which are configured to emit optical radiation, and a transparent crystalline layer formed over the array of VCSELs. The transparent crystalline layer has an outer surface configured to diffuse the radiation emitted by the VCSELs. 1. A radiation source , comprising:a semiconductor substrate;an array of vertical-cavity surface-emitting lasers (VCSELs) formed on the substrate, which are configured to emit optical radiation; anda crystalline layer formed over the array of VCSELs and having an outer surface configured to diffuse the radiation emitted by the VCSELs.2. The radiation source according to claim 1 , wherein the crystalline layer is transparent.3. The radiation source according to claim 1 , wherein the outer surface of the crystalline layer is patterned to define microlenses having different claim 1 , respective optical powers.4. The radiation source according to claim 3 , wherein the microlenses are arrayed in an irregular pattern over the VCSELs.5. The radiation source according to claim 1 , wherein the outer surface of the crystalline layer is randomly roughened.6. The radiation source according to claim 1 , wherein the crystalline layer comprises an epitaxial layer of a semiconductor material.7. The radiation source according to claim 6 , wherein the array of VCSELs comprises multiple epitaxial layers formed on the substrate claim 6 , and wherein the epitaxial layer of the semiconductor material matches one of the epitaxial layers of the VCSELs.8. The radiation source according to claim 6 , and comprising anode contacts electrically connected to the VCSELs through the crystalline layer.9. The radiation source according to claim 1 , wherein the crystalline layer comprises a dielectric material.10. A method of manufacturing a radiation source claim 1 , the method comprising:forming an array of vertical-cavity surface- ...

Creating arbitrary patterns on a 2-D uniform grid VCSEL array

An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation. 1. An optoelectronic device , comprising:a semiconductor substrate; and first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack;', 'second epitaxial layers formed over the lower DBR stack, defining a quantum well structure;', 'third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and', 'electrodes formed over the upper DBR stack, which are configured to inject an excitation current into the quantum well structure of at least some of the optoelectronic cells,, 'a regular array of optoelectronic cells, which are formed on the semiconductor substrate and comprisewherein the array comprises a first set of the optoelectronic cells that are configured to emit laser radiation in response to the excitation current and a second set of the optoelectronic cells, interleaved with the first set, in which at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the ...

Methods for Transferring Charge in an Image Sensor

Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, and the transfer circuit may have a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node. 1. A method of transferring charge from a first storage node to a second storage node in an integrated circuit (IC) , the method comprising: the first region of the IC is between the first storage node and the second region of the IC, the first region and the second region being positioned adjacent to the transfer gate;', 'the first region is configured to maintain a first variable potential less than a second variable potential of the second region;', 'a virtual barrier region of the IC is between the second region and the second storage node, and is configured to have a virtual barrier potential less than a potential of the second storage node; and', 'the first applied potential causes the first variable potential to be less than a potential of the first storage node;, 'applying, at a transfer gate, a first applied potential to a first region of the IC and to a second region of the IC, whereinaccumulating a quantity of charge in the first storage node; the first variable potential is greater than the potential of the first storage node; and', 'a portion of the accumulated charge of the first storage node is transferred into the second region;, 'applying, at the transfer gate, a second applied potential to the first region and to the second region so thatapplying, at the transfer gate, a third applied ...

WEBSITE LOGIN METHOD AND APPARATUS

The present application provides example website login methods and apparatuses. One example method includes identifying a website jump trigger indication to jump from a first website to a second website. A first token is then obtained from a cookie store of the web browser, the first token associated with a website identifier of the second website and a device fingerprint indicating a running environment at a time when the password-free proxy login was previously set. In response to determining that a current running environment corresponds to the device fingerprint, a second token corresponding to the first token is obtained, wherein the second token comprises an access token indicating that the second website grants password-free login permissions. A password-free login request is sent to the second website including the second token. In response to the second website verifying the second token, the second website is logged into without a password. 1. A computer-implemented method , comprising:identifying, using a web browser presenting a first website, a website jump trigger indication to jump from the first website to a second website;in response to identifying the website jump trigger, obtaining a first token from a cookie store of the web browser, the first token associated with a website identifier of the second website and a device fingerprint indicating a running environment at a time when the password-free proxy login was previously set;in response to determining that a current running environment corresponds to the running environment indicated by the device fingerprint, obtaining a second token corresponding to the first token, wherein the second token comprises an access token indicating that the second website grants password-free login permissions;sending, via the web browser, a password-free login request to the second website, the request comprising a third token corresponding to the website identifier of the second website, where the third token ...

Stacked Electromagnetic Radiation Sensors for Visible Image Sensing and Infrared Depth Sensing, or for Visible Image Sensing and Infrared Image Sensing

A sensor stack is described. The sensor stack includes first and second electromagnetic radiation sensors. The first electromagnetic radiation sensor has a high quantum efficiency for converting a first range of electromagnetic radiation wavelengths into a first set of electrical signals. The second electromagnetic radiation sensor is positioned in a field of view of the first electromagnetic radiation sensor and has a high quantum efficiency for converting a second range of electromagnetic radiation wavelengths into a second set of electrical signals and a low quantum efficiency for converting the first range of electromagnetic radiation wavelengths into the second set of electrical signals. The first range of wavelengths does not overlap the second range of wavelengths, and the second electromagnetic radiation sensor is at least partially transmissive to the first range of electromagnetic radiation wavelengths. 1. A sensor stack , comprising:a first electromagnetic radiation sensor having a high quantum efficiency for converting a first range of electromagnetic radiation wavelengths into a first set of electrical signals; and a high quantum efficiency for converting a second range of electromagnetic radiation wavelengths into a second set of electrical signals; and', 'a low quantum efficiency for converting the first range of electromagnetic radiation wavelengths into the second set of electrical signals; wherein:, 'a second electromagnetic radiation sensor, positioned in a field of view of the first electromagnetic radiation sensor and having,'}the first range of electromagnetic radiation wavelengths does not overlap the second range of electromagnetic radiation wavelengths; andthe second electromagnetic radiation sensor is at least partially transmissive to the first range of electromagnetic radiation wavelengths.2. The sensor stack of claim 1 , wherein: a semiconductor substrate comprising pixel circuitry for an array of pixels;', 'a photosensitive material ...

Top-emission vcsel-array with integrated diffuser

Edge based template matching

A method for image processing that includes determining edge pixels of a model image using an edge based technique, and an angular orientation for each of the edge pixels of the model image. The method determines a lower spatial resolution model image based upon the model image and determining respective angular orientations for the lower spatial resolution model image. The method determines edge pixels of an input image using an edge based technique, and an angular orientation for each of the edge pixels of the input image. The method determines a lower spatial resolution input image based upon the input image and determining respective angular orientations for the lower spatial resolution input image. The method matches the lower spatial resolution model image with the lower spatial resolution input image to determine candidate locations of an object within the input image and based upon the candidate locations matching the input image with the model image.

VCSEL structure with embedded heat sink

An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter.

Vertical 4-way shared pixel in a single column with internal reset and no row select

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Combination ESD protection circuits and methods

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.

Over-limit electrical condition protection circuits for integrated circuits

Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

Pixel array with shared pixels in a single column and associated devices, systems, and methods

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region.

Detouring in scripting systems

A system described herein includes a receiver component that receives third party code for execution in a host environment, wherein the third party code corresponds to a dynamic programming language, and wherein the third party code has at least one object reference to a first object that is used by the third party code. A detouring component automatically replaces the first object referenced by the third party code with a proxy object such that the third party code at runtime calls the proxy object instead of the first object.

Preventing artifacts due to underfill in flip chip imager assembly

A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC.

Identification of multivalent viral envelope protein epitopes

The present invention provides methods for identifying multivalent vaccine antigens derived from envelope proteins.

積層された単一光子アバランシェダイオード（ｓｐａｄ）画素アレイとのトランジスタ統合

【課題】単一光子アバランシェダイオード（ＳＰＡＤ）を有する画素のアレイを用いた光検出器を提供する。【解決手段】画素アレイは、画素と同じチップ又はウエハ上に配置されており、画素アレイの集光面の反対側のウエハの表面上に位置する、各ＳＰＡＤについて１つ以上の制御トランジスタを含む構成を有し得る。制御トランジスタは、画素アレイのウエハに接合された論理チップと相互接続するように配置又は構成され得る。画素は、ドーピング勾配を有する基板内に形成していることができる。制御トランジスタは、ＳＰＡＤ上若しくはＳＰＡＤ内に配置され得るか、又はＳＰＡＤに隣接しているが、ＳＰＡＤから絶縁され得る。個々のＳＰＡＤとそれぞれの制御トランジスタとの間の分離は、浅いトレンチ分離領域又は深いトレンチ分離領域を使用することができる。【選択図】図２

Website login method and apparatus

The present application provides a website login method and apparatus, and the method includes: when a first website receives a website jump trigger, obtaining a first token stored in cookies of a browser that the first website runs on, where the first token includes a website identifier of a second website on a second website list page indicated 5 by website trigger, a fingerprint to ndicate running environment where password-free proxy login is set for the second website; if the first website determines, based on the device fingerprint, that a current running environment is the same as the running environment where password-free proxy login is set for the second website, obtaining, by the first website, a second token that corresponds to the 10 first token; and sending, by the first website based on the website identifier in the first token, a password-free login request including a third token to second where the third token includes the second token; and logging in to the second website without a password when the second website successfully verifies the second token. Security password-free of second through he first website is 15 improved in the present application.

Web site login method and apparatus

The present application provides a website login method and apparatus, and the method includes: when a first website receives a website jump trigger, obtaining a first token stored in cookies of a browser that the first website runs on, where the first token includes a website identifier of a second website on a second website list page indicated by the website jump trigger, and a device fingerprint used to indicate a running environment where password-free proxy login is set for the second website; if the first website determines, based on the device fingerprint, that a current running environment is the same as the running environment where password-free proxy login is set for the second website, obtaining, by the first website, a second token that corresponds to the first token; and sending, by the first website based on the website identifier in the first token, a password-free login request including a third token to the second website, where the third token includes the second token; and logging in to the second website without a password when the second website successfully verifies the second token. Security of password-free login of the second website through the first website is improved in the present application.

Web site login method and apparatus

Application activation method and apparatus and electronic equipment

Embodiments of the present invention provide an application activation method and apparatus and electronic equipment. The activation method includes: determining one or more recommended application(s) according to information on practice of use of applications; and activating the one or more recommended application(s). With the embodiments of the present invention, many applications expected to be used need not to be looked for, thereby reducing a large quantity of repeated operations, and obtaining better user experience.

Dual Embedded Storage Nodes and Vertical Transfer Gates for Pixels of Global Shutter Image Sensors

Disclosed herein are global shutter image sensors and methods of operating such image sensors. An image sensor includes a semiconductor wafer having a light receiving surface opposite an electrical connection surface; an oxide extending from the light receiving surface toward the electrical connection surface and at least partially surrounding a pixel region; a photodiode disposed within the pixel region; and a set of storage nodes disposed under the photodiode, between the photodiode and the electrical connection surface. The set of storage nodes comprises a first storage node and a second storage node. The storage nodes may be disposed vertically beneath the photodiode, or side by side.

Vertically stacked image sensor

Ancestral Hepatitis C virus envelope protein sequence

The present invention provides ancestral sequences for hepatitis C virus (HCV) envelope proteins, as well as uses for such sequences in inducing protective immune responses in subjects infected or at risk of infection with HCV.

Vertically stacked image sensor

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Programmable Transmit/Receive Pixel Array and Applications

Disclosed herein are electronic devices that include arrays of dual function light transmit and receive pixels. The pixels of such arrays include a photodetector (PD) structure and a vertical-cavity, surface-emitting laser (VCSEL) diode, both formed in a common stack of epitaxial semiconductor layers. The pixels of the array may be configured by a controller or processor to function either as a light emitter by biasing the VCSEL diode, or as a light detector or receiver by a different bias applied to the PD structure, and this functionality may be altered in time. The array of dual function pixels may be positioned interior to an optical display of an electronic device, in some cases to provide depth sensing or autofocus. The array of pixels may be registered with a camera of an electronic device, such as to provide depth sensing or autofocus.

Stacked multi-spectral image sensor

A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.

Image sensor with buried light shield and vertical gate

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.

Creating arbitrary patterns on a 2-d uniform grid vcsel array

An optoelectronic device includes a semiconductor substrate (10) and an array of optoelectronic cells (12), formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack (20); second epitaxial layers formed over the lower DBR stack, defining a quantum well structure (22); third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack (24); and electrodes (30) formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells (16), interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

２次元均一グリッドｖｃｓｅｌアレイへの任意パターンの生成

【課題】パターン化された光源および光源を製造する改善された方法を提供する。 【解決手段】光電子デバイスは、半導体基板１０上に形成された光電子セル１２のアレイを含む。セルは、下部分布ブラッグ反射器（ＤＢＲ）スタックを画定する第１のエピタキシャル層と、下部ＤＢＲスタックの上に形成され、量子井戸構造を画定する第２のエピタキシャル層と、量子井戸構造の上に形成され、上部ＤＢＲスタックを画定する第３のエピタキシャル層と、各光電子セルの量子井戸構造に励起電流を注入するように構成可能なＤＢＲスタックの上に形成された電極、とを含む。光電子セルの第１のセットは、励起電流に応じてレーザー光線を放射する。第１のセットに介挿された、光電子セル１６の第２のセットでは、エピタキシャル層及び電極の中から選択される光電子セルの少なくとも１つの素子は、第２のセット内の光電子セルがレーザー光線を放射しないように構成されている。 【選択図】図１

Creating arbitrary patterns on a 2-d uniform grid vcsel array

光电设备

本实用新型题为“光电设备”。本实用新型公开了一种光电设备，所述光电设备包括半导体基板和在半导体基板上形成的光电池阵列。光电池阵列包括第一外延层，所述第一外延层限定下分布式布拉格反射器(DBR)叠层；第二外延层，所述第二外延层在所述下DBR叠层上形成并限定量子阱结构；第三外延层，所述第三外延层在所述量子阱结构上形成并限定上DBR叠层；以及在上DBR叠层上形成的电极，所述电极可被配置为将激发电流注入到每个光电池的量子阱结构中。第一组光电池被配置为响应于激发电流而发射激光辐射。在与第一组交织的第二组光电池中，光电池的选自外延层和电极的至少一个元件被配置为使得第二组中的光电池不发射激光辐射。

Creating arbitrary patterns on a 2-d uniform grid vcsel array

An optoelectronic device includes a semiconductor substrate (10) and an array of optoelectronic cells (12), formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack (20); second epitaxial layers formed over the lower DBR stack, defining a quantum well structure (22); third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack (24); and electrodes (30) formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells (16), interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

Creating arbitrary patterns on a 2-d uniform grid vcsel array

An optoelectronic device includes a semiconductor substrate (10) and an array of optoelectronic cells (12), formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack (20); second epitaxial layers formed over the lower DBR stack, defining a quantum well structure (22); third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack (24); and electrodes (30) formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells (16), interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

Ancestral dengue virus envelope protein

Disclosed is a dengue virus envelope protein sequence derived via ascertainment of a most recent common ancestor of the three dengue serotype variants, DENV-1, DENV-2, DENV-3 and DENV-4. This synthetic dengue virus envelope protein can be used as a tetravalent vaccine in the prevention of dengue fever, dengue hemorrhagic fever and dengue septic shock.

垂直積層型画像センサ

【課題】フォトダイオードチップ及びトランジスタアレイチップを有する垂直積層型画像センサを提供する。【解決手段】フォトダイオードチップは、少なくとも１つのフォトダイオードを含み、転送ゲートは、フォトダイオードチップの上面から垂直方向に延びる。本画像センサは、フォトダイオードチップの上に積層されたトランジスタアレイチップを更に含む。トランジスタアレイチップは、制御回路及び蓄積ノードを含む。本画像センサは、トランジスタアレイチップ上に垂直方向に積層された論理チップを更に含む。転送ゲートは、少なくとも１つのフォトダイオードからトランジスタアレイチップにデータを通信し、論理チップは、垂直転送ゲート、リセットゲート、ソースフォロワゲート及び行選択ゲートを選択的に活性化する。【選択図】図８

垂直積層型画像センサ

【課題】フォトダイオードチップ及びトランジスタアレイチップを有する垂直積層型画像センサを提供する。【解決手段】フォトダイオードチップは、少なくとも１つのフォトダイオードを含み、転送ゲートは、フォトダイオードチップの上面から垂直方向に延びる。本画像センサは、フォトダイオードチップの上に積層されたトランジスタアレイチップを更に含む。トランジスタアレイチップは、制御回路及び蓄積ノードを含む。本画像センサは、トランジスタアレイチップ上に垂直方向に積層された論理チップを更に含む。転送ゲートは、少なくとも１つのフォトダイオードからトランジスタアレイチップにデータを通信し、論理チップは、垂直転送ゲート、リセットゲート、ソースフォロワゲート及び行選択ゲートを選択的に活性化する。【選択図】図８

垂直堆疊式影像感測器

本發明揭示一種具有一光電二極體晶片及一電晶體陣列晶片的垂直堆疊式影像感測器。該光電二極體晶片包括至少一光電二極體，及自該光電晶體晶片之一頂部表面垂直延伸的一傳送閘。該影像感測器進一步包括堆疊於該光電二極體晶片上的一電晶體陣列晶片。該電晶體陣列晶片包括控制電路及儲存節點。該影像感測器進一步包括垂直地堆疊於該電晶體陣列晶片上的一邏輯晶片。該傳送閘將資料自該至少一光電二極體傳達至該電晶體陣列晶片，且該邏輯晶片選擇性地啟動該垂直傳送閘、重設閘、源極隨耦器閘及列選擇閘。