10-01-2019 дата публикации
Номер: WO2019007009A1
Принадлежит:
A multilevel cell thin film transistor memory and a preparation method therefor. In terms of structure, the memory is sequentially provided with, from bottom to top, a gate electrode (10), a charge blocking layer (20), a charge trapping layer (30), a charge tunneling layer (40), an active area (50), and a source/drain electrode (60); the charge tunneling layer (40) fully surrounds the charge trapping layer (30) so as to fully isolate the charge trapping layer (30) from the outside; the material of the charge trapping layer (30) comprises any one of ZnO, In2O3, Ga2O3, SnO2, InSnO or IGZO. The charge trapping layer (30) of the thin film transistor memory is fully surrounded by the charge tunneling layer (40), and thus is fully isolated from the outside, such that the physical properties and chemical composition of the charge trapping layer (30) is prevented from changing in a technological process, loss of charges stored in the charge trapping layer (30) is reduced, and the data retention ...
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