Component mounting method

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to each other. The package structure is over the first surface, and includes a die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the exposed first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant encapsulates the package structure, and exposes at least part of the second conductive terminals ...

Device assembly structure and method of manufacturing the same

A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Pillar Design for Conductive Bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Printing complex electronic circuits

Fan out system in package and method for forming the same

Improved stack structures in electronic devices

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

Thin wafer handling and known good die test method

THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Printing complex electronic circuits

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

SEMICONDUCTOR DEVICE

A semiconductor device includes a lead, a semiconductor element, and a sealing resin. The lead includes an island portion having an obverse surface and a reverse surface facing opposite sides in a thickness direction. The semiconductor element is mounted on the obverse surface of the island portion. The sealing resin covers the semiconductor element and the island portion. The sealing resin has a first portion and a second portion that overlaps with the island portion as viewed in the thickness direction. The sealing resin is configured such that the infrared transmittance of the second portion is higher than that of the first portion.

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Chip-sized package and fabrication method thereof

Disclosed is a method of forming a chip scale package, comprising providing a plurality of electronic elements each having opposing active and non-active surfaces and a hard board, wherein each electronic element has electrode pads formed thereon; forming a soft layer on the hard board surface and adhering the electronic elements to the soft layer via the non-active surface thereof; compressing the electronic elements so as to be encapsulated by the soft layer while still being exposed from the active surfaces thereof; forming a dielectric layer on both the active surfaces of the electronic elements and the soft layers; forming a first circuit layer on the dielectric layer for electrically connecting to the electrode pads. The invention can overcome the drawbacks of encountering softened films, encapsulant overflow or warps and chip deviation and contamination that are caused by directly attaching the active surface of a chip to an adhesive film, which may even cause poor electrical connection ...

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer ...

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

Halbleitereinheit und Verfahren zur Herstellung derselben

Das Ziel besteht darin, eine intermetallische Verbindung mit einem hohen Schmelzpunkt in einem Zustand mit reduzieren Hohlräumen in einem Bond-Bereich zu bilden, in dem ein Bonden zwischen Bond-Objekten durchgeführt wird. Eine Halbleitereinheit (30) der vorliegenden Erfindung weist eine Legierungsschicht (13) auf, die sandwichartig zwischen einer ersten Ag-Schicht (4), die auf einer Montageplatte oder einer Leiterplatte (12) ausgebildet ist, und einer zweiten Ag-Schicht (10) eingefügt ist, die auf einem Halbleiterelement (9) ausgebildet ist, wobei die Legierungsschicht 13 eine intermetallische Verbindung aus Ag3Sn enthält, die von Ag-Komponenten der ersten Ag-Schicht (4) und der zweiten Ag-Schicht (10) sowie Sn gebildet wird, und wobei eine Vielzahl von Drähten (5), die Ag enthalten, so angeordnet ist, dass sie sich von einem nach außen gewandten Randbereich der Legierungsschicht (13) aus erstrecken.

Semiconductor package

Thin integrated circuit chip-on-board assembly

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board.

Pillar design for conductive bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

PRINTED CIRCUIT BOARD

A printed circuit board includes: a first board unit including a plurality of first insulating layers and a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers; a second board unit including one or more second insulating layers and one or more second wiring layers respectively disposed on or in the one or more second insulating layers; and a first passive device embedded in at least one of the first and second board units. The second board unit is disposed on the first board unit, and the first board unit has a second cavity passing through at least a portion of the plurality of first insulating layers on the first passive device based on a stacking direction of the plurality of first wiring layers.

STACK STRUCTURES IN ELECTRONIC DEVICES

The column design of the conductive bump

CHIP PACKAGE STRUCTURE

In one embodiment, a chip package structure can include: (i) a substrate; (ii) a top chip including a plurality of vias arranged through the top chip to form electrical connections between an active surface of the top chip and a back surface of the top chip; (iii) a redistribution layer arranged on the back surface of the top chip; and (iv) a plurality of wire bonds that form electrical connections between the substrate and electrodes on the redistribution layer on the back surface of the top chip.

A wafer type diode package element and producing method thereof

FAN OUT SYSTEM IN PACKAGE AND METHOD FOR FORMING THE SAME

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

INTEGRATED CIRCUIT PACKAGE

An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

LOW PROFILE INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING A PLURALITY OF DIES

An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (μm) or less.

Chip packaging structure

Chip scale package and fabrication method thereof

A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

Semiconductor device

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Structure and method for fabricating a computing system with an integrated voltage regulator module

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

A microelectronic assembly 10 can include a substrate 30 having first and second surfaces 34, 58, an aperture 39 extending therebetween, and terminals 36. The assembly 10 can also include a first microelectronic element 12 having a front surface 16 facing the first surface 34, a second microelectronic element 14 having a front surface 22 projecting beyond an edge 29 of the first microelectronic element, first and second leads 70, 76 electrically connecting contacts 20, 52 of the microelectronic elements to the terminals, and third leads 73 electrically interconnecting the contacts of the first and second microelectronic elements. The contacts 20 of the first microelectronic element 12 can be disposed adjacent the edge 29. The contacts 26 of the second microelectronic element 14 can be disposed in a central region 19 of the front surface 22 thereof. The leads 70, 76, 99 can have portions aligned with the aperture 39.

Semiconductor device

A semiconductor device includes a wiring layer formed on a first surface of a first insulation layer and including an external connection pad and an internal connection pad located at an inner side of the external connection pad. A semiconductor element facing the first surface of the first insulation layer includes an electrode pad located corresponding to the internal connection pad, a bump formed on the electrode pad and connected to the internal connection pad, and a circuit element region defined in a first surface of the semiconductor element at an inner side of the electrode pad. A second insulation layer fills a gap between the first surfaces of the semiconductor element and the first insulation layer. A third insulation layer covers a second surface of the semiconductor element and the second insulation layer and includes an opening that exposes the external connection pad connected to an external connection terminal.

관통 유리 비아를 갖는 고집적 수동소자 제조방법

... 본 발명의 일실시예에 따르면, 기판에서 관통 유리 비아가 형성될 부분을 결정화하여 제1 세라믹부를 형성하는 제1 단계, 상기 기판의 일면에 수동소자부를 형성하는 제2 단계, 및 상기 기판의 제1 세라믹부를 식각하여 관통홀을 형성하고, 상기 관통홀에 금속층을 형성하여 관통 유리 비아를 형성하는 제3 단계를 포함하는, 관통 유리 비아를 갖는 고집적 수동소자 제조방법을 제공하여, 감광성 유리 기판을 이용하여 고주파용 수동소자부를 제조할 수 있고, 관통 유리 비아를 내장하여 초고주파 대역에서 우수한 성능을 갖고, 습식 식각을 이용하여 기판에 관통홀을 쉽게 형성하므로 제조가 용이하다.

Semiconductor package

A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture ...

Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

Semiconductor device

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Halbleitereinheit und Verfahren zur Herstellung derselben

Halbleitereinheit (30), bei der ein Halbleiterelement (9) an eine Montageplatte oder eine Leiterplatte (12) gebondet ist, wobei die Halbleitereinheit (30) Folgendes aufweist:- eine Legierungsschicht (13), die sandwichartig zwischen einer ersten Ag-Schicht (4), die auf der Montageplatte (12) ausgebildet ist, und einer zweiten Ag-Schicht (10) eingefügt ist, die auf dem Halbleiterelement (9) ausgebildet ist; wobei die Legierungsschicht (13) eine intermetallische Verbindung aus Ag3Sn enthält, die durch Ag-Komponenten der ersten Ag-Schicht (4) und der zweiten Ag-Schicht (10) sowie Sn gebildet ist, und eine Vielzahl von Drähten (5), die Ag enthält, so angeordnet ist, dass sie sich von einem nach außen gewandten Randbereich der Legierungsschicht (13) aus erstrecken.

Semiconductor device and method of forming ultra high density embedded semiconductor die package

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first ...

STRUCTURE OF BATTERY PROTECTION CIRCUIT MODULE PACKAGE COUPLED WITH HOLDER, AND BATTERY PACK HAVING SAME

A battery pack includes a structure of a battery protection circuit module package coupled with a holder, the structure including a basic package including a lead frame consisting of leads spaced apart from each other, and protection circuit elements provided on the lead frame, and an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a melt of resin into the first injection mold to perform an insert injection molding process, a battery core pack coupled with the structure, and an upper case for casing an upper part of the battery core pack to embed the structure therein. The encapsulant encapsulates the protection circuit elements to expose parts of the lead frame. The encapsulant and the basic package configure the battery protection circuit module package. The holder is coupled to the battery protection circuit module package due to the molding process.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag3Sn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer.

Chip scale diode package no containing outer lead pins and process for producing the same

A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Halbleiterbauelement und Halbleiterpackage mit mehreren Halbleiterchips und einem Laminat und Herstellungsverfahren dafür

Halbleiterbauelement, umfassend:ein Laminat (1);einen ersten Leistungshalbleiterchip (8), der mindestens teilweise in dem Laminat (1) eingebettet ist;einen zweiten Leistungshalbleiterchip (2), der mindestens teilweise in dem Laminat (1) eingebettet ist;einen Steuerhalbleiterchip (3), der dazu ausgelegt ist, zumindest einen von dem ersten Leistungshalbleiterchip (8) und dem zweiten Leistungshalbleiterchip (2) zu steuern, wobei der Steuerhalbleiterchip (3) auf einer ersten Hauptoberfläche (4) des Laminats (1) montiert ist; undeinen ersten elektrischen Kontakt (10B), der auf der ersten Hauptoberfläche (4) des Laminats (1) angeordnet ist, wobei der Steuerhalbleiterchip (3) elektrisch an den ersten elektrischen Kontakt (10B) gekoppelt ist.

Transformer-based driver for power switches

Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be careless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.

RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE

A radio frequency module includes a mounting substrate, a low-noise amplifier including an amplifying element and amplifying a radio frequency signal, and an impedance matching circuit including an integrated first inductor, in which the first inductor is connected to an input terminal of the low-noise amplifier, the low-noise amplifier and the impedance matching circuit are laminated in a direction perpendicular to a main surface of the mounting substrate, and a first multilayer body on which the low-noise amplifier and the impedance matching circuit are laminated is mounted on the main surface.

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG MIT EINER PASTENSCHICHT UND HALBLEITERVORRICHTUNG

복합 전자 회로의 인쇄

... 프로그래밍 가능 회로는 마이크로스코픽 트랜지스터들 또는 다이오드들의 인쇄된 그룹들의 어레이를 포함한다. 디바이스들은 잉크로서 사전-형성되고 인쇄되고 경화된다. 각각의 그룹 내의 디바이스들은 각각의 그룹이 단일 디바이스로서 동작하도록 병렬로 접속된다. 일 실시예에서, 각각의 그룹 내에 약 10개의 디바이스들이 포함되어, 잉여성은 각각의 그룹을 매우 신뢰성있게 한다. 각각의 그룹은 기판상의 패치 영역에서 종단하는 적어도 하나의 전기적 리드를 구비한다. 상호접속 도전체 패턴은 일반적인 회로의 맞춤화된 적용을 위한 로직 회로를 생성하기 위해 패치 영역에서 그룹들의 리드들 중 적어도 일부를 상호접속시킨다. 그룹들은 또한 로직 게이트들이 되도록 상호접속될 수 있고, 게이트 리드들은 패치 영역에서 종단한다. 다음에, 상호접속 도전체 패턴은 복잡한 로직 회로들을 형성하기 위해 게이트들을 상호접속시킨다.

FAN OUT SYSTEM IN PACKAGE AND METHOD FOR FORMING THE SAME

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

SILICON SHIELD FOR PACKAGE STRESS SENSITIVE DEVICES

외부 리드 핀들을 포함하지 않는 칩 스케일 다이오드 패키지 및 이를 생산하기 위한 공정

... 새로운 칩 스케일 다이오드 패키지는 외부 리드 핀들을 포함하지 않음으로 치수 정확성을 향상시키기 위해 칩 스케일 외관과 같이 소형화되고, 그 결과로 다이오드 패키지는 자동화된 대량 생산을 하도록 자동화장치에 의해 적절하게 생산되며; 생산된 다이오드 패키지는 SMT 다이오드 패키지 또는 어레이-타입 SMT 다이오드가 적용되어 더 유용하게 다양한 기능들을 향상시키기 위한 하나 이상의 다이오드 칩을 포함할 수 있으며, 본 발명의 다이오드 패키지는 연을 함유하지 않는 재료로 제조됨으로 인해 환경 보호에 대한 요건들을 만족시킨다.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ULTRA HIGH DENSITY EMBEDDED SEMICONDUCTOR DIE PACKAGE

Improved stack structures in electronic devices

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ULTRA HIGH DENSITY EMBEDDED SEMICONDUCTOR DIE PACKAGE

Plurality of semiconductor devices in resin with a via

According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.

INTEGRATED CIRCUIT PACKAGE

A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

Device electrode formation using metal sheet

A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact.

Structure and method for fabricating a computing system with an integrated voltage regulator module

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Integrated Circuit Package and Method

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

Carrier-bonding methods and articles for semiconductor and interposer processing

A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Improved stack structures in electronic devices

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

Structure of battery protection circuit module package coupled with holder and battery pack including the same

Structure and method for fabricating a computing system with an integrated voltage regulator module

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Radio frequency module and communication device

A radio frequency module includes a mounting substrate, a low-noise amplifier including an amplifying element and amplifying a radio frequency signal, and an impedance matching circuit including an integrated first inductor, in which the first inductor is connected to an input terminal of the low-noise amplifier, the low-noise amplifier and the impedance matching circuit are laminated in a direction perpendicular to a main surface of the mounting substrate, and a first multilayer body on which the low-noise amplifier and the impedance matching circuit are laminated is mounted on the main surface.

Multi-Terminal Device Packaging

A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact.

METHOD OF TEMPORARILY OR PERMANENTLY ATTACHING MICROELECTRONIC DEVICES OR INTERPOSERS TO SUBSTRATE FOR MOUNTING, HANDLING OR TESTING AND COMPONENTS USEFUL THEREFOR

A method of attaching a microelectronic element 30 to a substrate 20 can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps 34 each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses 24 extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Halbleiterbauelement mit mehreren Halbleiterchips und einem Laminat

Ein Halbleiterbauelement beinhaltet ein Laminat, einen ersten Halbleiterchip, der mindestens teilweise in dem Laminat eingebettet ist, einen zweiten Halbleiterchip, der auf einer ersten Hauptoberfläche des Laminats montiert ist, und einen ersten elektrischen Kontakt, der auf der ersten Hauptoberfläche des Laminats angeordnet ist. Der zweite Halbleiterchip ist elektrisch an den ersten elektrischen Kontakt gekoppelt.

팬 아웃 시스템 인 패키지 및 이의 형성 방법

... 패키지들 및 형성 방법들이 기술된다. 실시예에서, 시스템 인 패키지(SiP)는 제1 및 제2 재배선층(RDL)들, 제1 RDL(110)과 제2 RDL(210) 사이의 적층된 다이(130, 140), 및 RDL들 사이에서 연장되는 전도성 필러들(120)을 포함한다. 성형 화합물(105)은 제1 RDL과 제2 RDL 사이의 적층된 다이 및 전도성 필러들을 캡슐화할 수 있다.

캐리어 결합 방법, 및 반도체 및 인터포저 가공을 위한 물품

... 물품(2)을 형성하도록 표면 개질 층(30)을 통해 캐리어(10) 상에 배치된 얇은 시트(20)이며, 여기서 물품은 FEOL 반도체 가공에서와 같이 고온 가공에 적용될 수 있고, 기체방출하지 않고, 가공 동안 캐리어로부터 분리되지 않으면서 캐리어 상에 유지되나 얇은 시트 및 캐리어 중 더 얇은 것을 온전하게 남아있게 하는 실온 박리력에 의해서는 캐리어로부터 분리되는 얇은 시트를 갖는다. 비아(60)의 어레이(50)를 갖는 인터포저(56)는 얇은 시트 상에 형성될 수 있고, 장치(66)는 인터포저 상에 형성될 수 있다. 대안적으로, 얇은 시트는 FEOL 가공 동안 그 위에 반도체 회로가 형성된 기판일 수 있다.

Semiconductor device and method of forming ultra high density embedded semiconductor die package

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first ...

Chipscale-Diodenpaket ohne äußere Leiterstifte und Herstellungsverfahren dafür

Ein neuartiges Chipscale-Diodenpaket kann aufgrund nicht vorhandener äußerer Leiterstifte so klein wie ein Chip zugunsten höherer Maßgenauigkeit gefertigt werden, so dass das Diodenpaket in geeigneter Weise mithilfe von Automatisierungseinrichtungen in automatisierter Serienfertigung produziert werden kann; das produzierte Diodenpaket kann einen oder mehrere Diodenchips enthalten, um vielseitige Funktionen in nützlicheren Anwendungen zu erhöhen, und kann beispielsweise als SMT-Diodenpaket oder ein SMT-Diodenpaket vom Anordnungstyp ausgeführt werden; und da das erfindungsgemäße Diodenpaket ohne bleihaltige Materialien hergestellt wird, erfüllt es alle Anforderungen bezüglich des Umweltschutzes.

CARRIER-BONDING METHODS AND ARTICLES FOR SEMICONDUCTOR AND INTERPOSER PROCESSING

THIN INTEGRATED CIRCUIT CHIP-ON-BOARD ASSEMBLY AND METHOD OF MAKING

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

The battery protection circuit module package and the fixing frame and the combination structure of the body of the battery pack having the structure

복합 전자 회로의 인쇄

... 프로그래밍 가능 회로는 마이크로스코픽 트랜지스터들 또는 다이오드들의 인쇄된 그룹들의 어레이를 포함한다. 디바이스들은 잉크로서 사전-형성되고 인쇄되고 경화된다. 각각의 그룹 내의 디바이스들은 각각의 그룹이 단일 디바이스로서 동작하도록 병렬로 접속된다. 일 실시예에서, 각각의 그룹 내에 약 10개의 디바이스들이 포함되어, 잉여성은 각각의 그룹을 매우 신뢰성있게 한다. 각각의 그룹은 기판상의 패치 영역에서 종단하는 적어도 하나의 전기적 리드를 구비한다. 상호접속 도전체 패턴은 일반적인 회로의 맞춤화된 적용을 위한 로직 회로를 생성하기 위해 패치 영역에서 그룹들의 리드들 중 적어도 일부를 상호접속시킨다. 그룹들은 또한 로직 게이트들이 되도록 상호접속될 수 있고, 게이트 리드들은 패치 영역에서 종단한다. 다음에, 상호접속 도전체 패턴은 복잡한 로직 회로들을 형성하기 위해 게이트들을 상호접속시킨다.

Chip-sized package and fabrication method thereof

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture ...

Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first ...

DEVICE ASSEMBLY STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

Thin Wafer Handling and Known Good Die Test Method

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG MIT EINERPASTENSCHICHT UND HALBLEITERVORRICHTUNG

Verfahren zur Herstellung einer Halbleitervorrichtung, die eine Pastenschicht umfasst, umfassend das Anbringen eines Substrats an einem Träger, wobei das Substrat eine Vielzahl von Halbleiterdies umfasst, das Aufbringen einer Schicht aus einer Paste auf das Substrat, das Strukturieren der Schicht über den Schneidbereichen des Substrats und das Schneiden des Substrats entlang der Schneidbereiche.

Pillar design for conductive bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Structure and Method for Fabricating a Computing System with an Integrated Voltage Regulator Module

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Semiconductor device including multiple semiconductor chips and a laminate

A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first main surface of the laminate, and a first electrical contact arranged on the first main surface of the laminate. The second semiconductor chip is electrically coupled to the first electrical contact.

Structure of battery protection circuit module package coupled with holder, and battery pack having same

A battery pack includes a battery protection circuit module package coupled with a holder. The protection circuit module includes a basic package including a lead frame having a plurality of leads spaced apart from each other, and protection circuit elements provided on the lead frame, and an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a resin melt into the first injection mold to perform an insert injection molding process. The encapsulant encapsulates the protection circuit elements to expose parts of the lead frame, wherein the encapsulant and the basic package configure the battery protection circuit module package, and wherein the holder is coupled to the battery protection circuit module package due to the insert injection molding process.

Pillar Design for Conductive Bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive ...

THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

ELECTRONIC PACKAGING STRUCTURE

An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between ...

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture ...

Multi-terminal device packaging using metal sheet

A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact.

Semiconductor Device Package and Method of the Same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Copper interconnection structure and method for forming copper interconnections

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

Light emitting device package and a lighting device

Provided are a light emitting device package and a lighting device. The light emitting device package includes a base, a light emitting device on the base, a plurality of electrode pads on the base, the plurality of electrode pads electrically connected to the light emitting device, a frame disposed on the base, wherein a size of the frame is smaller than a size of the base, a silver layer on a portion of the plurality of electrode pads, the silver layer directly contacted with the frame and an optical member covering the light emitting device.

Protecting bond pad for subsequent processing

A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.

System-in-a-package based flash memory card

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Light emitting device having a lateral passibation layer

Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a passivation layer protecting a surface of the light emitting structure. The passivation layer includes a first passivation layer on a top surface of the light emitting structure and a second passivation layer having a refractive index different from that of the first passivation layer, the second passivation layer being disposed on a side surface of the light emitting structure. The second passivation layer has a refractive index greater than that of the first passivation layer.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Led package and method for manufacturing the same

An LED package includes a substrate, an LED chip, a bounding dam, and a first encapsulation. The substrate includes a first surface and a second surface opposite to the first surface. The LED chip is mounted on the first surface of the substrate. The bounding dam is formed on the first surface of the substrate and surrounds the LED chip. The bounding dam and the substrate cooperatively define a receiving space. The bounding dam is made of thermoset resin. The first encapsulation is formed in the receiving space and encloses the LED chip.

Semiconductor light emitting device substrate strips and packaged semiconductor light emitting devices

Semiconductor light emitting device packaging methods include fabricating a substrate configured to mount a semiconductor light emitting device thereon. The substrate may include a cavity configured to mount the semiconductor light emitting device therein. The semiconductor light emitting device is mounted on the substrate and electrically connected to a contact portion of the substrate. The substrate is liquid injection molded to form an optical element bonded to the substrate over the semiconductor light emitting device. Liquid injection molding may be preceded by applying a soft resin on the electrically connected semiconductor light emitting device in the cavity. Semiconductor light emitting device substrate strips are also provided.

Chip having a driving integrated circuit

A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Method for fabrication of a semiconductor device and structure

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Semiconductor device and method for producing such a device

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

High-voltage packaged device

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Light emitting device

A light emitting device, which has: a light emitting element; a package that comprises a concavity for holding the light emitting element, and that has on its side wall where the concavity is integrally formed a light reflector for reflecting light from the light emitting element and a light transmitter for transmitting light from the light emitting element to the outside.

Semiconductor device with less power supply noise

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Light emitting device and manufacturing method thereof

A light emitting device according to one embodiment includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the following equation (1) and an average particle diameter of 12 μm or more. (M 1−x1 Eu x1 ) 3−y Si 13−z Al 3+z O 2+u N 21−w   (1) (In the equation ( 1 ), M is an element that is selected from IA group elements, IIA group elements, IIIA group elements, IIIB group elements except Al, rare-earth elements, and IVB group elements. x1, y, z, u, and w satisfy the following relationship. 0<x1<1, −0.1<y<0.3, −3<z≦1, −3<u−w≦1.5)

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Method of processing of nitride semiconductor wafer, nitride semiconductor wafer, method of producing nitride semiconductor device and nitride semiconductor device

A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer.

Light emitting device

The present disclosure provides a light emitting device, including a serially-connected LED array including a plurality of LED cells on a single substrate, including a first LED cell, a second LED cell, and a serially-connected LED sub-array including at least three LED cells intervening the first and second LED cell, wherein each of the first and second LED cell including a first side and a second side that the first side of the first LED cell and/or the second LED cell neighboring to the LED sub-array, and the second side of the first LED cell neighboring to the second side of the second LED cell; a trench between the second sides of the first and second LED cells; and a protecting structure formed near the trench to prevent the light-emitting device from being damaged near the trench by a surge voltage higher than a normal operating voltage of the light emitting device.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Method for manufacturing electronic parts device and resin composition for electronic parts encapsulation

The present invention relates to a method for manufacturing an electronic parts device allowing for easy overmolding and underfilling without requiring a jig for preventing leakage of the melted resin composition, and a resin composition sheet for electronic parts encapsulation used therein.

Light emitting device and manufacturing method of light emitting device

A light emitting device may include a base provided with a recess portion in a side surface thereof, a light emitting element mounted on a main surface of the base, a first resin body filled in an inside of the recess portion, and covering at least the main surface and the light emitting element, a second resin body covering an outside of the first resin body from the main surface side to at least a position of the lowermost end of the recess portion in a direction orthogonal to the main surface, and phosphor, provided in the second resin body, for absorbing light emitted from the light emitting element and then emitting light having a different wavelength.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Method of making a light emitting device having a molded encapsulant

Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Led package structure

An LED package structure includes a heat conductive plate defining a concave groove therein, an LED die received in the concave groove, an eutectic layer sandwiched between the heat conductive plate and the substrate, a transparent encapsulant encapsulating the LED die on the heat conductive plate. The heat conductive plate forms an electrode circuit layer on the heat conductive plate around the concave groove. The LED die forms electrodes electrically connected with the electrode circuit layer. An electrically insulating heat conduction grease filled around the substrate and the eutectic layer.

Method and system for minimizing carrier stress of a semiconductor device

A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Light emitting diode package and method of making the same

The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Light Emitting Device

Embodiments relate to a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises: a substrate; a light emitting structure over the substrate, the light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the first conductive type semiconductor layer is partially exposed; a first region having a first concentration and provided at a region of the second conductive type semiconductor layer; a second region having a second concentration and provided at another region of the second conductive type semiconductor layer; and a second electrode over the second conductive type semiconductor layer.

Light emitting diode package

An exemplary light emitting diode (LED) package includes a substrate, an LED chip mounted on the substrate, and a wire. The LED chip includes a semiconductor structure and an electrode disposed on the semiconductor structure. The wire electrically connects the electrode of the LED chip to an electrical portion of the substrate. The wire has a first joint and a second joint connected to the substrate. The wire forms a first curved portion between the electrode and the first joint and a second curved portion between the first joint and the second joint.

Optoelectronic semiconductor component and method for producing an inorganic optoelectronic semiconductor component

An optoelectronic semiconductor component includes a carrier and at least one semiconductor layer sequence. The semiconductor layer sequence includes at least one active layer. The semiconductor layer sequence is furthermore mounted on the carrier. The semiconductor component furthermore includes a metal mirror located between the carrier and the semiconductor layer sequence. The carrier and the semiconductor layer sequence project laterally beyond the metal mirror. The metal mirror is laterally surrounded by a radiation-transmissive encapsulation layer.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 . By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 , and improve the crystal quality of the epitaxial layer 22 . Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Base plate

The present disclosure relates to a base plate, for example, for a power module, including a matrix formed of metal, for example, aluminium, wherein at least two reinforcements are provided in the matrix next to each other, and wherein the reinforcements are spaced apart from each other.

Laser ashing of polyimide for semiconductor manufacturing

A method for laser ashing of polyimide for a semiconductor manufacturing process using a structure, the structure comprising a supporting material attached to a semiconductor chip by a polyimide glue, includes releasing the supporting material from the polyimide glue, such that the polyimide glue remains on the semiconductor chip; and ashing the polyimide glue on the semiconductor chip using an ablating laser.

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Semiconductor structure and manufacturing method thereof

In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

Illumination apparatus

According to one embodiment, an illumination apparatus includes an LED (Light Emitting Diode) module, a light guide plate, and a support body. The support body supports the LED module and the light guide plate. A reflective surface of the support body is provided between a portion supporting the LED module and a portion supporting the light guide plate. The reflective surface is reflective with respect to the light emitted from the LED package. The LED module is tilted relative to the reflective surface with the LED package mounting surface being toward the reflective surface. An angle between the LED module and the reflective surface is less than 90°.

Light emitting devices and methods

Light emitting devices and methods such as light emitting diodes (LEDs) are disclosed for use in higher voltage applications. Variable arrangements of LEDs are disclosed herein. Arrangements can include one or more LED chips connected in series, parallel, and/or a combination thereof. LED chips can be disposed in a package body having at least one thermal element and one or more electrical components.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Illumination unit, projection display unit, and direct view display unit

An illumination unit includes a plurality of light sources each including a solid-state light-emitting device configured to emit light from a light emission region including a single or a plurality of light-emitting spots. The solid-state light-emitting device includes a single chip or a plurality of chips each emitting light beam. Three or more of the light-emitting spots are provided within the whole light sources, to allow the whole light sources to emit light beams in two or more wavelength bands different from one another. Two or more of the plurality of the light sources include respective light-emitting spots which emit light in the same wavelength band.

Wafer mold material and method for manufacturing semiconductor apparatus

The invention provides a wafer mold material for collectively subjecting a wafer having semiconductor devices on a surface thereof to resin molding, wherein the wafer mold material has a resin layer containing a filler and at least any one of an acrylic resin, a silicone resin having an epoxy group, an urethane resin, and a polyimide silicone resin, and the wafer mold material is formed into a film-like shape. There can be a wafer mold material that enables collective molding (wafer molding) with respect to a wafer having semiconductor devices formed thereon, has excellent transference performance with respect to a large-diameter thin-film wafer, can provide a flexible hardened material with low-stress properties, and can be preferably used as a mold material in a wafer level package with less warp of a formed (molded) wafer.

Acrylate composition

The invention provides a composition containing (A) one or more (meth)acrylate compounds selected from among a (meth)acryl-modified silicone fluid, a long-chain alkyl(meth)acrylate, and a polyalkylene glycol(meth)acrylate having a number average molecular weight of 400 or more; (B) a (meth)acrylate compound having an alicyclic hydrocarbon group which has six or more carbon atoms and which is bonded to the compound via an ester bond; (C) (meth)acrylic acid or a (meth)acrylate compound having a polar group; and (D) a radical polymerization initiator. The composition is suitably employed as a raw material for, for example, an encapsulating material or a lens, exhibits transparency and heat resistance comparable to conventional levels, and provides a cured product exhibiting excellent adhesion to a base member surrounding the cured product.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Optical module

There are provided an optical module including a semiconductor laser including a P-side electrode and an N-side electrode, and a semiconductor laser driver circuit that drives the semiconductor laser so as to output an optical signal from the semiconductor laser according to a pattern of a differentially transmitted digital electric signal, and the semiconductor laser driver circuit includes a positive-side terminal and a negative-side terminal for differentially transmitted non-inverted data, and a positive-side terminal and a negative-side terminal for differentially transmitted inverted data, and one terminal for the non-inverted data is electrically connected to one electrode of the semiconductor laser, and the other terminal for the non-inverted data, one terminal for the inverted data and the other terminal for the inverted data each are connected to the other electrode of the semiconductor laser.

Mold release film and process for producing light emitting diode

To provide a mold release film for producing a light emitting diode by a mold, which is less susceptible to formation of pin holes or rupture and which is applicable to mass production of a light emitting diode by means of a mold having a plurality of cavities, and a process for producing a light emitting diode by means of such a mold release film. A mold release film to be disposed on the cavity surface of a mold to form a substantially hemispherical lens portion by encapsulating a light emitting element of a light emitting diode with an encapsulation resin, which release film has a thickness of from 16 to 175 μm and a tensile rupture elongation of from 600 to 3,000% at 110° C. as measured in accordance with JIS K7127, and a process for producing a light emitting diode by means of such a mold release film.

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Light emitting diode, light emitting diode lamp, and illuminating apparatus

Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (Al X1 Ga 1-X1 )As (0≦X 1 ≦1) and a barrier layer which comprises a composition expressed by the composition formula of (Al X2 Ga 1-X2 )As (0<X 2 ≦1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (Al X3 Ga 1-X3 ) Y1 In 1-Y1 P (0≦X 3 ≦1, 0<Y 1 ≦1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Substrate bonding method and semiconductor device

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Solid element device and method for manufacturing the same

A method of making a solid element device that includes a solid element, an element mount part on which the solid element is mounted and which has a thermal conductivity of not less than 100 W/mK, an external terminal provided separately from the element mount part and electrically connected to the solid element, and a glass sealing part directly contacting and covering the solid element for sealing the solid element, includes pressing a glass material at a temperature higher than a yield point of the glass material for forming the glass sealing part.

Hybrid bonding interface for 3-dimensional chip integration

Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

Light emitting diodes and method for manufacturing the same

An exemplary LED includes an electrode layer, an LED die, a transparent electrically conductive layer, and an electrically insulating layer. The electrode layer includes a first section and a second section electrically insulated from the first section. The LED die is arranged on and electrically connected to the second section of the electrode layer. The transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. The electrically insulating layer is located between the LED die and the transparent electrically conductive layer to insulate the transparent electrically conductive layer from the second section of the electrode layer.

Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts

A test fixture ( 120 ) is disclosed for electrically testing a device under test ( 130 ) by forming a plurality of temporary mechanical and electrical connections between terminals ( 131 ) on the device under test ( 130 ) and contact pads ( 161 ) on the load board ( 160 ). The test fixture ( 120 ) has a replaceable membrane ( 150 ) that includes vias ( 151 ), with each via ( 151 ) being associated with a terminal ( 131 ) on the device under test ( 130 ) and a contact pad ( 161 ) on the load board ( 160 ). In some cases, each via ( 151 ) has an electrically conducting wall for conducting current between the terminal ( 131 ) and the contact pad ( 161 ). In some cases, each via ( 151 ) includes a spring ( 152 ) that provides a mechanical resisting force to the terminal ( 131 ) when the device under test ( 130 ) is engaged with the test fixture ( 120 ).

Adhesive film for light emitting device and method of manufacturing led package using the same

Provided is an adhesive film for an LED chip, including: a double-sided adhesive layer having the LED chip adhered to an upper surface thereof and a lead frame adhered to a lower surface thereof; an ultraviolet (UV) cured layer adhered to one surface of the double-sided adhesive layer; and upper and lower cover layers respectively adhered to faces exposed to the exterior of the double-sided adhesive layer and the UV cured layer.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Porous Thermoplastic Foams as Heat Transfer Materials

Interconnected, open-celled porous or microporous polymeric foams are used for the preparation of heat transfer devices. The use of such porous polymeric foams can generate a turbulent flow within a heat exchanging liquid, thus enabling increased heat transfer to and from the fluid. The present disclosure provides devices having a heat transfer element containing a heat exchange region wherein a heat exchange fluid can be circulated through a porous polymeric foam; and method for making and using such devices.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A hybrid photo-patternable dielectric material is provided that has dual-tone properties with a parabola like dissolution response to radiation. In one embodiment, the hybrid photo-patternable dielectric material includes a composition of at least one positive-tone component including a positive-tone polymer, positive-tone copolymer, or blends of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, negative-tone copolymer, or blends of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components.

Reprogrammable circuit board with alignment-insensitive support for multiple component contact types

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Semiconductor device and manufacturing method of the same

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Semiconductor device

Disclosed is a semiconductor device configured by encapsulating a semiconductor element, partially or entirely covered with a polyimide, using an epoxy resin composition for encapsulating semiconductor device which contains an epoxy resin (A), a phenol resin (B), a curing accelerator (C), an inorganic filler (D), and a silane coupling agent (E) represented by the formula (1): (in the formula (1), each of R 1 , R 2 and R 3 represents a C 1-4 hydrocarbon group, all of them may be the same or different from each other, and n represents an integer from 0 to 2), and/or a hydrolytic condensate thereof.