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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 30703. Отображено 100.
02-02-2012 дата публикации

Semiconductor device comprising a passive component of capacitors and process for fabrication

Номер: US20120025348A1
Автор: Laurent Marechal, Romain Coffy, Yvon Imbs
Принадлежит: STMicroelectronics Grenoble 2 SAS

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

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Номер записи: 1
02-02-2012 дата публикации

Semiconductor device and semiconductor package including the same

Номер: US20120025349A1
Автор: Hyun-seok Kim, Hyung-Dong Lee, Jun-Ho Lee
Принадлежит: Individual

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

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Номер записи: 2
02-02-2012 дата публикации

Methods of operating electronic devices, and methods of providing electronic devices

Номер: US20120028582A1
Автор: Patrick W. Tandy
Принадлежит: Round Rock Research LLC

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

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Номер записи: 3
09-02-2012 дата публикации

Energy Conditioning Circuit Arrangement for Integrated Circuit

Номер: US20120034774A1
Автор: Anthony A. Anthony, William M. Anthony
Принадлежит: X2Y Attenuators LLC

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

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Номер записи: 4
16-02-2012 дата публикации

High-frequency switch

Номер: US20120038411A1
Автор: Hirotsugu Wakimoto, Masanori Ochi, Masayuki Sugiura, Noriyasu Kurihara, Toshiki Seshita, Toshiyuki Shimizu, Yoshio Itagaki, Yoshitomo Sagae
Принадлежит: Toshiba Corp

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

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Номер записи: 5
01-03-2012 дата публикации

Light emitting device

Номер: US20120049208A1
Автор: Chao Hsing Chen, Chien Fu Shen, Hsin Mao Liu, Schang Jing Hon, Tsun Kai Ko
Принадлежит: Individual

The present disclosure provides a light emitting device, including a serially-connected LED array including a plurality of LED cells on a single substrate, including a first LED cell, a second LED cell, and a serially-connected LED sub-array including at least three LED cells intervening the first and second LED cell, wherein each of the first and second LED cell including a first side and a second side that the first side of the first LED cell and/or the second LED cell neighboring to the LED sub-array, and the second side of the first LED cell neighboring to the second side of the second LED cell; a trench between the second sides of the first and second LED cells; and a protecting structure formed near the trench to prevent the light-emitting device from being damaged near the trench by a surge voltage higher than a normal operating voltage of the light emitting device.

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Номер записи: 6
08-03-2012 дата публикации

Semiconductor package and manufacturing method for a semiconductor package as well as optical module

Номер: US20120056292A1
Автор: Masami Suzuki, Masayuki Nagao, Yasuyuki Ito
Принадлежит: Sony Corp

A semiconductor package includes: a supporting substrate; a functioning element and a first joining element formed on a first principal surface of the supporting substrate; a sealing substrate disposed in an opposing relationship to the supporting substrate with the functioning element and the first joining element interposed therebetween; a second joining element provided on a second principal surface of the supporting substrate; a through-electrode provided in and extending through the supporting substrate and adapted to electrically connect the first and second joining elements; and a first electromagnetic shield film coated in an overall area of a side face of the supporting substrate which extends perpendicularly to the first and second principal surfaces.

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Номер записи: 7
08-03-2012 дата публикации

Baluns for rf signal conversion and impedance matching

Номер: US20120056297A1
Автор: Petteri Litmanen, Richard Francis Taylor, Siraj Akhtar
Принадлежит: Texas Instruments Inc

A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.

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Номер записи: 8
15-03-2012 дата публикации

Shockley diode having a low turn-on voltage

Номер: US20120061719A1
Автор: Samuel Menard, Yannick Hague
Принадлежит: STMicroelectronics Tours SAS

A Shockley diode including: a vertical stack of first to fourth layers of alternated conductivity types between first and second electrodes; a recess formed in the fourth layer and extending vertically to penetrate into the second layer; a first region of same conductivity type as the second layer but of greater doping level, extending at the bottom of the recess in the second layer; and a second region of same conductivity type as the third layer but of greater doping level, extending along the lateral walls of the recess and connecting the first region to the fourth layer.

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Номер записи: 9
15-03-2012 дата публикации

Control device of semiconductor device

Номер: US20120061722A1
Автор: Masahiro MASUNAGA, Takayuki Hashimoto
Принадлежит: Renesas Electronics Corp

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

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Номер записи: 10
15-03-2012 дата публикации

Power amplifier circuit

Номер: US20120062325A1
Автор: Joong Jin NAM, Jun Goo WON, Ki Joong KIM, Seong Geon KIM, Youn Suk Kim
Принадлежит: Samsung Electro Mechanics Co Ltd

There is provided a power amplifier circuit capable of improving cross isolation between a high frequency band power coupler and a low frequency band power coupler, by directly transmitting power to the high frequency band power coupler and the low frequency band power coupler from a power amplifier, and forming a predetermined inductance circuit or an LC resonance circuit in a line transmitting the power to the high frequency band power coupler. The power amplifier circuit may include a power amplifying unit supplied with power from the outside and amplifying an input signal, a coupling unit having a high frequency band power coupler and a low frequency band power coupler, and an isolation unit including a first power line and a second power line, wherein the first power line has an inductor blocking signal interference generated in a predetermined frequency band.

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Номер записи: 11
15-03-2012 дата публикации

Semiconductor device including coupling conductive pattern

Номер: US20120064827A1
Автор: Hee-Seok Lee, Jong-Joo Lee, Sang-Youb Lee, Yong-Hoon Kim, Young-don Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

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Номер записи: 12
22-03-2012 дата публикации

Monolithic magnetic induction device

Номер: US20120068301A1
Автор: Johnny Kin On Sin, Ron Shu Yuen Hui, Rongxiang Wu
Принадлежит: Hong Kong University of Science and Technology HKUST

Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

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Номер записи: 13
22-03-2012 дата публикации

Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer

Номер: US20120068303A1
Автор: Hyung Sun Yook, Poh Ching Sim, Tsui Ping Chu
Принадлежит: Individual

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

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Номер записи: 14
22-03-2012 дата публикации

High speed digital interconnect and method

Номер: US20120068890A1
Автор: Baher S. Haroun, Marco Corsi, Nirmal C. Warke, Siraj Akhtar
Принадлежит: Texas Instruments Inc

In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

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Номер записи: 15
19-04-2012 дата публикации

Scratch protection for direct contact sensors

Номер: US20120091517A1
Автор: Danielle A. Thomas
Принадлежит: Individual

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

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Номер записи: 16
19-04-2012 дата публикации

Rf bus controller

Номер: US20120093132A1
Автор: Ahmadreza (Reza) Rofougaran
Принадлежит: Broadcom Corp

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

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Номер записи: 17
26-04-2012 дата публикации

Chip structure and process for forming the same

Номер: US20120098128A1
Автор: Ching-Cheng Huang, Jin-Yuan Lee, Mou-Shiung Lin
Принадлежит: Megica Corp

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

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Номер записи: 18
03-05-2012 дата публикации

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

Номер: US20120104588A1
Автор: Hong-Chin Lin, Nan-Jang Chen
Принадлежит: MediaTek Inc

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

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Номер записи: 19
10-05-2012 дата публикации

Semiconductor Inductor with a Serpentine Shaped Conductive Wire and a Serpentine Shaped Ferromagnetic Core and a Method of Forming the Semiconductor Inductor

Номер: US20120112296A1
Автор: Andrei Papou, Peter J. Hopper, Peter Smeys
Принадлежит: National Semiconductor Corp

The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

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Номер записи: 20
31-05-2012 дата публикации

Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method

Номер: US20120133021A1
Автор: Alexy Farcy, Jean-François Carpentier, Pierre Bar, Sylvain Joblot
Принадлежит: STMicroelectronics Crolles 2 SAS, STMICROELECTRONICS SA

A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.

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Номер записи: 21
31-05-2012 дата публикации

Radiofrequency amplifier

Номер: US20120133442A1
Автор: Igor Blednov
Принадлежит: NXP BV

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

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Номер записи: 22
14-06-2012 дата публикации

Semiconductor device

Номер: US20120146176A1
Автор: Fumio Sasaki, Ryoichi Ohara, Yoshitomo Sagae
Принадлежит: Toshiba Corp

A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors.

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Номер записи: 23
14-06-2012 дата публикации

Applying trenched transient voltage suppressor (tvs) technology for distributed low pass filters

Номер: US20120146717A1
Автор: Madhur Bobde
Принадлежит: Madhur Bobde

An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

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Номер записи: 24
21-06-2012 дата публикации

Integrated millimeter wave transceiver

Номер: US20120154238A1
Автор: Jean-François Carpentier, Patrice Garcia, Pierre Busson, Pierre Dautriche, Sebastien Pruvost
Принадлежит: STMICROELECTRONICS SA

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

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Номер записи: 25
05-07-2012 дата публикации

Rf-power device

Номер: US20120168840A1
Автор: Marnix Bernard Willemsen
Принадлежит: NXP BV

An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

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Номер записи: 26
05-07-2012 дата публикации

Rf identification device with near-field-coupled antenna

Номер: US20120171953A1
Автор: Alberto Pagani, Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Ferla, Giuseppe Palmisano
Принадлежит: STMICROELECTRONICS SRL

An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

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Номер записи: 27
19-07-2012 дата публикации

Esd protection against charge coupling

Номер: US20120182663A1
Автор: Christopher A. Bennett, Taeghyun Kang
Принадлежит: Individual

This document discusses among other things apparatus and methods for reducing ESD damage to buffer circuits. In an example, an output buffer can include an output, a first transistor configured to couple the output to a high logic supply rail, a second transistor configured to couple the output node to a low logic supply rail, pre-driver logic configured to drive a gate of the first transistor and a gate of the second transistor, and a first resistor configured to reduce electrostatic discharge (ESD) induced current between the first transistor and the pre-driver logic.

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Номер записи: 28
26-07-2012 дата публикации

Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure

Номер: US20120187531A1
Автор: ByungHoon Ahn, Gwang Kim, HyunTai Kim, YongTaek Lee
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.

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Номер записи: 29
26-07-2012 дата публикации

Integrated structures of high performance active devices and passive devices

Номер: US20120192139A1
Автор: Anthony K. Stamper, Daniel S. Vanslette, Robert M. Rassel
Принадлежит: International Business Machines Corp

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

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Номер записи: 30
02-08-2012 дата публикации

Power module and the method of packaging the same

Номер: US20120194148A1
Автор: Bai-Yao Lou, Chien-Hung Liu, Ho-Yin Yiu, Wei-Chung Yang
Принадлежит: XinTec Inc

A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

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Номер записи: 31
09-08-2012 дата публикации

Integrated Transistor and Anti-Fuse Programming Element for a High-Voltage Integrated Circuit

Номер: US20120199885A1
Автор: Martin H. Manley, Sujit Banerjee
Принадлежит: Power Integrations Inc

A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

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Номер записи: 32
09-08-2012 дата публикации

High Density Metal-Insulator-Metal Trench Capacitor

Номер: US20120199949A1
Автор: Clarence Chui, Evgeni P. Gousev, Je-Hsiung Lan, Jonghae Kim, Matthew Michael Nowak
Принадлежит: Qualcomm Inc

Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

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Номер записи: 33
23-08-2012 дата публикации

Microwave unit and method therefore

Номер: US20120211487A1
Автор: Bengt Madeberg, Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

A microwave unit comprising a motherboard and a package adapted to be assembled automatically in, e.g., a Surface Mounted Device, SMD, machine is disclosed. The microwave unit preferably comprises a connecting component interconnecting the motherboard and the package, and operable to make the signal ways on a same level at both the motherboard and at the package. Furthermore, the microwave unit preferably comprises a micro-strip adapted soldering tag for soldering on two sides.

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Номер записи: 34
30-08-2012 дата публикации

Multi-stack semiconductor integrated circuit device

Номер: US20120217658A1
Автор: Tadahiro Kuroda
Принадлежит: KEIO UNIVERSITY

The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception.

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Номер записи: 35
30-08-2012 дата публикации

Semiconductor apparatus, method for manufacturing the same and electric device

Номер: US20120217660A1
Автор: Keishiro Okamoto, Motoaki Tani
Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

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Номер записи: 36
30-08-2012 дата публикации

Vertical ballast technology for power hbt device

Номер: US20120218047A1
Автор: Julio Costa, Michael Carroll
Принадлежит: RF Micro Devices Inc

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

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Номер записи: 37
30-08-2012 дата публикации

Power module

Номер: US20120218717A1
Автор: Keiko Takahashi, Kenya Yamashita, Masanori Minamio
Принадлежит: Panasonic Corp

A reliable power module is realized, in which a good performance of radiating heat of the power semiconductor element is secured and it is hard for the heat of a power semiconductor element to be conducted to a driving element. A power module includes a power semiconductor element mounted on a lead frame, and a driving element mounted on the lead frame, and a heat radiating plate radiating heat which is generated by the power semiconductor element, and a resin holding the power semiconductor element, the driving element, and the heat radiating plate, wherein the heat radiating plate has a portion disposed at a side opposite to a surface of the lead frame where the power semiconductor element is mounted, a portion disposed between the power semiconductor element and the driving element, and a portion disposed below the power semiconductor element, as the portions being in a body.

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Номер записи: 38
20-09-2012 дата публикации

Esd network circuit with a through wafer via structure and a method of manufacture

Номер: US20120238069A1
Автор: Steven H. Voldman
Принадлежит: International Business Machines Corp

A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

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Номер записи: 39
27-09-2012 дата публикации

Magnetic integration double-ended converter

Номер: US20120241959A1
Автор: Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

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Номер записи: 40
04-10-2012 дата публикации

Integrated circuit package including miniature antenna

Номер: US20120249380A1
Автор: Carles Puente Baliarda, Carmen Borja Borau, Jaume Anguera Pros, Jordi Soler Castany
Принадлежит: Fractus SA

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

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Номер записи: 41
11-10-2012 дата публикации

On-Chip RF Shields with Backside Redistribution Lines

Номер: US20120258594A1
Автор: Gottfried Beer, Hans-Joachim Barth, Heinrich Koerner, Jens Pohl
Принадлежит: Individual

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

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Номер записи: 42
25-10-2012 дата публикации

Impedance matching arrangement for amplifier having split shunt capacitor and amplifier including the same

Номер: US20120268210A1
Автор: Kohei Fujii
Принадлежит: Avago Technologies Wireless IP Singapore Pte Ltd

An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

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Номер записи: 43
08-11-2012 дата публикации

Processing Signals by Couplers Embedded in an Integrated Circuit Package

Номер: US20120280763A1
Автор: Ahmadreza Rofougaran
Принадлежит: Broadcom Corp

Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

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Номер записи: 44
15-11-2012 дата публикации

Apparatus and methods for electronic amplification

Номер: US20120286878A1
Автор: Alan W. Ake, David Dening
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

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Номер записи: 45
15-11-2012 дата публикации

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

Номер: US20120289001A1
Автор: Anup Bhalla, Francois Hebert, Kai Liu, Ming Sun
Принадлежит: Alpha and Omega Semiconductor Ltd

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

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Номер записи: 46
29-11-2012 дата публикации

Power Semiconductor Module with Embedded Chip Package

Номер: US20120299150A1
Автор: Benjamin Tang, Frank Daeche, Kenneth Ostrom, Laura Carpenter
Принадлежит: INFINEON TECHNOLOGIES AG, Primarion Inc

A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

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Номер записи: 47
29-11-2012 дата публикации

Semiconductor device

Номер: US20120299178A1
Автор: Ko Kanaya, Yoshihiro Tsukahara
Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.

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Номер записи: 48
27-12-2012 дата публикации

Package structure of transient voltage suppressor

Номер: US20120327607A1
Автор: Ho-Shyan Lin, Tsu-Yang Wong
Принадлежит: Amazing Microelectronic Corp

A package structure of transient voltage suppressor is disclosed. The package structure comprises a package housing with a bottom thereof having a first contact pin, a second contact pin, and a third contact pin, wherein the third contact pin is positioned between the first contact pin and the second contact pin. A first diode is positioned in the package housing, and an anode and a cathode of the first diode are respectively connected with the third contact pin and the first contact pin. A second diode is installed in the package housing, and an anode and a cathode of the second diode are respectively connected with the third contact pin and the second contact pin.

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Номер записи: 49
27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1
Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding
Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 50
17-01-2013 дата публикации

System and Method for Wafer Level Packaging

Номер: US20130015467A1
Автор: Alfons Dehe, Gerhard Lohninger, Ulrich Krumbein
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

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Номер записи: 51
24-01-2013 дата публикации

System and Method for Packaging of High-Voltage Semiconductor Devices

Номер: US20130020672A1
Автор: Charles W. Tipton, Oladimeji O. Ibitayo
Принадлежит: US Department of Army

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

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Номер записи: 52
07-02-2013 дата публикации

Chip package structure

Номер: US20130032940A1
Автор: Hung-Che Shen
Принадлежит: CHIPMOS TECHNOLOGIES INC

A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively.

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Номер записи: 53
14-02-2013 дата публикации

Semiconductor Structure with Galvanic Isolation

Номер: US20130037909A1
Автор: Ann Gabrys, Peter J. Hopper, William French
Принадлежит: National Semiconductor Corp

Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.

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Номер записи: 54
21-02-2013 дата публикации

Semiconductor device and communication method

Номер: US20130043558A1
Автор: Kenta Ogawa, Yasutaka Nakashiba
Принадлежит: Renesas Electronics Corp

A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.

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Номер записи: 55
07-03-2013 дата публикации

Semiconductor device

Номер: US20130056730A1
Автор: Satoshi Goto, Satoshi Sakurai, Toru Fujioka
Принадлежит: Individual

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

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Номер записи: 56
21-03-2013 дата публикации

Semiconductor device and solid state relay using same

Номер: US20130069082A1
Автор: Hiroshi Okada, Takeshi Oomori, Takuya Sunada
Принадлежит: Panasonic Corp

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

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Номер записи: 57
28-03-2013 дата публикации

Power semiconductor module with wireless saw temperature sensor

Номер: US20130077222A1
Автор: Michael Sleven
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing, a base plate disposed in the housing, a plurality of substrates mounted to the base plate, a plurality of power transistor die mounted to the substrates and a plurality of terminals mounted to the substrates and protruding through the housing. The terminals are in electrical connection with the power transistor die. The power semiconductor module further includes a wireless surface acoustic wave (SAW) temperature sensor disposed in the housing of the power semiconductor module.

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Номер записи: 58
28-03-2013 дата публикации

Stacked semiconductor apparatus, system and method of fabrication

Номер: US20130077374A1
Автор: Kang-Wook Lee, Ki-tae Park, Young-don Choi, Yun-sang Lee
Принадлежит: Individual

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

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Номер записи: 59
04-04-2013 дата публикации

Semiconductor package including an integrated waveguide

Номер: US20130082379A1
Автор: Ahmadreza Rofougaran, Arya Reza Behzad, Jesus Alfonso Castaneda, Michael BOERS, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

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Номер записи: 60
04-04-2013 дата публикации

Electrostatic discharge protection

Номер: US20130083436A1
Автор: Jen-Chou Tseng, Ming-Hsiang Song, Tzu-Heng Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.

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Номер записи: 61
11-04-2013 дата публикации

Die package, method of manufacturing the same, and systems including the same

Номер: US20130088838A1
Автор: Baek Kyu Choi, Jae Jun Lee, Jeong Hyeon Cho, Jung Joon Lee, Sun Won Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die.

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Номер записи: 62
18-04-2013 дата публикации

Packaging structure and method of fabricating the same

Номер: US20130093629A1
Автор: Chao-Ya Yang, Chih-Hsien Chiu, Tsung-Hsien Tsai
Принадлежит: Siliconware Precision Industries Co Ltd

A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect.

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Номер записи: 63
18-04-2013 дата публикации

INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION

Номер: US20130094113A1
Автор: CHEN SHIH-HUNG, Ker Ming-Dou, LIN Kun-Hsien
Принадлежит: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor. 127-. (canceled)28. A method of providing electrostatic discharge (ESD) protection , comprising:providing a silicon controlled rectifier (SCR) including a semiconductor substrate and a well formed in the substrate;providing a p-type metal-oxide-semiconductor (PMOS) transistor formed in the well of the SCR including a gate, a first diffused region and a second diffused region spaced apart from the first diffused region;providing an n-type region formed in the well being electrically connected to the first diffused region of the PMOS transistor;providing a p-type region formed in the substrate being electrically connected to the second diffused region of the PMOS transistor; andkeeping the PMOS transistor at an on state before an ESD event occurs.29. The method of claim 28 , further comprising triggering a first current in the well in response to an ESD event.30. The method of claim 29 , further comprising triggering a second current in the substrate in response to the first current.31. The method of claim 28 , further comprising keeping the gate of the PMOS transistor at a reference voltage level before an ESD event occurs.32. A method of providing ...

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Номер записи: 64
18-04-2013 дата публикации

Power converters with integrated capacitors

Номер: US20130094157A1
Автор: David Giuliano
Принадлежит: Arctic Sand Technologies Inc

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

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Номер записи: 65
18-04-2013 дата публикации

Visual indicator for semiconductor chips for indicating mechanical or esd damage

Номер: US20130094531A1
Автор: Douglas Collins, Elaine Taylor, Richard Carson
Принадлежит: Individual

A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.

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Номер записи: 66
25-04-2013 дата публикации

Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus

Номер: US20130099340A1
Автор: Yasutaka Nakashiba
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a substrate, a bonding pad provided above the substrate, a first signal transmitting/receiving portion provided above the substrate and below the bonding pad, and a transistor provided over the substrate. The transistor is connected to the first signal transmitting/receiving portion.

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Номер записи: 67
25-04-2013 дата публикации

ESD PROTECTION DEVICE

Номер: US20130099353A1
Автор: ISHINO Satoshi, KATO Noboru, Sasaki Jun, YAMADA Kosuke
Принадлежит: MURATA MANUFACTURING CO., LTD.

An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer provided on a surface of the semiconductor substrate. An ESD protection circuit is provided on or in an outer layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post electrodes. First ends of the interlayer wiring lines disposed in the thickness direction are connected to the input/output electrodes disposed on the surface of the semiconductor substrate, and second ends of the interlayer wiring lines are connected to first ends of the in-plane wiring lines routed in plan view. Prismatic post electrodes are provided between second ends of the in-plane wiring lines and terminal electrodes. 1. An ESD protection device comprising:a semiconductor substrate that includes an ESD protection circuit connected to a line propagating a high frequency signal and input/output electrodes electrically connected to the ESD protection circuit; anda rewiring layer including pillar-shaped post electrodes electrically connected to the input/output electrodes and terminal electrodes; whereinwhen a distance in a radial direction from a center axis of each of the post electrodes to a side surface of the respective post electrode is represented by R and an azimuth in the radial direction is represented by θ,θ has a range over which dR/dθ at a same height of the post electrodes is not 0; andan inductance value of the post electrodes in a surge frequency is less than an inductance value of the post electrodes in a high frequency higher than the surge frequency.2. The ESD protection device according to claim 1 , wherein at least one θ for which dR/dθ at the same height changes discontinuously with respect to θ is obtained.3. The ESD protection device according to claim 1 , wherein each of the post electrodes has a polygonal cross-section ...

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Номер записи: 68
25-04-2013 дата публикации

Semiconductor device and fabrication method therefore

Номер: US20130100318A1
Автор: Junji Tanaka, Kouichi Meguro, Masanori Onodera
Принадлежит: SPANSION LLC

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

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Номер записи: 69
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130119472A1
Автор: Nakanishi Shoji, Risaki Tomomitsu, Shimazaki Koichi
Принадлежит: SEIKO INSTRUMENTS INC.

Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. 1. A semiconductor device , comprising:a semiconductor substrate;a first layer of a first conductivity type formed at a surface of the semiconductor substrate and having an impurity concentration higher than an impurity concentration of the semiconductor substrate;a second layer of a second conductivity type formed at the surface of the semiconductor substrate to be in contact with the first layer and having an impurity concentration higher than the impurity concentration of the semiconductor substrate;a base layer of a first conductivity type formed at the surface of the semiconductor substrate in the first layer and having an impurity concentration higher than the impurity concentration of the first layer;a collector layer of a second conductivity type formed at the surface of the semiconductor substrate in the second layer and having an impurity concentration higher than the impurity concentration of the second layer;an emitter layer of the second conductivity type located between the base layer and the collector layer, formed at the surface of the semiconductor substrate in the first layer, and having an impurity concentration higher than the impurity concentration of the first layer; andan electric field relaxation layer of a second conductivity type formed between the collector layer and the first layer to be in ...

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Номер записи: 70
30-05-2013 дата публикации

Interposer and semiconductor package with noise suppression features

Номер: US20130134553A1
Автор: Chewn-Pu Jou, Feng Wei KUO, Huan-Neng CHEN, Hui Yu Lee, Yen-Jen Chen, Yu-Ling Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

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Номер записи: 71
30-05-2013 дата публикации

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

Номер: US20130134579A1
Автор: Gregory E. Howard, Marie-Solange Anne Milleron, Matthew D. Romig, Souvik Mukherjee
Принадлежит: Texas Instruments Inc

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

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Номер записи: 72
06-06-2013 дата публикации

Wireless ic device

Номер: US20130140369A1
Автор: Masahiro Ozawa, Yuya DOKAI
Принадлежит: Murata Manufacturing Co Ltd

A wireless IC device that improves radiation gain without increasing substrate size and easily adjusts impedance, includes a multilayer substrate including laminated base layers. On a side of an upper or first main surface of the multilayer substrate, a wireless IC element is arranged to process a high-frequency signal. On a side of a lower or second main surface of the multilayer substrate, a first radiator is provided and is coupled to the wireless IC element via a feeding circuit including first interlayer conductors. On the side of the first main surface, a second radiator is provided and is coupled to the first radiator via second interlayer conductors.

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Номер записи: 73
13-06-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130147011A1
Автор: Hashimoto Takasuke, OKUSHIMA Mototsugu
Принадлежит:

A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section. 1. A semiconductor device comprising:a signal pad;a power supply line;a ground line;an inductor section whose one end is connected to said signal pad;a terminating resistor connected between the other end of said inductor section and said power supply line or said ground line;a first ESD protection element connected to a first node in said inductor section; anda second ESD protection element connected to a second node whose position is different from that of said first node in said inductor section, a first inductor connected between said signal pad and said first node; and', 'a second inductor connected between said terminating resistor and said second node,, 'wherein said inductor section compriseswherein said first node and said second node are connected in series between said first inductor and said second inductor,wherein said first ESD protection element is connected between said ground line and said first node,said second ESD protection element is connected between said power supply line and said second node,an interconnection connecting said first ESD protection element to said ground line is shared by adjacent first ESD protection elements, andan interconnection connecting said second ESD protection element to said power supply line is shared by adjacent second ESD protection elements.2. The semiconductor device according to claim 1 ,wherein an internal circuit is electrically connected to at least one of said first node and said ...

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Номер записи: 74
13-06-2013 дата публикации

Semiconductor Package Having Internal Shunt and Solder Stop Dimples

Номер: US20130147016A1
Автор: Hauenstein Henning M.
Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. 157-. (canceled)5868-. (canceled)69. A semiconductor package comprising:first and second conductive layers on top and bottom surfaces of an insulation layer;a semiconductor die mounted on said first conductive layer and having an electrode electrically connected to said first conductive layer;a current sense resistor situated in said insulation layer, said current sense resistor electrically connected to said first and second conductive layers and to said electrode of said semiconductor die.70. The semiconductor package of comprising at least one via in said insulation layer claim 69 , wherein said current sense resistor comprises resistive material situated in said at least one via.71. The semiconductor package of claim 69 , wherein said current sense resistor extends completely through said insulation layer.72. The semiconductor package of claim 69 , wherein said electrode comprises a drain electrode of said semiconductor die.73. The semiconductor package of claim 69 , wherein said current sense resistor electrically connects said second conductive layer to said electrode through said first conductive layer.74. The semiconductor package of claim 69 , wherein said current sense resistor comprises a plurality of parallel shunts distributed in said insulation layer.75. The semiconductor package of claim 69 , wherein said first conductive layer comprises a depression and said semiconductor die is ...

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Номер записи: 75
20-06-2013 дата публикации

ISOLATED EPITAXIAL MODULATION DEVICE

Номер: US20130154008A1
Автор: Li Yu, Voldman Steven Howard
Принадлежит: INTERSIL AMERICAS INC.

An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage. 1. An isolated epitaxial modulation device comprising:a substrate;a barrier structure formed on the substrate;an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure;a semiconductor device, the semiconductor device located in the isolated epitaxial region;a modulation network formed on the substrate and electrically coupled to the semiconductor device;a bond pad; anda ground pad;wherein the isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad; andwherein the semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.2. The isolated epitaxial modulation device of claim 1 , wherein the semiconductor device comprises one of a metal oxide semiconductor field-effect transistor (MOSFET) claim 1 , a bipolar junction transistor (BJT) claim 1 , and a laterally diffused metal oxide semiconductor (LDMOS) device.3. The isolated epitaxial modulation device of claim 1 , wherein the modulation network comprises a resistor-capacitor (RC) discriminator and a transistor.4. The isolated epitaxial modulation device of wherein the semiconductor device comprises:a plurality of parallel transistors configured to shunt electrostatic discharge (ESD) ...

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Номер записи: 76
20-06-2013 дата публикации

Integrated circuit and method of providing electrostatic discharge protection within such an integrated circuit

Номер: US20130155555A1
Автор: Fabrice Blanc, Flora POTTIER, Matthieu PAULY
Принадлежит: ARM LTD

An integrated circuit with electrostatic discharge (ESD) protection, and a method of providing such ESD protection within the integrated circuit, are disclosed. The integrated circuit comprises functional circuitry having functional components for performing processing functions required by the integrated circuit, and interface circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. The integrated circuit is formed of a plurality of layers, including component level layers within which any of the functional components formed from a standard cell are constructed, power grid layers providing a power distribution infrastructure for the functional components, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further comprises at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.

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Номер записи: 77
20-06-2013 дата публикации

Integrated circuit comprising an integrated transformer of the "balun" type with several input and output channels

Номер: US20130157587A1
Автор: Christophe Arricastres, Denis Pache, Floria Blanchet
Принадлежит: STMICROELECTRONICS SA

An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

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Номер записи: 78
04-07-2013 дата публикации

Packages with Passive Devices and Methods of Forming the Same

Номер: US20130168805A1
Автор: Chen-Hua Yu, Chiung-Han Yeh, Der-Chyang Yeh, Shang-Yun Hou, Shuo-Mao Chen, Yi-Jou Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

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Номер записи: 79
04-07-2013 дата публикации

ESD PROTECTION DEVICE

Номер: US20130168837A1
Автор: KATO Noboru, Sasaki Jun, YAMADA Kosuke
Принадлежит: MURATA MANUFACTURING CO., LTD.

An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes. 1. An ESD protection device comprising:a semiconductor substrate including an ESD protection circuit and first and second input/output electrodes electrically connected to the ESD protection circuit; anda rewiring layer including a first post-shaped electrode electrically connected to the first input/output electrode and a first terminal electrode, and a second post-shaped electrode electrically connected to the second input/output electrode and a second terminal electrode; whereina distance between centers of the first and second post-shaped electrodes is larger than a distance between centers of the first and second input/output electrodes.2. The ESD protection device according to claim 1 , wherein a minimum distance between the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes.3. The ESD protection device according to claim 1 , whereinthe rewiring layer includes first and second in-plane wiring lines disposed within an inner layer and first and second interlayer wiring lines ...

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Номер записи: 80
04-07-2013 дата публикации

Integrated Circuit Device

Номер: US20130169355A1
Автор: Hung-Ming Chen, Kuan-Neng Chen, Ming-Fang Lai
Принадлежит: Individual

An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.

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Номер записи: 81
11-07-2013 дата публикации

HIGH FREQUENCY CIRCUIT COMPRISING GRAPHENE AND METHOD OF OPERATING THE SAME

Номер: US20130175676A1
Автор: CHOI Jae-Young, JUN Seong-chan, KIM Whan-kyun, LIM Ju-hwan, OH Ju-yeong, SHIN Hyeon-jin, YOON Hyung-seo
Принадлежит:

A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit. 1. A high frequency circuit comprising:a first electronic device;a second electronic device; anda graphene interconnection unit which connects the first and second electronic devices,wherein at least one of a trench and a via is defined under the graphene interconnection unit.2. The high frequency circuit of claim 1 , further comprising:an insulating layer disposed under the graphene interconnection unit,wherein the at least one of the trench and the via is defined in the insulating layer.3. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal to the second electronic device via the graphene interconnection unit in a high frequency field.4. The high frequency circuit of claim 1 , wherein the trench has a depth in the range of about 1 nanometer to about 10 claim 1 ,000 nanometers.5. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal via the graphene interconnection unit at a frequency of about 0.8 gigahertz or higher.6. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal via the graphene interconnection unit at a frequency in a range of about 2 gigahertz to about 300 terahertz.7. The high frequency circuit of claim 1 , wherein each of the first and second electronic devices comprise a transistor.8. The high frequency circuit of claim 1 , wherein the graphene interconnection unit comprises a plurality of graphene units aligned substantially parallel to each other.9. The high frequency circuit of claim 1 , wherein the graphene interconnection unit conveys a current at a frequency in a range of about 1 megahertz to about 800 mega hertz.10. The high frequency circuit of claim 1 , wherein the graphene ...

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Номер записи: 82
11-07-2013 дата публикации

Reprocessing method of a semiconductor device

Номер: US20130178040A1
Автор: Jin-san Jung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A reprocessing method of a semiconductor device, the reprocessing method includes adjusting a resistance value of a first resistor by first trimming the first resistor, wherein the first resistor is electrically connected between a first pad and a second pad, forming a second resistor on the first trimmed first resistor, and adjusting a resistance value of the second resistor by second trimming the second resistor.

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Номер записи: 83
25-07-2013 дата публикации

Backside integration of rf filters for rf front end modules and design structure

Номер: US20130187246A1
Автор: Anthony K. Stamper, James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Panglijen Candra, Randy L. Wolf, Thomas J. DUNBAR
Принадлежит: International Business Machines Corp

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

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Номер записи: 84
25-07-2013 дата публикации

Semiconductor Chip and Methods for Producing the Same

Номер: US20130187254A1
Автор: MA Wanli
Принадлежит:

A fabrication method for thickening pad metal layers comprises: growing a first metal layer on a silicon substrate; etching the first metal layer to obtain a metal wire comprising a metal fuse and a pad; growing a passivation layer on the metal wire; etching the passivation layer to obtain a first window to expose a pad area; growing a second metal layer on the passivation layer having the first window; etching the second metal layer to obtain a metal layer covering the pad area only and expose the passivation layer outside the pad area; and etching the passivation layer outside the pad area to obtain a second window to expose a metal fuse area. 1. A fabrication method for thickening a pad metal layer , comprising:growing a first metal layer on a silicon substrate;etching the first metal layer to obtain a metal wire comprising a metal fuse and a pad;growing a passivation layer on the metal wire;etching the passivation layer to obtain a first window to expose a pad area;growing a second metal layer on the passivation layer having the first window;etching the second metal layer to obtain a metal layer covering the pad area and expose the passivation layer outside the pad area;and etching the passivation layer outside the pad area to obtain a second window to expose a metal fuse area.2. The method according to claim 1 , wherein parameters in the first etching and in the second etching for the passivation layer are the same.3. The method according to claim 2 , wherein the metal layer of the pad area has a total thickness of at least 1.5 μm.4. The method according to claim 1 , wherein the first and second metal layers are made of the same material.5. The method according to claim 1 , wherein at least one of the first metal layer or the second metal layer is made from an Al—Si—Cu alloy.6. The method according to claim 1 , wherein the second metal layer is etched by a wet etching process claim 1 , and the passivation layer and the first metal layer are etched by a dry ...

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Номер записи: 85
01-08-2013 дата публикации

Devices and methods related to electrostatic discharge-protected cmos switches

Номер: US20130194158A1
Автор: Ying-Kuang Chen
Принадлежит: Skyworks Solutions Inc

Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

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Номер записи: 86
01-08-2013 дата публикации

Transmission line transition having vertical structure and single chip package using land grip array coupling

Номер: US20130194754A1
Автор: Dong-Hyun Lee, Dong-Yun Jung, Jei-Young Lee, Ji-Hoon Kim, Jung-han Choi, Sung-Tae Choi, Young-Hwan Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

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Номер записи: 87
08-08-2013 дата публикации

Adjustable Meander Line Resistor

Номер: US20130200447A1
Автор: Hsiao-Tsung Yen, Yu-Ling Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor.

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Номер записи: 88
08-08-2013 дата публикации

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Номер: US20130200493A1
Автор: Sorgellos Bart, Van Camp Benjamin, Van Wijmeersch Sven, Vanhouteghem Wim
Принадлежит: Sofics BVBA

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP. 1. An electrostatic discharge (ESD) protection device coupled between a first node and a second node , the ESD protection device comprising:a first lowly doped region of a P dopant type;a second lowly doped region of a N dopant type formed within the first lowly doped region;a first highly doped region of the N dopant type formed within the first lowly doped region and coupled to the first node; anda second highly doped region of the P dopant type formed P dopant type within the second lowly doped region and coupled to the second node;wherein the ESD protection device is configured to sink current from the first node to the second node in response to an ESD event.2. The ESD protection device of claim 1 , further comprising:a third lowly doped region of the N dopant type formed within the first lowly doped region;wherein the first highly doped region is formed within the third lowly doped region.3. The ESD protection device of claim 1 , further comprising:a third lowly doped region of a P dopant type formed within the first lowly doped region;wherein the first highly doped region is formed within the third lowly doped region.4. The ESD protection device of claim 1 , further comprising:a biasing element coupled between the first highly doped region and the first lowly doped region, wherein the biasing element is configured to control a voltage across a reverse biased junction formed by the first ...

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Номер записи: 89
08-08-2013 дата публикации

Semiconductor package

Номер: US20130200509A1
Автор: Yong-Hoon Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

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Номер записи: 90
29-08-2013 дата публикации

Semiconductor Package with Integrated Electromagnetic Shielding

Номер: US20130221499A1
Автор: Kevin Kunzhong Hu, Pieter Vorenkamp, Rezaur Rahman Khan, Sam Ziqun Zhao, Sampath K.V. Karikalan, Xiangdong Chen
Принадлежит: Broadcom Corp

There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

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Номер записи: 91
29-08-2013 дата публикации

DEVICES AND METHODS RELATED TO INTERCONNECT CONDUCTORS TO REDUCE DE-LAMINATION

Номер: US20130221501A1
Автор: DICARLO Paul T., Hill Michael David, Smith Kim Rene
Принадлежит: SKYWORKS SOLUTIONS, INC.

Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground. 1. A device , comprising:a die having a semiconductor substrate with an intrinsic region;a metal layer in ohmic contact with the intrinsic region;a passivation layer formed over the metal layer and the intrinsic region, the passivation layer defining an opening dimensioned to expose at least a portion of the metal layer; andan interconnect conductor disposed over the metal layer and electrically connected to the metal layer through the opening, the interconnect conductor including an extension that extends over an edge of the opening of the passivation layer to inhibit or reduce the likelihood of the passivation layer de-laminating from the edge.2. The device of wherein the passivation layer includes a dielectric layer.3. The device of wherein the interconnect conductor is connected to a ground.4. The device of further comprising a radio-frequency (RF) circuit implemented on the die.5. The device of further comprising a contact pad connected to the RF circuit and in ohmic contact with the intrinsic region claim 4 , the contact pad and the metal layer configured so that a potential difference greater than a ...

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Номер записи: 92
29-08-2013 дата публикации

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

Номер: US20130222401A1
Автор: Keiju YAMADA, Koh Hashimoto, Koji Akita, Takayoshi Ito, Yukako Tsutsumi
Принадлежит: Toshiba Corp

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

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Номер записи: 93
05-09-2013 дата публикации

SEMICONDUCTOR DEVICE PROTECTED FROM ELECTROSTATIC DISCHARGE

Номер: US20130228867A1
Автор: Ito Mikihiko, Koyanagi Masaru, Suematsu Yasuhiro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor device includes a first semiconductor chip, at least one second semiconductor chip, a first connector, and a second connector. The first semiconductor chip includes a first input pad, first protection circuit, and first internal circuit. The at least one second semiconductor chip includes a second input pad, second protection circuit, and second internal circuit. The first connector electrically connects the first and second input pads. The second connector connects the first protection circuit and first input pad of the first semiconductor chip. The second protection circuit of the at least one second semiconductor chip is not connected to the second input pad. 1. A semiconductor device comprising:a first semiconductor chip including a first input pad, a first protection circuit, and a first internal circuit, the first input pad being connected to the first internal circuit and receiving an external signal, and the first protection circuit protecting the first internal circuit;at least one second semiconductor chip including a second input pad, a second protection circuit, and a second internal circuit, the second input pad being connected to the second internal circuit and receiving the external signal, and the second protection circuit protecting the second internal circuit;a first connector configured to electrically connect the first input pad and the second input pad; anda second connector configured to connect the first protection circuit and first input pad of the first semiconductor chip,wherein the second protection circuit of the at least one second semiconductor chip is not connected to the second input pad.2. The device according to claim 1 , further comprising:a body, the first and second semiconductor chips being stacked on the body; anda third input pad arranged on the body,wherein the first input pad is connected to the third input pad by a third connector.3. The device according to claim 1 , wherein the ...

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Номер записи: 94
05-09-2013 дата публикации

Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips

Номер: US20130228904A1
Автор: Jens Pohl, Klaus Pressel, Markus Brunnbauer, Ralf Plieninger, Recai Sezi, Stephan Brandl, Thorsten Meyer
Принадлежит: Intel Mobile Communications GmbH

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

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Номер записи: 95
19-09-2013 дата публикации

LIGHT-EMITTING ELEMENT UNIT AND LIGHT-EMITTING ELEMENT PACKAGE

Номер: US20130240922A1
Автор: Yamamoto Hiroki
Принадлежит: ROHM CO., LTD.

A light-emitting element according to the present invention includes a semiconductor light-emitting element having a front surface and a rear surface so that light is extracted from the rear surface, and having a first n-side electrode and a first p-side electrode on the front surface, and a support element having a conductive substrate having a front surface and a rear surface as well as a second n-side electrode and a second p-side electrode formed on the front surface of the conductive substrate, the first n-side electrode and the second n-side electrode, and the first p-side electrode and the second p-side electrode are so bonded to one another respectively that the semiconductor light-emitting element is supported by the support element in a facedown posture downwardly directing the front surface, and the support element has an n-side external electrode and a p-side external electrode formed on the rear surface of the conductive substrate, a conductive via passing through the conductive substrate from the front surface up to the rear surface for electrically connecting the second n-side electrode and the n-side external electrode and/or the second p-side electrode and the p-side external electrode with each other, and an insulating film formed between the via and the conductive substrate to cover the side surface of the via. 1. A light-emitting element unit comprising:a semiconductor light-emitting element having a front surface and a rear surface so that light is extracted from the rear surface, and having a first n-side electrode and a first p-side electrode on the front surface; anda support element having a conductive substrate having a front surface and a rear surface as well as a second n-side electrode and a second p-side electrode formed on the front surface of the conductive substrate, whereinthe first n-side electrode and the second n-side electrode, and the first p-side electrode and the second p-side electrode are so bonded to one another ...

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Номер записи: 96
19-09-2013 дата публикации

Esd protection element and esd protection device for use in an electrical circuit

Номер: US20130240992A1
Автор: Christian Russ, Harald Gossner
Принадлежит: INFINEON TECHNOLOGIES AG

An ESD protection element may include: a fin structure including a first connection region having a first conductivity type, a second connection region having a second conductivity type, first and second body regions formed between the connection regions, the first body region having the second conductivity type and formed adjacent to the first connection region, the second body region having the first conductivity type and formed adjacent to the second connection region, the body regions having a lower dopant concentration than the connection regions, a diffusion region formed between the body regions and having substantially the same dopant concentration as at least one of the first and second connection regions; a gate region on or above the first body region or the second body region; a gate control device electrically coupled to the gate region and configured to control at least one electrical potential applied to the gate region.

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Номер записи: 97
26-09-2013 дата публикации

Package with printed filters

Номер: US20130249656A1
Автор: Pavel VILNER
Принадлежит: Marvell Israel MISL Ltd

Aspects of the disclosure provide a circuit package. The circuit package includes a first signal terminal electrically coupled with a serializer/deserializer (SERDES), a second signal terminal electrically coupled with an external electronic component, and a trace disposed on an insulating layer. The trace is configured to transfer an electrical signal between the first signal terminal and the second signal terminal. The trace is patterned to provide a specific filtering characteristic to filter the electrical signal.

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Номер записи: 98
26-09-2013 дата публикации

Electronic device

Номер: US20130250536A1
Автор: Hirotaka Satake
Принадлежит: Hitachi Metals Ltd

An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

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Номер записи: 99
03-10-2013 дата публикации

Semiconductor devices including electromagnetic interference shield

Номер: US20130256847A1
Автор: Jong-ho Lee, Su-min Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

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Номер записи: 100