СПОСОБ ИЗГОТОВЛЕНИЯ ЛАМИНИРОВАННЫХ ЧИП-КАРТ

Изобретение относится к способу изготовления ламинированных чип-карт из бумаги или пленки. Технический результат заключается в создании способа изготовления, с помощью которого возможно изготовление чип-карт в большом объеме. Чип-карта выполнена по меньшей мере из двух слоев бумаги или пленки в качестве несущего материала, причем на одном слое размещен полупроводниковый кристалл, а второй слой имеет соединительные контакты и печатный проводник или внешние контактные площадки. Контакты полупроводникового кристалла электропроводным способом соединены с соединительными контактами второго слоя. При этом не требуется модуль микросхемы для изготовления чип-карт. Несущий материал, снабженный интегральными схемами и контактами, может ламинироваться с использованием формата бесконечного рулона, как при изготовлении бумаги. 3 з.п. ф-лы, 2 ил.

МОДУЛЬ ДЛЯ БЕСКОНТАКТНЫХ ЧИП-КАРТ ИЛИ СИСТЕМ ИНДЕНТИФИКАЦИИ

... 1. Модуль для бесконтактных чип-карт или систем идентификации, содержащий первую и вторую антенные контактные полоски (1, 2), которые соответственно имеют первую и отвернутую от нее вторую поверхность, полупроводниковую микросхему (3) с по меньшей мере двумя контактными средствами (7), причем по меньшей мере одно контактное средство (7) контактирует с первой поверхностью первой антенной контактной полоски (1), а по меньшей мере одно другое контактное средство контактирует с первой поверхностью второй антенной контактной полоски (2), по меньшей мере одну полоску (4, 5) клеящей пленки, которая по меньшей мере частично покрывает первую поверхность как первой, так и второй антенной контактной полоски (2), отличающийся тем, что по меньшей мере одна полоска (4, 5) клеящей пленки нанесена вне зоны, накрытой полупроводниковой микросхемой (3). 2. Модуль по п.1, отличающийся тем, что первая антенная контактная полоска и вторая антенная контактная полоска (2) имеют соответственно зону подсоединения ...

КОНТАКТИРОВАНИЕ ПОЛУПРОВОДНИКОВЫХ МИКРОСХЕМ В ЧИП-КАРТАХ

... 1. Чип-карта, которая имеет корпус (1) чип-карты, полупроводниковую микросхему (3), и закрепленную в корпусе (1) чип-карты подложку (2), с которой полупроводниковая микросхема (3) связана электрически и механически, при этом корпус (1) чип-карты имеет первую полость (10) и вторую полость (20), причем вторая полость (20) выполнена в основании первой полости (10), так что первая полость (10) простирается в боковые стороны над второй полостью (20), и плоскость (15) основания первой полости (10) охватывает вторую полость (20), при этом подложка (2) размещена в первой полости (10) и на своей верхней стороне (11) имеет верхние плоские контакты (4) для считывания чип-карты, а на своей нижней стороне (12) имеет нижние плоские контакты (5), которые посредством проходящих через подложку (2) проводников (6) контактных отверстий электрически связаны друг с другом, при этом полупроводниковая микросхема (3) посредством электрических соединений (9) связана с нижними плоскими контактами (5) подложки (2 ...

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО, ПРИСОЕДИНЕННОЕ К ОПОРНОЙ ПОДЛОЖКЕ

... 1. Структура, содержащая:опорную подложку, содержащую тело и множество сквозных отверстий, проходящих через всю толщину тела; иполупроводниковое светоизлучающее устройство, содержащее светоизлучающий слой, размещенный между областью n-типа и областью p-типа, причем полупроводниковое светоизлучающее устройство присоединено к опорной подложке посредством диэлектрического соединяющего слоя;при этом опорная подложка является не более широкой, чем полупроводниковое светоизлучающее устройство.2. Структура по п. 1, в которой область n-типа расположена с отступом от края полупроводникового светоизлучающего устройства.3. Структура по п. 2, которая дополнительно содержащая полимерный слой, размещенный между краем области n-типа и краем полупроводникового светоизлучающего устройства.4. Структура по п. 1 дополнительно содержащая металлический контакт, размещенный на области n-типа.5. Структура по п. 4, в которой металлический контакт проходит по боковой стенке на краю области n-типа.6. Структура по ...

СИЛИКОНОВАЯ КЛЕЯЩАЯ КОМПОЗИЦИЯ ДЛЯ ТОНКОЙ ПОВЕРХНОСТИ СКЛЕИВАНИЯ И СПОСОБ ЕЕ ПОЛУЧЕНИЯ

... 1. Композиция теплового интерфейса (20), содержащая смесь полимерной матрицы и наполнителя, имеющего частицы, характеризующиеся максимальным диаметром частиц, меньшим приблизительно 25 микронов. 2. Композиция теплового интерфейса (20) по п.1, где полимерная матрица содержит отверждаемую полимерную композицию, выбирают из группы, состоящей из полидиметилсилоксановых смол, эпоксидных смол, акрилатных смол, органополисилоксановых смол, полиимидных смол, фторуглеродных смол, бензоциклобутеновых смол и фторированных простых полиаллиловых эфиров, полиамидных смол, полиимидоамидных смол, смол на основе цианатных сложных эфиров, фенолрезольных смол, смол на основе ароматических сложных полиэфиров, смол на основе полифениленового простого эфира (РРЕ), бисмалеимидтриазиновых смол, фторсмол, их комбинаций и любых других полимерных систем, известных специалисту в данной области техники. 3. Композиция теплового интерфейса (20) по п.1, где наполнитель выбирают из группы, состоящей из коллоидального диоксида ...

Hybridisierungsofen für die Verbindung von Bauelementen mittels eines schmelzbares Materials

Verfahren zum Kapseln intergrierter Schaltungen und über das Verfahren hergestellte integrierte Schaltungsbausteine

Verfahren zum Kapseln integrierter Schaltungen, umfassend: Anbringen einer ersten integrierten Schaltung an einer ersten Fläche eines Substrats mit einer elektrischen Verbindung zwischen entsprechenden Kontakten des Substrats und der ersten integrierten Schaltung; Anbringen einer zweiten integrierten Schaltung an einer zweiten Fläche eines Substrats mit einer elektrischen Verbindung zwischen elektrischen Kontakten des Substrats und der zweiten integrierten Schaltung; und einen Ausformschritt, bei dem die erste und zweite integrierte Schaltung in Harz gekapselt werden.

Verbindungsverfahren zwischen einer integrierten Schaltung und einem Schaltungsträger und an dieses Verfahren angepasste, integrierte Schaltung

Chip-size package production

Production of a semiconductor chip-size housing (CSP) involves (a) bonding conductive wires (45) onto bond pads on a chip (41); (b) placing the chip in an electrolysis cell (55) such that the wire ends are outside the electrolyte solution (50) of the cell; (c) fitting an electroplating electrode (60) on an inner wall of the cell; (d) placing a conductive plate (65) as common electrode on the exposed wire ends; and (e) connecting the conductive plate (65) and the outer wall of the cell (55) to a current source (70). Preferably, the wires (45) consist of gold, the conductive plate (65) consists of copper and the electroplating electrode (60) consists of nickel or gold.

Anordnung zum Testen von Chips mittels einer gedruckten Schaltungsplatte

UND VERFAHREN ZU SEINER HERSTELLUNG

COOLING MEANS FOR INTEGRATED CIRCUIT CHIP DEVICE

Semiconductor assembly comprises (a) a substrate(12); (b) a semiconductor chip(10) having one surface bonded to the substrate, (c) a heat transfer element closely adjacent the second surface of the chip; (d) a thin layer(22) of heat conductive noneutectic alloy at the interface between heat transfer element and chip, pref. an alloy contg. Bi; and pref. (e) a spring type piston providing a load force to the heat transfer element, increasing contact between element and chip. The assembly pref. also includes a hat(20) providing a cover for the assembly and diffusing heat. A thin layer(22) of conductive noneutectic alloy is pref. provided at the interface between heat transfer element and hat surface. A diagonal spring type piston(16) pref. provides a load force increasing contact between heat transfer element and hat and chip surfaces. The thermal resistance of the chip interface is pref. 0.1-0.2 deg.C./W and of the heat interface is pref. 0.01-0.02 deg.C./W, both for contact load of 100g.

Leistungshalbleitervorrichtung

Leistungshalbleitervorrichtung, bei der folgende Elemente in Spritzharz eingeschlossen sind: ein Schaltungssubstrat, das eine metallische Wärmeabführeinrichtung beinhaltet und das eine Isolierschicht mit hoher Wärmeleitfähigkeit beinhaltet, die mit der einen Oberfläche der metallischen Wärmeabführeinrichtung verbunden ist und ein Verdrahtungsmuster aufweist, das auf einer Oberfläche der Isolierschicht mit hoher Wärmeleitfähigkeit vorgesehen ist, die zu der mit der metallischen Wärmeabführeinrichtung verbundenen Oberfläche der Isolierschicht mit hoher Wärmeleitfähigkeit entgegengesetzt ist; ein Leistungshalbleiterelement, das mit einem Element-Montagebereich des Verdrahtungsmusters verbunden ist; und eine Seitenfläche eines zylindrischen Verbindungsbereichs für den externen Anschluß, der auf dem Verdrahtungsmuster in elektrischer Verbindung mit dem Leistungshalbleiterelement vorgesehen ist und in den ein externer Anschluß einsetzbar und mit diesem verbindbar ist, wobei: der zylindrische ...

Verfahren zum Erreichen einer selektiven Adhäsionshemmung und -steuerung in Dickschicht-Leitern.

MIKROWELLEN-/MILLIMETERWELLEN-SCHALTUNGSSTRUKTUR MIT EINZELN MONTIERTEN ELEMENTEN VOM FLIPCHIPTYP UND HERSTELLUNGSVERFAHREN DAFÜR

Elektrischer Schaltungsapparat

Mehrschichtige keramische Platine, Verfahren zu ihrer Herstellung und ihre Anwendung.

Verfahren zum Montieren von Halbleiterelementen

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Modul für elektronische Komponente

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

Halbleiterbauteil mit einem vertikalen Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Halbleiterbauteil (1; 25) weist ein vertikales Halbleiterbauelement (2), eine erste Metallisierung (8) und eine zweite Metallisierung (13) auf. Die zweite Metallisierung (13) weist eine einstückige Folie mit einem ersten Ende (14) mit einer ersten Kontaktfläche (17), einem Zwischenbereich (15) und einem zweiten Ende (16) mit einer zweiten Kontaktfläche (19) auf. Die erste Kontaktfläche (17) ist auf der Rückseite (6) des Halbleiterbauelements (2) angeordnet und die zweite Kontaktfläche (19) ist im Wesentlichen in der Ebene der Außenkontaktfläche (12) der ersten Metallisierung (8) angeordnet und sieht eine Außenkontaktfläche (12) vor. Die erste Kontaktfläche (17) und die zweite Kontaktfläche (19) sind auf gegenüberliegenden Oberflächen der Folie der zweiten Metallisierung (13) angeordnet.

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

Leiterplatte mit primären und sekundären Durchgangslöchern

Leiterplatte mit primären und sekundären Durchgangslöchern

Leitpaste zum Verschluss von Vias in keramischen Leiterplatten

Cooling appts. for heat generating semiconductor devices - circulates cooling fluid through nozzles and over surfaces of devices in enclosed space

Heat generating electronic elements, such as LSI devices (2) are mounted on a circuit plate (3) of ceramic and are enclosed by a housing (4). Set into the surface of the housing are a number of nozzles (5) which are used to direct a cooling fluid over the surface of the devices. The fluid is circulated by a pump (14) through one inlet (9) and leaves by a second which connects with a heat exchanger (13). Other nozzles (6) allow cold fluid to mix with the vapour generated from the hot surfaces. ADVANTAGE - Provides effective cooling of LSI devices even when very large amount of heat is produced.

Verfahren und Vorrichtung zur "Flip-Chip" Montage eines elektronischen Bauteils

METHOD AND DEVICE FOR FIXING CHIPS BY ENERGY BEAMS

Modul mit einer Hochfrequenzschaltung

PARALLELEBENENSUBSTRAT

KUEHLUNGSANORDNUNG FUER HALBLEITERCHIPS.

Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier

The arrangement has the semiconductor chip (1) mounted on the chip carrier (2) and enclosed by a resin mass (3) or an insulation layer, before application of a conductive coating (4) to the opposite side of the semiconductor chip to the chip carrier, in the form of a conductive layer applied to the resin mass or insulation layer and connected to a metal layer (7) applied to the chip carrier, e.g. a low-pass filter layer. Also included are Independent claims for the following: (a) a chip card; (b) a chip module ...

Lichtemittierendes Element, Beleuchtungsvorrichtung und deren Vorrichtungsrahmen

Beleuchtungsvorrichtung, umfassend:- eine Tragbasis (5);- ein lichtemittierendes Element (1), das auf der Tragbasis (5) angeordnet ist, wobei das lichtemittierende Element (1) folgendes aufweist:- ein Substrat (2) mit einer Auflagerfläche (210) und einer Seitenfläche, und- mehrere Licht emittierende Dioden-, LED, Chips (14), die auf der Auflagerfläche (210) angeordnet sind und mehrere Außenoberflächen aufweisen;- eine erste Wellenlängenumwandlungsschicht (4), die die mehreren Außenoberflächen bedeckt, ohne die Seitenfläche zu bedecken,wobei das lichtemittierende Element (1) eine erste Hauptoberfläche (21A) aufweist, die durch die mehreren Außenoberflächen gebildet wird und einen Teil der Auflagerfläche (210), der nicht von den mehreren LED Chips (14) bedeckt ist, und eine zweite Hauptoberfläche (21B) aufweist, die der Auflagerfläche (210) gegenüberliegt,wobei wenigstens einer der mehreren LED Chips (14) betrieben wird, um Licht zu emittieren, welches vorgesehen ist, das Substrat (2) zu ...

Gedruckte Leiterplatte und ihre Anordnung

ELECTRONISCHE EINRICHTUNG, INFORMATIONSPROZESSOR UND ANORDNUNG ZUM UNTERDRÜCKEN VON ELEKTROMAGNETISCHEN STÖRUNGEN

Leistungshalbleiterbauelement mit großflächigen Außenkontakten sowie Verfahren zur Herstellung desselben

Überschlagsschutz für eine Anordnung eines Halbleiterbauelements auf einem Substrat

Überschlagsfeste Anordnung eines Halbleiterbauelements (1) mit einer integrierten Schaltung in einem no-lead Gehäuse, insbesondere einem QFN oder LDA Gehäuse (2), auf einem Substrat (3, 7), wobei das Halbleiterbauelement (1) auf seiner zum Substrat (3, 7) gerichteten Gehäuseunterseite zwei oder mehr elektrische Kontaktflächen (4) aufweist, zwischen denen im Betrieb des Halbleiterbauelements (1) eine Hochspannung besteht, die Kontaktflächen (4) des Gehäuses (2) mit korrespondierenden Kontaktflächen (6) des Substrats (3, 7) elektrisch miteinander verbunden sind, das Substrat (3, 7) zumindest bereichsweise mit einem Lötstopplack (14) beschichtet ist und die Verbindung der Kontaktflächen (4) des Gehäuses (2) mit den korrespondierenden Kontaktflächen (6) des Substrats (3, 7) durch eine Lotpaste (11) gebildet ist, und der Lötstopplack (14) zwischen den korrespondierenden Kontaktflächen (6) des Substrats (3, 7) vollständig entfernt ist.

HALBLEITERBAUTEIL

Halbleiterbauteil mit Korrosionsschutzschicht und Verfahren zur Herstellung desselben

Halbleiterbauteil (1; 23), das die folgenden Merkmale aufweist: - ein Schaltungsträger (2) mit mehreren Innenkontaktflächen (5), die ein erstes Material mit einem ersten elektrochemischen Potential aufweisen, - ein Halbleiterchip (3) mit einer aktiven Oberfläche (13) und einer Rückseite (11), wobei die aktive Oberfläche (13) mehrere Chipkontaktflächen (14) aufweist, die ein zweites Material mit einem zweiten elektrochemischen Potential aufweisen, und - Bonddrahtverbindungen (15) zwischen den Chipkontaktflächen (14) und den Innenkontaktflächen (5) des Schaltungsträgers (2), wobei die Bonddrähte (15) ein drittes Material mit einem dritten elektrochemischen Potential aufweisen, wobei die Verbindungsstellen (16) zwischen den Chipkontaktflächen (14) und den Bonddrähten (15) und die Verbindungsstellen (17) zwischen den Innenkontaktflächen (5) und den Bonddrähten (15) mit einer Korrosionsschutzschicht (20; 24) beschichtet sind, wobei Mittelbereiche (21) der Bonddrähte (15) frei von der Korrosionsschutzschicht ...

Fabrication method for semiconductor modules and components for substrates e.g. coils and antennas, involves pressing wafer on to substrate, with welding by ultrasound

A method for fabricating a semiconductor module with a contacted active structure involves preparing a semiconductor wafer, locating at least one thin aluminum-contact elevation into conducting connection with the one of the metallic contacts and aligning the surface of the wafer parallel to and towards the upper face of a substrate having a metallic structure, and pressing the wafer on to the substrate and welding the wafer on to the substrate by ultrasound. An independent claim is given for a semiconductor component/module.

Semiconductor device has copper-tin alloy layer formed on junction portion of solder ball consisting of tin, and wiring consisting of copper

A copper-tin alloy layer (21) of about 1.87 micron thickness, is formed on the junction portion of tin solder ball (11) and copper wiring (2). The rate of content of tin and lead in solder ball is 63% and 37%, respectively. The wiring is connected to the semiconductor chip. The distributed density per lead lump unit cross section of 3 or more in solder ball, is 20\*10<4> pieces/mm. An Independent claim is also included for manufacturing method of semiconductor device.

Laminierter Kondensator und Montageanordnung

Laminierter Kondensator mit folgenden Merkmalen: einem Kondensatorkörper (43) mit einem laminierten Stapel einer Mehrzahl von dielektrischen Schichten (42); zumindest einem Paar einer ersten und einer zweiten inneren Elektrode (44, 45), die sich gegenüberliegen, wobei zumindest eine der dielektrischen Schichten (42) zwischen denselben angeordnet ist, in dem Kondensatorkörper (43); einer Mehrzahl von ersten Durchführungsleitern (46), die zumindest eine der dielektrischen Schichten (42) durchdringen und die innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die ersten Durchführungsleiter (46) von den zweiten inneren Elektroden (45) elektrisch isoliert und mit den ersten inneren Elektroden (44) elektrisch verbunden sind, und einer Mehrzahl von zweiten Durchführungsleitern (47), die den Kondensatorkörper (43) durchdringen und innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die zweiten Durchführungsleiter (47) von den ersten inneren Elektroden (44) elektrisch isoliert ...

Verfahren zum Verbinden eines Chips mit einem Substrat unter Verwendung einer isotropen Verbindungsschicht und Verbundsystem aus Chip und Substrat

The invention relates to a method and a system whereby a chip (1) is coupled to a substrate (4), said chip having at least two bond pads (2) arranged on the same side at a distance from each other, and said substrate having at least two contact bond pads (5) arranged on the same side. An isotropic adhesive is applied to the side of the chips (1) where the bond pads (2) are arranged, or to the side of the substrate (4) where the contact bond pads (5) are arranged. The chip (1) and the substrate (4) are aligned in relation to each other so that the bond pads (2) of the chip (1) and the contact bond pads (5) of the substrates (4) are opposite each other. After the coupling, which occurs by bringing together the chip (1) and the substrate (2), a totally flat isotropic coupling layer (3) of adhesive is formed.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Verfahren zur effektiven Herstellung eines Halbleiterbauelements umfasst separates Herstellen eines ersten Substrats mit einer Transistorschicht und eines zweiten Substrats mit einer Metalldrahtschicht und Stapeln des ersten und zweiten Substrats. Ein Transistor auf dem ersten Substrat wird durch eine Anschlusselektrode elektrisch mit einem Metalldraht auf dem zweiten Substrat verbunden.

Verfahren zum Herstellen eines Halbleiterbauelements

Es wird ein Verfahren zum Herstellen eines Halbleiterbauelements (100) offenbart. Eine Ausführungsform stellt einen Träger (10) bereit. Halbleiterchips (11, 12) werden über dem Träger (10) platziert. Die Halbleiterchips (11, 12) enthalten Kontaktelemente (13). Ein Polymermaterial (15) wird über den Halbleiterchips (11, 12) und dem Träger (10) aufgebracht. Das Polymermaterial (15) wird entfernt, bis die Kontaktelemente (13) exponiert sind. Der Träger (10) wird von den Halbleiterchips (11, 12) entfernt.

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

CARRIER SUBSTRATE AND METHOD FOR PREPARING THE SAME

"CARRIER SUBSTRATE FOR ELECTRICAL CIRCUIT ELEMENT "

PURPOSE:To form a thin film circuit element having required accuracy without necessitating trimming by providing an electrode layer for connection to the circuit element on the topmost layer of insulating films, providing an element layer having the thin film circuit on any of other insulating films, and providing conductor wirings for connecting the electrode layer and external connecting terminals through the element layer. CONSTITUTION:Insulating layers 9a, 9b and 9c are formed on an insulating board. A thin film circuit element such as a thin film resistor is formed thereon. Therefore, irregularities, warping and the like on the surface of the insulating board, e.g. a ceramic substrate 6 are absorbed with the insulating films. The thin film circuit element is formed without the effects of the roughness of the surface of the insulating board. Therefore, the circuit element having the desired constants can be formed accurately. As a result, correction such as trimming is not required.

CPU power delivery system

A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.

Semiconductor device and production method

Semiconductor element cooling apparatus

Electronic device package

THERMAL HEAD DEVICE

FLIP CHIP SOLDER BOND STRUCTURE FOR DEVICES WITH GOLD BASED METALLISATION

An arrangement for solder bonding a flip chip to a semiconductor substrate having thereon layers of metallisation which have a tendency to interact with a solder material, comprises forming on said layers of metallisation a barrier metallisation layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

A carrier for a multilayer semiconductor device comprising a lower stage carrier (3) having a first containing section (12) for containing a first semiconductor device (110) to be the lower side device, and an upper stage carrier (2) having a second containing section (14) for containing a second semiconductor device (120) to be stacked on the first semiconductor device (110) and arranging the second semiconductor device (120) at a specified position on the first semiconductor device (110). By having such a structure, no dedicated stacking device is required, and thus cost can be reduced.

Flip chip package incorporating metallurgical bond to enhance thermal conduction

An integrated circuit device 10 incorporating a metallurgical bond to enhance thermal conduction to a heat sink 28. In a semiconductor device, a surface of an integrated circuit die 14 is metallurgically bonded to a surface of a heat sink 28. In an exemplary method of. manufacturing the device, the upper surface of a package substrate 12 includes an inner region and a peripheral region. The integrated circuit die 14 is positioned over the substrate surface and a active surface 16 of the integrated circuit die 14 is placed in contact with the package substrate 12. A metallic layer 30 is formed on a second opposing surface 18 of the integrated circuit die 14. A preform is positioned on the metallic layer and a heat sink 28 is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink 28 to the second surface 18 of the integrated circuit die 14.

Circuit module for memory expansion

A circuit module comprises a rigid, preferably thermally conductive, substrate 14, a flexible circuit 12 wrapped around an edge of the substrate, a plurality of chip scale packages (CSPs) attached to the flexible circuit and expansion board contacts 20 formed on the flexible circuit adjacent to the edge. The CSPs may be standard memory modules and are connected to the contacts 20 by means of conductive traces in the flexible circuit 16. The contacts 20 are arranged so that the circuit module may be plugged at its edge into a standard circuit board expansion slot in e.g. a computer. The substrate may assist in heat dissipation from the attached CSPs.

Circuit board assembly

TAPE AUTOMATED BONDED MICROCHIPS

Solder connect assembly and method of connecting a semiconductor package and a printed wiring board

Heat sink

ELECTRICAL CONTACT DEVICE

... 1,254,677. Circuit assemblies; fluid-pressure actuated switches. INTERNATIONAL BUSINESS MACHINES CORP. 27 May, 1970 [29 May, 1969], No. 25405/70. Headings H1N and H1R. [Also in Division H2] Recessed contacts 32 of a flexible composite sheet 16 are moved to contact terminal points 28 of an integrated circuit 30, which is to be tested by equipment connected to the ends of electrically conductive strips 26 remote from the contacts 32, by increasing fluid pressure in a pressure chamber 10 of which the sheet 16 forms one wall. The sheet 16 is clamped peripherally between a plastics collar 18 and the rim 14 of the pressure chamber and comprises a dielectric membrane 22 having strips 26 on its outside surface remote from the fluid 12 and a ground plane 24 on its inside surface, the impedance between the ground plane and each strip 26 being designed to match the test equipment to the integrated circuit 30. A further dielectric layer 62 and at least one electrically conductive strip 64 may be provided ...

SEMI-CONDUCTOR ASSEMBLY

Semiconductor device with improved thermal properties

A microwave semiconductor device with improved thermal properties is disclosed wherein multiple active semiconductor bodies are disposed between two electrically and thermally isolated heat sinks. Two separate thermal paths are provided for heat produced within the semiconductor material. The maximum operating power of devices such as double-drift IMPATT diodes is greatly extended.

CONTACTLESS SMART CARD OR CONTACT/CONTACTLESS HYBRID SMART CARD WITH FRAUD PREVENTION

HEATCONDUCTIVE GREASE AND PROCEDURE AND DEVICES, WITH WHICH THE GREASE IS USED

PROCEDURE FOR THE PRODUCTION OF A CONTACTLESS SMART CARD WITH A RADIO TOWER FROM SYNTHETIC MATERIAL

DISTRIBUTED CAPACITY

ADHESIVE, ADHESIVE ARTICLE, CIRCUIT SUBSTRATE FOR SEMICONDUCTOR ASSEMBLY WITH AN ADHESIVE AND A SEMICONDUCTOR ARRANGEMENT THESE CONTAINS

CCU COOLING ARRANGEMENT WITH IMPROVED ACHIEVEMENT

AMIDE-SUBSTITUTED SILIKONE AND PROCEDURE FOR YOUR PRODUCTION AND USE

ELECTRONIC BUILDING GROUP AND PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC BUILDING GROUP

MICROWAVE MINIATURE HOUSING AND PROCEDURE FOR THE PRODUCTION OF THIS HOUSING

EXCHANGEABLE CONNECTING ARRAYS FOR DOUBLE-SIDED DIMM PLACING

COMPOUND CERAMIC SUBSTRATE

TECHNOLOGY FOR MANUFACTURING A UMGOSSENEN AN ELECTRONIC BUILDING GROUP

EMBEDDED SUPPORT DISKS FOR RELIABLE PILE PATHS IN ELECTRONIC SUBSTRATES

PROCEDURE FOR SOLDERING ELECTRONIC ELEMENTS WITH SOLDERING PEAKS ON A SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC LABEL

PROCEDURE FOR THE PRODUCTION OF A LAMINATED PRINTED CIRCUIT BOARD

ELEMENT ARRANGEMENT WITH STARING SUBSTRATE.

CONTACTLESS SMART CARD WITH A RADIO TOWER AND A CHIP CARRIER FROM SYNTHETIC MATERIAL

EMV SCREEN WITH IMPROVED HEAT DISSIPATION

FLEXIBLE THERMAL LINKS AND BUILDING GROUPS

A combined heat sink/electromagnetic shield

COOLING SYSTEM FOR A SEMICONDUCTOR ELEMENT, SEMICONDUCTOR MODULE INCLUDING SUCH A SYSTEM AND A THERMALLY CONDUCTIVE MEMBER THEREFOR

A high temperature memory device

Circuit module system and method

Thin bond-line silicone adhesive composition and method for preparing the same

Circuit structure having a flip-mounted matrix of devices

Method for maintaining solder thickness in flipchip attach packaging processes

Wafer coating and singulation method

METHOD OF FORMING A MULTI-LAYER SEMICONDUCTOR STRUCTURE HAVING A SEAMLESS BONDING INTERFACE

ELECTRONIC CIRCUIT DEVICE AND PORDUCTION METHOD THEREFOR

PACKAGING MICROELECTROMECHANICAL STRUCTURES

Method and apparatus for cooling a semiconductor die

Dispensing process for fabrication of microelectronic packages

Alternate bump metallurgy bars for power and ground routing

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Heat dissipating material and semiconductor device using same

Disclosed is a heat dissipating material which is interposed between a heat-generating electronic component and a heat dissipating body. This heat dissipating material contains (A) 100 parts by weight of a silicone gel cured by an addition reaction having a penetration of not less than 100 (according to ASTM D 1403), and (B) 500-2000 parts by weight of a heat conductive filler. Also disclosed is a semiconductor device comprising a heat-generating electronic component and a heat dissipating body, wherein the heat dissipating material is interposed between the heat-generating electronic component and the heat dissipating body.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Redistribution layers for microfeature workpieces, and associated systems and methods

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Electronic module with vertical connector between conductor patterns

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Method of forming a packaged semiconductor device

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte

Process of electrodepositing a metal in a high aspect ratio via in a silicon substrate to form a through-silicon-via (TSV), utilizing an electrolytic bath including a redox mediator, in an electrolytic metal plating system including a chuck adapted to hold the silicon substrate and to heat the silicon substrate to a first temperature, a temperature control device to maintain temperature of the electrolytic bath at a second temperature, in which the first temperature is maintained in a range from about 30° C. to about 60° C. and the second temperature is maintained at a temperature (a) at least 5° C. lower than the first temperature and (b) in a range from about 15° C. to about 35° C.

Semiconductor device and semiconductor package including the same

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

Semiconductor device

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Film for flip chip type semiconductor back surface, process for producing strip film for semiconductor back surface, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface having a ratio of A/B falling within a range of 1 to 8×10 3 (%/GPa), in which A is an elongation ratio (%) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing and B is a tensile storage modulus (GPa) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing.

Method of manufacturing semiconductor chip

A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.

Method for fabrication of a semiconductor device and structure

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Gain Enhanced LTCC System-on-Package for UMRR Applications

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

High-frequency switch

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Composite Electronic Circuit Assembly

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

Memory systems and memory modules

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Authentication device, authentication method, and an information storage medium storing a program

There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.

Semiconductor structure having conductive vias and method for manufacturing the same

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Semiconductor Device and Semiconductor Process for Making the Same

The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor substrate has a first surface. The conductive via is disposed in the semiconductor substrate. Each conductive via has a conductor and an insulation wall disposed the peripheral of the conductor, and the conductive via is exposed on the first surface of the semiconductor substrate. The insulation ring is disposed the peripheral of the conductive via, and the depth of the insulation ring is smaller than that of the insulation wall. Since the insulation ring is disposed the peripheral of the conductive via, the insulation ring can protect the end of the conductive via from being damaged. Furthermore, the size of the insulation ring and the conductive via is larger than the conventional conductive via, the semiconductor device of the invention can utilize surface finish layer, RDL or UBM to easily connect the other semiconductor device.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Electronic Packaging With A Variable Thickness Mold Cap

An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

Semiconductor package integrated with conformal shield and antenna

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Thermal interface material application for integrated circuit cooling

Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Semiconductor device including coupling conductive pattern

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Package substrate unit and method for manufacturing package substrate unit

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

Measuring apparatus

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Integrated Power Converter Package With Die Stacking

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

Anti-tamper microchip package based on thermal nanofluids or fluids

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

System and method of forming a patterned conformal structure

A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Semiconductor package with through electrodes and method for manufacturing the same

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Corner structure for ic die

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Flexible underfill compositions for enhanced reliability

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

High-frequency switch module

A high-frequency switch module that significantly reduces deterioration of high-frequency characteristics and improves harmonic wave distortion characteristics includes a high-frequency switch and SAW filters mounted on a multilayer substrate. Low pass filters are provided within the multilayer substrate. The terminals of the high-frequency switch are located on the bottom surface of the semiconductor substrate. The high-frequency switch includes a high-frequency circuit ground terminal and a control circuit ground terminal, the multilayer substrate includes therein a ground electrode which is electrically connected to a top surface connection electrode to which the high-frequency circuit ground terminal is connected, and a wiring electrode electrically connected to a top surface connection electrode to which the control circuit ground terminal is connected is arranged so as to be insulated from the ground electrode.

Source Driver, An Image Display Assembly And An Image Display Apparatus

An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Integrated circuit packaging system with a shield and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

Circuit board including embedded decoupling capacitor and semiconductor package thereof

A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Chip Capacitor Precursors

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Chip stacked structure

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Semiconductor package

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Chip package and manufacturing method thereof

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

Memory module with memory stack and interface with enhanced capabilities

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof

Provided is a 3 D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

Wiring Substrate, Imaging Device and Imaging Device Module

A imaging device includes a first insulating substrate having a through hole, a connection electrode and a first wiring conductor, a second insulating substrate having outside terminals and a second wiring conductor, and an imaging element including a light-receiving portion arranged at a center portion on an upper surface thereof and a connection terminal arranged at an outer peripheral portion thereof, at least one of the lower surface of the first insulating substrate and the upper surface of the second insulating substrate including a recess portion, the through hole being located on an inner side thereof, the imaging element being arranged below the first insulating substrate such that the light-receiving portion is located within the through hole, the connection terminal being electrically connected to the connection electrode, the imaging element being accommodated inside the recess portion, outer peripheral portions of the first insulating substrate and the second insulating substrate being electrically connected to each other.

Semiconductor package and manufacturing method thereof

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Integrated circuit package system with encapsulation lock

An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Chip-on-chip structure and manufacturing method therof

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Semiconductor device and systems including the same

The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Display Device and Method of Fabricating the Same

A driver circuit for use with a passive matrix or active matrix electro-optical display device such as a liquid crystal display is fabricated to occupy a reduced area. A circuit (stick crystal) having a length substantially equal to the length of one side of the matrix of the display device is used as the driver circuit. The circuit is bonded to one substrate of the display device, and then the terminals of the circuit are connected with the terminals of the display device. Subsequently, the substrate of the driver circuit is removed. The driver circuit can be formed on a large-area substrate such as a glass substrate, while the display device can be formed on a lightweight material having a high shock resistance such as a plastic substrate.

Semiconductor device

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

Socket for a semiconductor device

A device, wherein, at cells 10 ai of a metallic upper housing 10 corresponding to a signal line, between an end portion of an adapter 24 that has electrically insulating properties the inner surface of an upper housing 12 that has electrically insulating properties, an annular air layer Ai is formed at the peripheries of sleeves 20 S of contact terminals 20 ai that have the same structure as each other, and wherein, at the cells 10 ai that correspond to ground lines, contact points 20 CT 2 of the contact terminals 20 ai are inserted in through-holes 12 ai of the lower housing 12, and their contact points 20 CT 1 are inserted into small diameter holes 22 b of conductive collars 22 that touch the inner surfaces of the cells 10 ai.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Underfill method and chip package

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Semiconductor package and semiconductor system including the same

Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Multilayered printed circuit board and manufacturing method thereof

An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22 , the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20 a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Thermal Gradient Reflow for Forming Columnar Grain Structures for Solder Bumps

A method includes heating a package structure including a first work piece and a second work piece to melt a plurality of solder bumps between the first and the second work pieces; and after the step of heating, allowing the plurality of solder bumps to solidify. During the step of solidifying, a first side of the package structure is maintained at a first temperature higher than a melting temperature of the plurality of solder bumps by using a heating source. During the step of solidifying, a second side of the package structure is maintained at a second temperature lower than the melting temperature by using a cooling source, wherein the second side is opposite the first side.

Semiconductor device package with electromagnetic shielding

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

Semiconductor device and method of forming the same

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.