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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 3137. Отображено 100.
14-03-2013 дата публикации

Disk array device and disk array device control method

Номер: US20130067165A1
Автор: Atsushi IGASHIRA, Chikashi Maeda, Hidejirou Daikokuya, Kazuhiko Ikeuchi, Kenji Kobayashi, Norihide Kubota, Ryota Tsukahara, Takeshi Watanabe
Принадлежит: Fujitsu Ltd

A disk array device includes hard disks from which RAID groups are configured. Therein, a volume setting unit sets one or more used areas. A data check control unit determines, on the basis of the state into which the used areas have been set, which areas in the RAID groups are subject to a diagnosis. A data check execution unit that executes a cyclical diagnosis on the areas determined, by the data check control unit, to be those subject to a diagnosis.

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Номер записи: 1
16-05-2013 дата публикации

Method and apparatus for checking a main memory of a processor

Номер: US20130124925A1
Автор: Christian Hildner
Принадлежит: SIEMENS AG

A method and an apparatus for checking a main memory of a processor, which includes a cache memory and a plurality of registers. Before the memory test is carried out, a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test is written to at least one register and is held there, and the access from the cache memory to the main memory is activated. The main memory is accessed via the cache memory such that bit patterns are written to the cache memory and from there to the main memory, and are read out again from the main memory via the cache memory and are compared. The area of the main memory to be tested is larger than the size of the cache memory. The interrupted boot-up sequence is then restarted or continued after completion of the memory test.

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Номер записи: 2
13-06-2013 дата публикации

IMAGE FORMING APPARATUS

Номер: US20130151903A1
Автор: KINOSHITA Hiroki
Принадлежит: SHARP KABUSHIKI KAISHA

An image forming apparatus has a plurality of device modules for executing predetermined functions; and a control module for controlling operation of the device modules. The control module comprises an initialization section for establishing a link; a master data transfer section for transferring data to a device module; and a link checking section for checking the state of the link. When a request for data transfer to a first device module out of the plurality of device modules is made, the link checking section checks the state of the link between the control module and the first device module. When the state of the link checked is determined to be abnormal, the initialization section establishes the link between the control module and the first device module, and then the master data transfer section transfers the data requested to be transferred to the first device module. 1. An image forming apparatus comprising:a plurality of device modules for executing predetermined functions; anda control module for controlling operation of the device modules, the device modules and the control module being connected through a PCI Express interface, an initialization section for establishing a link between the control module and each device module;', 'a master data transfer section for transferring data requested to be transferred to a predetermined device module; and', 'a link checking section for checking the state of the link between the control module and the device module, wherein, 'the control module comprisingwhen a request for data transfer to a first device module out of the plurality of device modules is made,the link checking section checks the state of the link between the control module and the first device module, andwhen the state of the link checked is determined to be abnormal,the initialization section establishes the link between the control module and the first device module, and thenthe master data transfer section transfers the data requested to be ...

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Номер записи: 3
27-06-2013 дата публикации

Method and software for testing touch panels

Номер: US20130162548A1
Автор: Chia-Lung Wang, Chun-Nan Chen, Pei-Hsu Wang, Po-Hua Chen, Tsung-Hsien Hsu, Wei-Shuo Hsu
Принадлежит: Hannstouch Solution Inc

The method for testing a touch panel includes steps of providing the touch panel, providing a software for testing the touch panel, and determining the data variable parameter corresponding to the touch panel so as to test the touch panel. The software contains a data variable parameter, which includes one selected from a group consisting of an interface setting variable parameter, a touch controller IC variable parameter, an automatic test variable parameter, a manual test variable parameter and a combination thereof

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Номер записи: 4
13-02-2014 дата публикации

Solid state drive tester

Номер: US20140047286A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

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Номер записи: 5
13-02-2014 дата публикации

Error generating apparatus for solid state drive tester

Номер: US20140047290A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

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Номер записи: 6
07-01-2016 дата публикации

AUTOMATIC TEST PATTERN GENERATION FOR A RECONFIGURABLE INSTRUCTION CELL ARRAY

Номер: US20160004617A1
Автор: Abdelmuti Ihab, Boynapalli Venugopal, Fang Joseph Weizhou, Khawam Sami, Macha Raju, Nousias Ioannis, Rao Hari Madhava
Принадлежит:

An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals. 1. An array , comprising:a plurality of tiles, each tile including:a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels; andan instruction cell comprising a plurality of logic gates for producing an instruction cell output from selected ones of the input channels;wherein each I/O port is configured to select from the instruction cell output and from the input channels for the remaining I/O ports to form the I/O port's output channels, and wherein a subset of the I/O ports are configured in a testing mode to prevent any of their output channels from being combinatorial signals.2. The array of claim 1 , wherein each I/O port includes:a plurality of first multiplexers corresponding to the I/O port's plurality of output channels; each first multiplexer being configured in a normal mode of operation to select from the I/O port's tile's instruction cell output and from the corresponding input channel from each of the remaining I/O ports in the I/O port's tile to form an output signala plurality ...

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Номер записи: 7
27-01-2022 дата публикации

Systems And Methods To Bifurcate At Least One Peripheral Component Interconnect Express (PCIE) Port In Accordance With A User-Selectable PCIE Bifurcation Setting

Номер: US20220027165A1
Автор: Cheng Che Nan, Juan Chien Yi, Leara William D.
Принадлежит:

Systems and methods disclosed herein provide a novel solution for PCIe port bifurcation. Unlike conventional client systems, which rely on resistors, jumpers or DIP switches, the disclosed systems and methods enable PCIe ports to be configured in accordance with a plurality of user-selectable PCIe bifurcation settings provided within a boot setup menu. When an “Auto” setting is selected in the boot setup menu, the disclosed systems and methods enable PCIe ports to be: (a) configured in accordance with the bifurcation requirements of the PCIe adapter card(s) connected to the PCIe ports, and (b) automatically reconfigured when bifurcation requirements change. Unlike conventional server systems, which require the user to enter BIOS setup and manually change the PCIe bifurcation settings provided in the BIOS setup menu, the systems and methods disclosed herein enable PCIe ports to be automatically reconfigured, when bifurcation requirements change, without user intervention. 1. An information handling system (IHS) , comprising:at least one Peripheral Component Interconnect Express (PCIe) port;a host processor having a PCIe interface coupled to the at least one PCIe port, wherein configuration pins of the PCIe interface are configured to receive configuration signals for configuring the at least one PCIe port;an embedded controller (EC) coupled to the configuration pins of the PCIe interface, wherein when the IHS is powered on or rebooted, the EC initiates a boot process for the IHS and executes program instructions early in the boot process before the host processor comes out of reset to detect a user-selectable PCIe bifurcation setting and drive the configuration signals, which are supplied to the configuration pins of the PCIe interface to configure the at least one PCIe port in accordance with the user-selectable PCIe bifurcation setting.2. The information handling system as recited in claim 1 , further comprising a non-volatile computer readable memory storing a ...

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Номер записи: 8
14-01-2016 дата публикации

SENSITIVE DATA PROTECTION DURING USER INTERFACE AUTOMATION TESTING SYSTEMS AND METHODS

Номер: US20160012247A1
Автор: Han Jun, Wu Junlong
Принадлежит:

There is provided systems and method for sensitive data protection during user interface automation testing. A user may transmit sensitive data to the test website framework, where the sensitive data is encrypted as a data key. The encrypted data key is set by an administrator of the test website and given to the user. The user may enter the key, where the test website framework application utilizes a conversion kit to decrypt the encrypted data key for use in the website user interface automation test. However, the encrypted data key is pulled into a version control system and/or viewed in test results so that the sensitive data remains hidden from view. In various embodiments, the encrypted data key may be entered into a web element, such as a password field, where the password field displays only the encrypted data key during test results. 1. A method comprising:receiving, from a client device, data entered to a field of a test website user interface (UI) by a user of the test website UI;encrypting at least a portion of the data using an encryption algorithm to generate cipher text of the data;entering the cipher text in a test data file for a test session by the user using the test website UI;generating a cipher mapping file for the cipher text in the test data file; andstoring the cipher mapping file with the encryption algorithm.2. The method of claim 1 , wherein the cipher text is visible in the data file.3. The method of claim 1 , wherein the data is entered into a web element prior to entering the cipher text in the test data file.4. The method of claim 1 , wherein the test data file is stored by a version control system.5. The method of claim 1 , wherein the cipher mapping file includes a key-value pair list corresponding to a plurality of data keys and a plurality of matching cipher text.6. The method of claim 5 , wherein the cipher mapping file is used to determine the cipher text in the test data file by a system administrator or test executor during ...

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Номер записи: 9
14-01-2021 дата публикации

System, apparatus and methods for automatically testing mobile devices

Номер: US20210011824A1
Автор: Bartosz BEDYNSKI, Brian Parsons, Gerald J. Parsons, Lukasz MACNAR, Mario HUBER, Mark Parsons, Martin Fiedler, Nick Gamber, Nidhin Davis, Pooya Heiraty, Sean PARSONS, Soham PATWARDHAM, Timothy HOPFER
Принадлежит: Communications Test Design Inc

Apparatus and methods for automatically testing mobile devices are disclosed according to various embodiments. In one example, a disclosed apparatus includes: a robot having a retention device into which the mobile device to be tested is positioned; a test computer having a processor and a non-transitory computer readable storage medium storing test software for testing the mobile device; and a user monitor electrically connected to the test computer and configured for providing a result of the testing of the mobile device. The mobile device is wirelessly connected to the test computer and has a test application installed thereon corresponding to the test software. The robot is configured for performing interaction and manipulation of the mobile device in cooperation with the test application and the test software during the testing.

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Номер записи: 10
19-01-2017 дата публикации

Mobile device, radio transceiver circuit, and impedance adjustment device

Номер: US20170019134A1
Автор: Jinfeng ZHOU, Zhichong CHEN
Принадлежит: Intel Corp

A mobile phone device, a radio frequency transceiver circuit and an impedance adjusting device. The present invention discloses a mobile phone device. The mobile phone device comprises a baseband processor, an antenna, a duplexer and a radio frequency transceiver circuit. The antenna is used to receive and send radio frequency signals. The duplexer is electrically connected to the antenna. The radio frequency transceiver circuit is connected to the baseband processor and the duplexer, respectively. The radio frequency transceiver circuit comprises a first power amplifier and an impedance adjusting device. The first power amplifier has a first output impedance. The impedance adjusting device is electrically connected between the first power amplifier and the duplexer, and comprises at least one switch, wherein the baseband processor is connected to and control the at least one switch of the impedance adjusting device to adjust an impedance value of the impedance adjusting device, such that a first load impedance of the first power amplifier and the first output impedance match one another.

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Номер записи: 11
19-01-2017 дата публикации

Methods for controlling mobile phones and instruments and systems using the same

Номер: US20170019514A1
Автор: Haibo Xu
Принадлежит: Intel Corp

Embodiments of the invention propose a method for mobile phone and instrument control a system using the method. The method for mobile phone and instrument control is performed by a processing unit and comprises the following steps: reading one script; determining what a destination is according to the script; if the destination is a mobile phone, transmitting a first control command to the mobile phone according to the script; and if the destination is one of a plurality of instruments, transmitting a second control command to the instrument according to the script.

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Номер записи: 12
17-01-2019 дата публикации

METHODOLOGY OF USING THE VARIOUS CAPABILITIES OF THE SMART BOX TO PERFORM TESTING OF OTHER FUNCTIONALITY OF THE SMART DEVICE

Номер: US20190020423A1
Автор: Diperna Derek, Kutchuk Artun, LEVENTHAL Ira, SCHAUB Keith
Принадлежит:

An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller coupled to a smart device in an enclosure, wherein the system controller comprises a memory comprising test logic and a processor. The enclosure comprises a plurality of components, wherein the processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic. The plurality of components comprises: (a) a robotic arm comprising a stylus affixed thereto; and (b) a platform comprising a device holder affixed thereto, wherein the smart device is inserted into the device holder; and (c) a wireless access point. The processor is further configured to: (a) control the smart device to activate wireless mode; (b) receive wireless signals from the wireless access point using the smart device; (c) retrieve wireless scan results from the smart device; and (d) analyze the wireless scan results. 1. An automatic system level testing (ASLT) system for testing smart devices , said system comprising:a system controller operable to be coupled to a smart device, wherein the system controller comprises a memory comprising test logic and a processor; a robotic arm comprising a stylus attached thereto, wherein the stylus is operable to manipulate the smart device to simulate human interaction therewith; and', 'a platform comprising a device holder attached thereto, wherein the device holder is operable to hold the smart device inserted therein, wherein the platform is operable to rotate in a x-z plane and a y-z plane;, 'an enclosure comprising a plurality of components, the plurality of components comprising retrieve metadata from a plurality of sensors on said smart device; and', 'transmit the metadata to the system controller., 'and wherein the processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic, and further wherein ...

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Номер записи: 13
25-01-2018 дата публикации

Inspection method for touch panel control substrate, and touch panel controller

Номер: US20180024182A1
Автор: Eiji NAKAUE, Narakazu Shimomura
Принадлежит: Sharp Corp

An inspection method for a touch panel control substrate, with which inspection for mounting failure is able to be simply executed, is provided. On the basis of a response that is obtained, in response to a drive signal supplied to a first drive line terminal ( 101 E), in a different drive line terminal ( 102 E, 103 E), an electrical connection state between the first drive line terminal ( 101 E) and the drive line terminal ( 102 E, 103 E) is detected.

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Номер записи: 14
25-01-2018 дата публикации

METHODS AND SYSTEM FOR DETECTING FALSE DATA INJECTION ATTACKS

Номер: US20180024900A1
Автор: Baone Chaitanya Ashok, Pan Yan, Premerlani William James
Принадлежит:

A system for detecting false data injection attacks includes one or more sensors configured to each monitor a component and generate signals representing measurement data associated with the component. The system also includes a fault detection computer device configured to: receive the signals representing measurement data from the one or more sensors, receive a fault indication of a fault associated with the component, generate a profile for the component based on the measurement data, and determine an accuracy of the fault indication based upon the generated profile. 1. A system for detecting false data injection attacks , said system comprising:one or more sensors configured to monitor a component and generate signals representing measurement data associated with the component; and receive the signals representing measurement data from the one or more sensors;', 'receive a fault indication of a fault associated with the component;', 'generate a profile for the component based on the measurement data; and', 'determine an accuracy of the fault indication based upon the generated profile., 'a fault detection computer device comprising a processor and a memory coupled to said processor, said fault detection computer device in communication with said one or more sensors, said fault detection computer device configured to2. The system in accordance with claim 1 , wherein said fault detection computer device is further configured to:store a plurality of profiles corresponding to a plurality of faults;compare the generated profile with the stored plurality of profiles; anddetermine the accuracy of the fault indication based on the comparison.3. The system in accordance with claim 2 , wherein said fault detection computer device is further configured to determine at least one potential sensor error based on the comparison.4. The system in accordance with claim 3 , wherein said fault detection computer device is further configured to issue a maintenance request based on ...

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Номер записи: 15
24-01-2019 дата публикации

TECHNOLOGIES FOR ERROR HANDLING FOR HIGH SPEED I/O DATA TRANSFER

Номер: US20190026178A1
Автор: Zhang Ning
Принадлежит:

Technologies for error handling of high speed input/output (I/O) data transfer is disclosed. Before a data transfer between an external I/O device (such as an SDIO card, other SDIO device, or USB device) and an I/O host controller of a compute device, tuning registers of the I/O host controller may be set. If the data transfer is unsuccessful, the compute device may access a table stored in the I/O host controller (or stored elsewhere in the compute device) which includes other sets of values of the tuning registers that may be used to successfully transfer data, and then attempt the data transfer with another set of values of the tuning registers. In order to initialize the table with sets of values that may be used, the compute device first performs test data transfers with various settings of the tuning registers. 125-. (canceled)26. A compute device comprising:an I/O host controller comprising one or more tuning registers; determine a plurality of tuning registers values sets, wherein each tuning registers values set indicates a setting for each of the one or more tuning registers;', 'apply, for each of the plurality of tuning registers values sets, the corresponding tuning registers values set to the one or more tuning registers;', 'perform, for each of the plurality of tuning registers values sets, a test data transfer between the compute device and a first I/O device using the I/O host controller with the corresponding tuning registers values set;', 'determine, for each of the plurality of tuning registers values sets, whether the corresponding test data transfer was successful; and', 'store, in a tuning registers values table of the compute device, an indication for each of at least two tuning registers values sets of the plurality of tuning registers values sets in response to a determination that the corresponding test data transfer of each of the at least two tuning registers values sets was successful., 'an I/O tuning filtering module to27. The compute ...

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Номер записи: 16
04-02-2021 дата публикации

MEMORY SYSTEMS AND WRITING METHODS OF THE MEMORY SYSTEMS

Номер: US20210034457A1
Автор: KIM Du Hyun
Принадлежит: SK HYNIX INC.

A memory system includes a host error correction code (ECC) encoder and a memory module. The host ECC encoder performs a host ECC encoding operation of write data to output host ECC encoded data, and the memory module includes a memory medium receiving the host ECC encoded data and a module controller controlling the memory medium. The module controller includes a parity remover and a module ECC decoder. The parity remover removes parity data from the host ECC encoded data to generate parity-removed data and performs a first write operation for writing the parity-removed data into the memory medium. The module ECC decoder performs a module ECC decoding operation of the host ECC encoded data to generate module ECC decoded data and performs a second write operation for writing the module ECC decoded data into the memory medium. 1. A memory system comprising:a host error correction code (ECC) encoder configured to perform a host ECC encoding operation on write data to output host ECC encoded data; anda memory module including a memory medium and a module controller, the memory module configured to receive the host ECC encoded data and the module controller configured to control the memory medium, a parity remover configured to remove parity data from the host ECC encoded data to generate parity-removed data and configured to perform a first write operation for writing the parity-removed data into the memory medium; and', 'a module ECC decoder configured to perform a module ECC decoding operation of the host ECC encoded data to generate module ECC decoded data and configured to perform a second write operation for writing the module ECC decoded data into the memory medium., 'wherein the module controller includes2. The memory system of claim 1 , wherein the host ECC encoder is disposed in a host.3. The memory system of claim 1 , wherein the host ECC encoded data includes the write data and the parity data.4. The memory system of claim 1 , wherein the first and second ...

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Номер записи: 17
04-02-2021 дата публикации

HARDWARE AND DRIVER VALIDATION

Номер: US20210034487A1
Автор: CHANG Yuen-Chen D., FOTEDAR Sandeep, KIRITA George A.
Принадлежит:

Compatibility testing systems and methods are disclosed that provide scalable validation testing of systems and devices. In examples, systems and devices are identified to provide fundamental information about driver operations and driver extensions functionality. The identification allows systems and devices having particular similarities to be grouped in object groups. Compatibility tests are tagged as corresponding to the identifiable systems, devices, and/or object groups, compatibility testing system and methods map test sets specifically tailored to systems and devices as identified by their driver operations and driver extensions functionality. The tailored test sets include tests that ensure compatibility and through optimized test-to-device target mapping, an optimal set of testing set is discovered and scheduled to run. Strategically controlling the amount of testing distributed and executed increases compatibility testing speed and scalability. 1. A system for compatibility testing , the system comprising:one or more memories that store a plurality of compatibility tests, the plurality of compatibility tests indicating devices that correspond thereto; and receive, by a server from a client system, information describing devices of the client system;', 'based on at least a portion of the received information, identify one or more devices of the client system, wherein a device is identified via an object identity;', 'based on the object identities of the identified devices, determine which of the identified devices are part of one or more device groups, wherein a device group comprises devices having a threshold of similarities;', 'based on the determination, select one or more devices of the identified devices for testing;', the compatibility test indicating correspondence with at least one of the selected devices, or', 'the compatibility test indicating correspondence with a device group comprising at least one of the selected devices;, 'in response to ...

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Номер записи: 18
08-02-2018 дата публикации

STORAGE DEVICE, TEST SYSTEM FOR TESTING THE SAME, AND METHOD THEREOF

Номер: US20180039554A1
Автор: WANG KyuYeul
Принадлежит:

Embodiments include a method of a test system that comprises a host device and at least one storage device having multiple ports connected to the host device through a multi-port connection, the method comprising: issuing, by a test program at the host device, a first command; generating, by a device driver at the host device, a plurality of second commands in response to the first command; and simultaneously transferring, by the host device, the second commands to each of the at least one storage device. 1. A method of a test system that comprises a host device and at least one storage device having multiple ports connected to the host device through a multi-port connection , the method comprising:issuing, by a test program at the host device, a first command;generating, by a device driver at the host device, a plurality of second commands in response to the first command; andsimultaneously transferring, by the host device, the second commands to each of the at least one storage device.2. The method of claim 1 , wherein:the multi-port connection is a dual port connection; andgenerating the second commands comprises generating two commands corresponding to the command.3. The method of claim 1 , wherein the first command comprises an operation code claim 1 , a first address claim 1 , a flag indicating a dual port operation claim 1 , and a second address.4. The method of claim 3 , wherein the generating of the second commands comprises determining claim 3 , by the device driver claim 3 , whether the flag exists in the first command.5. The method of claim 4 , wherein:the generating of the second commands comprises generating a first generated command having the operation code and the first address and a second generated command having the operation code and the second address if the flag exists; andthe simultaneously transferring of the second commands comprises simultaneously transferring the first generated command and the second generated command to each of the at ...

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Номер записи: 19
07-02-2019 дата публикации

METHOD AND APPARATUS FOR SECURING COMMUNICATION OF INSTRUCTIONS TO MANAGE ANTENNA POWER OUTPUT

Номер: US20190041929A1
Автор: Bologna Benny J., Koshy Kamal J., Montero Adolfo S.
Принадлежит: DELL PRODUCTS, LP

A system of antenna power management security may comprise a memory for storage in a standard absorption rate control register of code instructions executed to alter a transmitting antenna power level, and a processor operably connected to the memory executing code instructions of an antenna power management security system to store a randomly generated challenge number in a challenge register of the memory, determine a first response value based on the randomly generated challenge number, read a second response value determined by the processor executing code instructions of a basic input output system and stored in the memory, and if the first response value matches the second response value, allow the processor executing code instructions of the basic input output system to store a single command in the standard absorption rate control register within a preset time period, for later execution by the processor. 1. An information handling system comprising:a standard absorption rate control register for storage of one or more code instructions executed to alter a power level of a transmission by an operably connected transmitting antenna; store a randomly generated number in a challenge register;', 'determine a first response value based on the randomly generated number;', 'read a second response value determined by the processor executing basic input output system code instructions and stored in a response register;', 'compare the first response value to the second response value;', 'if the first response value matches the second response value, receive a power management command to alter power supplied to the transmitting antenna from the processor executing basic input output system code instructions via a secure interface; and', 'store the power management command within the standard absorption rate control register within a preset time period for later execution by the processor., 'a processor operably connected to the memory executing code instructions of an ...

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Номер записи: 20
25-02-2016 дата публикации

SEMICONDUCTOR DEVICE AND FAULT DETECTION METHOD THEREFOR

Номер: US20160055070A1
Автор: ITO Hirohiko
Принадлежит:

According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes. 1. A semiconductor device comprising:an arithmetic unit that performs processing for executing a computer program;a plurality of sound units that perform output of sound data stored in a memory to an external terminal and transfer of the sound data, input from the external terminal, to the memory;a route switching unit that switches a transfer route of sound data input to and output from the plurality of sound units, the route switching unit being provided between the plurality of sound units and the external terminal; anda memory transfer controller that includes a plurality of memory-transfer control units that control transmission and reception of data between the memory and the plurality of sound units, and a unit control unit that controls the plurality of memory-transfer control units, whereinthe arithmetic unit controls the route switching unit according to the computer program to configure at least three sound data transfer routes configured by one of the sound units and one of the memory-transfer control units, transfers reproduction sound data stored in the memory from the memory to the external terminal side via at least the one of the sound data transfer routes, and transfers at least two recording sound data generated on account of the reproduction sound data from the external terminal side to the memory via at least two of the sound data transfer routes.2. The semiconductor device according to claim 1 , wherein the arithmetic unit ...

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Номер записи: 21
13-02-2020 дата публикации

CHECKING DATA INTEGRITY OF DATA STORAGE SYSTEMS

Номер: US20200050508A1
Автор: Sipka Andrea, Wilkinson John
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method and apparatus for validating operation of a data volume on a storage medium. A data integrity component is provided which writes data blocks to the volume in a sequence, each data block storing a sequence number and also write status information specifying the sequence numbers of those preceding data blocks in the stream which are still being written to the volume at the time the data block is generated. Data validation is performed by reading back the stored data blocks from the volume and checking that the sequence numbers stored in them match those that should be present based on the sequence numbers stored in the write status information of the last-written data block found on the volume. 1. A method for validating operation of a storage medium that is subdivided into a number of address blocks available for data storage in a computing environment , the method comprising:for accessing data integrity of the storage medium, writing a stream of data blocks in sequence to the storage medium, each data block being allocated a sequence number indicating its position in the stream, the sequence number being stored with the data block together with write status information specifying the sequence numbers of those preceding data blocks in the stream.2. The method of claim 1 , further including:generating the stream of data blocks in sequence to write to the storage medium;allocating the address block to which a next data block in the stream is to be written by applying a sequencing function to the sequence number, wherein the sequencing function is periodic; andperforming a write process for each data block to its allocated address block.3. The method of claim 1 , wherein assessing the data integrity further includes:examining the storage medium to identify from the data blocks stored on the storage medium their sequence numbers;identifying a last-written data block having a highest sequence number from among the identified data blocks;extracting from the last- ...

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Номер записи: 22
14-02-2019 дата публикации

CORRELATION ACROSS NON-LOGGING COMPONENTS

Номер: US20190052516A1
Автор: Barli Praveen Kumar, Chatterjee Arijit, Hiremath Basaveshwar S., Syed Nosheen M., Wright David Christopher, Yuan Qingqing
Принадлежит:

Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s). 1. A computing system comprising a receiving component that is an instrumented component configured for generating log records for transaction processing associated with a transaction that is processed by multiple components , including at least one component that is not instrumented for logging , the computing system comprising:one or more processors; and receiving a transaction to process from a particular component;', 'determining that the particular component is a non-logging component which has not been instrumented for logging the transaction processes; and', 'in response to determining that the particular component is a non-logging component, creating an initial passing off log record associated with passing off of the transaction processing from the non-logging component to the receiving component., 'one or more storage device having stored computer-executable instructions that are executable by the one or more processors for causing the receiving component to perform a method comprising2. The computing system recited in claim 1 , wherein the method further includes:at the receiving component, creating a different passing off log record associated with passing off of the transaction processing from the receiving component to a new logging component.3. The ...

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Номер записи: 23
14-02-2019 дата публикации

CORRELATION ACROSS NON-LOGGING COMPONENTS

Номер: US20190052517A1
Автор: Barli Praveen Kumar, Chatterjee Arijit, Hiremath Basaveshwar S., Syed Nosheen M., Wright David Christopher, Yuan Qingqing
Принадлежит:

Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s). 1. A logging control computing system comprising:one or more processors; and receiving a first component log record, the first component log record being generated by a first component that is instrumented for generating log records associated with handling of transaction processing, the first component log record being generated in response to the first component receiving or processing the transaction processing;', 'receiving an impersonated information log record that is associated with handling of the transaction processing by a second component that received a handoff of the transaction processing from the first component, the impersonated information log record being generated by the first component rather than from the second component, wherein the second component is a non-logging component and wherein the impersonated information component log record was generated by the first component in response to a determination that the second component is a non-logging component; and', 'logging the first component log record and the impersonated information component log record into persistent storage to reflect a flow of the transaction processing by the first component and the second component., 'one or more computer-readable storage device having stored computer ...

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Номер записи: 24
26-02-2015 дата публикации

DISTRIBUTED PIN MAP MEMORY

Номер: US20150058677A1
Автор: BLOOM Scott, Jones Michael
Принадлежит: ADVANTEST CORPORATION

In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources. 1. In a testing device , a method for implementing distributed pin mapping , comprising:receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges;implementing accesses to the pin map memories locally at each of the plurality of bridges; andusing pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.2. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules.3. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.4. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules coupled together via a high-speed bus.5. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components claim 1 , wherein each bridge component comprises two half bridge components claim 1 , and wherein each half bridge component includes a pin map memory.6. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules claim 1 , and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.7. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules claim 1 , and wherein the pin electronics modules can be configured to support different combined resource modes of operation.8. ...

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Номер записи: 25
04-03-2021 дата публикации

COMPLEX PROGRAMMABLE LOGIC DEVICE AND OPERATION METHOD THEREOF

Номер: US20210064493A1
Автор: ZHAN Peng
Принадлежит:

A complex programmable logic device includes a SGPIO analyzing circuit, a IC analyzing circuit and a first multiplexer. The SGPIO analyzing circuit has a plurality of port analyzing circuits, a detecting circuit and a processing circuit. Each port analyzing circuit receives an input signal and outputs a first data. The detecting circuit detects the input signal of the first port analyzing circuit to output a detecting signal. The processing circuit captures port information of the first data outputted by at least part of the port analyzing circuits as a first control signal according to the detecting signal. The IC analyzing circuit analyzes a data flow for outputting a second control signal according to an address command related to an address message, a control command and an input data. The first multiplexer selects the first control signal or the second control to be outputted according to a testing signal. 1. A complex programmable logic device , comprising:a SGPIO analyzing circuit comprising:a plurality of port analyzing circuits, with each of the plurality of port analyzing circuits having an input terminal and an output terminal, the input terminal configured to receive a first input signal and the output terminal configured to output a piece of first data;a detecting circuit electrically connected to the input terminal of a first port analyzing circuit among the plurality of port analyzing circuits and detecting the first input signal received by the first port analyzing circuit for outputting a detecting signal; anda processing circuit electrically connected to the plurality of output terminals of the plurality of port analyzing circuits and the detecting circuit, the processing circuit obtaining port information included in each of the pieces of first data outputted by the output terminals of at least part of the plurality of port analyzing circuits according to the detecting signal for outputting a first control signal;{'sup': 2', '2, 'a IC analyzing ...

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Номер записи: 26
28-02-2019 дата публикации

Touch Screen Testing Platform for Engaging a Dynamically Positioned Target Feature

Номер: US20190064981A1
Автор: Jenkinson David Ross
Принадлежит:

A touch screen testing platform may be used to engage a dynamically positioned target feature being displayed on a touch screen enabled device during a testing protocol. The platform may record imagery displayed by the touch screen device and then analyze the imagery to locate the target feature within a reference coordinate system. The platform may recognize that the target feature is missing from the imagery and respond by causing the touch screen device to scroll through a command menu and/or toggle through virtual screens. Once located, the platform may instruct a robotic device tester to select the target feature by contacting the touch screen at the identified location using a conductive tip designed to simulate a user's fingertip. Prior to running a test, the camera may be focused to a point that is offset from the display screen of the touch screen device. 1. A system for testing a touch screen device , the system comprising:a camera configured to record an image of a touch screen of the touch screen device;a robot configured to move a tip to contact the touch screen; and receiving, from the camera, the image of the touch screen;', 'determining, based at least in part on the image, a coordinate location of a target feature displayed on the touch screen; and', 'causing the robot to provide an input to the touch screen device by moving the tip to contact the touch screen at the coordinate location to engage with the target feature on the touch screen, the input to the touch screen device to simulate a user selection of the target feature., 'a controller configured to control movement of the tip by the robot by2. The system of claim 1 , wherein the controller causing the robot to provide the input to the touch screen device comprises the controller providing an instruction to the robot to move the tip to contact the touch screen at the coordinate location.3. The system of claim 1 , wherein the controller is further configured to control movement of the tip by ...

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Номер записи: 27
28-02-2019 дата публикации

SECURITY ARRANGEMENT

Номер: US20190065411A1
Автор: PATZELT Andreas, Voss Christian, WOHLGEMUTH Christopher
Принадлежит:

The present invention relates to a security arrangement comprising a data processing unit for serial transmission of data for controlling outputs and for querying inputs of a process and a corresponding method; further comprising at least one parallel-to-serial converter comprising a shift register for converting data to query the inputs; at least one serial-to-parallel converter comprising a shift register for converting data to control the outputs; wherein the data to be transmitted includes diagnostic bits that are output from the serial-to-parallel converter and read back from the parallel-to-serial converter; and the read-back data is checked for errors by the data processing unit to ensure a secure data transmission. 1. A security arrangement comprising a data processing unit for serial transmission of data for controlling outputs and for querying inputs of a process; further comprisingat least one parallel-to-serial converter, comprising a shift register for converting data to query the inputs;at least one serial-to-parallel converter comprising a shift register for converting data to control the outputs; whereinthe data to be transmitted includes diagnostic bits that are output from the serial-to-parallel converter and read back from the parallel-to-serial converter; andthe read-back data is checked for errors by the data processing unit to ensure a secure data transmission.2. The security arrangement according to claim 1 , further comprising a coupling unit which is connected downstream of the data processing unit.3. The security arrangement according to claim 2 , wherein the coupling unit comprises at least one galvanic separating element.4. The security arrangement according to claim 1 , wherein the data processing unit is a security controller.5. The security arrangement according to claim 1 , comprising a plurality of serially connected serial-to-parallel converters and/or a plurality of serially connected parallel-to-serial converters.6. The security ...

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Номер записи: 28
28-02-2019 дата публикации

AUTOMATIC OPTIC INSPECTION DEVICE AND INSPECTION SYSTEM FOR DISPLAY PANEL

Номер: US20190066554A1
Автор: CHEONG Yoseop, Guo Hongyan, JIANG Zengyang, LI Baota, TANG Cundui, Wang Yong, WU Huailiang, XIE Zongtian, Yu Yang, ZHONG Guiping
Принадлежит:

An automatic optic inspection device and an inspection system for a display panel. The automatic optic inspection device includes: a housing including at least a top wall and a side wall, the side wall including a viewing port; a slide rail fixed on the housing near the top wall; and a camera slidably disposed below the slide rail. An optical axis of the camera passes through the viewing port. During the inspection, the camera is moved on the slide rails so that the camera is close to the stage of the lighting inspection machine and can perform automatic optic inspection of the display panel. When the automatic optic inspection device fails to inspect due to a fault, the camera can be moved along the slide rail so that the camera is moved away from the stage and manual inspection can take place while the inspection device is fixed. 1. An automatic optic inspection device , comprising:a housing comprising at least a top wall and a side wall, wherein the side wall is provided with a viewing port;a slide rail fixed on the housing near the top wall; anda camera slidably disposed on the slide rail and located below the slide rail, wherein an optical axis of the camera passes through the viewing port.2. The automatic optic inspection device according to claim 1 , wherein an extending direction of the slide rail is parallel to the optical axis of the camera.3. The automatic optic inspection device according to claim 1 , wherein a driving device is disposed on the slide rail and the driving device is configured to drive the camera to slide along the slide rail.4. The automatic optic inspection device according to claim 1 , wherein the housing further comprises a support frame on which the sidewall is disposed.5. The automatic optic inspection device according to claim 1 , wherein the housing further comprises a movable door.6. The automatic optic inspection device according to claim 1 , further comprising an inspection and analysis device disposed inside the housing claim 1 ...

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Номер записи: 29
07-03-2019 дата публикации

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

Номер: US20190073285A1
Автор: Hayashida Akira
Принадлежит: FUJITSU LIMITED

An information processing device includes a device, a management device that is connected to the device via a first transmission route and configured to acquire information regarding the device via the first transmission route, and a processing device that is connected to the device via a second transmission route, connected to the management device via a third transmission route, and configured to initialize the device and acquire the information from the management device via the third transmission route. 1. An information processing device comprising:a device;a management device that is connected to the device via a first transmission route and configured to acquire information regarding the device via the first transmission route; anda processing device that is connected to the device via a second transmission route, connected to the management device via a third transmission route, and configured to initialize the device and acquire the information from the management device via the third transmission route.2. The information processing device according to claim 1 , whereinthe management device is a baseboard management controller,the processing device has a processor configured to perform BIOS,the device is an input/output device,the first transmission route is an Inter-Integrated Circuit type of wire, andthe second transmission route is a Peripheral Component Interconnect-Express type of wire.3. The information processing device according to claim 1 , whereinthe processing device is further configured to, when an error has occurred during initialization of the device, identify the device that has the error on the basis of the acquired information.4. The information processing device according to claim 1 , whereinthe management device is connected to the device via the second transmission route,the management device is configured to acquire the information regarding the device via the second transmission route.5. The information processing device according to ...

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Номер записи: 30
24-03-2022 дата публикации

COMPUTER AND CONDUIT FOR SYSTEM TESTING

Номер: US20220091949A1
Автор: Bernas Arlene Yap, Chen Yuexi, Kang Baoxiang, Lim Si Xiang, Pakeh Mochammed Iqbal, Tan Kiat Chun
Принадлежит:

A method for testing an interaction system response to different types of interaction devices is disclosed. A testing computer can execute various sets of interaction device logic during different test interaction. The testing computer can electronically communicate with an access device during test interaction through a conduit mobile device. As a result, the testing computer can electronically communicate with the access device even when the testing computer is remotely located. 1. A method comprising:receiving, by a testing computer, an interaction input message from a mobile device, wherein the mobile device previously received the interaction input message from an access device for an interaction, the mobile device being in short-range communication with the access device;determining, by the testing computer, using a set of logic emulating a specific type of interaction device, an interaction output message based on the interaction input message; andtransmitting, by the testing computer, the interaction output message to the mobile device, wherein the mobile device forwards the interaction output message to the access device.2. The method of further comprising:generating, by the testing computer, an interaction report indicating how the access device functioned during the interaction.3. The method of claim 1 , wherein the set of logic emulating the specific type of interaction device emulates operation of a contactless smart card claim 1 , an NFC sticker claim 1 , a mobile phone claim 1 , a payment ring claim 1 , or a wearable device.4. The method of claim 1 , wherein the testing computer is in long-range communication with the mobile device.5. The method of claim 1 , wherein the interaction input message is an application protocol data unit command claim 1 , wherein the interaction output message is an application protocol data unit response claim 1 , and wherein the access device receives the application protocol data unit response and the access device ...

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Номер записи: 31
05-06-2014 дата публикации

Verification of a vector execution unit design

Номер: US20140156969A1
Автор: Maarten J. Boersma, Udo Krautz, Ulrike Schmidt
Принадлежит: International Business Machines Corp

A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.

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Номер записи: 32
22-03-2018 дата публикации

Detecting and sparing of optical pcie cable channel attached io drawer

Номер: US20180081761A1
Автор: Christoper J. Engel, Ellen M. Bauman, Gregory M. Nordstrom, Harald Pross, Jesse P. Arroyo, Kaveh Naderi, Thomas R. Sand, Timothy R. Block
Принадлежит: International Business Machines Corp

A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

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Номер записи: 33
22-03-2018 дата публикации

AUTOMATED TEST GENERATION FOR MULTI-INTERFACE ENTERPRISE VIRTUALIZATION MANAGEMENT ENVIRONMENT

Номер: US20180081795A1
Автор: Abdirashid Mohammad, Duale Ali Y., HANIF TARIQ
Принадлежит:

Embodiments for automated testing of a virtualization management system are described. According to one aspect, a method includes generating a test case including a plurality of instances of commands and sending the test case to a plurality of interfaces supported by the virtualization management system. The method also includes generating a response file corresponding to each command in the test case. The method also includes comparing results from each interface to an instance of a command and in response to the results from each interface being identical, storing, the results in the response file corresponding to the command. The method also includes reporting an error in response to the results from each interface of the virtualization management system not being identical. The present document further describes examples of other aspects such as systems, computer products. 1. A computer-implemented method for testing interfaces , the method comprising:generating commands executable by a virtualization management system;executing, by a computer, the commands on the virtualization management system using the interfaces supported by the virtualization management system, each of the interfaces being different;comparing, by the computer, results of the execution for each of the interfaces;determining, by the computer, an error occurred when the results of each of the interfaces are different; andstoring, by the computer, the results when the results of each of the interfaces are identical.2. The computer-implemented method of claim 1 , wherein each one of the interfaces is operable to communicate with the virtualization management system.3. The computer-implemented method of claim 1 , wherein each one of the interfaces is a structured as a different form of communicating with the virtualization management system.4. The computer-implemented method of claim 1 , wherein the commands are for a test case.5. The computer-implemented method of claim 1 , wherein at least one ...

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Номер записи: 34
12-06-2014 дата публикации

HOST COMPUTER AND METHOD FOR TESTING SAS EXPANDERS

Номер: US20140164845A1
Автор: WU CHIH-HUANG
Принадлежит: HON HAI PRECISION INDUSTRY CO., LTD.

In a method for testing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to a master SAS expander through a first serial port, and connects to slave SAS expanders through a second serial port. The host computer sends a test command to the master SAS expander to test the master SAS expander, and stores the test result of the master SAS expander into a flash memory of the master SAS expander. The host computer controls the master SAS expander to transfer the test command to each of the slave SAS expanders to test each of the slave SAS expanders, and stores the test result of each of the slave SAS expanders into the flash memory. The host computer displays all the test results on a display device of the host computer obtained from the flash memory. 1. A host computer being connected to a master serial attached small computer system interface (SAS) expander and a plurality of slave SAS expanders , the host computer comprising:at least one processor; anda storage device storing a computer-readable program including instructions that, which when executed by the at least one processor, causes the at least one processor to:establish a first connection between the host computer and the master SAS expander through a first serial port, and establish a second connection between the master SAS expander and each of the slave SAS expanders in series through a second serial port;send a test command to the master SAS expander through the first serial port, and test the master SAS expander according to the test command;obtain a test result of the master SAS expander through the first serial port, and store the test result of the master SAS expander into a flash memory of the master SAS expander;control the master SAS expander to transfer the test command to each of the slave SAS expanders in sequence through the second serial port, and test each of the slave SAS expanders according to the test command; andobtain a test ...

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Номер записи: 35
25-03-2021 дата публикации

INFORMATION PROCESSING APPARATUS

Номер: US20210089416A1
Автор: Katayama Yosuke, Sasaki Ken, Seto Yuichiro
Принадлежит: Lenovo (Singapore) Pte. Ltd.

An information processing apparatus includes a BIOS storage unit that stores at least a Basic Input Output System (BIOS) program, a main controller that starts up an operating system by executing the BIOS program, and a sub-controller that manages peripheral apparatuses and accesses the BIOS storage unit, in which the sub-controller includes a digest computation unit that computes a digest value on the basis of BIOS program data stored in the BIOS storage unit in parallel to execution of a process in the main controller, and in which the main controller determines validity of the BIOS program on the basis of the digest value. 1. An information processing apparatus comprising:a BIOS storage unit that stores at least a Basic Input Output System (BIOS) program;a main controller that starts up an operating system by executing the BIOS program; anda sub-controller that manages peripheral apparatuses and from which the BIOS storage unit is accessible,wherein the sub-controller includes a digest computation unit that computes a digest value on the basis of BIOS program data stored in the BIOS storage unit in parallel with execution of a process in the main controller, andwherein the main controller determines validity of the BIOS program on the basis of the digest value.2. The information processing apparatus according to claim 1 ,wherein the BIOS storage unit is accessible from the main controller via the sub-controller.3. The information processing apparatus according to claim 1 ,wherein the digest computation unit computes the digest value in response to starting of an operation of the sub-controller.4. The information processing apparatus according to claim 1 ,wherein the digest computation unit computes the digest value in response to a digest value computation request from the main controller.5. The information processing apparatus according to claim 1 ,wherein the digest computation unit computes the digest value in response to starting of an operation of the sub- ...

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Номер записи: 36
31-03-2016 дата публикации

CONTROLLING A BYTE CODE TRANSFORMER ON DETECTION OF COMPLETION OF AN ASYNCHRONOUS COMMAND

Номер: US20160092332A1
Автор: Blake Thomas A., Quadrozzi Daniele M., Ross Martin A.
Принадлежит:

Controlling a byte code transformer on detection of completion of an asynchronous command. An asynchronous command is received by an asynchronous manager from a test framework. The asynchronous command manager issues the asynchronous command to an application. A transformer is loaded for transforming byte code associated with the application in order to output one or more method names and associated timestamps of one or more method entry points and one or more method exit points. A check is made as to whether an expected result has been generated by the application. In response to determining that an expected result has been successfully generated, a time period associated with successful generation of the expected result is compared with the timestamps in order to determine matching timestamps and associated matching method names. The transformer is modified in accordance with the matching method names such that a subsequent transformation executes on byte code associated with the matching method names. 1. A computer-implemented method of controlling a byte code transformer on detection of completion of an asynchronous command , the computer-implemented method comprising:receiving, by an asynchronous command manager of a processor, an asynchronous command from a test framework;issuing, by the asynchronous command manager, the asynchronous command to an application;loading a transformer for transforming byte code associated with the application in order to output one or more method names and associated timestamps of one or more method entry points and one or more method exit points;checking whether an expected result has been generated by the application;based on determining that the expected result has been successfully generated, comparing a time period associated with successful generation of the expected result with the associated timestamps in order to determine matching timestamps and associated matching method names; andmodifying the transformer in accordance ...

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Номер записи: 37
30-03-2017 дата публикации

SYSTEM AND METHOD FOR UNIVERSAL SERIAL BUS (USB) PROTOCOL DEBUGGING

Номер: US20170091060A1
Автор: Bennett Joseph A., Gutierrez Raul, VADIVELU KARTHI R.
Принадлежит: Intel Corporation

In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described. 1. An electronic device , comprising:a processor; and detect a connection from a remote electronic device to a USB port of the electronic device;', 'determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port; and', 'in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller., 'at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to2. The electronic device of claim 1 , wherein the logic is further configured to:map the USB port of the electronic device to a host controller in response to a determination that the USB port of the electronic device is to be configured as a downstream facing port.3. The electronic device of claim 1 , wherein the logic is further configured to:communicate a configuration status of the USB port of the electronic device to a controller of the USB subsystem.4. The electronic device of claim 1 , wherein the logic is further configured to:determine whether a USB debug feature is enabled for the electronic device; andin response to a determination that the USB debug controller is ...

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Номер записи: 38
05-05-2022 дата публикации

FORMAL VERIFICATION TOOL TO VERIFY HARDWARE DESIGN OF MEMORY UNIT

Номер: US20220139480A1
Автор: Darbari Ashish, Singleton Iain
Принадлежит:

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

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Номер записи: 39
19-03-2020 дата публикации

Test method of in-cell touch display device

Номер: US20200090567A1
Автор: Hsing-Ying LEE, Jui-Hsin Tsai, Sung-Chun Lin
Принадлежит: Hannstar Display Corp, Hannstar Display Nanjing Corp

A test method of an in-cell touch display device includes providing a plurality of first test signals and a plurality of second test signals to the first connection pads and the second connection pads of the in-cell touch display device, respectively. Each of the first connection pads is electrically connected to a corresponding data line of the in-cell touch display device, and each of the second connection pads is electrically connected to a corresponding touch electrode of the in-cell touch display device, and the in-cell touch display device is tested after the first and second test signals are provided to the first and second connection pads.

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Номер записи: 40
01-04-2021 дата публикации

TEST EQUIPMENT INTERFACE ADD-ON

Номер: US20210096970A1
Автор: Clark Brian T., Ganapathy Vasanth, Gilton Jeffrey S., Nichols Douglas R., Pfenninger Matthew B.
Принадлежит: GENERAL ELECTRIC COMPANY

Devices, systems, and methods for providing an engine control system configured with a two-part test equipment monitor where at least one part is selectively removable are disclosed. An engine control system for an aircraft includes an electronic control unit (ECU). The ECU is configured to implement a production support equipment module and a selectively removable test support equipment module. The production support equipment module enables restricted data monitoring of the engine control system. The test support equipment module enables a comprehensive interface with the engine control system when installed with the ECU. 1. An engine control system for an aircraft comprising: a production support equipment module, wherein the production support equipment module enables restricted data monitoring of the engine control system; and', 'a selectively removable test support equipment module, wherein the test support equipment module enables a comprehensive interface with the engine control system when installed with the ECU., 'an electronic control unit (ECU), wherein the ECU is configured to implement2. The engine control system of claim 1 , wherein the restricted data monitoring functionality of the production support equipment module enables at least one of: sending a continuous data stream to an aircraft bus from one or more addresses of a memory module or querying an installed software version.3. The engine control system of claim 1 , wherein the comprehensive interface functionality of the test support equipment module enables at least one of:sending a continuous data stream from one or more addresses of a memory module to a test equipment device communicatively coupled to the ECU,modifying a list of addresses stored in memory,making adjustments to the engine control system,reading data from addresses in memory,writing data to addresses in memory, orinjecting parameter data into the ECU.4. The engine control system of claim 3 , wherein injecting parameter data ...

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Номер записи: 41
13-04-2017 дата публикации

Configurable Input/Output Sub-channels for Optimized Diagnostics

Номер: US20170103007A1
Автор: Peck Joseph E.
Принадлежит:

A novel diagnostics and verifiable input/output (DVIO) channel may reduce fixed diagnostic circuitry and allow standard input/output channels to be repurposed as diagnostics for specific deployments. The DVIO channel may include a digital input sub-channel and a digital output sub-channel, with each sub-channel including basic protection and diagnostic circuitry for performing basic diagnostics. The two sub-channels may be used independently of each other, and they may also be coupled together to create an enhanced digital input or digital output channel, which is capable of performing more advanced diagnostics such as output readback or test pulse generation, for example. Multiple DVIO channels may be coupled together to create a multiple-channel digital input or digital output with redundant signal paths. In this way the input/output resources may be configured to meet the specific needs of a given application, and minimize the test and diagnostic circuitry required in traditional implementations. 1. A configurable digital input/output channel comprising:an input terminal;an output terminal;a digital input sub-channel configured to perform first diagnostics; anda digital output sub-channel coupled to the output terminal and configured to perform second diagnostics;wherein the digital input sub-channel and the digital output sub-channel are configured to be selectively coupled together, wherein when coupled together, the digital input sub-channel and the digital output sub-channel interoperate as an enhanced digital channel configured to perform advanced diagnostics in addition to the first diagnostics and the second diagnostics.2. The configurable digital input/output channel of claim 1 , wherein when the digital input sub-channel and the digital output sub-channel are coupled together claim 1 , one sub-channel of the digital input sub-channel and the digital output sub-channel is configured to perform diagnostics for the other sub-channel of the digital input sub ...

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Номер записи: 42
04-04-2019 дата публикации

PRINT VERIFICATION SYSTEM THAT REPORTS DEFECTIVE PRINTHEADS

Номер: US20190102270A1
Автор: Dennison Carl Michael
Принадлежит: RICOH COMPANY, LTD.

Systems and methods are provided for print verification that reports defective printheads. One embodiment is a Print Verification System (PVS) that includes an interface to receive print data, and an imaging device to obtain image data of printed output of the print data. The PVS also includes a processor to detect a print error on a page by comparing the print data and the image data. The processor determines a lateral distance of a location of the print error with respect to an edge of the page, identifies a print engine that printed the page, determines a lateral offset of the print engine with respect to the edge of the page, identifies a printhead among a plurality of printheads of the print engine that caused the print error based on the lateral distance of the print error and the lateral offset of the print engine. 1. A system comprising: an interface configured to receive print data representing pages to print on print media;', 'an imaging device configured to obtain image data of the pages printed on the print media; and', 'a processor configured to detect a print error on a page by comparing the print data and the image data, to analyze the image data to determine a lateral distance of a location of the print error with respect to an edge of the page, to identify a print engine that printed the page, to determine a lateral offset of the print engine with respect to the edge of the page, to identify a printhead among a plurality of printheads of the print engine that caused the print error based on the lateral distance of the print error and the lateral offset of the print engine, to increment a count of errors for the printhead in a log stored in memory, and to report the count of errors for the printhead to a graphical user interface., 'a print verification system comprising2. The system of wherein: detecting that the page is one of multiple pages placed on a sheet of the print media in an N-up configuration, wherein N is an integer greater than one;', ' ...

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Номер записи: 43
28-04-2016 дата публикации

Quasi Disk Drive For Testing Disk Interface Performance

Номер: US20160117233A1
Автор: Dobbelstein Steven L., Pratt Steven L.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Embodiments relate to diagnostic evaluation of hardware components of a computer machine. A conventional storage device is replaced with a modified storage device. Read and write operations are received by the modified storage device. Issuance of a response to the read and write operations is limited to an acknowledgement receipt, which is employed to evaluate performance and/or bandwidth of the machines with respect to hardware for data storage. 1. A method comprising:configuring a computer system with a port connection to directly receive a persistent storage device;the port connection receiving a modified storage device, the modified device having logic to emulate behavior of the persistent device;emulating behavior of the persistent device, including sending a request from an application to the modified device, the request to access the modified device, including the modified device to issue a response to the request with a reply after emulating a transaction, the response including a measurement of duration for completion of the transaction at the modified device, wherein emulating the behavior includes returning a null data set for responding to a read transaction; andtesting performance of supporting hardware in communication with the modified device, including evaluating speed of processing the request.2. The method of claim 1 , further comprising evaluating speed of an intermediate component that supports physical communication of the request to the hardware element.3. The method of claim 1 , wherein testing performance further comprises evaluating response data to determine duration for processing the request and capacity of associated hardware to support the request.4. A system comprising: a computer system with a port connection to directly receive a persistent storage device;', 'the port connection receiving a modified storage device, the modified device having logic to emulate behavior of the persistent device;', a diagnostic program to support ...

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Номер записи: 44
10-07-2014 дата публикации

METHOD AND SYSTEM FOR DIAGNOSING APPARATUS

Номер: US20140195855A1
Автор: Chang Lin, Li Yi, Tao Lin, WANG Feizhou
Принадлежит: Huawei Technologies Co., Ltd.

A method for diagnosing an apparatus in a computer system, which includes: determining to enter a diagnostic mode after the computer system is started; initializing a cache in the computer system; after initializing the cache, performing a diagnosis of the apparatus by executing a diagnostic program; and after the diagnosis of the apparatus is completed, executing a Basic Input Output System (BIOS) or Extensible Firmware Interface (EFI) program and loading an operating system. 1. A method for diagnosing an apparatus in a computer system , comprising:determining to enter a diagnostic mode after the computer system is started;initializing a cache in the computer system;performing a diagnosis of the apparatus by executing a diagnostic program; andexecuting a Basic Input Output System (BIOS) or Extensible Firmware Interface (EFI) program and loading an operating system.2. The method according to claim 1 , wherein the step of determining comprises:detecting a trigger of a General Purpose Input/Output (GPIO) pin level.3. The method according to claim 1 , whereinthe diagnostic program is independent of the BIOS or EFI program.4. The method according to claim 1 , further comprising:loading the diagnostic program into the cache for execution.5. The method according to claim 1 , further comprising:initializing a serial port in the computer system before performing the diagnosis of the apparatus; andoutputting diagnostic results of the apparatus through the serial port.6. A non-transitory storage medium configured to store units comprising:a determining unit configured to determine to enter a diagnostic mode after a computer system is started;an initializing unit configured to initialize a cache in the computer system;a diagnosing unit configured to diagnose an apparatus in the computer system by executing a diagnostic program; anda normal startup unit configured to execute a Basic Input Output System (BIOS) or Extensible Firmware Interface (EFI) program, and load an operating ...

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Номер записи: 45
26-04-2018 дата публикации

BACK-PRESSURE IN VIRTUAL MACHINE INTERFACE

Номер: US20180113732A1
Автор: Garg Ankit, GARG Deepak Kumar, Ghattaas Georges Antoun Elias, Khalil Abdallah Galal Yahya, Stickley John R., Tawfik Hanan Mohamed Sameh
Принадлежит:

This application discloses a computing system having a virtual machine and a host program that communicate via a virtual interface. The virtual machine can generate a data packet for transmission to the host program via the virtual interface. The virtual machine can receive a saturation signal generated by a virtual interface driver in the virtual interface. The virtual interface driver can be configured to populate a virtual buffer in the virtual interface with the data packet. The virtual machine can determine an availability of resources in the virtual buffer to store the data packet based, at least in part, on the saturation signal, and selectively stall transmission of the data packet to the host program based, at least in part, on the saturation signal. The host program can bypass a hypervisor in the computing system to directly access the virtual buffer in the virtual interface. 1. A method comprising:generating, by a virtual machine in a computing system, a data packet for transmission to a host program in the computing system via a virtual buffer;determining, by the virtual machine, an availability of resources in the virtual buffer to store the data packet; andselectively stalling, by the virtual machine, transmission of the data packet to the host program based, at least in part, on the determined availability of the resources in the virtual buffer to store the data packet.2. The method of further comprises receiving claim 1 , by the virtual machine claim 1 , a saturation signal generated by a virtual interface driver configured to populate the virtual buffer with the data packet claim 1 , wherein the determination of the availability of resources in the virtual buffer is based claim 1 , at least in part claim 1 , on the saturation signal.3. The method of further comprises stalling transmission of the data packet to the host program in the computing system when a size of the data packet exceeds a magnitude of the storage space in the virtual buffer ...

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Номер записи: 46
04-05-2017 дата публикации

Touch screen, display device and method of operating display device

Номер: US20170123565A1
Автор: Wusheng Li
Принадлежит: BOE Technology Group Co Ltd

Disclosed is a touch screen which includes: a display panel; a cover plate located at a light exit side of the display panel; a plurality of touch electrodes located at a side of the cover plate facing towards the display panel; and a bezel portion surrounding the touch electrodes and comprising a non-black photoresist layer, a low-reflectivity conductive layer and an insulating layer which are successively stacked in a direction from the cover plate to the display panel. Also disclosed are a display device and a method of operating the display device.

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Номер записи: 47
27-05-2021 дата публикации

SYSTEM AND METHOD FOR SIMULATING HUMAN MANUAL INPUT FOR DEVICES USING CAPACITIVE TOUCHSCREENS

Номер: US20210157455A1
Автор: Kikinis Dan
Принадлежит:

Disclosed are systems, methods, and devices for simulating human manual input for devices using capacitive touchscreens. In one embodiment, the system comprises a test fixture, wherein the test fixture comprises a matrix of tubes, each tube being coated with a conductive coating; and a camera located under the matrix and configured to record the capacitive touchscreen of the device under test. The system further includes a tablet to receive images from the camera and display a visual representation of the capacitive touchscreen of the device under test, wherein the tablet is configured to receive a plurality of touch events; update the visual representation of the capacitive touchscreen of the device under test in response to the plurality of touch events; and generate a simulation of touch events, the simulation representing interaction with the device under test. The system further includes a workstation communicatively coupled to the tablet and configured to receive the simulation from the tablet device; and transmit the simulation to the test fixture to enable the execution of the simulation on one or more additional devices under test. 1. A system comprising:a camera;a text fixture for simulating manual input comprising a matrix of individually addressable structures, wherein the matrix of individually addressable structures comprises one of a liquid crystal display (LCD) display or a matrix of conductively coated tubes; and recording a simulation one or more touch events on a touchscreen that simulates touching the device under test; and', 'generating, from the simulation, a matrix representation including a plurality of touch events, the matrix representation executable by the text fixture for simulating the one or more touch events., 'a tablet configured to receive images from the camera and display a visual representation of a capacitive touchscreen of a device under test, wherein the tablet is configured to generate a simulation of touch events ...

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Номер записи: 48
27-05-2021 дата публикации

Method, System, Storage Media And Device For Stress Test Of Baseboard Management Controllers

Номер: US20210157698A1
Автор: Song Bao-Dong
Принадлежит:

Method, system, storage medium and device for stress test of the baseboard management controllers are provided. In the method, serial numbers of servers under test and physical addresses of baseboard management controllers of the servers under test are acquired and stored. The baseboard management controllers are determined according to the stored serial numbers and the physical addresses, and the stress test is performed on the baseboard management controllers of the servers under test based on multi threads in one-to-one correspondence. Therefore, the technical effect of remotely performing the stress tests on the baseboard management controllers of the servers in batches can be achieved. 1. A method for stress test of baseboard management controllers , comprising:acquiring serial numbers of servers under test, and physical addresses of baseboard management controllers of the servers under test;storing the serial numbers and the physical addresses; anddetermining the baseboard management controllers according to the serial numbers and the physical addresses, and performing stress tests on the baseboard management controllers of the servers under test based on multi threads in one-to-one correspondence.2. The method according to claim 1 , wherein the step of acquiring the serial numbers of the servers under test claim 1 , and the physical addresses of the baseboard management controllers of the servers under test claim 1 , comprises any one of steps:acquiring the serial numbers and the physical addresses of the baseboard management controllers by a packet broadcast manner through a dynamic host configuration protocol; andreceiving the serial numbers and the physical addresses of the baseboard management controllers transmitted from the servers under test, through a transmission control protocol.3. The method according to claim 1 , wherein the step of storing the serial numbers and the physical addresses comprises:installing preset software based on the serial ...

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Номер записи: 49
12-05-2016 дата публикации

SYSTEM AND METHOD FOR DISTRIBUTING ELECTRICAL POWER

Номер: US20160132089A1
Автор: Sihler Christof Martin, Tenca Pierluigi
Принадлежит:

A bus for distributing electrical power to a plurality of sets of electrical devices is disclosed. The bus includes one or more bus separators and a plurality of bus sections. The plurality of bus sections includes at least a first bus section and a second bus section electrically coupled to each other via a bus separator, where the first bus section is electrically connectable to a first set of electrical devices having a first importance metric and the second bus section is electrically connectable to a second set of electrical devices having a second importance metric different from the first importance metric. The bus separator is configured to isolate the first bus section and the second bus section based on occurrence of a fault condition. A Direct Current power distribution system employing the bus and a method for distributing electrical power via the bus are also disclosed. 1. A bus for distributing electrical power to a plurality of sets of electrical devices , the bus comprising:one or more bus separators; anda plurality of bus sections, wherein the plurality of bus sections comprises at least a first bus section and a second bus section electrically coupled to each other via a bus separator of the one or more bus separators, wherein the first bus section is electrically connectable to a first set of electrical devices of the plurality of sets of electrical devices having a first importance metric and the second bus section is electrically connectable to a second set of electrical devices of the plurality of sets of electrical devices having a second importance metric different from the first importance metric, andwherein the bus separator is configured to isolate the first bus section and the second bus section based on occurrence of a fault condition.2. The bus of claim 1 , wherein at least one bus section of the plurality of bus sections is electrically connectable to two or more sets of electrical devices of the plurality of sets of electrical devices ...

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Номер записи: 50
01-09-2022 дата публикации

EVENT INPUT DEVICE TESTING

Номер: US20220276943A1
Автор: Barson Michael, Dearden Christopher, Wolf Benjamin H.
Принадлежит:

Devices, systems, and methods for event input device testing are described herein. In some examples, one or more embodiments include a controller comprising a memory and a processor to execute instructions stored in the memory to cause a first event input device of a group of event input devices to perform an automated test process, and determine whether a second event input device of the group of event input devices has detected a hazard event while the first event input device is performing the automated test process. 1. A controller for event input device testing , comprising:a memory; and cause a first event input device of a group of event input devices to perform an automated test process as part of an automated test analysis according to a predetermined test sequence;', 'determine whether a second event input device of the group of event input devices has detected a hazard event while the first event input device is performing the automated test process;', 'cause, according to the predetermined test sequence, the second event input device to perform an automated test process as part of the automated test analysis; and', 'determine whether the first event input device has detected a hazard event while the second event input device is performing the automated test process., 'a processor configured to execute executable instructions stored in the memory to2. The controller of claim 1 , wherein the processor is configured to execute the executable instructions to cause an alarm to be generated in response to determining the second event input device has detected a hazard event while the first event input device is performing the automated test process.3. The controller of claim 1 , wherein the processor is configured to execute the executable instructions to cause an alarm to be generated in response to determining the first event input device has detected a hazard event while the second event input device is performing the automated test process.4. The ...

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Номер записи: 51
17-05-2018 дата публикации

SYSTEM AND METHOD FOR VERIFYING GENERAL PURPOSE INPUT OUTPUT FUNCTIONS

Номер: US20180137021A1
Автор: CHEN CIA-YUN
Принадлежит:

A system to verify the correct functioning of general purpose input output (GPIO) pins includes a main device and a processing chip. The main device stores a processing program, an executing program, and at least one predetermined value in relation to at least one GPIO parameter. The executing program is copied to a detection device and the processing program generates a mirror image document after compiling. The mirror image document is burned into the processing chip which is executed after the detection device is started. The executing program is executed as the processing chip is started. The executing program reads at least one actual GPIO value and verifies whether the at least one GPIO of the detection device is failed upon non-matching of the predetermined parametric value with the at least one GPIO actual value. A method to verify the correct functioning of the GPIO pins is also provided. 1. A system for verifying general purpose input output (GPIO) functions comprising:a processing chip defined on a detection device; and a processing program to generate a mirror image document after compiling;', 'an executing program configured to be copied to the detection device; and', 'at least one predetermined value in relation to at least one GPIO parameter;, 'a main device storingwherein the mirror image document is burned into the processing chip;wherein the processing chip is started after the detection device is started;wherein the executing program is executed after the processing chip is started;wherein the executing program is configured to read at least one actual value corresponding to the at least one GPIO parameter of the detection device after being executed;wherein the at least one predetermined value is compared with the at least one actual value to verify whether the at least one GPIO parameter of the detection device is failed.2. The system of claim 1 , wherein at least one predetermined value in relation to at least one GPIO parameter is stored in a ...

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Номер записи: 52
08-09-2022 дата публикации

Touch control substrate, test method thereof, and manufacturing method of touch control screen

Номер: US20220283687A1
Автор: Aimin Dai
Принадлежит: TCL China Star Optoelectronics Technology Co Ltd

The present application provides a touch control substrate, a test method thereof, and a manufacturing method of a touch control screen. The touch control substrate includes touch control electrodes, test terminals, and electrical connection members. Each of the test terminals is connected to two adjacent touch control electrodes. Each of the electrical connection members corresponds to each of the touch control electrodes. The touch control electrodes are electrically connected to the test terminals through the electrical connection members. The touch control electrodes form a series circuit through the corresponding electrical connection members and the corresponding test terminals.

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Номер записи: 53
30-04-2020 дата публикации

SAS Connector Conduction Detecting System And Method Thereof

Номер: US20200132768A1
Автор: Sang Yuan
Принадлежит:

A SAS connector conduction detecting system and a method thereof are provided. By a SAS connector on a detection circuit board and a mainboard SAS connector of a mainboard are connected to each other, and the detection circuit board and a test access port controller are connected in series with each other through a JTAG input connector and a JTAG output connector on the detection circuit board. The detection circuit board can provide the conduction detection for one mainboard SAS connector of the mainboard, thereby achieving the technical effect of improving the detection efficiency of the SAS connector. 1. A SAS connector conduction detecting system , comprising: a plurality of mainboard SAS connectors; and', 'a boundary scan chip; wherein the boundary scan chip is electrically connected to the mainboard SAS connectors respectively;, 'a mainboard, comprising the SAS connector is electrically connected to the CPLD, the first JTAG chip, the second JTAG chip; the ADC, and the voltage regulator respectively;', 'the JTAG input connector is electrically connected to the JTAG output connector; the buffer, and the first multiplexer respectively;', 'the JTAG output connector is electrically connected to the JTAG input connector and the first multiplexer respectively;', 'the buffer is electrically connected to the JTAG input connector, the JTAG output connector; and the CPLD respectively;', 'the CPLD is electrically connected to the buffer, the first JTAG chip, the SAS connector; and the microprocessor respectively;', 'the first JTAG chip is electrically connected to the SAS connector, the CPLD, and the second JTAG chip respectively;', 'the second JTAG chip is electrically connected to the SAS connector and the first JTAG chip respectively;', 'the first multiplexer is electrically connected to the JTAG input connector, the JTAG output connector, the CPLD; and the microprocessor respectively;', 'the second multiplexer is electrically connected to the microprocessor, the ...

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Номер записи: 54
26-05-2016 дата публикации

DETECTING AND SPARING OF OPTICAL PCIE CABLE CHANNEL ATTACHED IO DRAWER

Номер: US20160147606A1
Автор: Arroyo Jesse P., Bauman Ellen M., Block Timothy R., Engel Christopher J., Naderi Kaveh, Nordstrom Gregory M., Pross Harald, Sand Thomas R.
Принадлежит:

A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel. 1. A method for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer in a computer system , comprising:providing system firmware for implementing health check functions and detecting state and sparing functions;providing one or more optical cables coupled between host bridge and an PCIE enclosure, each optical cable including one or more spare optical channels;identifying a failed optical channel and rerouting the failed optical channel to a spare optical channel.2. The method as recited in claim 1 , includes providing each optical cable with a plurality of optical channels for PCIE bidirectional traffic claim 1 , at least one optical channel for sideband communications and the one or more spare optical channels.3. The method as recited in claim 1 , includes providing lane sparing hardware on both ends of each optical cable.4. The method as recited in claim 3 , includes providing lane sparing hardware with a set of PCIE lane multiplexers and a lane sparing hardware control device used to control the set of PCIE lane multiplexers.5. The method as recited in claim 4 , includes programming the lane sparing hardware control device by system firmware for changing input to output mapping of the PCIE lane multiplexers.6. The method as recited in claim 5 , includes controlling the lane sparing hardware control device using sideband signals and ...

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Номер записи: 55
04-06-2015 дата публикации

PROCESSING INPUT/OUTPUT REQUESTS USING PROXY AND OWNER STORAGE SYSTEMS

Номер: US20150154128A1
Автор: LI-ON Oren, NISSAN-MESSING Orit, PEREK Eyal
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A first storage system is configured as a proxy for a logical volume stored on a second storage system. A probe request verifying availability of the logical volume is conveyed to an identified port, and upon receiving a response from a second storage system verifying the availability of the logical volume for an I/O request, the I/O request is conveyed to the identified port, a result of the I/O request is received from the identified port, the result is conveyed to the host computer. 1. A method for configuring a first storage system as a proxy for a logical volume stored on a second storage system , comprising:conveying, to an identified port, a probe request to verify an availability of the logical volume for an input/output (I/O) request; andupon receiving a response from a second storage system verifying the availability of the logical volume for the I/O request, conveying the I/O request to the identified port, receiving a result of the I/O request from the identified port, and conveying the result to a host computer.2. The method of claim 1 , further comprising receiving claim 1 , by the first storage system claim 1 , the I/O request from the host computer for the logical volume claim 1 , wherein the host computer identifies the port on the second storage system for the I/O request.3. The method according to claim 1 , further including claim 1 , 'wherein the I/O request is selected from a list comprising a request to read data from the logical volume and a request to write data to the logical volume.', 'upon receiving a response from the second storage system verifying the availability of the logical volume for the I/O request, conveying the I/O request to the identified port, receiving a result of the I/O request from the identified port, and conveying the result to the host computer;'}4. The method according to claim 1 , and comprising receiving claim 1 , from the second storage system claim 1 , a response to the probe request indicating a non-availability ...

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Номер записи: 56
15-09-2022 дата публикации

METHOD AND DEVICE FOR POSITIONING FAULTY DISK

Номер: US20220291991A1
Автор: LIU Yuxue
Принадлежит:

Disclosed are a method and device for positioning a faulty disk. The method comprises: in response to detecting that a first disk is faulted, determining positioning information of the first disk, the positioning information comprising a logic Enclosure Identity (EID) and a logic Slot Identity (SID); and positioning the first disk according to the EID and SID of the first disk. 1. A method for positioning a faulty disk , comprising:in response to detecting that a first disk is faulted, determining positioning information of the first disk, the positioning information comprising a logic Enclosure Identity (EID) and a logic Slot Identity (SID);and positioning the first disk according to the EID and SID of the first disk.2. The method of claim 1 , wherein the determining positioning information of the first disk comprises:identifying a management mode of the first disk, which is Serial Attached SCSI (SAS) controller management or Redundant Arrays of Independent Drives (RAID) management; anddetermining positioning information of the first disk according to the management mode of the first disk.3. The method of claim 1 , wherein claim 1 , in response to the management mode of the first disk being SAS controller management claim 1 , the determining positioning information of the first disk according to the management mode of the first disk comprises:determining Small Computer System Interface (SCSI) bus information of the first disk according to the name of the first disk; andacquiring the EID and SID of the first disk mapped in a corresponding sysfs according to the SCSI bus information of the first disk.4. The method of claim 3 , after acquiring the EID and SID of the first disk mapped in a corresponding sysfs according to the SCSI bus information of the first disk claim 3 , further comprising:verifying whether the SCSI bus information of the first disk presents and whether the SID of the first disk is within a scope of jurisdiction of a logic enclosure corresponding to ...

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Номер записи: 57
31-05-2018 дата публикации

INPUT DEVICE TEST SYSTEM AND METHOD THEREOF

Номер: US20180150370A1
Автор: Chang Pei-Ming
Принадлежит:

The present invention provides an input device test system, configured to test an input device having a plurality of functional elements. The input device test system includes: a test host, configured to execute a test program and a message interception program, and output a test message by means of the test program; and a test platform, configured to receive the test message and operate the input device according to the test message, where the input device outputs a response message to the test host in response to the operation, where the message interception program is used to intercept the response message and convert the response message into at least one code, and the test program determines whether the at least one code is consistent with the test message. 1. An input device test system , configured to test an input device having a plurality of functional elements , wherein the input device test system comprises:a test host, configured to execute a test program and a message interception program, and output a test message by means of the test program; anda test platform, configured to receive the test message and operate the input device according to the test message, wherein the input device outputs a response message to the test host in response to the operation, whereinthe message interception program is used to intercept the response message and convert the response message into at least one code, and the test program determines whether the at least one code is consistent with the test message.2. The input device test system according to claim 1 , wherein the input device is a mouse or a touchpad.3. The input device test system according to claim 1 , wherein the functional elements comprise: a left key claim 1 , a right key claim 1 , a capacitance detector claim 1 , or an optical detector.4. The input device test system according to claim 1 , wherein the test host comprises a screen claim 1 , which is configured to display a human-machine interface of the ...

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Номер записи: 58
01-06-2017 дата публикации

Switching Allocation of Computer Bus Lanes

Номер: US20170153949A1
Автор: Garibay Victor A., Hurlimann Daniel E., Mehta Chetan, Pizzano Fernando, Sand Thomas R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter. 1. A system comprising:a processor in communication with memory;a module comprising a multiplexer in communication with the processor, and two or more host bridges in communication with the multiplexer; anda plurality of connectors in communication with respective host bridges, including a first connector in communication with a first host bridge and a second connector in communication with a second host bridge, wherein each host bridge is positioned as an interface between its respective connector and the multiplexer, and wherein each connector is configured to receive a respective adapter including the first connector in receipt of a first primary adapter and the second connector in receipt of a second primary adapter; detect a presence of two or more adapters present at boot-time, including the first primary adapter and the second primary adapter;', 'dynamically control an initial system lane allocation, by the multiplexer, among the two or more detected adapters, wherein the initial system lane allocation maximizes adapter functionality, the allocation including an assignment of at least one system lane to the first primary adapter; and', 'in response to detection of a failure of the first primary adapter after the initial system lane allocation, the multiplexer to dynamically transfer at least one ...

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Номер записи: 59
14-05-2020 дата публикации

METHOD, COMPUTER APPARATUS, AND USER INTERFACE FOR PERFORMING AUTOMATIC TEST UPON STORAGE DEVICES

Номер: US20200151072A1
Автор: Chou Li-Ling, Yang Shang-Ta
Принадлежит:

A method of automatic test upon storage devices, connected to user interface of computer apparatus via external connection port(s), includes: providing user interface which can be controlled by user to input at least one set of setting parameters for execution of testing task of at least one test software tool; automatically configuring information of at least one field for the execution of the testing task according to the at least one set of setting parameters; automatically executing the at least one test software tool to perform the testing task upon the multiple storage devices according to the information of the at least one field; and automatically storing result of the testing task and displaying the result on the user interface for user. 1. A method for performing automatic test upon multiple solid-state drive (SSD) storage devices to be tested , the multiple SSD storage devices to be connected to a computer apparatus via a first external connection port interface and at least one second external connection port interface , the first external connection port interface being different from the at least one second external connection port interface , the computer apparatus including a user interface , the automatic test is controlled by the computer apparatus to sequentially or simultaneously send multiple test signals to multiple flash memory controllers of the multiple SSD storage devices which are connected to the first external connection port interface and the at least one second external connection port interface via the first external connection port interface and the at least one second external connection port interface for performing corresponding testing , the multiple flash memory controllers being arranged for performing the corresponding testing upon multiple flash memory chips of the multiple SSD storage devices according to the multiple test signals received from the computer apparatus so as to respectively obtain and record multiple test ...

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Номер записи: 60
23-05-2019 дата публикации

Methods and Systems for Monitoring the Integrity of a GPU

Номер: US20190155711A1
Автор: Fabius Aidan, Malnar Tomislav, McCormick John, Ramkissoon Sherwyn R., Szober Gregory J., Viggers Stephen, Wenger Kenneth
Принадлежит: Channel One Holdings Inc.

Methods and systems for monitoring the integrity of a graphics processing unit (GPU) are provided. The method comprises the steps of determining a known-good result associated with an operation of the GPU, and generating a test image comprising a test subject using the operation of the GPU, such that the test subject is associated with the known-good result. The test image is written to video memory, and the known-good result is written to system memory. Subsequently, the test subject from the test image is transfered from video memory to system memory. The test subject in the system memory is compared with the known-good result in system memory. If the test subject does not match the known-good result, then a conclusion is drawn that the integrity of the GPU has been compromised. 1. A method for monitoring integrity of a graphics processing unit (GPU) , comprising:a) determining a known-good result associated with an operation of the GPU;b) generating a test image comprising a test subject using the operation of the GPU, the test subject being associated with the known-good result;c) writing the test image to a video memory and writing the known-good result to a system memory;d) writing the test subject from the test image in video memory to the system memory;e) comparing the test subject in the system memory with the known-good result in the system memory; andf) writing a flag to system memory indicating failure if comparing the test subject with the known-good result indicates a difference between the test subject and the known-good result.2. The method of claim 1 , wherein the test subject comprises pixel data pertaining to the test image and the known-good result comprises a model image.3. The method of claim 1 , wherein the test subject comprises a cyclic-redundancy check (CRC) value based on the test image claim 1 , and the known-good result comprises an expected value for the CRC value.4. The method of claim 1 , wherein the test subject comprises a sequence ...

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Номер записи: 61
24-06-2021 дата публикации

INTELLIGENT MEMORY DEVICE TEST RESOURCE

Номер: US20210191832A1
Автор: Hamor Gary D.
Принадлежит:

A memory device test resource includes a dedicated processing device for the memory device test resource, the dedicated processing device configured to facilitate testing of a memory device of a memory sub-system coupled to the memory device test resource. The memory device test resource further includes a memory sub-system interface port coupled to the dedicated processing device and configured to couple the memory device test resource to the processing device, a test condition component coupled to the dedicated processing device and configured to generate a test condition at the memory device test resource, and a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resource. 1. A memory device test resource comprising:a dedicated processing device for the memory device test resource, the dedicated processing device configured to facilitate testing of a memory device of a memory sub-system coupled to the memory device test resource;a memory sub-system interface port coupled to the dedicated processing device and configured to couple the memory device test resource to the memory sub-system;a test condition component coupled to the dedicated processing device and configured to generate a test condition at the memory device test resource;a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resource.2. The memory device test resource of claim 1 , wherein the dedicated processing device is configured to perform operations comprising:detecting that the memory sub-system has coupled to the memory device test resource;identifying a test to be performed for the memory device of the memory sub-system, wherein the test comprises one or more test instructions to be executed in performance of the test; andcausing the one or more test instructions to be transmitted to the memory ...

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Номер записи: 62
15-06-2017 дата публикации

System and method for simulating human manual input for devices using capacitive touchscreens

Номер: US20170168622A1
Автор: Dan Kikinis
Принадлежит: Future Dial Inc

Disclosed are systems, methods, and devices for simulating human manual input for devices using capacitive touchscreens. In one embodiment, the system comprises a test fixture, wherein the test fixture comprises a matrix of tubes, each tube being coated with a conductive coating; and a camera located under the matrix and configured to record the capacitive touchscreen of the device under test. The system further includes a tablet to receive images from the camera and display a visual representation of the capacitive touchscreen of the device under test, wherein the tablet is configured to receive a plurality of touch events; update the visual representation of the capacitive touchscreen of the device under test in response to the plurality of touch events; and generate a simulation of touch events, the simulation representing interaction with the device under test. The system further includes a workstation communicatively coupled to the tablet and configured to receive the simulation from the tablet device; and transmit the simulation to the test fixture to enable the execution of the simulation on one or more additional devices under test.

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Номер записи: 63
01-07-2021 дата публикации

Touch Screen Testing Platform for Engaging a Dynamically Positioned Target Feature

Номер: US20210197392A1
Автор: Jenkinson David Ross
Принадлежит:

A touch screen testing platform may be used to engage a dynamically positioned target feature being displayed on a touch screen enabled device during a testing protocol. The platform may record imagery displayed by the touch screen device and then analyze the imagery to locate the target feature within a reference coordinate system. The platform may recognize that the target feature is missing from the imagery and respond by causing the touch screen device to scroll through a command menu and/or toggle through virtual screens. Once located, the platform may instruct a robotic device tester to select the target feature by contacting the touch screen at the identified location using a conductive tip designed to simulate a user's fingertip. Prior to running a test, the camera may be focused to a point that is offset from the display screen of the touch screen device. 1. A system for testing a touch screen device , the system comprising:a camera configured to record one or more images of a touch screen of the touch screen device;a robot configured to move a tip to contact the touch screen; and receiving, from the camera, a first image of the touch screen;', 'determining, based at least in part on the first image, an absence of a target feature in the first image;', 'in response to the determining the absence of the target feature, executing an instruction to cause the robot to provide the touch screen device with a first input;', 'receiving, from the camera, a second image of the touch screen;', 'determining, based at least in part on the second image, a coordinate location of the target feature displayed on the touch screen; and', 'causing the robot to provide a second input to the touch screen device by moving the tip to contact the touch screen at the coordinate location to engage with the target feature on the touch screen, the second input to the touch screen device to simulate a user selection of the target feature., 'a controller configured to control movement of ...

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Номер записи: 64
23-06-2016 дата публикации

Matrix circuit detecting failure location in common signal

Номер: US20160178689A1
Автор: Hiroshi Okita
Принадлежит: FANUC Corp

A matrix circuit includes, besides a plurality of common signal lines and a plurality of data signal lines arranged in a matrix, a plurality of monitoring signal lines that allow states of the common signal lines to be monitored. Inputs to the monitoring signal lines during one scan of the common signal lines are stored such that a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines is detected and a location of the faulty common signal line is identified based on the stored inputs to the monitoring signal lines.

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Номер записи: 65
01-07-2021 дата публикации

Method, device and terminal for testing memory chip

Номер: US20210200460A1
Автор: Ruei-Yuan GUO, Tianchen LU
Принадлежит: Changxin Memory Technologies Inc

The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.

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Номер записи: 66
21-06-2018 дата публикации

FAX FUNCTION DIAGNOSIS METHOD, AND APPARATUS FOR PERFORMING THE METHOD

Номер: US20180176394A1
Автор: HAN Chang-min, HAN Ho-sung, SUNG In-soo, WON Cheol-yon
Принадлежит:

A fax function diagnosis method and an apparatus for performing the method are provided. The fax function diagnosis method includes receiving a diagnosis request to diagnose a fax function of an image forming apparatus, diagnosing the fax function of the image forming apparatus by transmitting or receiving a test page, and performing an operation based on a result of the diagnosing. 1. A fax function diagnosis method comprising:receiving a diagnosis request to diagnose a fax function of an image forming apparatus;diagnosing the fax function of the image forming apparatus by transmitting or receiving a test page; andperforming an operation based on a result of the diagnosing.2. The fax function diagnosis method of claim 1 , wherein the receiving of the diagnosis request comprises receiving the diagnosis request from the image forming apparatus or a mobile device via an email or an application.3. The fax function diagnosis method of claim 1 , wherein the performing of the operation based on the diagnosis result comprises transmitting the diagnosis result to the image forming apparatus if the diagnosis result indicates that a problem solvable by the image forming apparatus directly changing settings has occurred.4. The fax function diagnosis method of claim 1 , wherein the performing of the operation based on the diagnosis result comprises transmitting the diagnosis result to a mobile device of a service engineer if the diagnosis result indicates that a problem solvable by the service engineer has occurred.5. The fax function diagnosis method of claim 1 , wherein the performing of the operation based on the diagnosis result comprises transmitting a problem solution request to a service provider of a public switched telephone network (PSTN) if the diagnosis result indicates that a problem has occurred in the PSTN.6. The fax function diagnosis method of claim 1 , wherein the performing of the operation based on the diagnosis result comprises transmitting the diagnosis ...

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Номер записи: 67
13-06-2019 дата публикации

Method and apparatus for securing communication of instructions to manage antenna power output

Номер: US20190179385A1
Автор: Adolfo S. Montero, Benny J. Bologna, Kamal J. Koshy
Принадлежит: Dell Products LP

A method and an information handling system comprising a processor executing instructions of a basic input/output system (BIOS) module operatively connected to a network interface device standard absorption rate (SAR) antenna power control register via a bus interface and the processor executing code instructions for a power management command for altering a power level of a transmission by an operably connected transmitting antenna according to SAR requirements in response to detection at a sensor indicating a change to transmission power levels is required, where the bus interface is secured by implementing a challenge/response cryptographic system between the BIOS module and the network interface device before allowing the read/write command to access the standard absorption rate control register.

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Номер записи: 68
15-07-2021 дата публикации

DIAGNOSTIC SYSTEM

Номер: US20210216429A1
Автор: Chang Wei-Hsian, Chang Yu-Chieh, CHIANG Kun-Hsin, Hsieh Wen-Yen, Huang Hsin-Hui, HUANG Ming-Yi, Kuo Chih-Wei, Liao Tang-Hui
Принадлежит:

A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.

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Номер записи: 69
25-09-2014 дата публикации

Keyboard testing machine

Номер: US20140283629A1
Автор: Chin-Shun LAI, Hung-Wei Wang, Lung-Chiang CHU
Принадлежит: QUANTA COMPUTER INC

A keyboard testing machine for testing a keyboard of an electronic apparatus is provided. The keyboard testing machine includes a rack, a fixing base, and a pressing module. The fixing base is operatively connected to the rack and located over the electronic apparatus. The pressing module is located over the keyboard and includes a drive shaft, a rotating member, and a pressing assembly. The drive shaft is rotatably disposed on the fixing base. The rotating member is sleeved onto the drive shaft and has a cam portion. The pressing assembly is operatively connected to the fixing base and the cam portion. When the drive shaft rotates together with the rotating member, the cam portion drives the pressing assembly to linearly move relative to the fixing base, so as to make the pressing assembly cyclically press the keyboard.

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Номер записи: 70
20-06-2019 дата публикации

Method, Apparatus and Electronic Device For Read/Write Speed Testing

Номер: US20190189238A1
Автор: Kun Zhao, Zhenbei YU
Принадлежит: Zhuhai Juntian Electronic Technology Co Ltd

The present invention provides a method for read/write speed testing, comprising: obtaining a test speed of reading data from or writing data to each of a plurality of memories, the plurality of memories including a random access memory and at least one buffer memory associated with the random access memory; and determining an actual speed of reading data from or writing data to the random access memory according to the test speed of reading data from or writing data to the each memory. Embodiments of the present invention further disclose an apparatus for read/write speed testing and electronic device. With the embodiments of the present invention, the read/write speed of the random access memory can be tested more accurately.

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Номер записи: 71
22-07-2021 дата публикации

PERSISTENCE POINTS BASED COVERAGE MECHANISM FOR FLOW TESTING IN HIGH-PERFORMANCE STORAGE SYSTEMS

Номер: US20210224171A1
Автор: Kamran Lior, Soukhman Alex
Принадлежит:

A processing device maintains a data structure for a set of process flows executing on one or more processing cores of a storage system. The data structure comprises entries identifying particular execution instances of one or more persistence point functions, each modifying persistent state, with the execution instances having been designated as tested in conjunction with testing of one or more process flows of the set of process flows. The processing device detects an execution instance of a persistence point function of a given one of the process flows, determines whether or not the detected execution instance of the persistence point function has a corresponding entry in the data structure, and responsive to the detected execution instance of the persistence point function not having a corresponding entry in the data structure, initiates a test of the given process flow that includes the detected execution instance of the persistence point function. 1. An apparatus comprising:at least one processing device comprising a processor coupled to a memory;said at least processing device being configured:to maintain a data structure for a set of process flows executing on one or more processing cores of a storage system, the data structure comprising entries identifying particular execution instances of one or more persistence point functions, the execution instances having been designated as tested in conjunction with testing of one or more process flows of the set of process flows, each such persistence point function performing at least one operation that modifies persistent storage of the storage system;to detect an execution instance of a persistence point function of a given one of the process flows;to determine whether or not the detected execution instance of the persistence point function has a corresponding entry in the data structure; andresponsive to the detected execution instance of the persistence point function not having a corresponding entry in the ...

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Номер записи: 72
11-06-2020 дата публикации

FORMAL VERIFICATION TOOL TO VERIFY HARDWARE DESIGN OF MEMORY UNIT

Номер: US20200185051A1
Автор: Darbari Ashish, Singleton Iain
Принадлежит:

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read. 1. A formal verification tool configured to verify operation of an instantiation of a hardware unit for storing data defined in a hardware design , the formal verification tool comprising:monitoring logic configured to monitor one or more control signals of the instantiation of the hardware unit to detect writes to a symbolic address of the instantiation of the hardware unit and reads of the symbolic address of the instantiation of the hardware unit, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the hardware unit which causes the formal verification tool to assess each of the possible address values; andassertion verification logic configured to verify a formal assertion that establishes that when the monitoring logic detects a read of the symbolic address that occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address.2. The formal verification tool of claim 1 , further comprising a seen symbolic write register and wherein the monitoring logic is further configured to claim 1 , in response to detecting a write to the ...

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Номер записи: 73
25-09-2014 дата публикации

APPARATUS AND METHOD FOR SPECIFYING A FAILURE PART IN A COMMUNICATION NETWORK

Номер: US20140289560A1
Автор: NISHI Tetsuya
Принадлежит: FUJITSU LIMITED

A monitoring device specifies a failure part in a first device group including a plurality of information processing devices and a relay device relaying access of the plurality of information processing devices. The monitoring device includes a determination unit and a test controller. The determination unit determines whether one or more destination addresses of information transmitted from the relay device to outside of the first device group, include an address of a storage device included in a second device group connected to the first device group through the relay device, where the storage device is a destination of access of at least one of the plurality of information processing devices. The test controller causes one of the plurality of information processing devices to execute a communication test with respect to the address of the storage device. 1. An apparatus for specifying a failure part in a first device group including a plurality of information processing devices and a relay device relaying access of the plurality of information processing devices , the apparatus comprising:a determination unit configured to determine whether one or more destination addresses of information transmitted from the relay device to outside of the first device group, include a first address assigned to a storage device included in a second device group, the second device group being connected to the first device group through the relay device, the storage device being a destination of access of at least one of the plurality of information processing devices; anda test controller configured to cause one of the plurality of information processing devices to execute a communication test with respect to the first address of the storage device.2. The apparatus of claim 1 , whereinthe test controller causes a controller provided for the one information processing device and configured to control one or more virtual machines, to execute a communication test with respect to the ...

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Номер записи: 74
13-07-2017 дата публикации

Universal Smart Connection Pad

Номер: US20170199799A1
Автор: McWethy Chris
Принадлежит: BBY SOLUTIONS, INC.

The present invention is a pad for connecting a host device to a slave device through a slave adapter. The host may provide services to the slave, including power and data connections. Pins in the pad magnetically align the slave adapter. The host and slave may collaborate on which pins are assigned to connections. The system handles various usage modifications including, for example, dislocation of the slave adapter, and changes in pin assignments. 1. A system , comprising:a) a processing system that includes a processor; [ (A) are arranged equally-spaced in a grid having a plurality of rows and a plurality of columns,', '(B) have magnetic polarities that alternate within a row in the plurality of rows, and alternate within a column in the plurality of columns,', '(C) are equally-spaced within a row in the plurality of rows, and equally-spaced within a column in the plurality of column, and', '(D) through a first subset of which the connection pad can electronically connect to a first slave device and communicate electronically with the first slave device,, '(i) a set of pins, which'}, '(ii) a first hardware interface through which the pad can electrically connect to a host device and communicate electronically with the host device, and, 'b) a connection pad, which includes'}c) the host device, which includes a second hardware interface through which the host can electrically connect to the connection pad and communicate electronically with the connection pad, (i) a power module, under control of the processing system, whereby the host provides power through a first subset of pins in the set of pins, to a first external slave device,', '(ii) a mating module, under control of the processing system, whereby the host receives identification information from the first slave device and establishes and maintains electronic data communication with the first slave device through a second subset of pins in the set of pins, and the first and the second hardware interfaces, ...

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Номер записи: 75
30-07-2015 дата публикации

Touch panel inspecting apparatus

Номер: US20150212625A1
Автор: Koji Iwami, Koji Sakamoto, Osamu Hikita, Shigeki Fujita, Toshihide Matsukawa
Принадлежит: Nidec Read Corp

A touch panel inspecting apparatus includes a workpiece holder, a pseudo finger, an X-Y movement mechanism, a memory part, an electric pneumatic regulator, and a panel signal acquiring part. The workpiece holder allows a touch panel, which is an inspection target, to be set thereon. The pseudo finger is contactable with the touch panel set on the workpiece holder. The X-Y movement mechanism moves the pseudo finger relative to the touch panel. The memory part stores therein a set value of pressing force of the pseudo finger, in a changeable manner. The electric pneumatic regulator regulates the pressing force to bring the pseudo finger into contact with the touch panel, based on the set value stored in the memory part. The panel signal acquiring part acquires an electric signal output from the touch panel.

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Номер записи: 76
27-06-2019 дата публикации

STORAGE SYSTEM AND BACKEND CONSTRUCTION METHOD FOR STORAGE SYSTEM

Номер: US20190197000A1
Автор: KUROKAWA Midori, YAMASAKI Yuta
Принадлежит:

Provided is a storage system in which a switch is logically divided into a plurality of partitions including: a plurality of first partitions which are coupled to a plurality of master devices of a processor unit and to which none of storage devices are coupled; and one or more second partitions which are coupled to a plurality of storage devices and which are not coupled to the processor unit. The switch has an address conversion function which is a function for enabling transfer between different partitions. A virtual master device is provided to each of the second partitions. With respect to each of the second partitions, the virtual master device in the second partition executes initial setting with respect to each of all storage devices coupled to the second partition. 1. A storage system comprising:a switch that relays communication according to a communication interface in which the number of master devices that can be present in the same partition is defined;a plurality of storage devices coupled to the switch;a memory unit including one or more memories; anda processor unit which is one or more processors coupled to the memory unit and the switch and has a plurality of master devices, whereinthe switch is logically partitioned into a plurality of partitions,the plurality of partitions include a plurality of first partitions and one or more second partitions,the plurality of master devices of the processor unit are coupled to the plurality of first partitions via a plurality of paths, and the plurality of storage devices are not coupled to the plurality of first partitions,the plurality of storage devices are coupled to the one or more second partitions, and the processor unit is not coupled to the one or more second partitions,the switch has an address conversion function which is a function of enabling transfer between different partitions,a virtual master device is provided in each of the one or more second partitions, andthe virtual master device in each ...

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Номер записи: 77
21-07-2016 дата публикации

ADAPTIVE DEVICE-INITIATED POLLING

Номер: US20160212035A1
Автор: Canosa John Thomas, Taylor John Louis
Принадлежит:

A method includes periodically sending a polling call to an enterprise system outside the firewall at a first polling rate during normal operating conditions, monitoring for a fault condition, periodically sending polling calls to the device outside the firewall at a second polling rate when a fault condition is detected, the second polling rate being higher than the first polling rate. The second polling rate is used as result of a fault condition. The method also includes sending a problem report with the polling calls when the fault condition is detected. 1. A method performed by a processor associated with a device , the method comprising:sending first polling calls from the processor to an enterprise system over a computer network, the enterprise system being on a different side of a security system on the computer network than the processor and the device;detecting a fault condition at the device, the fault condition being triggered by a deviation from a predefined operation of the device or by an input to the device from an external source;in response to detecting the fault condition, sending second polling calls to the enterprise system, the second polling calls utilizing more bandwidth on the network than the first polling calls, the second polling calls including information about the fault condition;the second polling calls opening a portal through the security system, through which portal data is passable by the enterprise system to the processor;following at least some of the second polling calls, determining that the fault condition has been addressed; andin response to determining that the fault condition has been addressed, resuming the first polling calls from the processor to the enterprise system.2. The method of claim 1 , wherein the first polling calls are sent at a first rate claim 1 , the second polling calls are sent at a second rate claim 1 , and the second rate is greater than the first rate.3. The method of claim 1 , wherein the ...

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Номер записи: 78
04-07-2019 дата публикации

S.M.A.R.T. THRESHOLD OPTIMIZATION METHOD USED FOR DISK FAILURE DETECTION

Номер: US20190205193A1
Автор: Jin Hai, Wu Song, XIONG Zhuang
Принадлежит:

An S.M.A.R.T. threshold optimization method used for disk failure detection includes the steps of: analyzing S.M.A.R.T. attributes based on correlation between S.M.A.R.T. attribute information about plural failed and non-failed disks and failure information and sieving out weakly correlated attributes and/or strongly correlated attributes; and setting threshold intervals, multivariate thresholds and/or native thresholds corresponding to the S.M.A.R.T. attributes based on distribution patterns of the strongly or weakly correlated attributes. As compared to reactive fault tolerance, the disclosed method has no negative effects on reading and writing performance of disks and performance of storage systems as a whole. As compared to the known methods that use native disk S.M.A.R.T. thresholds, the disclosed method significantly improves disk failure detection rate with a low false alarm rate. As compared to disk failure forecast based on machine learning algorithm, the disclosed method has good interpretability and allows easy adjustment of its forecast performance. 1. A self monitoring analysis and reporting technology (S.M.A.R.T.) threshold optimization method used for disk failure detection , comprising the steps of:collecting S.M.A.R.T. attributes associated with a plurality of computer disk drives;analyzing the collected S.M.A.R.T. attributes based on correlation between S.M.A.R.T. attribute information about plural failed and non-failed disks and failure information;seperating weakly correlated attributes and strongly correlated attributes;setting within a computer having a disk drive at least one of threshold intervals, multivariate thresholds and/or native thresholds corresponding to the S.M.A.R.T. attributes based on distribution patterns of the strongly correlated attributes and weakly correlated attributes; andchanging the disk drive within the computer when one or more of the settings of at least one of threshold intervals, multivariate thresholds and/or ...

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Номер записи: 79
12-08-2021 дата публикации

DEVICE AND METHOD FOR VERIFYING A COMPONENT OF A STORAGE DEVICE

Номер: US20210248049A1
Автор: Olarig Sompong Paul, YAO Xuebin
Принадлежит:

A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result. 1. A storage device configured for hardware verification comprising:a first hardware component comprising a connector and a first verification logic, the first validation logic configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion; anda second hardware component coupled to the first hardware component via the connector, the second hardware component comprising a second validation logic, the second validation logic configured to monitor and receive the first signal via the connector,wherein in response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result,wherein the storage device is configured to take an action in response to the result.2. The device of claim 1 , wherein the first hardware component includes at least one of a field gate programmable array (FPGA) or an application-specific integrated circuit claim 1 , and the second hardware component includes non-volatile memory.3. The device of claim 1 , wherein the expected signal is associated with ...

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Номер записи: 80
16-07-2020 дата публикации

Display module test platform

Номер: US20200225296A1
Автор: FENG CHEN, Yuqing Wang
Принадлежит: Kunshan Govisionox Optoelectronics Co Ltd

The present application relates to the field of display technology, and discloses a display module test platform, including a core processor. The core processor is capable of supporting installation of a terminal operating system. A display output terminal of the core processor is connected to a display module to be tested. The display module to be tested includes a touch structure. The touch structure and the core processor communicate with each other via an Inter-Integrated Circuit (I2C) bus.

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Номер записи: 81
01-08-2019 дата публикации

SYSTEM AND METHOD FOR OBJECTIVELY MEASURING USER EXPERIENCE OF TOUCH SCREEN BASED DEVICES

Номер: US20190235655A1
Автор: Matthews Joshua Scott, TEITELBAUM David Michael, TSENG Benjamin Kou-An
Принадлежит: APKUDO, LLC

In certain embodiments, latency measurement related to touch screen response may be facilitated. In some embodiments, a robotic member may be moved to perform a physical contact with a touch screen of a device. Frame change rates of the touch screen may be monitored. A response end time of a response depicted on the touch screen may be determined based on the monitored frame change rates of the touch screen, where the touch-screen-depicted response is a response to. A latency of the touch screen response to the first contact may be determined based on a contact time of the physical contact and the response end time. 1. A method of measuring latency related to touch screen response , the method comprising:monitoring, by one or more processors, frame change rates of a touch screen of a device;determining, by one or more processors, based on the monitored frame change rates of the touch screen, a response end time of a response depicted on the touch screen, the touch-screen-depicted response being a response to a physical contact with the touch screen; anddetermining, by one or more processors, a latency of the touch screen response to the first contact based on a contact time of the physical contact and the response end time.2. The method of claim 1 , further comprising:causing, by one or more processors, a robotic member to move to perform the physical contact with the touch screen.3. The method of claim 1 , further comprising:generating, by a camera, a video of an interaction with the touch screen of the device, wherein the interaction comprises (i) the physical contact with the touch screen and (ii) the touch-screen-depicted response of the touch screen to the physical contact; anddetermining the contact time of the physical contact based on the interaction video,wherein monitoring the frame change rates comprises monitoring, the frame change rates of the touch screen based on the interaction video.4. The method of claim 3 , wherein the camera has a recording rate ...

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Номер записи: 82
01-08-2019 дата публикации

DEFECT DETECTION METHOD FOR MULTILAYER DAISY CHAIN STRUCTURE AND SYSTEM USING THE SAME

Номер: US20190236240A1
Автор: Guo Mei-Hui, Huang Yu-Jung, Pan Chung-Long
Принадлежит: I-SHOU UNIVERSITY

A defect detection method for a multilayer daisy chain structure, including: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that the multilayer daisy chain has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values. 1. A defect detection method for a multilayer daisy chain structure , comprising:generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure;generating a group of training samples for each of the physicals models to form a training sample group and dividing the training sample group into a training set and a testing set;obtaining a group of scattering parameter values corresponding to the training set via the training set;generating a classifier model via the group of scattering parameter values;measuring an error value of the classifier model using the test set and using the classifier model as a defect model of the at least one defect type based on the error value; andinputting, to the classifier model, at least one scattering parameter value of the multilayer daisy chain structure to be detected so as to determine that the multilayer daisy chain structure has a determined defect corresponding to the at least one defect type, whereinthe multilayer has been having the determined defect corresponding to the at least one defect type since being manufactured; andall steps of the detect ...

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Номер записи: 83
07-09-2017 дата публикации

Self-diagnosis of device drive-detected errors and automatic diagnostic data collection

Номер: US20170255535A1
Автор: Nathan Allan Rabe, Thomas Freeman
Принадлежит: Western Digital Technologies Inc

A self-diagnostic device driver includes a memory that stores machine instructions and a processor coupled to the memory that executes the machine instructions to record an operational history associated with the device driver. The processor further executes the machine instructions to detect an error associated with the device driver, remove an associated driver from service, and automatically replicate a sequence of device driver operations corresponding to a segment of the operational history immediately preceding detection of the error. The processor also executes the machine instructions to automatically record a diagnostic history associated with the device driver while replicating the sequence of device driver operations. After the sequence has been replicated, the device is returned to service.

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Номер записи: 84
27-11-2014 дата публикации

Pcie switch-based server system, switching method and device

Номер: US20140351654A1
Автор: Fei Long, Xiong Zhang
Принадлежит: Huawei Technologies Co Ltd

A PCIE switch-based server system, switching method and device are disclosed. The system includes: an active PCIE switch device, where the active PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; a standby PCIE switch device, where the standby PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; where the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device are interconnected, so that the standby PCIE switch device obtains switch network configuration information of the active PCIE switch device through the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device.

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Номер записи: 85
15-09-2016 дата публикации

INTERCONNECT PATH FAILOVER

Номер: US20160266989A1
Автор: Jolad Amarnath, Kadayam Harihara, Keremane Hrishikesh, Mittal Rishabh, Ramasubramaniam Vaiapuri
Принадлежит:

One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadata stored within a write cache) may be mirrored from the primary storage controller to the secondary storage controller over one or more interconnect paths. Responsive to identifying a failover trigger for a failed interconnect path, the secondary storage controller is instructed to fence (e.g., block) I/O operations from the failed interconnect path. Streams of data and/or metadata that were affected by the failure may be instructed to transmit such data and/or metadata over one or more non-failed interconnect paths to the secondary storage controller during failover of the failed interconnect path. 1. A method , comprising:identifying a failover trigger associated with a first interconnect path between a first storage controller and a second storage controller;sending a fence instruction to the second storage controller, the fence instruction instructing the second storage controller to fence I/O operations from the first interconnect path; andresponsive to receiving a fence acknowledgement message from the second storage controller, performing interconnect failover for the first interconnect path utilizing a second interconnect path to transmit storage information from the first storage controller to the second storage controller.2. The method of claim 1 , wherein the first interconnect path is between a first nonvolatile memory of the first storage controller and a second nonvolatile memory of the second storage controller for data mirroring.3. The method of claim 1 , the identifying a failover trigger comprising:responsive to a polling interval expiring, polling the second ...

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Номер записи: 86
15-08-2019 дата публикации

Enhanced Serial Peripheral Interface (eSPI) Signaling for Crash Event Notification

Номер: US20190251010A1
Автор: Aditya Bhutada, Mazen Gedeon, Zhenyu Zhu
Принадлежит: Intel Corp

Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI master device to an eSPI slave device. In embodiments, the eSPI master device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI master device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI master device and the eSPI slave device. Other embodiments may be described and/or claimed.

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Номер записи: 87
14-09-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170262195A1
Автор: ICHIGUCHI Tetsuichiro, IZUMI Shinya, TAKE Yukiko
Принадлежит:

In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU. 1. A semiconductor device , comprising:a main processor that controls operation of the semiconductor device;a rewritable nonvolatile memory; anda memory controller that controls write and erase operations to the nonvolatile memory,wherein the memory controller includes a storage unit that stores a control program used to perform read/write/erase operations to the nonvolatile memory and the memory controller reads the control program from the storage unit to perform read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, andwherein the memory controller executes a test firmware to evaluate the nonvolatile memory.2. The semiconductor device according to claim 1 , wherein the memory controller includes:a rewrite controller that controls write and erase operations to the nonvolatile memory; anda general-purpose processor,wherein, when the semiconductor device is in normal operation, the rewrite controller reads the control program from the storage unit and executes the control program for read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, andwherein, when the semiconductor device is in test operation to evaluate the characteristics of the nonvolatile memory, the general-purpose processor executes the test firmware.3. The ...

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Номер записи: 88
14-09-2017 дата публикации

METHOD AND SYSTEM FOR IMPROVING FLASH STORAGE UTILIZATION BY PREDICTING BAD M-PAGES

Номер: US20170262336A1
Автор: Agarwal Rajiv, Bonwick Jeffrey S., Ferreira Jeffrey Paul, Shapiro Michael W., Tabrizi Haleh
Принадлежит:

A method for managing persistent storage. The method includes selecting a page for a proactive read request, where the page is located in the persistent storage. The method further includes issuing the proactive read request to the page, receiving, in response to the proactive read request, a bit error value (BEV) for data stored on the page, obtaining a BEV threshold (T) for the page, wherein T is determined using a program/erase cycle value associated with the page and a retention time of the data stored on the page, making a first determination that the BEV is greater than T, based on the first determination: identifying an m-page, where the m-page is a set of pages and the page is in the set of pages, and setting the m-page as non-allocatable for future operations. 1. A method for managing persistent storage , the method comprising:selecting a page for a proactive read request, wherein the page is located in the persistent storage;issuing the proactive read request to the page;receiving, in response to the proactive read request, a bit error value (BEV) for data stored on the page;obtaining a BEV threshold (T) for the page, wherein T is determined using a program/erase cycle value associated with the page and a retention time of the data stored on the page;making a first determination that the BEV is greater than T; identifying an m-page, wherein the m-page is a set of pages, wherein the page is in the set of pages;', 'setting the m-page as non-allocatable for future operations., 'based on the first determination2. The method of claim 1 , further comprising:making a second determination that the data on the page is correctable using error-correcting codes; 'scheduling the data on the page to be written to a new allocatable page in the persistent storage.', 'based on the second determination3. The method of claim 2 , further comprising:after the scheduling:writing the data on the page to the new allocatable page as part of a garbage collection operation.4. The ...

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Номер записи: 89
22-09-2016 дата публикации

ELECTRONIC DEVICE HAVING MULTIPLEXED INPUT/OUTPUT TERMINALS

Номер: US20160274989A1
Автор: KRUECKEN JOSEF MARIA JOACHIM, Litovtchenko Vladimir
Принадлежит:

An electronic device has terminals for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver and a terminal control circuit for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error. 1. An electronic device , the device comprising:at least one terminal arrangement to interface internal signals in the electronic device to external signals of other electronic devices via a terminal,the terminal arrangement comprising the terminal, a terminal driver and a terminal control circuit,the terminal control circuit configured to receive a terminal configuration, the terminal configuration defining properties of the terminal driver,the terminal driver being coupled to the terminal control circuit configured to set an actual configuration of the terminal driver according to the terminal configuration, andthe electronic device comprising at least one terminal checker configured tocompare the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed,and when the configuration of the terminal driver is a not allowed configuration, set the actual configuration to a default configuration.2. The Device as claimed in claim 1 , wherein the ...

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Номер записи: 90
13-08-2020 дата публикации

INSPECTING APPARATUS

Номер: US20200257388A1
Автор: FUJITA Shigeki, Hikita Osamu, Iwami Koji, Matsukawa Toshihide, SAKAMOTO Koji
Принадлежит:

An inspection apparatus is provided with a holder configured to set an inspection target thereon, the inspection target configured to detect a contact position on the inspection target touched by a human finger; pseudo finger(s) configured to be detected as the human finger upon contact with the inspection target; a positioner configured to move the pseudo finger(s) relative to the inspection target and to change the contact position of the pseudo finger(s) relative to the inspection target; a memory configured to store, respectively, a value of a pressing force in a range of pressing forces said range including a zero pressing force for each of the pseudo finger(s) on the inspection target; a controller configured to regulate the pressing force for pseudo finger(s) of the pseudo finger(s) based on the respective value; and a sensor configured to acquire an electric signal output from the inspection target. 1. An inspection apparatus comprising:a holder configured to set an inspection target thereon, the inspection target configured to detect a contact position on the inspection target touched by a human finger;at least one pseudo finger configured to be detected as the human finger upon contact with the inspection target, the at least one pseudo finger being an elongated member;a positioner configured to move the at least one pseudo fingers relative to the inspection target and to change the contact position of the at least one pseudo finger relative to the inspection target;a memory configured to store a respective value of a pressing force in a range of pressing forces, said range including a zero pressing force value, for each of the at least one pseudo finger on the inspection target;a controller configured to regulate the pressing force for at least one pseudo finger based on the one or more respective values; anda sensor configured to acquire an electric signal output from the inspection target.2. The inspection apparatus of claim 1 , further comprising:a ...

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Номер записи: 91
27-09-2018 дата публикации

PCIe VIRTUAL SWITCHES AND AN OPERATING METHOD THEREOF

Номер: US20180276161A1
Автор: AHN Sungjoon
Принадлежит:

A memory system and an operating method thereof include: at least a host; and at least PCIe coupled with the host, wherein the at least PCIe link includes at least a PCIe switch and a plurality of PCIe endpoints, wherein the plurality of PCIe endpoints includes used PCIe endpoints and unused PCIe endpoints, the used PCIe endpoints are mapped into a PCIe enumeration tree, and the unused PCIe endpoints are removed from the PCIe enumeration tree, at virtual switch mode. 1. A memory system comprising:at least a host; andat least a PCIe link coupled with the host, wherein the at least PCIe link includes at least a PCIe switch and a plurality of PCIe endpoints, whereinthe plurality of PCIe endpoints includes used PCIe endpoints and unused PCIe endpoints, the used PCIe endpoints are mapped into a PCIe enumeration tree, and the unused PCIe endpoints are removed from the PCIe enumeration tree, at virtual switch mode.2. The memory system recited in wherein the PCIe enumeration tree includes virtual switch mapping between upstream PCIe ports and downstream PCIe ports of the plurality of PCIe switch.3. The memory system recited in wherein the used PCIe endpoints include PCIe endpoints identified in accordance with virtual switch configurations.4. The memory system recited in wherein the used PCIe endpoints include PCIe endpoints identified needed to be included in the PCIe enumeration tree.5. The memory system recited in wherein the virtual switch mapping includes virtual switch mapping conducted in accordance with virtual switch configurations.6. The memory system recited in wherein the virtual switch mapping includes each edge in the PCIe enumeration tree mapped into upstream-downstream mapping of virtual switch configuration on the PCIe switch.7. The memory system recited in wherein the virtual switch mapping is performed repeatedly for all PCIe switches.8. The memory system recited in further comprising configuration data in accordance with virtual switch mapping.9. A ...

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Номер записи: 92
05-10-2017 дата публикации

MECHANISM FOR PCIE CABLE TOPOLOGY DISCOVERY IN A RACK SCALE ARCHITECTURE ENVIRONMENT

Номер: US20170286352A1
Автор: Kumar Mohan J., Nachimuthu Murugasamy K.
Принадлежит:

A mechanism for PCIe cable topology discovery in a Rack Scale Architecture (RSA) and associated methods, apparatus, and systems. Pooled system drawers installed in rack are interconnected via multiple PCIe cables coupled to PCIe ports on the pooled system drawers. The PCIe ports are associated with host ports connections between server nodes and host ports in respective pooled system drawers are automatically detected, with corresponding PCIe connection information being automatically generated and aggregated to determine the PCIe cable topology for the rack. In one aspect, PCIe devices are emulated for each host port in a pooled storage drawer including pooled PCIe storage devices. Server nodes in a pooled compute drawer send PCIe configuration messages over the PCIe cables, with returned reply messages generated by the emulated PCIe devices identifying the host ports. Information pertaining to the host ports, pooled system drawers, and server nodes is used to determine the PCIe cable topology. 1. A method for determining Peripheral Component Interconnect Express (PCIe) cable topology in a rack in which a plurality pooled system drawers are installed and interconnected by a plurality of PCIe cables , the pooled system drawers including one or more pooled compute drawers , each including a plurality of server nodes , the method comprising: 'automatically detecting a connection between a server node in a first pooled system drawer to which a first end of the PCIe cable is connected and a port on a second pooled system drawer to which a second end of the PCIe cable is connected and automatically generating corresponding PCIe connection information; and', 'for each of the plurality of PCIe cables,'}automatically generating a PCIe cable topology for the rack by aggregating the PCIe connection information for each PCIe cable.2. The method of claim 1 , wherein the second pooled system drawer includes a plurality of PCIe ports to which the second end of a respective PCIe ...

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Номер записи: 93
12-10-2017 дата публикации

DEVICE INTERFERENCE DETECTION AND REMEDIATION

Номер: US20170293521A1
Автор: Chakra Al, Dunne Jonathan, Harpur Liam, Patrocinio Eduardo A.
Принадлежит:

A computer-implemented method includes calculating a first efficiency of a first device connected to a host system when a second device is not connected to the host system. Connection of the second device to the host system is detected. The method further includes calculating a second efficiency of the first device when the second device is connected to the host system. An interference quotient of the first device is calculated, by a computer processor, based on the first efficiency and the second efficiency. A user is warned of interference between the first device and the second device, responsive to the interference quotient being in an unacceptable range. 1. A computer-implemented method comprising:calculating a first efficiency of a first device connected to a host system when a second device is not connected to the host system;detecting connection of the second device to the host system;calculating a second efficiency of the first device when the second device is connected to the host system;calculating, by a computer processor, an interference quotient of the first device based on the first efficiency and the second efficiency; andwarning a user of interference between the first device and the second device, responsive to the interference quotient being in an unacceptable range.2. The computer-implemented method of claim 1 , further comprising suggesting a first remedial action to a user claim 1 , the first remedial action being directed to change the interference quotient claim 1 , responsive to the interference quotient being in the unacceptable range.3. The computer-implemented method of claim 2 , further comprising:maintaining an action table of remedial actions in rank order;identifying the first remedial action as a highest-ranked remedial action in the action table that has not yet been tried to change the interference quotient; andselecting the first remedial action to be suggested to the user, responsive to the first remedial action being the highest ...

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Номер записи: 94
19-10-2017 дата публикации

DEVICE WITH LOW-OHMIC CIRCUIT PATH

Номер: US20170300397A1
Автор: Barrenscheen Jens
Принадлежит:

A device, including a low-ohmic circuit path; a normal operation circuit path coupled in parallel with the low-ohmic circuit path; and a circuit element configured to select between the low-ohmic circuit path and the normal operation circuit path. 1. A device , comprising:a low-ohmic circuit path;a normal operation circuit path coupled in parallel with the low-ohmic circuit path; anda circuit element configured to select between the low-ohmic circuit path and the normal operation circuit path even when the device is not powered.2. The device of claim 1 , wherein the circuit element is configured to select between the low-ohmic circuit path and the normal operation circuit path based on a supply voltage.3. The device of claim 2 , wherein:the circuit element comprises an under-voltage lockout (UVLO) circuit configured to detect whether the supply voltage is above a predetermined threshold voltage,if the supply voltage is not above the predetermined threshold voltage, the UVLO circuit selects the low-ohmic circuit path, andif the supply voltage is above the predetermined threshold voltage, the UVLO circuit selects the normal operation circuit path.4. The device of claim 3 , wherein the low-ohmic circuit path comprises a switch and a resistor coupled in series claim 3 , and the UVLO circuit selects between the low-ohmic circuit path and the normal operation circuit path by controlling the switch.5. The device of claim 2 , further comprising:a checker circuit configured to check a status of the device for an error or failure, and configured to select the low-ohmic circuit path even if the device is receiving the supply voltage.6. The device of claim 1 , wherein the low-ohmic circuit path comprises a bi-directional normally-on switch between an input and an output of the device.7. The device of claim 6 , wherein the switch is comprised of two anti-serially coupled normally-on transistors.8. The device of claim 1 , wherein the circuit element is further configured to ...

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Номер записи: 95
25-10-2018 дата публикации

Automated test generation for multi-interface and multi-platform enterprise virtualization management environment

Номер: US20180307574A1
Автор: Tariq Hanif, Tin H. To
Принадлежит: International Business Machines Corp

Embodiments for automated testing of a virtualization management system are described. An example computer-implemented method for automated testing of a virtualization management system includes sending, by a test server, a test case to a plurality of instances of the system under test, the test case sent to each instance of the system under test via each interface from a plurality of interfaces supported by the system under test. The method further includes, for each instance of the system under test, performing multi-interface comparison. The comparison includes comparing, by the test server, responses to the test case from each of the interfaces. The method also includes in response to the responses from each of the interfaces being identical, storing the responses in an instance-response file corresponding to the instance. The method also includes reporting, by the test server, an error in response to the responses from each interface not being identical.

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Номер записи: 96
02-11-2017 дата публикации

QUARTZ PLASTIC COMPOSITE OPTICAL FIBER ASSEMBLY, RECOGNITION METHOD AND DEVICE

Номер: US20170315302A1
Автор: Gong Yu, Hao Xiangyong, MA Aiping, Zhang Dezhi
Принадлежит: ZTE CORPORATION

A composite optical fiber assembly of quartz and plastic, an identification method and an identification device are disclosed. The composite optical fiber assembly of quartz and plastic includes a quartz optical fiber, a connector of the quartz optical fiber, at least two plastic optical fibers, and connectors of plastic optical fibers respectively corresponding to the at least two plastic optical fibers. The plastic optical fibers are laid on the quartz optical fiber. With the structure, whether the connectors at the two ends are properly connected can be intuitively inspected by eyes and displayed. 1. A composite optical fiber assembly of quartz and plastic , comprising: a quartz optical fiber , a connector of the quartz optical fiber , at least two plastic optical fibers , and connectors of plastic optical fibers respectively corresponding to the at least two plastic optical fibers , wherein the plastic optical fibers are laid on the quartz optical fiber.2. The composite optical fiber assembly of quartz and plastic of claim 1 , wherein each of the at least two plastic optical fibers is configured to conspicuously highlight the various connection states of the connector of the quartz optical fiber when a light source is introduced into the connector of the plastic optical fiber.3. An identifying method claim 1 , comprising:determining whether the connector of the quartz optical fiber disposed with the plastic optical fiber is properly connected; anddepending on the result of the determination, lightening the plastic optical fiber on the quartz optical fiber of which the connector has been properly connected, such that the plastic optical fiber conspicuously highlights a connection state of the connector of the quartz optical fiber.4. The method of claim 3 , wherein lightening the plastic optical fiber on the quartz optical fiber of which the connector has been properly connected claim 3 , such that the plastic optical fiber conspicuously highlights a connection ...

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Номер записи: 97
01-11-2018 дата публикации

SYSTEM AND METHOD FOR SIMULATING HUMAN MANUAL INPUT FOR DEVICES USING CAPACITIVE TOUCHSCREENS

Номер: US20180314373A1
Автор: Kikinis Dan
Принадлежит:

Disclosed are systems, methods, and devices for simulating human manual input for devices using capacitive touchscreens. In one embodiment, the system comprises a test fixture, wherein the test fixture comprises a matrix of tubes, each tube being coated with a conductive coating; and a camera located under the matrix and configured to record the capacitive touchscreen of the device under test. The system further includes a tablet to receive images from the camera and display a visual representation of the capacitive touchscreen of the device under test, wherein the tablet is configured to receive a plurality of touch events; update the visual representation of the capacitive touchscreen of the device under test in response to the plurality of touch events; and generate a simulation of touch events, the simulation representing interaction with the device under test. The system further includes a workstation communicatively coupled to the tablet and configured to receive the simulation from the tablet device; and transmit the simulation to the test fixture to enable the execution of the simulation on one or more additional devices under test. 1. A system for simulating human manual input for devices using capacitive touchscreens , the system comprising: an LCD display; and', 'a camera located under the matrix and configured to record the capacitive touchscreen of the device under test;, 'a test fixture designed to receive a device under test having a capacitive touchscreen, wherein the test fixture comprises receive a plurality of touch events;', 'update the visual representation of the capacitive touchscreen of the device under test in response to the plurality of touch events; and', 'generate a simulation of touch events, the simulation representing interaction with the device under test; and, 'a tablet configured to receive images from the camera and display a visual representation of the capacitive touchscreen of the device under test, wherein the tablet is ...

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Номер записи: 98
01-11-2018 дата публикации

Intermittent display issue monitoring system

Номер: US20180315363A1
Автор: Mark Perry Abbott
Принадлежит: Honeywell International Inc

A system to detect intermittent failures of a display system including a display and a display processing system is provided. The system may include, but is not limited to, a sensor system configured to capture a light level of the display, and a processor configured to cause the display processing system to generate the static image on the display, determine, when the display is displaying the static image, a baseline light level of the display, validate an existence of an intermittent display error when the light level of the display is greater than the baseline light level by a first predetermined amount or when the light level of the display is less than the baseline light level by a second predetermined amount at least once over the predetermined amount of time, determine a recurrence rate, and associate an error type with each instance.

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Номер записи: 99
01-11-2018 дата публикации

SMART BOX FOR AUTOMATIC FEATURE TESTING OF SMART PHONES AND OTHER DEVICES

Номер: US20180316443A1
Автор: Diperna Derek, Kutchuk Artun, LEVENTHAL Ira, SCHAUB Keith
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An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller operable to be coupled with a smart device in an enclosure, wherein the system controller comprises a memory comprising test logic and a processor. The system also comprises the enclosure, wherein the enclosure comprises a plurality of components, the plurality of components comprising: (i) a robotic arm comprising a stylus, wherein the stylus is operable to manipulate the smart device to simulate human interaction therewith; and (ii) a platform comprising a device holder, wherein the device holder is operable to receive a smart device inserted there into. The processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic. 122-. (canceled)23. An automatic system level testing (ASLT) system for testing smart devices , the system comprising:a system controller operable to be coupled with a smart device, wherein the system controller comprises a memory comprising test logic and a processor;an enclosure, wherein the enclosure comprises an image plate with a fixed reference image, and wherein the enclosure further comprises a plurality of components, the plurality of components comprising:a robotic arm comprising a stylus attached, wherein the stylus is operable to manipulate the smart device to simulate human interaction therewith;a platform comprising a device holder, wherein the device holder is operable to receive a smart device inserted there into; launch a camera application on the smart device;', 'control the platform to position the smart device in a suitable location relative to the image plate;', 'control the smart device to capture an image of the fixed reference image on the image plate using a camera on the smart device;', 'retrieve a captured image from the smart device; and', 'compare the captured image with a reference image stored in the memory of the system ...

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