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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 10331. Отображено 100.
05-01-2012 дата публикации

Semiconductor substrate and semiconductor device

Номер: US20120001195A1
Автор: Isao Makabe, Keiichi Yui, Ken Nakata, Takamitsu Kitamura
Принадлежит: Sumitomo Electric Industries Ltd

A semiconductor substrate inclu8des an AlN layer that is formed so as to contact a Si substrate and has an FWMH of a rocking curve of a (002) plane by x-ray diffraction, the FWMH being less than or equal to 1500 seconds, and a GaN-based semiconductor layer formed on the AlN layer.

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Номер записи: 1
19-01-2012 дата публикации

Performance of nitride semiconductor devices

Номер: US20120012894A1
Автор: Jinwook Chung, Tomas Apostol Palacios
Принадлежит: Massachusetts Institute of Technology

A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region.

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Номер записи: 2
02-02-2012 дата публикации

Semiconductor wafer, method of producing semiconductor wafer, method of judging quality of semiconductor wafer, and electronic device

Номер: US20120025271A1
Автор: Tsuyoshi Nakano
Принадлежит: Sumitomo Chemical Co Ltd

There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.

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Номер записи: 3
22-03-2012 дата публикации

Field modulating plate and circuit

Номер: US20120068772A1
Автор: Ronaldus Johannus Martinus van Boxtel, Saad Kheder Murad
Принадлежит: Individual

Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.

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Номер записи: 4
17-05-2012 дата публикации

METHOD FOR FABRICATING A GaN-BASED THIN FILM TRANSISTOR

Номер: US20120122281A1
Автор: Chia-Hua Chang, YI Chang, Yueh-Chin Lin
Принадлежит: National Chiao Tung University NCTU

A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.

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Номер записи: 5
07-06-2012 дата публикации

Reducing wafer distortion through a low cte layer

Номер: US20120138945A1
Автор: Chi-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Ho-Yung David Hwang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

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Номер записи: 6
07-06-2012 дата публикации

Island matrixed gallium nitride microwave and power switching transistors

Номер: US20120138950A1
Автор: Ahmad Mizan, Girvan Patterson, Greg Klowak, John Roberts
Принадлежит: GaN Systems Inc

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

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Номер записи: 7
07-06-2012 дата публикации

Compound semiconductor device and manufacturing method thereof

Номер: US20120138955A1
Автор: Atsushi Yamada, Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer.

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Номер записи: 8
07-06-2012 дата публикации

Compound semiconductor device and manufacturing method thereof

Номер: US20120139038A1
Автор: Kenji Imanishi, Toshihide Kikkawa
Принадлежит: Fujitsu Ltd

A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1<x2≦1” is found when a composition of the first AlGaN layer is represented by Al x1 Ga 1-x1 N, and a composition of the second AlGaN layer is represented by Al x2 Ga 1-x2 N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

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Номер записи: 9
28-06-2012 дата публикации

Semiconductor device

Номер: US20120161153A1
Автор: Masahiko Kuraguchi, Miki Yumoto
Принадлежит: Toshiba Corp

A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.

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Номер записи: 10
05-07-2012 дата публикации

Semiconductor element, hemt element, and method of manufacturing semiconductor element

Номер: US20120168771A1
Автор: Makoto Miyoshi, Mikiya Ichimura, Mitsuhiro Tanaka, Shigeaki Sumiya, Tomohiko Sugiyama
Принадлежит: NGK Insulators Ltd

A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In x1 Al y1 Ga z1 N, a barrier layer formed of a second group-III nitride having a composition of In x2 Al y2 N, and a contact layer formed of a third group-III nitride having insularity and adjacent to the barrier layer, and the Schottky electrode is connected to the contact layer. In addition, a heat treatment is performed under a nitrogen atmosphere after the gate electrode has been formed.

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Номер записи: 11
05-07-2012 дата публикации

Heterostructure device and associated method

Номер: US20120171824A1
Автор: Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan, Vinayak Tilak
Принадлежит: General Electric Co

A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

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Номер записи: 12
12-07-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120178226A1
Автор: Kozo Makiyama
Принадлежит: Fujitsu Ltd

A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.

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Номер записи: 13
30-08-2012 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20120217543A1
Автор: Toshihide Kikkawa, Toshihiro Ohki, Yuichi Minoura
Принадлежит: Fujitsu Ltd

At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.

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Номер записи: 14
30-08-2012 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20120217591A1
Автор: Yoichi Kamada
Принадлежит: Fujitsu Ltd

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

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Номер записи: 15
13-09-2012 дата публикации

High temperature performance capable gallium nitride transistor

Номер: US20120228675A1
Автор: Sten Heikman, Yifeng Wu
Принадлежит: Cree Inc

A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

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Номер записи: 16
20-09-2012 дата публикации

Normally-Off Semiconductor Devices

Номер: US20120235160A1
Автор: Sten Heikman, Yifeng Wu
Принадлежит: Individual

Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

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Номер записи: 17
01-11-2012 дата публикации

Bipolar Transistor with Lateral Emitter and Collector and Method of Production

Номер: US20120273760A1
Автор: Lcon C.M. van den Oever, Ray J.E. Hueting
Принадлежит: EPCOS AG

A bipolar transistor includes a substrate of semiconductor material, a high-mobility layer in the substrate, and a donor layer adjacent to the high-mobility layer. An emitter terminal forms an emitter contact on the donor layer, and a collector terminal forms a collector contact on the donor layer. A base terminal is electrically conductively connected with the high-mobility layer. The transistor can be produced in a HEMT technology or BiFET technology in GaAs.

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Номер записи: 18
01-11-2012 дата публикации

High electron mobility transistor

Номер: US20120274402A1
Автор: Christopher Boguslaw Kocon
Принадлежит: Texas Instruments Inc

A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain.

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Номер записи: 19
22-11-2012 дата публикации

Functional element and manufacturing method of same

Номер: US20120292642A1
Автор: Akihiro Urata, Masahiro Araki, Masahiro Shiota, Takaaki Utsumi
Принадлежит: Sharp Corp

Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ 1 - 100], [ - 1010], and [ 01 - 01] of the substrate from a [ 0001 ] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

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Номер записи: 20
06-12-2012 дата публикации

Lateral trench mesfet

Номер: US20120305932A1
Автор: Andreas Peter Meiser, Franz Hirler
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

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Номер записи: 21
06-12-2012 дата публикации

Compound semiconductor device and method for manufacturing the same

Номер: US20120307534A1
Автор: Atsushi Yamada
Принадлежит: Fujitsu Ltd

An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

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Номер записи: 22
17-01-2013 дата публикации

Semiconductor structure and method of forming the same

Номер: US20130015460A1
Автор: Chun Lin Tsai, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu, Po-Chih Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

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Номер записи: 23
21-02-2013 дата публикации

Hemt with integrated low forward bias diode

Номер: US20130043484A1
Автор: Gilberto Curatola, Oliver Häberlen
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

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Номер записи: 24
21-02-2013 дата публикации

Nitride semiconductor transistor

Номер: US20130043492A1
Автор: Tetsuzo Ueda, Toshiyuki Takizawa
Принадлежит: Panasonic Corp

A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

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Номер записи: 25
28-03-2013 дата публикации

Semiconductor device

Номер: US20130075786A1
Автор: Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

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Номер записи: 26
28-03-2013 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20130077352A1
Автор: Atsushi Yamada, Sanae Shimizu
Принадлежит: Fujitsu Ltd

A semiconductor device includes a substrate; a first nitride semiconductor layer provided over the substrate and having a nitride-polar surface; a gate electrode provided over the first nitride semiconductor layer; and a semiconductor layer provided on the first nitride semiconductor layer and only under the gate electrode, and exhibiting a polarization.

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Номер записи: 27
04-04-2013 дата публикации

Nitride semiconductor device and manufacturing method thereof

Номер: US20130082277A1
Автор: Ki Yeol Park, Seok Yoon HONG, Woo Chul Jeon, Young Hwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.

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Номер записи: 28
04-04-2013 дата публикации

Compound semiconductor device and method for fabricating the same

Номер: US20130082360A1
Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Toyoo Miyajima
Принадлежит: Fujitsu Ltd

A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

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Номер записи: 29
18-04-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130092952A1
Автор: IMADA Tadahiro
Принадлежит: FUJITSU LIMITED

A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor. 1. A semiconductor device , comprising:a substrate;a transistor that comprises a first electron transit layer and an electron supply layer which are stacked in a thickness direction of the substrate;a second electron transit layer formed over the substrate in parallel to the first electron transit layer and the electron supply layer;an anode electrode that forms a Schottky junction with the second electron transit layer; anda cathode electrode that forms an ohmic junction with the second electron transit layer, whereinthe anode electrode is connected to a source of the transistor, andthe cathode electrode is connected to a drain of the transistor.2. The semiconductor device according to claim 1 , wherein the transistor comprises an n-type gallium nitride layer formed over the electron supply layer.3. The semiconductor device according to claim 2 , wherein the transistor comprises:an insulating layer formed on the n-type gallium nitride layer and made of an aluminum nitride or an aluminum gallium nitride; anda second n-type gallium nitride layer formed on the insulating layer.4. The semiconductor device according to claim 1 , wherein the transistor is located between the substrate and the second electron transit layer.5. The semiconductor device according to claim 1 , wherein the second electron transit layer is located between the substrate and the transistor.6. The semiconductor device ...

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Номер записи: 30
25-04-2013 дата публикации

Gan-on-si switch devices

Номер: US20130099324A1
Автор: Jenn Hwa Huang, Weixiao Huang
Принадлежит: Individual

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

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Номер записи: 31
02-05-2013 дата публикации

Semiconductor device

Номер: US20130105812A1
Автор: Akihisa Terano, Kazuhiro Mochizuki, Ryuta Tsuchiya, Takashi Ishigaki
Принадлежит: HITACHI LTD

A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

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Номер записи: 32
09-05-2013 дата публикации

Gallium Nitride Semiconductor Devices and Method Making Thereof

Номер: US20130112986A1
Автор: Chen-Ju YU, Chih-Wen Hsiung, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.

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Номер записи: 33
23-05-2013 дата публикации

Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap

Номер: US20130126889A1
Автор: Sandeep Bahl
Принадлежит: Texas Instruments Inc

An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.

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Номер записи: 34
13-06-2013 дата публикации

Semiconductor device including stepped gate electrode and fabrication method thereof

Номер: US20130146944A1
Автор: Byoung-Gue Min, Dong Min Kang, Eun Soo Nam, Ho Kyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Jong Min Lee, Jong-Won Lim, Seong-II Kim
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

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Номер записи: 35
13-06-2013 дата публикации

Semiconductor having integrally-formed enhanced thermal management

Номер: US20130147050A1
Автор: Richard William Bonner, III, Tapan Desai
Принадлежит: Advanced Cooling Technologies Inc

A semiconductor structure and method of manufacturing that has integrally-formed enhanced thermal management. During operation of a semiconductor device, electron flow between the source and the drain creates localized heat generation. A containment gap is formed by selectively removing a portion of the back side of the semiconductor device substrate directly adjacent to a localized heat generation area. A thermal management material is filled in the containment gap. This thermal management material enhances the thermal management of the semiconductor device by thermally coupling the localized heat generation area to a heat sink. The thermal management material may be a Phase Change Material (PCM) having a heat of fusion effective for absorbing heat generated in the localized heat generation area by the operation of the semiconductor device for reducing a peak operating temperature of the semiconductor device.

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Номер записи: 36
20-06-2013 дата публикации

ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF

Номер: US20130153923A1
Автор: Decoutere Stefaan
Принадлежит: IMEC

Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. 1. A method of manufacturing an enhancement mode III-nitride high electron mobility transistor (HEMT) , the method comprising:providing a substrate comprising a stack of layers on the substrate, each layer comprising a III-nitride material, and a passivation layer comprising high temperature (HT) silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by metal-organic chemical vapor deposition (MOCVD) or low pressure chemical vapor deposition (LPCVD) at a temperature higher than about 450° C.;forming a recessed gate region by removing substantially completely the passivation layer only in the gate region, thereby exposing the underlying upper layer;forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region; andforming a gate contact in the gate region and source/drain contacts through the passivation layer.2. The method according to claim 1 , wherein the passivation layer is formed in-situ with the stack of III-nitride layers.3. The ...

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Номер записи: 37
27-06-2013 дата публикации

Transistor with enhanced channel charge inducing material layer and threshold voltage control

Номер: US20130161641A1
Автор: Charles R. Eddy, Jr., Francis J. Kub, Karl D. Hobart, Michael A. Mastro, Travis Anderson
Принадлежит: US Department of Navy

High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

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Номер записи: 38
27-06-2013 дата публикации

JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE

Номер: US20130161706A1
Автор: Cheng Kangguo, Kerber Pranita, Khakifirooz Ali, Ning Tak H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). 1. A method of fabricating a Schottky field effect transistor (FET) comprising:forming a replacement gate structure on a portion of a semiconductor substrate, wherein a source region and a drain region are formed in opposing sides of the portion of the semiconductor substrate that the replacement gate structure is formed on;forming a dielectric on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure;removing the replacement gate structure to provide an opening to an exposed portion of the semiconductor substrate; anddepositing a metal gate conductor within the opening in direct contact with the exposed portion of the semiconductor substrate.2. The method of claim 1 , wherein the depositing of the metal gate conductor comprises physical vapor deposition (PVD) of an elemental metal.3. The method of claim 1 , wherein the source region and the drain region are doped to an n-type conductivity claim 1 , and a channel region of the semiconductor substrate present between the source region and the drain region is doped to an n-type conductivity.4. The method of claim 1 , wherein the semiconductor substrate is a ...

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Номер записи: 39
04-07-2013 дата публикации

Enhancement mode gallium nitride based transistor device

Номер: US20130168687A1
Автор: Rong Xuan, Suh-Fang Lin, Wei-Hung Kuo
Принадлежит: Industrial Technology Research Institute ITRI

Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current.

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Номер записи: 40
18-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Номер: US20130181255A1
Автор: Inoue Kazutaka, Kiyama Makoto, Okada Masaya, Saitoh Yu, Yaegashi Seiji, Yokoyama Mitsunori
Принадлежит: Sumitomo Electric Industries, Ltd.

There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer including a channel located on a wall surface of an opening a p-type barrier layer whose end face is covered, a source layer that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer. 1. A vertical semiconductor device including a group III nitride-based stacked layer having an opening , the semiconductor device comprising:a regrown layer including a channel located so as to cover a wall surface of the opening;a p-type group III nitride-based semiconductor layer having an end face covered with the regrown layer at the wall surface of the opening;a group III nitride-based source layer that serves as a top layer of the group III nitride-based stacked layer and is located on the p-type group III nitride-based semiconductor layer;a gate electrode located on the regrown layer in the opening; anda source electrode located on the group III nitride-based stacked layer around the opening so as to be in contact with the regrown layer and the group III nitride-based source layer,wherein the regrown layer includes an electron drift layer and an electron source layer and the channel is formed of two-dimensional electron gas generated in the electron drift layer at a position near an interface between the electron drift layer and the electron source layer, andthe group III nitride-based source layer has a superlattice structure that is ...

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Номер записи: 41
15-08-2013 дата публикации

Method of manufacturing compound semiconductor device

Номер: US20130210203A1
Автор: Kenji Imanishi, Toshihide Kikkawa
Принадлежит: Fujitsu Ltd

A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

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Номер записи: 42
29-08-2013 дата публикации

Semiconductor device and method for producing same

Номер: US20130221434A1
Автор: Kazutaka Inoue, Makoto Kiyama, Masaya Okada, Mitsunori Yokoyama, Seiji Yaegashi, Yu Saitoh
Принадлежит: Sumitomo Electric Industries Ltd

It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4 /p-type GaN-based barrier layer 6 /n-type GaN-based contact layer 7 . The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26 , a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.

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Номер записи: 43
19-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Номер: US20130240896A1
Автор: OZAKI Shirou
Принадлежит:

A method of fabricating a semiconductor device may form a nitride semiconductor layer on a substrate, form a first insulator layer on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer. 1. A semiconductor device comprising:a nitride semiconductor layer formed on a substrate;an insulator formed on the nitride semiconductor layer;a gate electrode formed on the insulator layer; anda source electrode and a drain electrode in contact with the nitride semiconductor layer,wherein the nitride semiconductor layer includes a first semiconductor layer formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer,wherein the insulator layer includes a first insulator layer formed on the second semiconductor layer, and a second insulator layer formed on the first insulator layer, andwherein the second insulator layer has a density higher than that of the first insulator layer.2. The semiconductor device as claimed in claim 1 , wherein the nitride semiconductor layer further includes a third semiconductor layer formed on the second semiconductor layer.3. A semiconductor device comprising:a nitride semiconductor layer formed on a substrate;an insulator formed on the nitride semiconductor layer;a gate electrode formed on the insulator layer; anda source electrode and a drain electrode formed on the nitride semiconductor layer,wherein the nitride semiconductor layer includes a first semiconductor layer formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer, andwherein a ratio of oxygen atoms with respect to metal atoms ...

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Номер записи: 44
03-10-2013 дата публикации

Group iii nitride-based high electron mobility transistor

Номер: US20130256681A1
Автор: Ivan Huang, Willie Huang, Winston Wang
Принадлежит: WIN Semiconductors Corp

A group III nitride-based high electron mobility transistor (HEMT) is disclosed. The group III nitride-based high electron mobility transistor (HEMT) comprises sequentially a substrate, a GaN buffer layer, a GaN channel layer, a AlN spacer layer, a barrier layer, a GaN cap layer, and a delta doped layer inserted between the AlN spacer layer and the barrier layer. The HEMT structure of the present invention can improve the electron mobility and concentration of the two-dimensional electron gas, while keeping a low contact resistance.

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Номер записи: 45
03-10-2013 дата публикации

Gate Overvoltage Protection for Compound Semiconductor Transistors

Номер: US20130256699A1
Автор: Gianmauro Pozzovivo, Gilberto Curatola, Martin Vielemeyer, Michael Hutzler
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

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Номер записи: 46
03-10-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130256753A1
Автор: Mayumi Morizuka, Yoshiharu Takada
Принадлежит: Toshiba Corp

According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.

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Номер записи: 47
10-10-2013 дата публикации

Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof

Номер: US20130264609A1
Автор: Bian Jiantao, Di Zengfeng, Wang Xi, Zhang Miao
Принадлежит:

The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure. 1. A heterogeneously integrated semiconductor substrate material of Ge and a group III-V semiconductor material coplanar on a bulk silicon substrate , wherein a silicone support substrate , a Ge semiconductor layer , a group III-V semiconductor material layer , and an isolation medium material between Ge and the group III-V semiconductor material are disposed;the Ge semiconductor layer is located on the silicon support substrate, the group III-V semiconductor material layer is located on a part of the Ge semiconductor layer, and a top of the group III-V semiconductor material layer and a Ge semiconductor layer laterally adjacent to the group III-V semiconductor material layer are coplanar, the isolation medium material ...

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Номер записи: 48
24-10-2013 дата публикации

NON-PLANAR III-N TRANSISTOR

Номер: US20130277683A1
Автор: Chau Robert, Chu-Kung Benjamin, Dewey Gilbert, Kavalieros Jack, Metz Matthew, Mukherjee Niloy, Pillarisetty Ravi, Radosavljevic Marko, Then Han Wui
Принадлежит:

Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 0) plane on a (110) plane of the silicon. 1. A high electron mobility transistor (HEMT) , comprising:a non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls;a first crystalline semiconductor layer disposed over the first and second sidewalls;a source and drain region at opposite ends of the non-planar, polar crystalline semiconductor body with the channel region disposed there between; anda gate structure disposed over the first crystalline semiconductor layer along at least the second sidewall.2. The HEMT of claim 1 , wherein the first crystalline semiconductor layer is to provide a back barrier with a heterojunction formed along the first sidewall claim 1 , and to provide a two dimensional electron gas (2DEG) within a channel region of the non-planar claim 1 , polar crystalline semiconductor body with a heterojunction along the second sidewall.3. The HEMT of claim 2 , wherein the gate structure is further disposed over the first crystalline semiconductor layer along the first sidewall to gate the ...

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Номер записи: 49
24-10-2013 дата публикации

HIGH VOLTAGE FIELD EFFECT TRANSITOR FINGER TERMINATIONS

Номер: US20130277687A1
Автор: HENRY HALDANE S., Kobayashi Kevin Wesley, Ritenour Andrew P.
Принадлежит: RF MICRO DEVICES, INC.

A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation. 1. A field effect transistor comprising:a substrate;an active region disposed on the substrate;at least one source finger in contact with the active region;at least one gate finger in rectifying contact with the active region;at least one drain finger in contact with the active region; andat least one source field plate integral with the at least one source finger such that the at least one source field plate extends over the at least one gate finger with a portion of the source field plate extending outside of the active region.2. The field effect transistor of wherein the at least one source field plate includes at least one side that extends downwardly towards the active region between the at least one gate finger and the at least one drain finger.3. The field effect transistor of wherein the at least one gate finger includes a gate field plate integrated with the at least one gate finger.4. The field effect transistor of wherein the gate field plate integrated with the at least one gate finger appears as a T shape or alternatively as a r shape when viewed from an end of the at ...

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Номер записи: 50
31-10-2013 дата публикации

PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTOR (pHEMT) COMPRISING LOW TEMPERATURE BUFFER LAYER

Номер: US20130285119A1
Автор: Hans G. Rohdin, John Stanback, Jonathan Abrokwah, Nate PERKINS, Phil Marsh
Принадлежит: Avago Technologies Wireless IP Singapore Pte Ltd

A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.

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Номер записи: 51
07-11-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130292690A1
Автор: ANDO Yuji, OTA Kazuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.

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Номер записи: 52
14-11-2013 дата публикации

Contact Structures for Compound Semiconductor Devices

Номер: US20130299842A1
Автор: Clemens Ostermaier, Gerhard Prechtl, Gianmauro Pozzovivo, Oliver Häberlen
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

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Номер записи: 53
28-11-2013 дата публикации

A non-uniform lateral profile of two-dimensional electron gas charge density in type iii nitride hemt devices using ion implantation through gray scale mask

Номер: US20130313611A1
Автор: Karim S. Boutros, Sameh Khalil
Принадлежит: HRL LABORATORIES LLC

A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.

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Номер записи: 54
28-11-2013 дата публикации

Selectively Area Regrown III-Nitride High Electron Mobility Transistor

Номер: US20130313613A1
Автор: Asif Khan, Qhalid Fareed, Vinod Adivarahan
Принадлежит: UNIVERSITY OF SOUTH CAROLINA

Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.

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Номер записи: 55
05-12-2013 дата публикации

In-situ barrier oxidation techniques and configurations

Номер: US20130320349A1
Автор: Andrew A. Ketterson, Paul Saunier
Принадлежит: Triquint Semiconductor Inc

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.

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Номер записи: 56
12-12-2013 дата публикации

LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET

Номер: US20130328060A1
Автор: Liu LinLin, Peres Boris, POPHRISTIC Milan
Принадлежит: POWER INTEGRATIONS, INC.

A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads. 1. A semiconductor device , comprising:a heterostructure that includes a channel layer extending in a longitudinal direction, a first portion of the channel layer being located on a mesa and a second portion of the channel layer being located off the mesa;a series of interdigitated gate, source and drain electrodes extending in the longitudinal direction and being disposed over the first portion of the channel layer located on the mesa, the source and drain electrodes extending in the longitudinal direction beyond an edge of the mesa and extending over the second portion of the channel layer, the gate electrodes extending along a sidewall of the mesa;a source pad located off the mesa;a conductive source interconnect having a first portion electrically connected to one of the source electrodes and a second portion electrically connected to the source pad;a gate pad located off the mesa and overlapping the source pad at least in part; anda conductive gate interconnect having a first portion electrically connected to a portion of the gate electrode extending along the mesa sidewall, the conductive gate interconnect having a second portion electrically communicating with the gate pad.2. The ...

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Номер записи: 57
19-12-2013 дата публикации

Quantum-well-based semiconductor devices

Номер: US20130337623A1
Автор: Gilbert Dewey, Marko Radosavljevic, Matthew V. Metz, Ravi Pillarisetty, Robert S. Chau
Принадлежит: Intel Corp

Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

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Номер записи: 58
26-12-2013 дата публикации

DOUBLE ALUMINUM NITRIDE SPACERS FOR NITRIDE HIGH ELECTRON-MOBILITY TRANSISTORS

Номер: US20130341635A1
Автор: Cao Yu, Johnson Wayne, Laboutin Oleg
Принадлежит:

An epitaxial structure and a high electron mobility transistor (HEMT) employing the epitaxial structure includes a first spacer layer over a channel layer, a first barrier layer over the first spacer layer, and a second spacer layer over the first barrier layer. 1. An epitaxial structure , comprising:a) a substrate;b) a buffer layer on the substrate;c) a channel layer over the buffer layer, wherein the channel layer includes a 2-dimensional electron gas;d) a first spacer layer on the channel layer;e) a first barrier layer on the first spacer layer;f) a second spacer layer on the first barrier layer; andg) a second barrier layer on the second spacer layer;2. The epitaxial structure of claim 1 , wherein the first and second barrier layers are each independently formed of at least one member of the group consisting of aluminum nitride claim 1 , aluminum gallium nitride claim 1 , indium aluminum nitride claim 1 , and indium aluminum gallium nitride.3. The epitaxial structure of claim 2 , wherein the first and second barrier layers each independently consist essentially of InGaAlN claim 2 , where 0.03≦y≦0.3 and 0.01≦z≦0.1.4. The epitaxial structure of claim 3 , wherein the channel layer consists essentially of InGaN claim 3 , where 0≦x≦1.5. The epitaxial structure of claim 4 , wherein the first spacer layer is formed of a material selected from the group consisting of aluminum nitride claim 4 , aluminum gallium nitride.6. The epitaxial structure of claim 5 , wherein the second spacer layer is formed of a material selected from the group consisting of aluminum gallium nitride claim 5 , indium aluminum gallium nitride.7. The epitaxial structure of claim 6 , wherein the average collective thickness of the first and second barrier layers claim 6 , and the second spacer layer is about 11 nm.8. The epitaxial structure of claim 7 , wherein the first barrier layer has an average thickness of about 8 nm claim 7 , the second barrier layer has an average thickness of about 2 nm and ...

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Номер записи: 59
26-12-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130341640A1
Автор: Hiroyuki Sakurai
Принадлежит: Individual

According to an embodiment, a semiconductor device includes a semiconductor, a source electrode, a drain electrode, an insulating layer and a gate electrode. The semiconductor layer includes an GaN layer and a AlGaN layer provided on the GaN layer. The source electrode and the drain electrode are provided on the semiconductor layer. The insulating layer is provided on the semiconductor layer between the source electrode and the drain electrode. The gate electrode includes a penetrating portion and a gate field plate, the penetrating portion being in contact with the semiconductor layer through the insulating layer and containing platinum in contact with the semiconductor layer, the gate field plate being in contact with an upper face of the insulating layer with a contact length of not less than 0.1 micrometers and not more than 0.3 micrometers and containing platinum in contact with the upper surface.

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Номер записи: 60
02-01-2014 дата публикации

Group iii nitride semiconductor device, production method therefor, and power converter

Номер: US20140004669A1
Автор: Toru Oka
Принадлежит: Toyoda Gosei Co Ltd

A method for producing a semiconductor device, includes forming a first carrier transport layer including a Group III nitride semiconductor, forming a mask on a region of the first carrier transport layer, selectively re-growing a second carrier transport layer on an unmasked region of the first carrier transport layer, the second carrier transport layer including a Group III nitride semiconductor, and selectively growing a carrier supply layer on the second carrier transport layer, the carrier supply layer including a Group III nitride semiconductor having a bandgap different from that of the Group III nitride semiconductor of the second carrier transport layer.

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Номер записи: 61
23-01-2014 дата публикации

High electron mobility transistors and methods of manufacturing the same

Номер: US20140021480A1
Автор: Woo-Chul JEON
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A HEMT according to example embodiments may include a first semiconductor layer, a second semiconductor layer configured to induce a 2-dimensional electron gas (2DEG) in the second semiconductor layer, an insulating mask layer on the second semiconductor layer, a depletion forming layer on one of a portion of the first semiconductor layer and a portion of the second semiconductor layer that is exposed by an opening defined by the insulating mask layer, a gate on the depletion forming layer, and a source and a drain on at least one of the first semiconductor layer and the second semiconductor layer. The source and drain may be spaced apart from the gate. The depleting forming layer may be configured to form a depletion region in the 2DEG.

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Номер записи: 62
30-01-2014 дата публикации

Silicon Carbide Lamina

Номер: US20140030836A1
Автор: Christopher J. Petti, Steve Babayan, Venkatesan Murali
Принадлежит: Twin Creeks Technologies Inc

A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.

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Номер записи: 63
06-02-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140035004A1
Автор: FUJIMOTO Hidetoshi, Naka Toshiyuki, Ohno Tetsuya, SAITO Wataru, Saito Yasunobu, Yoshioka Akira
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer. 1. A semiconductor device comprising:a first nitride semiconductor layer;a second nitride semiconductor layer provided on the first nitride semiconductor layer and including a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer;a first heterojunction field effect transistor having a first source electrode provided on the second nitride semiconductor layer and forming an electric connection with the second nitride semiconductor layer, a first drain electrode provided on the second nitride semiconductor layer and forming an electric connection with the second nitride semiconductor layer, and a first gate electrode provided between the first source electrode and the first drain electrode;a first Schottky barrier diode having a first anode electrode provided on the second nitride semiconductor layer, forming an electric connection with the second nitride semiconductor layer, and electrically connected to the first drain electrode, and having a first cathode electrode provided on the second nitride ...

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Номер записи: 64
06-02-2014 дата публикации

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140038372A1
Автор: KANAMURA MASAHITO, MAKIYAMA Kozo
Принадлежит: FUJITSU LIMITED

Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output. 1. A method of manufacturing a compound semiconductor device , the compound semiconductor device comprising:a substrate;an electron transit layer formed above the substrate;an electron supply layer formed above the electron transit layer; anda source electrode, a drain electrode, and a gate electrode formed between the source electrode and the drain electrode, which are formed above the electron supply layer,wherein a first insulating film is formed at a position closer to the drain electrode than to the gate electrode and a second insulating film is formed at a position closer to the gate electrode than to the drain electrode, between the gate electrode and the drain electrode, andwherein a two-dimensional electron gas concentration at a portion corresponding to below the second insulating film is made lower than a two-dimensional electron gas concentration at a portion corresponding to below the first insulating film between the electron transit layer and the electron supply layer.2. The method of manufacturing a compound semiconductor device according to claim ...

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Номер записи: 65
13-02-2014 дата публикации

High electron mobility transistor

Номер: US20140042449A1
Автор: Jae-joon Oh, Jai-Kwang Shin, Jong-Bong Ha, Jong-Seob Kim, Ki-Yeol Park, Sun-Kyu Hwang, Woo-Chul JEON, Young-Hwan Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG.

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Номер записи: 66
13-02-2014 дата публикации

Field effect transistor device

Номер: US20140042455A1
Автор: Geng-Yen Lee, Hui-Ling Lin, Jen-Inn Chyi, Shih-Peng Chen
Принадлежит: Delta Electronics Inc, National Central University

A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.

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Номер записи: 67
06-03-2014 дата публикации

GaN Dual Field Plate Device with Single Field Plate Metal

Номер: US20140061659A1
Автор: Bruce M. Green, James A. Teplik
Принадлежит: Individual

A low leakage current transistor ( 2 ) is provided which includes a GaN-containing substrate ( 11 - 14 ) covered by a passivation surface layer ( 17 ) in which a T-gate electrode with sidewall extensions ( 20 ) is formed and coated with a multi-level passivation layer ( 30 - 32 ) which includes an intermediate etch stop layer ( 31 ) which is used to define a continuous multi-region field plate ( 33 ) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.

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Номер записи: 68
13-03-2014 дата публикации

Active Area Shaping of III-Nitride Devices Utilizing Steps of Source-Side and Drain-Side Field Plates

Номер: US20140070280A1
Автор: Michael A. Briere
Принадлежит: International Rectifier Corp USA

In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include one or more steps, where the drain-side field plate has a different number of the one or more steps than the source-side field plate.

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Номер записи: 69
27-03-2014 дата публикации

VERTICAL MICROELECTRONIC COMPONENT AND CORRESPONDING PRODUCTION METHOD

Номер: US20140084299A1
Автор: Daves Walter, SCHELLING Christoph
Принадлежит: ROBERT BOSCH GMBH

A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches. Each fin includes a GaN/AlGaN heterolayer region formed on the side wall and including a channel region extending essentially parallel to the side wall. Each fin includes a gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in the associated trench on the side wall. A common source terminal region arranged above the fins is connected to a first end of the channel region in a vicinity of the upper sides. A common drain terminal region arranged above the back side is connected to a second end of the channel region in a vicinity of the front side. 1. A vertical microelectronic component , comprising:a semiconductor substrate including a front side and a back side; at least one GaN/AlGaN heterolayer region formed on the side wall and including an embedded channel region extending essentially parallel to the side wall; and', 'at least one gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in an associated trench on the side wall;, 'an arrangement of a multiplicity of fins formed on the front side of the semiconductor substrate, each fin having a side wall and an upper side and separated from other fins by trenches, each fin includinga common source terminal region arranged above the fins and connected to a respective first end of the channel region in a vicinity of the upper sides of the fins; anda common drain terminal region arranged above the back side and connected to a respective second end of the channel region in a vicinity of the front side of the semiconductor substrate.2. The vertical microelectronic component according to claim 1 , wherein:each fin includes two GaN/AlGaN ...

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Номер записи: 70
27-03-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140084300A1
Автор: ANDO Yuji, Inoue Takashi, Nakayama Tatsuo, Okamoto Yasuhiro, OTA Kazuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition InAlN (0≦z≦1), a channel layer having a composition of: AlGaN (0≦x≦1) or InGaN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode. 1. A semiconductor device including a field effect transistor comprising:a substrate; anda semiconductor layer provided on the substrate, the semiconductor layer including:{'sub': 1-z', 'z, 'a lower barrier layer provided on the substrate, Ga-face grown and lattice-relaxed, the lower barrier layer having a composition of InAlN (0≦z≦1); and'}{'sub': x', '1-x', 'y', '1-y, 'a channel layer provided on the lower barrier layer and lattice-matched to the lower barrier layer, the channel layer having a composition of: AlGaN (0≦x≦1) or InGaN (0≦y≦1) or GaN;'}a source electrode and a drain electrode disposed spaced to each other, the source electrode and the drain electrode each having an ohmic contact to an upper part of the semiconductor layer; anda gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.2. The semiconductor device according to claim 1 , wherein the field effect transistor comprises negative surface charges induced by to electric polarization on an interface between the lower barrier layer and the channel layer.3. The semiconductor device according to claim 1 , wherein a negative electric field is applied to the gate insulating film in an equilibrium state.4. The semiconductor device according to claim 1 , wherein the channel layer ...

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Номер записи: 71
27-03-2014 дата публикации

Power device and method for manufacturing the same

Номер: US20140087529A1
Автор: Jae Hoon Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.

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Номер записи: 72
03-04-2014 дата публикации

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140092635A1
Автор: KAMADA Youichi, Kiuchi Kenji
Принадлежит:

An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode. 1. A compound semiconductor device comprising:a compound semiconductor layer;a pair of electrodes formed on an upper side of the compound semiconductor layer; anda high-resistance layer disposed in a lower portion of at least one electrode out of the pair of electrodes and higher in an electric resistance value than the electrodes.2. The compound semiconductor device according to claim 1 , wherein the high-resistance layer contains an Al—Si-Ncompound that satisfies{'br': None, 'i': 'x+y+z=', '1'}{'br': None, 'and'}{'br': None, 'i': ' Подробнее

Номер записи: 73
10-04-2014 дата публикации

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20140097468A1
Автор: HIKITA Masahiro, Nishio Akihiko, OKITA Hideyuki, Sato Takahiro, TAKEDA Hidenori, Uemoto Yasuhiro
Принадлежит: Panasonic Corporation

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer () located over the substrate; a second nitride semiconductor layer () located over the first nitride semiconductor layer (), having a larger band gap than the first nitride semiconductor layer (), and having a recess () penetrating into the first nitride semiconductor layer (); and a third nitride semiconductor layer () continuously covering the second nitride semiconductor layer () and the recess (), and having a larger band gap than the first nitride semiconductor layer (); a gate electrode () located above a portion of the third nitride semiconductor layer () over the recess (); and a first ohmic electrode () and a second ohmic electrode () located on opposite sides of the gate electrode (). 1. A nitride semiconductor device comprising:a substrate; a first nitride semiconductor layer having a recess,', 'a second nitride semiconductor layer located over a portion of the first nitride semiconductor layer other than the recess, and having a larger band gap than the first nitride semiconductor layer, and', 'a third nitride semiconductor layer continuously covering the second nitride semiconductor layer and the recess of the first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer;, 'a semiconductor layer stack that is located over the substrate, and includes'}a gate electrode that is located above a portion of the third nitride semiconductor layer over the recess; anda first ohmic electrode and a second ohmic electrode that are located on opposite sides of the gate electrode.2. The nitride semiconductor device according to claim 1 , whereinthe second nitride semiconductor layer has a larger band gap than the third nitride semiconductor layer.3. The nitride semiconductor device according to claim 1 , whereinthe third nitride semiconductor layer has a larger band gap than the second nitride semiconductor layer.4. The nitride ...

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Номер записи: 74
01-01-2015 дата публикации

HEMT Structure with Iron-Doping-Stop Component and Methods of Forming

Номер: US20150001582A1
Автор: Cao Yu, Johnson Wayne, Laboutin Oleg
Принадлежит: IQE KC, LLC

An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer. 1. An iron-doped high electron-mobility transistor structure , comprising:a) a substrate;b) a nucleation layer over the substrate; i) an iron-doped layer over the nucleation layer;', {'sup': 16', '−3, 'ii) an iron-doping-stop layer adjoining the iron-doped layer at a juncture, the iron-doping-stop layer having an iron concentration below about 1×10cmat a surface distal to the juncture with the iron-doped layer, and wherein the iron-doping stop layer has an average thickness in a range of between about 1 nm and about 100 nm'}], 'c) a buffer layer over the nucleation layer, said buffer layer including,'}d) a channel layer over the buffer layer; ande) a carrier-supplying barrier layer over the channel layer.2. The iron-doped high electron mobility transistor structure of claim 1 , wherein the iron-doping layer has a thickness in a range of between about 5 nm and about 20 nm.3. The iron-doped high electron-mobility transistor structure of claim 1 , wherein the concentration of iron is essentially constant from the nucleation layer to the iron-doping-stop layer.4. The iron-doped high electron mobility transistor structure of claim 3 , wherein the iron-doped layer of the buffer layer has an average thickness in a range of between about 0.5 and about 20 μm.5. The high ...

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Номер записи: 75
01-01-2015 дата публикации

NITRIDE SEMICONDUCTOR DEVICE

Номер: US20150001586A1
Автор: Fujita Koichiro, Morishita Satoshi
Принадлежит:

A nitride semiconductor device includes a substrate, a nitride semiconductor laminate, and an ohmic electrode of TiAl-based material. The nitride semiconductor laminate has a first nitride semiconductor layer on the substrate, and a second nitride semiconductor layer forming a heterointerface with the first nitride semiconductor layer. The nitride semiconductor device has an oxygen concentration profile in a depth direction of the device across between the ohmic electrode and the nitride semiconductor laminate. The profile has a first oxygen concentration peak near an interface between the ohmic electrode and the nitride semiconductor laminate in a region, of the nitride semiconductor laminate, that is on a substrate side of the interface, and a second oxygen concentration peak having an oxygen concentration of 3×10cm-1.2×10cmin a position deeper than that of the first oxygen concentration peak. 1. A nitride semiconductor device comprising:a substrate;a nitride semiconductor laminate placed on the substrate and having a heterointerface;an ohmic electrode comprising a TiAl-based material, at least a part of the ohmic electrode being placed on the nitride semiconductor laminate or in the nitride semiconductor laminate;the nitride semiconductor laminate including a first nitride semiconductor layer placed on the substrate, and a second nitride semiconductor layer placed on the first nitride semiconductor layer and forming the heterointerface with the first nitride semiconductor layer; and a first oxygen concentration peak in a position in vicinity of an interface between the ohmic electrode and the nitride semiconductor laminate, the position of the first oxygen concentration peak being located in a region of the nitride semiconductor laminate that is on a substrate side of the interface between the ohmic electrode and the nitride semiconductor laminate, and', {'sup': 17', '−3', '18', '−3, 'a second oxygen concentration peak in a position deeper than the position of ...

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Номер записи: 76
06-01-2022 дата публикации

POLARIZATION CONTROLLED TRANSISTOR

Номер: US20220005938A1
Автор: Johnson Noble M., LU JENGPING, Wunderer Thomas
Принадлежит:

A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction. 1. A transistor comprising:a first layer comprising a group III-nitride semiconductor;a second layer comprising a group III-nitride semiconductor disposed over the first layer;a third layer comprising a group III-nitride semiconductor disposed over the second layer, an interface between the second layer and the third layer forming a polarization heterojunction;a fourth layer comprising a group III-nitride semiconductor disposed over the third layer, an interface between the third layer and the fourth layer forming a pn junction;a first electrical contact pad disposed on the fourth layer;a second electrical contact pad disposed on the third layer;a third electrical contact pad electronically coupled to bias the polarization heterojunction.2. The transistor of claim 1 , wherein the second layer is n-doped claim 1 , the third layer is n-doped and the fourth layer is p-doped.3. The transistor of claim 2 , wherein a doping concentration of n-doped layers on the order of 10to 10cmand a doping concentration of p-doped layers on the order of 10to 10cm.4. The transistor of claim 1 , wherein a distance between the pn junction and the polarization heterojunction is between 25 nm and 500 nm.5. The transistor of claim 1 , wherein ...

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Номер записи: 77
06-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20220005939A1
Автор: Chiu Han-Chin
Принадлежит:

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer above the substrate, a semiconductor stack disposed on and in contact with the first nitride semiconductor layer, and a first electrode in contact with the semiconductor stack. Wherein the semiconductor stack comprises a first layer and a second layer, and a lattice constant of the first layer along an a-axis is less than the second layer. 1. A semiconductor device , comprising:a substrate;a first nitride semiconductor layer disposed above the substrate;a semiconductor stack disposed on and in contact with the first nitride semiconductor layer; anda first electrode in contact with the semiconductor stack,wherein the semiconductor stack comprises a first layer and a second layer, and a lattice constant of the first layer along an a-axis is less than the second layer.2. The semiconductor device according to claim 1 , wherein the first layer comprises AlGaM claim 1 , and the value y ranges from 0 to 1.3. The semiconductor device according to claim 1 , wherein the second layer comprises InAlN claim 1 , and the value x ranges from 0 to 1.4. The semiconductor device according to claim 1 , wherein the lattice constant along the a-axis of the first layer ranges from approximately 3.1 Å to approximately 3.18 Å.5. The semiconductor device according to claim 1 , wherein the lattice constant along the a-axis of the second layer ranges from approximately 3.2 Å to approximately 3.5 Å.6. The semiconductor device according to claim 1 , wherein the first layer is in contact with the first nitride semiconductor layer.7. The semiconductor device according to claim 1 , wherein the second layer is in contact with the first electrode.8. The semiconductor device according to claim 1 , wherein the semiconductor stack further comprises a third layer interposed between the first layer and the second layer claim 1 , the a ...

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Номер записи: 78
06-01-2022 дата публикации

SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Номер: US20220005944A1
Автор: CHOU Yi-Lun
Принадлежит:

A semiconductor device structure includes a substrate, a channel layer, a barrier layer and a doped group III-V layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The doped group III-V layer is disposed on the barrier layer. The doped group III-V layer includes a first portion and a second portion. The first portion has a first concentration of a first element. The second portion is adjacent to the first portion and has a second concentration of the first element. The gate structure is disposed on the first portion of the doped group III-V layer. The first concentration of the first element is different from the second concentration of the first element. 1. A semiconductor device structure , comprising:a substrate;a channel layer disposed on the substrate;a barrier layer disposed on the channel layer; a first portion having a first concentration of a first element; and', 'a second portion adjacent to the first portion having a second concentration of the first element; and, 'a doped group III-V layer disposed on the barrier layer, comprisinga gate structure disposed on the first portion of the doped group III-V layer,wherein the first concentration of the first element is different from the second concentration of the first element.2. The semiconductor device structure of claim 1 , wherein a first surface of the first portion is substantially coplanar with a first surface of the second portion.3. The semiconductor device structure of claim 1 , wherein a first surface of the first portion has an elevation same to a first surface of the second portion.4. The semiconductor device structure of claim 1 , wherein a first surface of the first portion has an elevation greater than a first surface of the second portion.5. The semiconductor device structure of claim 1 , wherein a first surface of the first portion has an elevation less than a first surface of the second portion.6. The semiconductor device structure of ...

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Номер записи: 79
07-01-2016 дата публикации

High electron mobility transistor structure and method of making the same

Номер: US20160005823A1
Автор: Chen-Ju YU, Chih-Wen Hsiung, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu, King-Yuen Wong
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

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Номер записи: 80
07-01-2021 дата публикации

ELECTRONIC DEVICE WITH 2-DIMENSIONAL ELECTRON GAS BETWEEN POLAR-ORIENTED RARE-EARTH OXIDE LAYER GROWN OVER A SEMICONDUCTOR

Номер: US20210005720A1
Автор: Clark Andrew, Dargis Rytis, Hammond Richard, LEBBY MICHAEL, Pelzel Rodney
Принадлежит:

Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer. 1. A layered structure , comprising:a group III-nitride (III-N) layer, wherein the III-N layer has an orientation that is not polar; anda polar rare-earth oxide layer grown over the III-N layer.2. The layered structure of claim 1 , wherein the orientation of the III-N layer is non-polar.3. The layered structure of claim 1 , wherein the orientation of the III-N layer is semi-polar.4. The layered structure of claim 1 , further comprising:a rare-earth silicide layer grown over the polar rare-earth oxide layer.5. The layered structure of claim 1 , further comprising:an epitaxial metal layer epitaxially grown over the polar rare-earth oxide layer.6. The layered structure of claim 1 , wherein the polar rare earth oxide layer has at least a first portion of electrons that diffuse to an interface between the polar rare-earth oxide layer and the III-N layer or are transferred to the III-N layer to form an n-type 2-dimensional electron gas (2DEG) on the III-N layer.7. The layered structure of claim 6 , wherein the III-N layer and the polar rare-earth oxide layer are selected to yield a conduction band offset between the III-N layer and the polar rare-earth oxide layer that is sufficient for electrons to diffuse from the polar rare-earth oxide layer into the III-N layer.8. The layered structure of claim 1 , further comprising:a group IV substrate;an epi-twist rare-earth oxide layer over the group IV substrate; andwherein ...

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Номер записи: 81
07-01-2021 дата публикации

Semiconductor device

Номер: US20210005730A1
Автор: Akira Mukai, Masahiko Kuraguchi
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, and third semiconductor regions. The third electrode is between the first electrode and the second electrodes. The first semiconductor region includes Alx1Ga1-x1N and includes first to seventh partial regions. The fourth partial region is between the first partial region and the third partial region. The fifth partial region is between the third partial region and the second partial region. The second semiconductor region includes Alx2Ga1-x2N and includes first and second semiconductor portions. The sixth partial region is between the fourth partial region and the first semiconductor portion. The seventh partial region is between the fifth partial region and the second semiconductor portion. The third semiconductor region includes Alx3Ga1-x3N and includes a first semiconductor film part. The first semiconductor film part is between the sixth partial region and the third electrode.

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Номер записи: 82
07-01-2021 дата публикации

Electronic Device Including a High Electron Mobility Transistor Including a Gate Electrode and a Gate Interconnect and a Method of Using the Same

Номер: US20210005740A1
Автор: Banerjee Abhishek, Moens Peter
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film. 1. An electronic device comprising a high electron mobility transistor comprising:a gate electrode;a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; anda gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.2. The electronic device of claim 1 , further comprising a channel layer and a barrier layer overlying the channel layer claim 1 , wherein the gate electrode includes a III-N semiconductor material and contacts the channel layer or the barrier layer.3. The electronic device of claim 1 , wherein the high electron mobility transistor further comprises a drain electrode and a source electrode wherein:the gate electrode is between the drain electrode and the source electrode, andthe gate interconnect contacts the gate electrode over a region configured to allow a current to flow between the drain electrode and the source electrode when the high electron mobility transistor is in an on-state.4. The electronic ...

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Номер записи: 83
07-01-2021 дата публикации

NITRIDE SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF

Номер: US20210005741A1
Автор: OTAKE Hirotaka
Принадлежит:

Disclosed is a nitride semiconductor apparatus including a substrate, a first nitride semiconductor layer disposed above the substrate, and constituting an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and constituting an electron supply layer, a nitride semiconductor gate layer disposed on the second nitride semiconductor layer having a ridge portion at at least an area thereof, and containing an acceptor-type impurity, a gate electrode disposed on the ridge portion, a source electrode and a drain electrode disposed opposite to each other, with the ridge portion interposed therebetween, on the second nitride semiconductor layer, and a strip-shaped insulator disposed between the substrate and a surface layer portion of the first nitride semiconductor layer, and extending along a length direction of the ridge portion when viewed in plan. 1. A nitride semiconductor apparatus comprising:a substrate;a first nitride semiconductor layer disposed above the substrate, and constituting an electron transit layer;a second nitride semiconductor layer formed on the first nitride semiconductor layer, and constituting an electron supply layer;a nitride semiconductor gate layer disposed on the second nitride semiconductor layer having a ridge portion at at least an area thereof, and containing an acceptor-type impurity;a gate electrode disposed on the ridge portion;a source electrode and a drain electrode disposed opposite to each other, with the ridge portion interposed therebetween, on the second nitride semiconductor layer; anda strip-shaped insulator disposed between the substrate and a surface layer portion of the first nitride semiconductor layer, and extending along a length direction of the ridge portion when viewed in plan, whereinthe insulator is disposed below the gate electrode, andthe insulator has a width greater than twice a width of a bottom surface of the gate electrode.2. The nitride semiconductor ...

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Номер записи: 84
02-01-2020 дата публикации

Dielectric Passivation for Electronic Devices

Номер: US20200006500A1
Автор: RAJAN Siddharth, Wang Caiyu, Xia Zhanbo
Принадлежит:

Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact. 1. A transistor comprising:a channel layer extending between a source contact and a drain contact;a barrier layer in electrical communication with the channel layer;a gate contact in electrical communication with the barrier layer;wherein at least a junction portion of the barrier layer connects the gate contact and drain contact, and the junction portion of the barrier layer is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity of the channel layer.2. A transistor according to claim 1 , further comprising a non-conductive substrate supporting the channel layer.3. A transistor according to claim 1 , wherein the junction portion of the barrier layer is the entirety of the barrier layer and connects the gate contact to the channel layer.4. A transistor according to claim 1 , wherein the junction dielectric permittivity is between 2 times and 40 times greater than the channel dielectric permittivity.5. A transistor according to claim 4 , wherein the junction dielectric permittivity is about 30 times greater than the channel dielectric permittivity.6. A transistor according to claim 4 , ...

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Номер записи: 85
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20190006500A1
Автор: Okamoto Yasuhiro, UEDA Takehiro
Принадлежит:

Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part. 1. A semiconductor device , comprising:a first nitride semiconductor layer;a second nitride semiconductor layer formed over the first nitride semiconductor layer;a third nitride semiconductor layer formed over the second nitride semiconductor layer;a mesa part formed over the third nitride semiconductor layer and including a fourth nitride semiconductor layer;a source electrode formed over the third nitride semiconductor layer and on a first side of the mesa part;a drain electrode formed over the third nitride semiconductor layer and on a second side of the mesa part;a gate electrode formed above the mesa part; anda side part formed on at least one side of the mesa part and including the fourth nitride semiconductor layer,wherein the side part extends to the outside of the gate electrode, andwherein generation of two-dimensional electron gas between the second nitride semiconductor layer and the third nitride semiconductor layer is suppressed below the mesa part while being unsuppressed below the side part.2. The semiconductor device according to claim 1 , wherein the mesa part includes the fourth nitride semiconductor layer ...

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Номер записи: 86
02-01-2020 дата публикации

PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING AN ACCESS REGION

Номер: US20200006521A1
Автор: Banerjee Abhishek, Jeon Woochul, Moens Peter, Salih Ali, TACK Marnix, VANMEERBEEK Piet
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region. 1. A process of forming an electronic device comprising:forming a channel layer overlying a substrate;forming a barrier layer overlying the channel layer;forming a p-type semiconductor layer over the barrier layer;patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure; and{'sub': f', 'g', '(1-f-g), 'forming an access region layer over the barrier layer after patterning the p-type semiconductor layer, wherein the access region layer includes AlInGaN, wherein 0 Подробнее

Номер записи: 87
02-01-2020 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE AND METHOD OF FORMING SAME

Номер: US20200006522A1
Автор: Chen Ching Yu, Yeh Chia-Ling
Принадлежит:

A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer. 1. A method comprising:forming a first III-V compound layer over a substrate;forming a second III-V compound layer over the first III-V compound layer, the second III-V compound layer having a greater band gap than the first III-V compound layer;forming a third III-V compound layer over the second III-V compound layer, the third III-V compound layer and the first III-V compound layer comprising a same III-V compound;forming a passivation layer along a topmost surface and sidewalls of the third III-V compound layer; andforming a fourth III-V compound layer over the second III-V compound layer, the fourth III-V compound layer having a greater band gap than the first III-V compound layer.2. The method of claim 1 , wherein forming the passivation layer comprises:blanket depositing a dielectric material over the second III-V compound layer and the third III-V compound layer; andpatterning the dielectric material to expose a topmost surface of the second III-V compound layer, a remaining portion of the dielectric material forming the passivation layer.3. The method of claim 1 , wherein the third III-V compound layer is a p-doped layer.4. The method of claim 1 , wherein forming the fourth III-V ...

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Номер записи: 88
03-01-2019 дата публикации

COMPOUND SEMICONDUCTOR DEVICE AND FABRICATION METHOD

Номер: US20190006503A1
Автор: ISHIGURO Tetsuro, KOTANI Junji, Nakamura Norikazu
Принадлежит: FUJITSU LIMITED

Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region. 1. A compound semiconductor device comprising:an electron transit layer;an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region;a first electrode disposed above the first region; anda second electrode disposed above the second region.2. The compound semiconductor device as claimed in claim 1 , whereinthe second region is thinner than a portion of the first region that is under the second region.3. The compound semiconductor device as claimed in claim 1 , whereinthe second region includes a part of an upper surface of the electron supply layer.4. The compound semiconductor device as claimed in claim 1 , whereinan end of the second region that faces the first electrode in a cross-sectional view is aligned flush with an end of the second electrode that faces the first electrode.5. The compound semiconductor device as claimed in claim 1 , whereinan end of the second region that faces the first electrode in a cross-sectional view is extended toward the first electrode with respect to an end of the second electrode that faces the first electrode.6. The compound semiconductor device as claimed in claim 1 , whereinthe second region contains an n-type impurity in at least an upper portion in a thickness direction.7. The compound semiconductor device as claimed in claim 6 , whereinthe second region contains ...

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Номер записи: 89
20-01-2022 дата публикации

METHOD AND APPARATUS FOR ANALYSIS OF INTERFACE STATE OF MIS-HEMT DEVICE

Номер: US20220018888A1
Автор: LIN Xinnan, Xiong Shuhao
Принадлежит:

Disclosed are method and an apparatus for analysis of an interface state of a MIS-HEMT device. By means of establishing an equivalent model of MIS-HEMT(s) that includes equivalent circuits representing a dielectric layer, a barrier layer and a channel layer, plotting a group of a capacitance-frequency function curve and a conductance-frequency function curve that can be best fitted to the measured capacitance-frequency scatter diagram and the measured conductance-frequency scatter diagram via the equivalent model, taking such best-fitted group as the fitted function curve group, and calculating parameters about the interface state of MIS-HEMT(s) according to the group of assigned values corresponding to the fitted function curve group, the parameters of the analyzed interface state can be more accurate since the fitted frequency function curve group can, with the aid of the equivalent model, simultaneously fit the measured capacitance-frequency scatter diagram and the measured conductance-frequency scatter diagram. 1. A method for analysis of interface state of MIS-HEMT device , comprising:establishing an equivalent model of a MIS-HEMT device to be analyzed, the MIS-HEMT device including a dielectric layer, a barrier layer and a channel layer, the equivalent model including a dielectric-layer equivalent circuit representing the electrical characteristics of the dielectric layer, a barrier-layer equivalent circuit representing the electrical characteristics of the barrier layer, a channel-layer equivalent circuit representing the electrical characteristics of the channel layer and an interface-state equivalent circuit representing the electrical characteristics of the interface state between the dielectric layer and the barrier layer, the dielectric-layer equivalent circuit, the barrier-layer equivalent circuit and the channel-layer equivalent circuit being connected in series, the interface-state equivalent circuit being connected in parallel to the barrier-layer ...

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Номер записи: 90
20-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20220020870A1
Автор: ERA Atsushi, NONODA Ryohei
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor layers to be overlaid on the substrate and a gate electrode, a drain electrode, and a source electrode provided on the plurality of semiconductor layers, wherein each of the plurality of semiconductor layers includes a channel layer made with GaN and a barrier layer provided in contact with an upper surface of the channel layer and made with AlGaN, and a carbon concentration of the channel layer included in an uppermost semiconductor layer among the plurality of semiconductor layers is lower than an average value of carbon concentration of the channel layer included in the at least one semiconductor layer other than the uppermost semiconductor layer among the plurality of semiconductor layers. 1. A semiconductor device comprising:a substrate;a plurality of semiconductor layers to be overlaid on the substrate; anda gate electrode, a drain electrode, and a source electrode provided on the plurality of semiconductor layers, wherein{'sub': x', '1-x, 'each of the plurality of semiconductor layers includes a channel layer made with GaN and a barrier layer provided in contact with an upper surface of the channel layer and made with AlGaN, and'}a carbon concentration of the channel layer included in an uppermost semiconductor layer among the plurality of semiconductor layers is lower than an average value of carbon concentration of the channel layer included in the at least one semiconductor layer other than the uppermost semiconductor layer among the plurality of semiconductor layers.2. The semiconductor device according to claim 1 , wherein a two-dimensional electron gas is formed at an interface with the barrier layer in the channel layer in each of the plurality of semiconductor layers.31. The semiconductor device according to claim 1 , wherein the channel layer included in the uppermost semiconductor layer is thinner than the channel layer included in the ...

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Номер записи: 91
08-01-2015 дата публикации

METHOD TO FABRICATE SELF-ALIGNED ISOLATION IN GALLIUM NITRIDE DEVICES AND INTEGRATED CIRCUITS

Номер: US20150011057A1
Автор: Beach Robert, Cao Jiali, Cao Jianjun, Chiang Ming-Kun, Kolluri Seshadri, Lidow Alexander, Liu Fang Chang, Ma Yanping, Nakata Alana, Strittmatter Robert, Zhao Guang Yuan, Zhou Chunhua
Принадлежит:

A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer. 1. A method of forming an integrated circuit having at least two transistor devices , the method comprising:forming a buffer layer on a substrate;forming a GaN layer over the buffer layer;forming a barrier layer over the GaN layer;forming a dielectric layer over the barrier layer;forming at least one device contact opening in the dielectric layer for each of the at least two transistor devices and an isolation contact opening in the dielectric layer between the at least two transistor devices;forming a metal layer over the dielectric layer, the device contact openings and the isolation contact opening;forming a photoresist film above each of the device contact openings;etching the metal layer to form a metal mask window above the isolation contact opening; andetching a portion of the barrier layer and the GaN layer that is exposed by the isolation contact opening in the dielectric layer.2. The method of claim 1 , wherein the isolation contact opening is wider than the metal mask window.3. The method of claim 1 , wherein the metal mask window is wider than the ...

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Номер записи: 92
08-01-2015 дата публикации

Method of Manufacturing HEMTs with an Integrated Schottky Diode

Номер: US20150011058A1
Автор: Haeberlen Oliver, Ostermaier Clemens, Prechtl Gerhard
Принадлежит:

An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device. 111-. (canceled)12. A method of manufacturing a transistor device , comprising:forming a compound semiconductor material on a semiconductor carrier;forming a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions;forming a Schottky diode integrated with the semiconductor carrier; andforming contacts extending from the source and drain regions through the compound semiconductor material and in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions.13. A method according to claim 12 , wherein forming the contacts comprises:forming a first trench extending through the source region and the compound semiconductor material and into the semiconductor carrier;forming a second trench extending through the drain region and the compound semiconductor material and into the semiconductor carrier, the first trench extending deeper into the semiconductor carrier than the second trench;forming an insulating material along sidewalls of the first trench; andfilling the first and second trenches with an ...

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Номер записи: 93
27-01-2022 дата публикации

DEVICE AND SEMICONDUCTOR STRUCTURE FOR IMPROVING THE DISADVANTAGES OF P-GAN GATE HIGH ELECTRON MOBILITY TRANSISTOR

Номер: US20220029008A1
Автор: Hsin Yue-Ming, Lai Yu-Chen, YANG Chun-Chieh, ZHONG Yi-Nan
Принадлежит:

A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal. 1. A device , comprising:a first transistor, comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to the first source terminal; anda second transistor, comprising a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is coupled to the first drain terminal.2. The device of claim 1 , wherein each of the first transistor and the second transistor is an E-mode HEMT.3. The device of claim 1 , wherein each of the first transistor and the second transistor is a p-GaN gate HEMT.4. The device of claim 1 , wherein the device is an E-mode HEMT formed by the first transistor and the second transistor.5. The device of claim 4 , wherein the E-mode HEMT comprises a gate terminal claim 4 , a source terminal claim 4 , and a drain terminal claim 4 , wherein the gate terminal is formed by the first gate terminal claim 4 , the source terminal is formed by the second source terminal claim 4 , and the drain terminal is formed by the second drain terminal.6. The device of claim 5 , wherein the first gate terminal is spaced apart from the first drain terminal by a first length claim 5 , wherein a gate leakage of the E-mode HEMT is determined according to the first length.7. The device of claim 5 , wherein the second gate terminal is spaced apart from the second drain terminal by a second length claim 5 , wherein a breakdown voltage between the drain terminal and the source terminal of the E-mode HEMT is determined according to the first length and the second length.8. The device of claim 5 , wherein a threshold ...

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Номер записи: 94
27-01-2022 дата публикации

Field Effect Transistor and Method for Manufacturing Same

Номер: US20220029009A1
Автор: Sugiyama Hiroki
Принадлежит:

A buffer layer, an etching stop layer, and a channel layer are epitaxially grown in this order on a substrate. The substrate contains InP that has a high resistance by, for example, being doped with Fe. The buffer layer contains a compound semiconductor lattice-matched to InP. The etching stop layer includes InAlP (0≤x≤0.75). The channel layer contains InGaAs (0 Подробнее

Номер записи: 95
15-01-2015 дата публикации

III-Nitride Semiconductor Device with Reduced Electric Field

Номер: US20150014701A1
Автор: Briere Michael A.
Принадлежит:

A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate. 117-. (canceled)18. In a III-Nitride semiconductor device having a III-Nitride layer , and a 2DEG layer disposed adjacent a bottom of said III-Nitride layer;first and second laterally spaced contacts coupled to a top of said III-Nitride layer;a source contact coupled to said top of said III-Nitride layer and laterally disposed between said first and second drain contacts;first and second gate contacts coupled to said top of said III-Nitride layer and disposed between said source contact and said first drain contact and between said source contact and said second drain contact respectively; andfirst and second conductive field plates disposed between said first drain contact and said first gate contact and said second drain contact and said second gate contact respectively; said first and second field plate contacts connected to one another and to said source contact.19. The device of claim 18 , wherein said III-Nitride layer is GaN.20. The device of claim 18 , wherein said first and second field plates are a highly conductive III-Nitride material.21. The device of claim 18 , wherein said field plates are selected from the group including GaN and AlGaN.22. The device of claim 18 , wherein said gate contact is a Schottky contact.23. The device of claim 18 , wherein said gate contact is dielectrically insulated from a surface of said III-Nitride layer.24. The device of claim 18 , which further includes a highly conductive N+ III-Nitride pad.25. (canceled)26. The device of claim 18 , which further includes a dielectric layer disposed over said III-Nitride layer.27. The device of claim 18 , wherein said first field plate is a layer of highly ...

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Номер записи: 96
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE WITH VERTICALLY INTEGRATED PHEMTS

Номер: US20180012986A1
Автор: Hurtt Sheila K., Nevers Corey A., Schwartz Dana A.
Принадлежит:

The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other. 1. An apparatus comprising:a substrate; the lower pHEMT structure comprises a lower doping layer doped with at least one n-type dopant; and', 'a lower pHEMT is formed in or on the second region;, 'a lower pseudomorphic high electron mobility transistor (pHEMT) structure formed over the substrate and having a first region and a second region that is laterally disposed with the first region, whereinan isolation layer residing over the first region; and the upper pHEMT structure comprises an upper doping layer doped with at least one n-type dopant;', 'an upper pHEMT is formed in or on the upper pHEMT structure; and', 'the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other., 'an upper pHEMT structure formed over the isolation layer and not extending over the second region, wherein2. The apparatus of wherein the isolation layer does not extend over the second region.3. The apparatus of wherein the isolation layer is formed of aluminum gallium arsenide (AlGaAs) claim 1 , wherein x has a value between 0 and 1 representing ...

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Номер записи: 97
10-01-2019 дата публикации

FET WITH BURIED GATE STRUCTURE

Номер: US20190013386A1
Автор: Carter Andy, King Casey, Shinohara Keisuke, Urteaga Miguel
Принадлежит:

A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments. 1. A field-effect transistor (FET) , comprising:a substrate;an epitaxial buffer layer on said substrate;an epitaxial channel layer on said buffer layer;source and drain electrodes on said substrate's top surface; and ["a plurality of buried gate structures, the tops of which extend above said substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the current-carrying portion of said channel layer, such that said buried gate structures contact said channel layer only from the sides of said channel layer; and", "a head portion above and not in contact with said substrate's top surface which contacts and interconnects all of said buried gate structures;"], 'a gate electrode, comprisingsuch that said FET's drain current is controlled by channel width modulation by lateral gating of the channel layer by said buried gates structures.2. The FET of claim 1 , wherein said FET is a high electron mobility transistor (HEMT) and said current-carrying portion of said channel layer comprises a two-dimensional electron gas (2DEG) plane.3. The FET of claim 2 , further comprising an epitaxial top barrier layer above said channel ...

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Номер записи: 98
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20210013312A1
Автор: LIAO Wen-Chia
Принадлежит:

A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate;forming an active layer on the substrate;forming a p-type doped layer on the active layer, wherein the p-type doped layer has a first thickness;forming a gate electrode on the p-type doped layer;forming a first passivation layer to cover the gate electrode and the active layer;forming a lower portion of a conductive plate on the first passivation layer, wherein a portion of the first passivation layer between the lower portion and the active layer has a second thickness smaller than the first thickness;forming a second passivation layer to cover the lower portion and the first passivation layer;forming a source via hole and a drain via hole in the second passivation layer and forming a source via hole and a drain via hole in the first passivation layer, the source via hole of the first passivation layer and the source via hole of the second passivation layer together exposing a portion of the active layer, and the drain via hole of the first passivation layer and ...

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Номер записи: 99
14-01-2021 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR DEVICES AND METHODS FOR FORMING THE SAME

Номер: US20210013331A1
Автор: Chen Chih-Yen
Принадлежит: Vanguard International Semiconductor Corporation

A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer. 1. A high electron mobility transistor device , comprising:a gate electrode disposed on a semiconductor layer;a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode:a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess;a second dielectric layer disposed on the source field plate;a source electrode disposed on the second dielectric layer and electrically connected to the source field plate;a third dielectric layer disposed on the source electrode; anda drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first recess is located between the drain structure and the gate structure.2. The high electron mobility transistor device as claimed in claim 1 , wherein a portion of the first dielectric layer is located between the first recess and the drain structure claim 1 , and the source field plate does not cover the portion of the first dielectric layer.3. The high electron mobility transistor ...

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Номер записи: 100