СПОСОБ ОБРАБОТКИ ПОДЛОЖЕК И ПОДЛОЖКА, ОБРАБОТАННАЯ ЭТИМ СПОСОБОМ

Изобретение относится к обработке подложек для получения вогнуто-выпуклой структуры. Сущность изобретения: способ обработки подложек включает в себя распыление мелких частиц вместе со сжатым газом из трубки под давлением на поверхность подложки, диспергирование частиц, заряженных посредством трения с внутренней стенкой трубки под давлением, на поверхности подложки, при этом заряженные частицы прилипают к подложке без агрегации, формирование вогнуто-выпуклой структуры на поверхности подложки путем травления поверхности подложки с частицами как маской и одновременного удаления маски травлением. Изобретение обеспечивает возможность сократить число операций способа для формирования вогнуто-выпуклой структуры. 4 з.п. ф-лы, 8 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ МАСКИ ДЛЯ НАНЕСЕНИЯ ТОНКИХ СЛОЕВ В МИКРОСТРУКТУРАХ

Использование: в микроэлектронике для формирования элементов микроструктур. Сущность изобретения: в качестве материала для маски, изготавливаемой методом фотолитографии, берется монокристаллический кремний, который травится анизотропно, причем сторону маски, прилегающую к напыляемой поверхности обрабатываемого кристалла, травят одновременно с этой поверхностью. Техническим результатом изобретения является повышение точности изготовления рисунка маски. 1 ил.

СПОСОБ ФОРМИРОВАНИЯ ПЕРЕХОДНЫХ КОНТАКТНЫХ ОКОН

Способ относится к области микроэлектроники, к технологии изготовления интегральных схем на этапе формирования многоуровневой металлической разводки. Сущность изобретения: для формирования наклонного профиля переходных окон в диэлектрике сформированная на его поверхности фоторезистивная маска подвергается термообработке при 140-160oС до получения наклонных стенок окон, а затем плазмохимическим травлением при соотношении скоростей травления диэлектрика и фоторезиста (1...1,5):1 этот профиль переносится на окна в слое диэлектрика. Способ позволяет достичь технического результата, заключающегося в улучшении воспроизводимости получаемого наклона профиля окон, что уменьшает возможность обрывов металла на стенках окон и приводит к увеличению выхода годных. 3 ил.

СПОСОБ ПОЛУЧЕНИЯ РЕЛЬЕФА В ДИЭЛЕКТРИЧЕСКОЙ ПОДЛОЖКЕ

Изобретение относится к микроэлектронике и может быть использовано для получения рельефа в диэлектрических и пьезоэлектрических подложках, содержащих в своем составе двуокись кремния, при изготовлении микромеханических приборов, кварцевых резонаторов и т.д. Сущность изобретения: в способе получения рельефа в диэлектрической подложке, включающем нанесение на подложку защитной маски в виде многослойной тонкопленочной системы двух материалов и формирование конфигурации защитной маски, травление подложки и удаление защитной маски, в качестве маски используется многослойная тонкопленочная система иттрий-оксид иттрия, полученная напылением в вакууме, причем толщина слоя иттрия не менее 1 мкм, а толщина слоя оксида иттрия не менее 0,05 мкм. Между слоем иттрия и слоем оксида иттрия может быть сформирован переходной слой из смеси этих материалов. Изобретение позволяет увеличить процент выхода годных за счет исключения пор и разрывов в защитном слое, а также позволяет удешевить конечную продукцию ...

ЖИДКАЯ КОМПОЗИЦИЯ, СПОСОБ ПОЛУЧЕНИЯ КРЕМНИЕВОЙ ПОДЛОЖКИ И СПОСОБ ПОЛУЧЕНИЯ ПОДЛОЖКИ ДЛЯ ГОЛОВКИ ДЛЯ ВЫБРОСА ЖИДКОСТИ

Изобретение относится к жидкой композиции, способу получения кремниевой подложки и к способу получения подложки для головки для выброса жидкости. Сущность изобретения: жидкая композиция, используемая для проведения анизотропного травления кристалла кремниевой подложки, снабженной маской для травления, формируемой из пленки оксида кремния, включает гидроксид цезия, щелочное органическое соединение и воду, в которой отношение по массе гидроксида цезия к массе жидкой композиции составляет 1% мас. до 40% мас. включительно. Изобретение обеспечивает повышение скорости анизотропного травления кремния при снижении травления пленки оксида кремния, используемой в качестве маски. 3 н. и 4 з.п. ф-лы, 4 ил., 2 табл., 8 пр.

СПОСОБ ПЛАЗМЕННОГО ТРАВЛЕНИЯ КОНТАКТНЫХ ОКОН В ИЗОЛИРУЮЩИХ И ПАССИВИРУЮЩИХ СЛОЯХ ДИЭЛЕКТРИКОВ НА ОСНОВЕ КРЕМНИЯ

Использование: микроэлектроника, производство БИС и СБИС. Сущность изобретения: способ плазменного травления контактных окон в изолирующих и пассивирующих слоях диэлектриков на основе кремния, включает обработку слоя диэлектрика в индивидуальном диодном реакторе при давлении от 300 до 1200 Па и плотности ВЧ-мощности от 4,0 до 8,0 Вт/см2 в плазме четырехкомпонентной смеси при следующем соотношении компонентов от: октафторпропан или гексафторэтан 12 37, гексафторид серы или трифторид азота 1 4, кислород 1 4, гелий 55 - 86, что позволяет повысить скорость травления и уменьшить осаждение фторуглеродных полимеров. 1 табл., 2 ил.

Способ защиты углов кремниевых микромеханических структур при анизотропном травлении

Изобретение относится к области приборостроения и может применяться при изготовлении кремниевых микромеханических чувствительных элементов датчиков, таких как акселерометры, датчики угловой скорости, датчики давления. Изобретение обеспечивает повышение метрологических характеристик микромеханических датчиков за счет повышения линейности преобразования. Сущность изобретения: в способе защиты углов трехмерных микромеханических структур на кремниевой пластине с кристаллографической ориентацией (100) при глубинном анизотропном травлении в водном растворе гидрооксида калия KOH формируют масочный рисунок с элементами защиты углов, примыкающими к исходной части топологической маски вблизи точки пересечения сторон защищаемой трехмерной микроструктуры на пластине и продолжающимися за пределы исходной части маски. Травление проводят до тех пор, пока кремниевые элементы, сформированные в области маски защиты углов, не стравятся в процессе анизотропного химического травления до границы исходной топологической ...

ЖИДКАЯ КОМПОЗИЦИЯ, СПОСОБ ПОЛУЧЕНИЯ КРЕМНИЕВОЙ ПОДЛОЖКИ И СПОСОБ ПОЛУЧЕНИЯ ПОДЛОЖКИ ДЛЯ ГОЛОВКИ ДЛЯ ВЫБРОСА ЖИДКОСТИ

... 1. Жидкая композиция, используемая для проведения анизотропного травления кристалла кремниевой подложки, снабженной маской для травления, сформированной из пленки оксида кремния, с пленкой оксида кремния, используемой в качестве маски, причем жидкая композиция содержит: ! гидроксид цезия; ! щелочное органическое соединение; и ! воду. ! 2. Жидкая композиция по п.1, в которой щелочное органическое соединение включает гидроксид тетраметиламмония. ! 3. Жидкая композиция по п.1, в которой отношение по массе гидроксида цезия к массе жидкой композиции составляет от 1 мас.% до 40 мас.% включительно. ! 4. Жидкая композиция по п.2, в которой отношение по массе гидроксида тетраметиламмония к массе жидкой композиции составляет от 5 мас.% до 25 мас.% включительно. ! 5. Способ получения кремниевой подложки, причем способ включает: ! получение кремниевой подложки, на которой пленку оксида кремния, формируемую с отверстием, формируют, по меньшей мере, на одной поверхности подложки; и ! травление подложки ...

СПОСОБ ЗАЩИТЫ УГЛОВ ТРЕХМЕРНЫХ МИКРОМЕХАНИЧЕСКИХ СТРУКТУР НА КРЕМНИЕВОЙ ПЛАСТИНЕ ПРИ ГЛУБИННОМ АНИЗОТРОПНОМ ТРАВЛЕНИИ

Способ защиты углов трехмерных микромеханических структур на кремниевой пластине (100), которую подвергают анизотропному травлению в водном растворе КОН, включающий формирование масочного рисунка с элементами защиты углов, примыкающими к основной части топологической маски вблизи точки пересечения сторон защищаемого чипа на пластине и продолжающимися за пределы основной части маски, травление масочного рисунка на пластине в анизотропном травителе, при этом для защиты выпуклого угла чипа формируют хотя бы один Т-образный маскирующий элемент защиты угла, содержащий продольную и поперечную части, у которого ширина поперечной части меньше высоты продольной части, отличающийся тем, что Т-образные маскирующие элементы защиты углов формируют на основе металлизированной структуры V-Cu'-Cu'', а каждый из Т-образных симметрично расположенных элементов выполняют из двух полосок - продольной вдоль направления [110] и поперечной, расположенной в поперечном направлении под прямым углом к продольной полоске ...

Способ локального травления фосфида галлия

Использование: технология изготовления полупроводниковых приборов на фосфиде галлиа Цель: повышение кэчества травления за счет повышения полирующих свойств травителя и сохранения топологии при глубоком (40 - 50 мкм) травления. Сущность изобретения, формирование углублений в пластинах фосфида галлия { 100 } проводят в травителе., содержащем иодат одновалентного металла -5-1.5 мас.%, соляную кислоту - 7 - 25 мас.%, воду - остальное; или метапериодат одно- валетного металла - 1 -10 мас.%, сопяную кислоту - ТО - 20 мас.%, воду - остальное, при перемешивании с частотой вращения 30-60 об/мин, температуре 0 - 30° С и расположении элементов топологии фотошаблона на пластине в направлении 100. 1 табл., ...

СПОСОБ АНИЗОТРОПНОГО ТРАВЛЕНИЯ КРИСТАЛЛОВ КРЕМНИЯ

Способ анизотропного травления кристаллов кремния, включающий формирование на рабочей стороне подложки маски и обработку в анизотропно травящих растворах, отличающийся тем, что перед травлением нерабочую сторону облучают ионами гелия с энергией не менее 100 кэВ, причем дозу облучения определяют на рабочей стороне контрольного образца по изменению значения периода кристаллической решетки кристалла, когда его величина перестает зависеть от дозы.

Способ травления структур поликремний-окисел кремния

Изобретение относится к электронной технике,а именно к технологии из-. готовления интегральных схем,в частности к получению проводящих элемен- ; тов заданной конфигурации из поликристаллического кремния, лежащего на слое окисла кремния .Цель изобретения - повышение качест аа травления за счет получения заданных профиля травления, ухода размеров и селективности травления . Травление ведут в атмосфере тетрафторметана при давлении 5-13 Па и удельной мощности разряда от 0,3 Вт/см до 0,8 Вт/см . Зятем в смеси тетрафторметана с 6-8 об.% кислорода при давлении 35-40 Па и удельной мощности разряда 0,1-0,15 Вт/см . Длительность второй стадии Г определяется-выражением tr u/2 (oLS +р) , где U - заданный уход размера элемента относительно маски; S - зффектив-. ная площадь поверхности обрабатываемого материала, ni к jb - постоянные , зависящие от обрабатываемого материала . При получении конфигурации элементов из попикристаллическо гр кремния постоянные oi и р равны 9,5 10 с/см и 3-10 с/см соответственно ...

Halbleiterbauelement mit einem Aggregat von Mikro-Nadeln aus Halbleitermaterial

Semiconductor device having a trench, and method for fabricating such a semiconductor device

A semiconductor device having a trench (30) which comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate (11), a trench (30) provided between the elements (13), and an isolating material (12), introduced into the trench (30) for separating the elements (13). The trench is widened on both sides in its bottom-section zone (30a). The semiconductor device is fabricated by the bottom-section zone (30a) of the trench (30) being widened by etching. ...

Halbleitersubstrat und Verfahren zum Fertigen von diesem

Ein Halbleitersubstrat umfasst eine erste Materialschicht, die aus einem ersten Material gefertigt ist und mehrere Vorsprünge umfasst, und eine zweite Materialschicht, die aus einem zweiten Material, das von dem ersten Material verschieden ist, gefertigt ist und Räume zwischen den mehreren Vorsprüngen füllt und die mehreren Vorsprünge abdeckt. Jeder der Vorsprünge umfasst eine Spitze und mehrere Flächen, die an der Spitze zusammenlaufen, und benachbarte Flächen benachbarter Vorsprünge stehen miteinander in Kontakt.

Anti-Dishing-Struktur für eingebetteten Speicher

Einige Ausführungsformen der vorliegenden Anmeldung sind auf einen integrierten Schaltkreis (IC) gerichtet. Der integrierte Schaltkreis weist ein Halbleitersubstrat mit einem peripheren Bereich und einem Speicherzellenbereich auf, die durch eine Trennstruktur getrennt sind. Die Trennstruktur reicht in eine Oberseite des Halbleitersubstrats hinein und weist ein dielektrisches Material auf. Auf dem peripheren Bereich ist ein Logikbauelement angeordnet, und auf dem Speicherbereich ist ein Speicherbauelement angeordnet. Das Speicherbauelement weist eine Gate-Elektrode und eine Speicher-Hartmaske über der Gate-Elektrode auf. Auf der Trennstruktur ist eine Anti-Dishing-Struktur angeordnet. Eine Oberseite der Anti-Dishing-Struktur und eine Oberseite der Speicher-Hartmaske haben gleiche Höhen, die von der Oberseite des Halbleitersubstrats gemessen werden.

Verfahren zur Herstellung einer Maskenschicht mit Öffnungen verkleinerter Breite

Verfahren zur Herstellung einer Maskenschicht, bei dem - eine organische Resist-Schicht (3) über einer zu strukturierenden Schicht (2) eines Halbleitersubstrats erzeugt wird; - die organische Resist-Schicht (3) lithographisch strukturiert wird, wobei eine Resist-Öffnung (4) in der Resist-Schicht (3) erzeugt wird; - auf der strukturierten Resist-Schicht (3) ein Polymerisat-Film (5) erzeugt wird, welcher die Seitenwände und den Boden (6) der Resist-Öffnung (4) bedeckt; und - der Polymerisat-Film (5) durch einen anisotropen und gegenüber der zu strukturierenden Schicht (2) selektiven Plasma-Ätzschritt in einer Sauerstoff-haltigen Atmosphäre am Boden (6) der Resist-Öffnung (4) entfernt wird, dadurch gekennzeichnet, - daß es sich bei dem Polymerisat-Film (5) um ein Fluorkohlenwasserstoff-Polymerisat-Film handelt, welcher durch ein kaltes Plasma-Abscheideverfahren mit einem Tetrafluormethan, Methan und ein Inertgas umfassenden Prozeßgasgemisch erzeugt wird.

VERFAHREN UND VORRICHTUNG ZUM AETZEN VON HALBLEITEROBERFLAECHEN

Herstellung eines elektronischen Bauteiles unter Verwendung eines Schrittes zur Strukturerzeugung

A METHOD OF MAKING A COMPONENT FOR A MICROELECTRONIC CIRCUIT AND A SEMICONDUCTOR DEVICE AND AN OPTICAL WAVEGUIDE MADE BY THAT METHOD

MIT ERHÖHTER LEISTUNG MITTELS ELEKTRONENSTRAHLUNG UND INTEGRIERTE SCHALTUNG MIT DIESEM TRANSISTORGATTER

Verfahren zur Herstellung eines Grabenkondensators

MITTEL ZUM AETZEN VON CHROM ODER MOLYBDAEN

VERFAHREN ZUM AETZEN VON SILICIUMNITRID

Semiconductor component - based on thin monocrystalline semiconductor film on insulated substrate

Esp. for use in high speed switching components or ICs, the thin film, is not >3 mu m thick, is formed by a number of different possible processes at the base of a groove cut in from one face of the disc of insulating material, eg. undoped Ge, and is then covered by an insulation film and a support layer. Esp. the thin monocrystalline film is of Si and the insulation film covering it is dioxide, nitride or oxy-nitride of Si. relatively simple and cheap method for high quality.

Selektives ätzen von Silikat

VERFAHREN ZUR FOTOLITHOGRAFISCHEN LACKMASKIERUNG

Verfahren zum Damage-Ätzen der Rückseite einer Halbleiterscheibe bei geschützter Scheibenvorderseite

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE HAVING TRENCH MEMORY CAPACITOR

HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Nicht-Dorn-Schnittbildung

Verfahren zum Bilden von Nicht-Dorn-Schnitten. Auf einer Metallhartmaskenschicht wird eine dielektrische Schicht gebildet und auf der Dielektrikumsschicht wird eine strukturierte Opferschicht gebildet. Die dielektrische Schicht wird geätzt, um einen Nicht-Dorn-Schnitt in der Dielektrikumsschicht zu bilden, der bezüglich der Öffnung in der strukturierten Opferschicht vertikal ausgerichtet ist. Auf einem Bereich der Metallhartmaskenschicht, der durch den Nicht-Dorn-Schnitt in der Dielektrikumsschicht freigelegt wird, wird eine Metallschicht gebildet. Die Metallhartmaskenschicht wird strukturiert, wobei die Metallschicht die Metallhartmaskenschicht über dem Bereich maskiert.

Verfahren zum Ausbilden von Aussparungen in einem Halbleiterbauelement und mit dem Verfahren hergestelltes Bauelement

Verfahren zum Herstellen wenigstens einer Aussparung (12) in einem Halbleiterbauelement (1, 10) mit den Schritten:Aufbringen wenigstens einer Maske (20) auf dem Halbleiterbauelement (1, 10),Ausbilden wenigstens eines Gitters (22) mit mehreren Gitteröffnungen (26) in der Maske (20) über der auszubildenden Aussparung (12), wobei die Gitteröffnungen (26) in Abhängigkeit von der Ätzrate und/oder Dimensionierung der auszubildenden Aussparung (12) ausgebildet sind,wobei für eine breitere Aussparung (12) und/oder eine randnahe Aussparung (12) ein Gitter (22) mit kleineren Gitteröffnungen (26) und für eine schmälere Aussparung (12) und/oder eine Aussparung (12) im Innenbereich des Halbleiterbauelements (1, 10) ein Gitter (22) mit größeren Gitteröffnungen (26) über der auszubildenden Aussparung (12) in der Maske (20) ausgebildet wird;Ausbilden der Aussparung (12) unterhalb des Gitters (22).

Verfahren zur Bildung einer Verbindungsleitung in einem Halbleiterbauelement uner Verwendung einer Phasenverschiebungsfotomaske

Ein Verfahren zur Bildung einer Doppeldamaszierstruktur. Das Verfahren umfasst ein Ablagern eines Zwischenlagendielektrikums auf einer darunterliegenden Schicht, ein Ablagern eines Fotoresists auf dem Zwischenlagendielektrikum und ein Belichten und Entwickeln des Fotoresists unter Verwendung einer Phasenverschiebungsfotomaske, um ein Fotoresistmuster mit Grabenmustern und Lochmustern zu bilden. Das Verfahren umfasst auch ein Ätzen des Zwischenlagendielektrikums unter Verwendung der Lochmuster des Fotoresistmusters, ein Entfernen der Lochmuster des Fotoresistmusters und ein Bilden von Kontakt- und Verdrahtungslöchern mit einer doppelstufigen Struktur im Zwischenlagendielektrikum, indem das Zwischenlagendilektrikum durch Verwendung der Grabenmuster der Fotoresistmuster geätzt wird.

Verfahren zum Herstellen von Teilbereichen in planaren Halbleiteranordnungen,die mittels dielektrischen Materials gegeneinander sowie gegen die restlichen Bereiche des Halbleiterkoerpers isoliert sind

Verfahren zum Strukturieren einer Siliziumschicht

Es wird ein Verfahren zum Strukturieren einer Siliziumschicht vorgeschlagen, bei dem eine Lackmaske (16) auf die Siliziumschicht (12) aufgebracht und die Siliziumschicht (12) selektiv zur Lackmaske (16) mittels eines Ätzgasgemisches, umfassend SF¶6¶, HBr und He/O¶2¶, geätzt wird. Die mit diesem Verfahren in die Siliziumschicht (12) geätzten Öffnungen weisen besonders steile Seitenwände auf. Darüber hinaus ist die Ätzselektivität zu einer Lackmaske deutlich verbessert.

Wafer i.e. silicon-wafer, edge protecting method for manufacturing of integrated circuits of semiconductor chip, involves removing mask, and producing local oxide layer by local oxidation in area in which pad-nitride layer is removed

The method involves producing a pad-oxide layer (2) on a wafer (1) with two main sides (10, 11) lying opposite to each other and an edge (12). A pad-nitride layer (3) is applied on the pad-oxide layer. A mask (4) is applied on the main side (10) and structured such that a strip-like area along the edge remains free. The pad-nitride layer in an area of the upper side (10) is removed upto the edge of the wafer, where the area is free from the mask. The mask is removed, and a local oxide layer is produced by local oxidation in the area in which the pad-nitride layer is removed.

Improvements in or relating to methods of providing separated metal layers side by side on a support

... 1,081,472. Etching. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. April 15, 1965 [April 21, 1964], No. 16247/65. Heading B6J. [Also in Division H1] A first metal layer is applied to a support, an etching resist mask is applied to the layer, the metal is etched away where unmasked and also to a small distance beneath the mask by undercoating, and a second metal layer is deposited on the support where unmasked, so that the two metal layers are separated by a gap at the position of the undercut. A monocrystal germanium body 1, Fig. 1, of antimony-doped N- type material 2 has formed on its upper and under sides a P-type layer 3 by diffusion of indium. The upper side is covered with a resist lacquer and the P-type layer removed from the under surface by etching. The lacquer is removed, and arsenic diffused to form an N-type layer 4 on the upper side. An N-type layer of reduced resistivity is also formed on the under side. A thin silver layer 5 is deposited on the layer 4. An etch-resist lacquer ...

Semiconductor device fabrication

Improvements in or relating to Etching Processes for Semiconductor Devices

... 1,194,730. Etching. INTERNATIONAL BUSINESS MACHINES CORP. 3 Nov., 1967 [28 Dec., 1966], No. 50053/67. Heading B6J. [Also in Divisions C7 and H1] An oxide coated surface of a semi-conductor is etched with a solution comprising monobasic ammonium phosphate and ammonium fluoride. A preferred etchant comprises an aqueous solution of 2-10% by weight of monobasic ammonium phosphate and 10-35% by weight of ammonium fluoride. The etchant is stated to be suitable for the removal of oxides from the surfaces of silicon and germanium semiconductor devices. In an example, Figs. 1A- 1E, silicon dioxide film 2 on silicon substrate 1 is selectively etched through a photoresist mask with buffered hydrofluoric acid to form apertures 3. Phosphorus pentoxide is diffused through the apertures to establish source and drain diffusion regions 4 and 5 simultaneously forming phosphosilicate glass film overcoat 6, Fig. 1B, which is selectively etched through a photoresist mask 8 with buffered hydrofluoric acid to ...

Method for producing a semiconductor device

In a method for producing a semiconductor device including etching an Al x Ga 1-x As (0 * less than or equal to * x * less than or equal to * 1) layer by a dry etching method, an etchant gas is used containing chlorine, a group V gas, and a hydrogen gas which are supplied at the same time, and said gas etching is carried out under conditions that a partial pressure of said group V gas is in a range from 8 x 10 -3 Torr to 0.08 Torr and the flow rate of said group V gas to said etching gas is lower than 2.5. A stripe-shaped SiN mask 21 extends along the ?0 1 1! direction to produce a ridge structure with planes 24, 25. Alternatively, if the mask 21 extends along the ?011! direction, a single sloping plane is produced.

Method for producing a semiconductor device

Method of forming a shallow trench isolation structure without divots in a semiconductor substrate

A method of forming a shallow trench isolation structure in a substrate (2) is described. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion (12), extending laterally over a silicon oxide film (4) and a silicon nitride film (6), and a lower portion (10) extending in a trench in a silicon substrate (2); and carrying out an isotropic etching to said upper portion (12) of the isolation silicon oxide film and the silicon oxide film (4), thereby forming an isolation trench structure without divots (Fig. 5G) in said trench in said silicon substrate. The process may involve lateral etching of the silicon nitride film (6) or involve forming sloped portions in the silicon nitride film (16) by sputter etching.

Aperture forming method

A method of forming through-holes in a multi-level interconnect system in which a layer of photo-resist is spun over a masking layer prior to mask-etching so that when the photo-resist is exposed and developed some remains in the bottom of through holes formed in the surface layer so as to protect the base layer from the mask-etching agent.

ISOLATION STRUCTURE IN MOS DEVICES AND PROCESS OF PREPARING THE SAME

Field effect transistor having a recessed gate

The device comprises a substrate (11), a source electrode (22) and a drain electrode (23), a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate electrode (29) which may be inclined toward the source or drain electrodes and formed over the recessed channel portion. A method of forming an asymmetric recessed channel using reactive ion etching is also divided. ...

Method of forming a protective layer in a semiconductor structure

A method for forming a protective layer from surface portions of a mesa-shaped semiconductor to electrically isolate a junction region formed within the semiconductor from external contaminants. A top contact electrode is formed on an upper surface of a substrate. An active region, having formed therein the junction, is formed on the bottom portion of the substrate. A support is then formed on the active region. The top contact is first used as an etching mask, and a chemical etchant is brought into contact with unmasked portions of the substrate to form a mesa-shaped structure with divergent side walls. The divergent side walls have bottom portions which include the active region and which extend beyond the periphery of the top contact electrode. The top contact is next used as an implant mask and particles are implanted in exposed portions of the side walls extending beyond the periphery of the top contact electrode to convert the exposed semiconductor material into the protective layer ...

Wet etching Al/Ti stacked layers using fluoric, periodic and sulphuric acids

In the manufacture of an electronic device in which a wiring layer 5,12,14 is formed by stacking a Ti (or alloy thereof) layer 10 on an Al (or alloy thereof) layer 11, an equal etching rate in a single etching step is obtained using an etchant comprising fluoric acid (HF), periodic acid (HIO4) and sulphuric acid (H2SO4). The total weight ratio of the fluoric acid and periodic acid is 0.05-30 wt%, the weight ratio of the sulphuric acid is 0.05-20 wt%, and the weight ratio of periodic acid to fluoric acid is 0.01-2 wt%.

Process for wet etching a semiconductor wafer

Wet etching a silicon dioxide layer from both sides of a rotating horizontally orientated silicon substrate is disclosed. The entire dioxide layer upon the top side of the substrate is removed and the bottom side layer is removed only a short distance (a) inside the rim. The etching medium comprises at least one carboxylic acid added to a hydrofluoric acid or a combination of hydrofluoric acid and ammonium fluoride. The carboxylic acid may be present as an anhydride or a salt, especially an ammonium salt. The solution may also be diluted up to 90% water. The process allows the edge of the silicon dioxide layer remaining upon the bottom of the wafer to be smooth (4') rather than jagged (4).

Silicon etchant and etching method

Disclosed is an etchant having long life, which is suppressed in decrease of etching rate when heated, that is characteristic to etchants containing a hydroxylamine, during etching of silicon, especially during anisotropic etching of silicon in a production process of an MEMS component. An etching method is also disclosed. The silicon etchant is an alkaline aqueous solution containing an alkali metal hydroxide, a hydroxylamine and an inorganic carbonate compound and having a pH of not less than 12, which is characterized by anisotropically dissolving single-crystal silicon. A method for etching silicon by using the etchant is also disclosed.

Patterning layer stacks for electronic devices

There is provided a method of patterning a stack of layers defining one or more electronic device elements, comprising: creating a first thickness profile in an uppermost portion of the stack of layers by laser ablation; and etching the stack of layers to translate the first thickness profile into a second thickness profile at a lower level; wherein the etching reduces the thickness of said uppermost portion of the stack and one or more lower layers of the stack under said uppermost portion.

Method of making integrated circuits

A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed. Mesas, the tops of which are the active regions, are formed by ion beam etching of the silicon substrate. The mesas are protected by caps of silicon nitride overlying the top and sides of the mesas during field oxide formation. Subsequently the caps of silicon nitride are removed and the exposed sides of the mesas are oxidized to form a thick layer of silicon dioxide contiguous to the mesas.

Multi-step mesa

Multi-step mesa walls are formed by pretreating one or more selected portions 262, 252 of the semiconductor material which is to be removed by etching to form the mesa to change the average removal rate of the pretreated material in the subsequent etching step; protecting by a mask 245 portions 244 etc. of the semiconductor material's surface while leaving unprotected those portions, including non-pretreated portions 272, of the surface which are to be removed to form the plateaus of the mesa wall; and exposing the semiconductor wafer to a single etching process which removes the pretreated material at different rates than it removes the non-pretreated material. Thus single etch and single masking steps may give plural depths of etch. The pre-treatment may be a doping step (N+) which is used to simultaneously provide contact areas elsewhere on the chip. ...

Method of Dividing Semiconductor Wafers.

... 1,189,582. Etching. LICENTIA PATENTVERWALTUNGS G.m.b.H. 17 May, 1968 [26 July, 1967], No. 23583/68. Heading B6J. [Also in Division Hl] A semi-conductor wafer, e.g. of Si, Ge or a III-V compound, is subdivided into smaller dice by etching through a vapour-deposited metal mask, e.g. of Cr. After etching the wafer, the metal mask may be removed by further etching with dilute HCl activated with Zn.

FABRICATION PROCESS

METHOD FOR TRANSFERRING PATTERNS ON SILICONE LADDER TYPE RESIN AND ETCHING SOLUTION USED IN SUCH METHOD

Double trench for isolation of semiconductor devices

METHOD OR PROCESS FOR ETCHING HOLES

Improvements in and relating to semi-conductive devices

... 863,612. Transistors. MULLARD Ltd. May 21, 1957, No. 16102/57. Class 37. A method of making a semi-conductor device comprises the steps of diffusing a first impurity into a semi-conductor crystal to form a relatively thick diffused layer therein, removing material from part of the crystal to a depth extending through, or through at least 70% of the diffused layer, and diffusing into the new surface thus formed a second impurity characteristic of the same conductivity type, and possibly of the same material, as the first, to produce a relatively thin diffused layer beneath the new surface. Diffusion of the second impurity may be from an applied layer or pellet, from the atmosphere, or from the first-diffused layer, and a point contact can be made to the new surface after the second diffusion step. As shown, Fig. 1, in the manufacture of a PNP transistor, a slice 1 of P-type monocrystalline germanium is heated at 830‹ C. for about 2 hours in a current of hydrogen in a chamber containing a ...

Method of producing semiconductor devices

... A recess or pit in a body of silicon is produced by crystallographically damaging a portion of the body and etching that portion to provide a substantially flat bottomed pit. Fig. 1 shows a silicon body 4 subjected to the predetermined pressure of a 3-sided diamond point 6 by means of a weighted lever 8. The body is then etched in a boiling 30% solution of potassium hydroxide for 10 minutes. Fig. 2 shows a silicon wafer 2 suitable for a transistor having an emitter recess 4 and a collector recess 6 produced as above. Sodium hydroxide may be used as the etchant and additives such as ethylene glycol (which tends to flatten the bottom of the recess) or sodium carbonate (to raise the boiling point) may be used. The effect of different concentrations of etchant on recess shape is discussed. The crystallographic damage may be caused by rotation of or scratching by the diamond point.

METHOD OF ETCHING MULTILAYERED ARTICLES

... 1527106 Etching TELETYPE CORP 9 Oct 1975 [10 Oct 1974] 41356/75 Heading B6J A layer of SiO 2 is etched with buffered HF, e.g. HF + NH 4 F, the underlying aluminium layer being passivated by the HF. The passivated layer is then treated with a substantially HF-free solution of NH 4 F to prevent deterioration thereof. Etching of the SiO 2 may be through apertures in a photoresist mask.

RECESSED OXIDE N-CHANNEL FETS

... 1499848 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [28 June 1974] 21855/75 Heading H1K A semi-conductor device comprises a P-type semi-conductor substrate 11, Fig. ID, having an N-channel FET 20-23, Fig. 2, formed therein and isolated by a recessed region 18 which has an interface with the channel region, there being a region 19 containing additional P-type dopant extending from the interface into the channel region to increase its threshold. The device is formed by providing a P-type <100>substrate having a surface protection layer 12, an oxidation barrier 13, an ion-implantation blocking layer 14, and a pattern-defining photoresist (15), Fig. 1A (not shown), exposing and developing the photoresist (15) to provide a pattern on the blocking layer 14, etching the blocking layer 14, the barrier 13 and the protecting layer 12 through the pattern, etching the substrate 11 in the exposed areas with an anisotropic etchant to obtain canted sidewalls 33, ion inplanting ...

PROCEDURE FOR the PRODUCTION OF SAME-ADJUSTING L FÖRMIGEN SIDE PANEL SPACER DISTANCE PIECES

PROCEDURE FOR MASKING OF SILICON FOR AN ANISOTROPIC WET CORROSION

AZEOTROP SIMILAR COMPOSITION OF 1,2-DICHLOR-3,3,3-TRIFLUORPROPEN AND HYDROGEN FLUORIDE

PRODUCTION OF CHEMICAL MARKINGS

VERFAHREN ZUR HERSTELLUNG MEHRERER HALBLEITERBAUELEMENTE

SPINNING ON PROTECTIVE COATINGS FOR THE WET CORRODING PROCESSING OF MICROELECTRONIC SUBSTRATES

MANUFACTURING PROCESS OF A SEMICONDUCTOR LAYER WITH NOT ADAPTED LATTICE

SMALL-AREA THIN FILM TRANSISTOR.

PROTECTING LAYER OF METAL FOR STRUCTURE ON SEMICONDUCTOR SUBSTRATE WHEN CORRODING WITH KOH

PROCEDURE FOR THE PRODUCTION OF A STRUCTURE AND A PROCEDURE FOR PREPARING A SEMICONDUCTING ARRANGEMENT WITH THE HELP OF THIS PROCEDURE

Procedure for manufacturing monoliths

Method of forming enhanced transistor gate using e-beam radiation and integrated circuit including this transistor gate

A method of producing thin silicon epitaxial films

METHOD FOR LIMITING DIVOT FORMATION IN POST SHALLOW TRENCH ISOLATION PROCESSES

Metal-assisted chemical etch to produce porous group iii-v materials

Improved method for etching vias

METHOD OF MANUFACTURING THIN PLATES HAVING SURFACE STRUCTURES OF DIFFERENT DEPTHS OR HEIGHTS

Composition and method for removing probing ink and negative photoresist from silicon wafers

Methods and apparatus for cleaning semiconductor substrates after polishing of copper film

METHOD OF MAKING A SEMICONDUCTOR ARTICLE AND THE ARTICLE PRODUCED THEREBY

METHOD OF PREFERENTIALLY ETCHING OPTICALLY FLAT MIRROR FACETS IN INGAASP/INP HETEROSTRUCTURES

METHOD FOR SELECTIVE ETCHING OF TITANIUMDIOXIDE

A method of selectively etching a titanium oxide layer with a view to the formation of a mask for the localization of the anodic oxidation of an underlying metallic layer. The method is characterized in that the material comprising the said titanium oxide layer is dipped in a solution of hydrogen peroxide and ammonia. Application to the formation of contacts on semiconductor devices.

ETCHANT FOR SILICON DIOXIDE FILMS DISPOSED ATOP SILICON OR METALLIC SILICIDES

An etchant comprising a solution of hydrogen fluoride dissolved in an organic solvent such as glycerine. The solution is substantially free of unbound water and ammonium fluoride. The etchant is particularly suitable for removing silicon dioxide disposed atop a metallic silicide formed in a silicon semiconductor where the silicon may be exposed.

PROCESS FOR ETCHING HOLES

... - PROCESS FOR ETCHING HOLES A method for etching at least one aperture having a defined crystallographic geometry in single crystals which includes masking the crystal to protect predetermined portions thereof from being etched, and then anisotropically etching with a mixture of sulfuric acid and phosphoric acid.

SOLUBLE SURFACTANT ADDITIVES FOR AMMONIUM FLUORIDE/HYDROFLUORIC ACID OXIDE ETCHANT SOLUTIONS

SOLUBLE SURFACTANT ADDITIVES FOR AMMONIUM FLUORIDE/HYDROFLUORIC ACID OXIDE ETCHANT SOLUTIONS Silicon trioxide etching solutions with soluble surfact additives are provided. The improved silicon dioxide etchants are produced by adding soluble perfluronated surfactant additives to standard oxide etchants in the manufacture of integrated circuits. These surfactant additives are unique because they remain dissolved in the oxide etchant (ammonium fluoride/hydrofluoric acid mixture) even after 0.2 micron filtration. In addition, the filtered solutions retain their surface active properties and are low in metallic ion impurities. The surfactant additives provide etchant solutions with lower surface tensions, which improves substrate wetting and yields better etchant performance. The surfactant does not leave residues or adversely affect etchant profiles.

METHOD OF PREFERENTIALLY ETCHING OPTICALLY FLAT MIRROR FACETS IN INGAASP/INP HETEROSTRUCTURES

METHOD OF PREFERENTIALLY ETCHING OPTICALLY FLAT MIRROR FACETS IN InGaAsP/InP HETEROSTRUCTURES Highly reproducible, optically flat mirror facets are created by etching a predetermined area of the InGaAsP/InP heterostructure system to expose a crystallographic surface throughout the entire heterostructure system. Contact of the exposed surface with HCl causes a preferred crystallographic plane to be exposed as an optically flat mirror face.

METHOD OF MANUFACTURING OXIDIZING AGENT AND METHOD OF OXIDATION BY THE USE OF THE OXIDIZING AGENT

A method of manufacturing an oxidizing agent comprises the step of oxidizing polyoxyalkylene having an average molecular weight of 1,000 to 30,000 and being represented by the following general formula: ? R - O ?n where R stands for alkylene group represented by (CH2)m where m = 2 or 3. A solution such as an aqueous solution containing polyoxyalkylene of more than 1% by weight, or a melted polyoxyalkylene is treated by supplying an oxidizing gas thereinto to oxidize and decompose the polyoxyalkylene into the oxidizing agent. A method of oxidation by the use of the oxidizing agent manufactured by the above-described method is applied to, for example, a surface treatment of semiconductor or metal.

METHOD FOR STRIPPING LAYERS OF ORGANIC MATERIAL

HIGH SPEED, HIGH VOLTAGE TRANSISTOR

ETCHING OF GROUP SIIIU-SVU SEMICONDUCTORS

TELEVISION CAMERA TUBES

REMOVAL OF PROJECTIONS ON EPITAXIAL LAYERS

REMOVAL OF PROJECTIONS ON EPITAXIAL LAYERS A method for removing projections from the surface of epitaxially-deposited semiconductor layers is described. These projections can adversely affect the results of photolithographic processing. The method comprises forming an oxide layer on the surface and mechanically fracturing the oxide-coated projections. In the ensuing step anisotropic semiconductor etchants are applied to the surface to remove the projections selectively.

METHOD FOR SELECTIVELY ETCHING ALXGAL-XAS MULTILAYER STRUCTURES

ETCHANT FOR SILICON DIOXIDE FILMS DISPOSED ATOP SILICON OR METALLIC SILICIDES

IMAGING METHOD AND MATERIAL

METHOD FOR STRIPPING LAYERS OF ORGANIC MATERIAL

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED BY MEANS OF THE METHOD

Spacer double patterning that prints multiple cd in front-end-of-line

A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.

Self aligned triple patterning

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.

Methods for Pitch Reduction

An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches. Adjacent pairs of lines are separated by a first trench in the plurality of first trenches, and each pair of lines comprises a first line and a second line defining a corresponding second trench in the plurality of second trenches.

Method for forming fine pattern of semiconductor device

A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Integrated circuit fabrication methods utilizing embedded hardmask layers for high resolution patterning

Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.

Multiple Patterning Method

An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Methods for fabricating semiconductor devices and semiconductor devices using the same

A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Non-conformal hardmask deposition for through silicon etch

The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps.

Shrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask Material

In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Method of reducing striation on a sidewall of a recess

A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF 4 , HBr, O 2 and He. Next, the substrate is etched by taking the patterned photoresist layer as a mask after the repairing process. Finally, the patterned photoresist layer is removed.

Semiconductor device manufacturing apparatus

A semiconductor device manufacturing apparatus includes: a first pattern forming unit for forming a first pattern by patterning a first mask material layer; a boundary layer forming unit for forming a boundary layer at sidewall portions and top portions of the first pattern; a second mask material layer forming unit for forming a second mask material layer so as to cover a surface of the boundary layer; a second mask material removing unit for removing a part of the second mask material layer to expose top portions of the boundary layer; a boundary layer etching unit for forming a second pattern by etching and removing the boundary layer and forming a void between the sidewall portions of the first pattern and the second mask material layer; and a trimming unit for reducing a width of the first pattern and a width of the second pattern to predetermined widths.

Method for Reducing a Minimum Line Width in a Spacer-Defined Double Patterning Process

The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.

Layer Alignment in FinFET Fabrication

Methods for aligning layers more accurately for FinFETs fabrication. An embodiment of the method, comprises: forming a plurality of dummy line features and a plurality of spacer elements according to a first pattern; removing portions of the plurality of spacer elements and portions of the plurality of dummy line features according to a second pattern; defining a reference area by removing some unwanted spacer elements according to a third pattern; aligning a front-end-of-line (FEOL) layer in X direction with the reference area defined by the third pattern; and aligning the FEOL layer in Y direction with the plurality of spacer elements defined by the first pattern. The reference area may be an active area or an alignment mask. The plurality of dummy line features and the plurality of spacer elements are formed on a substrate. The FEOL layer may be a poly layer or a shield layer.

Lithographic Method for Making Networks of Conductors Connected by Vias

A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING ANION GROUP

There is provided a method of making a semiconductor device utilizing a resist underlayer film forming composition comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): RRSi(R)(1). 1. A production method of a semiconductor device , comprising:applying a resist underlayer film forming composition comprising a silane compound containing an anion group, onto a semiconductor substrate and baking the composition to form a resist underlayer film;wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof;applying a composition for a resist onto the resist underlayer film to form a resist film;exposing the resist film to light;developing the resist after the exposure to obtain a resist pattern;etching the resist underlayer film using the resist pattern as a protecting film; andprocessing the semiconductor substrate using the patterned resist and the patterned resist underlayer film.2. A production method of a semiconductor device , comprising:forming an organic underlayer film on a semiconductor substrate;applying a resist underlayer film forming composition comprising a silane compound containing an anion group onto the organic underlayer film and baking the composition to form a resist underlayer film;wherein the silane compound containing an anion group is a hydrolyzable organosilane in ...

Multi-layer pattern for alternate ald processes

A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.

Inverse spacer processing

A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.

CARBAZOLE NOVOLAK RESIN

There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): 4. The production method according to claim 3 , wherein the hard mask is formed by depositing an inorganic substance on the resist underlayer film. This is a Division of application Ser. No. 13/377,055 filed Dec. 8, 2011, which in turn is a 371 of International Application No. PCT/JP2010/060223, filed Jun. 16, 2010, which claims the benefit of Japanese Patent Application No. JP2009-146289 filed Jun. 19, 2009. The disclosure of the prior applications is hereby incorporated by reference herein in its entirety.The present invention relates to a carbazole novolak resin including a particular structure. It further relates to a resist underlayer film forming composition including the carbazole novolak resin, a resist underlayer film formed from the composition, a resist pattern forming method using the resist underlayer film forming composition, and a production method of a semiconductor device. It also relates to a high refractive index film forming composition including the carbazole novolak resin, a high refractive index film that is formed from the composition and has transparency in a visible region, and an electronic device including the high refractive index film.Conventionally, microfabrication of semiconductor substrates has been carried out by lithography using a photoresist composition in the production of semiconductor devices. For the microfabrication of semiconductor substrates, there is a known fabrication method in which a resist film formed from a photoresist composition is formed on a substrate to be fabricated such as a silicon wafer, active rays such as ultraviolet rays are applied onto the resist film through a mask pattern with a pattern that is transferred to ...

PATTERN FORMATION METHOD AND POLYMER ALLOY BASE MATERIAL

According to one embodiment, a pattern formation method is provided, the pattern formation includes: laminating a self-assembled monolayer and a polymer film on a substrate; causing chemical bonding between the polymer film and the self-assembled monolayer by irradiation with an energy beam to form a polymer surface layer on the self-assembled monolayer; and forming on the polymer surface layer a polymer alloy having a pattern of phase-separated structures. 1. A pattern formation method comprising:laminating a self-assembled monolayer and a polymer film on a substrate;causing chemical bonding between the polymer film and the self-assembled monolayer by irradiation with an energy beam to thereby form a polymer surface layer on the self-assembled monolayer; andforming on the polymer surface layer a polymer alloy having a pattern of phase-separated structures.2. The pattern formation method according to claim 1 , further comprisingremoving a portion of the polymer film on the polymer surface layer, which is not chemically bonded after the formation of the polymer layer.3. The pattern formation method according to claim 1 , whereina partial region on the substrate is selectively irradiated with the energy beam to cause selective chemical bonding between the polymer film on the partial region and the self-assembled monolayer, thereby forming the polymer surface layer; andthe polymer alloy is formed after removing the polymer film on a region which is not irradiated with the energy beam.4. The pattern formation method according to claim 3 , whereinthe phase-separated structures of the polymer alloy are formed of a first phase and a second phase;the first phase is formed on the polymer surface layer; andthe second phase is formed on a surface of the self-assembled monolayer exposed by the removal of the polymer film on the region which is not irradiated with the energy beam.5. The pattern formation method according to claim 1 , further comprising:coating a photoresist on ...

PATTERN FORMING METHOD

In a pattern forming method, a pattern having at least either a recess or a protrusion of a curable composition is formed of a curable composition by curing the curable composition into a cured film with a mold having a surface provided with at least either a recess or a protrusion, and separating the mold from the curable composition. The method includes (i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film, (ii) generating a gas from the gas generation region, and (iii) separating the mold from the cured film during or after the step of (ii). 1. A pattern forming method for forming a pattern having at least one of a recess and a protrusion of a curable composition by curing the curable composition disposed on a work substrate into a cured film in a state where a mold having a surface provided with at least one of a recess and a protrusion is substantially in contact with the curable composition , and separating the mold from the cured film , the method comprising:(i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film;(ii) generating a gas from the gas generation region; and(iii) separating the mold from the cured film during or after the step of (ii).2. The pattern forming method according to claim 1 , wherein the gas generation region is formed so that the curable composition will not generate a gas in the step of (ii).3. The pattern forming method according to claim 1 , wherein the curable composition is a photo-curable composition that will be cured by being exposed to light.4. The pattern forming method according to claim 1 , wherein the gas generator agent is a compound that will generate a gas by receiving a pressure claim 1 , and the step of (ii) is performed by ...

Methods of forming patterns of a semiconductor device

Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Etch resistant alumina based coatings

Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.

ETCHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

In an etching method of an embodiment, a film to be etched, which includes a first metallic element, is formed on a semiconductor substrate. A carbide layer, which includes a second metallic element, is formed on the film to be etched. The carbide layer is etched. The film to be etched is etched by using the carbide layer as a mask. 1. An etching method comprising:forming a film to be etched, which includes a first metallic element, on a semiconductor substrate;forming a carbide layer, the carbide layer including a second metallic element, on the film to be etched;etching the carbide layer into a desired pattern; andetching the film to be etched by using the carbide layer as a mask.2. The etching method of claim 1 , whereinthe first metallic element is an element selected from Pt, Au, Ag, Ir, Pd, Rh, Ru and Os, andthe second metallic element is an element selected from Ti, Ta, W, Mo, Nb and Hf.3. The etching method of claim 1 , wherein the carbide layer is any one of a TaC film and a TiC film.4. The etching method of claim 1 , wherein the etching of the film to be etched is plasma etching performed with a Clgas and an Ogas being supplied.5. The etching method of claim 1 , further comprising:forming a hard mask layer on the carbide layer, and thereafter etching the hard mask layer; andetching the carbide layer by using the hard mask layer as a mask.6. The etching method of claim 5 , wherein the hard mask layer is a silicon oxide film.7. The etching method of claim 5 , wherein the etching of the hard mask layer is plasma etching performed with a fluorocarbon gas being supplied.8. A method of manufacturing semiconductor device comprising:forming a stack structure above a substrate, the stack structure including a lower electrode, a magnetoresistive effect element, and an upper electrode, the stack structure including a first metallic element;forming a carbide layer, which includes a second metallic element, on the stack structure;etching the carbide layer into a ...

SUBSTRATE PROCESSING SYSTEM, GAS SUPPLY UNIT, METHOD OF SUBSTRATE PROCESSING, COMPUTER PROGRAM, AND STORAGE MEDIUM

The present invention is to provide a technique for uniformly processing a substrate surface in the process of processing a substrate by supplying a gas. The inside of a shower head having gas-jetting pores for supplying a gas to a substrate is partitioned into a center section from which a gas is supplied to the center portion of a substrate, and a peripheral section from which a gas is supplied to the peripheral portion of the substrate, and the same process gas is supplied to the substrate from these two sections at flow rates separately regulated. The distance from the center of the center section of the gas supply unit to the outermost gas-jetting pores in the center section is set 53% or more of the radius of the substrate. Moreover, an additional gas is further supplied to the peripheral portion of the substrate. 111-. (canceled)12. A method of processing a substrate by the use of a substrate processing system comprising:a processing vessel,a table that is placed in the processing vessel and on which a substrate will be placed,a gas supply unit set on the top of the processing vessel facing the table, including of a center section that corresponds to the center portion of the substrate and has a large number of gas-jetting pores, and a peripheral section that corresponds to the peripheral portion of the substrate and has a large number of gas jetting pores,a first-gas supply means of supplying a common gas to the center and peripheral sections of the gas supply unit at flow rates separately regulated,a second-gas supply means of supplying an additional gas, in addition to the common gas, to the peripheral section of the gas supply unit, anda means of evacuating the processing vessel,the method comprising the steps of:supplying to the substrate from the center and peripheral sections of the gas supply unit the common process gas that has been supplied to the two sections by the first-gas supply means at flow rates separately regulated,supplying, in addition to ...

ETCHING METHOD, SUBSTRATE PROCESSING METHOD, PATTERN FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT

A fluorocarbon layer is formed on a silicon substrate that is a to-be-processed substrate (step A). A resist layer is formed on the thus-formed fluorocarbon layer (step B). Then, the resist layer is patterned into a predetermined shape by exposing the resist layer to light by means of a photoresist layer (step C). The fluorocarbon layer is etched using the resist layer, which has been patterned into a predetermined shape, as a mask (step D). Next, the resist layer served as a mask is removed (step E). After that, the silicon substrate is etched using the remained fluorocarbon layer as a mask (step F). Since the fluorocarbon layer by itself functions as an antireflective film and a harm mask, the reliability of processing can be improved, while reducing the cost. 1. An etching method , wherein a to-be-processed substrate is etched using a fluorocarbon layer patterned on the to-be-processed substrate as a mask.2. The etching method of claim 1 , wherein at least one of a SiCN layer claim 1 , a SiCO layer and an amorphous carbon layer is interposed between the fluorocarbon layer and the to-be-processed substrate.3. The etching method of claim 1 , wherein at least one of a SiCN layer claim 1 , a SiCO layer and an amorphous carbon layer is formed above the fluorocarbon layer.4. A substrate processing method comprising:a fluorocarbon layer forming process in which a fluorocarbon (CFx: x is a random number) layer is formed on the to-be-processed substrate;a resist layer forming process in which a resist layer is formed on the fluorocarbon layer; a patterning process in which the resist layer is patterned into a predetermined shape;a fluorocarbon layer etching process in which the fluorocarbon layer is etched using the resist layer patterned into a predetermined shape as a mask to pattern the fluorocarbon layer; anda to-be-processed substrate etching process in which the to-be-processed substrate is etched using the patterned fluorocarbon layer as a mask.5. The substrate ...

RESIST PATTERN THICKENING MATERIAL, METHOD FOR FORMING RESIST PATTERN, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern to be thickened, e.g., in form of lines and spaces pattern, can thicken the resist pattern to be thickened regardless of the size of the resist pattern to be thickened; and which is suited for forming a fine space pattern or the like, exceeding exposure limits. The present invention also provides a process for forming a resist pattern and a process for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized. 2. The method for forming a resist pattern according to claim 1 , wherein after the applying of the resist pattern thickening material over the surface of the workpiece so as to cover the surface of the resist pattern claim 1 , the resist pattern thickening material is heated.3. The method for forming a resist pattern according to claim 1 , wherein after the heating of the resist pattern thickening material claim 1 , the resist pattern thickening material is rinsed.4. The method for forming a resist pattern according to claim 3 , wherein the resist pattern thickening material is rinsed with at least any one of water and an alkali developer.65. The method for manufacturing a semiconductor device according to claim claim 3 , wherein the forming of the resist pattern further comprises heating and rinsing the surface of the resist pattern thickening material after the applying of the resist pattern thickening material over the surface of the workpiece so as to cover the surface of the resist pattern.75. The method for manufacturing a semiconductor device according to claim claim 3 , further comprising applying a surfactant over the surface of the resist pattern before the forming of the resist pattern.8. The method for manufacturing a semiconductor device according to claim 7 , wherein the surfactant is at least one selected from ...

METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES

An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. 140-. (canceled)41. A method of fabricating an integrated circuit structure on a support structure , the method comprising:forming a plurality of linearly extending polymer lines in a matrix phase material;removing a portion of the matrix phase material;cutting the polymer lines at an angle relative a linearly extending direction to form respective angled end faces at each of the polymer lines, the respective angled end faces being spaced in the linearly extending direction; andforming an extension of each of the polymer lines at each respective angled end face.42. The method of claim 41 , wherein the removing the portion of the matrix phase material includes exposing the portion of the matrix phase material to ultraviolet light and immersing the matrix phase material in a developer solution.43. The method of claim 42 , wherein the developer solution is an acidic metal salt solution.44. The method of claim 41 , wherein the polymer comprises polystyrene and the matrix phase material comprises polymethylmethacrylate.45. The method of claim 41 , wherein the cutting is performed by using a remaining portion of the matrix phase material as an etch mask to cut the polymer lines at an angle.46. ...

Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing

Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.

PHOTOLITHOGRAPHIC METHODS

Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices. 1. A method of forming an electronic device , comprising:(a) providing a semiconductor substrate comprising one or more layers to be patterned;(b) forming a photoresist layer over the one or more layers to be patterned;(c) coating a photoresist overcoat composition over the photoresist layer, wherein the overcoat composition comprises a basic quencher, a polymer and an organic solvent;(d) exposing the layer to actinic radiation; and(e) developing the exposed film with an organic solvent developer.2. The method of claim 1 , wherein the organic solvent developer comprises 2-heptanone.3. The method of claim 1 , wherein the organic solvent developer comprises n-butyl acetate.4. The method of claim 1 , wherein the organic solvent developer comprises n-butyl propionate.5. The method of claim 1 , wherein the organic solvent of the photoresist overcoat composition comprises an alkyl butyrate.6. The method of claim 5 , wherein the organic solvent of the photoresist overcoat composition comprises a C-Calkyl butyrate.7. The method of claim 1 , wherein the organic solvent of the photoresist overcoat composition comprises an alkyl propionate.8. The method of claim 7 , wherein the organic solvent of the photoresist overcoat composition comprises a C-Calkyl propionate.9. The method of claim 1 , wherein the organic solvent of the photoresist overcoat composition comprises a ketone.10. The method of claim 9 , wherein the solvent comprises a C-Cbranched ketone. This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 61/533,106, filed Sep. 9, 2011, the entire contents of which are incorporated herein by reference.The invention relates ...

REMOVABLE TEMPLATES FOR DIRECTED SELF ASSEMBLY

A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate. 1. A method of fabricating a self-assembled template , comprising:forming a pattern of sacrificial posts on a substrate, the pattern configured to direct self-assembly of a block copolymer;applying the block copolymer to the substrate having the pattern of sacrificial posts; andperforming an etching process to remove a non-final pattern block of the block copolymer and the sacrificial posts such that a final pattern remains on the substrate.2. The method of claim 1 , further comprising:performing a chemical functionalization with respect to the sacrificial posts.3. The method of claim 2 , wherein performing the chemical functionalization comprises:applying a surface layer having an affinity to the non-final pattern block on the sacrificial posts.4. The method of claim 3 , wherein the surface layer is selectively applied according to a desired morphology of the final pattern.5. The method of claim 1 , wherein forming the pattern of sacrificial posts on the substrate comprises:applying a polymethylmethacrylate (PMMA) film; andperforming electron beam lithography at a dose/energy that causes the PMMA film to behave as a negative resist to pattern the PMMA into the pattern of sacrificial posts on the substrate.6. The method of ...

TREATMENT LIQUID FOR INHIBITING PATTERN COLLAPSE IN MICROSTRUCTURE AND METHOD OF MANUFACTURING MICROSTRUCTURE USING THE SAME

The objects of the present invention are to provide a treatment liquid able to inhibit pattern collapse in a microstructure such as a semiconductor device or a micromachine, as well as a method of manufacturing a microstructure using the same. 1. A treatment liquid for inhibiting pattern collapse in a metal microstructure comprising an alkylphosphonic acid or salt thereof in which said alkyl moiety contains 6 to 18 carbon atoms; water; and a glycol of the following formula (1) or (2):{'br': None, 'sub': 2', '4', 'n, 'sup': '1', 'HO(CHO)R\u2003\u2003(1)'}{'br': None, 'sub': 3', '6', 'm, 'sup': '1', 'HO(CHO)R\u2003\u2003(2)'}{'sup': '1', 'sub': 1', '4, 'wherein Rdenotes a hydrogen atom or a C-Calkyl group, n denotes an integer of 2 to 4, and m denotes an integer of 1 to 3.'}2. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the microstructure contains at least one metal selected from among titanium claim 1 , tantalum and aluminum.3. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 0.1 ppm to 10 claim 1 ,000 ppm.4. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 0.5 ppm to 1 claim 1 ,000 ppm.5. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 5 ppm to 800 ppm.6. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of glycols is 60% by weight to 99% by weight.7. A method of manufacturing a microstructure containing at least one metal selected from among titanium claim 1 , tantalum and aluminum claim 1 , the method comprising: [{'br': None, 'sub': 2', '4', 'n, 'sup': '1', 'HO(CHO)R\u2003\u2003(1)'}, {'br': None, 'sub': 3', '6', 'm, 'sup': '1', 'HO(CHO)R\u2003\u2003(2)'}], 'in rinsing steps following wet-etching or dry-etching, using a treatment liquid for ...

METHOD OF FABRICATING AND CORRECTING NANOIMPRINT LITHOGRAPHY TEMPLATES

A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence. 1. A method of fabricating a nanoimprint lithography template , comprising:installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage, and a template stage;mounting a template substrate on the template stage; andexposing regions on the template substrate with light emitted by the light source in a scanning process performed by the equipment, characterized in that at least one part of the scanning lithography equipment is inclined such that a line passing through a center of light exposing each of the regions, respectively, in a first direction in which the light propagates towards the template substrate is incident on the exposure region at an oblique angle.2. The method of claim 1 , wherein the scanning process includes passing the light through an elongated slit interposed between the reticle and the template substrate with respect to an optical axis of the equipment extending in said direction in which the light propagates towards the template substrate.3. The method of claim 2 , wherein the scanning process includes moving the reticle stage and the template stage in a second direction perpendicular to the first direction in which the slit is elongated.4. The method of claim 3 , wherein the scanning process is characterized in that the reticle stage is inclined relative to the template substrate.5. The method of claim 3 , wherein the scanning process includes moving the template stage to be inclined.6. The method of claim 1 , wherein the scanning ...

Non-bridging contact via structures in proximity

A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

COMPOSITION FOR FORMING A RESIST UNDERLAYER FILM INCLUDING HYDROXYL GROUP-CONTAINING CARBAZOLE NOVOLAC RESIN

There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: 2. The composition for forming a resist underlayer film according to claim 1 , wherein in formula (1) claim 1 , R claim 1 , R claim 1 , R claim 1 , and Rare hydrogen atoms claim 1 , and Ris a naphthalene ring or a pyrene ring.3. The composition for forming a resist underlayer film according to claim 1 , wherein in formula (2) claim 1 , Ar is a naphthalene ring claim 1 , Rand Rare hydrogen atoms claim 1 , and Ris a naphthalene ring or pyrene ring.4. The composition for forming a resist underlayer film according to claim 1 , further comprising a cross-linking agent.5. The composition for forming a resist underlayer film according to claim 1 , further comprising an acid and/or an acid generator.6. A resist underlayer film claim 1 , obtained by applying the composition for forming a resist underlayer film according to onto a semiconductor substrate claim 1 , and then baking the composition.7. A method for forming a resist pattern that is used in semiconductor production claim 1 , the method comprising a step of forming an underlayer film by applying the composition for forming a resist underlayer film according to onto a semiconductor substrate claim 1 , and then baking the composition.8. A method for producing a semiconductor device claim 1 , the method comprising the steps of: forming an underlayer film using the composition for forming a resist underlayer film according to on a semiconductor substrate; forming a resist film on the underlayer film; forming a patterned resist film by irradiation of light or electron beams and developing; etching the underlayer film according to the patterned resist film; and ...

USE OF SURFACTANTS HAVING AT LEAST THREE SHORT-CHAIN PERFLUORINATED GROUPS RF FOR MANUFACTURING INTEGRATED CIRCUITS HAVING PATTERNS WITH LINE-SPACE DIMENSIONS BELOW 50 NM

The use of surfactants A, the 1% by weight aqueous solutions of which exhibit a static surface tension <25 mN/m, the said surfactants A containing at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, heptafluoroisopropyl, and pentafluorosulfanyl; for manufacturing integrated circuits comprising patterns having line-space dimensions below 50 nm and aspect ratios >3; and a photolithographic process making use of the surfactants A in immersion photoresist layers, photoresist layers exposed to actinic radiation, developer solutions for the exposed photoresist layers and/or in chemical rinse solutions for developed patterned photoresists comprising patterns having line-space dimensions below 50 nm and aspect ratios >3. By way of the surfactants A, pattern collapse is prevented, line edge roughness is reduced, watermark defects are prevented and removed and defects are reduced by removing particles. 1. A process for manufacturing an integrated circuit , the process comprising:manufacturing an integrated circuit with a surfactant A,wherein a 1% by weight aqueous solution of the surfactant A has a static surface tension of less than 25 mN/m;the surfactant A comprises at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, and pentafluorosulfanyl; andthe integrated circuits comprises a pattern having a line-space dimension below 50 nm and an aspect ratio of greater than 3.2. The process according to claim 1 , wherein the perfluorinated groups Rf are bonded to the same multi-valent central moiety B.4. The process according to claim 2 , wherein the surfactant A comprises a hydrophobic group D.6. The process according to claim 1 ,wherein manufacturing the integrated circuit with surfactant A comprises manufacturing with the surfactant A in an immersion ...

ORGANIC FILM COMPOSITION, METHOD FOR FORMING ORGANIC FILM AND PATTERNING PROCESS USING THIS, AND HEAT-DECOMPOSABLE POLYMER

The invention provides an organic film composition comprises (A) a heat-decomposable polymer, (B) an organic solvent, and (C) an aromatic ring containing resin, with the weight reduction rate of (A) the heat-decomposable polymer from 30° C. to 250° C. being 40% or more by mass. There can be provided an organic film composition having not only a high dry etching resistance but also an excellent filling-up or flattening characteristics. 1. An organic film composition comprising (A) a heat-decomposable polymer , (B) an organic solvent , and (C) an aromatic ring containing resin , with the weight reduction rate of (A) the heat-decomposable polymer from 30° C. to 250° C. being 40% or more by mass.2. The organic film composition according to claim 1 , wherein (A) the heat-decomposable polymer is in the state of liquid at 100° C. with the weight reduction rate thereof from 30° C. to 250° C. being 70% or more by mass.9. The organic film composition according to claim 1 , wherein (C) the aromatic ring containing resin contains a naphthalene ring.16. The organic film composition according to claim 1 , wherein (C) the aromatic ring containing resin comprises a resin (C3) that is obtained by polycondensation of one or two or more aromatic ring containing compounds with benzophenone claim 1 , naphthophenone claim 1 , or fluorenone.17. The organic film composition according to claim 9 , wherein (C) the aromatic ring containing resin comprises a resin (C3) that is obtained by polycondensation of one or two or more aromatic ring containing compounds with benzophenone claim 9 , naphthophenone claim 9 , or fluorenone.18. The organic film composition according to claim 10 , wherein (C) the aromatic ring containing resin comprises a resin (C3) that is obtained by polycondensation of one or two or more aromatic ring containing compounds with benzophenone claim 10 , naphthophenone claim 10 , or fluorenone.19. The organic film composition according to claim 11 , wherein (C) the aromatic ...

FILM FORMING DEVICE, SUBSTRATE PROCESSING SYSTEM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A substrate processing system of forming a resist pattern having a molecular resist of a low molecular compound on a substrate includes a film forming device configured to form a resist film on the substrate; an exposure device configured to expose the formed resist film; and a developing device configured to develop the exposed resist film. The film forming device includes a processing chamber configured to accommodate therein the substrate; a holding table that is provided in the processing chamber and configured to hold the substrate thereon; a resist film deposition head configured to supply a vapor of the molecular resist to the substrate held on the holding table; and a depressurizing device configured to depressurize an inside of the processing chamber to a vacuum atmosphere. 1. A film forming device of forming a resist film having a molecular resist of a low molecular compound on a substrate , the film forming device comprising:a processing chamber configured to accommodate therein the substrate;a holding table that is provided in the processing chamber and configured to hold the substrate thereon;a resist film deposition head configured to supply a vapor of the molecular resist to the substrate held on the holding table; anda depressurizing device configured to depressurize an inside of the processing chamber to a vacuum atmosphere.2. The film forming device of claim 1 , further comprising:a sacrificial film deposition head configured to supply, onto a target film on the substrate, a vapor of a film forming material used in forming a sacrificial film that is formed between the target film and the resist film and serves as a mask when etching the target film;an anti-reflection film deposition head configured to supply, onto the sacrificial film, a vapor of a film forming material used in forming an anti-reflection film formed between the sacrificial film and the resist film; anda transfer device configured to transfer the substrate held on the holding table, ...

NANOMETRIC IMPRINT LITHOGRAPHY METHOD

A nanoimprint lithography method, including: pressing a mold in a photosensitive resin to form at least one imprint pattern defined by a stamped area and an adjacent area, the adjacent area being less stamped or not stamped at all, and being thicker than the stamped area; and exposure to a certain amount of sunlight. Respective thicknesses of the two areas are defined such that the two areas absorb a different amount of the sunlight and the amount of sunlight provided by the exposure is predetermined so as to be great enough to activate the resin in whichever of the two areas has the greater absorption, and so as not to be great enough to activate the other of the two areas. 119-. (canceled)20. A nanometric imprint lithography method comprising:a preparation during which a photosensitive resist is disposed on a substrate;at least one pressing a mold in the resist to form in the resist at least one imprint pattern delimited at least partly by two adjacent areas, one of the two areas having a thickness less than a thickness of the other one of the two areas;exposing at least the two areas during which the two areas receive a same insolation dose; andwherein the thicknesses of the two areas are defined so that, to be activated, the resist in one of the two areas requires an insolation dose different from the insolation dose necessary for activating the resist in the other one of the two areas, and the insolation dose afforded by the exposure is determined so as to be sufficiently great to activate the resist in only one of the two areas and so as not to be sufficiently great to activate the other one of the two adjacent areas.21. A method according to claim 20 , wherein the absorption of the insolation dose by the resist according to its thickness defines a substantially sinusoidal curve claim 20 , and wherein the thickness of the resist in one of the two areas corresponds substantially to a maximum of the sinusoidal curve and the thickness of the resist in the other ...

Methods of Manufacturing Semiconductor Devices

Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

COMPOSITION FOR FORMING PATTERN REVERSAL FILM AND METHOD FOR FORMING REVERSAL PATTERN

There is provided a silicon-containing composition for forming a pattern reversal film that can be reworked by an organic solvent that is normally used for the removal of resist patterns. A composition for forming a pattern reversal film, characterized by comprising: polysiloxane; an additive; and an organic solvent, wherein the polysiloxane has a structural unit of Formula (1) and a structural unit of Formula (2): 2. The composition for forming a pattern reversal film according to claim 1 , wherein the additive is an organic acid selected from the group consisting of maleic acid claim 1 , citric acid claim 1 , salicylic acid claim 1 , 3-hydroxybenzoic acid claim 1 , 4-hydroxybenzoic acid claim 1 , 2 claim 1 ,6-dihydroxybenzoic acid claim 1 , 3 claim 1 ,5-dihydroxybenzoic acid claim 1 , gallic acid claim 1 , phthalic acid claim 1 , pyromellitic acid claim 1 , and ascorbic acid.3. The composition for forming a pattern reversal film according to claim 1 , wherein the organic solvent is selected from Calcohols.4. The composition for forming a pattern reversal film according to claim 1 , wherein the polysiloxane contains the structural unit of Formula (1) and the structural unit of Formula (2) in a molar ratio of 50:50 to 99:1.5. A method for forming a reversal pattern claim 1 , the method comprising:forming a resist pattern on a substrate to be treated;{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'applying the composition for forming a pattern reversal film as claimed in so as to cover the pattern of the resist pattern, heating the composition at a temperature of 80° C. to 180° C., and forming a pattern reversal film;'}etch-backing the pattern reversal film and exposing the surface of the resist pattern; andremoving the resist pattern and forming a reversal pattern.6. A method for removing a pattern reversal film claim 1 , the method comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'peeling a pattern reversal film obtained by covering a resist pattern ...

Integrated Circuit Method With Triple Patterning

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features. 1. An integrated circuit (IC) design method comprising:receiving an IC design layout having a plurality of IC features;identifying, from the IC design layout, at least one of first IC features violating at least one of a plurality of design rules; andgenerating a modified IC design layout based on the identified IC feature, wherein the modified IC design layout includes a first modified IC feature for generating a first photomask and a second modified IC feature for generating a second photomask.2. The method of claim 1 , wherein the first modified IC feature includes a connecting feature claim 1 , and the second modified IC feature includes a trimming feature.3. The method of claim 1 , wherein the design rules include:a feature design rule for defining a minimum length of the IC feature; anda relational design rule for defining a minimum spacing between at least two IC features.4. The method of claim 3 , wherein the method further includes:identifying, from the IC design layout, a second IC feature not violating at least one of the design rules.5. The method of claim 4 , wherein the identified second IC feature violates the relational design rule that the identified second IC feature separates from the identified first IC feature by a space smaller than the defined minimum spacing.6. The method of claim 4 , ...

Methods of fabricating fine patterns and photomask sets used therein

Photo mask sets and methods of fabricating fine patterns are provided. The method includes forming a first layer having a first main pattern part and a first dummy pattern part on a base layer, forming a second layer on the first layer, etching the first layer using the second layer as an etch mask to form a third main pattern part composed of a remaining portion of the first main pattern part and to remove the first dummy pattern part, and removing the second layer. The second layer is formed to have a second main pattern part exposing portions of the first main pattern part and to have a second dummy pattern part exposing the first dummy pattern part.

Compositions of Matter, and Methods of Removing Silicon Dioxide

Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX 3 and PQ 3 , where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate. 1. A method for fabricating an integrated circuit , comprising: a laterally-elongated first terminal section; and', 'a plurality of laterally-elongated first extensions extending transverse to the first terminal section;, 'forming a first tiered mandrel, the first tiered mandrel comprising a laterally-elongated second terminal section; and', 'a plurality of laterally-elongated second extensions extending transverse to the second terminal section,', 'wherein the first and the second extensions are interdigitated, and', 'wherein the first and second terminal sections are disposed on opposite sides of the interdigitated first and second extentions;, 'forming a second tiered mandrel, the second tiered mandrel comprisingforming spacers on sidewalls of the first and second tiered mandrels;selectively etching the first and second tiered mandrels relative to the spacers to form a spacer pattern defined by the spacers; andprocessing an underlying layer through a mask defined by the spacer pattern.2. The method of claim 1 , wherein forming the first tiered mandrel comprises forming the first extensions extending at about a right angle to the first terminal section claim 1 , and wherein forming the second tiered mandrel comprises forming the second extensions extending at about a right angle to the second terminal section.3. The method ...

Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures

Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.

Hardmask layer with alternating nanolayers

A hardmask layer is formed with an increased etch resistance based on alternating nanolayers of TiN with alternating residual stresses. Embodiments include depositing a first nanolayer of TiN, and depositing a second nanolayer of TiN on the first nanolayer, wherein the first and second nanolayers have different residual stresses.

Methods of forming a semiconductor device

A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

SEMICONDUCTOR DEVICE WITH SILICON-CONTAINING HARD MASK AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer. 1. A semiconductor device comprising:a semiconductor substrate having an etch target layer provided on the surface thereof; anda hard mask layer formed over the etch target layer and including silicon,wherein the hard mask layer comprises a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.2. The semiconductor device of claim 1 , wherein the second area including an impurity is formed over the first area in the hard mask layer.3. The semiconductor device of claim 1 , wherein the second area comprises boron4. The semiconductor device of claim 1 , wherein the first area comprises an undoped polysilicon layer claim 1 , and the second area comprises a boron-doped polysilicon layer.5. The semiconductor device of claim 4 , wherein the doping concentration of boron in the boron-doped polysilicon layer has a range of about 1×10atoms/cmto 1×10atoms/cm.6. The semiconductor device of claim 1 , wherein the second area has a smaller thickness than the first area.7. A method for fabricating a semiconductor device claim 1 , comprising:forming an etch target layer over a semiconductor substrate;forming a silicon-containing layer over the etch target layer, the silicon-containing layer comprising a first area and a second area formed over the first area and having a smaller etch rate than the first area;patterning the silicon-containing layer; andetching the etch target layer using the patterned silicon-containing layer as an etch barrier.8. The method of claim 7 , ...

Semiconductor fin on local oxide

A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION

Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. 1. A method for forming an integrated circuit , comprising:forming a first plurality of mandrels on a first level over a substrate;forming a first plurality of spacers on sidewalls of the first plurality of mandrels;forming a second plurality of mandrels on a second level over the first level;forming a second plurality of spacers on the sidewalls of the second plurality of mandrels, the second plurality of spacers elongated generally parallel to the first plurality of spacers;selectively etching portions of the first and the second pluralities of mandrels to form a pattern defined by spacers of the first and the second pluralities of spacers; andtransferring the pattern to the substrate.2. The method of claim 1 , wherein forming the first plurality of mandrels comprises patterning a carbon-containing layer to define the first plurality of mandrels in the carbon-containing layer.3. The method of claim 2 , wherein the carbon-containing layer is formed of amorphous carbon.4. The method of claim 1 , ...

PATTERN FORMATION METHOD

A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film. 1. A pattern formation method , comprising:forming a first layer on a substrate;forming a second layer on the first layer;forming a resist pattern on the second layer in a line and space pattern, the space pattern having openings that expose a portion of the second layer;removing the resist pattern to form a first region and a second region on the second layer, wherein the first region has a greater hydrophobicity than the second region;forming a directed self-assembly material layer containing a first segment and a second segment on the second layer;microphase separating the directed self-assembly material layer to form a self-assembled pattern containing a first polymer part that includes the first segment and a second polymer part that includes the second segment; andremoving either the first polymer part or the second polymer part using the other as a mask to process the first layer.2. The method of claim 1 , wherein removing the resist pattern comprises oxidizing the resist pattern.3. The method of claim 2 , wherein removing the resist pattern comprises exposing the resist pattern and the second layer to oxygen plasma.4. The method of claim 2 , wherein removing the resist pattern comprises exposing the resist pattern to ozonated water.5. The method ...

CARBON DEPOSITION-ETCH-ASH GAP FILL PROCESS

Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles. 1. A method comprising:a) providing a substrate in a semiconductor process chamber, the substrate having a top surface and at least one gap feature with a gap entry width where the at least one gap feature intersects the top surface;b) performing a deposition process to deposit a carbon film layer on the substrate and on exposed surfaces of the at least one gap feature, wherein the deposition process is performed at least until the deposited carbon film layer causes the gap entry width to be reduced;c) performing an anisotropic etch process on the substrate with a dominant anisotropic axis substantially perpendicular to the substrate at least until the gap entry width increases from the gap entry width at the conclusion of (b);d) performing X additional cycles of (b) and (c), wherein X is a positive integer; ande) performing an ashing process to remove localized build-up of carbon film on the top surface of the substrate adjacent to the at least one gap feature produced as a result of (b) through (d).2. The method of claim 1 , further comprising:f) performing Y additional cycles of (a) through (e), wherein Y is a positive integer.4. The method of claim 2 , wherein:X is between about 1 and 100, and Y is between about 2 and 1000.5. The method of claim 2 , wherein:X is between about 2 and 20, andY is between about 10 to 100.6 ...

Reverse Tone STI Formation

A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. 1. A method comprising:forming a pad oxide layer over a semiconductor substrate;forming a hard mask over the pad oxide layer;forming a mandrel layer over the hard mask;performing a first lithography process to pattern the mandrel layer and to form a plurality of mandrels;forming a spacer layer, wherein the spacer layer comprises top portions over the mandrels, and sidewall portions on sidewalls of the mandrels;patterning the spacer layer to leave the sidewall portions of the spacer layer;etching the hard mask and the pad oxide layer to form hard mask patterns and pad oxide patterns, wherein the step of etching is performed using the sidewall portions of the spacer layer as an etching mask;removing the sidewall portions of the spacer layer;filling spaces between the hard mask patterns and the pad oxide patterns with a dielectric material;removing the hard mask patterns and the pad oxide patterns; andperforming an epitaxy to grow a semiconductor material in spaces left by the removed hard mask patterns and the pad oxide patterns.2. The method of claim 1 , wherein the step of patterning the spacer layer comprises two lithography processes.3. The method of claim 1 , wherein the step of filling the spaces comprises a spin-on coating step claim 1 , and a curing step after the spin-on coating step to cure the dielectric material.4. The method of claim 1 , wherein after the step of epitaxy claim 1 , a top surface of the semiconductor material is substantially level with a top surface of the dielectric ...

PHOTOCURED PRODUCT AND METHOD FOR PRODUCING THE SAME

It is intended to provide a photocured product that is prepared using the photo-imprint method and has favorable pattern precision and improvement in pattern defects. The present invention provides a photocured product obtained by irradiating a coating film in contact with a mold with light, the photocured product containing a fluorine atom-containing surfactant, wherein of secondary ion signals obtained by the surface analysis of the photocured product based on time-of-flight secondary ion mass spectrometry, the intensity of a CHO ion signal is higher than that of a CHO ion signal. 1. A photocured product obtained by irradiating a photocurable composition in contact with a mold with light , the photocured product containing a fluorine atom-containing surfactant ,{'sub': 2', '5', '3', '7, 'sup': +', '+, 'wherein of secondary ion signals obtained by a surface analysis of the photocured product based on time-of-flight secondary ion mass spectrometry, an intensity of a CHO ion signal is higher than that of a CHO ion signal.'}2. The photocured product according to claim 1 , wherein the fluorine atom-containing surfactant is a compound comprising ethylene oxide.3. A photocurable composition for obtaining a photocured product by light irradiation in contact with a mold claim 1 , the photocurable composition comprising:at least a polymerizable monomer;a photopolymerization initiator; anda fluorine atom-containing surfactant,{'sub': 2', '5', '3', '7, 'sup': +', '+, 'wherein of secondary ion signals obtained by a surface analysis of the photocured product based on time-of-flight secondary ion mass spectrometry, an intensity of a CHO ion signal is higher than that of a CHO ion signal.'}4. A method for forming a photocured product having a predetermined pattern shape on a substrate claim 1 , comprising:coating the substrate with a photocurable composition;contacting the photocurable composition with a mold;irradiating the photocurable composition with light via the mold; ...

SELF-ALIGNED PATTERNING TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES

A method for fabricating a semiconductor device utilizing a plurality of masks and spacers. The method includes forming parallel first trenches in a substrate using a first lithographic process. The substrate includes sidewalls adjacent to the parallel first trenches. Forming first spacers adjacent to the sidewalls. Removing the sidewalls, which in part includes using a second lithographic process. Forming second spacers adjacent to the first spacers, resulting in spacer ridges. Etching portions of the substrate between the spacer ridges resulting in second trenches. 1forming a plurality of parallel first trenches in a substrate using a first lithographic process such that the portions of the substrate adjacent to the parallel first trenches include sidewalls;forming a plurality of first spacers adjacent to the sidewalls of the substrate;forming a plurality of fillers in the parallel first trenches;removing the sidewalls of the substrate, wherein removing the sidewalls includes using a second lithographic process;forming a plurality of second spacers adjacent to the first spacers;removing the fillers;wherein the adjacent first and second spacers in physical contact result in a plurality of spacer ridges.. A method for fabricating a semiconductor device, comprising: This application claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 13/931,798 filed Jun. 28, 2013, the entire text of which is specifically incorporated by reference herein.This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating sub-lithographic semiconductor device features.In general, semiconductor device scaling may be restricted by the current resolution limits of lithography technology. With the ongoing down-scaling of semiconductor devices and drive to increase feature density, Double Patterning Technology has been introduced as a solution to the resolution limits of current lithography ...

Methods and Structures for Protecting One Area While Processing Another Area on a Chip

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. 1. A method of protecting a material surface comprising steps ofdepositing a material layer on said material surface, said material layer providing an interface selected from the group consisting of a grain interface and a material interface,lithographically patterning said material layer, andremoving said material layer from said material surface selectively to said material surface.27-. (canceled)8. A method as recited in claim 1 , wherein said depositing step includesdepositing a first layer of polysilicon material,exposing said first layer of polysilicon material to an ambient gas to form a said grain interface, anddepositing a second layer of polysilicon material.9. A method as recited in claim 8 , wherein said ambient gas includes oxygen.10. A method as recited in claim 9 , wherein said first and second layers of polysilicon material have a total thickness of less than 40 nm.11. A method as recited in claim 1 , wherein said depositing step includesdepositing a layer of polysilicon, anddepositing a layer of metal in said layer of polysilicon to form a said material interface.12. A method as recited in claim 11 , wherein said metal is tungsten.13. A method as recited in claim 11 , including the further step of forming a silicide from said layer of metal and said layer of polysilicon.14. A ...

SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure. 1. A method for fabricating a semiconductor device having a gate structure , comprising:providing a substrate and a mandrel layer, wherein the substrate, the hard mask layer and the mandrel layer are stacked sequentially;forming a cutting trench in the mandrel layer, wherein the cutting trench penetrates through the mandrel layer and exposes the substrate;patterning the mandrel layer to form a plurality of mandrel patterns and removing a part of the substrate through the cutting trench to form a first recess on the substrate;forming a spacer on sidewalls of the mandrel patterns and a sidewall of the first recess;removing the mandrel layer;performing an etching process, using the spacer as a mask, to form a second recess under the first recess, wherein the first recess and the second recess form a step structure;removing the spacer;forming a first insulating structure in the second recess; andforming a gate structure on the first insulating structure.2. The method for fabricating the semiconductor device having the gate structure according to claim 1 , wherein the etching process comprises transferring a pattern of the spacer to the substrate to form a patterned protrusion claim 1 , so that the substrate includes a third recess and a ...

Photoresist and Method of Manufacture

A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating additive in order to form a floating additive region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating additive may comprise an additive group which will decompose along with a fluorine unit bonded to the additive group which will decompose. Additionally, adhesion between the middle layer and the photoresist may be increased by applying an adhesion promotion layer using either a deposition process or phase separation, or a cross-linking may be performed between the middle layer and the photoresist. 1. A method of manufacturing a semiconductor device , the method comprising: a group to be decomposed; and', 'a fluorine group bonded to the group to be decomposed; and, 'dispensing an anti-reflective material over a substrate to form an anti-reflective coating layer, the anti-reflective material having a first concentration of a floating additive, wherein the floating additive further comprisesforming a floating region adjacent to a top surface of the anti-reflective coating, the floating region having a second concentration of the floating additive greater than the first concentration.2. The method of claim 1 , wherein the group to be decomposed further comprises an acid labile group.3. The method of claim 1 , wherein the floating region further comprises a catalyst.4. The method of claim 3 , wherein the catalyst is a thermal acid generator.5. The method of claim 4 , further comprising baking the floating region claim 4 , wherein the baking the floating region initiates a reaction between the thermal acid generator and the floating additive which cleaves the group to be decomposed.6. The method of claim 1 , wherein the fluorine group is a substituted fluorine.7. The method of claim 1 , further comprising applying a middle layer to the floating region.8. A method of manufacturing a ...

CROSS-BAR FIN FORMATION

A first mask layer is formed on top of a semiconductor substrate. A mandrel material is formed perpendicular to the first mask layer. A second mask layer is formed on one or more exposed surfaces of the mandrel material. The mandrel material is removed. A pattern of the first mask layer and the second mask layer is transferred into the semiconductor substrate. 1. A method of forming a semiconductor structure , the method comprising:forming a first mask layer on top of a semiconductor substrate;forming a mandrel material perpendicular to the first mask layer;forming a second mask layer on one or more exposed surfaces of the mandrel material;removing the mandrel material; andtransferring a pattern of the first mask layer and the second mask layer into the semiconductor substrate.2. The method of claim 1 , further comprising:forming a cut masking layer over at least a portion of the mandrel material, at least a portion of the second mask layer, and at least a portion of the first mask layer;selectively removing the mandrel material and the second mask layer not covered by the cut masking layer; andremoving the cut masking layer.3. The method of claim 1 , wherein a width of the material layer is between 5 nanometers (nm) and 20 nm and wherein the material layer is selected from the group consisting of silicon nitride (SiN) claim 1 , silicon carbide (SiC) claim 1 , silicon oxynitride (SiON) claim 1 , carbon-doped silicon oxide (SiOC) claim 1 , silicon-carbon-nitride (SiCN) claim 1 , boron nitride (BN) claim 1 , silicon boron nitride (SiBN) claim 1 , siliconboron carbonitride (SiBCN) claim 1 , silicon oxycarbonitride (SiOCN) claim 1 , silicon oxide claim 1 , titanium nitride (TiN).4. The method of claim 1 , wherein the mandrel material is between 10 nm and 50 nm and wherein the mandrel material is selected from the group consisting of amorphous silicon (aSi) claim 1 , polycrystalline silicon claim 1 , amorphous silicon germanium (aSiGe) claim 1 , and polycrystalline ...

Manufacturing Method of Semiconductor Device

According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask. 1. A manufacturing method of a semiconductor device comprising:forming a first film on a processing target by using a first material;forming a second film on the first film by using a second material;selectively removing the second and first films to provide an opening pierced in the second and first films;selectively forming a metal film on an inner surface of the opening in the first film; andprocessing the processing target by using the metal film as a mask.2. The method of claim 1 ,wherein the first material is a material to which metal atoms of the metal film precipitate, andthe second material is a material to which the metal atoms of the metal film do not precipitate.3. The method of claim 2 ,wherein the first material is carbon (C) or (Si), andthe second material is a silicon oxide film (SiO2).4. The method of claim 1 ,wherein the metal film is formed by electroless plating.5. The method of claim 4 ,wherein the metal film is formed by subjecting palladium (Pd) to electroless plating.6. The method of claim 1 ,wherein the processing target comprises a surface layer made of a material to which metal atoms of the metal film precipitate, andthe method further comprises forming a third film between the processing target and the first film by using a material to which metal atoms of the metal film do not precipitate.7. The method of claim 4 , further comprising:modulating growth selectively of a metal by pretreatment using an SAM before forming the metal film.8. The method of ...

Spacer Etching Process for Integrated Circuit Design

A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. 1. A method , comprising:forming a first material layer on a substrate;performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer, the first layout including a first subset of a target pattern;performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, the second layout including a second subset of the target pattern and a cut pattern for the first subset;forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features;removing the first material layer;forming a second material layer on the substrate and within openings defined by the spacer features; andremoving the spacer features.2. The method of claim 1 , wherein the forming of the second material layer includes:forming the second material layer by ...

METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE

A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask. 1. A method of forming patterns of a semiconductor device , comprising:forming a material film on a substrate;forming a hard mask on the material film;forming a first mold mask pattern and a second mold mask pattern on the hard mask;forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern;forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers;forming a mask pattern on the hard mask to cover the first gap and expose the second gap;forming an auxiliary pattern to cover the second gap;removing the mask pattern; andforming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.2. The method of claim 1 , ...

METHOD FOR INTEGRATED CIRCUIT PATTERNING

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. 1. A method of forming a target pattern for an integrated circuit , the method comprising:providing a patterned first spacer layer over a substrate;forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer; andforming a patterned material layer over the second spacer layer with a second mask, whereby the patterned material layer and the second spacer layer collectively define a plurality of trenches, and wherein the second spacer layer remains formed over the patterned first spacer layer and on the sidewalls of the patterned first spacer layer after the plurality of trenches are defined.2. The method of claim 1 , further comprising:transferring the plurality of trenches to the substrate.3. The method of claim 1 , further comprising:etching the second spacer layer through openings of the plurality of trenches to expose the substrate;etching the substrate through the openings of the plurality of trenches; andafter etching, removing the patterned first spacer layer, the second spacer layer, and the patterned material layer.4. The method of claim 1 , further comprising:forming a plurality of lines over the substrate with a first mask;forming a first spacer layer over the substrate, ...

METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. 1. A method of manufacturing a semiconductor device , comprising:forming an object layer on a substrate;forming a first pattern on the object layer in a first region of the substrate, the first pattern having a plurality of spacers that are spaced apart from and parallel with each other;forming a second pattern on the object layer in a second region of the substrate; andpatterning the object layer on the substrate using the first and second patterns as a mask, respectively.2. The method of claim 1 , wherein the object layer includes a conductive layer claim 1 , so that first and second conductive patterns are formed on the substrate corresponding to the first and second patterns claim 1 , respectively.3. The method of claim 1 , wherein forming the first pattern includes:forming a buffer pattern on the object layer;forming the spacers on sidewalls of the buffer pattern; andremoving the buffer pattern from the object layer of the substrate, so that the spacers remain on the object layer and spaced apart from each other.4. The method of claim 3 , wherein forming the buffer pattern includes:forming a buffer layer on the object ...

METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. 1. A method of manufacturing a semiconductor integrated circuit device , comprising the steps of:(a) forming a hard mask film over a first main surface of a semiconductor wafer and making a first opening in the hard mask film in a first region over the first main surface;(b) forming sidewall insulating films on the side surfaces of the hard mask film of the first opening, respectively;(c) forming a first shallow trench in a semiconductor region surface of the first main surface in the first opening, with the hard mask film and the sidewall insulating films as masks;(d) after the step (c), oxidizing at least an exposed portion of an inner surface of the first shallow trench and the semiconductor region surface of the first main surface in the first opening;(e) after the step (d), filling the first shallow trench and the first opening with an insulating film;(f) after the step (e), removing the insulating film outside the first shallow trench so as to leave the insulating film outside the first shallow trench in the first opening and thereby forming a drain offset STI insulating film inside and outside the first shallow trench, and(g) after the step (f), forming a first gate electrode from an upper portion of a gate insulating film in a first active region contiguous to the drain offset STI insulating film to an upper portion of the drain offset insulating film.2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the step of:(h) after the step (c) but before the step (d), making a second opening in the hard mask film in a second region over the first main surface and thereby forming a second shallow trench in a semiconductor region surface of the first main surface in the second opening;wherein in the step (d), at least an ...

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer and in the first openings. The carbon-containing silicon dioxide layer is planarized to remove portions extending outside the first openings and generate a plurality of mask elements from remaining portions of the carbon-containing silicon dioxide layer. The patterned mask layer is removed. The process layer is etched using the mask elements as an etch mask.

METAL ON METAL MULTIPLE PATTERNING

The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer. 1. A method , comprising:patterning a first metal layer as a mandrel;forming a dielectric spacer on the first metal layer;forming a second metal layer on the dielectric spacer; andforming a metal cap on the second metal layer.2. The method of claim 1 , further comprising forming at least one airgap between patterned sections of the first metal layer.3. The method of claim 2 , wherein the at least one airgap is surrounded by the dielectric spacer.4. The method of claim 1 , further comprising forming nitrogen doped carbide on sections of the mandrel.5. The method of claim 1 , further comprising forming a plurality of pinched off airgaps between sections of the mandrel by deposition of a dielectric material between sections of the mandrel.6. The method of claim 1 , wherein the dielectric spacer comprises a low-k dielectric material.7. The method of claim 1 , wherein the first metal layer is a same material as the second metal layer.8. The method of claim 7 , wherein the first metal layer and the second metal layer comprises one of cobalt claim 7 , ruthenium claim 7 , nickel claim 7 , aluminum claim 7 , tungsten claim 7 , and tantalum.9. The method of claim 1 , wherein the first metal layer is a different material than the second metal layer.10. The method of claim 1 , further comprising forming a plurality of cuts in the mandrel.11. The method of claim 1 , wherein the metal cap comprises tantalum.12. A method claim 1 , comprising:forming a metal mandrel with cuts along its longitudinal extent;forming a metal layer on the metal mandrel;forming a plurality of low-k dielectric spacers on sidewalls of the metal mandrel;forming a metal cap on the metal layer; andforming at least one airgap between sections of patterned metal in the metal mandrel,wherein the at least one ...

ATOM IMPLANTATION FOR REDUCTION OF COMPRESSIVE STRESS

Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material. 1. A method , comprising:patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material;forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material; andimplanting atoms through the lower RI material and into the hard mask material to reduce a compressive stress in the hard mask material.2. The method of claim 1 , further comprising:forming the lower RI material over the hard mask material prior to implanting the atoms;wherein the lower RI material is a last material formed over the hard mask material at a temperature greater than 100 degrees Celsius.3. The method of claim 1 , further comprising:forming a photoresist material in a pattern over the lower RI material;removing a portion of the lower RI material consistent with the pattern to initiate formation of a pillar of a semiconductor device; andimplanting the atoms through a remaining lower RI material and into the hard mask material to reduce a probability of an unintended bend of the pillar based on the reduced compressive stress in the hard mask material.4. The method of claim 3 , wherein to reduce the probability of the unintended bend of the pillar comprises reducing a potential level of line width roughness on the pillar.5. The method of claim 3 , wherein to reduce the probability of the unintended bend ...

PATTERN FORMING MATERIAL, PATTERN FORMING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The pattern forming material of an embodiment is a pattern forming material containing a polymer composed of two or more kinds of monomer units, in which a first monomer unit in the monomer units is provided with an ester skeleton having a first carbonyl group and one or more second carbonyl groups which bind to the ester skeleton, among the second carbonyl groups, the second carbonyl group that is farthest from a main chain of the polymer constituting the pattern forming material is present on a linear chain, and a second monomer unit in the monomer units is provided with a crosslinkable functional group on a side chain terminal. 1. A pattern forming material comprising a polymer composed of two or more kinds of monomer units including a first monomer unit and a second monomer unit ,wherein the first monomer unit in the monomer units is provided with an ester skeleton having a first carbonyl group and one or more second carbonyl groups which bind to the ester skeleton,among the second carbonyl groups, the second carbonyl group that is farthest from a main chain of the polymer is present on a linear chain, andwherein the second monomer unit in the monomer units is provided with a crosslinkable functional group on a side chain terminal.2. The pattern forming material according to claim 1 ,wherein the first monomer unit is at least one of acetonyl methacrylate, acetonyl acrylate, acetoacetyloxyethyl methacrylate, acetoacetyloxyethyl acrylate, acetylacrylic acid anhydride, acetylmethacrylic acid anhydride, 2-acetoacetyl methacrylate, 2-acetoacetyl acrylate, 2,4-dioxopentyl methacrylate, and 2,4-dioxopentyl acrylate, andthe second monomer unit is at least one of glycidyl acrylate, glycidyl methacrylate, 4-hydroxybutyl acrylate glycidyl ether, 4-hydroxybutyl methacrylate glycidyl ether, (3-ethyl-3-oxetanyl)methyl acrylate, and (3-ethyl-3-oxetanyl) methyl methacrylate.3. The pattern forming material according to claim 2 ,wherein the monomer units contain a third monomer ...

Method for Manufacturing Semiconductor Device

The present application relates to the field of semiconductor technologies, and discloses methods for manufacturing a semiconductor device. The manufacturing method includes: forming an etchable material layer on a substrate; forming multiple openings on the etchable material layer by means of patterning processing to determine a position of a core; etching the substrate at bottoms of the multiple openings, so that the bottoms of the multiple openings extend into the substrate; depositing a material of the core to fill the multiple openings; etching the material of the core so as to expose the etchable material layer; removing the etchable material layer to leave multiple cores; depositing spacers; over etching the spacers so as to expose the multiple cores, and etching a part of the substrate, where an etching depth of the substrate is the same as a depth to which the openings extend into the substrate; and removing the multiple cores. The methods address the problem of a distance offset of gaps between spacers. 1. A method for manufacturing a semiconductor device , comprising:forming an etchable material layer on a substrate;forming multiple openings on the etchable material layer by means of a patterning processing to determine a position of a core;etching the substrate at bottoms of the multiple openings so that the bottoms of the multiple openings extend into the substrate;depositing a material of a core to fill the multiple openings;etching the material of the core to expose the etchable material layer;removing the etchable material layer to leave multiple cores;depositing spacers;over etching the spacers to expose the multiple cores, and etching a part of the substrate, wherein an etching depth of the substrate is the same as a depth to which the openings extend into the substrate; andremoving the multiple cores.2. The manufacturing method according to claim 1 , whereinthe etchable material layer comprises an amorphous carbon layer and a low-temperature oxide ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. 17-. (canceled)8. A manufacturing method of a semiconductor device comprising:forming core patterns, onto which a plurality of linear shaped first mask patterns, each of which is offset in a middle by a wiring pitch in an orthogonal direction with respect to a wiring direction, is transferred, on a processing target layer;forming first sidewall patterns on sidewalls of the core patterns;removing the core patterns while leaving the first sidewall patterns on the processing target layer;forming a second mask pattern that covers part of a space between the first sidewall patterns on the processing target layer; andforming first openings in the processing target layer by processing the processing target layer exposed from the first sidewall patterns and the second mask pattern.9. The manufacturing method of a semiconductor device according to claim 8 , wherein a width of the first mask patterns and an interval between the first mask patterns are twice the wiring pitch.10. The manufacturing method of a semiconductor device according to claim 8 , further comprising slimming the core patterns before forming the first sidewall patterns.11. The manufacturing method of a semiconductor device ...

Spin on Hard-Mask Material

Disclosed and claimed herein is a composition for forming a spin-on hard-mask, having a fullerene derivative and a crosslinking agent. Further disclosed is a process for forming a hard-mask. 2. The composition of claim 1 , further comprising one or more thermal acid generators.3. The composition of claim 2 , wherein the one or more thermal acid generators are chosen from alkyl esters of organic sulfonic acids claim 2 , alicyclic esters of organic sulfonic acids claim 2 , amine salts of organic sulfonic acids claim 2 , 2-nitrobenzyl esters of organic sulfonic acids claim 2 , 4-nitrobenzyl esters of organic sulfonic acids claim 2 , benzoin esters of organic sulfonic acids claim 2 , β-hydroxyalkyl esters of organic sulfonic acids claim 2 , β-hydroxycycloalkyl esters of organic sulfonic acids claim 2 , triaryl sulfonium salts of organic sulfonic acids claim 2 , alkyl diaryl sulfonium salts of organic sulfonic acids claim 2 , dialkyl aryl sulfonium salts of organic sulfonic acids claim 2 , trialkyl sulfonium salts of organic sulfonic acids claim 2 , diaryl iodonium salts of organic sulfonic acids claim 2 , alkyl aryl sulfonium salts of organic sulfonic acids claim 2 , or ammonium salts of tris(organosulfonyl) methides.4. The composition of claim 2 , further comprising one or more photoacid generators.5. The composition of claim 4 , wherein the one or more photoacid generators are chosen from halogenated triazines claim 4 , 2-nitrobenzyl esters of organic sulfonic acids claim 4 , 4-nitrobenzyl esters of organic sulfonic acids claim 4 , triaryl sulfonium salts of organic sulfonic acids claim 4 , alkyl diaryl sulfonium salts of organic sulfonic acids claim 4 , dialkyl aryl sulfonium salts of organic sulfonic acids claim 4 , diaryl iodonium salts of organic sulfonic acids claim 4 , alkyl aryl sulfonium salts of organic sulfonic acids claim 4 , n-organosulfonyloxybicyclo[2.2.1]-hept-5-ene-2 claim 4 ,3-dicarboximides claim 4 , or 1 claim 4 ,3-dioxoisoindolin-2-yl ...

PATTERN FORMATION METHOD

According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide. 1. A pattern formation method comprising:forming a layer above an underlying layer, the layer including a block copolymer;forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer; andselectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.2. The method according to claim 1 , whereineach of the first polymer and the second polymer has a carbon-based main chain; the first polymer includes a unit of a first monomer in a chemical formula thereof, and the second polymer includes a unit of a second monomer in a chemical formula thereof; anda first value in the first monomer is larger than a second value in the second monomer, each of the first value and the second value being defined as total number of atoms divided by number of atoms obtained by subtracting number of oxygen atoms from number of carbon atoms.3. The method according to claim 1 , whereinthe etching gas further includes an inert gas, anda ratio of the carbon monoxide to total amount of the inert gas and the carbon monoxide is 10% or more.4. The method according to claim 1 , wherein the etching gas further includes a gas containing a hydrogen atom in a chemical formula thereof.5. The method according to claim 4 , wherein the gas containing a hydrogen atom is one of hydrogen claim 4 , hydrogen bromide claim 4 , and methane.6. The method according to claim 1 , whereinthe etching gas further includes hydrogen, anda ratio of the carbon monoxide ...

VERTICAL CHANNEL TRANSISTORS FABRICATION PROCESS BY SELECTIVE SUBTRACTION OF A REGULAR GRID

A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process. 1. A method to provide a vertical device patterning , comprising:forming a grid comprising a first set of grid lines and a second set of grid lines on a substrate using a first lithography process; anddefining a vertical device feature by selectively patterning at least one of the first set of grid lines and the second set of grid lines using a second lithography process.2. The method of claim 1 , wherein the first lithography process comprises a deep ultraviolet (DUV) lithography claim 1 , and the second lithography process comprises an electron beam lithography claim 1 , extreme ultraviolet (EUV) lithography claim 1 , or any combination thereof.3. The method of claim 1 , wherein the first set of grid lines and the second set of grid lines comprises a material selective to the substrate.4. The method of claim 1 , further comprisingdepositing a first hard mask layer on the grid;patterning the first hard mask layer to expose a portion of the at least one of the first set of grid lines and the second set of grid lines.5. The method of claim 1 , further comprisingremoving a portion of the at least one of the first set of grid lines and the second set of grid lines.6. The method of claim 1 , wherein the vertical device feature comprises a transistor claim 1 , an interconnect claim 1 , a trench claim 1 , or any combination thereof.7. The method of claim 1 , further comprisingforming the device using the patterned at least one of the first set of grid lines and the second set of grid lines as a mask.8. A method to manufacture an electronic device comprising:forming a grid comprising a first set of grid lines and a second set of grid lines on a substrate;depositing a ...

METHOD OF FORMING GRAPHENE NANOPATTERN, GRAPHENE-CONTAINING DEVICE, AND METHOD OF MANUFACTURING THE GRAPHENE-CONTAINING DEVICE

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer. 1. A method of forming a graphene nanopattern , the method comprising:providing a graphene layer on a substrate, the graphene layer having a smaller width than the substrate;forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer,the block copolymer layer including a plurality of first regions and a plurality of second regions arranged parallel to the graphene layer, andone of the plurality of first regions being arranged along an edge portion of the graphene layer;forming a mask pattern from the block copolymer layer by removing one of the plurality of first regions and the plurality of second regions of the block copolymer layer; andpatterning the graphene layer in a nanoscale by using the mask pattern as an etching mask.2. The method of claim 1 , wherein the forming the block copolymer layer includes forming the block copolymer layer to directly contact the graphene layer.3. The method of claim 1 , wherein the forming the block copolymer layer includes forming the block copolymer layer to directly contact the region of the ...

Method for Overcoming Broken Line and Photoresist Scum Issues in Tri-Layer Photoresist Patterning

A method of fabricating a semiconductor device includes forming a first layer over a substrate and forming a second layer over the first layer. The method further includes patterning the second layer into a mask having one or more openings that expose portions of the first layer. The method further includes etching the first layer through the one or more openings via a first etching process, resulting in a patterned first layer. The first etching process includes forming a coating layer around both the mask and the patterned first layer while the first layer is being etched. 1. A method of fabricating a semiconductor device , comprising:forming a first layer over a substrate;forming a second layer over the first layer;patterning the second layer into a mask having one or more openings that expose portions of the first layer; andetching the first layer through the one or more openings via a first etching process, resulting in a patterned first layer, wherein the first etching process includes forming a coating layer around both the mask and the patterned first layer while the first layer is being etched.2. The method of claim 1 , wherein the first etching process includes a plasma etching process claim 1 , and wherein the plasma etching process is performed using at least an Hgas.3. The method of claim 2 , wherein the Hgas is configured to induce a polymer material to be deposited around both the mask and the patterned first layer as the coating layer while the first layer is being etched.4. The method of claim 2 , wherein the plasma etching process is a continuous plasma process.5. The method of claim 1 , wherein the second layer includes a photo-sensitive material.6. The method of claim 5 , wherein the mask includes photoresist scum that protrudes outward from the mask claim 5 , further comprising:removing the photoresist scum via a second etching process before the etching of the first layer.7. The method of claim 6 , wherein the first and second etching processes ...

WIRING STRUCTURE AND METHOD OF FORMING A WIRING STRUCTURE

A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask. 1. A wiring structure comprising:a lower wiring structure on a substrate;a dummy lower wiring structure being at a level substantially the same as that of the lower wiring structure, the dummy lower wiring structure including first dummy lower wirings and second dummy lower wirings, the first dummy lower wirings being closer to the lower wiring structure than the second dummy lower wirings, and each of the second dummy lower wirings having a size greater than that of each of the first dummy lower wirings;an upper wiring structure over the lower wiring structure, the upper wiring structure at least partially overlapping the lower wiring structure;a dummy upper wiring structure being at a level substantially the same as that of the upper wiring structure and at least partially overlapping the dummy lower wiring structure, the dummy upper wiring structure including first dummy upper wirings and second dummy upper wirings, the first dummy upper wirings being closer to the upper wiring structure than the second dummy upper wirings, and each of the second dummy upper wirings having a size greater than that of ...

PATTERNING FINS AND PLANAR AREAS IN SILICON

A method including for forming a plurality of mandrels, a plurality of sidewall spacers, and a plurality of offset spacers above a hardmask layer, the sidewall spacers being separated by the plurality of mandrels and the plurality of offset spacers in an alternating order, each of the plurality of sidewall spacers being in direct contact with a single offset spacer and a single mandrel, the plurality of mandrels being separated from the plurality of offset spacers by the plurality of sidewall spacers, depositing a fill material above the plurality of mandrels, above the plurality of sidewall spacers, above the plurality of offset spacers, and above the hardmask layer, and removing the plurality of mandrels and the plurality of offset spacers selective to the plurality of sidewall spacers, the fill material, and the hardmask layer. 1. A method comprising:forming a plurality of mandrels, a plurality of sidewall spacers, and a plurality of offset spacers above a hardmask layer, the sidewall spacers being separated by the plurality of mandrels and the plurality of offset spacers in an alternating order, each of the plurality of sidewall spacers being in direct contact with a single offset spacer and a single mandrel, the plurality of mandrels being separated from the plurality of offset spacers by the plurality of sidewall spacers;depositing a fill material above the plurality of mandrels, above the plurality of sidewall spacers, above the plurality of offset spacers, and above the hardmask layer; andremoving the plurality of mandrels and the plurality of offset spacers selective to the plurality of sidewall spacers, the fill material, and the hardmask layer.2. The method of claim 1 , wherein depositing the fill material above the plurality of mandrels claim 1 , above the plurality of sidewall spacers claim 1 , above the plurality of offset spacers claim 1 , and above the hardmask layer comprises:depositing a material having a high etch selectivity relative to the ...

PATTERNING METHOD

A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns. 1. A patterning method , comprising:providing a substrate having thereon a target layer, a hard mask layer on the target layer, a lower pattern transfer layer on the hard mask layer, and an upper pattern transfer layer on the lower pattern transfer layer;performing a first self-aligned reverse patterning (SARP) process to pattern the upper pattern transfer layer into an upper pattern mask on the lower pattern transfer layer;performing a second self-aligned reverse patterning (SARP) process to pattern the lower pattern transfer layer into a lower pattern mask, wherein the upper pattern mask and the lower pattern mask together define an array of hole patterns;filling the array of hole patterns with an organic dielectric layer;etching back the organic dielectric layer and the upper pattern mask until the lower pattern mask is exposed;removing the lower pattern mask, leaving remnants of the organic dielectric layer on the hard mask layer to form island patterns;using the island patterns as an etching hard mask to pattern the hard mask layer into hard mask patterns; andusing the hard mask patterns as an etching hard ...

Methods Of Forming Self-Aligned Vias

Processing methods comprising selectively orthogonally growing a first material through a mask to provide an expanded first material are described. The mask can be removed leaving the expanded first material extending orthogonally from the surface of the first material. Further processing can create a self-aligned via. 1. A processing method comprising:providing a substrate with a substrate surface comprising a first surface of a first material and a second surface of a second material different from the first material;forming a mask on the substrate, the mask having an opening exposing at least a portion of the first surface and the second surface;oxidizing the first material to expand the first material straight up from the first surface through the opening in the mask to extend above a top surface of the mask forming an expanded first material; andremoving the mask from the substrate to leave the expanded first material extending orthogonally from the substrate surface.2. The method of claim 1 , wherein the first material comprises a metal selected from the group consisting of Co claim 1 , Mo claim 1 , W claim 1 , Ta claim 1 , Ti claim 1 , Ru claim 1 , Rh claim 1 , Cu claim 1 , Fe claim 1 , Mn claim 1 , V claim 1 , Nb claim 1 , Hf claim 1 , Zr claim 1 , Y claim 1 , Al claim 1 , Sn claim 1 , Cr claim 1 , La and combinations thereof.3. The method of claim 1 , wherein the second material comprises a dielectric.4. The method of claim 1 , wherein oxidizing the first material comprises exposing the first material to an oxidizing agent comprising one or more of O claim 1 , O claim 1 , NO claim 1 , HO claim 1 , HO claim 1 , CO claim 1 , CO claim 1 , N/Ar claim 1 , N/He claim 1 , or N/Ar/He.5. The method of claim 1 , further comprising depositing a third material comprising a dielectric on the substrate surface claim 1 , the third material surrounding the expanded first material extending above the top surface of the mask.6. The method of claim 5 , wherein the third ...

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION

Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed. 1. A semiconductor structure , comprising:a plurality of semiconductor fins protruding from a substantially planar surface of a semiconductor substrate, the plurality of semiconductor fins having a grating pattern interrupted by a first location having a first fin portion having a first height and interrupted by a second location having a second fin portion having a second height different from the first height;a trench isolation layer disposed between the plurality of semiconductor fins and adjacent to lower portions of the plurality of semiconductor fins, but not adjacent to upper portions of the plurality of semiconductor fins, and wherein the trench isolation layer is disposed over the first and second fin portions;one or more gate electrode stacks disposed on top surfaces and sidewalls of the upper portions of the plurality of semiconductor fins and on portions of the trench isolation layer; andsource and drain regions disposed on either side of the one or more gate electrode stacks.2. The semiconductor structure of claim 1 , wherein the grating pattern has a constant pitch.3. The semiconductor structure of claim 1 , ...

Tunneling Field-Effect Transistor And Fabrication Method Thereof

The present disclosure relates to a tunneling field-effect transistor and a fabrication method. One example transistor includes a semiconductor substrate, a semiconductor nanosheet, a source region and a drain region, a dielectric layer, and a gate metal layer. The semiconductor nanosheet is vertically disposed on the semiconductor substrate. The source region and the drain region are connected using a channel. The drain region, the channel, and the source region are disposed on the semiconductor nanosheet in turn. The drain region is in contact with the semiconductor substrate. The source region is located at an end, of the semiconductor nanosheet, far away from the semiconductor substrate. The dielectric layer comprises at least a gate dielectric layer, is disposed on a surface of the semiconductor nanosheet, and surrounds the channel. The gate metal layer is disposed on a surface of the gate dielectric layer and surrounds the gate dielectric layer. 1. A tunneling field-effect transistor , wherein the tunneling field-effect transistor comprises:a semiconductor substrate;a semiconductor nanosheet, the semiconductor nanosheet vertically disposed on the semiconductor substrate;a source region and a drain region, wherein the source region and the drain region are connected using a channel, the drain region, the channel, and the source region are disposed on the semiconductor nanosheet in turn, the drain region is in contact with the semiconductor substrate, and the source region is located at an end, of the semiconductor nanosheet, far away from the semiconductor substrate;a dielectric layer, wherein the dielectric layer comprises at least a gate dielectric layer, and the dielectric layer is disposed on a surface of the semiconductor nanosheet and surrounds the channel; anda gate metal layer, the gate metal layer disposed on a surface of the gate dielectric layer and surrounding the gate dielectric layer, wherein the gate dielectric layer and the gate metal layer ...

METHODS FOR MAKING EUV PATTERNABLE HARD MASKS

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. The mixing and depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space. 1. A method for making an EUV-patternable film on a surface of a substrate , comprising:mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; anddepositing the organometallic material onto the surface of the substrate to form the EUV-patternable film.2. The method of claim 1 , wherein the organometallic precursor has the formula{'br': None, 'MaRbLc,'}wherein: M is a metal with an atomic absorption cross section of 1×107 cm2/mol or higher; R is alkyl, such as CnH2n+1, wherein n≥3; L is a ligand, ion or other moiety which is reactive with the counter reactant; a≥1; b≥1; and c ≥1.3. The method of claim 2 , wherein M is selected from the group consisting of tin claim 2 , bismuth claim 2 , antimony claim 2 , and combinations thereof; R is selected from the group consisting i-propyl claim 2 , n-propyl claim 2 , t-butyl claim 2 , i-butyl claim 2 , n-butyl claim 2 , sec-butyl claim 2 , i-pentyl claim 2 , n-pentyl claim 2 , t-pentyl claim 2 , sec-pentyl and mixtures thereof; and L is selected from the group consisting of amines claim 2 , alkoxy claim 2 , carboxylates claim 2 , halogens claim 2 , and mixtures thereof.4. The method of claim 1 , wherein the organometallic precursor is t-butyl tris(dimethylamino) tin claim 1 , i-butyl tris(dimethylamino) tin claim ...

SEMICONDUCTOR DEVICE WITH FIN ISOLATION

A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile. 1. A semiconductor device , comprising:a substrate;a first semiconductor fin and a second semiconductor fin over the substrate, wherein the second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other, the first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion of the first semiconductor fin faces and is spaced apart from an end sidewall of the second end portion of the second semiconductor fin; anda gate structure extending substantially perpendicularly to the first semiconductor fin, wherein when viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin, and when viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.2. The semiconductor device of claim 1 , wherein when viewed form above claim 1 , the gate structure further overlaps second end portion of the second ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask. 1. A method of manufacturing a semiconductor device , comprising:forming hard mask patterns by sequentially depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate, and etching the hard mask layer;forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask;oxidizing opposite side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer;forming spacer patterns covering side surfaces of the silicon oxide layer;forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns;etching the sacrificial layer and the silicon oxide layer;forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask; andforming activation pins by etching the substrate using the support mask patterns as an etch mask.2. The ...

DRAM SEMICONDUCTOR DEVICE HAVING REDUCED PARASITIC CAPACITANCE BETWEEN CAPACITOR CONTACTS AND BIT LINE STRUCTURES AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes. 1. A semiconductor device , comprising:a plurality of bit line structures disposed on a semiconductor substrate;a first oxide layer disposed on sidewalls of the plurality of bit line structures;a second oxide layer disposed on the first oxide layer in a first region;a capacitor contact disposed between the plurality of bit line structures in a second region, wherein the first oxide layer contacts the plurality of bit line structures and the capacitor contact, and the first region and the second region are arranged in a staggered manner, and a direction of the first region and the second region are perpendicular to directions of the plurality of bit line structures; anda nitride layer disposed on the first oxide layer, the plurality of bit line structures and the capacitor contact, wherein the nitride layer contacts a top surface of the first oxide layer.2. The semiconductor device as claimed in claim 1 , wherein the top surface of the first oxide layer is higher than top surfaces of the plurality of bit line structures.3. The semiconductor device as claimed in claim 1 , further comprising:a plurality of hard masks disposed between the plurality of bit line structures and the nitride layer, wherein sidewalls ...

Method of Reducing Trench Depth Variation from Reactive Ion Etching Process

A semiconductor wafer having a main surface is provided. A first etch resistant mask is provided on the main surface. A first reactive ion etching step that forms a first group of trenches using the first etch resistant mask is performed. Each of the trenches in the first group is covered with a second etch resistant mask after performing the first reactive ion etching step. A second reactive ion etching step that forms a second group of trenches using one or both of the first etch resistant mask and the second etch resistant mask is performed. The trenches in the second group are laterally offset from the trenches in the first group. The first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second group. 1. A method of forming a semiconductor device , the method comprising:providing a semiconductor wafer comprising a main surface;providing a first etch resistant mask on the semiconductor wafer that partially covers the main surface and includes a first set of openings;performing a first reactive ion etching step that forms a first group of trenches by removing semiconductor material through the first set of openings;covering each of the trenches in the first group with a second etch resistant mask after performing the first reactive ion etching step;providing a second set of openings in one or both of: the first etch resistant mask, and the second etch resistant mask, the second set of openings;performing a second reactive ion etching step that forms a second group of trenches by removing semiconductor material through the second set of openings, the trenches in the second group being laterally offset from the trenches in the first group,wherein the first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second groupwherein the first ...

INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact. 1. A method of forming an integrated circuit comprising:forming a heterostructure over a substrate structure, wherein the substrate structure comprises a given semiconductor material;etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material;forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure;forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure;performing a contact fill with conductive material to form a castellated gate contact that extends across the castellated channel region and substantially surrounds each of the plurality of ridge ...

METHODS OF FORMING PATTERNS

Methods of forming patterns are provided. The methods may include sequentially forming an etch-target layer and a photoresist layer on a substrate, exposing two first portions of the photoresist layer to light to transform the two first portions into two first photoresist patterns and exposing a second portion of the photoresist layer to light to transform the second portion into a second photoresist pattern disposed between the two first photoresist patterns. The method may also removing portions of the photoresist layer to leave the two first photoresist patterns and the second photo resist pattern on the etch-target layer such that the etch-target layer is exposed. 1. A method of forming a pattern , comprising:forming an etch-target layer on a substrate;forming a photoresist layer on the etch-target layer;performing a first exposure process to transform first portions of the photoresist layer into first photoresist patterns spaced apart from each other;performing a second exposure process to transform second portions of the photoresist layer into second photoresist patterns spaced apart from each other; andremoving portions of the photoresist layer not transformed into the first and second photoresist patterns to expose a top surface of the etch-target layer,wherein each of the second photoresist patterns is disposed between two directly adjacent ones of the first photoresist patterns.2. The method of claim 1 , further comprising:forming mask patterns in gaps between the first and second photoresist patterns after removing the portions of the photoresist layer;removing the first and second photoresist patterns; andetching the etch-target layer using the mask patterns as an etch mask.3. The method of claim 2 , wherein each of the first and second photoresist patterns has a pillar shape.4. The method of claim 2 , wherein the mask patterns are formed of a metal-containing organic layer.5. The method of claim 1 , further comprising etching the etch-target layer using ...

PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

According to one embodiment, first, an embedment material is embedded between linear core material patterns in such a manner that a height thereof becomes lower than a height of each of the core material patterns. Then, a shrink agent is supplied and solidified on the embedment material. Subsequently, the solidified shrink agent and the embedment material are removed and a spacer film is formed on an object of processing. Then, the spacer film is etched-back and a spacer pattern is formed by removal of the core material patterns. The solidified shrink agent which is formed in such a manner that a width of the spacer pattern becomes narrow in a region corresponding to a position where the shrink agent, in a sectional surface vertical to an extended direction of the spacer pattern is supplied is removed.

Self-Aligned Double Patterning

A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

In a manufacturing method of a semiconductor device according to an embodiment, a mask material comprising at least one layer of a hafnium silicate (HfSiOn (n is a positive number)) film is formed on a processing target film. The processing target material is processed using the mask material as a mask. The hafnium silicate film is located almost at a central portion of the mask material or between the central portion of the mask material and an upper surface thereof.

LIQUID COMPOSITION AND ETCHING METHOD FOR ETCHING SILICON SUBSTRATE

An etching method includes etching a silicon substrate with a liquid composition containing an alkaline organic compound, water, and a boron compound with a content in the range of 1% by mass to 14% by mass. The boron compound is at least one of boron sesquioxide, sodium tetraborate, metaboric acid, sodium perborate, sodium borohydride, zinc borate, and ammonium borate.

Semiconductor Device and Method of Manufacture

A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved. 1. A method of manufacturing a semiconductor device , the method comprising:patterning a first mask material over a substrate to have a first opening, wherein the first mask material has a first thickness and the first opening has a first depth less than the first thickness;irradiating the first mask material with an ion beam after the patterning the first mask material to form an irradiated first mask material; andpatterning the substrate using the irradiated first mask material as a mask.2. The method of claim 1 , wherein the irradiating the first mask material exposes the substrate.3. The method of claim 2 , wherein the patterning the substrate is performed at least in part by irradiating the substrate using the irradiated first mask material as a lens.4. The method of claim 1 , wherein the irradiating the first mask material reshapes the first mask material to form a second opening from the first opening claim 1 , wherein the second opening has a smaller width than the first opening.5. The method of claim 1 , wherein the first mask material comprises aluminum oxide.6. The method of claim 1 , wherein the irradiating the first mask material further comprises irradiating the mask material with gallium ions.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:applying a mask material to a substrate;patterning the mask material to form a first opening in the mask material;irradiating the mask ...

THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region. 1. A method for preserving interlevel dielectric in a gate cut region , comprising:forming a liner in a recess on top of a recessed dielectric fill-in a device region and in a cut region, the liner including a material to provide etch selectivity to protect the recessed dielectric fill;recessing gate structures in the cut region to form a gate recess using the liner to protect the recessed dielectric fill from being etched;removing a gate material from within the gate structures using the liner to protect the recessed dielectric fill from being etched; andforming a dielectric gap fill to replace the gate material and to fill the gate recess in the cut region.2. The method as recited in claim 1 , wherein forming the liner includes:conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill; andplanarizing the liner to remove the liner over the gate structures.3. The method as recited in claim 1 , wherein forming the liner includes:forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.4. The method as recited in claim 1 , wherein forming the liner includes:forming the liner from TiN.5. The method as recited in claim 1 , wherein recessing the gate structures in ...

SEMICONDUCTOR DEVICE STRUCTURE WITH FINE BORON NITRIDE SPACER PATTERNS AND METHOD FOR FORMING THE SAME

The present disclosure provides a semiconductor device structure with fine boron nitride spacer patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first boron nitride spacer disposed over the first target structure, wherein a topmost point of the first boron nitride spacer is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view. 1. semiconductor device structure , comprising:a first target structure and a second target structure disposed over a semiconductor substrate; anda first boron nitride spacer disposed over the first target structure, wherein a topmost point of the first boron nitride spacer is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.2. The semiconductor device structure of claim 1 , further comprising:a second boron nitride spacer disposed over the second target structure, wherein a topmost point of the second boron nitride spacer is between the central line of the first target structure and the central line of the second target structure in the cross-sectional view.3. The semiconductor device structure of claim 1 , wherein the first target structure has a high etching selectivity against the first boron nitride spacer.4. The semiconductor device structure of claim 1 , wherein the first target structure and the second target structure are made of a thermal decomposable material claim 1 , a photonic decomposable material claim 1 , or an e-beam decomposable material.5. The semiconductor device structure of claim 1 , wherein a top surface of the semiconductor substrate is exposed between the first target structure and the second target ...