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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 4745. Отображено 100.

19-07-2012 дата публикации

Semiconductor Device, An Electronic Device and an Electronic Apparatus

Номер: US20120181633A1

Автор: Masayasu Miyata

Принадлежит: Seiko Epson Corp

A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5 ; and a gate insulating film 3 provided between the base 2 and the gate electrode 5 . The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2 , and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.

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Номер записи: 1

30-08-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120220130A1

Автор: Chai-O CHUNG

Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a trench over a substrate, forming a spin on dielectric (SOD) layer in a first part of the trench, and forming an oxide layer within the trench, where the oxide layer is formed over the SOD layer by using a process for plasma chemical vapor deposition.

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Номер записи: 2

06-09-2012 дата публикации

Reduced pattern loading using silicon oxide multi-layers

Номер: US20120225565A1

Автор: Paul Edward Gee, Shankar Venkataraman, Sidharth Bhatia

Принадлежит: Applied Materials Inc

Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

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Номер записи: 3

25-04-2013 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20130099350A1

Автор: Bing-Hung Chen, Chih-tang Peng, Hao-Ming Lien, Tze-Liang Lee

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

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Номер записи: 4

09-05-2013 дата публикации

METHOD FOR DEPOSITING CYCLIC THIN FILM

Номер: US20130115783A1

Автор: Kim Hai Won, Woo Sang Ho

Принадлежит: EUGENE TECHNOLOGY CO., LTD.

Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method comprises the steps of forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; and forming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber. 1. A method of depositing a cyclic thin film , the method comprising the steps of:forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; andforming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber.2. The method of claim 1 , wherein the step of forming the insulating film including silicon comprises injecting one or more reacting gases selected from a group consisting of O claim 1 , O claim 1 , N claim 1 , and NH.3. The method of claim 1 , wherein the insulating film including silicon is a silicon oxide film or a silicon nitride film.4. The method of claim 2 , wherein the step of forming the insulating film including silicon comprises forming the plasma atmosphere by injecting one or more ignition gases selected from a group consisting of Ar claim 2 , He claim 2 , Kr claim 2 , and Xe.5. The method of claim 4 , wherein the ignition gases are injected at flow rate of 100 to 3000 sccm claim 4 , and the reaction gases are injected at flow rate of 10 to 500 sccm.6. The method of claim 1 , wherein the step of forming the insulating film including silicon comprises forming the plasma atmosphere using Oor Oas ...

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Номер записи: 5

13-06-2013 дата публикации

Method of Manufacturing Semiconductor Device, Method of Processing Substrate, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium

Номер: US20130149874A1

Автор: Hirose Yoshiro, Sano Atsushi

Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate. 1. A method of manufacturing a semiconductor device , comprising: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times;', 'forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and', 'modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate., 'forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle comprising2. The method according to claim 1 , wherein the first reactive gas contains a plurality of ligands containing the carbon atoms.3. The method according to claim 1 , wherein the ...

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Номер записи: 6

20-06-2013 дата публикации

Film Deposition Using Tantalum Precursors

Номер: US20130157475A1

Автор: Anthis Jeffrey W., Thompson David

Принадлежит:

Provided are methods of depositing tantalum-containing films via atomic layer deposition and/or chemical vapor deposition. The method comprises exposing a substrate surface to flows of a first precursor comprising TaClR, TaBrRor TaIR, wherein R is a non-halide ligand, and a second precursor comprising an aluminum-containing compound, wherein x has a value in the range of 1 to 4. The R group may be C1-C5 alkyl, and specifically methyl. The resulting films comprise tantalum, aluminum and/or carbon. Certain other methods relate to reacting TaClwith a coordinating ligand to provide TaClcoordinated to the ligand. A substrate surface may be exposed to flows of a first precursor and second precursor, the first precursor comprising the TaClcoordinated to a ligand, the second precursor comprising an aluminum-containing compound. 1. A method of depositing a film , the method comprising exposing a substrate surface to flows of a first precursor comprising TaClR , TaBrRor TaIR , wherein R is a non-halide ligand , and a second precursor comprising an aluminum-containing compound , wherein x has a value in the range of 1 to 4.2. The method of claim 1 , wherein R is C1-C5 alkyl.3. The method of claim 2 , wherein R comprises a methyl group.4. The method of claim 1 , wherein the first precursor is selected from TaClRor TaClR claim 1 , wherein R is a non-halide ligand.5. The method of claim 1 , wherein the aluminum-containing compound comprises an aluminum hydrocarbon.6. The method of claim 5 , wherein the aluminum hydrocarbon comprises one or more of trimethyl aluminum claim 5 , triethyl aluminum or dimethyl aluminum hydride.7. The method of claim 1 , wherein the aluminum-containing compound comprises an alane-amine complex.8. The method of claim 7 , wherein the alane-amine complex comprises dimethylethylamine alane claim 7 , triethylamine alane claim 7 , trimethylamine alane or methylpyrrolidine alane.9. The method of claim 1 , wherein the substrate surface is exposed to ...

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Номер записи: 7

25-07-2013 дата публикации

Low Temperature Deposition of Silicon-Containing Films

Номер: US20130189853A1

Автор: Cheng Hansong, Han Bing, HASEBE Kazuhide, JR. Eugene Joseph, Karwacki, Lei Xinjian, MATSUNAGA Masanobu, Xiao Manchao, Yang Liu, YONEZAWA Masato

Принадлежит:

This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition. 1. A process to deposit silicon nitride or carbon-doped silicon nitride on a substrate in a processing chamber , comprising:a. contacting the substrate with a nitrogen-containing source to absorb at least a portion of the nitrogen-containing source on the substrate;b. purging unabsorbed nitrogen-containing source;c. contacting the substrate with a silicon-containing precursor to react with the portion of the absorbed nitrogen-containing source; andd. purging unreacted silicon-containing precursor;wherein the process is a plasma-enhanced process; and{'sub': x', 'n', 'm-x, 'sup': 1', '2', '1', '2, 'the silicon-containing precursor is monochloroalkylsilane having a general formula of ClSiHRRwherein x=1, 2; m=1, 2, 3; n=0, 1, n+m=<3; Rand Rare linear, branched or cyclic independently selected from the group consisting of alkyl, alkenyl, alkynyl, and aryl having 1-10 carbon atoms.'}2. (canceled)3. (canceled)4. The silicon-containing precursor in is selected from the group consisting of ClSiEtH claim 1 , ClSiEtH claim 1 , ClSi(CH═CH)H claim 1 , ClSi(CH═CH)MeH claim 1 , ClSi(CH═CH)EtH claim 1 , ClSi(CCH)H claim 1 , ClSi(iso-Pr)H claim 1 , ClSi(sec-Bu)H claim 1 , ClSi(tert-Bu)H claim 1 , ClSi(iso-Pr)H claim 1 , ClSi(sec-Bu)H claim 1 , ClSi(tert-Bu)H claim 1 , and mixtures thereof.5. The process of is selected from the group consisting of plasma enhanced atomic layer deposition claim 1 , and plasma enhanced cyclic chemical vapor deposition; wherein the plasma is ...

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Номер записи: 8

31-10-2013 дата публикации

DENSIFICATION FOR FLOWABLE FILMS

Номер: US20130288485A1

Автор: Choi Jun Tae, Hong Sukwon, Liang Jingmei

Принадлежит: Applied Materials, Inc.

A method of forming a dielectric layer is described. The method first deposits an initially-flowable layer on a substrate. The initially-flowable layer is then densified by exposing the substrate to a high-density plasma (HDP). Essentially no additional material is deposited on the initially-flowable layer, in embodiments, but the impact of the accelerated ionic species serves to condense the layer and increase the etch tolerance of the processed layer. 1. A method of forming a dielectric layer on a substrate , the method comprising the sequential steps of:forming a dielectric layer on the substrate, wherein the dielectric layer is flowable during the operation of forming the dielectric layer, andtreating the dielectric layer by exposing the layer to a high density plasma, wherein exposing the layer to the high density plasma increases a density of the dielectric layer.2. The method of wherein a temperature of the substrate is maintained below 400° C. during the operation of treating the dielectric layer.3. The method of wherein a plasma density of the high density plasma is on the order of 10ions/cmor greater.4. The method of wherein the high density plasma is formed from one or more of O claim 1 , O claim 1 , NH claim 1 , NO claim 1 , HO claim 1 , H claim 1 , Ar claim 1 , Nor He.5. The method of wherein the high density plasma is formed by applying an RF power greater than or about 1 kW.6. The method of wherein a vertical thickness of the dielectric layer remains the same or decreases and essentially no new layer is formed above the dielectric layer during the operation of treating the dielectric layer with the high density plasma.7. The method of wherein a step of chemical mechanical polishing occurs after forming the dielectric layer and before treating the dielectric layer to increase its density.8. The method of wherein the sequential steps are repeated at least twice to increase a dielectric density compared with a single deposition sequence of the same total ...

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Номер записи: 9

07-11-2013 дата публикации

HIGH TEMPERATURE ATOMIC LAYER DEPOSITION OF SILICON OXIDE THIN FILMS

Номер: US20130295779A1

Автор: "ONeill Mark Leonard", Chandra Haripin, Han Bing, Lei Xinjian, Pearlstein Ronald Martin, Wang Meiliang, Xiao Manchao

Принадлежит:

Composition(s) and atomic layer deposition (ALD) process(es) for the formation of a silicon oxide containing film at one or more deposition temperature of about 500° C. is disclosed. In one aspect, the composition and process use one or more silicon precursors selected from compounds having the following formulae I, II, described and combinations thereof

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Номер записи: 10

05-12-2013 дата публикации

FILM FORMING METHOD AND APPARATUS

Номер: US20130323935A1

Автор: HEMEL Volker, KADONAGA Kentaro, Suzuki Keisuke, ZOBEL Bernhard

Принадлежит:

A method of forming a thin film on a surface of target objects in a vacuum-evacuable processing chamber by using a source gas and a reaction gas includes: forming a mixed gas by mixing the source gas and an inert gas in a gas reservoir tank, and supplying the mixed gas and the reaction gas into the processing chamber. 1. A method of forming a thin film on a surface of target objects in a vacuum-evacuable processing chamber by using a source gas and a reaction gas , the method comprising:forming a mixed gas by mixing the source gas and an inert gas in a gas reservoir tank; andsupplying the mixed gas and the reaction gas into the processing chamber.2. The method of claim 1 , wherein the mixed gas and the reaction gas are intermittently supplied.3. The method of claim 2 , wherein the mixed gas and the reaction gas are alternately and repeatedly supplied.4. The method of claim 2 , wherein the mixed gas and the reaction gas are simultaneously supplied.5. The method of claim 2 , wherein a purge gas is continuously supplied into the processing chamber.6. The method of claim 2 , further comprising:purging a residual gas remaining in the processing chamber before at least one of supplying the mixed gas and supplying the reaction gas.7. The method of claim 6 , wherein claim 6 , during the purging claim 6 , an inert gas is supplied in a pulse-like manner by a plurality of times.8. The method of claim 1 , wherein the mixed gas is intermittently supplied and the reaction gas is continuously supplied.9. The method of claim 1 , wherein a volume ratio of the source gas to the mixed gas in the gas reservoir tank ranges from 1/2 to 1/8.10. The method of claim 1 , wherein the source gas and the inert gas are introduced into the gas reservoir tank in a timely offset manner.11. The method of claim 1 , wherein the source gas and the inert gas are introduced into the gas reservoir tank simultaneously.12. The method of claim 1 , wherein the reaction gas includes a gas selected from a group ...

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Номер записи: 11

19-12-2013 дата публикации

APPARATUS FOR THE DEPOSITION OF HIGH DIELECTRIC CONSTANT FILMS

Номер: US20130333621A1

Автор: COLLINS Richard Omar, METZNER Craig R., RONSSE Bobby M.

Принадлежит:

An integrated deposition system is described that is capable of vaporizing low vapor pressure liquid precursors and conveying the vapor to a processing region to fabricate advanced integrated circuits. The integrated deposition system includes a heated exhaust system, a remote plasma generator, a processing chamber, a liquid delivery system, and a computer control module that together create a commercially viable and production worthy system for depositing high capacity dielectric materials from low vapor pressure precursors. 1. An apparatus for depositing a film , the apparatus comprising:a chamber body having a processing region defined therein;a vaporizer;a vapor delivery system having a first region beginning at the vaporizer, a second region communicating with the processing region and a third region disposed between the first and second regions, wherein the first region is maintained at a lower temperature than the second region; anda chamber lid disposed on the chamber body and having inner and outer temperature control regions.2. The apparatus of claim 1 , wherein a temperature gradient defined over the first and second regions is between about 20 to about 25 degrees Celsius.3. The apparatus of claim 1 , wherein the first vapor path further comprises:a carrier gas supply line is coupled to the first vapor path at a transition between the first and third regions.4. The apparatus of claim 1 , wherein a diameter of the third region is greater than a diameter of the first region and less than a diameter of the second region.5. The apparatus of claim 1 , wherein a temperature of the third region is greater than a temperature of the first region and less than a temperature of the second region.6. The apparatus of further comprising:a hafnium precursor source coupled to the vaporizer.7. The apparatus of claim 6 , wherein the temperature gradient is maintained between a minimum temperature of 100 degrees Celsius and a maximum temperature of 190 degrees Celsius.8. An ...

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Номер записи: 12

19-12-2013 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130337625A1

Автор: Fujiwara Naonori

Принадлежит:

The present invention provides a method for manufacturing a semiconductor device including a metal compound film formation process based on an atomic layer deposition (ALD) with repeating a plurality of cycles in which a supply time of a metallic source gas at the first time of the cycles is longer than a supply time of the source gas at the second time or later of the cycles, the ALD including, as one cycle, supplying the metallic source gas to adsorb a metallic source onto a foundation; purging the metallic source gas from a film-forming space; supplying a reactant gas to convert the metallic source into a corresponding metal compound; and purging the reactant gas. 2. The method as claimed in claim 1 , wherein the supply time of the source gas in the first cycle is longer than the supply time of the source gas in each of the second cycle or later cycle.3. The method as claimed in claim 1 , wherein the first cycle is to deposit a first layer on a material as the foundation inferior in adsorption ability with respect to the metallic source to the first layer and the second cycle is to deposit a second layer on the first layer.4. The method as claimed in claim 1 , wherein supplying the reactant gas includes supplying an oxidizing gas as the reactant gas to form a metal oxide film by repeating a plurality of cycles.5. The method as claimed in claim 4 , wherein the metallic source comprises zirconium as a metallic element.6. The method as claimed in claim 5 , wherein the metallic source is tetrakis(ethyl-methyl-amino) zirconium.7. The method as claimed in claim 6 , wherein the supply time of the source gas in the first cycle is 250 to 420 seconds and the supply time of the source gas in the second cycle or later is 75 to 150 seconds.8. The method as claimed in claim 7 , wherein the supply time of the source gas in the first cycle is 300 to 350 seconds and the supply time of the source gas in the second cycle or later is 90 to 120 seconds.9. The method as claimed in ...

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Номер записи: 13

02-01-2014 дата публикации

SILICON OXIDE FILM FORMING METHOD AND APPARATUS

Номер: US20140004715A1

Автор: KUROKAWA Masaki, OBU Tomoyuki

Принадлежит:

A method of forming a silicone oxide film includes: forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; and modifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere. 1. A method of forming a silicone oxide film , comprising:forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; andmodifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere.2. The method of claim 1 , wherein the chlorine-containing silicon source includes one of tetrachlorosilane claim 1 , trichlorosilane claim 1 , dichlorosilane claim 1 , monochlorosilane and hexachlorodisilane.3. The method of claim 1 , wherein a temperature in the reaction chamber is maintained at 600 to 1000 degrees C. at forming the silicone oxide film and modifying the silicon oxide film.4. The method of claim 1 , wherein a temperature in the reaction chamber at forming the silicone oxide film is equal to a temperature in the reaction chamber at modifying the silicon oxide film.5. The method of claim 1 , wherein modifying the silicon oxide film includes supplying the hydrogen and the oxygen into the reaction chamber at a ratio of a supply amount of the oxygen to a supply amount of the hydrogen ranging from 1.2:1 to 3:1.6. A silicone oxide film forming apparatus claim 1 , comprising:a film forming unit ...

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Номер записи: 14

09-01-2014 дата публикации

SILICON OXIDE FILM FORMING METHOD AND APPARATUS

Номер: US20140011371A1

Автор: KUROKAWA Masaki, OBU Tomoyuki

Принадлежит: TOKYO ELECTRON LIMITED

A silicone oxide film forming method includes forming a silicon oxide film on a plurality of target objects by supplying a chlorine atom-containing silicon source into a reaction chamber accommodating the plurality of target objects. Forming the silicon oxide film includes making an interior of the reaction chamber be under a hydrogen atmosphere by supplying a hydrogen gas into the reaction chamber. 1. A method of forming a silicone oxide film , comprising:forming a silicon oxide film on a plurality of target objects by supplying a chlorine atom-containing silicon source into a reaction chamber accommodating the plurality of target objects,wherein forming the silicon oxide film includes making an interior of the reaction chamber be under a hydrogen atmosphere by supplying a hydrogen gas into the reaction chamber.2. The method of claim 1 , wherein the chlorine atom-containing silicon source includes one of tetrachlorosilane claim 1 , trichlorosilane claim 1 , dichlorosilane claim 1 , monochlorosilane and hexachlorodisilane.3. The method of claim 1 , wherein a temperature in the reaction chamber is maintained at 600 to 1000 degrees C. at forming the silicone oxide film.4. The method of claim 1 , wherein a supply amount of the hydrogen gas supplied into the reaction chamber is 0.5 to 5 times of a supply amount of the chlorine atom-containing silicon source.5. A silicone oxide film forming apparatus claim 1 , comprising:a film forming gas supply unit configured to supply a film forming gas into a reaction chamber accommodating a plurality of target objects, the film forming gas having a chlorine atom-containing silicon source;a hydrogen supply unit configured to supply a hydrogen gas into the reaction chamber; anda control unit configured to control the film forming gas supply unit and the hydrogen supply unit,wherein the control unit controls the hydrogen supply unit such that the hydrogen supply unit supplies the hydrogen gas into the reaction chamber, thus making an ...

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Номер записи: 15

09-01-2014 дата публикации

Film deposition method

Номер: US20140011372A1

Автор: Hiroyuki Kikuchi, Hitoshi Kato, Takeshi Kumagai, Tatsuya Tamura

Принадлежит: Tokyo Electron Ltd

A film deposition method deposits a silicon oxide film on a substrate in which a concave portion is formed by supplying a silicon-containing gas to the substrate so that the silicon-containing gas is adsorbed on the substrate and by oxidizing the adsorbed silicon-containing gas with an oxidation gas. A gas-phase temperature in an atmosphere above the substrate to which the silicon-containing gas is supplied can be kept lower by an inactive gas supplied from a separation area that separates the silicon gas supply part and the oxidation gas supply part even if the substrate is heated to a temperature higher than a temperature that can decompose the silicon-containing gas. Accordingly, the silicon-containing gas can adsorb on the substrate without decomposing in the gas phase.

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Номер записи: 16

20-02-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

Номер: US20140051261A1

Автор: Hirose Yoshiro, Ota Yosuke

Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber. 1. A method of manufacturing a semiconductor device , comprising:forming an oxycarbonitride film, an oxycarbide film or an oxide film containing a specific element on a substrate by alternately performing a specific number of times:forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; andforming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, or an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber.2. The method of claim 1 , whereinin forming the first layer, supplying the first source and supplying the second source are alternately performed once;in forming the second layer, the oxygen-containing gas is supplied; andforming the first layer and forming the second layer are alternately performed the specific number of times, to thereby form the oxycarbonitride film or the oxycarbide film containing the specific element, on the ...

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Номер записи: 17

27-02-2014 дата публикации

METHOD FOR FORMING SILICON OXIDE FILM OF SEMICONDUCTOR DEVICE

Номер: US20140057458A1

Автор: HAN Ji Hye, Hong Kwon, KIM Hyung Hwan, LEE Geun Su, LEE Jong Min, Park Hyung Soon

Принадлежит: SK HYNIX INC.

A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved. 1. A method for forming a silicon oxide film of a semiconductor device comprising:depositing a silicon oxide precursor over a semiconductor substrate, a surface of the semiconductor substrate including a step coverage region; andforming a silicon oxide film by curing the silicon oxide precursor,wherein the surface of the semiconductor substrate is treated with an amine-based compound.2. The method according to claim 1 , wherein the step coverage region includes any of a trench claim 1 , a contact hole claim 1 , and two or more conductive patterns.3. The method according to claim 1 , wherein the silicon oxide precursor compound comprises a silicon-containing compound and a solvent.4. The method according to claim 3 , wherein the silicon-containing compound has a weight-average molecular weight of 3000-7000 claim 3 , the silicon-containing compound being any of a polysilazane compound claim 3 , and a trisilylamine compound.5. The method according to claim 3 , wherein the solvent is any of dibutyl ether claim 3 , benzene claim 3 , toluene claim 3 , xylene claim 3 , and diisopropyl ether.6. The method according to claim 1 , wherein the silicon oxide precursor is applied by a coating or a deposition process.7. The method according to claim 6 , wherein the coating or deposition process is carried out under a room temperature condition.8. The method according to claim 1 , wherein the curing process is carried out by any of a steam annealing claim 1 , a thermal annealing claim 1 , an inductively coupled plasma annealing claim 1 , an ultraviolet annealing claim 1 , an e-beam annealing claim 1 , an acid-vapor catalytic decomposition annealing claim 1 , a base-vapor catalytic ...

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Номер записи: 18

06-03-2014 дата публикации

Method of forming a material layer in a semiconductor structure

Номер: US20140065808A1

Автор: Boris Bayha, Carsten Grass, Martin Trentzsch, Peter Krottenthaler

Принадлежит: Globalfoundries Inc

A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

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Номер записи: 19

13-03-2014 дата публикации

PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS

Номер: US20140073113A1

Автор: NAKAHARA Yoichi

Принадлежит: TOKYO ELECTRON LIMITED

A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited. 1. A plasma etching method , comprising:depositing a silicon-containing deposit by plasma process using Si-containing gas on an object to be processed which includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the plurality of narrow linear portions and the film to be processed which is exposed between the plurality of narrow linear portions; andetching the deposit by plasma of CF-based gas and CHF-based gas after depositing the silicon-containing deposit so as to expose the plurality of narrow linear portions of the organic film and the film to be processed between the plurality of narrow linear portions.2. The plasma etching method of claim 1 , further comprising:ashing the exposed organic film so as to selectively remove the exposed organic film;etching the rigid film remaining after the etching the deposit; andetching the film to be processed using the remaining rigid film as a mask.3. The plasma etching method of claim 1 , wherein bias voltage is applied in the depositing the silicon-containing deposit.4. The plasma etching method of claim 1 , further comprising:performing a surface modifying processing on the silicon-containing deposit using plasma by hydrogen gas ...

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Номер записи: 20

13-03-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Номер: US20140073142A1

Автор: HARADA Katsuyoshi, Hirose Yoshiro, Sano Atsushi, SHIMAMOTO Satoshi

Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A thin film having high HF resistance and a low dielectric constant can be formed in a low temperature range with a high productivity. A thin film including a predetermined element and a borazine ring skeleton is formed on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a source gas including the predetermined element and a halogen group to the substrate and supplying a reaction gas including a borazine compound to the substrate under a condition where the borazine ring skeleton in the borazine compound is maintained. 1. A method of manufacturing a semiconductor device , the method comprising forming a thin film including a predetermined element and a borazine ring skeleton on a substrate by performing a cycle a first predetermined number of times , the cycle comprising:supplying a source gas including the predetermined element and a halogen group to the substrate; andsupplying a reaction gas including a borazine compound to the substrate,wherein the cycle is performed under a condition where the borazine ring skeleton in the borazine compound is maintained.2. The method according to claim 1 , wherein in the act of supplying the source gas claim 1 , a first layer including the predetermined element and the halogen group is formed claim 1 , andwherein in the act of supplying the reaction gas, a second layer including the predetermined element and the borazine ring skeleton is formed by causing the first layer to react with the borazine compound to modify the first layer.3. The method according to claim 2 , wherein in the act of supplying the reaction gas claim 2 , the halogen group included in the first layer is caused to react with a ligand included in the borazine compound.4. The method according to claim 2 , wherein in the act of supplying the reaction gas claim 2 , the halogen group included in the first layer is caused to react with a ligand included in the borazine compound to separate the halogen group reacted ...

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Номер записи: 21

01-01-2015 дата публикации

Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus, and Non-transitory Computer-readable Recording Medium

Номер: US20150004804A1

Автор: Hirose Yoshiro, ORIHASHI Yugo

Принадлежит:

A thin film having a low dielectric constant and a high resistance to HF at a low temperature range is formed with high productivity. A film containing a predetermined element, oxygen and at least one of carbon and nitrogen is formed on a substrate by performing, a predetermined number of times, a cycle comprising: (a) supplying a source gas containing the predetermined element to the substrate; and (b) supplying a reaction gas containing nitrogen, carbon and oxygen to the substrate. 1. A method of manufacturing a semiconductor device , comprising forming a film containing a predetermined element , oxygen and at least one of carbon and nitrogen on a substrate by performing , a predetermined number of times , a cycle comprising: (a) supplying a source gas containing the predetermined element to the substrate; and (b) supplying a reaction gas containing nitrogen , carbon and oxygen to the substrate.2. The method of claim 1 , wherein a first layer containing the predetermined element is formed in (a) claim 1 , andthe first layer is modified by reacting with the reaction gas to form a second layer containing the predetermined element, oxygen, carbon and nitrogen in (b).3. The method of claim 1 , wherein the reaction gas contains an isocyanate group.4. The method of claim 1 , wherein the source gas contains the predetermined element and one of a halogen element and an amino group.5. The method of claim 1 , wherein a first layer containing the predetermined element and one of a halogen element and an amino group is formed in (a) claim 1 , andthe one of the halogen element and the amino group in the first layer reacts with a ligand of the reaction gas in (b).6. The method of claim 5 , wherein the one of the halogen element and the amino group is separated from the first layer and the ligand is separated from the reaction gas in (b).7. The method of claim 6 , wherein atoms of the predetermined element in the first layer having the one of the halogen element and the amino ...

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Номер записи: 22

01-01-2015 дата публикации

LOW-K OXIDE DEPOSITION BY HYDROLYSIS AND CONDENSATION

Номер: US20150004806A1

Автор: ANTONELLI George Andrew, Draeger Nerissa Sue, Ndiege Nicholas Muga, Nittala Krishna, van Cleemput Patrick A., Wong Derek B.

Принадлежит:

Methods for depositing flowable dielectric films using halogen-free precursors and catalysts on a substrate are provided herein. Halogen-free precursors and catalysts include self-catalyzing aminosilane compounds and halogen-free organic acids. Flowable films may be used to fill pores in existing dielectric films on substrates having exposed metallization layers. The methods involve hydrolysis and condensation reactions. 1. A method of depositing a film on a semiconductor substrate , the method comprising:introducing process gases comprising a silicon-containing precursor, an oxidant, and a halogen-free acid catalyst compound to a reaction chamber; andexposing the substrate to the process gases under conditions such that a condensed flowable film forms on the substrate,{'sub': 'N', 'wherein the chemical reactions that form the flowable film comprise a S1 hydrolysis mechanism and condensation.'}2. The method of claim 1 , wherein the halogen-free catalyst compound is selected from the group consisting of acetic acid claim 1 , and photosensitive organic acid catalysts.3. The method of claim 2 , wherein the photosensitive organic acid catalyst is selected from the group consisting of sulfonic acid claim 2 , picric acid claim 2 , tartaric acid claim 2 , citric acid claim 2 , ethylenediaminetetraacetic acid claim 2 , pyrophosphoric acid claim 2 , substituted derivatives of these acids claim 2 , and combinations thereof.4. The method of claim 2 , wherein the substrate is exposed to the process gases while the substrate is exposed to UV radiation.5. The method of claim 1 , wherein the oxidant is selected from the group consisting of water claim 1 , ozone claim 1 , and peroxide.6. The method of claim 1 , wherein the silicon-containing precursor and the oxidant are introduced to the reaction chamber via separate inlets.7. The method of claim 1 , wherein the halogen-free catalyst compound is introduced to the reaction chamber separate from the silicon-containing precursor and ...

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Номер записи: 23

05-01-2017 дата публикации

Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device

Номер: US20170004966A1

Автор: Sato Takayuki

Принадлежит:

A substrate processing apparatus includes: a plasma generating unit to excite a process gas into plasma state; a process chamber where a substrate is processed using the process gas excited in plasma state; a loading port installed at a sidewall of the process chamber, wherein the substrate is passed through the loading port when the substrate is loaded into the process chamber; a substrate support supporting the substrate in the process chamber; an electrode unit installed in the substrate support and including a plurality of divided electrodes; an impedance adjusting unit electrically connected to each of the plurality of electrodes to adjust an impedance thereof; and a control unit to control the impedance of the impedance adjusting unit so as to adjust the electrical potentials of the respective electrodes of the electrode unit. The substrate processing apparatus improves the uniformity of a substrate during a substrate processing process using plasma. 1. A substrate processing apparatus comprising:a plasma generating unit configured to excite a process gas into plasma state;a process chamber where a substrate is processed using the process gas excited in plasma state;a loading port installed at a sidewall of the process chamber, wherein the substrate is passed through the loading port when the substrate is loaded into the process chamber;a substrate support supporting the substrate in the process chamber;an electrode unit installed in the substrate support and including a plurality of divided electrodes;an impedance adjusting unit electrically connected to each of the plurality of electrodes and configured to adjust an impedance thereof; anda control unit configured to control the impedance of the impedance adjusting unit so as to adjust the electrical potentials of the respective electrodes of the electrode unit, wherein the control unit controls the impedance adjusting unit such that an impedance of an electrode positioned in a direction facing the loading ...

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Номер записи: 24

05-01-2017 дата публикации

SELECTIVE DEPOSITION OF SILICON OXIDE FILMS

Номер: US20170004974A1

Автор: Mallick Abhijit Basu, Manna Pramit

Принадлежит:

Embodiments described herein generally provide a method for filling features formed on a substrate. In one embodiment, a method for selectively forming a silicon oxide layer on a substrate is provided. The method includes selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature. 1. A method for selectively forming a silicon oxide layer on a substrate , comprising:selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by exposing the patterned feature to tetraethyl orthosilicate (TEOS) and ozone.2. The method of claim 1 , further comprising:after the selectively depositing a silicon oxide layer within the patterned feature, annealing the selectively deposited silicon oxide layer.3. The method of claim 2 , further comprising:after the annealing the selectively deposited silicon oxide layer, wet etching the silicon oxide layer.4. The method of claim 1 , wherein the tetraethyl orthosilicate (TEOS) flows into a 300 mm substrate processing chamber at a rate between 400 mg/minute and 2 g/minute.5. The method of claim 4 , wherein the ozone flows into the 300 mm substrate ...

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Номер записи: 25

05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20170005055A1

Автор: Suzuki Shinya

Принадлежит:

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are ...

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Номер записи: 26

07-01-2016 дата публикации

METHOD FOR SELECTIVELY DEPOSITING A LAYER ON A THREE DIMENSIONAL STRUCTURE

Номер: US20160005607A1

Автор: Omstead Thomas R., Renau Anthony, Russell Simon

Принадлежит:

A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion. 1. A method , comprising:providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane;directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam;directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; andproviding a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness of the layer grown on the second portion.2. The method of claim 1 , further comprising providing the second species as reactive ions to the substrate before the directing the angled ions claim 1 , wherein the reactive ions form a sub- ...

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Номер записи: 27

07-01-2016 дата публикации

ETCHING METHOD, ETCHING APPARATUS AND STORAGE MEDIUM

Номер: US20160005621A1

Автор: NARUSHIMA Kensaku, Takahashi Hiroyuki, TODA Satoshi

Принадлежит:

A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times. 1. A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by a pattern layer and stopping the etching before a base layer of the silicon oxide film is etched , the method comprising:heating the target substrate in a vacuum atmosphere;intermittently supplying, as an etching gas, at least one of a first processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a second processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit in multiple cycles.2. The method of claim 1 , wherein a time period of said supplying the etching gas to the target substrate in each cycle is about 0.5 sec to 5 sec.3. The method of claim 1 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.4. The method of claim 2 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.5. The method of claim 1 , wherein the compound of nitrogen claim 1 , hydrogen and fluorine is either NHF or NHFHF.6. The method of claim 2 , wherein the compound of nitrogen claim 2 , hydrogen and fluorine is either NHF or NHFHF.7. The method of claim 3 , wherein the compound of nitrogen claim 3 , hydrogen and fluorine is either NHF or NHFHF.8. The method of claim ...

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Номер записи: 28

07-01-2021 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Номер: US20210005448A1

Автор: NAKATANI Kimihiko

Принадлежит: KOKUSAI ELECTRIC CORPORATION

There is provided a technique that includes: forming a silicon oxide film having a non-stoichiometric composition on a substrate by repeating a cycle a plurality of times, the cycle including non-simultaneously performing: (a) adsorbing a pseudo catalyst on a surface of the substrate by supplying the pseudo catalyst to the substrate; (b) adsorbing silicon contained in a silicon hydride on the surface of the substrate by action of the pseudo catalyst adsorbed on the surface of the substrate by supplying the silicon hydride to the substrate; and (c) oxidizing the silicon adsorbed on the surface of the substrate by supplying an oxidizing agent to the substrate under a condition in which atomic oxygen is not generated. 1. A method of manufacturing a semiconductor device , comprising: (a) adsorbing a pseudo catalyst on a surface of the substrate by supplying the pseudo catalyst to the substrate;', '(b) adsorbing silicon contained in a silicon hydride on the surface of the substrate by action of the pseudo catalyst adsorbed on the surface of the substrate by supplying the silicon hydride to the substrate; and', '(c) oxidizing the silicon adsorbed on the surface of the substrate by supplying an oxidizing agent to the substrate under a condition in which atomic oxygen is not generated., 'forming a silicon oxide film having a non-stoichiometric composition on a substrate by repeating a cycle a plurality of times, the cycle including non-simultaneously performing2. The method according to claim 1 , wherein a ratio of the number of silicon atoms to the number of oxygen atoms in the silicon oxide film having the non-stoichiometric composition is larger than a ratio of the number of silicon atoms to the number of oxygen atoms in a silicon oxide film having a stoichiometric composition.3. The method according to claim 1 , wherein the silicon oxide film having the non-stoichiometric composition is made of a substance represented by a chemical formula SiO(where 1.5≤x≤1.9).4. The ...

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Номер записи: 29

07-01-2021 дата публикации

METHOD OF FORMING A STRUCTURE ON A SUBSTRATE

Номер: US20210005449A1

Автор: Blanquart Timothee, de Roest David

Принадлежит:

The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: 1. A method of providing a structure by depositing a layer on a substrate in a reactor , the method comprising: [{'sub': 2n+2−y−z', 'in', 'y', 'z, '(1) HSXA, wherein the formula (1) compound is a cyclic compound, n=3-10, y=1 or more and up to 2n−z, z=0 or more and up to 2n−y, X is I or Br, and A is a halogen other than X;'}, {'sub': 2n+2−y−z−w', 'n', 'y', 'z', 'w, '(2) HSiXAR, wherein, n=1-10, y=1 or more and up to 2n+2−z−w, z=0 or more and up to 2n+2−y−w, w=0 or more and up to 2n+2−y−z, X is I or Br, A is a halogen other than X, and R is an organic ligand; or'}, {'sub': 2n+2−y−z−w', 'n', 'y', 'z', 'w, 'sup': II', 'II, '(3) HSiXAR, wherein, n=1-10, y=0 or more and up to 2n+2−z−w, z=0 or more and up to 2n+2−y−w, w=1 or more and up to 2n+2−y−z, X is I or Br, A is a halogen other than X, and Ris an organic ligand containing I or Br;'}], 'introducing a silicon halide precursor, wherein the silicon halide precursor has a general formulaand wherein the silicon halide comprises at least one hydrogen;introducing a reactant gas comprising one or more of oxygen, helium, and argon in the reactor;providing an energy source to create a plasma from the reactant gas to form reactive species; andusing the reactive species, forming a layer comprising silicon dioxide.2. The method according to claim 1 , wherein the reactant gas comprises less than 5000 ppm nitrogen.3. The method according to claim 1 , wherein the method comprises a PECVD process.4. The method according to claim 1 , wherein the reactant gas comprises argon.5. The method according to claim 1 , wherein a temperature within a reaction chamber of the reactor is between 25° C. and 700° C.6. The method according to claim 1 , wherein the plasma is remotely generated.7. The method according to claim 1 , wherein at least one of the silicon halide precursor and the reactant gas is pulsed to the ...

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Номер записи: 30

04-01-2018 дата публикации

FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE

Номер: US20180006035A1

Автор: Liu Yanxiang, RIM Kern, Yuan Jun

Принадлежит:

Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET. 1. A Fin Field Effect Transistor (FinFET) complementary metal oxide semiconductor (CMOS) circuit , comprising:a semiconductor substrate;a P-type FinFET comprising a first Fin formed from the semiconductor substrate and corresponding to a P-type semiconductor material (P-type) diffusion region;an N-type FinFET comprising a second Fin formed from the semiconductor substrate and corresponding to an N-type semiconductor material (N-type) diffusion region;a first single diffusion break (SDB) isolation structure formed in the first Fin on a first side of a gate of the P-type FinFET;a second SDB isolation structure formed in the first Fin on a second side of the gate of the P-type FinFET opposite of the first side of the gate of the P-type FinFET;a first double diffusion break (DDB) isolation structure formed in the second Fin on a first side of a gate of the N-type FinFET; anda second DDB isolation structure formed in the second Fin on a second side of the gate of the N-type FinFET opposite of the first side of the gate of the N-type FinFET.2. The FinFET ...

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Номер записи: 31

02-01-2020 дата публикации

Treatment for Adhesion Improvement

Номер: US20200006055A1

Автор: CHANG CHIH-WEI, Chen Ching-Yi, CHEN HUNG-HSU, Loh Wei-Yip

Принадлежит:

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer. 1. A method comprising:forming an opening in an insulating layer of a structure;depositing an adhesion layer in the opening;incorporating nitrogen atoms into the adhesion layer; anddepositing metal into the opening, the metal forming an interlayer interposed between a metal plug and the adhesion layer, the interlayer comprising a compound of the metal and nitrogen.2. The method of claim 1 , wherein the adhesion layer comprises non-crystalline TiN.3. The method of claim 1 , wherein the metal of the metal plug comprises Co.4. The method of claim 1 , wherein incorporating nitrogen atoms into the adhesion layer comprises applying an N/Hplasma treatment to the adhesion layer.5. The method of claim 4 , further comprising:prior to depositing the metal, soaking the structure in silane, wherein the compound includes silicon.6. The method of claim 1 , further comprising:prior to depositing the adhesion layer, depositing a metal layer in the opening; andforming a silicide.7. The method of claim 6 , wherein the adhesion layer is a nitride of the metal of the metal layer.8. The method of claim 1 , wherein the metal nitride interlayer comprises a first crystalline structure claim 1 , wherein the metal plug comprises a second crystalline structure claim 1 , and wherein the first crystalline structure and second crystalline structure have a lattice ...

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Номер записи: 32

02-01-2020 дата публикации

Device and Method for High Pressure Anneal

Номер: US20200006063A1

Автор: C.P. Liao, Cheng-Po CHAU, Sen-Hong Syue, Szu-Ying Chen, Y.C. Chan, Y.H. Wang, Ya-Wen Chiu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

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Номер записи: 33

02-01-2020 дата публикации

Methods of Sealing Openings, and Methods of Forming Integrated Assemblies

Номер: US20200006113A1

Автор: YANG Guangjun

Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening. 132-. (canceled)33. A method of forming an integrated assembly , comprising: 'covering an upper portion of the opening with a sealant material and leaving a lower portion of the opening empty.', 'providing a construction having an opening between a pair of spaced structures; and'}34. The method of wherein the covering comprises providing a mass of material on at least one of the pair of structures and processing the mass of material to form the sealant material.35. The method of further comprising treating the sealant material to fill any pinholes present in the sealant material.36. The method of wherein the covering comprises providing a mass of material adjacent the opening and processing the mass of material to form the sealant material.37. The method of wherein the covering comprises providing a mass of material and sputtering particles from the mass of material to form the sealant material.38. The method of wherein the providing and the sputtering are performed simultaneously.3942322. The method of wherein the providing and the sputtering are conducted within a reaction chamber in the presence of chemical species which include SiCl together with one or more of O claim 38 , O claim 38 , HO.40. The method of wherein the sputtering occurs after the providing.41. The method of wherein the mass of material comprises one or more elements selected from group 14 of the periodic table.42. The method of wherein the mass of material comprises one or more elements selected from group 14 of the periodic ...

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Номер записи: 34

03-01-2019 дата публикации

METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS

Номер: US20190006232A1

Автор: Chanemougame Daniel, Han Geng, LIEBMANN Lars, Xie Ruilong

Принадлежит:

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions. 1. An integrated circuit product , comprising:a first layer of insulating material comprising a first insulating material positioned above a device layer of a semiconductor substrate, the device layer comprising transistors;a metallization blocking structure positioned in an opening in the first layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material;a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure; anda conductive metallization line comprising first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure, wherein the conductive metallization line has a long axis extending along the first and second portions.2. The product of claim 1 , wherein the first insulating material and the second insulating material are selectively etchable relative to one another.3. The product of claim 1 , wherein the first insulating material comprises silicon and oxygen ...

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Номер записи: 35

08-01-2015 дата публикации

NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR PRODUCING NON-VOLATILE SEMICONDUCTOR MEMORY

Номер: US20150008500A1

Автор: Fukumoto Yohei, Sasaki Takaoki

Принадлежит:

A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate. 1. A non-volatile semiconductor memory comprising:a silicon substrate;a first silicon oxide film;a second silicon oxide film;a first silicon nitride film; anda second silicon nitride film, whereinthe first silicon oxide film is layered on the silicon substrate,the first silicon nitride film is layered on the first silicon oxide film,the second silicon oxide film is layered on the first silicon nitride film, andthe second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate.2. A non-volatile semiconductor memory comprising:a silicon substrate;a first silicon oxide film;a second silicon oxide film;a third silicon oxide film;a first silicon nitride film; anda second silicon nitride film, whereinthe first silicon oxide film is layered on the silicon substrate,the first silicon nitride film is layered on the first silicon oxide film,the second silicon oxide film is layered on the first silicon nitride film,the third silicon oxide film has a thickness that is smaller than that of the first silicon oxide film, andthe second silicon nitride film has a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon ...

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Номер записи: 36

12-01-2017 дата публикации

Furnace-type semiconductor apparatus, method of cleaning the same, and method of forming thin film using the same

Номер: US20170008042A1

Автор: Giduck Kweon, Hyouncheol Kim, Jong-Il Park, lnwoo Seo, Wooksung Son, Youngil Kwon

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Embodiments of the inventive concepts provide a method of cleaning a furnace-type semiconductor apparatus that is equipped in a clean room and includes a process chamber in which a process of forming a thin film is performed on a substrate. The method includes supplying air of the clean room into the process chamber after the process of forming the thin film, and thermally treating an inside of the process chamber using the air of the clean room supplied to the inside of the process chamber. An adhered material containing chlorine is formed on an inner surface of the process chamber by the process of forming the thin film, and the chlorine of the adhered material is removed by the thermal treatment of the inside of the process chamber.

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Номер записи: 37

20-01-2022 дата публикации

DEFECTIVE CHIP PROCESSING METHOD

Номер: US20220020650A1

Автор: Greenlaw David

Принадлежит:

When a chip, or manufactured integrate circuit, is found to have a portion that is defective, “floorsweeping” may be used to salvage the working portion of the chip. Floorsweeping involves downgrading, or turning off, the portion of the chip with the defect and then operating the remaining portion of the chip as a lower quality chip than the larger chip that was originally intended. In use, applications will then only use the active portion of the chip. However, the resulting lower quality chip will still have the same static leakage of the larger, non-defective chip. This leakage results from a voltage still being applied to the entire area of the larger chip, even though a portion of that area has been downgraded. The present disclosure provides a method for processing defective chips to form a smaller chip that avoids the excess static leakage associated with floorsweeping by physically removing the defective portion of the chip. 1. A method , comprising:identifying a defective portion of a chip;physically cutting the defective portion of the chip away from a working portion of the chip;polishing a cut side of the working portion of the chip.2. The method of claim 1 , wherein the chip is a graphics processing unit (GPU).3. The method of claim 1 , wherein the chip includes repeating sub-blocks.4. The method of claim 3 , wherein the defective portion of the chip includes one or more neighboring sub-blocks of the repeating sub-blocks.5. The method of claim 1 , wherein the defective portion of the chip is identified from results of testing of the chip.6. The method of claim 1 , wherein physically cutting the defective portion of the chip away from the working portion of the chip includes making at least one of a vertical laser cut or a horizontal laser cut through the chip.7. The method of claim 6 , wherein the at least one of the vertical laser cut or the horizontal laser cut is made in a lane existing between the defective portion of the chip and the working ...

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Номер записи: 38

08-01-2015 дата публикации

BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY

Номер: US20150011050A1

Автор: Chiu Chia-Pin, Manusharow Mathew J., Qian Zhiguo

Принадлежит:

Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. 119-. (canceled)20. A method , comprising:forming a sacrificial layer on a surface of a bridge substrate comprising a glass, ceramic, or a semiconductor material;forming an electrically conductive layer on the sacrificial layer, the electrically conductive layer being coupled with the surface of the bridge substrate through the sacrificial layer by an electrically conductive material; andremoving material of the sacrificial layer to provide an air gap between the surface of the bridge substrate and the electrically conductive layer.21. The method of claim 20 , further comprising:prior to forming the sacrificial layer, forming electrical routing features through the bridge substrate and on the surface of the bridge substrate, the electrical routing features including through-hole vias, traces, and pads.22. The method of claim 20 , wherein forming the sacrificial layer comprises depositing silicon oxide (SiO).23. The method of claim 21 , further comprising:prior to forming the electrically conductive layer, forming openings in the sacrificial layer to expose one or more of the electrical routing features; ...

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Номер записи: 39

27-01-2022 дата публикации

INTERLAYER DIELECTRIC LAYER STRUCTURE FOR POWER MOS DEVICE AND METHOD FOR MAKING THE SAME

Номер: US20220028984A1

Автор: CHEN Zhengrong, JIN Lipei, LIU Xiuyong, WU Changming, Zhang Jiliang

Принадлежит: HUA HONG SEMICONDUCTOR (WUXI) LIMITED

The present application relates to the field of semiconductor forming technologies, in particular to an interlayer dielectric layer structure for a power MOS device and a method for making the same. The interlayer dielectric layer structure for a power MOS device comprises a silicon-rich oxide SiOfilm layer deposited on the surface of the power MOS device, wherein a silicon dioxide film layer is deposited on the silicon-rich oxide SiOfilm layer. The method for forming an interlayer dielectric layer structure for a power MOS device comprises the following steps: depositing a silicon-rich oxide SiOfilm layer on the surface of the power MOS device; and depositing a silicon dioxide film layer on the silicon-rich oxide SiOfilm layer. 1. An interlayer dielectric layer structure for a power MOS device , including a silicon-rich oxide SiOfilm layer deposited on the surface of the power MOS device , wherein a silicon dioxide film layer is deposited on the silicon-rich oxide SiOfilm layer.2. The interlayer dielectric layer structure for a power MOS device according to claim 1 , wherein the refractive index of the silicon-rich oxide SiOfilm layer is 1.5 to 1.65.3. The interlayer dielectric layer structure for a power MOS device according to claim 1 , wherein the ratio of the number of silicon atoms to the number of oxygen atoms in the silicon-rich oxide is greater than 0 and less than ½.4. A method for forming an interlayer dielectric layer structure for a power MOS device claim 1 , including the following steps:{'sub': 'x', 'depositing a silicon-rich oxide SiOfilm layer on the surface of the power MOS device; and'}{'sub': 'x', 'depositing a silicon dioxide film layer on the silicon-rich oxide SiOfilm layer.'}5. The method for forming an interlayer dielectric layer structure for a power MOS device according to claim 4 , wherein the step of depositing a silicon-rich oxide SiOfilm layer on the surface of the power MOS device comprises:{'sub': x', '4', '2, 'claim-text': {'br': ...

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Номер записи: 40

12-01-2017 дата публикации

EMISSIVITY, SURFACE FINISH AND POROSITY CONTROL OF SEMICONDUCTOR REACTOR COMPONENTS

Номер: US20170011909A1

Автор: Shugrue John Kevin, White Carl Louis

Принадлежит:

An apparatus and methods are provided related to a surface of a reaction chamber assembly component. The surface may be roughened and/or anodized to provide desirable emissivity and porosity to help reduce burn-in time of a reaction chamber and to help reduce particles within the chamber. The apparatus and methods may be suitable for thin film deposition on semiconductor or other substrates. 1. An apparatus comprising:an aluminum alloy reaction chamber assembly component having at least one anodized surface layer.2. The apparatus of wherein the anodized surface layer has a thickness in a range of 3-15 μm.3. The apparatus of wherein the anodized surface layer has a surface roughness average of 0.4-6.3 μm.4. The apparatus of wherein the anodized surface layer has an emissivity of at least 0.50.5. The apparatus of wherein the anodized surface layer has an emissivity of at least 0.50.6. The apparatus of wherein the anodized surface layer has a surface roughness average of 0.4-6.3 μm.7. The apparatus of wherein the component is a showerhead.8. The apparatus of wherein the at least one anodized surface layer defines a downwardly facing surface of the showerhead.9. The apparatus of wherein the at least one anodized surface layer defines an upwardly facing surface of the showerhead.10. The apparatus of wherein the at least one anodized surface layer defines an upwardly facing surface of the showerhead.11. The apparatus of further comprising a substrate support assembly having a substrate support surface adapted to support thereon a substrate; wherein the showerhead has a surface which is essentially parallel to the substrate support surface; and the at least one anodized surface layer defines the surface of the showerhead.12. The apparatus of wherein the showerhead comprises a showerhead plate; and the at least one anodized surface layer defines a surface of the showerhead plate.13. The apparatus of further comprising a reaction chamber in which the showerhead plate is ...

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Номер записи: 41

12-01-2017 дата публикации

REACTIVE CURING PROCESS FOR SEMICONDUCTOR SUBSTRATES

Номер: US20170011910A1

Автор: Bankras Radko G., Jdira Lucian, Jongbloed Bert, Oosterlaken Theodorus G.M., Pierreux Dieter, Terhorst Herbert, van der Jeugd Cornelius A.

Принадлежит:

In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen peroxide, with the pressure in the process chamber at about 300 Torr or less. In some embodiments, the residence time of hydrogen peroxide molecules in the process chamber is about five minutes or less. The curing process temperature may be set at about 500° C. or less. The curing process may be applied to cure flowable dielectric materials and may provide highly uniform curing results, such as across a batch of semiconductor substrates cured in a batch process chamber. 131-. (canceled)32. A semiconductor processing system , comprising: [{'sub': 2', '2, 'expose the semiconductor substrates in the process chamber to an ambient containing HO; and'}, {'sub': 2', '2, 'maintain a process chamber pressure at about 300 Torr or below while exposing the substrates to the ambient containing HO.'}], 'a vertical furnace comprising a hot wall, batch process chamber configured to accommodate a plurality of semiconductor substrates in a wafer boat, wherein the semiconductor processing system is configured to33. The system of claim 32 , wherein the semiconductor processing system is configured to maintain the process chamber pressure at about 150 Torr or below while exposing the substrates to the ambient containing HO.34. The system of claim 32 , wherein the semiconductor processing system is configured to maintain a partial pressure of HOin the process chamber at about 1-100 Torr.35. The system of claim 32 , wherein the semiconductor processing system is configured to maintain a process chamber temperature at about 50° to about 500° C. during exposing the semiconductor substrate.36. The system of claim 32 , wherein the semiconductor processing system is configured to expose the semiconductor substrates in the process chamber to hydrogen while exposing the substrate to the ambient containing HO.37. The system of claim 32 , ...

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Номер записи: 42

12-01-2017 дата публикации

SILICON-ON-INSULATOR DEVICE AND INTERMETALLIC DIELECTRIC LAYER STRUCTURE THEREOF AND MANUFACTURING METHOD

Номер: US20170011957A1

Автор: Ma Jingjing, WANG Dejin, Wang Zhiyong

Принадлежит:

Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer () covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer () is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device. 1. An intermetallic dielectric layer structure of a silicon-on-insulator device , comprising: a Si-rich oxide layer covering a metal interconnection , a fluorine-silicon glass layer formed on the Si-rich oxide layer , and an undoped silicate glass layer formed on the fluorine-silicon glass layer; wherein a thickness of the Si-rich oxide layer is 700 angstroms ±10%.2. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , characterized in that claim 1 , the Si-rich oxide layer is an in-situ Si-rich oxide layer.3. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , characterized in that claim 1 , a thickness of the undoped silicate glass layer is 2000 angstroms ±10%.4. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , further comprising a silicon nitride layer provided between the metal interconnection and the fluorine-silicon glass layer.5. A silicon-on-insulator device claim 1 , comprising a substrate claim 1 , a buried oxide ...

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Номер записи: 43

12-01-2017 дата публикации

Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells

Номер: US20170012053A1

Автор: Simsek-Ege Fatma Arzum, Sun Jie

Принадлежит:

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells. 113-. (canceled)14. A method of forming vertically-stacked memory cells , comprising:forming a first insulative material over a stack of alternating dielectric levels and conductive levels;forming a first opening through the first insulative material and through the stack of alternating dielectric levels and conductive levels;forming cavities extending into the conductive levels along sidewalls of the first opening;forming a silicon nitride liner within the first opening and extending into the cavities;forming a second insulative material over the silicon nitride liner and over the first insulative material, the second insulative material covering the first opening and not extending downwardly into the first opening to an uppermost level of the stack, a remaining portion of the first opening being beneath the second insulative material;forming select gate material over the second insulative material;forming a second opening the through the select gate material and the second insulative material, and to the remaining portion of the first ...

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Номер записи: 44

12-01-2017 дата публикации

METHODS OF FORMING AN ISOLATION STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20170012098A1

Автор: Park Seok-Han

Принадлежит:

A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transformed into a second oxide layer and a third oxide layer, respectively, in the first trench, resulting in a semiconductor device with an isolation structure with good isolation characteristics. 1. A method of manufacturing an isolation structure , the method comprising:forming a hard mask on a first region and a second region of a substrate;etching the substrate using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width;forming a first oxide layer on the hard mask and on the first and second trenches, the first oxide layer being conformally formed on an inner wall of the first trench and filling the second trench;conformally forming a polysilicon layer on the ...

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Номер записи: 45

15-01-2015 дата публикации

METHOD FOR PRODUCING A MOS STACK ON A DIAMOND SUBSTRATE

Номер: US20150014707A1

Автор: Chicot Gauthier, Marechal Aurélien, Muret Pierre, Pernot Julien

Принадлежит: UNIVERSITE JOSEPH FOURIER

The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition. 1. A method of manufacturing a component comprising a conductive gate insulated from a single-crystal diamond semiconductor substrate by an insulating region , comprising the steps of:a) oxygenating the surface of the substrate to replace hydrogen surface terminations of the substrate with oxygen surface terminations; andb) forming the insulating region at the surface of the substrate by atomic layer deposition.2. The method of claim 1 , wherein at step a) claim 1 , the substrate is placed in an enclosure containing dioxygen at a pressure lower than the atmospheric pressure claim 1 , and is irradiated with ultraviolet light.3. The method of claim 1 , wherein the insulating region is made of aluminum oxide.4. The method of claim 3 , wherein claim 3 , at step b) claim 3 , the forming of each atom monolayer of aluminum oxide comprises a phase of placing into contact the component surface with an atmosphere comprising trimethyl-aluminum claim 3 , followed by a phase of placing into contact the component surface with an atmosphere comprising water vapor.5. The method of claim 1 , wherein the gate is made of metal.6. The method of claim 1 , wherein the gate is made of aluminum.7. The method of claim 1 , wherein the substrate comprises an upper epitaxial layer made of P-type doped single-crystal diamond.8. A component comprising a semiconductor substrate made of doped single-crystal diamond coated with a conductive gate insulated by an insulating region claim 1 , wherein a surface region of the substrate located ...

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Номер записи: 46

11-01-2018 дата публикации

SELECTIVE FILM DEPOSITION METHOD TO FORM AIR GAPS

Номер: US20180012792A1

Автор: Zhu Chiyu

Принадлежит:

A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device. 1. A method of forming an air gap for a semiconductor device through selective deposition comprising:providing a substrate for processing in a reaction chamber;providing a first surface overlying the substrate for selectively depositing a film, wherein the first surface comprises a first vertical portion;providing a second surface overlying the substrate, wherein the second surface comprises a second vertical portion; andselectively depositing the film at least on the first vertical portion of the first surface;wherein the second surface differs from the first surface and wherein deposition of the film is selective on first surface relative to deposition of the film on the second surface,wherein selectively depositing the film defines in part an air gap, and pulsing a metal halide precursor on the first vertical portion;', 'pulsing an oxygen precursor on the first vertical portion; and', 'repeating the pulsing steps until the film grows to a desired thickness., 'wherein the step of selectively depositing the film comprises2. The method of claim 1 , further comprising a third surface and a fourth surface overlying the substrate claim 1 , wherein the third surface comprises the same material as the first surface claim 1 , wherein the fourth surface comprises the same material as the second surface claim 1 , and wherein the deposition is selective on third surface relative to the deposition the fourth surface.3. The method of claim 2 , wherein both the third and the fourth surfaces comprises vertical portions and selectively depositing the film comprises deposition on the said first and third vertical surfaces.4. ...

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Номер записи: 47

11-01-2018 дата публикации

PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME

Номер: US20180012817A1

Автор: Chuang Cheng-Chi, Huang Kun-Ming, Hung Hsuan-Hui, Lin Ming-Yi

Принадлежит:

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer. 1. A method of making a passivation structure , the method comprising:forming a doped dielectric layer over a bottom dielectric layer, wherein forming the doped dielectric layer includes varying a dopant concentration of the doped dielectric layer as a distance from the bottom dielectric layer increases; andforming a top dielectric layer over the doped dielectric layer.2. The method of claim 1 , wherein the forming the doped dielectric layer includes sub-atmospheric pressure chemical vapor deposition (SACVD).3. The method of claim 2 , wherein the forming the doped dielectric layer includes using tetraethyl orthosilicate (TEOS).4. The method of claim 1 , wherein the forming the doped dielectric layer includes introducing the dopant concentration after formation of a dielectric layer.5. The method of claim 1 , wherein the forming the doped dielectric includes varying the dopant concentration in a single tool by changing a flow rate of dopant material.6. The method of claim 1 , wherein the forming the doped dielectric layer includes varying the dopant concentration of phosphorus.7. The method of claim 1 , further comprising:forming a molding compound layer over the top dielectric layer.8. A method of fabricating a semiconductor device claim 1 , the semiconductor device comprising: [ depositing a first doped layer having a first dopant concentration;', 'depositing a second doped layer having a second dopant concentration over the first doped layer; and', 'depositing a third doped layer having a third dopant concentration over the second doped layer, wherein the third dopant concentration is different from at least one of the first ...

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Номер записи: 48

15-01-2015 дата публикации

COMPOSITIONS AND METHODS FOR MAKING SILICON CONTAINING FILMS

Номер: US20150014823A1

Автор: "ONeill Mark Leonard", Han Bing, Jihnson Andrew David, Lei Xinjian, Mallikarjunan Anupama, VRTIS Raymond Nicholas, Wang Meiliang

Принадлежит:

Described herein are low temperature processed high quality silicon containing films. Also disclosed are methods of forming silicon containing films at low temperatures. In one aspect, there are provided silicon-containing film having a thickness of about 2 nm to about 200 nm and a density of about 2.2 g/cmor greater wherein the silicon-containing thin film is deposited by a deposition process selected from a group consisting of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), cyclic chemical vapor deposition (CCVD), plasma enhanced cyclic chemical vapor deposition (PECCVD, atomic layer deposition (ALD), and plasma enhanced atomic layer deposition (PEALD), and the vapor deposition is conducted at one or more temperatures ranging from about 25° C. to about 400° C. using an alkylsilane precursor selected from the group consisting of diethylsilane, triethylsilane, and combinations thereof. 1. A method for depositing a silicon-containing film on at least one surface of a device comprising a metal oxide , the method comprising:providing the at least one surface of the device in a reaction chamber;{'sup': 1', '2', '3', '1', '2', '3', '1', '2', '3', '2', '3, 'sub': 1-10', '4', '10', '3', '12', '3', '12', '6', '10', '1-10', '4', '10', '3', '12', '3', '12', '6', '10, 'introducing into the reaction chamber an alkylsilane precursor having a formula RRRSiH; wherein Ris chosen from the group consisting of a Clinear or branched alkyl group; a Cto Ccyclic alkyl group; a Cto Calkenyl group; a Cto Calkynyl group; and a Cto Caryl group; Rand Rare independently selected from hydrogen a Clinear or branched alkyl group; a Cto Ccyclic alkyl group; a Cto Calkenyl group; a Cto Calkynyl group; and a Cto Caryl group and wherein Rand any one of Rand Rcan be linked to form a ring when Rand Rare not hydrogen;'}introducing into the reaction chamber an oxygen source; and{'sup': '3', 'depositing by a deposition process the silicon containing film on the at least ...

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Номер записи: 49

10-01-2019 дата публикации

THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY

Номер: US20190013412A1

Автор: XIE Huafei

Принадлежит: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Provided is a thin film transistor, a manufacturing method thereof and a display. The method comprises steps of: forming a source pattern layer and a drain pattern layer above a substrate, wherein a channel area is formed between the source pattern layer and the drain pattern layer; forming an active layer in the channel area with a solution containing silicon quantum dots. With this method, the active layer of the thin film transistor is manufactured by spin coating with silicon quantum dots as material in the present invention. The manufacturing process is simple and the production cost is reduced to enrich the preparation materials of thin film transistor for promoting the mobility of the silicon-based thin film transistor, which is beneficial to improve the electrical uniformity of large area silicon-based thin film transistors. 1. A manufacturing method of a thin film transistor , comprising steps of:sequentially forming a bottom gate pattern layer and a bottom gate insulating layer covering the bottom gate pattern layer on a substrate;forming a source pattern layer and a drain pattern layer above the substrate, wherein a channel area is formed between the source pattern layer and the drain pattern layer;forming an active layer in the channel area with a solution containing silicon quantum dots;wherein the step of forming the active layer in the channel area with the solution containing silicon quantum dots comprises:forming a silicon quantum dots layer in the channel area with the solution containing silicon quantum dots by spin coating;evaporating the silicon quantum dots layer in vacuum at a low temperature to form a silicon quantum dots active layer.2. The method according to claim 1 , wherein the method further comprise:forming a top gate insulating layer covering the source pattern layer, the drain pattern layer and the active layer;forming a top gate pattern layer on the top gate insulating layer.3. The method according to claim 2 , wherein the method ...

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Номер записи: 50

14-01-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20210013094A1

Автор: HUANG SING-KAI, Liu Jack, WU Wei-Cheng, Young Charles Chew-Yuen

Принадлежит:

A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode. 1. A method of manufacturing a semiconductor device , the method comprising:providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is leveled with the first surface;forming an alignment layer over the first surface of the wafer and the top surface of the gate electrode;forming a photoresist on the alignment layer to cover a portion of the top surface of the gate electrode;removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface of the gate electrode:forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure;removing a portion of the dielectric to expose the alignment structure by chemical mechanical polishing:removing the alignment structure to expose at least a portion of the gate electrode; and forming a gate conductor over and in contact with the gate electrode.2. The method of claim 1 , wherein the gate conductor is embedded in the dielectric.3. The method of ...

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Номер записи: 51

09-01-2020 дата публикации

SELECTIVE GROWTH OF SIO2 ON DIELECTRIC SURFACES IN THE PRESENCE OF COPPER

Номер: US20200013615A1

Автор: FOX Alexander R., Hausmann Dennis M., LAWLOR Colleen

Принадлежит:

Methods and apparatuses for selectively depositing silicon oxide on surfaces relative to a metal-containing surface such as copper are provided. Methods involve exposing a substrate having hydroxyl-terminated or dielectric surfaces and copper surfaces to a copper-blocking reagent such as an alkyl thiol to selectively adsorb to the copper surface, exposing the substrate to a silicon-containing precursor for depositing silicon oxide, exposing the substrate to a weak oxidant gas and igniting a plasma, or water vapor without plasma, to convert the adsorb silicon-containing precursor to form silicon oxide. Some methods also involve exposing the substrate to a reducing agent to reduce any oxidized copper from exposure to the weak oxidant gas. 1. A method of selectively depositing silicon oxide on a hydroxyl-terminated surface relative to copper on a substrate , the method comprising:providing the substrate comprising the hydroxyl-terminated surface and exposed copper metal surface;prior to depositing the silicon oxide, exposing the substrate to a copper-blocking reagent to selectively adsorb onto the exposed copper metal surface;exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the hydroxyl-terminated surface;exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursors to silicon oxide; andexposing the substrate to a reducing agent to reduce the exposed copper metal surface.2. The method of claim 1 , wherein the copper-blocking reagent comprises sulfur.3. The method of claim 1 , wherein the copper-blocking reagent is an alkyl thiol.4. The method of claim 3 , wherein the copper-blocking reagent is selected from the group consisting of ethane thiol and butane thiol.5. The method of claim 1 , wherein the copper-blocking reagent is an alkyl thiol having a chemical formula SH(CH)CHwhereby n is an integer between and including 2 and ...

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Номер записи: 52

15-01-2015 дата публикации

METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS

Номер: US20150017794A1

Автор: Fukazawa Atsuki, Fukuda Hideaki, Haukka Suvi, Nakano Ryu, Namba Kunitoshi, NISKANEN Antti, Takamure Noboru

Принадлежит: ASM International. N.V.

The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. 1. (canceled)2. A method for depositing doped silicon oxide on a substrate by an atomic layer deposition (ALD) process , the ALD process comprising at least one doped silicon oxide deposition cycle , wherein a doped silicon oxide deposition cycle comprises:contacting the substrate with a silicon precursor;contacting the substrate with a dopant precursor; andcontacting the substrate with a reactive species such that a doped silicon oxide is formed.3. The method of claim 2 , wherein the substrate is contacted simultaneously with the silicon precursor and the dopant precursor.4. The method of claim 2 , wherein the ALD process is a plasma enhanced atomic layer deposition (PEALD) process.5. The method of claim 4 , wherein the reactive species comprises oxygen.6. The method of claim 2 , wherein the reactive species comprises a non-excited species of oxygen.7. The method of claim 2 , wherein the reactive species comprises excited species of nitrogen.8. The method of claim 2 , wherein the substrate is contacted with oxygen after being contacted with the silicon precursor and the dopant precursor.9. The method of claim 2 , wherein the doped silicon oxide deposition cycle comprises claim 2 , in order:contacting the substrate with the silicon precursor;contacting the substrate with the dopant precursor; andcontacting the substrate with a plasma generated from oxygen such that that a doped silicon oxide is formed.10. The method of claim 2 , wherein the doped silicon oxide deposition cycle comprises claim 2 , in order:contacting ...

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Номер записи: 53

15-01-2015 дата публикации

Non-Volatile Memory With Silicided Bit Line Contacts

Номер: US20150017795A1

Автор: CHAN Simon Siu-Sing, LU Ching-Huang, SHIRAIWA Hidehiko, Xue Lei

Принадлежит:

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. 1. A method comprising:disposing a first dielectric layer on a substrate;disposing a dielectric charge trapping layer on the first dielectric layer;disposing a second dielectric layer on the dielectric trapping layer;patterning a hard mask on the second dielectric layer;disposing an oxide spacer on sidewalls of the hard mask to leave exposed a bit line contact region;removing portions of the second dielectric layer, dielectric trapping layer and first dielectric layer within the bit line contact region;removing portions of the oxide spacer to leave exposed a portion of the second dielectric layer; andremoving the exposed portion of the second dielectric layer to thereby yield extended portions of the dielectric trapping layer and first dielectric layer.2. The method of claim 1 , wherein the first dielectric layer comprises silicon dioxide.3. The method of claim 1 , wherein the dielectric charge trapping layer comprises silicon-rich nitride (SiRN).4. The method of claim 1 , wherein the second dielectric layer comprises silicon oxide.5. The method of claim 1 , further comprising:forming a metalized portion within the bit line contact region.6. The method of claim 5 , wherein the metallized portion comprises a silicide.7. The method of claim 6 , wherein the silicide comprises at least one of titanium silicide claim 6 , cobalt silicide and nickel silicide.8. The method of claim 5 , wherein forming the metalized portion within the bit line contact region ...

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Номер записи: 54

15-01-2015 дата публикации

METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE

Номер: US20150017808A1

Автор: Koh Cha-won

Принадлежит:

A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space. 1. A method of forming a micro pattern of a semiconductor device , the method comprising:forming an acid-extinguisher containing film on a substrate;forming a photoresist film on the acid-extinguisher containing film, the photoresist film containing a potential acid;forming an exposed area by exposing a portion of the photoresist film to light, the exposed area containing acids;forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area;developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film;exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film; andremoving the acid-extinguisher containing film exposed through the space.2. The method of claim 1 , further comprising:washing a ...

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Номер записи: 55

15-01-2015 дата публикации

SEQUENTIAL PRECURSOR DOSING IN AN ALD MULTI-STATION/BATCH REACTOR

Номер: US20150017812A1

Автор: Chandrasekharan Ramesh, LaVoie Adrien, Leeser Karl, Slevin Damien

Принадлежит:

Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations. 2. The method of claim 1 , wherein the first dosing phase transitions to the second dosing phase by redirecting the continuous flow of precursor from the first processing station to the second processing station.3. The method of claim 2 , wherein the redirecting is done through operation of one or more valves which control precursor flow.4. The method of claim 1 , wherein the deposited material is a dielectric and the plasma is an oxidative plasma.5. The method of claim 4 , wherein the deposited material contains silicon and the film precursor is a silicon-containing film precursor.6. The method of claim 1 , wherein the removing is performed by purging the one or more reaction chambers with an inert purge gas.7. The method of claim 1 , wherein the removing is performed by applying vacuum to the one or more reaction chambers.8. The method of claim 1 , wherein the plasma is generated within the one or more reaction chambers with application of RF power.9. The method of claim 1 , wherein the plasma is generated ...

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Номер записи: 56

21-01-2016 дата публикации

LOW-K DIELECTRIC GAPFILL BY FLOWABLE DEPOSITION

Номер: US20160020089A1

Автор: Lee Young S., Liang Jingmei, SRINIVASAN Mukund, Thadani Kiran V.

Принадлежит:

Methods are described for forming a flowable low-k dielectric layer on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. A similarly deposited silicon oxide layer may be deposited first to improve the gapfill capabilities. Alternatively, or in combination, the flow of a silicon-and-carbon-containing precursor may be reduced during deposition to change the properties from low-k to high strength roughly following the filling of features of the patterned substrate.

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Номер записи: 57

19-01-2017 дата публикации

METHOD FOR PROTECTING LAYER BY FORMING HYDROCARBON-BASED EXTEMELY THIN FILM

Номер: US20170018420A1

Автор: Kato Richika, Nakano Ryu

Принадлежит:

A method for protecting a layer includes: providing a substrate having a target layer; depositing a protective layer on the target layer, which protective layer contacts and covers the target layer and is constituted by a hydrocarbon-based layer; and depositing an oxide layer on the protective layer so that the protective layer in contact with the oxide layer is oxidized. The hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant. 1. A method for protecting a layer , comprising:providing a substrate having a target layer;depositing a protective layer on the target layer, said protective layer contacting and covering the target layer and constituted by a hydrocarbon-based layer, which hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant; anddepositing an oxide layer on the protective layer so that the protective layer in contact with the oxide layer is oxidized.2. The method according to claim 1 , wherein the hydrocarbon-based layer is constituted by a hydrocarbon polymer containing silicon and nitrogen.3. The method according to claim 1 , wherein the target layer is a silicon substrate.4. The method according to claim 1 , wherein the oxide layer is constituted by silicon oxide.5. The method according to claim 1 , wherein the oxide layer is constituted by metal oxide.6. The method according to claim 1 , wherein the alkylaminosilane is selected from the group consisting of bisdiethylaminosilane (BDEAS) claim 1 , biszimethylaminosilane (BDMAS) claim 1 , hexylethylaminosilane (HEAD) claim 1 , tetraethylaminosilane (TEAS) claim 1 , tert-butylaminosilane (TBAS) claim 1 , bistert-butylaminosilena (BTBAS) claim 1 , bisdimethylaminodimethylaminosilane (BDMADMS) claim 1 , heptametyhlsilazane (HMDS) claim 1 , trimethysylyldiethlamine (TMSDEA) claim 1 , ...

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Номер записи: 58

21-01-2016 дата публикации

Gap-filling dielectric layer method for manufacturing the same and applications thereof

Номер: US20160020139A1

Автор: Chieh-Wen Lo, Chih-Chien Liu, Wen-Yi Teng, Yuh-Min Lin

Принадлежит: United Microelectronics Corp

A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×10 22 atoms/cm 3 is formed.

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Номер записи: 59

21-01-2016 дата публикации

Edge Termination Using Guard Rings Between Recessed Field Oxide Regions

Номер: US20160020279A1

Автор: Limburn Nicholas, Ngwendson Luther-King, Turner Russell, Vytla Rajeev Krishna

Принадлежит:

An edge termination structure is disclosed. The edge termination structure includes an active cell in a semiconductor wafer, an edge termination region adjacent the active cell in the semiconductor wafer, where the edge termination region includes recessed field oxide regions and guard rings adjacent to the active cell. At least one of the guard rings has a depth greater than a depth of at least one of the recessed field oxide regions. A top surface of each of the recessed field oxide regions is substantially coplanar with a top surface of the semiconductor wafer and with a top surface of each of the guard rings. The recessed field oxide regions may be thermally grown in recesses in the semiconductor wafer. The recessed field oxide regions may include silicon dioxide.

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Номер записи: 60

19-01-2017 дата публикации

SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Номер: US20170018552A1

Автор: Jung Dongjin, KIM Ilgweon, Lee JooYoung, Moon Daehyun, SEO Hyeoungwon

Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of recess regions on an upper surface of a substrate, forming a first oxide layer in the recess regions, forming a polysilicon layer on the first oxide layer, forming a second oxide layer by oxidizing the polysilicon layer, and forming a gap-fill layer on the second oxide layer to fill the recess regions, wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a plurality of recess regions on an upper surface of a substrate;forming a first oxide layer in the recess regions;forming a polysilicon layer on the first oxide layer;forming a second oxide layer by oxidizing the polysilicon layer; andforming a gap-fill layer on the second oxide layer to fill the recess regions,wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer.2. The method of claim 1 , wherein the first oxide layer is formed by using an atomic layer deposition process.3. The method of claim 2 , wherein the first oxide layer has a first thickness and the second oxide layer has a second thickness greater than the first thickness.4. The method of claim 1 , wherein the substrate comprises a cell array region and a peripheral circuit region claim 1 ,the recess regions include a first recess region in the cell array region and a second recess region in the peripheral circuit region, andthe first recess region includes a plurality of active regions extending in a first direction and includes recesses between the active regions, wherein a maximum distance between active regions in either the first direction or a second direction perpendicular to the first direction is a first width; andthe second recess region includes a plurality of active regions and at ...

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Номер записи: 61

19-01-2017 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170018558A1

Автор: SHAMOTO Reiko, TAKEKIDA Hideto

Принадлежит: KABUSHIKI KAISHA TOSHIBA

A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side. 1. A nonvolatile semiconductor memory device , comprising:a substrate;a memory cell disposed on the substrate, the memory cell accumulating a charge as data; anda cover layer covering the memory cell,the cover layer having a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a side of the memory cell.2. The nonvolatile semiconductor memory device according to claim 1 , whereinthe intermediate layer is silicon oxide.3. The nonvolatile semiconductor memory device according to claim 1 , whereinthe intermediate layer is amorphous silicon.4. The nonvolatile semiconductor memory device according to claim 1 , whereinthe second silicon nitride layer is thicker than the first silicon nitride layer.5. The nonvolatile semiconductor memory device according to claim 3 , further comprising:a peripheral transistor disposed in a periphery of the memory cell; and a contact disposed in a periphery of said peripheral transistor, whereinthe cover layer covers an upper portion of the peripheral transistor and has an end of the cover layer contacting the contact,a spacer configured from an insulator is disposed on the upper portion of the peripheral transistor, andthe cover layer is divided by the spacer.6. The nonvolatile semiconductor memory device according to claim 1 , whereinthe cover layer further comprises: a second intermediate layer disposed on an upper surface of the second silicon nitride layer; and a third silicon nitride layer disposed on an upper surface of said second intermediate layer.7. The nonvolatile semiconductor ...

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Номер записи: 62

03-02-2022 дата публикации

SILICON NITRIDE FILMS HAVING REDUCED INTERFACIAL STRAIN

Номер: US20220037145A1

Автор: LIANG Yong, Melnichuk Ann

Принадлежит: Psiquantum, Corp.

In some embodiments a method comprises depositing a first silicon nitride layer on a top surface of a semiconductor wafer and forming one or more first gaps in the first silicon nitride layer. The one or more first gaps can relieve stress formed in the first silicon nitride layer. A first fill material is deposited on the first silicon nitride layer and the first silicon nitride layer is planarized. A second silicon nitride layer is deposited across the first silicon nitride layer and one or more second gaps are formed in the second silicon nitride layer. The one or more second gaps can relieve stress formed in the second silicon nitride layer. A second fill material is deposited across the second silicon nitride layer and the second silicon nitride layer is planarized. 1. A method comprising:providing a silicon wafer;depositing a first portion of a silicon nitride layer on the silicon wafer;selectively removing first regions of the first portion of the silicon nitride layer along one or more dicing lanes to define one or more first gaps between areas of the first portion of the silicon nitride layer;depositing a first fill material on the first portion of the silicon nitride layer and into the one or more first gaps;planarizing a top surface of the first portion of the silicon nitride layer such that the first fill material within the one or more first gaps is coplanar with the top surface of the first portion of the silicon nitride layer;depositing a second portion of the silicon nitride layer such that it extends across the first portion of the silicon nitride layer and across the first fill material disposed within the one or more first gaps;selectively removing second regions of the second portion of the silicon nitride layer along the one or more of the dicing lanes to define one or more second gaps between areas of the second portion of the silicon nitride layer;depositing a second fill material on the second portion of the silicon nitride layer and into the ...

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Номер записи: 63

03-02-2022 дата публикации

MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

Номер: US20220037377A1

Автор: CHO EN-TSUNG, XIA Yuming, Ye Lidan

Принадлежит:

Disclosed are a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method of the array substrate includes: providing a substrate; depositing and patterning a gate layer on the substrate; depositing a protective layer on the substrate covered with the gate layer by atomic layer deposition; and depositing and patterning an amorphous silicon layer and an ohmic contact layer on the protective layer. The uniform protective layer of the present disclosure reduces the influence on the field effect mobility of the thin film transistor, makes the display of the product more stable, and improves the display effect. 1. A manufacturing method of an array substrate , comprising:providing a substrate;depositing and patterning a gate layer on the substrate;depositing a protective layer on the substrate covered with the gate layer by atomic layer deposition; anddepositing and patterning an amorphous silicon layer and an ohmic contact layer on the protective layer.2. The manufacturing method of the array substrate of claim 1 , wherein depositing a protective layer on the substrate covered with the gate layer by atomic layer deposition comprises:placing the substrate covered with the gate layer into a reaction chamber for atomic layer deposition, heating the reaction chamber to adjust a temperature to a preset temperature, and evacuating the reaction chamber to adjust a pressure to a preset pressure;controlling a silicon precursor source to be sent into and to stay in the reaction chamber for a first preset time period;controlling an inert gas to purge the reaction chamber for a second preset time period;controlling a nitrogen precursor source to be sent into and to stay in the reaction chamber for a third preset time period;controlling the inert gas to purge the reaction chamber for a fourth preset time period; andcyclically repeating the operations of controlling a silicon precursor source to be sent into and to stay in the ...

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Номер записи: 64

18-01-2018 дата публикации

SELF-LIMITING AND SATURATING CHEMICAL VAPOR DEPOSITION OF A SILICON BILAYER AND ALD

Номер: US20180019116A1

Автор: Chang Mei, EDMONDS Mary, KACHIAN Jessica S., KIM Hyunwoong, Kummel Andrew C., Park Sang Wook, Yoshida Naomi

Принадлежит:

Embodiments described herein provide a self-limiting and saturating Si—Obilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO, but instead produce a saturated Si—Ofilm with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials. 1. A substrate processing method , comprising:heating a substrate in a reaction chamber to a temperature of less than 500° C.;exposing the substrate to a chlorosilane precursor utilizing a chemical vapor deposition process; andexposing the substrate to an anhydrous HOOH precursor utilizing the chemical vapor deposition process, wherein a chlorine terminated saturated silicon bilayer is deposited on the substrate.2. The method of claim 1 , wherein the substrate comprises one or more of indium gallium arsenide claim 1 , indium gallium antimonide claim 1 , indium gallium nitride claim 1 , silicon germanium claim 1 , and metallic materials.3. The method of claim 2 , wherein the reaction chamber is heated to a temperature of between 300° C. and 500° C.4. The method of claim 1 , wherein the chlorosilane precursor is selected from the group consisting of SiCl claim 1 , SiCl claim 1 , and SiCl.5. The method of claim 1 , further comprising:{'sub': 2', '6, 'exposing the substrate to an SiClprecursor utilizing an atomic layer deposition process; and'}{'sub': 2', '6, 'exposing the substrate to an anhydrous HOOH precursor utilizing the atomic layer deposition process, where in the atomic layer deposition process cyclically exposes the substrate to the SiClprecursor and the anhydrous HOOH precursor in an alternating manner.'}6. The method of claim 1 , further comprising:cleaning the substrate by a de-capping process or atomic H exposure prior to exposing the substrate to either of the chlorosilane precursor or the anhydrous HOOH precursor.7. ...

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Номер записи: 65

17-01-2019 дата публикации

CONTROLLED ETCH OF NITRIDE FEATURES

Номер: US20190019688A1

Автор: Bergman Eric J., Hanson Kyle Moran, Klocke John L., McHugh Paul, Sharbono Charles

Принадлежит: Applied Materials, Inc.

Methods of etching a semiconductor substrate may include applying an etchant to the semiconductor substrate. The semiconductor substrate may include an exposed region of an oxygen-containing material and an exposed region of a nitrogen-containing material. The methods may include heating the semiconductor substrate from a first temperature to a second temperature. The methods may include maintaining the semiconductor substrate at the second temperature for a period of time sufficient to perform an etch of the nitrogen-containing material relative to the oxygen-containing material. The methods may also include quenching the etch subsequent the period of time. 1. A method of etching a semiconductor substrate , the method comprising:applying an etchant to the semiconductor substrate, wherein the semiconductor substrate includes an exposed region of an oxygen-containing material and an exposed region of a nitrogen-containing material;heating the semiconductor substrate from a first temperature to a second temperature;maintaining the semiconductor substrate at the second temperature for a period of time sufficient to perform an etch of the nitrogen-containing material relative to the oxygen-containing material; andquenching the etch subsequent the period of time.2. The method of etching a semiconductor substrate of claim 1 , wherein the first temperature is below about 100° C.3. The method of etching a semiconductor substrate of claim 1 , wherein the second temperature is above about 100° C.4. The method of etching a semiconductor substrate of claim 1 , wherein the etchant comprises phosphoric acid at a concentration of at least about 60% by volume.5. The method of etching a semiconductor substrate of claim 4 , wherein the etchant further comprises tetraethyl orthosilicate.6. The method of etching a semiconductor substrate of claim 1 , wherein the period of time is less than or about 60 seconds.7. The method of etching a semiconductor substrate of claim 1 , wherein the ...

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Номер записи: 66

17-01-2019 дата публикации

Method of manufacture of a semiconductor on insulator structure

Номер: US20190019721A1

Автор: Henry Frank Erk, Jeffrey L. Libbert, Mayank Bulsara, Sasha Kweskin

Принадлежит: SunEdison Semiconductor Ltd

A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.

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Номер записи: 67

17-01-2019 дата публикации

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME

Номер: US20190019795A1

Автор: Chang Wei-Che, Chen Huang-Nan, Takesako Kazuaki

Принадлежит: WINBOND ELECTRONICS CORP.

A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas. 1. A dynamic random access memory (DRAM) , comprising:a plurality of isolation structures, located in a substrate to divide the substrate into a plurality of active areas, wherein the active areas are configured in a shape of band and arranged in an array;a plurality of word line sets, disposed in parallel in a Y direction in the substrate;a plurality of bit-line structures, disposed in parallel in an X direction on the substrate and crossing the word line sets;a plurality of spacers, disposed in parallel in the X direction on sidewalls of the bit-line structures and comprising silicon oxide;a plurality of capacitors, respectively disposed at two terminals of a long side of each of the active areas; anda plurality of capacitor contacts, respectively located between the capacitors and the active areas.2. The DRAM according to claim 1 , wherein each of the spacers comprises a first spacer and a second spacer claim 1 , and the first spacer is located between the bit-line structure and the second spacer.3. The DRAM according to claim 2 , wherein the first spacers comprise silicon nitride claim 2 , and the second spacers ...

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Номер записи: 68

16-01-2020 дата публикации

INTERCONNECTS WITH NON-MANDREL CUTS FORMED BY EARLY BLOCK PATTERNING

Номер: US20200020531A1

Автор: Huang Haigou, Ning Guoxiang, Ren Yuping, Singh Sunil K.

Принадлежит:

Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer. 1. A method comprising:depositing a hardmask over a dielectric layer;forming a block mask that is arranged over a portion of the hardmask; andafter forming the block mask, forming a first mandrel and a second mandrel on the hardmask,wherein the first mandrel is adjacent to the second mandrel, the first mandrel is laterally spaced from the second mandrel, the portion of the hardmask is arranged between the first mandrel and the second mandrel, and the first mandrel and the second mandrel each have a non-overlapping arrangement with the block mask.2. The method of further comprising:forming a first sidewall spacer and a second sidewall spacer respectively arranged on the hardmask adjacent to the first mandrel and adjacent to the second mandrel.3. The method of wherein the block mask is comprised of titanium dioxide or silicon dioxide claim 2 , and the first sidewall spacer and the second sidewall spacer are comprised of titanium dioxide or silicon dioxide.4. The method of wherein the block mask claim 2 , the first sidewall spacer claim 2 , and the second sidewall spacer are comprised of titanium dioxide.5. The method of wherein the block mask claim 2 , the first sidewall spacer claim 2 , and the second sidewall spacer are comprised of silicon dioxide.6. The method of wherein the block mask is comprised of a first material claim 2 , the first sidewall spacer and the second sidewall spacer are comprised of a second ...

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Номер записи: 69

21-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210020501A1

Автор: KUME lppei, ONO Takanobu

Принадлежит: Kioxia Corporation

A semiconductor device according to an embodiment comprises a semiconductor substrate and a semiconductor element provided on the semiconductor substrate. A first insulation film is configured to cover the semiconductor element. A first sidewall film is provided on a side part of the first insulation film, of which an absorption coefficient for ultraviolet light is larger than that of the first insulation film. 1. A semiconductor device comprising:a semiconductor substrate;a semiconductor element provided on the semiconductor substrate;a first insulation film configured to cover the semiconductor element; anda first sidewall film provided on a side part of the first insulation film, of which an absorption coefficient for ultraviolet light is larger than that of the first insulation film.2. The device of claim 1 , wherein the first sidewall film includes a silicon nitride film.3. The device of claim 1 , wherein the first sidewall film includes a metal film.4. The device of claim 3 , wherein the first sidewall film contains at least one of tungsten claim 3 , titanium claim 3 , and aluminum.5. The device of claim 1 , further comprising a second sidewall film configured to cover an outer side of the first sidewall film.6. The device of claim 5 , wherein the first insulation film includes a first interlayer dielectric film and a second interlayer dielectric film provided above the first interlayer dielectric film claim 5 , andthe first sidewall film or the second sidewall film is in direct contact with an interface between the first interlayer dielectric film and the second interlayer dielectric film.7. The device of claim 6 , wherein the semiconductor element includes a first semiconductor circuit that is provided on the semiconductor substrate and is covered by the first interlayer dielectric film claim 6 , and a second semiconductor circuit that is provided above the first semiconductor circuit and is covered by the second interlayer dielectric film.8. The device of ...

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Номер записи: 70

17-04-2014 дата публикации

METHOD AND APPARATUS OF FORMING SILICON NITRIDE FILM

Номер: US20140106577A1

Автор: TABUKI Keiji, TONEGAWA Yamato

Принадлежит: TOKYO ELECTRON LIMITED

Provided is a method of forming a silicon nitride film on an object to be processed, which includes: supplying a silicon raw material gas into a processing chamber; and supplying a nitridant gas into the processing chamber, wherein supplying the silicon raw material gas includes an initial supply stage in which the silicon raw material gas is initially supplied and a late supply stage following the initial supply stage, wherein a first internal pressure of the processing chamber defined in the initial supply stage is lower than a second internal pressure of the processing chamber defined in the late supply stage. 1. A method of forming a silicon nitride film on an object to be processed , the method comprising:supplying a silicon raw material gas into a processing chamber; andsupplying a nitridant gas into the processing chamber,wherein supplying the silicon raw material gas includes an initial supply stage in which the silicon raw material gas is initially supplied and a late supply stage following the initial supply stage,wherein a first internal pressure of the processing chamber defined in the initial supply stage is lower than a second internal pressure of the processing chamber defined in the late supply stage.2. The method of claim 1 , wherein the silicon nitride film formed on the object to be processed has a refractive index of more than 2.0.3. The method of claim 1 , wherein the silicon nitride film is formed on the object to be processed by repeatedly supplying the silicon raw material gas and the nitridant gas.4. The method of claim 1 , wherein an in-plane uniformity of thickness of the silicon nitride film formed on the object to be processed is controlled by controlling the first internal pressure in the initial supply stage.5. The method of claim 1 , wherein a refractive index of the silicon nitride film formed on the object to be processed is controlled by controlling a time interval in the late supply stage.6. The method of claim 1 , wherein the ...

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Номер записи: 71

22-01-2015 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20150024564A1

Автор: Katsuki Shogo, SAKAMOTO Toshiro

Принадлежит:

A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate. 1. A method for manufacturing a semiconductor device , the semiconductor device including a first MOS transistor in a first region of a semiconductor substrate and a second MOS transistor in a second region of the semiconductor substrate , the method comprising:forming a first gate oxide film in each of the first region and the second region by thermally oxidizing the semiconductor substrate;forming a protective film on the first gate oxide film;implanting fluorine into each of the first region and the second region through the protective film and the first gate oxide film;removing, after the implantation of the fluoride, the protective film from the first gate oxide film in the second region;removing the first gate oxide film from the second region; andforming a second gate oxide film in the second region by thermally oxidizing the semiconductor substrate in a state where the first gate oxide film is left in the first region and the first gate oxide film is removed from the second region, the second gate oxide film being different in thickness or type from the first gate oxide film.2. The method for manufacturing the semiconductor device according to claim 1 , further comprising claim 1 ,removing the protective film from the first gate oxide film in the first region, between the removing the first gate oxide film from the second region and the forming the second ...

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Номер записи: 72

23-01-2020 дата публикации

ENCAPSULATED FLEXIBLE ELECTRONICS FOR LONG-TERM IMPLANTATION

Номер: US20200022601A1

Автор: Fang Hui, LEE Yoon Kyeung, ROGERS John A., SONG Enming, ZHAO Jianing

Принадлежит:

Provided are methods of making a long-term implantable electronic device, and related implantable devices, including by providing a substrate having a first encapsulation layer that covers at least a portion of the substrate, the first encapsulation layer having a receiving surface; providing one or more electronic devices on the first encapsulation layer receiving surface; and removing at least a portion of the substrate from the first encapsulation layer; thereby making the long-term implantable electronic device. Further desirable properties, including device lifetime increases during use in environments that are challenging for sensitive electronic device components, are achieved through the use of additional layers such as longevity-extending layers and/or ion-barrier layers in combination with an encapsulation layer. 1. A method of making a long-term implantable electronic device , the method comprising the steps of:providing a substrate having a first encapsulation layer that covers at least a portion of the substrate, the first encapsulation layer having a receiving surface;providing one or more electronic devices on the first encapsulation layer receiving surface;removing at least a portion of the substrate from the first encapsulation layer;thereby making the long-term implantable electronic device.2. The method of claim 1 , wherein the first encapsulation layer is deposited on the substrate claim 1 , grown on the substrate claim 1 , formed on the substrate or transfer printed on the substrate.3. The method of claim 1 , wherein the first encapsulation layer is made by thermally oxidizing a portion of the substrate.4. The method of further comprising the steps of:depositing a barrier layer over an exposed surface of said one or more electronic devices;adhering to the barrier layer a top substrate having a second encapsulation layer, wherein the second encapsulation layer faces the barrier layer; andremoving at least a portion of the top substrate from the ...

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Номер записи: 73

24-01-2019 дата публикации

Method of Producing a Thin Metal-Organic Framework Film Using Vapor Phase Precursors

Номер: US20190024235A1

Автор: Ameloot Rob, De Vos Dirk, Stassen Ivo, VEREECKEN Philippe M.

Принадлежит:

A method of producing a metal-organic framework (MOF) film on a substrate is disclosed, the method comprising providing a substrate having a main surface and forming on said main surface a MOF film using an organometallic compound pre-cursor and at least one organic ligand, wherein each of said organometallic compound precursor and said at least one organic ligand is provided only in vapour phase. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. (canceled)13. (canceled)14. A substrate structure comprising:a substrate having a main surface; anda metal organic framework (MOF) film on said main surface, wherein said MOF film has a thickness range of 1 nm to 250 nm and is pin-hole free.15. The substrate structure according to claim 14 , wherein said main surface is covered with a conformal layer of a dielectric material.16. The substrate structure according to claim 14 , wherein said substrate structure further comprises a stack consisting of layers of MOF films and layers of materials having a refractive index higher than 1.4 claim 14 , wherein each layer of said MOF film is disposed alternating with each layer of said high refractive index materials.17. (canceled)18. The substrate structure according to claim 14 , wherein said substrate is a Si substrate.19. The substrate structure according to claim 14 , wherein said substrate is a bulk Si substrate.20. The substrate structure according to claim 15 , wherein the conformal layer of the dielectric material is deposited by Atomic Lay Deposition (ALD).21. The substrate structure according to claim 15 , wherein the conformal layer of dielectric material comprises an oxide layer.22. The substrate structure according to claim 21 , wherein the oxide layer is an electrical conductor.23. The substrate structure according to claim 21 , wherein the oxide layer is an electrical insulator.24. The substrate structure according to ...

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Номер записи: 74

28-01-2016 дата публикации

HYDROXYL GROUP TERMINATION FOR NUCLEATION OF A DIELECTRIC METALLIC OXIDE

Номер: US20160027640A1

Автор: Ando Takashi, Chudzik Michael P., DAI Min, Frank Martin M., Hilscher David F., JR. Joseph F., Krishnan Rishikesh, Linder Barry P., Ortolland Claude, Shepard

Принадлежит:

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations. 1. A method of forming a semiconductor device comprising:providing a first device region having a first semiconductor material portion of a first semiconductor material;providing a second device region having a second semiconductor material portion of a second semiconductor material that is different from said first semiconductor material;forming a first semiconductor-containing dielectric material layer on said first semiconductor material portion and a second semiconductor-containing dielectric material layer on said second semiconductor material portion; andforming a metal oxide layer on said first semiconductor-containing dielectric material layer and said second semiconductor-containing dielectric material layer, wherein a portion of said metal oxide layer and a portion of each of said first semiconductor-containing dielectric material layer and said second semiconductor-containing dielectric material layer form a gate oxide material in each of said first and second device regions, wherein a difference in thickness of said gate oxide materials over said first device region and said second device region is less than 3 angstroms.2. The method of claim 1 , wherein said ...

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Номер записи: 75

26-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170025532A1

Автор: Fujii Hiroki, Mori Takahiro

Принадлежит: RENESAS ELECTRONICS CORPORATION

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. 1. A semiconductor device comprising:a semiconductor substrate having a primary surface;a first-conductive-type first semiconductor layer that is formed over the primary surface of the semiconductor substrate;a second-conductive-type drain region that is formed in the first semiconductor layer;a second-conductive-type source region that is formed in the first semiconductor layer at a distance away from the drain region;an isolation insulating film having a first thickness that is formed at a part of the first semiconductor layer located between the drain region and the source region;a second-conductive-type drift layer that is formed from the surface of the first semiconductor layer up to a position deeper than the bottom of the isolation insulating film so as to surround the isolation insulating film and the drain region from the lateral and lower sides;a gate electrode that is formed over a region located between the isolation insulating film and the source region and including a part serving as a channel; anda buried electrode that is formed at a part of the isolation insulating film located between the drain region and the gate electrode at a distance away from the drain region and the gate electrode,wherein the buried electrode includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.2. The semiconductor device according to claim 1 ,wherein the buried electrode and the drain region are electrically coupled to each other, andwherein a voltage same as that applied to the drain region is applied to the buried electrode.3. The semiconductor device according to claim 1 ,wherein the buried electrode is arranged in the isolation insulating film on the side where the ...

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Номер записи: 76

28-01-2016 дата публикации

VERTICAL STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR DEVICE

Номер: US20160027917A1

Автор: Chang Hui-Cheng, Chen Bing-Hung, CHEN DE-FANG, Huang Huang-Yi, LIN CHENG-TUNG, Lin Huan-Just, TSAI Ming-Hsing, TSAI Teng-Chun, Wang Li-Ting

Принадлежит:

According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment. 1. A method of forming a semiconductor device , comprising:providing a vertical structure over a substrate;forming an etch stop layer over the vertical structure;forming an oxide layer over the etch stop layer; andoxidizing the oxide layer by using an oxygen plasma treatment.2. The method of claim 1 , wherein oxidizing the oxide layer by using the oxygen plasma treatment further comprises oxidizing the oxide layer without furnace annealing.3. The method of claim 1 , wherein oxidizing the oxide layer by using the oxygen plasma treatment further comprises using the oxygen plasma treatment with a power of about 1 KW to about 100 KW claim 1 , an oxygen flow of about 10 SCCM to about 1000 SCCM and a pressure of about 0.5 Torr to about 1000 Torr.4. The method of claim 1 , further comprising performing a rapid thermal annealing with a temperature of about 300° C. to about 1000° C. and a duration of about 0.01 second to about 10 seconds.5. The method of claim 1 , wherein forming the oxide layer over the etch stop layer further comprises forming the oxide layer by using flowable chemical vapor deposition.6. The method of claim 1 , wherein forming the oxide layer over the etch stop layer further comprises forming the oxide layer by using high-density plasma chemical vapor deposition.7. The method of claim 1 , further comprising performing chemical ...

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Номер записи: 77

25-01-2018 дата публикации

Deposition Of Flowable Silicon-Containing Films

Номер: US20180025907A1

Автор: Ashok Tejasvi, Kalutarage Lakmal C., Mallick Abhijit Basu, Manna Pramit, Saly Mark, Thompson David

Принадлежит:

Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill. 1. A processing method comprising exposing a substrate surface to a silicon-containing precursor and a co-reactant to deposit a flowable film , the silicon-containing precursor having at least one akenyl or alkynyl group.2. The processing method of claim 1 , wherein the co-reactant comprises a plasma comprising a plasma gas.4. The processing method of claim 3 , wherein one or more of R1-R6 of the silicon-containing precursor is CR′CR″.5. The processing method of claim 4 , wherein all of R1-R6 of the silicon-containing precursor comprises CR′CR″.6. The processing method of claim 5 , wherein each R′ is the same and each R″ is the same substituent.7. The processing method of claim 6 , wherein the silicon-containing precursor comprises tetravinylsilane (Si(CHCH)).8. The processing method of claim 3 , wherein one or more of R1-R6 of the silicon-containing precursor is CCR′.9. The processing method of claim 8 , wherein all of R1-R6 of the silicon-containing precursor comprises CCR′.10. The processing method of claim 9 , wherein each R′ is the same and each R″ is the same substituent.11. The processing method of claim 10 , wherein the silicon-containing precursor comprises silicon tetraacetalide (Si(CCH)).12. The processing method of claim 2 , wherein the plasma gas comprises one or more of NH claim 2 , O claim 2 , CO claim 2 , CO claim 2 , Ar claim 2 , He or H.13. The processing method of claim 12 , wherein the plasma gas comprises ammonia.14. The processing method of claim 2 , further comprising curing the flowable film to form a cured film.15. The processing method of claim 14 , wherein curing the flowable film comprises exposing the flowable ...

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Номер записи: 78

25-01-2018 дата публикации

Semiconductor Structure with Resistor Layer and Method for Forming the Same

Номер: US20180026031A1

Автор: Chen I-Tseng, Huang Chun-Hsien, Huang Hon-Lin, Lin Yu-Hung

Принадлежит:

A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous. 1. A method for forming a semiconductor device structure , comprising: providing the substrate having the dielectric layer on a stage;', 'transferring the substrate from the stage into a deposition chamber, wherein the transferred substrate has a temperature below a temperature of the deposition chamber; and', 'depositing the resistor layer in the deposition chamber, wherein the substrate is not heated during the depositing., 'forming a resistor layer over a dielectric layer over a semiconductor substrate, wherein a major structure of the resistor layer is amorphous, and wherein the forming the resistor layer includes2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the substrate is not heated in the deposition chamber before forming the resistor layer.3. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the resistor layer is formed along (111) claim 1 , (200) and (220) crystal orientations.4. The method for forming the semiconductor device structure as claimed in claim 3 , wherein an intensity of the (200) crystal orientation is higher than an intensity of the (111) crystal orientation.5. The method for forming the semiconductor device structure as claimed in claim 4 , wherein an intensity of the (220) crystal orientation is substantially equal to the intensity of the (111) crystal orientation.6. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the resistor layer includes titanium nitride (TiN) claim 1 , tantalum nitride (TaN) claim 1 , silicon chrome (SiCr) claim 1 , ...

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Номер записи: 79

10-02-2022 дата публикации

DEPOSITION OF LOW-STRESS CARBON-CONTAINING LAYERS

Номер: US20220044926A1

Автор: ALAYAVALLI Kaushik, KUSTRA Rick, Mallick Abhijit Basu, Pinson Jay D., Qi Bo, Wang Huiyuan

Принадлежит: Applied Materials, Inc.

Examples of the present technology include semiconductor processing methods that provide a substrate in a substrate processing region of a substrate processing chamber, where the substrate is maintained at a temperature less than or about 50° C. An inert precursor and a hydrocarbon-containing precursor may be flowed into the substrate processing region of the substrate processing chamber, where a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor may be greater than or about 10:1. A plasma may be generated from the inert precursor and the hydrocarbon-containing precursor, and a carbon-containing material may be deposited from the plasma on the substrate. The carbon-containing material may include diamond-like-carbon, and may have greater than or about 60% of the carbon atoms with sphybridized bonds. 1. A semiconductor processing method comprising:providing a substrate in a substrate processing region of a substrate processing chamber, wherein the substrate is maintained at a temperature less than or about 50° C.;flowing an inert precursor and a hydrocarbon-containing precursor into the substrate processing region of the substrate processing chamber, wherein a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor is greater than or about 10:1;generating a plasma from the inert precursor and the hydrocarbon-containing precursor; anddepositing a carbon-containing material from the plasma on the substrate.2. The semiconductor processing method of claim 1 , wherein the hydrocarbon-containing precursor is flowed at a flow rate of less than or about 50 sccm.3. The semiconductor processing method of claim 1 , wherein the inert precursor is flowed at a flow rate of more than or about 1000 sccm.4. The semiconductor processing method of claim 1 , wherein the substrate processing chamber is maintained at a pressure of less than or about 100 mTorr.5. The semiconductor processing method of claim 1 , wherein the carbon- ...

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Номер записи: 80

10-02-2022 дата публикации

SILICON COMPOUNDS AND METHODS FOR DEPOSITING FILMS USING SAME

Номер: US20220044928A1

Автор: ACHTYL JENNIFER LYNN ANNE, ENTLEY William Robert, Lei Xinjian, RIDGEWAY ROBERT G., VRTIS RAYMOND N.

Принадлежит: Versum Materials US, LLC

A chemical vapor deposition method for producing a dielectric film, the method comprising: providing a substrate into a reaction chamber; introducing gaseous reagents into the reaction chamber wherein the gaseous reagents comprise a silicon precursor comprising an silicon compound having Formula I as defined herein and applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a film on the substrate. The film as deposited is suitable for its intended use without an optional additional cure step applied to the as-deposited film. 2. The method of wherein the silicon precursor further comprises a hardening additive.3. The method of wherein the silicon compound comprises at least one selected from the group consisting of 1 claim 1 ,1-dimethoxy-1-silacyclopentane claim 1 , 1 claim 1 ,1-diethoxy-1-silacyclopentane claim 1 , 1 claim 1 ,1-di-n-propyloxy-1-silacyclopentane claim 1 , 1 claim 1 ,1-di-iso-propyloxy-1-silacyclopentane claim 1 , 1 claim 1 ,1-dimethoxy-1-silacyclobutane claim 1 , 1 claim 1 ,1-diethoxy-1-silacyclobutane claim 1 , 1 claim 1 ,1-di-n-propyloxy-1-silacyclobutane claim 1 , 1 claim 1 ,1-di-iso-propyloxy-1-silacyclobutane claim 1 , 1 claim 1 ,1-dimethoxy-1-silacyclohexane claim 1 , 1 claim 1 ,1-di-iso-propyloxy-1-silacyclohexane claim 1 , 1 claim 1 ,1-di-n-propyloxy-1-silacyclohexane claim 1 , 1-methoxy-1-acetoxy-1-silacyclopentane claim 1 , 1 claim 1 ,1-diacetoxy-1-silacyclopentane claim 1 , 1-methoxy-1-acetoxy-1-silacyclobutane claim 1 , 1 claim 1 ,1-diacetoxy-1-silacyclobutane claim 1 , 1-methoxy-1-acetoxy-1-silacyclohexane claim 1 , 1 claim 1 ,1-diacetoxy-1-silacyclohexane claim 1 , 1-ethoxy-1-acetoxy-1-silacyclopentane claim 1 , 1-ethoxy-1-acetoxy-1-silacyclobutane claim 1 , and combinations thereof.4. The method of wherein the hardening additive comprises tetraethoxysilane.5. The method of wherein the hardening additive comprises tetramethoxysilane.6. The method of which is a plasma ...

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Номер записи: 81

10-02-2022 дата публикации

SEMICONDUCTOR DEVICE WITH REDUCED CRITICAL DIMENSIONS

Номер: US20220044933A1

Автор: Su Kuo-Hui

Принадлежит:

A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension. 1. A semiconductor structure , comprising:a base layer with a top surface;a primary pattern with a pattern top surface and a sidewall, disposed on the top surface of the base layer, wherein the primary pattern has a first critical dimension;a plurality of processed areas on the pattern top surface and on a part of the top surface of the base layer exposed by the primary pattern; anda secondary pattern disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.2. The semiconductor structure of claim 1 , wherein the base layer and the primary pattern comprise silicon.3. The semiconductor structure of claim 2 , wherein the secondary pattern comprises silicon dioxide.4. The semiconductor structure of claim 2 , wherein the base layer comprises a silicon substrate.5. The semiconductor structure of claim 2 , wherein the primary pattern comprises polysilicon.6. The semiconductor structure of claim 1 , wherein the processed areas comprise ion implantation damage.7. A semiconductor structure claim 1 , comprising:a base layer with a top surface;a plurality of processed areas on the top surface, wherein the processed areas have a first critical dimension and each of the processed areas has an ...

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Номер записи: 82

10-02-2022 дата публикации

SUBSTRATE SUPPORTING APPARATUS, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD

Номер: US20220044956A1

Автор: CHOI Seung Woo, LEE Seung Hwan, Park Ju Hyuk

Принадлежит:

A substrate processing method capable of stably loading a substrate regardless of a variation in pressure of a reaction space includes supplying an inert gas; and forming a thin film by sequentially and repeatedly supplying a source gas, supplying a reaction gas, and activating the reaction gas, wherein a center portion of a substrate and a center portion of a susceptor are spaced apart from each other to form a separate space, the reaction space above the substrate and the separate space communicate with each other via one or more channels, an inert gas is introduced to the separate space through the one or more channels during the supplying of the inert gas, and the inert gas prevents pressure imbalance between the separate space and the reaction space during a thin film deposition process. 1. A substrate processing method comprising:providing a substrate within a substrate supporting apparatus;supplying an inert gas within the substrate supporting apparatus; anddepositing a thin film onto the substrate by sequentially and repeatedly supplying a source gas, supplying a reaction gas, and activating the reaction gas within the substrate supporting apparatus,wherein the substrate supporting apparatus comprises:a susceptor main body comprising an inner portion, a periphery portion, and a concave portion between the inner portion and the periphery portion; anda rim arranged in the concave portion,wherein, when the substrate is mounted on the rim,the rim contacts the substrate within an edge exclusion zone of the substrate,an upper surface of the inner portion is lower than an upper surface of the rim to make a rear surface of the substrate spaced apart from the inner portion,a first space is formed between the rear surface of the substrate and the inner portion,a second space is formed above the substrate, andone or more channels are formed in at least one of the susceptor main body and the rim, the one or more channels connecting the first space to the second space ...

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Номер записи: 83

24-01-2019 дата публикации

Method For Selectively Etching Silicon Oxide Film

Номер: US20190027373A1

Автор: KWON Bong-Soo, Sim Tae-Yong

Принадлежит:

The present invention relates to a method for selectively etching a silicon oxide film by using a low-temperature process in a semiconductor manufacturing process and, more specifically, the method comprises the steps of: putting, into a reactor, a substrate having a silicon oxide film and a silicon nitride film formed thereon; setting process conditions including a process temperature having a range of 0° C. to 30° C. below zero; and supplying process gas into the reactor under the process conditions so as to selectively etch the silicon oxide film with respect to the silicon nitride film. 1. A selective etching method of a silicon oxide film , the method comprising:transferring a substrate with a silicon oxide film and a silicon nitride film formed thereon into a reactor;setting a process condition including process temperature of the substrate in the range of 0° C. to 30° C. below zero; andsupplying process gas to the reactor under the process condition to selectively etch the silicon oxide film with respect to the silicon nitride film.2. The method of claim 1 , wherein process pressure in the reactor is in the range of 30 to 200 Torr.3. The method of claim 1 , wherein process pressure in the reactor is maintained at 50 to 150 Torr claim 1 , andwherein hydrogen fluoride (HF) gas and IPA gas are used as the process gas.4. The method of claim 3 , wherein a flow rate ratio of the hydrogen fluoride (HF) gas and the IPA gas is equal to or greater than 5:1.5. The method of claim 3 , wherein a flow rate ratio of the hydrogen fluoride (HF) gas and the IPA gas is equal to or greater than 10:1.6. A selective etching method of a silicon oxide film claim 3 , the method comprising:transferring a substrate with a silicon oxide film and a silicon nitride film formed thereon into a reactor;setting a process condition including process gas, process pressure in the reactor, and process temperature of the substrate for selectively removing a silicon oxide film with respect to the ...

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Номер записи: 84

24-01-2019 дата публикации

Techniques and Structure for Forming Thin Silicon-on-Insulator Materials

Номер: US20190027396A1

Автор: Evans Morgan D., Hautala John, Waite Andrew M.

Принадлежит: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.

A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation. 1. A method , comprising: an insulator layer: and', 'a silicon layer, the silicon layer disposed on the insulator layer, the silicon layer comprising a first silicon thickness variation;, 'providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprisingforming an oxide layer on the silicon layer, the oxide layer having a uniform thickness; andselectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a non-uniform oxide thickness, whereinafter thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness is configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.2. The method of claim 1 , wherein a first thickness of the oxide layer is removed at a first position of the substrate claim 1 , wherein a second thickness of the oxide layer is removed at a second position of the substrate claim 1 , the second thickness being greater than the first thickness claim 1 , wherein claim 1 , before the selectively forming the oxide layer claim 1 , the silicon layer comprises a first silicon thickness at the first position claim 1 , wherein the silicon layer comprises a ...

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Номер записи: 85

24-01-2019 дата публикации

SHALLOW TRENCH ISOLATION (STI) GAP FILL

Номер: US20190027556A1

Автор: JR. Joseph F., Krishnan Rishikesh, Liu Jinping, Shepard, Shu Jiehui, XU Yiheng

Принадлежит:

A method of forming a shallow trench isolation (STI) for an integrated circuit (IC) structure to mitigate fin bending disclosed. The method may include forming a first insulator layer in a first portion of an opening in a substrate by a bottom-up atomic layer deposition (ALD) process; and forming a second insulator layer on the first insulator layer in a second portion of the opening. The opening may be position between a set of fins in the substrate. The method may further include forming an oxide liner in the opening before the forming the first insulator layer. The second insulator layer may be formed by deposition using a flowable chemical vapor deposition (FCVD) process, high aspect ratio process (HARP), high-density plasma chemical vapor deposition (HDP CVD) process, or any other conventional insulator material deposition process. 1. A method of forming an integrated circuit (IC) structure , the method comprising:providing an initial structure having: a substrate; a plurality of fins extending from the substrate; and a trench in the substrate isolating neighboring ones of the plurality of fins from one another,forming a first insulator layer in a first portion of the trench in the substrate by a bottom-up atomic layer deposition (ALD) process,wherein forming the first insulator layer by the ALD process includes forming the first insulator layer in a substantially V-shaped cross-sectional geometry or a substantially U-shaped cross-sectional geometry in the trench, and wherein the first insulator layer only partially fills the trench during the ALD process;forming a second insulator layer directly on the first insulator layer in a second portion of the trench,wherein forming the second insulator layer directly on the first insulator layer in the trench includes filling a gap in the substantially V-shaped cross-sectional geometry or the substantially U-shaped cross-sectional geometry in the trench; andannealing the first insulator layer and the second insulator ...

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Номер записи: 86

29-01-2015 дата публикации

PROCESS FOR THINNING THE ACTIVE SILICON LAYER OF A SUBSTRATE OF "SILICON ON INSULATOR" (SOI) TYPE

Номер: US20150031190A1

Автор: Boedt Francois, Kerdiles Sébastien

Принадлежит:

The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer, on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness. 116.-. (canceled)17. A method for thinning an active silicon layer of a silicon-on-insulator (SOI) substrate having an insulator layer buried between the active silicon layer and a support , the method comprising:forming a sacrificial silicon oxide layer by sacrificial thermal oxidation of a portion of the active silicon layer;forming a complementary oxide layer on the active silicon layer using an oxidizing plasma, the complementary oxide layer having a thickness profile at least substantially complementary to a thickness profile of the sacrificial silicon oxide layer such that a sum of the thicknesses of the complementary oxide layer and the sacrificial silicon oxide layer are at least substantially constant over the entire surface of the SOI substrate; andremoving the sacrificial silicon oxide layer; andremoving the complementary oxide layer;wherein the thinned active silicon layer has an at least substantially uniform thickness after forming and removing each of the sacrificial silicon oxide layer and the complementary oxide layer.18. The method of claim 17 , wherein forming the complementary oxide layer using the oxidizing plasma is carried out in a ...

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Номер записи: 87

29-01-2015 дата публикации

Method for manufacturing semiconductor wafers

Номер: US20150031202A1

Автор: Jean-Luc Delcarri, Julien VITIELLO

Принадлежит: ALTATECH SEMICONDUCTOR

The invention relates to a method for manufacturing a semiconductor wafer including a conductive via extending from a main surface of the wafer, said the via having a shape factor greater than five, the wafer including a dielectric layer, the method including: producing, by means of deep etching, at least one recess in the semiconductor wafer, the recess extending from the main surface of the wafer and having a shape factor greater than five, the recess including a side surface; forming at least one dielectric layer in the recess, including two treatments in a controlled-pressure reactor, one of said the treatments including the chemical vapor deposition, at sub-atmospheric pressure, of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a temperature lower than 400° C. and at a pressure greater than 100 Torr in the reactor, and another of the treatments including the plasma-enhanced chemical vapor deposition of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a pressure of less than 20 Torr in the reactor; and filling the recess with a conductive material, thus forming a via.

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Номер записи: 88

23-01-2020 дата публикации

Minimization of Carbon Loss in ALD SiO2 Deposition on Hardmask Films

Номер: US20200027718A1

Автор: Agnew Douglas Walter, Karim Ishtak

Принадлежит:

A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate. 1. A method for processing a substrate in a process chamber , the substrate having an initial pattern of spin-on-hardmask (SOH) defined on a surface of the substrate , the method comprising:exposing the surface of the substrate with the initial pattern of spin-on-hardmask (SOH) to a sequential operation for a defined number of times to form an oxide film layer of a thickness;directionally etching the oxide film layer to expose a top of the SOH of the initial pattern and the surface of the substrate; andperforming an ashing operation to remove the SOH of the initial pattern to leave oxide sidewalls, the oxide sidewalls defining a self-aligned double pattern.2. The method of claim 1 , wherein the sequential operation includes claim 1 ,exposing the surface of the substrate to a first precursor using a first plasma so as to allow the first precursor to be partially absorbed on the surface of the substrate to form Silicon-Hydrogen bonds; andexposing the surface of the substrate to a second precursor using a second plasma to cause oxygen radicals released from a weak oxidant of the second precursor to react with Silicon-Hydrogen bonds formed on the surface of the substrate to define the oxide film layer.3. The method of claim 2 , further includes performing a purging operation of the first precursor from the process chamber prior to introducing the second precursor into the process chamber.4. The method of claim 2 , further includes ...

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Номер записи: 89

28-01-2021 дата публикации

METHOD OF FORMING OXIDE FILM INCLUDING TWO NON-OXYGEN ELEMENTS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF FORMING DIELECTRIC FILM, AND SEMICONDUCTOR DEVICE

Номер: US20210028010A1

Автор: CHO Younjoung, JUNG Kyooho, KIM Haeryong, KIM Younsoo, MOON Sunmin, RYU Seungmin, SONG Jeonggyu, WOO Changsu

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of forming an oxide film including two non-oxygen elements includes providing a first source material on a substrate, the first source material including a first central element, providing an electron donor compound to be bonded to the first source material, providing a second source material on the substrate after the providing of the electron donor compound, the second source material including a second central element, and providing an oxidant on the substrate. 1. A method of forming an oxide film including two non-oxygen elements , the method comprising:providing a first source material on a substrate, the first source material comprising a first central element;providing an electron donor compound to be bonded to the first source material;providing a second source material on the substrate after the providing of the electron donor compound, the second source material comprising a second central element; andproviding an oxidant on the substrate.2. The method of claim 1 , whereinthe electron donor compound includes an oxygen-containing, nitrogen-containing, sulfur-containing, or phosphorus-containing hydrocarbon compound having an unshared electron pair.3. The method of claim 1 , whereinthe electron donor compound comprises at least one of a C1-C10 alcohol compound, a C2-C10 ether compound, a C3-C10 ketone compound, a C6-C12 aryl compound, a C3-C15 allyl compound, a C4-C15 diene compound, a C5-C20 β-diketone compound, a C5-C20 β-ketoimine compound, a C5-C20 β-diimine compound, ammonia, a C1-C10 amine compound, a C1-C10 thiol compound, and a C2-C10 thioether compound.4. The method of claim 1 , further comprisingproviding the electron donor compound on the substrate before the providing the first source material on the substrate.5. The method of claim 4 , further comprisingproviding the electron donor compound on the substrate after the providing the second source material on the substrate and before the providing the oxidant.6. The method of claim 1 , ...

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Номер записи: 90

28-01-2021 дата публикации

OXIDE FILM FORMATION METHOD

Номер: US20210028011A1

Автор: KAMEDA Naoto, MIURA Toshinori

Принадлежит: MEIDENSHA CORPORATION

Disclosed is an oxide film formation method that includes supplying an ozone gas having an ozone concentration of 20 to 100 vol %, an unsaturated hydrocarbon gas and a raw material gas to a workpiece () placed in a pressure-reduced treatment furnace (), whereby an oxide film is formed on a surface of the workpiece () by a chemical vapor deposition process. An example of the unsaturated hydrocarbon gas is an ethylene gas. An example of the raw material gas is a TEOS gas. The flow rate of the ozone gas is preferably set equal to or more than twice the total flow rate of the unsaturated hydrocarbon gas and the raw material gas. By this oxide film formation method, the oxide film is formed on the workpiece () at a high deposition rate even under low-temperature conditions of 200° C. or lower. 110.-. (canceled)11. An oxide film formation method comprising supplying , to a workpiece on which an oxide film is to be formed , an ozone gas , an unsaturated hydrocarbon gas and a raw material gas containing a Si element or metal element which is a constituent element of the oxide film , whereby the oxide film is formed on a surface of the workpiece by a chemical vapor deposition process ,wherein a supply flow rate of the ozone gas and a supply flow rate of the unsaturated hydrocarbon gas are maintained constant, and a supply flow rate of the raw material gas is changed with time or periodically.12. An oxide film formation method comprising supplying , to a workpiece on which an oxide film is to be formed , an ozone gas , an unsaturated hydrocarbon gas and a raw material gas containing a Si element or metal element which is a constituent element of the oxide film , whereby the oxide film is formed on a surface of the workpiece by a chemical vapor deposition process ,wherein a supply flow rate of the ozone gas and a supply flow rate of the raw material gas are maintained constant, and a supply flow rate of the unsaturated hydrocarbon gas is changed with time or periodically.13. ...

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Номер записи: 91

28-01-2021 дата публикации

Semiconductor structure including mim capacitor

Номер: US20210028275A1

Автор: Shun-Yi Lee, Tung-Jiun Wu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.

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Номер записи: 92

02-02-2017 дата публикации

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

Номер: US20170032955A1

Автор: Sumiya Masahiro, TANAKA Motohiro

Принадлежит: HITACHI HIGH-TECHNOLOGIES CORPORATION

In a plasma processing apparatus comprising a processing chamber arranged in a vacuum chamber, a sample stage arranged under the processing chamber and having its top surface on which a wafer to be processed is mounted, a vacuum decompression unit for evacuating the interior of the processing chamber to reduce the pressure therein, and introduction holes arranged above said sample stage to admit process gas into the processing chamber, the wafer having its top surface mounted with a film structure and the film structure being etched by using plasma formed by using the process gas, the film structure is constituted by having a resist film or a mask film, a poly-silicon film and an insulation film laminated in this order from top to bottom on a substrate and before the wafer is mounted on the sample stage and the poly-silicon film underlying the mask film is etched, plasma is formed inside the processing chamber to cover the surface of members inside the processing chamber with a coating film containing a component of Si. 17-. (canceled)8. A plasma processing method for plasma-etching a material to be processed in a processing chamber , comprising: [{'sub': 4', '2', '4', '4, 'depositing a deposit film inside the processing chamber by using a plasma using at least one of a first mixture gas comprising SiCland Oand a second mixture gas comprising SiCland methane (CH); and'}, 'in response to determining that the deposit film has been deposited, plasma etching a surface of the deposit film using a first gas comprising a Freon element and then placing the material to be processed on a sample stage in the processing chamber,, 'in response to determining that the material is not placed in the processing chamber,'} 'plasma-etching the material,', 'in response to determining that the material to be processed is placed on the sample stage,'} 'plasma-cleaning an interior portion of the processing chamber using a second gas comprising the Freon element, the second gas being ...

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Номер записи: 93

04-02-2016 дата публикации

METHODS AND APPARATUSES FOR SHOWERHEAD BACKSIDE PARASITIC PLASMA SUPPRESSION IN A SECONDARY PURGE ENABLED ALD SYSTEM

Номер: US20160035566A1

Автор: Baldasseroni Chloe, Kang Hu, KUMAR Purushottam, LaVoie Adrien, Pasquale Frank, Qian Jun, Swaminathan Shankar

Принадлежит:

Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O. Also disclosed are apparatuses which implement the foregoing processes. 2. The method of claim 1 , wherein the secondary purge gas is O.3. The method of claim 1 , wherein the primary purge gas is an inert gas.4. The method of claim 3 , wherein the primary purge gas is Ar and/or N.5. The method of claim 1 , wherein the primary purge gas is not flowed to the processing chamber during (a)-(b) or (d).6. The method of claim 5 , wherein substantially all primary purge gas is removed from the processing chamber prior to (d).7. The method of claim 1 , wherein the secondary purge gas is continuously flowed to the processing chamber during (a)-(d).8. The method of claim 1 , wherein a flow of carrier gas is used for flowing the film precursor into the processing chamber in (a).9. The method of claim 8 , wherein the carrier gas is an inert gas.10. The method of claim 9 , wherein the carrier gas is Nand/or Ar.11. The method of claim 1 , further comprising:(e) removing desorbed film precursor and/or reaction by-product from the volume surrounding the film layer when present after reacting the adsorbed precursor by purging the ...

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Номер записи: 94

04-02-2016 дата публикации

Method for Masking a Surface Comprising Silicon Oxide

Номер: US20160035570A1

Автор: Laermer Franz

Принадлежит:

A method for masking a surface, in particular a surface having silicon oxide, aluminum or silicon, includes providing a substrate having a surface to be masked, in particular having a surface having silicon oxide, aluminum or silicon; and producing a defined masking pattern by locally selective forming of colloidal silicon oxide on the surface. The method allows for the creating of an extremely stable masking in a simple and cost-effective manner, in contrast to a plurality of etching media, in particular in contrast to hydrofluoric acid, in order to thus create extremely accurate and defined structures such as by an etching process. 1. A method for masking a surface , comprising:locating a substrate having a surface to be masked, the surface comprising silicon oxide, aluminum, or silicon; andproducing a defined masking pattern by local selective formation of colloidal silicon oxide on the surface.2. The method as claimed in claim 1 , further comprising:{'sub': 2', '6, 'carrying out the local selective formation of colloidal silicon oxide by spatially selective and successive application and drying of fluorosilicic acid (HSiF) on the surface.'}3. The method as claimed in claim 2 , further comprising:selectively applying fluorosilicic acid to the surface by printing, spin coating, atomization, or spreading of the fluorosilicic acid; by dipping the surface in fluorosilicic acid; or by printing fluorosilicic acid onto the surface.4. The method as claimed in claim 2 , wherein further comprising:drying the fluorosilicic acid using an oven, a hotplate, a hot air fan, a radiant heater, or by air drying at room temperature.5. The method as claimed in claim 1 , further comprising:masking the surface to form a negative masking pattern before producing the defined masking pattern.6. The method as claimed in claim 5 , further comprising:producing the negative masking pattern using a photoresist.7. The method as claimed in claim 1 , further comprising:cleaning the surface before ...

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Номер записи: 95

01-02-2018 дата публикации

METHOD FOR PLANARIZING MATERIAL LAYER

Номер: US20180033633A1

Автор: Hsu Li-Chieh, Huang Po-Cheng, Li Kun-Ju, Li Yu-Ting, Lin Chien-Nan, Liu Yi-Liang, Tsai Fu-Shou

Принадлежит:

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely. 1. A method for planarizing a silicon layer , comprising:providing a silicon layer having at least one recess therein;forming a photoresist layer covering the silicon layer and filling up the recess;hardening the photoresist layer;planarizing of the photoresist layer by taking a top surface of the silicon layer as a stop layer, wherein the step of planarizing the photoresist layer comprises planarizing the photoresist layer by a chemical mechanical planarization process; andetching back the photoresist layer and the silicon layer to remove the photoresist layer entirely.2. The method for planarizing a silicon layer of claim 1 , further comprising:providing a substrate covered by the silicon layer, wherein the substrate comprises an isolated pattern and a dense pattern, and the recess is directly above the isolated pattern.3. The method for planarizing a silicon layer of claim 2 , wherein the dense pattern comprises a plurality of fins claim 2 , and the isolated pattern comprises a flat surface.4. (canceled)5. The method for planarizing a silicon layer of claim 1 , wherein the step of planarizing the photoresist layer comprises planarizing the photoresist layer by an etching process.6. The method for planarizing a silicon layer of claim 1 , further comprising:after etching back the silicon layer, patterning the silicon layer to form at least one gate.7. The method for planarizing a silicon layer of claim 1 , wherein after forming the photoresist layer covering the silicon layer and before ...

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Номер записи: 96

01-02-2018 дата публикации

Multi-Patterning to Form Vias with Straight Profiles

Номер: US20180033685A1

Автор: Chen Chih-Hao, Chen Chun-Kai, CHOU Chia Cheng, Ko Chung-Chi, Lee Tze-Liang, Pan Shing-Chyang, Shiu Jung-Hau

Принадлежит:

A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material. 1. A method comprising:forming a carbon-containing layer;forming a capping layer over the carbon-containing layer;in a double-patterning process, forming a first opening and a second opening in the capping layer and the carbon-containing layer;patterning a photo resist underlying the carbon-containing layer using the carbon-containing layer as an etching mask;etching a dielectric layer underlying the photo resist to extend the first opening and the second opening into the dielectric layer, wherein the photo resist is used as an etching mask; andfilling portions of the first opening and the second opening in the dielectric layer with a conductive material.2. The method of claim 1 , wherein the carbon-containing layer has a carbon atomic percentage higher than about 25 percent.3. The method of claim 2 , wherein the carbon atomic percentage is between about 25 percent and about 35 percent.4. The method of claim 1 , wherein each of the first opening and the second opening is formed by steps comprising:forming and patterning an additional photo resist over the ...

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Номер записи: 97

17-02-2022 дата публикации

STEAM OXIDATION INITIATION FOR HIGH ASPECT RATIO CONFORMAL RADICAL OXIDATION

Номер: US20220051890A1

Автор: KIM Taewan, Olsen Christopher S.

Принадлежит:

A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region. 1. A substrate oxidation assembly comprising:a chamber body defining a processing volume;a substrate support disposed in the processing volume;a plasma source coupled to the processing volume;a steam source fluidly coupled to the processing volume and comprising a catalytic steam generator; anda substrate heater configured to heat to between 700° C. and 1100° C.2. The substrate oxidation assembly of claim 1 , further comprising a quartz-lined conduit fluidly coupling the steam source to the processing volume.3. The substrate oxidation assembly of claim 1 , wherein the processing volume includes a plasma volume claim 1 , the plasma source is coupled to the plasma volume claim 1 , the steam source is coupled to an inlet of the chamber body claim 1 , and the plasma volume is between the inlet and the substrate support.4. The substrate oxidation assembly of claim 1 , further comprising a gas distributor coupled to the chamber body claim 1 , wherein:the gas distributor has one or more inlet ports,the steam source is fluidly coupled to the one or more inlet ports, andthe gas ...

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Номер записи: 98

17-02-2022 дата публикации

Semiconductor Device and Method

Номер: US20220052169A1

Автор: MORE Shahaji B., SAVANT Chandrashekhar Prakash

Принадлежит:

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region. 1. A device comprising:a gate structure over a substrate;a gate spacer adjacent the gate structure;a source/drain region adjacent the gate spacer;a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; anda second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; anda source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.2. The device of claim 1 , wherein the first concentration of the impurity decreases through the first ILD in a direction extending from a top of the first ILD to a bottom of the first ILD.3. The device of claim 1 , wherein the second concentration of the impurity is zero.4. The device of claim 1 , wherein the first ILD is disposed in gaps around the source/drain region claim 1 , and the second ILD extends along a top surface of the first ILD.5. The device of claim 1 , wherein a thickness of the first ILD is greater than a thickness of the second ILD.6. A device comprising:a gate structure over a substrate;a source/drain region adjacent the gate structure; ...

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Номер записи: 99

31-01-2019 дата публикации

Implantations for Forming Source/Drain Regions of Different Transistors

Номер: US20190035694A1

Автор: Chang Shih-Chieh, MORE Shahaji B., Pan Zheng-Yang, Wang Chun-Chieh

Принадлежит:

A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack. 1. A method comprising: forming a silicon oxide layer on a semiconductor region;', 'depositing a hafnium oxide layer over the silicon oxide layer;', 'depositing a lanthanum oxide layer over the hafnium oxide layer; and', 'depositing a work-function layer over the lanthanum oxide layer; and, 'forming a first gate stack of a first transistor comprisingforming first source/drain regions on opposite sides of the first gate stack.2. The method of further comprising depositing a hafnium silicate layer between the silicon oxide layer and the hafnium oxide layer.3. The method of claim 2 , wherein the hafnium silicate layer has a hafnium atomic percentage lower than about 10 percent.4. The method of claim 1 , wherein the silicon oxide layer is free from hafnium.5. The method of further comprising depositing a lanthanum silicon oxide layer over the lanthanum oxide layer.6. The method of further comprising:removing the lanthanum oxide layer and the hafnium oxide layer; anddepositing an additional hafnium oxide layer over the silicon oxide layer.7. The method of further comprising depositing a titanium silicon nitride layer over the lanthanum oxide layer.8. A method comprising:forming a silicon oxide layer comprising a first portion and a second portion over a first semiconductor region and a second semiconductor region, respectively;depositing a first hafnium oxide layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the silicon oxide layer;depositing a lanthanum oxide layer comprising a first portion ...

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Номер записи: 100