Semiconductor device having super junction structure and method for manufacturing the same

A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.

Bipolar transistor structure having split collector region and method of making the same

A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Information transmission system and method

An information transmission system includes a mobile device, a signal transmission line and an internet device with networking capabilities. The mobile device includes a user interface, an encoder, a modulator and an audio connector. The user interface receives network setting information, and the encoder is coupled to the user interface to encodes the network setting information into information codes. The modulator is coupled to the encoder to modulate the information codes to form an audio signal embedded with the information codes. The audio connector is coupled to the modulator, and the signal transmission line is connected to the audio connector of the mobile device to transmit the audio signal embedded with the information codes. The internet device is connected to the signal transmission line, receives the audio signal with the embedded information codes, and decodes the information codes into the network setting information.

IP camera, communication method and communication system

An IP camera, a communication method and a communication system are provided. The IP camera includes an image capturing unit, a video processing unit and a connection processing unit. The image capturing unit captures a plurality of consecutive images. The video processing unit is coupled to the image capturing unit, and generates a first video stream and a second video stream according to the images. The connection processing unit is coupled to the video processing unit, processes the first video stream into a first packet stream, and processes the second video stream into a second packet stream. The connection processing unit transmits the first packet stream to a local area wireless network unit through a first wireless link, and the connection processing unit transmits the second packet stream to an external electronic device through a second wireless link.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Semiconductor device and method for fabricating the same

A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.

Isolation structure for semiconductor device

A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon.

Partial SOI on power device for breakdown voltage improvement

Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Method of fabricating a lateral insulated gate bipolar transistor

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

Passivation structure and method of making the same

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Methods for forming a high-voltage super junction by trench and epitaxial doping

A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Ultra high voltage semiconductor device with electrostatic discharge capabilities

A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion are formed having a same doping type and a different doping concentration than the drain rectangular portion.

ULTRA HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE CAPABILITIES

A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion are formed having a same doping type and a different doping concentration than the drain rectangular portion.

Apparatus and Method for High Voltage MOS Transistor

A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor. 1. An apparatus comprising:a first drain/source region formed over a substrate;a second drain/source region formed over the substrate; and a first conductor coupled to the first drain/source region through a first metal plug;', 'a second conductor coupled to the second drain/source region through a second metal plug; and', 'a plurality of first floating metal rings formed between the first conductor and the second conductor, wherein a cross sectional length of a first floating metal ring is approximately equal to a distance between two adjacent first floating metal rings., 'a first metal layer formed over the substrate comprising2. The apparatus of claim 1 , further comprising: a third conductor coupled to the first conductor through a third metal plug;', 'a fourth conductor coupled to the second conductor through a fourth metal plug; and', 'a plurality of second floating metal rings formed between the third conductor and the fourth conductor, wherein an overlap between a second floating metal ring and a corresponding first floating metal ring is approximately equal to a half of a difference between the cross sectional length of the first floating metal ring and the distance between two adjacent first floating metal rings; and, 'a second metal layer formed over the first metal layer comprisinga passivation layer formed on the second metal layer, wherein the passivation ...

PASSIVATION SCHEME

An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation. 1. An integrated circuit , comprising:a substrate; and a bottom dielectric layer formed over the substrate;', 'a doped dielectric layer formed over the bottom dielectric layer; and', 'a top dielectric layer formed over the doped dielectric layer., 'passivation layers including2. The integrated circuit of claim 1 , wherein the doped dielectric layer is doped with phosphorus claim 1 , boron claim 1 , or both.3. The integrated circuit of claim 1 , wherein the doped dielectric layer is doped with dopants ranging from 3% to 8%.4. The integrated circuit of claim 1 , wherein the doped dielectric layer has a thickness ranging from 5000 Å to 7000 Å.5. The integrated circuit of claim 1 , wherein the bottom dielectric layer comprises SiO.6. The integrated circuit of claim 1 , wherein the bottom dielectric layer has a thickness ranging from 2000 Å to 3000 Å.7. The integrated circuit of claim 1 , wherein the top dielectric layer comprises silicon nitride or polyimide.8. The integrated circuit of claim 1 , wherein the top dielectric layer has a thickness ranging from 2000 Å to 3000 Å.9. The integrated circuit of claim 1 , further comprising a metal layer formed between the substrate and the bottom dielectric layer.10. The integrated circuit of claim 1 , further comprising a molding compound layer formed over the top dielectric layer.11. A method claim 1 , comprisingforming a bottom dielectric layer for passivation over a substrate;forming a doped dielectric layer for passivation over the bottom dielectric layer; andforming a top dielectric layer for passivation over the doped dielectric layer.12. The method of claim 11 , wherein the doped dielectric ...

LATERAL INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE WITH LOW PARASITIC BJT GAIN AND STABLE THRESHOLD VOLTAGE

A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure. 1. A semiconductor device comprising:a semiconductor substrate having an insulator layer and a silicon layer over the insulator layer; and a drift region having a first type of conductivity over the insulator layer;', 'a first well region in the drift region and having the first type of conductivity;', 'a second well region in the drift region and having a second type of conductivity, the second type of conductivity being opposite the first type of conductivity;', 'a first insulating structure over and partially embedded in the drift region between the first well region and the second well region;', 'a second insulating structure over and partially embedded in the second well region;', 'a gate structure over the first insulating structure and partially over the second well region;', 'a drain region in the first well region;', 'a source region in the second well region between the second insulating structure and the gate structure, the source region including a first source region having the second type of conductivity and a second source region having the first type of conductivity, wherein the second source region is disposed partially under a portion of the gate structure; and', 'a third well region within the second well region disposed under the source region, the third well region having the second type of conductivity at a ...

Passivation structure and method of making the same

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided. 1. A semiconductor device having a super junction structure , comprising:a substrate;an epitaxial layer of a first conductivity type over the substrate;a first trench in the epitaxial layer;a first doped region of a second conductivity type opposite to the first conductivity type in the epitaxial layer and surrounding the first trench;a second trench in the epitaxial layer and separated from the first trench; anda second doped region of the first conductivity type in the epitaxial layer and surrounding the second trench, wherein the second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer.2. The semiconductor device of claim 1 , wherein the second doped region has a dopant concentration in a range of about 10ions/cmto about 10ions/cm.3. The semiconductor device of claim 1 , wherein the second trench is an angled trench.4. The semiconductor device of claim 1 , further comprising a fill material in the second trench.5. The semiconductor device of claim 4 , further comprising an insulating material between the fill ...

Passivation structure and method of making the same

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING

A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. 1. An integrated circuit , comprising:a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein, wherein the neighboring trenches each have trench sidewalls and a trench bottom surface;a region having a second conductivity type and disposed in or adjacent to a trench and meeting the semiconductor substrate region at a p-n junction deep in the substrate; anda gate electrode formed on the semiconductor substrate region and electrically isolated from the semiconductor substrate region by a gate dielectric;a body region having the second conductivity type and disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate, and a source region having the first conductivity type and disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.2. The integrated circuit of claim 1 , further comprising:an oxide formed within the trench in a recess in the region having the second conductivity type.3. The integrated circuit of claim 2 , ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer. 1. A semiconductor device comprising:a gallium nitride (GaN) layer on a substrate;an aluminum gallium nitride layer (AlGaN) disposed on the GaN layer;a gate metal stack disposed on the AlGaN layer;at least one ohmic contact disposed on the AlGaN layer;a gate field plate disposed between the ohmic contact and the gate metal stack;an anti-reflective coating (ARC) layer formed on the ohmic contact; andan etch stop layer formed on the ARC layer.2. The semiconductor device of claim 1 , wherein the etch stop layer is made of oxide or silicon nitride.3. The semiconductor device of claim 1 , wherein the ARC layer is made of TiN.4. The semiconductor device of claim 1 , wherein the gate field plate is made of TiN claim 1 , Ti claim 1 , Al claim 1 , AlCu claim 1 , or Cu.5. The semiconductor device of claim 1 , further comprising a metal contact penetrating the etch stop layer for connecting to the ARC layer.6. The semiconductor device of claim 1 , further comprising a doped GaN region formed between the gate metal stack and the AlGaN layer.7. The semiconductor device of claim 1 , further comprising a two dimensional electron gas (2DEG) region at a junction of the AlGaN layer and the GaN layer.8. The semiconductor device of claim 1 , wherein the at least one ohmic contact comprises a source contact and a drain contact claim 1 , the gate field plate is ...

Ultra high voltage semiconductor device with electrostatic discharge capabilities

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10. 1. A semiconductor structure , comprising:a semiconductor substrate with a first conductivity type;a first doped region with a second conductivity type in the semiconductor substrate;a second doped region with the second conductivity type in the semiconductor substrate; anda dielectric in the semiconductor substrate, and between the first doped region and the second doped region;wherein the first doped region and the second doped region are symmetrical with reference to the dielectric, the first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate, wherein the dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.2. The semiconductor structure of claim 1 , further comprising a cover over the dielectric.3. The semiconductor structure of claim 1 , wherein the first depth is greater than 15 μm.4. The semiconductor structure of claim 1 , wherein a sidewall of the dielectric is surrounded by the first doped region and the second doped region.5. The semiconductor structure of claim 1 , wherein the first doped region is electrically connected with the second doped region through an interconnect external to the semiconductor substrate.6. The semiconductor structure of claim 1 , further comprising an epitaxial layer under the first doped region and the second doped region claim 1 , wherein the epitaxial layer is ...

PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT

The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed. 1. A power device , comprising:a transistor disposed on a first surface of a device wafer and including a source region, a drain region, and a channel region which are laterally spaced apart over the first surface; anda handle wafer bonded to a second surface of the device wafer with an intermediate oxide layer, the handle wafer comprising: an un-recessed region having a first handle wafer thickness under the source region, and a recessed region having a second handle wafer thickness under both the channel region and the drain region, the second wafer thickness being less than the first wafer thickness.2. (canceled)3. (canceled)4. The power device of claim 1 , wherein the power device is isolated using the intermediate oxide layer.5. The power device of claim 1 , wherein the device wafer has a device wafer thickness of between approximately 2 μm and approximately 10 μm.6. (canceled)7. The power device of claim 1 , wherein the transistor has a breakdown voltage of greater than approximately 500 V.8. A semiconductor device disposed on a device wafer bonded to a handle wafer with an intermediate oxide layer claim 1 , comprising:a first field oxide layer disposed above a source region of the semiconductor device;a second field oxide layer ...

Passivation structure and method of making the same

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Bipolar transistor structure having split collector region and method of making the same

A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

SEMICONDUCTOR DEVICE

A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer. 1. A semiconductor device comprising:a III-V compound layer;a source contact and a drain contact over the III-V compound layer;a gate contact over the III-V compound layer and between the source contact and the drain contact;a gate field plate over the III-V compound layer;a first etch stop layer over the source contact; anda second etch stop layer over the drain contact and separated from the first etch stop layer.2. The semiconductor device of claim 1 , wherein a top surface of the gate field plate is lower than a top surface of the gate contact.3. The semiconductor device of claim 1 , further comprising:a first anti-reflective coating (ARC) layer between the first etch stop layer and the source contact; anda second ARC layer between the second etch stop layer and the drain contact, wherein the first ARC layer is separated from the second ARC layer.4. The semiconductor device of claim 3 , wherein the first ARC layer and the gate field plate comprises the same material.5. The semiconductor device of claim 3 , further comprising:a third ARC layer over the gate contact.6. The semiconductor device of claim 1 , further comprising:a protection layer surrounding the source contact, the drain contact, and a bottom portion of the gate contact; anda dielectric layer surrounding a top portion of the gate contact.7. A semiconductor device comprising:a first semiconductor layer;a second semiconductor layer over the first semiconductor layer;a source/drain contact over the ...

Semiconductor structure and preparation method thereof

A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon.

Multiple Layer Substrate

A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. 1. A substrate for an integrated circuit , comprising:a device wafer having a raw carrier concentration; anda first epitaxial layer disposed over the device wafer, the first epitaxial layer having a first carrier concentration,wherein the first carrier concentration is higher than the raw carrier concentration.2. The substrate of claim 1 , wherein the first carrier concentration ranges from 1.25 to 2.25 times the raw carrier concentration.3. The substrate of claim 1 , further comprising a second epitaxial layer having a second carrier concentration claim 1 , wherein the second epitaxial layer is disposed over the first epitaxial layer and the second carrier concentration is lower than the first carrier concentration.4. The substrate of claim 1 , wherein the device wafer comprises silicon.5. The substrate of claim 1 , wherein the first epitaxial layer comprises silicon and dopants.6. The substrate of claim 5 , wherein the dopants comprise phosphorous.7. The substrate of claim 5 , wherein the dopants comprise boron.9. The substrate of claim 8 , wherein the additional epitaxial layers comprises silicon with dopants.10. The substrate of claim 8 , wherein each of the additional epitaxial layers has a same thickness.11. A method of fabricating a substrate for an integrated circuit claim 8 , comprising:providing a device wafer; andforming a first epitaxial layer over the device wafer, wherein the device wafer has a raw carrier concentration, the first epitaxial layer has a first carrier concentration, and the first carrier concentration is higher than the raw carrier concentration.12. The method of claim 11 , wherein the first epitaxial layer is formed to have the first carrier concentration ...

Ultra high voltage semiconductor device with electrostatic discharge capabilities

A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.

IP CAMERA, COMMUNICATION METHOD AND COMMUNICATION SYSTEM

An IP camera, a communication method and a communication system are provided. The IP camera includes an image capturing unit, a video processing unit and a connection processing unit. The image capturing unit captures a plurality of consecutive images. The video processing unit is coupled to the image capturing unit, and generates a first video stream and a second video stream according to the images. The connection processing unit is coupled to the video processing unit, processes the first video stream into a first packet stream, and processes the second video stream into a second packet stream. The connection processing unit transmits the first packet stream to a local area wireless network unit through a first wireless link, and the connection processing unit transmits the second packet stream to an external electronic device through a second wireless link. 1. An IP camera , comprising:an image capturing unit, capturing a plurality of consecutive images;a video processing unit, coupled to the image capturing unit, and generating a first video stream and a second video stream according to the images; anda connection processing unit, coupled to the video processing unit, processing the first video stream into a first packet stream, and processing the second video stream into a second packet stream,wherein the connection processing unit transmits the first packet stream to a local area wireless network unit through a first wireless link, and the connection processing unit transmits the second packet stream to an external electronic device through a second wireless link.2. The IP camera as claimed in claim 1 , whereinwhen the connection processing unit determines that the first wireless link exists, the connection processing unit transmits a first notification signal to the video processing unit to generate the first video stream; andwhen the connection processing unit determines that the second wireless link exists, the connection processing unit transmits a second ...

ULTRA HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE CAPABILITIES

A semiconductor device comprises a semiconductor substrate, a first layer over the semiconductor substrate, and a drain region in the first layer. The drain region comprises a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion have a same doping type and a different doping concentration than the drain rectangular portion. 1. A semiconductor device comprising:a semiconductor substrate;a first layer over the semiconductor substrate; a drain rectangular portion having a first end and a second end;', 'a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region; and', 'a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region; and, 'a drain region in the first layer, the drain region comprising'}a source region free from contact with and surrounding the drain region in the first layer,wherein the first drain end portion and the second drain end portion have a same doping type and a different doping concentration as the drain rectangular portion.2. The semiconductor device of claim 1 , wherein the source region comprises:a first source rectangular portion parallel to, and aligned with, the drain rectangular portion on a first side of the drain rectangular portion;a second source ...

PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT

Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. 1. A method , comprising:providing a bonded wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer bonding the device wafer to the handle wafer;forming a semiconductor device in the device wafer; andforming a recess in a lower surface of the handle wafer and thereby defining a recessed region of the handle wafer, wherein the recessed region of the handle wafer has a first handle wafer thickness which is greater than zero, and wherein an un-recessed region of the handle wafer has a second handle wafer thickness that is greater than the first handle wafer thickness.2. The method of claim 1 , wherein the device wafer has a first conductivity type claim 1 , and wherein forming the semiconductor device in the device wafer comprises:performing a first implant into an upper surface of the device wafer to form a well having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type; andforming a gate over the upper surface of the device wafer and over a portion of the well, wherein the gate is separated from the device wafer by a gate dielectric; andperforming a second implant into the upper surface of the device wafer within the well adjacent the gate to form a first shallow doped region, which has ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer. 1. A method comprising:depositing a contact metal layer over a III-V compound layer;depositing an anti-reflective coating (ARC) layer over the contact metal layer;depositing an etch stop layer over the ARC layer;etching the etch stop layer, the ARC layer, and the contact metal layer to form a contact stack over the III-V compound layer;depositing a conductive layer over the III-V compound layer; andetching the conductive layer to form a gate field plate, wherein the etch stop layer has an etch selectivity different from that of the conductive layer.2. The method of claim 1 , wherein the conductive layer and the ARC layer comprises the same material.3. The method of claim 1 , wherein etching the conductive layer is performed such that the etch stop layer is substantially free from coverage by the gate field plate.4. The method of claim 1 , further comprising:etching the etch stop layer to expose the ARC layer; andforming a source/drain electrode over the ARC layer.5. The method of claim 4 , wherein etching the etch stop layer is performed such that a portion of the etch stop layer remains over the ARC layer after etching the etch stop layer.6. The method of claim 1 , wherein etching the conductive layer is performed such that a top of the gate field plate is in a position lower than a bottom of the ARC layer.7. The method of claim 1 , wherein depositing the etch stop layer is ...

METHOD OF MAKING BIPOLAR TRANSISTOR

A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process. 1. A method of making a bipolar transistor , the method comprising:patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening;performing a first implantation process through the first opening;patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening; andperforming a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.2. The method of claim 1 , wherein patterning the first photoresist comprises defining the first opening in an area of the collector region surrounding the second opening.3. The method of claim 1 , wherein performing the second implantation process comprises implanting a higher dopant concentration than the first implantation process claim 1 , and the second implantation process comprises implanting a dopant concentration ranging from about 5×10ions/cmto about 5×10ions/cm.4. The method of claim 1 , wherein patterning the first photoresist comprises defining a plurality of first openings.5. The method of claim 1 , wherein performing the second ...

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING

A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate. 1. A method of forming a semiconductor arrangement , comprising:forming a first well to a first depth and a first width in a substrate; and the second well surrounds the first well,', 'the first depth is greater than the second depth, and', 'the second width is greater than the first width., 'forming a second well to a second depth and a second width in the substrate, wherein2. The method of claim 1 , wherein the first depth is at least 0.1 micrometers greater than the second depth.3. The method of claim 1 , comprising:driving dopants of the first well from the first depth in the substrate to a third depth in the substrate by subjecting the substrate to a dopant drive-in condition.4. The method of claim 3 , wherein the dopant drive-in condition comprises a temperature within a range of 900° Celsius to 1000° Celsius.5. The method of claim 1 , comprising: forming the first well comprises forming the first well to a third depth in the substrate, and', 'the third depth is a depth of an upper surface of the buried oxide layer., 'forming a buried oxide layer in the substrate, wherein6. The method of claim 1 , comprising:forming a first conductive region in the second well; andforming a second conductive region in the substrate.7. The method of claim 6 , wherein:forming the first conductive region comprises doping the substrate with a first dopant type, andthe first dopant type is a different dopant type than a dopant type of the second well.8. The method of claim 1 , comprising:forming a first conductive region within the second well and to a first ...

SEMICONDUCTOR DEVICE

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer. 1. A device , comprising:a first III-V compound layer;a second III-V compound layer over the first III-V compound layer;a dielectric layer over the second III-V compound layer;an contact extending through the dielectric layer to the second III-V compound layer, wherein the contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer;a metal-containing layer over and in contact with the contact and a portion of the metal-containing layer is directly above the dielectric layer; anda metal contact over and in contact with the metal-containing layer.2. The device of claim 1 , wherein a bottommost surface of the metal-containing layer is wider than a bottommost surface of the metal contact.3. The device of claim 1 , wherein a bottom portion of the contact is embedded in the second III-V compound layer.4. The device of claim 1 , further comprising an etch stop layer over the metal-containing layer.5. The device of claim 4 , wherein the etch stop layer laterally surrounds a bottom of the metal contact.6. The device of claim 4 , wherein a sidewall of the etch stop layer is substantially aligned with a sidewall of the metal-containing layer.7. The device of claim 1 , further comprising a gate structure over the second III ...

PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHES

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer. 1. A method for forming an integrated circuit , the method comprising:forming an interlayer dielectric (ILD) layer covering a substrate;forming a conductive pad overlying the ILD layer;performing a first etch into the ILD layer to form a trench, wherein the trench extends through the ILD layer from a top of the ILD layer to the substrate;depositing a first passivation layer covering the ILD layer and the conductive pad;performing a second etch into the first passivation layer to form a pad opening overlying and exposing the conductive pad; anddepositing a second passivation layer covering the ILD layer, the conductive pad, and the first passivation layer, and further lining sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench, wherein the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.2. The method according to claim 1 , wherein the first passivation layer is deposited before the first etch claim 1 , wherein the first etch is also performed into the first passivation layer claim 1 , such that the trench extends through the first passivation layer ...

INFORMATION TRANSMISSION SYSTEM AND METHOD

An information transmission system includes a mobile device, a signal transmission line and an internet device with networking capabilities. The mobile device includes a user interface, an encoder, a modulator and an audio connector. The user interface receives network setting information, and the encoder is coupled to the user interface to encodes the network setting information into information codes. The modulator is coupled to the encoder to modulate the information codes to form an audio signal embedded with the information codes. The audio connector is coupled to the modulator, and the signal transmission line is connected to the audio connector of the mobile device to transmit the audio signal embedded with the information codes. The internet device is connected to the signal transmission line, receives the audio signal with the embedded information codes, and decodes the information codes into the network setting information. 1. An information transmission system , comprising: a user interface for receiving network setting information;', 'an encoder coupled to the user interface to encodes the network setting information into information codes;', 'a modulator coupled to the encoder to modulate the information codes to form an audio signal embedded with the information codes; and', 'an audio connector coupled to the modulator to receive the audio signal embedded with the information codes;, 'a mobile device, comprisinga signal transmission line connected to the audio connector of the mobile device to transmit the audio signal embedded with the information codes; andan internet device with networking capabilities connected to the signal transmission line, the internet device receiving the audio signal with the embedded information codes and decoding the information codes into the network setting information.2. The information transmission system as claimed in claim 1 , wherein the information codes are embedded in the audio signal using frequency modulation or ...

METHOD OF FABRICATING A LATERAL INSULATED GATE BIPOLAR TRANSISTOR

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well. 1. A method of fabricating a transistor , the method comprising:doping a first well in a silicon layer of a substrate, wherein the substrate has a first type of conductivity, and the first well and the silicon layer have a second type of conductivity;doping a second well and a third well having the first type of conductivity in the silicon layer, the first, second, and third wells being non-overlapping with one another;thermally growing a first insulating layer over the second well between the first well and the third well and a second insulating layer over the third well;forming a gate stack on the substrate, the gate stack having a first part overlying the first insulating layer and a second part overlying a portion of the third well;forming a first source region in the third well, the first source region having the second type of conductivity;forming a gate spacer around the gate stack;doping a fourth well in the third well between the second insulating layer and the gate spacer, the fourth well having the first type of conductivity;forming a second source region over a portion of the fourth well; andforming a drain ...

Multiple Layer Substrate

A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. 1. A method of fabricating a substrate for an integrated circuit , the method comprising:receiving a device wafer; andforming a first epitaxial layer over the device wafer, wherein the device wafer has a raw carrier concentration, the first epitaxial layer has a first carrier concentration, and the first carrier concentration ranges from 1.25 to 2.25 times the raw carrier concentration.2. The method of claim 1 , further comprising forming a second epitaxial layer over the first epitaxial layer claim 1 , wherein the second epitaxial layer has a second carrier concentration lower than the first carrier concentration.3. The method of claim 1 , wherein the device wafer comprises silicon.5. The method of claim 1 , wherein the first epitaxial layer comprises silicon and dopants.6. The method of claim 5 , wherein the dopants comprise at least one of phosphorous.7. The method of claim 5 , wherein the dopants comprise boron.9. The method of claim 8 , wherein the first carrier concentration ranges from 1.25 to 2.25 times the raw carrier concentration.10. The method of claim 8 , wherein the device wafer comprises silicon.11. The method of claim 8 , wherein the first epitaxial layer comprises silicon and dopants.12. The method of claim 11 , wherein the dopants comprise one of phosphorous and boron.13. The method of claim 8 , wherein the additional epitaxial layers comprise silicon with dopants.14. The method of claim 8 , wherein each of the additional epitaxial layers has a same thickness.15. A method of forming a semiconductor device claim 8 , the method comprising:forming a semiconductor wafer comprising silicon, the semiconductor wafer having a raw carrier concentration; andforming an epitaxial ...

HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING

A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. 1. A method , comprising:providing a semiconductor substrate region having a first conductivity type;forming neighboring trenches in the semiconductor substrate region;forming an epitaxial (EPI) liner, which has a second conductivity type, along sidewalls of the trenches and over bottom surfaces of the trenches;performing a thermal treatment to out-diffuse dopants from the EPI liner into a surrounding portion of the semiconductor substrate region, thereby forming an out-diffused region having the second conductivity type;forming a gate dielectric and a gate electrode over the semiconductor substrate region between the neighboring trenches;forming body regions at least partially under the gate electrode in the semiconductor substrate region; andforming source regions on opposite sides of the gate electrode and adjacent to the body regions.2. The method of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.3. The method of claim 1 , wherein the thermal treatment comprises exposing the substrate region and the EPI liner to a ...

Method of making bipolar transistor

A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×10 12 ions/cm 3 to about 5×10 13 ions/cm 3 , and the lightly doped peripheral region has a same maximum depth as the highly doped central region.

SEMICONDUCTOR DEVICE

A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate. 1. A high electron mobility transistor (HEMT) , comprising:a first III-V compound layer;a second III-V compound layer over the first III-V compound layer;source and drain structures over the second III-V compound layer and spaced apart from each other;a gate structure over the second III-V compound layer and between the source and drain structures;a gate field plate over the second III-V compound layer and between the gate structure and the drain structure; andan etch stop layer over the drain structure and spaced apart from the gate field plate.2. The HEMT of claim 1 , further comprising an anti-reflective coating (ARC) layer between the etch stop layer and the drain structure.3. The HEMT of claim 2 , wherein the ARC layer and the gate field plate comprise the same material.4. The HEMT of claim 2 , wherein the ARC layer fully covers a top surface of the drain structure.5. The HEMT of claim 2 , wherein a sidewall of the etch stop layer is substantially aligned with a sidewall of the ARC layer.6. The HEMT of claim 2 , wherein a sidewall of the ARC layer is substantially aligned with a sidewall of the drain structure.7. The HEMT of claim 1 , further comprising a doped III-V compound layer layer between the gate structure and the second III-V compound layer.8. The HEMT of claim 1 , wherein the gate field plate is free from coverage by the etch stop layer.9. The HEMT of claim 1 , further comprising a dielectric layer over the ...

PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHES

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer. 1. An integrated circuit comprising:a substrate;an interlayer dielectric (ILD) layer overlying the substrate;a conductive pad overlying the ILD layer;a first passivation layer overlying the ILD layer and the conductive pad, wherein the first passivation layer defines a pad opening overlying and partially exposing the conductive pad; anda second passivation layer overlying the ILD layer, the conductive pad, and the first passivation layer, and further lining a sidewall of the first passivation layer in the pad opening, wherein the second passivation layer has a high resistance to moisture or vapor relative to the ILD layer.2. The integrated circuit according to claim 1 , wherein the ILD layer and the first passivation layer comprise oxide claim 1 , and wherein the second passivation layer comprises silicon nitride claim 1 , aluminum oxide claim 1 , or polyimide.3. The integrated circuit according to claim 1 , wherein the second passivation layer has an L-shaped profile directly contacting the conductive pad and the sidewall of the first passivation layer.4. The integrated circuit according to claim 1 , further comprising:a plurality of peripheral ...

Apparatus and method for high voltage MOS transistor

A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer

A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of a silicon rich silicon oxide material formed over the thin film transistor device. The passivation layer formed of the silicon rich silicon oxide material provides the thin film transistor device with enhanced performance.

Semiconductor device

A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

A thin film transistor structure and manufacturing method thereof for reducing the threshold voltage shift

METHOD OF FORMING AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUITS

Integrierte Schaltung, die Folgendes aufweist:ein Substrat (102);eine dielektrische Zwischenschicht, ILD, (104) die das Substrat (102) bedeckt, wobei die ILD-Schicht (104) einen Graben (108) mindestens teilweise definiert, und wobei sich der Graben (108) durch die ILD-Schicht (104) von einer Oberseite der ILD-Schicht (104) zu dem Substrat (102) erstreckt;ein leitfähiges Pad (106a), das die ILD-Schicht (104) überlagert;eine erste Passivierungsschicht (110), die die ILD-Schicht (104) und das leitfähige Pad (106a) überlagert, wobei die erste Passivierungsschicht (110) eine Pad-Öffnung definiert, die das leitfähige Pad (106a) überlagert, undeine zweite Passivierungsschicht (114), die die ILD-Schicht (104), das leitfähige Pad (106a) und die erste Passivierungsschicht (110) überlagert und ferner erste Seitenwände der ersten Passivierungsschicht (110) in der Pad-Öffnung (106a) und zweite Seitenwände der ersten ILD-Schicht (104) in dem Graben (108) auskleidet,wobei das Substrat (102) Folgendes aufweist:ein Bulk-Halbleitersubstrat (102s), undeine Schicht der Gruppe III-V (102g), die das Bulk-Halbleitersubstrat (102s) bedeckt, wobei die ILD-Schicht (104) die Schicht der Gruppe III-V (102g) bedeckt, wobei sich der Graben (108) durch die Schicht der Gruppe III-V (102g) zu dem Bulk-Halbleitersubstrat (102s) erstreckt, und wobei der Graben (108) teilweise von der Schicht der Gruppe III-V (102g) definiert ist. An integrated circuit comprising: a substrate (102); an interlayer dielectric, ILD, (104) covering said substrate (102), said ILD layer (104) at least partially defining a trench (108), and wherein the trench (108) extends through the ILD layer (104) from a top surface of the ILD layer (104) to the substrate (102);a conductive pad (106a) overlying the ILD layer (104);a first Passivation layer (110) overlying the ILD layer (104) and the conductive pad (106a), the first passivation layer (110) defining a pad opening overlying the conductive pad (106a) and a second passivation ...

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Processing device and method of hemodynamic analysis for detecting a syndrome

A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining smoothness of the waveform segments; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the waveform segments, and generating a detection result.

Processing device and method of hemodynamic analysis for detecting a particular syndrome

A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining systolic peaks for determining first and second portions of the waveform segments; determining smoothness of the second portions; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the second portions, and generating a detection result.

Semiconductor device

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

半導體裝置與其製造方法

一種半導體裝置，包括了半導體基板、在半導體基板上的第一層、與在第一層中的汲極區域。汲極區域包括：汲極矩形部份，其具有第一端第二端；第一汲極端點部份，其是相鄰於汲極矩形部份，且從汲極矩形部份的第一端開始延伸並遠離汲極區域的中心；第二汲極端點部份，其是相鄰於汲極矩形部份，且從汲極矩形部份的第二端開始延伸並遠離汲極區域的該中心。半導體裝置還包括了第一層中的源極區域，此源極區域不接觸地圍繞汲極區域。第一汲極端點部份與第二汲極端點部份具有和汲極矩形部份相同的摻雜類型與不同的摻雜濃度。

Substrate designed for minimizing waste in singulation

Ultra high voltage semiconductor device with electrostatic discharge capabilities

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

Method and system of wire bonding for use in fabrication of semiconductor package

A method and a system of wire bonding for use in semiconductor package fabrication are proposed. When one wire-bonded substrate unit of a substrate mounted with chips is introduced into a testing region, a next adjacent substrate unit is simultaneously formed with bonding wires in a wire-bonding region. In the testing region, the wire-bonded substrate unit is tested for wire bonding quality. If no wire opening or short occurs, the wire-bonded substrate unit is readily used for subsequent package fabrication. If wire opening or short is detected, a controlling module associated with the testing region generates a control signal to the wire-bonding region for interrupting a wire-bonding process, whereby causes of wire opening or short are overcome, and defective bonding wires are reworked. Therefore, inferiors or malfunction is timely detected, making overall fabrication process more time-effectively implemented; and inferiors are reworked for later usage, thereby significantly reducing fabrication costs.

Semiconductor structures

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Multi-die integrated circuit package structure and method of manufacturing the same

A multi-die IC package structure and a method of manufacturing this multi-die IC package structure are proposed. This multi-die IC package structure is constructed on a lead frame including an inner-lead part having a plurality of inner leads surrounding a cavity in the center thereof, without the forming of a die pad. Next, a stacked multi-die structure is mounted on the inner-lead part of the lead frame, which is formed in such a manner the undermost semiconductor die has its non-circuit surface insulatively attached to the inner-lead part of the lead frame and its circuit surface insulatively attached to the overlying one, and also in such a manner that each of the semiconductor dies other than the undermost one has its non-circuit surface insulatively attached to the circuit surface of the underlying one. By the proposed method, the overall packaging process is significantly less complex than the prior art, thus allowing the manufacture process more cost-effective to carry out.

車用多媒體系統與監視系統

一種車用多媒體系統與監視系統。車用多媒體系統包括影音擷取裝置、傳輸線路以及影音播放裝置。影音擷取裝置包括影像擷取元件、第一射頻模組以及第一連接電路。影音播放裝置包括第二連接電路、第二射頻模組以及顯示器。其中，第一連接電路與第二連接電路皆具有電感與電容。影音擷取裝置透過傳輸線路來傳送射頻影像訊號與電力訊號至影音播放裝置，以使顯示器顯示影像擷取元件所擷取的影像。

Semiconductor package having stacked chip and a method for fabricating

燈罩固定組件

Lead frame base for semiconductor packaging process

Method for identifying defective substrate

Semiconductor device

A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

網路攝影機、通訊方法以及通訊系統

本發明提供一種網路攝影機、通訊方法以及通訊系統。網路攝影機包括影像擷取單元、視訊處理單元以及連線處理單元。影像擷取單元擷取連續的多個影像。視訊處理單元耦接影像擷取單元，根據影像產生第一視訊流以及第二視訊流。連線處理單元耦接視訊處理單元將第一視訊流處理為第一封包流，以及將第二視訊流處理為第二封包流。其中，連線處理單元透過第一無線連結將第一封包流傳送至一區域無線網路單元，以及連線處理單元透過第二無線連結將第二封包流傳送至外部電子裝置。

QFN package and a fabrication method thereof

A QFN package comprising a die pad, which has a first upper surface and a corresponding first lower surface, and at least a loop shaped groove conformal to, and inside the periphery of, the first lower surface of the die pad. A plurality of leads are formed and located along the boundary edges of the die pad. Each lead has a second upper surface and a corresponding second lower surface. A chip has an active surface and a corresponding back surface, and its back surface is adhered on the first upper surface of the die pad. A plurality of bonding pads is formed on the active surface of the chip, and are electrically connected to the leads. A molding compound, which encapsulates the chip, the die pad and the leads, leaves exposed on the first lower surface of the die pad and the second lower surfaces of the leads.

Semiconductor package having stacked chip and a method for fabricating

Attachable/detachable plasma cleaning magazine for loading carriers during semiconductor packaging process

Lead frame base for semiconductor packaging process

Passivierungsstruktur und Verfahren zu ihrer Herstellung

Eine Passivierungsstruktur umfasst eine untere dielektrische Schicht. Die Passivierungsstruktur umfasst weiter eine dotierte dielektrische Schicht über der unteren dielektrischen Schicht. Die dotierte dielektrische Schicht umfasst eine erste dotierte Schicht und eine zweite dotierte Schicht. Die Passivierungsstruktur umfasst weiter eine obere dielektrische Schicht über der dotierten dielektrischen Schicht.

Pyramid-shaped capacitor structure

Solder ball accommodating structure

Semiconductor structures

Attachable/detachable plasma cleaning magazine for loading carriers during semiconductor packaging process

鋼骨營建工作平台

Lamp holder

A lamp holder includes a heat dissipating seat having a compartment. A substrate is mounted in the compartment of the heat dissipating seat. The substrate includes a control circuit and at least one slot. At least one lighting element is mounted in the at least one slot and in electrical connection with the control circuit. The substrate further includes two flexible terminals in electrical connection with the control circuit and the at least one slot. When mounting the lamp holder into a space of a base, the flexible terminals are inserted into two coupling holes in a conductive portion of an inner periphery of the space. The heat dissipating seat is then pressed downward so that the resiliency of the flexible terminals urges the heat dissipating seat into the space of the base, providing easy assembly.

Method and system for detecting location of a segment of a feeding tube inside a patient

A method for detecting a location of a segment of a feeding tube is provided. The feeding tube has a proximal end, a hollow tube body and a distal end, and is placed inside the body of a patient. An audio collecting component is placed on a predetermined part of the patient. The method includes steps of pumping air into the proximal end of the feeding tube, collecting sound to obtain audio data by the audio collecting component, performing audio analysis on the audio data, and determining whether a segment of the hollow tube body is at a part inside the body of the patient that corresponds with the location of the audio collecting component based on result of the audio analysis.

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Solder ball implanting apparatus and retrieving device thereof

Casing of electronic element

Semiconductor arrangement and method of making

A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Fabrication method and carrier of semiconductor packages

Lamp holder

Casing for communication convertor

Solder ball implanting apparatus and retrieving device thereof

Fabrication method and carrier of semiconductor packages

Semiconductor arrangement and method of making

A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

燈罩

【物品用途】;本創作係為一種配合燈具使用以提供照明之燈罩。;【創作特點】;本創作之燈罩包含一罩體及一座體。該罩體為可透光材質，該罩體係近似四邊錐形體，其各側邊均形成向上漸縮之傾斜型態，且各該側邊之間均以適度的圓弧相鄰接，該罩體頂部具有一頂面，該頂面與各側邊之間均設有一斜面以形成兩段式傾斜型態，可藉此簡單創意以突顯該罩體之極簡風格。該座體係對應該罩體之底部形狀，且其底部具有四個半球形凸粒，更突顯出該燈罩整體之特殊造型。