METHOD TO FORM HIGH CAPACITANCE THIN FILM CAPACITORS (TFCS) AS EMBEDDED PASSIVES IN ORGANIC SUBSTRATE PACKAGES

Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. 1. An electronic package , comprising:a package substrate;an organic layer over the package substrate; and a first electrode, wherein the first electrode comprises a seam between a first conductive layer and a second conductive layer;', 'a dielectric layer over the first electrode; and', 'a second electrode over the dielectric layer., 'a capacitor embedded in the organic layer, wherein the capacitor comprises2. The electronic package of claim 1 , wherein the seam is characteristic of diffusion bonding between the first conductive layer and the second conductive layer.3. The electronic package of claim 1 , wherein the dielectric layer is a ceramic material.4. The electronic package of claim 3 , wherein the ceramic material comprises a crystalline microstructure.5. The electronic package of claim 3 , wherein the ceramic material comprises a ceramic oxide.6. The electronic package of claim 5 , herein the ceramic oxide comprises titanium claim 5 , oxygen claim 5 , and one or both of barium and strontium.7. The electronic package of claim 3 , wherein the ceramic material comprises a ferroelectric ceramic.8. The electronic package of claim 1 , wherein the dielectric layer has a capacitance density of 10 nF/mmor greater.9. The electronic package of claim 1 , wherein a thickness of the dielectric layer is between 200 nm and 800 nm.10. The electronic package of claim 1 , further comprising:a barrier layer between the dielectric layer and the first ...

STRUCTURES WITHIN A SUBSTRATE LAYER TO CURE MAGNETIC PASTE

Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures. 1. A package comprising:a substrate having a first side and a second side opposite the first side; andan inductor embedded within the substrate, wherein the inductor is disposed between a first substrate layer adjacent to the first side of the substrate and a second substrate layer adjacent to the second side of the substrate.2. The package of claim 1 , wherein the substrate is a coreless substrate.3. The package of claim 1 , wherein the inductor includes a magnetic core and a copper (Cu) winding inductor structure.4. The package of claim 3 , wherein the magnetic core includes at least one of: a Fe—Co or Fe—Ni based nano ferromagnetic alloy powder claim 3 , or nano flakes that include CoFeO claim 3 , CoNiFe claim 3 , NiFeMo or NiFe.5. The package of claim 3 , wherein the magnetic core is in physical contact with the Cu winding inductor structure.6. The package of claim 1 , wherein the magnetic core comprises two coupled magnetic cores.7. The package of claim 1 , further comprising a die coupled to the first side of the substrate.8. A method for embedding a magnetic inductor in a substrate layer claim 1 , the method comprising:creating a structure within the substrate layer that identifies a defined region within the substrate layer;inserting a magnetic paste into the defined region; andwherein the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.9 ...

CAPACITORS WITH NANOISLANDS ON CONDUCTIVE PLATES

Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique. 1. A device comprising:a first conductive plate having a first side and a second side opposite the first side;a second conductive plate having a first side and a second side opposite the first side, wherein the first side of the first conductive plate faces the first side of the second conductive plate;a first plurality of nanoislands distributed on the first side of the first conductive plate and a second plurality of nanoislands distributed on the first side of the second conductive plate, wherein the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor.2. The device of claim 1 , wherein the nanoislands include a dielectric material.3. The device of claim 1 , further comprising gaps between each of the first plurality and the second plurality of nanoislands claim 1 , wherein the gaps form super-capacitive junctions.4. The device of claim 3 , wherein the gaps between the nanoislands are between 0.5 and 5.0 nm.5. The device of claim 1 , wherein the first plurality or the second plurality of nanoislands include a selected one of silicon nitride (SiN) ...

SUBSTRATE ARCHITECTURE FOR ENHANCED ELECTROSTATIC CHUCKING

The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated ...

CONTROLLED ORGANIC LAYERS TO ENHANCE ADHESION TO ORGANIC DIELECTRICS AND PROCESS FOR FORMING SUCH

An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer. 1. An interconnection structure , comprising:a dielectric layer;an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness; anda Ti layer on the TiC layer.2. The interconnection structure of claim 1 , further comprising a via in the dielectric layer claim 1 , wherein the interfacial TiC layer and the Ti layer are in the via.3. The interconnection structure of claim 1 , wherein the dielectric layer is a photoimageable dielectric (PID).4. The interconnection structure of claim 3 , further comprising a buildup dielectric layer underneath the PID.5. The interconnection structure of claim 1 , further comprising a Cu layer on the Ti layer.6. An interconnection structure claim 1 , comprising:a dielectric layer;an interfacial TiN layer on the dielectric layer, the interfacial TiN layer having a uniform thickness; anda Ti layer on the TiN layer.7. The interconnection structure of claim 6 , further comprising a via in the dielectric layer claim 6 , wherein the interfacial TiC layer and the Ti layer are in the via.8. The interconnection structure of claim 6 , wherein the dielectric layer is a photoimageable dielectric (PID).9. The interconnection structure of claim 8 , further comprising a buildup dielectric layer underneath the PID.10. The interconnection structure of claim 6 , further comprising a Cu layer on the Ti layer.11. A system claim 6 , comprising:one or more storage components; and a dielectric layer;', 'an interfacial TiC layer on the dielectric layer, the TiC layer having a uniform thickness; and', 'a Ti layer on the TiC layer., 'one or more integrated circuit die including one or more interconnection structures, the interconnection structures including12. The system of claim 11 , ...

DESIGN OPTIMIZATION FOR RASTER SCANNING

The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

TWO-AXIS MAGNETIC FIELD SENSOR HAVING REDUCED COMPENSATION ANGLE FOR ZERO OFFSET

A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer. 1. A magnetoresistive thin-film magnetic field sensor , comprising:an antiferromagnetic pinning layer; an amorphous ferromagnetic layer having a thickness in the range of 2 to 15 Angstroms over the pinning layer; and', 'a first crystalline ferromagnetic layer over the amorphous ferromagnetic layer;, 'a pinned layer comprisinga nonmagnetic coupling layer over the pinned layer;a ferromagnetic fixed layer over the nonmagnetic coupling layer;a dielectric tunnel barrier layer over the ferromagnetic fixed layer; anda ferromagnetic sense layer over the dielectric tunnel barrier layer.2. The magnetoresistive thin-film magnetic field sensor of wherein the pinned layer further includes a second crystalline ferromagnetic layer between the amorphous ferromagnetic layer and the pinning layer.3. The magnetoresistive thin-film magnetic field sensor of wherein the second crystalline ferromagnetic layer comprises CoFe claim 2 , where Fe is 10.0-25.0 by atomic weight.4. The magnetoresistive thin-film magnetic field sensor of wherein the second crystalline ferromagnetic layer has a thickness in the range of 2 to 10 Angstroms.5. The magnetoresistive thin-film ...

DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package. 1. A semiconductor package , comprising:a buildup film, wherein one or more metal pads are disposed in the buildup film; anda plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs, wherein the plurality of dual-damascene ZMVs and the trace are disposed in the buildup film and wherein the plurality of dual-damascene ZMVs connect with the one or more metal pads in the buildup film.2. The semiconductor package of claim 1 , wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size.3. The semiconductor package of claim 2 , wherein each of the one or more metal pads has a third size and wherein the third size is substantially equal to or greater than the first size.4. The semiconductor package of claim 1 , wherein a sidewall of one of the plurality of dual-damascene ZMVs and a sidewall of the trace are co-planar with each other.5. A semiconductor package claim 1 , comprising:a buildup film, wherein one or more metal pads are formed in the buildup film;a first photoimageable dielectric (PID) layer on the buildup film;a second PID layer on the first PID layer; anda ...

NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad. 1. An electronic package , comprising: a cavity that passes through the interposer;', 'a through interposer via (TIV); and', 'an interposer pad electrically coupled to the TIV;, 'an interposer, wherein the interposer comprisesa nested component in the cavity, wherein the nested component comprises a component pad; and an intermediate pad; and', 'a bump over the intermediate pad., 'a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect, wherein the first interconnect and the second interconnect each comprise2. The electronic package of claim 1 , further comprising:a polymer layer over and around the interposer and the nested component.3. The electronic package of claim 2 , wherein the intermediate pads are over a surface of the mold layer.4. The electronic package of claim 3 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the mold layer claim 3 , and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the mold layer.5. The electronic package of claim 3 , wherein the intermediate pad of the first ...

GLASS DIELECTRIC LAYER WITH PATTERNING

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

METHOD OF FORMING A PACKAGE SUBSTRATE

The present disclosure is directed to a method providing a substrate core having a glass core layer with top and bottom surfaces and a build-up process performing operations to form a plurality of through-glass vias formed through the glass core layer and a plurality of conductive layers on the top and bottom surfaces of the glass core layer. As an integral part of the build-up process, a defect detection method may be used to detect defects in the glass core layer. The inspection for defects may be performed after selected operations. After one or more defect (e.g., crack) is uncovered, a repair process may be performed to repair the defects in the glass core layer. The repair of a defect may be performed immediately upon detection or after selected operations as a comprehensive repair of a group of defects.

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer. 1. An electronic package , comprising:a mold layer having a first surface and a second surface opposite the first surface;a plurality of first dies embedded in the mold layer, wherein each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer; anda second die embedded in the mold layer, wherein the second die is positioned between the plurality of first dies and the second surface of the mold layer.2. The electronic package of claim 1 , wherein the plurality of first dies are electrically coupled to the second die with first level interconnects (FLI).3. The electronic package of claim 2 , wherein active surfaces of the plurality of first dies are oriented to be facing an active surface of the second die.4. The electronic package of claim 1 , wherein the plurality of first dies comprise dies fabricated at a first process node claim 1 , and wherein the second die is fabricated at a second process node that is less advanced than the first process node.5. The electronic package of claim 1 , further comprising:a plurality of high speed input/out (HSIO) dies embedded in the mold layer.6. The electronic package of claim 5 , wherein the plurality of HSIO dies are electrically coupled to the second die.7. The electronic package of claim 5 , wherein each of the ...

SELECTIVE DEPOSITION OF EMBEDDED THIN-FILM RESISTORS FOR SEMICONDUCTOR PACKAGING

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor. 1. A package substrate , comprising:a dielectric having a cavity, wherein the cavity has a footprint;a resistor embedded in the cavity of the dielectric, wherein the resistor has a plurality of surfaces and a top surface; anda plurality of traces on the resistor, wherein the plurality of surfaces of the resistor are a plurality of activated surfaces.2. The package substrate of claim 1 , wherein the resistor has a plurality of sidewalls.3. The package substrate of claim 2 , wherein the plurality of sidewalls of the resistor are a plurality of activated sidewalls.4. The package substrate of claim 2 , wherein the plurality of sidewalls are tapered.5. The package substrate of claim 1 , wherein the dielectric includes at least one of a plurality of metallization particles and a plurality of metallization ions claim 1 , wherein the resistor includes one or more resistive materials claim 1 , and wherein the one or more resistive materials is selected from the group consisting of nickel-phosphorus (NiP) claim 1 , aluminum- ...

HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

COPPERLESS REGIONS TO CONTROL PLATING GROWTH

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

TECHNIQUES FOR DIE TILING

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

GLASS DIELECTRIC LAYER WITH PATTERNING

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern. 1. A package comprising:a glass layer with a first side and a second side opposite the first side, wherein the glass layer is a dielectric layer;another layer coupled with the first side of the glass layer; anda pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.2. The package of claim 1 , wherein the pattern includes a trace etched in glass or a through-glass via.3. The package of claim 2 , wherein the trace etched in glass is to provide a redistribution layer (RDL).4. The package of claim 3 , wherein the RDL includes a fan out.5. The package of claim 1 , wherein the deposited material includes copper or a copper alloy claim 1 , or wherein the deposited material includes a seed layer.6. The package of wherein the another layer is a selected one of a substrate claim 1 , an adhesive layer claim 1 , or another glass layer.7. The package of claim 1 , wherein the glass layer is a first glass layer claim 1 , and the deposited material is a first deposited material; and a second glass layer with a first side and a second side opposite the first side, wherein the first side of the second glass layer is coupled with the second side of the first glass layer; and', 'a pattern on the second side of the glass layer to receive the second deposited material in at ...

SURFACE FINISHES WITH LOW RBTV FOR FINE AND MIXED BUMP PITCH ARCHITECTURES

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

EMBEDDED PATCH FOR LOCAL MATERIAL PROPERTY MODULATION

Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material. 1. A package substrate , comprising:a substrate comprising a first dielectric material;a first trace embedded in the substrate; anda patch in direct contact with the first trace, wherein the patch comprises a second dielectric material that is different than the first dielectric material.2. The package substrate of claim 1 , wherein the patch is in direct contact with a first surface and a second surface of the first trace claim 1 , wherein the first surface is opposite the second surface.3. The package substrate of claim 2 , wherein the patch is in direct contact with an entire perimeter of the first trace.4. The package substrate of claim 1 , wherein a length of the first trace is substantially equal to a length of the patch.5. The package substrate of claim 1 , further comprising:a second trace over the first trace; anda third trace under the first trace.6. The package substrate of claim 5 , wherein the patch is in direct contact with the second trace and the third trace.7. The package substrate of claim 1 , further comprising:a second trace adjacent to the first trace, wherein the patch surrounds the first trace and the second trace.8. The package substrate of claim 1 , wherein the first dielectric material has a first dielectric constant and the second dielectric material has a second dielectric constant that is lower than the first dielectric constant.9. The package substrate of claim 8 , wherein the second dielectric constant is less than 3.10. The package substrate of claim 1 , wherein the patch locally modifies one or more of a mechanical property claim 1 , ...

NO-REMELT SOLDER ENFORCEMENT JOINT

No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

SANDWICH-MOLDED CORES FOR HIGH-INDUCTANCE ARCHITECTURES

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via. 1. A package substrate , comprising:a first encapsulation layer over a substrate;a second encapsulation layer below the substrate;a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate, wherein the first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and wherein the second interconnect includes a second PTH core, a third via, and a fourth via; anda magnetic portion vertically surrounds the first interconnect, wherein the first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via, and wherein the second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.2. The package substrate of claim 1 , wherein each of the first and second encapsulation layers is a photoimageable mold layer claim 1 , and wherein the first and second interconnects vertically extend from a bottom surface of ...

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die. 1. A die assembly , comprising:a die;one or more die pads on a first surface of the die; anda die attach film on the die, wherein the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.2. The die assembly of claim 1 , further comprising one or more die pads attached to a second surface of the die.3. The die assembly of claim 1 , wherein the one or more openings include one or more channels that contain an underfill material.4. The die assembly of claim 1 , wherein the one or more openings include one or more channels that contain an underfill material that is different from the die attach film material.5. The die assembly of claim 1 , wherein the one or more die pads are through silicon via (TSV) backside die pads.6. The die assembly of claim 1 , wherein the die assembly is on a first package substrate and the one or more die pads are connected to an individual die claim 1 , a first die and a second die claim 1 , a second package substrate or an interposer.7. The die assembly of claim 1 , wherein the die assembly is surrounded by mold.8. A system claim 1 , comprising:one or more storage components; and a die in a die mount space;', 'one or more die pads attached to a first surface of the die; and', 'a die attach film on the die, wherein the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die., 'one or more integrated circuit die including a die assembly that includes9. The system claim 8 , further comprising one or more die pads attached to a second surface of the die.10. The system of claim 8 , wherein the one or more openings ...

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

NESTED INTERPOSER PACKAGE FOR IC CHIPS

SURFACE FINISHES WITH LOW RBTV FOR FINE AND MIXED BUMP PITCH ARCHITECTURES

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV). 1. An electronic package:a package substrate;first conductive pads formed over the package substrate, wherein the first conductive pads have a first surface area;second conductive pads over the package substrate, wherein the second conductive pads have a second surface area that is greater than the first surface area;a solder resist layer over the first conductive pads and the second conductive pads;a plurality of solder resist openings through the solder resist layer, wherein each of the solder resist openings expose one of the first conductive pads or the second conductive pads, wherein the solder resist openings are filled with conductive material, and wherein a top surface of the conductive material is substantially coplanar with a top surface of the solder resist layer; andsolder bumps over the conductive material in the solder resist openings.2. The electronic package of claim 1 , wherein the solder bumps have a low bump thickness variation (BTV).3. The electronic package of claim 2 , wherein the BTV is less than 5 um.4. ...

ENABLING MAGNETIC FILMS IN INDUCTORS INTEGRATED INTO SEMICONDUCTOR PACKAGES

Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure. 1. A semiconductor package , comprising:a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;a raised pad structure on the first build-up layer, the raised pad structure comprising a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other;a magnetic film encapsulating the plurality of inductor features and the raised pad structure in a magnetic film, the magnetic film comprising one or more magnetic fillers, wherein top surfaces of the raised pad structure and the magnetic film are co-planar;an additional layer on the top surfaces of the raised pad structure and the magnetic film; anda via on the top surface of the raised pad structure, the via being formed through the additional layer.2. The semiconductor package of claim 1 , wherein the raised pad structure has a z-height that is ...

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

CARRIER CHUCK AND METHODS OF FORMING AND USING THEREOF

The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer. 1. A microelectronic device package , comprising:a redistribution layer (RDL);an interposer over the RDL;a glass core over the RDL and surrounding the interposer; anda plurality of dies over the interposer, wherein the plurality of dies are communicatively coupled with the interposer.2. The microelectronic device package of claim 1 , further comprising:conductive vias formed through the glass core.3. The microelectronic device package of claim 1 , wherein a thickness of the glass core is substantially the same as the thickness of the interposer.4. The microelectronic device package of claim 1 , wherein the interposer is embedded in a mold layer.5. The microelectronic device package of claim 4 , wherein the plurality of dies are embedded in the mold layer.6. The microelectronic device package of claim 1 , wherein the plurality of dies are communicatively coupled to each other by conductive traces in the interposer.7. The microelectronic device package of claim 1 , wherein the interposer is an active die.8. The microelectronic device package of claim 7 , wherein the active die comprises active devices at a first process node claim 7 , and wherein the plurality of dies comprise active devices at a second process node.9. The microelectronic device package of claim 1 , wherein the interposer is a bridge.10. The microelectronic device package of claim 1 , further comprising a plurality of interposers claim 1 , wherein the plurality of interposers are surrounded by the ...

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad. 1. An electronic package , comprising:an interposer, wherein a cavity passes through the interposer;a nested component in the cavity; and a first bump;', 'a bump pad over the first bump; and', 'a second bump over the bump pad., 'a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect, wherein the first and second interconnects comprise2. The electronic package of claim 1 , wherein the bump pad of the first interconnect is substantially coplanar to the bump pad of the second interconnect.3. The electronic package of claim 1 , wherein the nested component and the interposer are embedded in an underfill layer and a first mold layer.4. The electronic package of claim 3 , wherein the die is embedded in a second mold layer.5. The electronic package of claim 1 , wherein the cavity is entirely within a footprint of the die.6. The electronic package of claim 1 , wherein a first portion of the cavity is within a footprint of the die claim 1 , and wherein a second portion of the cavity is outside of the footprint of the die.7. The electronic package of claim 1 , wherein through component vias extend through the nested component.8. The electronic package of claim 1 , wherein the nested component is a passive component.9. The electronic package of claim 1 , wherein the nested component is an active component.10. The electronic package of claim 1 , ...

GLASS COATING TO MINIMIZE ROUGHNESS INSIDE THROUGH GLASS VIAS

A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

PATCH ACCOMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness. 1. A method of making a multi-die patch , the method comprising:forming a first patterned conductive layer defining multiple contact pads on a first carrier structure;placing a first die on a first plurality of contact pads of the multiple contact pads;placing a second die on a second plurality of contact pads of the multiple contact pads;embedding the first die and the second die in a dielectric disposed on the patterned conductive layer;attaching a second carrier structure to the dielectric on a surface of the dielectric opposite the first carrier;removing the first carrier structure;forming routing traces, the routing traces configured to electrically couple the first and second die with one or more surface die;forming first terminals connected with a first plurality of routing traces of the routing traces, the first terminals exposed at a first side of the dielectric; andforming second terminals connected with a second plurality of routing traces of the routing traces, the second terminals exposed at a second side of the dielectric, the second side opposite the first side.2. The method of claim 1 , wherein a thickness of the first die is different than the thickness of the second die.3. The method of claim 1 , wherein the forming second terminals includes removing the second carrier structure.4. The method of claim 3 , wherein removing the second carrier structure includes laser ablating an adhesive layer of the second carrier structure.5. The method of claim 3 , wherein removing the second carrier structure includes coupling a stiffener to the first side before removing the second carrier structure.6. The method of ...

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

THIN FILM BARRIER SEED MATALLIZATION IN MAGNETIC-PLUGGED THROUGH HOLE INDUCTOR

Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath. 1. An inductor , comprising;a substrate core;a conductive through-hole through the substrate core; anda magnetic sheath around the conductive through hole, wherein the magnetic sheath is separated from the plated through hole by a barrier layer that is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.2. The inductor of claim 1 , wherein the first surface of the magnetic sheath is substantially coplanar with a first surface of the substrate core and wherein the second surface of the magnetic sheath is substantially coplanar with a second surface of the substrate core.3. The inductor of claim 2 , wherein the barrier layer is in contact with and over the first surface of the substrate core and the second surface of the substrate core.4. The inductor of claim 3 , wherein the magnetic sheath is fully embedded claim 3 , wherein an outer surface of the magnetic sheath is in direct contact with the substrate core.5. The inductor of claim 1 , wherein a thickness of the barrier layer is 1 μm or less.6. The inductor of claim 1 , wherein a thickness of the magnetic sheath is 50 μm or greater.7. The inductor of claim 1 , wherein the first surface of the magnetic sheath is not substantially coplanar with a first surface of the substrate core and wherein the second surface of the magnetic sheath is not substantially coplanar with a second surface of the substrate core.8. The inductor of claim 7 , wherein a first film ...

TECHNIQUES FOR DIE TILING

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

PACKAGE ARCHITECTURE WITH TUNABLE MAGNETIC PROPERTIES FOR EMBEDDED DEVICES

Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material. 1. An electronic package , comprising:a package substrate, wherein the package substrate comprises a plurality of dielectric layers; anda plurality of passive components in a first dielectric layer of the plurality of dielectric layers, wherein first passive components of the plurality of passive components each comprise a first magnetic material, and wherein second passive components of the plurality of passive components each comprise a second magnetic material, wherein a composition of the first magnetic material is different than a composition of the second magnetic material.2. The electronic package of claim 1 , wherein the first passive components are included in a first circuitry block claim 1 , and wherein the second passive components are included in a second circuitry block.3. The electronic package of claim 2 , wherein the first circuitry block provides signal filtering claim 2 , RF shielding claim 2 , or power delivery claim 2 , and wherein the second circuitry block provides a different one of signal filtering claim 2 , RF shielding claim 2 , or power delivery.4. The electronic package of claim 2 , wherein the first magnetic material has a first permeability and the second magnetic material has a second ...

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

GLASS CORE PATCH WITH IN SITU FABRICATED FAN-OUT LAYER TO ENABLE DIE TILING APPLICATIONS

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die. 1. An electronic package , comprising: a plurality of first pads on a first surface of the glass substrate;', 'a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface;', 'a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch;, 'a glass substrate, comprisinga bridge substrate over the glass substrate;a first die electrically coupled to first pads and the bridge substrate; anda second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.2. The electronic package of claim 1 , wherein the second pads are part of a fan-out layer patterned directly into the second surface of the glass substrate.3. The electronic package of claim 1 , wherein the first pitch is less than approximately 100 μm and the second pitch is greater than approximately 100 μm ...

HYBRID GLASS CORE FOR WAFER LEVEL AND PANEL LEVEL PACKAGING APPLICATIONS

Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole. 1. A package substrate , comprising:a plurality of glass layers;a plurality of dielectric layers, wherein the glass layers alternate with the dielectric layers;a through-hole through the plurality of glass layers and the plurality of dielectric layers; anda conductive through-hole via in the through-hole.2. The package substrate of claim 1 , wherein the conductive through-hole via is in direct contact with the glass layers.3. The package substrate of claim 1 , wherein the dielectric layers fully embed the glass layers.4. The package substrate of claim 3 , wherein the conductive through-hole via is separated from sidewall surfaces of the glass layers by the dielectric layers.5. The package substrate of claim 1 , wherein a thickness of each of the glass layers is approximately 100 μm or less.6. The package substrate of claim 1 , wherein a thickness of each of the dielectric layers is approximately 100 nm or less.7. The package substrate of claim 1 , wherein a diameter of the through-hole is approximately 100 μm or more.8. The package substrate of claim 1 , wherein an aspect ratio of the glass layer thickness to a through-hole diameter (thickness:diameter) is 1:1 or less.9. The package substrate of claim 1 , wherein the through-hole comprises a plurality of openings stacked over each other claim 1 , wherein each opening is through one of the plurality of glass layers.10. The package substrate of claim 9 , wherein an amount of misalignment between neighboring openings of the plurality of openings is ...

TWO-AXIS MAGNETIC FIELD SENSOR HAVING REDUCED COMPENSATION ANGLE FOR ZERO OFFSET

A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer. 1. A magnetoresistive thin-film magnetic field sensor , comprising:a substrate;an insulating layer over the substrate; a first pinning layer over the insulating layer;', a first amorphous ferromagnetic layer having a thickness in the range of 2 to 15 Angstroms over the first pinning layer; and', 'a first crystalline ferromagnetic layer over the first amorphous ferromagnetic layer;, 'a first pinned layer comprising, 'a first nonmagnetic coupling layer over the first pinned layer;', 'a first ferromagnetic fixed layer over the first nonmagnetic coupling layer;', 'a first dielectric tunnel barrier layer over the first ferromagnetic fixed layer; and', 'a first ferromagnetic sense layer over the first dielectric tunnel barrier layer;, 'a first sensor layer stack over the insulating layer, the first sensor layer stack comprising a second pinning layer over the insulating layer;', a second amorphous ferromagnetic layer having a thickness in the range of 2 to 15 Angstroms over the second pinning layer; and', 'a second crystalline ferromagnetic layer over the second amorphous ferromagnetic layer;, 'a second pinned layer comprising, 'a second ...

MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE

An MRAM bit () includes a free magnetic region (), a fixed magnetic region () comprising an antiferromagnetic material, and a tunneling barrier () comprising a dielectric layer positioned between the free magnetic region () and the fixed magnetic region (). The MRAM bit () avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Husing a combination of high H(uniaxial anisotropy), high H(saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes. 1. An MRAM cell capable of storing data , the MRAM cell comprising:a free magnetic region; a first ferromagnetic layer including a first cobalt alloy,', 'a second ferromagnetic layer, wherein the second ferromagnetic layer includes cobalt,', 'a third ferromagnetic layer, and', the first anti-ferromagnetic coupling layer is disposed between the first and third ferromagnetic layers, and', 'the second ferromagnetic layer is disposed between the first ferromagnetic layer and the first anti-ferromagnetic coupling layer; and, 'a first anti-ferromagnetic coupling layer, wherein], 'a fixed magnetic region consisting essentially of an unpinned, fixed synthetic antiferromagnetic (SAF) magnetic structure, wherein the unpinned, fixed SAF magnetic structure comprisesa dielectric layer disposed between the free magnetic region and the unpinned, fixed SAF magnetic structure.2. The MRAM cell of wherein the first cobalt alloy is a cobalt-iron-boron alloy.3. The MRAM cell of wherein the third ferromagnetic layer includes a cobalt-iron-boron alloy and wherein the concentration of boron in the first ferromagnetic layer is different from the concentration of boron in the third ferromagnetic layer.4. The MRAM cell of wherein the second ferromagnetic layer is a cobalt-iron alloy.5. The MRAM cell of wherein the cobalt-iron-boron alloy of the first ferromagnetic layer includes a boron concentration of greater than 9%.6. The MRAM cell of wherein the first cobalt alloy is a ...

Cavity Generation For Embedded Interconnect Bridges Utilizing Temporary Structures

Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate. 1. A package comprising:a substrate;a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; anda plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge;wherein the interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.2. The package of claim 1 , further comprising two or more dies coupled to the surface of the substrate claim 1 , the two or more dies being connected by the silicon interconnect bridge claim 1 , a first die being coupled to a first set of the plurality of contacts and a second die being coupled with a second set of the plurality of contacts.3. The package of claim 1 , wherein the at least one temporary structure includes sacrificial material.4. The package of claim 3 , wherein the sacrificial material includes a material that decomposes upon the application of a decomposition condition.5. The package of claim 4 , wherein the sacrificial material includes a material that decomposes upon the application of a thermal condition.6. The package of claim 1 , further comprising dielectric material at least partially surrounding the interconnect bridge.7. The package of claim 1 ...

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element. 1. An electronic package for use as an integrated voltage regulator with a microelectronic system , the electronic package comprising:a substrate defining at least one layer having one or more of electrically conductive elements separated by a dielectric material; anda magnetic foil having ferromagnetic alloy ribbons, the magnetic foil embedded within the substrate adjacent to the one or more of electrically conductive elements, wherein the magnetic foil is positioned to interface with and be spaced from the one or more of electrically conductive elements.2. The electronic package of claim 1 , wherein the magnetic foil is positioned within the substrate to have a major surface thereof extend in a first plane that is substantially parallel with a second plane defined by the at least one layer having the one or more of electrically conductive elements.3. The electronic package of claim 1 , wherein the magnetic foil is positioned within the substrate to have major surfaces thereof extend in both a first plane that is substantially parallel with a second plane defined by the at least one layer having the one or more of electrically conductive elements and a third plane that is substantially perpendicular with the second plane.4. The electronic package of claim 1 , wherein the magnetic foil is shaped and positioned in two ...

INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate. 1. A modular semiconductive device , comprising:an at least partially embedded interconnect bridge in an opening in a glass substrate, wherein the glass substrate includes a die side and a land side, and wherein the glass substrate is an inorganic substrate;a dielectric film over the glass substrate, over the interconnect bridge, and in the opening in the glass substrate;a plurality of through-glass vias (TGVs) that communicate from the die side to the land side;a first semiconductive device coupled to the interconnect bridge and to a first TGV of the plurality of TGVs, wherein the first semiconductive device includes substrate bond pads that couple to the first TGV, and interconnect bridge bond pads that couple to the interconnect bridge, wherein the first semiconductive device has an active surface, the active surface facing away from the interconnect bridge; anda subsequent semiconductive device coupled to the interconnect bridge and to a second TGV of the plurality of TGVs, wherein the subsequent semiconductive device includes substrate bond pads that couple to the second TGV, and interconnect bridge bond pads that couple to the interconnect bridge.2. The modular semiconductive device of claim 1 , further including at least one first chiplet coupled to the first semiconductive device claim 1 , wherein the at least one first chiplet is on the first semiconductive device at the active surface.3. The modular semiconductive device of claim 1 , further including:at least one first chiplet coupled to the first semiconductive device, wherein the at least one first chiplet is on the first semiconductive device at the active surface; andat least one subsequent chiplet coupled to the first semiconductive device, wherein the at least one subsequent chiplet is on the ...

Package with passivated interconnects

Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE

An MRAM bit () includes a free magnetic region (), a fixed magnetic region () comprising an antiferromagnetic material, and a tunneling barrier () comprising a dielectric layer positioned between the free magnetic region () and the fixed magnetic region (). The MRAM bit () avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Husing a combination of high H(uniaxial anisotropy), high H(saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes. 1. An MRAM cell comprising:a free magnetic region; a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt,', 'a second layer,', 'a third layer of one or more ferromagnetic materials, and', the first anti-ferromagnetic coupling layer is disposed between the first and third layers, and', 'the second layer is disposed between the first layer and the first anti-ferromagnetic coupling layer; and, 'a first anti-ferromagnetic coupling layer, wherein], 'a fixed magnetic region consisting essentially of an unpinned, fixed synthetic antiferromagnetic (SAF) magnetic structure, wherein the unpinned, fixed SAF magnetic structure comprisesa dielectric layer disposed between the free magnetic region and the unpinned, fixed SAF magnetic structure.2. The MRAM cell of wherein the cobalt of the one or more ferromagnetic materials of the first layer is a cobalt alloy.3. The MRAM cell of wherein the one or more ferromagnetic materials of the third layer includes a cobalt-boron alloy.4. The MRAM cell of wherein the cobalt alloy of the one or more ferromagnetic materials of the first layer is a cobalt-boron alloy and wherein the concentration of boron of the first layer is different from the concentration of boron of the third layer.5. The MRAM cell of wherein the cobalt-boron alloy of the first and/or third layer is a cobalt-iron-boron alloy.6. The MRAM cell of wherein the cobalt alloy of the one or more ...

Via interconnects in substrate packages

Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

METHODS OF MANUFACTURING MAGNETORESISTIVE MTJ STACKS HAVING AN UNPINNED, FIXED SYNTHETIC ANTI-FERROMAGNETIC STRUCTURE

A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer. 1. A magnetoresistive magnetic tunnel junction (MTJ) stack comprising:a free magnetic region having one or more ferromagnetic materials; a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, iron and boron,', 'a multi-layer region including a plurality of layers, wherein each layer of the plurality of layers of the multi-layer region includes one or more ferromagnetic materials, and', 'a layer of anti-ferromagnetic coupling material disposed between the first layer of one or more ferromagnetic materials and the multi-layer region; and, 'a fixed magnetic region consisting essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure, wherein the unpinned, fixed SAF structure comprisesa dielectric layer disposed (i) between the free magnetic region and the fixed magnetic region and (ii) on the first layer of one or more ferromagnetic materials.2. The magnetoresistive magnetic tunnel junction (MTJ) stack of wherein more than one layer of ...

ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration. 1. A composite device assembly comprising:a plurality of dies, each die of the plurality of dies includes a respective array of contacts; one or more embedded multi-die interconnect bridges (EMIB) having associated conductive traces, the one or more EMIB configured to interconnect the plurality of dies; and', 'a plurality of via assemblies; and', a base pad in communication with a conductive trace of the EMIB, the base pad including a first conductive material;', 'a cap in communication with a contact of the first array of contacts, the cap including a solder cap layer including a second conductive material different from the first conductive material, and the cap including an electromigration resistant cap layer, the solder cap layer on the electromigration resistant cap layer, the electromigration resistant cap layer having a third conductive material different from the first and second conductive materials, the electromigration resistant cap layer configured to isolate each of the base pad and the solder cap layer from intermetallic compound growth; and', 'a via between the base pad and the cap, the ...

MOLDED EMBEDDED BRIDGE FOR ENHANCED EMIB APPLICATIONS

Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer. 1. (canceled)2. A device comprising:a substrate; anda bridge embedded in the substrate, the bridge including a plurality of routing layers, each routing layer having a plurality of traces,wherein a first routing layer of the plurality of routing layers has a first silica filler content and a second routing layer of the plurality of routing layers has a second silica filler content, the second silica filler content different than the first silica filler content.3. The device of claim 2 , wherein the first routing layer has a coefficient of thermal expansion different than a coefficient of thermal expansion of the second routing layer.4. The device of claim 2 , wherein a concentration of the first silica filler content and a concentration of the second silica filler content varies linearly.5. The device of claim 2 , wherein a concentration of the first silica filler content and a concentration of the second filler content varies non-linearly.6. The device of claim 2 , wherein the first routing layer is made of a material having the first silica filler content and the second routing layer is made of the material having the second silica filler content.7. The device of claim 2 , further comprising a mold that encapsulates at least a majority of the bridge claim 2 , the mold having a silica filler content that differs from the first and second silica filler contents.8. The device of claim 7 , wherein the mold has a coefficient of thermal expansion that is in between a coefficient of thermal expansion of the substrate and ...

PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLAR AND VIA CONNECTIONS FOR FAN OUT SCALING

Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented. 125-. (canceled)26. An integrated circuit package , comprising:a package substrate having a first face and an opposing second face, wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um, and wherein the package substrate includes a plurality of layers; a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um; and', 'a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via; and, 'a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers at the first face of the package substrate, and wherein the high-density interconnect layer includesa first die, wherein the first die is electrically coupled to an individual pillar of the plurality of pillars on the high-density interconnect layer.27. The integrated circuit package of claim 26 , wherein a diameter of an individual pillar of the plurality of pillars is between 2 um and 20 um.28. The integrated circuit package of claim 26 , wherein a diameter of the via is between 2 um and 10 um.29. The integrated circuit package of claim 26 , further comprising:a ...

RADIO FREQUENCY ANTENNAS AND WAVEGUIDES FOR COMMUNICATION BETWEEN INTEGRATED CIRCUIT DEVICES

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device. 1. An integrated circuit package , comprising:a package substrate;a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices include radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto; anda radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.2. The integrated circuit package of claim 1 , wherein the radio frequency waveguide comprises a plate structure having a recess therein.3. The integrated circuit package of claim 2 , wherein the plate structure extends over each integrated circuit device of the plurality of integrated circuit devices.4. The integrated circuit package of claim 1 , wherein the radio frequency waveguide comprises a pipe structure extending between the first integrated circuit device and the second integrated circuit device.5. The integrated circuit package of claim 1 , wherein the radio ...

ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS

An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer. 1. An electronic assembly , comprising:a base substrate having a first surface and an opposing second surface, wherein the base substrate includes at least one opening defined by at least one sidewall extending from the first surface to the second surface; and a magnetic material layer on the at least one sidewall of the at least one opening of the base substrate;', 'a barrier layer on the magnetic material layer, wherein the barrier layer comprises a nitride material layer;', 'a plating seed layer on the barrier layer; and', 'a conductive fill material abutting the plating seed layer., 'an inductor disposed within the at least one opening, wherein the inductor comprises2. The electronic assembly of claim 1 , wherein the nitride material layer comprises silicon and nitrogen.3. The electronic assembly of claim 1 , wherein the magnetic material layer comprises at least one material selected from the group consisting of iron claim 1 , nickel claim 1 , cobalt claim 1 , and rare-earth metals.4. The electronic assembly of claim 1 , wherein the plating seed layer comprises copper.5. The electronic assembly of claim 1 , wherein the conductive fill material comprises conductive particles dispersed in a resin.6. The electronic assembly of claim 5 , wherein the ...

TWO-AXIS MAGNETIC FIELD SENSOR HAVING REDUCED COMPENSATION ANGLE FOR ZERO OFFSET

A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer. 1. A magnetoresistive thin-film magnetic field sensor disposed on or in a substrate , the magnetoresistive thin-film magnetic field sensor comprising:an insulating layer over the substrate; a pinning layer over the insulating layer, a pinned layer comprising: (i) an amorphous ferromagnetic layer over the pinning layer, wherein the amorphous ferromagnetic layers comprises CoFeB, and (ii) a crystalline ferromagnetic layer over the amorphous ferromagnetic layer,', 'a nonmagnetic coupling layer over the pinned layer, and', 'a ferromagnetic fixed layer over the nonmagnetic coupling layer;', 'a dielectric tunnel barrier layer over the ferromagnetic fixed layer of the reference structure; and', 'a ferromagnetic sense layer over the dielectric tunnel barrier layer; and', 'wherein the first sensor layer stack has a first shape anisotropy defining a first reference direction, and the second sensor stack has a second shape anisotropy defining a second reference direction, wherein the first reference direction is different from the second reference direction., 'a reference structure comprising, 'first and second sensor layer stacks disposed over the ...

HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER

Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls. 1. An integrated circuit package substrate , comprising:a patterned conductive layer;a dielectric bi-layer in contact with the patterned conductive layer, wherein the dielectric bi-layer includes a first dielectric sub-layer and a second dielectric sub-layer; anda conductive via in the dielectric bi-layer, wherein the conductive via extends through the first and second dielectric sub-layers, and wherein a sidewall of the via is substantially vertical.2. The integrated circuit package substrate of claim 1 , wherein the second dielectric sub-layer is more susceptible to etching compared to the first dielectric sub-layer.3. The integrated circuit package substrate of claim 1 , wherein the sidewall of the conductive via is positioned approximately 90-100 degrees to the patterned conductive layer.4. The integrated circuit package substrate of claim 1 , wherein the conductive via has two or more sidewalls and the two or more sidewalls are substantially parallel to each other.5. The integrated circuit ...

ELECTROLESS-CATALYST DOPED-MOLD MATERIALS FOR INTEGRATED-CIRCUIT DIE PACKAGING ARCHITECTURES

Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system. 1. An integrated circuit package substrate , comprising:a doped mold layer including activated catalyst particles that are at a perimeter of a via corridor, and inactive catalyst particles in a mold-material matrix of the doped mold layer;a via-corridor liner of an electrically conductive material that contacts the activated catalyst particles;a via contacting the via-corridor liner and eking out the via corridor; andwherein the via contacts at least one of a bond pad and a trace.2. The integrated circuit package substrate of claim 1 , further including at least two integrated circuit dice claim 1 , one of which coupled to the via claim 1 , and wherein the at least two integrated circuit dice are part of a chipset in a computing system.3. The integrated circuit package substrate of claim 1 , wherein the inactive catalyst particles include palladium-containing particles that exhibit a first oxidative state claim 1 , and wherein the activated catalyst particles include palladium-containing particles that exhibit a different oxidative state from the first oxidative state.4. The integrated circuit package substrate of claim 1 , further including:activated catalyst particles that are at a perimeter of a trace corridor, and the inactive particles in the mold-material matrix;a trace-corridor liner of an electrically conductive material that contacts the activated catalyst particles; anda trace contacting the trace-corridor liner and eking out the trace corridor.5. The integrated circuit package substrate of claim 1 , further including: ...

INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC MATERIAL

Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid. 1. An integrated circuit (IC) package support , comprising: a solenoid,', 'a first portion of a magnetic material in an interior of the solenoid, and', 'a second portion of magnetic material outside the interior of the solenoid., 'an inductor, including2. The IC package support of claim 1 , wherein the solenoid includes a plurality of conductive lines and conductive vias through multiple layers of dielectric material.3. The IC package support of claim 1 , wherein the first portion of the magnetic material is oriented along a longitudinal axis of the solenoid.4. The IC package support of claim 1 , wherein the first portion of the magnetic material has a height that is greater than a height of the solenoid.5. The IC package support of claim 1 , wherein the second portion of the magnetic material is oriented parallel to a longitudinal axis of the solenoid.6. The IC package support of claim 5 , wherein the second portion of the magnetic material has a cylinder shape claim 5 , a planar shape claim 5 , or a C-shaped cross-section.7. The IC package support of claim 1 , wherein the IC package support is coreless.8. The IC package support of claim 1 , wherein the magnetic material includes a magnetic paste.9. The IC package support of claim 1 , wherein the IC package support is a package substrate or an interposer.10. An integrated circuit (IC) package claim 1 , comprising:an IC package support having an inductor embedded therein, wherein the inductor includes a solenoid and a magnetic structure around the solenoid, and the magnetic structure includes multiple portions of magnetic material oriented perpendicular to a ...

HIGH-PERMEABILITY MAGNETIC-DIELECTRIC FILM-BASED INDUCTORS

Various embodiments include, for example, a magnetic-dielectric film-based inductor that can be embedded in an electronic package for use as an integrated voltage-regulator, multiple conductive regions to provide electrical interconnects to the magnetic-dielectric-based inductor from other devices, multiple conductive pillars that are electrically coupled to and formed over at least some of the conductive regions, and a magnetic-dielectric layer formed over at least some of conductive regions and conductive pillars. The magnetic-dielectric layer is formed by a multi-layer formation technique having multiple dielectric-material layers and multiple magnetic-material layers. Each of the magnetic-material layers is interspersed with at least one of the dielectric-material layers. Other devices, apparatuses, and methods are described. 1. A magnetic-dielectric film-based inductor , comprising:a plurality of conductive regions to provide electrical interconnects to the magnetic-dielectric-based inductor from one or more other devices;a plurality of conductive pillars that are electrically coupled to and formed over at least some of the plurality of conductive regions; and a plurality of dielectric-material layers; and', 'a plurality of magnetic-material layers, each of the plurality of magnetic-material layers being interspersed with at least one of the plurality of dielectric-material layers., 'a magnetic-dielectric layer formed over at least some of the plurality of conductive regions and the plurality of conductive pillars, the magnetic-dielectric layer including'}2. The magnetic-dielectric film-based inductor of claim 1 , wherein the magnetic-dielectric layers have a permeability greater than about 5.3. The magnetic-dielectric-based inductor of claim 1 , wherein a thickness of each of the plurality of dielectric-material layers is in a range of about 1 nm to about 20 nm.4. The magnetic-dielectric film-based inductor of claim 1 , wherein a thickness of each of the ...

INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING

According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height. 1. A substrate for an integrated circuit , the substrate comprising:a dielectric layer; anda conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer, the conductive layer comprising:a via having a first end and an opposite second end, wherein the via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end, and the via has a substantially non-tapered profile in the z-direction; anda trace adjacent to the via and having a second height in the z-direction that is different than the first height.2. The substrate of claim 1 , wherein the dielectric layer comprises a dielectric material chosen from an epoxy laminate claim 1 , polytetrafluoroethylene claim 1 , phenolic cotton pater claim 1 , woven glass claim 1 , or mixtures thereof.3. The substrate of claim 1 , wherein the conductive layer comprises copper.4. The substrate of claim 1 , wherein the via has a substantially constant width.5. The substrate of claim 1 , wherein the first height ranges from about 1.5 times to about 4 times greater than the second height.6. The substrate of claim 1 , wherein a width of the via ranges from about 1.5 times to about 4 times greater than a width of the trace.7. A substrate for an integrated circuit claim 1 , the substrate comprising:a dielectric layer; anda metallic ...

Surface finishes for interconnection pads in microelectronic structures

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.

MICROELECTRONIC DEVICE INCLUDING NON-HOMOGENEOUS BUILD-UP DIELECTRIC

Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material. 1. A photoimageable dielectric material , comprising:a first region of photoimageable dielectric material forming a first surface of the photoimageable dielectric material, the first region having a first carbon content;a second region of photoimageable dielectric material forming a second surface of the photoimageable dielectric material, the second region having a second carbon content greater than the first carbon content.2. The photoimageable dielectric material of claim 1 , wherein the first region of the photoimageable dielectric material has a first vertical dimension; and wherein the second region of the photoimageable dielectric material has a second vertical dimension less than the first vertical dimension.3. The photoimageable dielectric material of claim 1 , wherein the first and second regions of photoimageable dielectric material form a bi-layer photoimageable dielectric material.4. The photoimageable dielectric material of claim 2 , wherein the first region of photoimageable dielectric material extends for at least 90% of the distance between the first surface of the photoimageable dielectric material and the second surface of the photoimageable dielectric material.5. The photoimageable dielectric material of ...

MULTI-DIE MICROELECTRONIC DEVICE WITH INTEGRAL HEAT SPREADER

The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device. 1. A microelectronic device , comprising:a thermally conductive base plate having multiple recesses formed therein;multiple semiconductor die structures extending beside one another and within respective recesses in the base plate, the multiple semiconductor die structures mechanically and thermally coupled to the thermally conductive base plate by a thermal interface material within the recesses, wherein the semiconductor die structures include active surfaces, and wherein the active surfaces of the semiconductor die structures face away from the thermally conductive base plate;a molded component surrounding the multiple semiconductor die structures and contacting the thermally conductive base plate; anda redistribution layer formed on the multiple semiconductor die and the molded component, the redistribution layer comprising multiple dielectric layers each containing vias and supporting respective conductive traces, wherein a first dielectric layer of the redistribution layer is formed at least in part on the molded component;wherein at least first and second semiconductor die structures are electrically interconnected with one another through the redistribution layer.2. The microelectronic device of claim 1 , wherein the first semiconductor die structure of the multiple semiconductor die structures comprises a stack of semiconductor die.3. The microelectronic device of claim 1 , wherein each of the first and second semiconductor die ...

INTEGRATED CIRCUIT PACKAGE SUPPORTS

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed. 1. An electronic apparatus , comprising: a first dielectric material having a first surface and an opposing second surface,', 'a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the first surface of the first dielectric material,', 'a second dielectric material, having a first surface and an opposing second surface, on the first dielectric material, and', 'a second conductive via in the second dielectric material, wherein the second conductive via has tapered sidewalls with an angle that is greater than 80 degrees relative to the first surface of the second dielectric material., 'an integrated circuit (IC) package support, including2. The electronic apparatus of claim 1 , wherein the second conductive via has a maximum diameter between 2 microns and 20 microns.3. The IC package support of claim 1 , wherein the IC package support further includes:a material on sidewalls of the second conductive via, wherein the material includes an adhesion promoter material.4. The electronic apparatus of claim 2 , wherein the first conductive via has a maximum diameter between 20 microns and 50 microns.5. The electronic apparatus of claim 1 , wherein the first dielectric material or the second dielectric material includes silica filler particles.6. The electronic apparatus of claim 1 , wherein the second dielectric material is non-photoimageable.7. The electronic apparatus of claim 1 , wherein the IC package support is an interposer or a package substrate.8. An electronic apparatus claim 1 ...

MAGNETORESISTIVE STACKS WITH AN UNPINNED, FIXED SYNTHETIC ANTI-FERROMAGNETIC STRUCTURE AND METHODS OF MANUFACTURING THEREOF

A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer. 120-. (canceled)21. A method of fabricating a magnetoresistive magnetic tunnel junction (MTJ) stack , comprising:forming a free magnetic region having at least one layer of one or more ferromagnetic materials; forming a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt;', 'forming a second layer of one or more ferromagnetic materials;', 'forming an anti-ferromagnetic coupling layer between the first layer and the second layer; and', 'forming a third layer of one or more ferromagnetic materials between the first layer and the anti-ferromagnetic coupling layer; and, 'forming a fixed magnetic region consisting essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure, wherein forming the fixed magnetic region includesforming a dielectric layer between the free magnetic region and the fixed magnetic region.22. The method of claim 21 , wherein the first layer includes an alloy having cobalt claim 21 , iron claim 21 , and boron claim ...

NESTED INTERPOSER WITH THROUGH-SILICON VIA BRIDGE DIE

An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. 1. An electronic package , comprising: an interposer substrate;', 'a cavity that passes into but not through the interposer substrate;', 'a through interposer via (TIV) within the interposer substrate; and', 'an interposer pad electrically coupled to the TIV;, 'an interposer, wherein the interposer comprisesa nested component in the cavity, wherein the nested component comprises a component pad coupled to a through-component via;a core via beneath the nested component, the core via extending from the nested component through the interposer substrate; anda die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.2. The electronic package of claim 1 , wherein the first interconnect and the second interconnect each comprise:an intermediate pad; anda bump over the intermediate pad.3. The electronic package of claim 2 , further comprising:a dielectric layer over and around the interposer and the nested component.4. The electronic package of claim 3 , wherein the intermediate pads are over a surface of the dielectric layer.5. The electronic package of claim 4 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer claim 4 , and wherein the intermediate pad ...

Stretchable embedded electronic package

An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

CORELESS ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS

An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries. 1. An apparatus , comprising:a first high-permeability magnetic ferrite element;a second high-permeability magnetic ferrite element; andan inductor coil between the first high-permeability magnetic ferrite element and the second high-permeability magnetic ferrite element.2. The apparatus of claim 1 , wherein at least one of the first high-permeability magnetic ferrite element and the second high-permeability magnetic ferrite element comprises a nickel/zinc ferrite.3. The apparatus of claim 1 , wherein at least one of the first high-permeability magnetic ferrite element and the second high-permeability magnetic ferrite element comprises a nickel/zinc/cobalt ferrite.4. The apparatus of claim 1 , wherein the inductor coil comprises a first surface claim 1 , an opposing second surface claim 1 , and at least one side extending between the first surface and the second surface claim 1 , wherein a width of the first surface is greater than a width of the second surface.5. The apparatus of claim 1 , further including a frame structure claim 1 , wherein the first high-permeability magnetic ferrite element abuts the frame structure.6. The apparatus of claim 1 , wherein the inductor coil is at least partially embedded in the first high-permeability magnetic ferrite element.7. The apparatus of claim 1 , wherein the inductor coil is substantially encapsulated by the first high-permeability magnetic ferrite element and the second high-permeability magnetic ferrite element.8. An ...

SEMICONDUCTOR PACKAGE HAVING NONSPHERICAL FILLER PARTICLES

Semiconductor packages having nonspherical filler particles are described. In an embodiment, a semiconductor package includes a package substrate having a dielectric layer over an electrical interconnect. The dielectric layer includes nonspherical filler particles in a resin matrix. The nonspherical filler particles have an aspect ratio greater than one. 1. A semiconductor package , comprising:a package substrate including a dielectric layer over an electrical interconnect layer, wherein the dielectric layer includes a plurality of nonspherical filler particles in a resin matrix; anda semiconductor die mounted on the package substrate.2. The semiconductor package of claim 1 , wherein the resin matrix includes an organic resin material claim 1 , and wherein the plurality of nonspherical filler particles include an inorganic material.3. The semiconductor package of claim 2 , wherein each of the plurality of nonspherical filler particles has a respective aspect ratio greater than 1.4. The semiconductor package of claim 3 , wherein the respective aspect ratios are greater than 1.5.5. The semiconductor package of claim 3 , wherein the plurality of nonspherical filler particles are cylindrical.6. The semiconductor package of claim 3 , wherein the plurality of nonspherical filler particles are ellipsoidal.7. The semiconductor package of claim 2 , wherein the dielectric layer includes a top surface claim 2 , wherein the plurality of nonspherical filler particles have respective exposed surfaces at the top surface claim 2 , and wherein the respective exposed surfaces are coplanar with an upper surface of the resin matrix at the top surface.8. The semiconductor package of claim 7 , wherein the respective exposed surfaces have different areal shapes.9. The semiconductor package of claim 7 , wherein each of the plurality of nonspherical filler particles includes a respective longitudinal axis at a respective angle to the respective exposed surface claim 7 , wherein the ...

MOLD MATERIAL FOR DIRECT METALLIZATION

This document discusses, among other things, a microelectronic system including a mold compound having a base layer and a surface layer on the base layer, and a seed layer deposited on the surface layer of the mold compound. The mold compound includes a monomer epoxy resin, a hardener, a filler material, and a polymer interphase material, wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the monomer epoxy resin and hardener alone. 1. A microelectronic system , comprising: an epoxy resin;', 'a hardener;', 'a filler material; and', 'a polymer interphase material; and, 'a mold compound including a base layer and a surface layer on the base layer, the mold compound includinga seed layer deposited on the surface layer of the mold compound,wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the epoxy resin and hardener alone.2. The system of claim 1 , wherein the base layer includes the filler material claim 1 , and the surface layer includes the polymer interphase material.3. The system of claim 1 , wherein the epoxy resin includes a monomer epoxy resin claim 1 ,wherein the hardener includes biphenyl diamine,wherein the filler material includes silica, andwherein the polymer interphase material includes polyetherimide.4. The system of claim 3 , wherein the monomer epoxy resin includes at least one of biphenyl epoxy or epoxy novolac.5. The system of claim 3 , wherein the mold compound includes a silane adhesion promoter.6. The system of claim 1 , wherein the hardener includes an amine hardener or a phenol hardener.7. The system of claim 1 , wherein the base layer has a thickness between 5 and 100 microns claim 1 , and the surface layer has a thickness between 50 nanometers and 5 microns.8. The system of claim 1 , wherein the polymer interphase material forms the surface layer of the mold ...

Stretchable electronic assembly

A stretchable electronic assembly comprising a stretchable body, a plurality of electronic components encapsulated in the stretchable body, at least one meandering conductor connected to at least one electronic component of the plurality of electronic components, at least one hollow pocket formed in the stretchable body, the at least one meandering conductor encapsulated in the stretchable body and the at least one meandering conductor located within the at least one hollow pocket formed in the stretchable body. 1. A stretchable electronic assembly , comprising:a stretchable body;a plurality of electronic components encapsulated in the stretchable body;at least one meandering conductor connected to at least one electronic component of the plurality of electronic components;at least one hollow pocket formed in the stretchable body;the at least one meandering conductor encapsulated in the stretchable body; andthe at least one meandering conductor located within the at least one hollow pocket formed in the stretchable body.2. The stretchable electronic assembly of claim 1 , wherein:the at least one meandering conductor located within the at least one hollow pocket has a length; andat least a portion of the length of the at least one meandering conductor located within the at least one hollow pocket is unsecured in the at least one hollow pocket.3. The stretchable electronic assembly of claim 1 , wherein:the at least one meandering conductor located within the at least one hollow pocket has a length; andat least a portion of the length of the at least one meandering conductor located within the at least one hollow pocket is unsecured from the stretchable body.4. The stretchable electronic assembly of claim 1 , wherein:the at least one hollow pocket is larger than the at least one meandering conductor such that at least a portion of the at least one meandering conductor located within the at least one hollow pocket is spaced from the stretchable body by the hollow pocket ...

PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed. 125-. canceled26. A method of forming a conductive via , the method comprising:forming a die pad over a die in a foundation layer;depositing a seed layer over the die pad and the foundation layer;depositing a first photoresist layer over the seed layer and patterning the first photoresist layer to form a conductive line opening over the die pad;depositing a conductive material into the conductive line opening to form a conductive line;depositing a second photoresist layer over the first photoresist layer and patterning the second photoresist layer to form a via opening over the conductive line;depositing the conductive material into the via opening to form the conductive via, wherein the conductive material only deposits on the portions of the exposed conductive line;removing the second photoresist layer and the first photoresist layer;recessing portions of the exposed seed layer; andexposing a top surface of the conductive via.27. The method of claim 26 , further comprising forming an adhesion layer over the conductive via claim 26 , the die claim 26 , and the foundation layer prior to exposing the top surface ...

DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package. 1. A method of forming a semiconductor package , the method comprising:depositing a first resist layer on a buildup film, wherein one or more metal pads are formed in the buildup film;depositing a second resist layer on the first resist layer;exposing portions of the first and second resist layers using light that passes through a photomask;removing portions of the first and second resist layers to form a plurality of cavities and a plurality of pillars, wherein two of the cavities uncover a top side of the buildup film, wherein one of the cavities uncovers a top side of a pillar formed from the first resist layer, and wherein two of the pillars are formed from the first and second resist layers;removing any remaining portions of the resist layers to reveal top surfaces of the buildup film and the one or more metal pads;plating a conductive material into the cavities to fill the cavities and cover top sides of the buildup film and the one or more metal pads; andpolishing the conductive material such that top sides of the buildup film are co-planar with a top side of the conductive material, wherein the polished conductive material forms a plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs.2. The method ...

THIN FILM PASSIVE DEVICES INTEGRATED IN A PACKAGE SUBSTRATE

An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed. 1. A package substrate comprising:one or more first conductive contacts on a first surface;one or more second conductive contacts on a second surface opposite the first surface;a dielectric layer between the first and the second surfaces; andan embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material.2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. A system comprising:a processor;a communication interface; and an integrated circuit device coupled with one or more first conductive contacts on a first substrate surface;', 'one or more second conductive contacts on a second substrate surface opposite the first substrate surface;', 'a dielectric layer between the first and the second substrate surfaces; and', 'an embedded capacitor on the dielectric layer conductively coupled with the integrated circuit device, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a ...

MOLDED EMBEDDED BRIDGE FOR ENHANCED EMIB APPLICATIONS

Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer. 125-. (canceled)26. An embedded multi-die interconnect bridge (EMIB) substrate comprising:an organic substrate; anda bridge embedded in the organic substrate, the bridge including a plurality of routing layers embedded within the bridge, each routing layer having a plurality of traces, each of the plurality of routing layers having a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.27. The EMIB substrate of claim 26 , wherein the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.28. The EMIB substrate of claim 26 , wherein the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.29. The EMIB substrate of claim 26 , wherein a routing layer of the plurality of routing layers with the lowest CTE is adjacent a die interconnect region of the EMIB substrate.30. The EMIB substrate of claim 26 , further comprising a mold having a CTE higher than a highest CTE of one of the plurality of routing layers claim 26 , the mold encapsulating a portion of the routing layers.31. The EMIB substrate of claim 26 , wherein the variation in CTE for each of the plurality of routing layers results from each of the plurality of routing layers having a different silica filler content.32. The EMIB substrate of claim 26 , wherein the CTE of the plurality of routing layers varies from about 7/° C. to about 25/° C.33. An embedded multi-die interconnect bridge (EMIB) substrate comprising:an organic substratea bridge ...

INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING

According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height. 1. A substrate for an integrated circuit , the substrate comprising:a dielectric layer; and a first region having a first width in an x or y direction and a first height in a z-direction; and', 'a second region having a second width in the x or y direction and a second height in the z-direction,', 'wherein the first height is greater than the second height and the first region has a constant cross-sectional shape in the z-direction., 'a metallic transmission line, comprising2. The substrate of claim 1 , wherein the dielectric layer comprises a dielectric material chosen from an epoxy laminate claim 1 , polytetrafluoroethylene claim 1 , phenolic cotton pater claim 1 , woven glass claim 1 , or mixtures thereof.3. The substrate of claim 2 , wherein the dielectric layer comprises a plurality of individual layers of the dielectric material.4. The substrate of claim 1 , wherein the dielectric layer comprises different dielectric materials.5. The substrate of claim 1 , wherein the individual layers of the dielectric material comprise a same dielectric material.6. The substrate of claim 1 , wherein the metallic transmission line comprises copper.7. The substrate of claim 1 , wherein the constant cross-sectional shape is chosen from a circle claim 1 , an oval claim 1 , a triangle claim 1 , a square claim 1 , a rectangle claim 1 , a pentagon claim 1 , a hexagon claim 1 , a ...

INTEGRATED MAGNETIC INDUCTORS FOR EMBEDDED-MULTI-DIE INTERCONNECT BRIDGE SUBSTRATES

An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device. 1. (canceled)2. The semiconductor package substrate of claim 4 , further including wherein the magnetic material includes a surplus in the recess that insulates the inductor coil.3. The semiconductor package substrate of claim 4 , further including an adhesive dielectric material in the recess that insulates the inductor coil.4. A semiconductor device package claim 4 , comprising:an inductor coil in a semiconductor package substrate;a magnetic material in interstices of the inductor coil;a recess that projects a footprint onto at least a portion of the inductor coil; andan embedded multi-die interconnect bridge (EMIB) die in the recess.5. The semiconductor device package of claim 4 , further including a recess fill material in the recess that contacts the recess and the EMIB die.6. The semiconductor device package of claim 4 , further including wherein the magnetic material contacts the EMIB die with a surplus of the magnetic material claim 4 , between the EMIB die and the inductor coil.7. The semiconductor device package of claim 4 , further including wherein an adhesive dielectric contacts the inductor coil and the EMIB die at a backside of the EMIB die.8. (canceled)9. A semiconductor device package claim 4 , comprising:an inductor coil in a semiconductor package substrate;a magnetic material in interstices of the inductor coil;a recess that projects a footprint onto at least a portion of the inductor coil;wherein the inductor coil is a first inductor coil;a subsequent inductor coil in the semiconductor package substrate;wherein the magnetic material is in interstices of the subsequent inductor coil;wherein the recess projects the footprint onto at least a portion ...

MULTI-LAYERED ADHESION PROMOTION FILMS

Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading. 1. An integrated circuit package comprising:a first structure comprising a conductive material on and/or within a first dielectric material, the first structure having at least one surface; a first portion over the at least one surface of the first structure and comprising a second dielectric material having a first dielectric constant,', 'a second portion over the first portion and comprising a third dielectric material having a second dielectric constant, and', 'a third portion over the second portion and comprising a fourth dielectric material having a third dielectric constant,', 'wherein the first dielectric constant is greater than the second dielectric constant and the second dielectric constant is greater than the third dielectric constant., 'a second structure including'}2. The integrated circuit package of claim 1 , wherein the surface of the first structure has a surface roughness of 100 nm or less.3. The integrated circuit ...

CONDUCTIVE ROUTE PATTERNING FOR ELECTRONIC SUBSTRATES

A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion. 1. A conductive route , comprising:a first route portion, wherein the first route portion has a first surface, an opposing second surface and at least one side surface extending between the first surface and the second surface of the first route portion;an etch stop structure on the first route portion, wherein the etch stop structure has a first surface and an opposing second surface and wherein the second surface of the etch stop structure abuts the first surface of the first route portion;a second route portion on the etch stop layer, wherein the second route portion has a first surface, an opposing second surface and at least one side surface extending between the first surface and the second surface of the second route portion and wherein the second surface of the second route portion abuts the first surface of the etch stop structure; anda passivating layer abutting the at least one side surface of the second route portion.2. The integrated circuit assembly of claim 1 , wherein the first route portion has no passivating layer abutting the at least one side surface thereof.3. The integrated circuit assembly of claim 1 , wherein at least one of the first route portion and the second route portion comprises a metal.4. The integrated circuit assembly of claim 3 , wherein ...

EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING

Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core. 1. A semiconductor patch comprising:a glass core having first and second opposed major surfaces extending in an x-y direction;a conductive via extending from the first major surface to the second major surface substantially in a z-direction;a bridge die embedded in a dielectric material in communication with the conductive via; andan overmold at least partially encasing the glass core.2. The semiconductor patch of claim 1 , wherein the glass core comprises a soda-lime glass claim 1 , borosilicate glass claim 1 , alumino-silicate glass claim 1 , alkali-borosilicate glass claim 1 , aluminoborosilicate glass claim 1 , an alkalialuminosilicate glass claim 1 , or a mixture thereof.3. The semiconductor patch of claim 1 , wherein the glass core comprises a monolithic glass core or a laminate glass core.4. The semiconductor patch of claim 1 , wherein the Coefficient of Thermal Expansion (CTE) of the glass core is in a range of from about 3 to about 12.5. The semiconductor patch of claim 1 , wherein the through via comprises a conducting material.6. A semiconductor package comprising: a glass core having first and second opposed major surfaces extending in an x-y direction;', 'a conductive via extending from the first major surface to the second major surface substantially in a z-direction; and', 'a bridge die in electrical communication with the conductive via;', 'a substrate having third and fourth opposed major surfaces extending in the x-y direction and electronically coupled to ...

SUBSTRATE INTEGRATED WAVEGUIDE

This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor. 120-. (canceled)21. An optical signal transmission system , comprising:a substrate including dielectric material; anda waveguide including a first metal having an outer surface and an inner surface,wherein at least a portion of the outer surface is proximate the dielectric material, wherein the inner surface defines a path, and wherein the waveguide is configured to receive an optical signal at the inner surface and to transmit the optical signal along at least a portion of the path.22. The system of claim 21 , wherein the substrate includes a conductor claim 21 , separate from the waveguide claim 21 , the conductor configured to transmit an electrical signal through the dielectric material.23. The system of claim 22 , wherein the conductor is the same metal as the first metal.24. The system of claim 22 , wherein at least a portion of the conductor is formed in the same process step as at least a portion of the first metal.25. The system of claim 21 , wherein the waveguide is a hollow metal waveguide including an input configured to receive the optical signal claim 21 , a body configured to transmit the optical signal claim 21 , and an ...

MRAM HAVING AN UNPINNED, FIXED SYNTHETIC ANTI-FERROMAGNETIC STRUCTURE

An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer. 1. An MRAM cell comprising:a free magnetic region having at least one layer of one or more ferromagnetic materials; a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt,', 'a multi-layer region including a plurality of layers, wherein each layer of the plurality of layers of the multi-layer region includes one or more ferromagnetic materials, and', 'a layer of anti-ferromagnetic coupling material disposed between the first layer of one or more ferromagnetic materials and the multi-layer region; and, 'a fixed magnetic region consisting essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure, wherein the unpinned, fixed SAF structure comprisesa dielectric layer disposed between the free magnetic region and the fixed magnetic region.2. The MRAM cell of wherein more than one layer of the plurality of layers of the multi-layer region includes cobalt.3. The MRAM cell of wherein more than one layer of the plurality of layers of the multi-layer region includes a cobalt alloy.4. The MRAM cell of ...

PACKAGE SUBSTRATE HAVING COPPER ALLOY SPUTTER SEED LAYER AND HIGH DENSITY INTERCONNECTS

Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer. 125-. (canceled)26. An integrated circuit (IC) package substrate , comprising:a first dielectric layer;a seed layer formed on the first dielectric layer, wherein the seed layer comprises a copper alloy;a patterned conductive layer formed on the seed layer; anda second dielectric layer formed on the first dielectric layer and the patterned conductive layer.27. The IC package substrate of claim 26 , wherein the copper alloy comprises one or more of manganese claim 26 , cobalt claim 26 , ruthenium claim 26 , tungsten claim 26 , or aluminum.28. The IC package substrate of claim 26 , wherein a thickness of the seed layer is less than 0.5 um.29. The IC package substrate of claim 26 , wherein a top surface of the seed layer is roughened during formation.30. The IC package substrate of claim 26 , wherein a top surface of the seed layer is roughened after formation by low ion bombardment.31. The IC package substrate of claim 26 , wherein a line space width is 2/2 um.32. The IC package substrate of claim 26 , wherein a thickness of the second dielectric layer is approximately equal to a width of a conductive trace.33. An integrated circuit (IC) device claim 26 , comprising: a first dielectric layer;', 'a seed layer formed on the first dielectric layer, wherein the seed layer comprises a copper alloy;', 'a patterned conductive layer formed on the seed layer; and', 'a second dielectric layer formed on the first dielectric layer and the patterned conductive ...

PANEL LEVEL PACKAGING FOR MULTI-DIE PRODUCTS INTERCONNECTED WITH VERY HIGH DENSITY (VHD) INTERCONNECT LAYERS

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed. 1. A device , comprising:a first die having a first plurality of die pads;a second die having a second plurality of die pads;a molding layer laterally around the first die and the second die and between the first die and the second die, the molding layer laterally around the first plurality of die pads and the second plurality of die pads, wherein the molding layer has a top surface co-planar with a top surface of the first plurality of die pads and with a top surface of the second plurality of die pads;a plurality of conductive vias directly on and in contact with the first plurality of die pads and the second plurality of die pads; anda plurality of conductive lines directly on and in contact with the top surface of the molding layer.2. The device of claim 1 , wherein the plurality of conductive vias comprise:a seed layer over the first plurality of die pads and the second plurality of die pads, and over the molding layer;a first photoresist layer over the seed layer and the first photoresist layer patterned to form a plurality of conductive line openings over the first plurality of die pads and the second ...

RFIC HAVING COAXIAL INTERCONNECT AND MOLDED LAYER

Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package. 1. An integrated circuit structure , comprising:a die including a die pad on a die face;a redistribution layer over the die, wherein the redistribution layer includes an interconnect extending from the die pad orthogonal to the die face, the interconnect comprising a conductive trace and a conductor, the conductor laterally surrounding the conductive trace, and wherein the die pad is between the die face and the redistribution layer;a molded layer over the redistribution layer, wherein the molded layer includes a molding compound; andan antenna including a first antenna patch electrically coupled to the interconnect, and a second antenna patch mounted on the molded layer.2. The integrated circuit structure of claim 1 , wherein the first antenna patch is mounted on the redistribution layer claim 1 , and wherein the molded layer is between the first antenna patch and the second antenna patch.3. The integrated circuit structure of claim 2 , wherein the first antenna patch is between the redistribution layer and the molded layer.4. The integrated circuit structure of claim 2 , wherein the redistribution layer is between the die and the first antenna patch claim 2 , and wherein the redistribution layer includes a lateral trace to carry an electrical signal between the interconnect and the first antenna patch.5. The integrated circuit structure of claim 1 , wherein the die is embedded in the molded layer.6. The integrated circuit structure of ...

BENDABLE AND STRETCHABLE ELECTRONIC DEVICES AND METHODS

Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials. 125.-. (canceled)26. A method of making a stretchable and bendable apparatus comprising:depositing a first elastomer material on a panel;laminating trace material on the elastomer material;processing the trace material to pattern the trace material into one or more traces and one or more bond pads;attaching a die to the one or more bond pads; anddepositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.27. The method of claim 26 , wherein processing the trace material includes processing the trace material so as to form a trace with a thickness of less than about 500 nanometers.28. The method of claim 27 , further comprising:situating a first trace encapsulation material on the first elastomer material before laminating the trace material on the first elastomer material; andselectively removing portions of the first trace encapsulation material to pattern the first trace encapsulation material.29. The method of claim 28 , further comprising:situating a second trace encapsulation material on the one or more traces; andselectively removing portions of the second trace encapsulation material.30. The method of claim 26 , further comprising:releasing the first elastomer material ...

ELECTRICAL INTERCONNECT BRIDGE

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers. 1. An electrical interconnect bridge to be embedded in a package substrate , comprising:a molded bridge substrate comprising a mold compound material;a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and spaced (FLS) traces; anda via extending through the bridge substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers to route electrical signals between a first electronic component and a second electronic component supported by the package substrate.2. The electrical interconnect bridge of claim 1 , wherein a first routing layer of the plurality of routing layers includes a first mold compound material and a second routing layer of the plurality of routing layers includes a second mold compound material.3. The electrical interconnect bridge of claim 1 , wherein the plurality of routing layers each includes the same mold compound material.4. The electrical interconnect bridge of claim 1 , wherein the mold compound material comprises epoxy phenol claim 1 , epoxy anhydride claim 1 , epoxy amine claim 1 , or a combination thereof.5. The electrical interconnect bridge of claim 1 , wherein the first and second plurality of FLS traces have a maximum width of about 10 μm.6. The electrical interconnect bridge of claim 1 , ...

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES

An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process. 1. An apparatus including a package comprising:the package comprising:solder resist layer;an electrode embedded in a bottom portion of the solder resist layer; anda solder bump extending through the solder resist layer to the electrode, the solder bump including an electroless nickel, electroless palladium, electroless tin (ENEPET) stack.2. The apparatus of claim 1 , wherein the ENEPET stack comprises:a first layer contacting the electrode, wherein the first layer includes a nickel-material;a second layer over the first layer, wherein the second layer includes palladium; anda third layer over the second layer, wherein the third layer includes tin or a tin alloy.3. The apparatus of claim 1 , wherein the package further comprises:a second electrode embedded in a bottom portion of the solder resist layer in parallel with the electrode; anda second solder bump extending through the solder resist layer to the second electrode, the second solder bump including a second ENEPET stack;wherein a pitch between the second ENEPET stack and an adjacent stack is different than a pitch between the ENEPET stack and an adjacent stack.4. The apparatus of claim 3 , wherein the pitch between the ENEPET stack and the adjacent stack is less than 25 μm.5. An apparatus including a package comprising:a first pair of electroless nickel, electroless palladium, electroless tin (ENEPET) stacks formed in a solder resist layer of the package ...

SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE CONTAINING NON-HOMOGENEOUS DIELECTRIC LAYER

Semiconductor packages including package substrates having non-homogeneous dielectric layers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package substrate includes a dielectric layer having a resin-rich region, e.g., a resin-rich sublayer, and a filler-rich region, e.g., a filler-rich sublayer. The sublayers may contain respective mixtures of an organic resin material and an inorganic filler material. The filler-rich sublayer may have a higher density of the inorganic filler material than the resin-rich sublayer. A density of the inorganic filler material may be lesser near a top surface of 0 the dielectric layer in which an electrical interconnect is embedded. The electrical interconnect may have a greater adhesion affinity to the organic resin material than the inorganic filler material, and thus, the electrical interconnect may readily attach to the functionally-graded dielectric layer. 1. A semiconductor package , comprising:a package substrate including a build-up laminate having a dielectric layer, wherein the dielectric layer includes a resin-rich region having a first mixture of an organic resin material and an inorganic filler material, and a filler-rich region having a second mixture of the organic resin material and the inorganic filler material, and wherein the filler-rich region has a higher density of the inorganic filler material than the resin-rich region; anda semiconductor die mounted on the package substrate.2. The semiconductor package of further comprising an electrical interconnect attached to the resin-rich region of the dielectric layer claim 1 , wherein the semiconductor die is electrically connected to the electrical interconnect.3. The semiconductor package of claim 2 , wherein the resin-rich region covers the electrical interconnect.4. The semiconductor package of claim 1 , wherein the filler-rich region is a filler-rich sublayer of the dielectric layer claim 1 , and wherein the ...

FLEXIBLE PACKAGING FOR A WEARABLE ELECTRONIC DEVICE

The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace. 120-. (canceled)21. A stretchable packaging system for a wearable electronic device , comprising:a first electronic component,a second electronic component,a flexible interconnection connecting the first and second electronic components, andan elastomer layer having a variable thickness and at least partially encapsulating the first and second electronic components and the flexible interconnection,wherein a first region of the layer at least partially encapsulates the first electronic component and has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the flexible interconnection, and a third region of the elastomer layer that at least partially encapsulates the second electronic component has a third thickness that is greater than the second thickness.22. The system of claim 21 , and further comprising a third electronic component and a second flexible interconnection between the third electronic component and the second electronic component.23. The system of claim 22 , wherein a fourth region of the elastomer at least partially encapsulates the second flexible inter connection and a fifth region of the elastomer at least partially encapsulates the third electronic component.24. The system of claim 21 , wherein the first thickness ranges from about 1.5 to about 10 times greater than the thickness of the second thickness.25. The system of claim 21 , wherein the thickness of each of the first ...

Electronic assembly that includes void free holes

A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.

METHODS OF FORMING BARRIER STRUCTURES IN HIGH DENSITY PACKAGE SUBSTRATES

Methods/structures of forming package structures are described. Those methods/structures may include forming a first conductive trace adjacent a second conductive trace on a dielectric material of a high density package substrate. A barrier layer is formed on at least one of the first conductive trace or the second conductive trace, wherein the barrier layer comprises a corrosion resistant material, and forming a conductive via on a portion of the barrier layer. 125-. (canceled)26. A microelectronic package structure comprising:a package substrate comprising a dielectric material;a first conductive trace disposed adjacent a second conductive trace, wherein the first and second conductive traces are disposed on the dielectric material;a barrier layer directly on at least one of the first conductive trace or the second conductive trace, wherein the barrier layer comprises a corrosion resistant material; anda conductive via on a portion of the barrier layer.27. The microelectronic package structure of claim 26 , wherein a spacing between the first and second conductive traces is between about 1 micron to about 5 microns.28. The microelectronic package structure of claim 26 , wherein a width of at least one the first or second conductive traces is between about 1 micron to about 5 microns.29. The microelectronic package structure of claim 26 , wherein the barrier layer comprises a material that is more noble than copper.30. The microelectronic package structure of claim 26 , wherein the barrier layer comprises at least one of nickel claim 26 , phosphorus claim 26 , ruthenium claim 26 , cobalt claim 26 , tungsten claim 26 , copper claim 26 , silver claim 26 , platinum claim 26 , palladium claim 26 , gold claim 26 , rhodium or ruthenium or alloys thereof.31. The microelectronic package structure of claim 26 , wherein the barrier layer comprises a thickness of about 20 nm to about 300 nm.32. The microelectronic package structure of claim 26 , wherein the barrier layer ...

STRETCHABLE ELECTRONIC ASSEMBLY

Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body. 120-. (canceled)21. A stretchable electronic assembly , comprising:a stretchable body that includes electronic components;a plurality of meandering conductors that connect the electronic components, wherein the plurality of meandering conductors are exposed from the stretchable body;a plurality of conductive pads that are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors, wherein the plurality of conductive pads are exposed from the stretchable body.22. The stretchable electronic assembly of claim 21 , wherein the stretchable body includes an upper surface and a lower surface claim 21 , wherein the plurality of meandering conductors are exposed from the lower surface of the stretchable body.23. The stretchable electronic assembly of claim 21 , wherein the stretchable body includes an upper surface and a lower surface claim 21 , wherein the plurality of conductive pads are exposed from the lower surface of the stretchable body.24. The stretchable electronic assembly of claim 21 , wherein at least one of the electronic components is an electronic package.25. The stretchable electronic assembly of claim 21 , wherein at least one of ...

Magnetoresistive MTJ Stack having an Unpinned, Fixed Synthetic Anti-Ferromagnetic Structure

A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer. 1. A magnetoresistive magnetic tunnel junction (MTJ) stack comprising:a free magnetic region having one or more ferromagnetic materials; a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, iron and boron,', 'a multi-layer region including a plurality of layers, wherein each layer of the plurality of layers of the multi-layer region includes one or more ferromagnetic materials, and', 'a layer of anti-ferromagnetic coupling material disposed between the first layer of one or more ferromagnetic materials and the multi-layer region; and, 'a fixed magnetic region consisting essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure, wherein the unpinned, fixed SAF structure comprisesa dielectric layer disposed (i) between the free magnetic region and the fixed magnetic region and (ii) on the first layer of one or more ferromagnetic materials.2. The magnetoresistive magnetic tunnel junction (MTJ) stack of wherein more than one layer of ...

MAGNETORESISTIVE STACKS WITH AN UNPINNED, FIXED SYNTHETIC ANTI-FERROMAGNETIC STRUCTURE AND METHODS OF MANUFACTURING THEREOF

A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (1) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may he disposed on the first layer.

TECHNIQUES FOR DIE TILING

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die. 113-. (canceled)14. A heterogeneous-chip package comprising:a first base die;a second base die;a silicon bridge configured to couple terminals of a first side of the first base die with terminals of a first side of the second base die;an organic substrate disposed about the silicon bridge and adjacent the first side of the first and second base dies, the organic substrate configured to provide electrical terminals for coupling the heterogeneous-chip package to a circuit;an advanced node die coupled to electrical connections of a second side of one of the first base die or the second base die; andwherein the heterogeneous-chip package includes a width dimension of greater than 50 mm.15. The heterogeneous-chip package of claim 14 , wherein the first base die is configured to connect second terminals of the first side of the first base die with second terminals of the second side of the first base die.16. The heterogeneous-chip package of claim 14 , wherein the second base die is configured to connect second terminals of the first side of the second base die with second terminals of the second side of the second base die.17. The heterogeneous-chip package of claim 14 , wherein an area of a footprint of the heterogeneous-chip package is larger than 700 mm2 and the advance node die includes 7 nm technology.18. The heterogeneous-chip package of claim 14 , wherein the heterogeneous-chip package includes a length dimension of greater than 50 mm.19. (canceled)20. ...

INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate. 1. A modular semiconductive device , comprising:an at least partially embedded multi-die interconnect bridge (EMIB) in a glass substrate, wherein the glass substrate includes a die side and a land side;a plurality of through-glass vias (TGVs) that communicate from the die side to the land side;a first semiconductive device coupled to the EMIB and to at least one TGV, wherein the first semiconductive device includes substrate bond pads that couple to the at least one TGV, and EMIB bond pads that couple to the EMIB; anda subsequent semiconductive device coupled to the EMIB and to at least one TGV, wherein the subsequent semiconductive device includes substrate bond pads that couple to the at least one TGV, and EMIB bond pads that couple to the EMIB.2. The modular semiconductive device of claim 1 , further including at least one first chiplet coupled to the first semiconductive device claim 1 , wherein the at least one first chiplet is on the first semiconductive device at an active surface.3. The modular semiconductive device of claim 1 , further including:at least one first chiplet coupled to the first semiconductive device, wherein the at least one first chiplet is on the first semiconductive device at an active surface; andat least one subsequent chiplet coupled to the first semiconductive device, wherein the at least one subsequent chiplet is on the first semiconductive device at the active surface.4. The modular semiconductive device of claim 1 , further including:at least one first chiplet coupled to the first semiconductive device, wherein the at least one first chiplet is on the first semiconductive device at an active surface;at least one subsequent chiplet coupled to the first semiconductive device, wherein the at least one subsequent chiplet is on the ...

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES

An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process. 1. An apparatus including a package comprisinga first pair of nickel, palladium, tin (NPT) stacks formed in a solder resist of the package, the first pair of NPT stacks having a first pitch;a second pair of NPT stacks formed in the solder resist of the package having a second pitch, wherein the first pitch is different than the second pitch;a first electrode that extends through a portion of the solder resist and through a first dielectric layer to a second dielectric layer, wherein a first NPT stack of the first pair of NPT stacks contacts the first electrode; anda second electrode that extends through a portion of the solder resist and through the first dielectric layer to an embedded multi-die interconnect bridge (EMIB) configured to provide high-bandwidth connection between a first die and a second die, wherein a second NPT stack of the second pair of NPT stacks contacts the second electrode.2. The apparatus of claim 1 , wherein the second pitch is greater than 100 μm.3. The apparatus of claim 2 , wherein the first pitch is less than 25 μm.4. The apparatus of claim 1 , wherein the first NPT stack is situated in a first trench in the solder resist that includes sidewalls angled outward from a horizontal center of the trench.5. The apparatus of claim 1 , wherein the first NPT stack is situated in a first trench in the solder resist that includes sidewalls perpendicular to a top surface of the solder resist.6. ...

Embedded die microelectronic device with molded component

Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Electrical interconnect bridge

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

MULTI-LAYER MOLDED SUBSTRATE WITH GRADED CTE

This document discusses, among other things, a multi-layer molded substrate having layers with a graded coefficients of thermal expansions (CTEs) to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to top and bottom surfaces of the multi-layer molded substrate, respectively. 120-. (canceled)21. A system , comprising: a first molded layer including a first mold compound having a first coefficient of thermal expansion (CTE); and', 'a second molded layer including a second mold compound having a second CTE lower than the first CTE,', 'a third molded layer including a third mold compound having a third CTE lower than the second CTE,, 'a multi-layer molded substrate, includingwherein the second molded layer is between the first and third molded layers.22. The system of claim 21 , wherein the different first claim 21 , second claim 21 , and third CTEs are configured to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to a bottom surface and a top surface of the multi-layer molded substrate claim 21 , respectively.23. The system of claim 21 , including a first structure attached to a bottom surface of the first molded layer claim 21 , the first structure having a higher CTE than the second and third CTEs; anda second structure attached to a top surface of the third molded layer, the second structure having a lower CTE than the first and second CTEs.24. The system of claim 21 , wherein the first molded layer is configured to closer match a C of a first structure attached to a bottom surface of the first molded layer than the second and third molded layers claim 21 , and the third molded layer is configured to closer match a CTE of a second structure attached to a top surface of the third molded layer than the first and second molded layers.25. The system of claim 24 , including the first and second structures claim 24 , the first structure including a ...

ETCH BARRIER FOR MICROELECTRONIC PACKAGING CONDUCTIVE STRUCTURES

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure. 1. An integrated circuit package comprising:a first layer comprising a dielectric material;a structure comprising a conductive material over the first layer, wherein the structure comprises a surface roughness of 50 nm or less;a second layer over the structure, the second layer compositionally distinct from the first layer; anda third layer over the first layer, the structure, and the second layer, the third layer comprising the dielectric material and compositionally distinct from the second layer.2. The integrated circuit package of claim 1 , wherein the structure includes a first portion having a first width and a second portion having a second width that is wider than the first width.3. The integrated circuit package of claim 2 , wherein the second width of the second portion is 2 μm to 10 μm wider than the first width of the first portion.4. The integrated circuit package of claim 2 , wherein the second portion extends laterally beyond a first side of the first portion by 1 μm to 5 μm claim 2 , and wherein the second portion extends laterally beyond a second side of the first portion by 1 μm to 5 μm.5. The integrated circuit package of claim 1 , wherein the second layer comprises silicon and one or more of nitrogen claim 1 , carbon claim 1 , and oxygen.6. The integrated circuit package of claim 1 , wherein the structure ...

MULTI-LAYER FLEXIBLE/STRETCHABLE ELECTRONIC PACKAGE FOR ADVANCED WEARABLE ELECTRONICS

Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric. 1. A method for making a flexible , wearable circuit , the method comprising:forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace and a first dielectric; andforming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace and a second dielectric.2. The method of claim 1 , wherein forming the first flexible conductor and forming the second flexible conductor includes forming each flexible conductor with a meandering claim 1 , repeating pattern having an amplitude;wherein the flexible wearable circuit is configured to stretch; andwherein a stretch limit of each of the flexible conductors is a function of the amplitude.3. The method of claim 2 , wherein forming the first flexible conductor includes attaching a first resist layer to the substrate claim 2 , the first resist layer defining the meandering path of the first flexible conductor.4. The method of claim 3 , wherein forming the first flexible conductor includes forming the first conductive trace using the meandering path defined by the first resist layer.5. The method of claim 4 , wherein forming the first flexible conductor includes removing the first resist layer.6. The method of claim 5 , wherein the forming the first flexible conductor ...

PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLAR AND VIA CONNECTIONS FOR FAN OUT SCALING

Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented. 125-. (canceled)26. An integrated circuit package , comprising:a high-density interconnect layer having a first side and an opposing second side;a pillar formed on the first side of the high-density interconnect layer;a via formed on the second side of the high-density interconnect layer;a first die; anda package substrate.27. The integrated circuit package of claim 26 , wherein the first die is electrically coupled to the pillar.28. The integrated circuit package of claim 26 , wherein the package substrate is electrically coupled to the via.29. The integrated circuit package of claim 26 , further comprising:a cavity formed on the package substrate.30. The integrated circuit package of claim 29 , further comprising:a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate.31. The integrated circuit package of claim 30 , further comprising:a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die.32. The integrated circuit package of claim 26 , wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer.33. The integrated circuit package of claim 26 , wherein an input/output (I/O) of the package substrate is between 15 and 60 I/O/mm/layer.34. A computing device claim 26 , comprising:a circuit board; and a high ...

TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE

Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces. 1. A method comprising:fabricating a first portion of an inductor coil at a first substrate of an integrated circuit package;fabricating a second portion of the inductor coil in a second substrate, wherein the second substrate is a non-semiconductor substrate; andelectrically and mechanically coupling the integrated circuit package and the first portion of the inductor coil with the second substrate and the second portion of inductor coil.2. The method of claim 1 , wherein fabricating a second portion of the inductor coil in a second substrate includes fabricating a second portion of the inductor coil in a printed circuit board.3. The method of claim 1 , wherein fabricating a second portion of the inductor coil in a second substrate includes fabricating a second portion of the inductor coil in an interposer.4. The method of claim 1 , wherein fabricating a second portion of the inductor coil in a second substrate includes fabricating a second portion of the inductor coil in an interface.5. The method of claim 4 , wherein the interface is a package-to-package interface of a package-on-package device.6. The method of claim 1 , wherein fabricating the first portion of the inductor coil includes coupling a trace of the substrate forming a first portion of a first winding coil to first and second external terminations of the second substrate claim 1 , the trace configured ...

INTEGRATED CIRCUIT PACKAGE SUPPORTS

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed. 1. An electronic apparatus , comprising: a dielectric material, wherein the dielectric material is non-photoimageable, and', 'a conductive via through the dielectric material, wherein the conductive via has a diameter that is less than 20 microns., 'an integrated circuit (IC) package support, including2. The electronic apparatus of claim 1 , wherein the conductive via has tapered sidewalls with an angle that is greater than 85 degrees.3. The IC package support of claim 1 , wherein the IC package support further includes:an adhesion promoter material on sidewalls of the conductive via.4. The electronic apparatus of claim 1 , wherein the conductive via has a diameter between 2 microns and 15 microns.5. The electronic apparatus of claim 1 , wherein the dielectric material includes silica filler particles.6. The electronic apparatus of claim 1 , wherein the IC package support is a package substrate.7. The electronic apparatus of claim 1 , wherein the IC package support is an interposer.8. An electronic apparatus claim 1 , comprising: a first dielectric material having a planarized top surface, wherein the first dielectric material includes first filler particles having a first particle size, and', 'a second dielectric material on the top surface of the first dielectric material, wherein the second dielectric material includes second filler particles having a second particle size, and the second particle size is smaller than the first particle size., 'an integrated circuit (IC) package support, including9. The electronic apparatus of claim 8 , wherein the IC package support further includes:a conductive ...

TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE

Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces. 1. An apparatus comprising:a first die having first plurality of external terminations;a second die having a second plurality of external terminations;a plurality of connectors coupling the first plurality of external terminations to the second plurality of external terminations; andan inductor winding comprising the plurality of connectors.2. The apparatus of claim 1 , wherein an integrated circuit package includes the second die.3. The apparatus of claim 1 , wherein the plurality of connectors includes solder balls.4. The apparatus of claim 1 , including a magnetic material disposed within the inductor winding and disposed between the first die and the second die.5. The apparatus of claim 4 , wherein the plurality of connectors is arranged in two groups and the magnetic material is disposed between the two groups of connectors.6. The apparatus of claim 4 , wherein the magnetic material is mechanically coupled to a surface of the first die claim 4 , the surface directly adjacent the second die.7. The apparatus of claim 4 , wherein the magnetic material is mechanically coupled to a surface of the second die claim 4 , the surface directly adjacent the first die.8. An inductor comprising:a winding; anda core disposed inside the winding; first conductive traces of a first die;', 'second conductive traces of a second die;', 'a plurality of connectors configured to connect the first die with the second die; and', 'wherein each ...

TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE

Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces. 1. An apparatus comprising:a first circuit package having first plurality of external terminations;a second circuit package having a second plurality of external terminations;a plurality of connectors coupling the first plurality of external terminations to the second plurality of external terminations; andan inductor winding comprising the plurality of connectors.2. The apparatus of claim 1 , wherein the first circuit package includes a semiconductor substrate having the first plurality of external terminations.3. The apparatus of claim 1 , wherein the second circuit package include a non-semiconductor interposer.4. The apparatus of claim 1 , including a magnetic material disposed within the inductor winding and disposed between the first circuit package and the second circuit package.5. The apparatus of claim 4 , wherein the plurality of connectors is arranged in two groups and the magnetic material is disposed between the two groups of connectors.6. The apparatus of claim 4 , wherein the first circuit package includes an integrated circuit (IC) package;wherein the second circuit package includes a printed circuit board; andwherein magnetic material is mechanically coupled to a surface of the integrated circuit package, the surface directly adjacent the printed circuit board.7. The apparatus of claim 4 , wherein the first circuit package includes an integrated ...

ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration. 1. A composite device assembly comprising:a plurality of dies, each die of the plurality of dies includes a respective array of contacts; one or more embedded multi-die interconnect bridges (EMIB) having associated conductive traces, the one or more EMIB configured to interconnect the plurality of dies; and', 'a plurality of via assemblies; and, 'a substrate extending from a first substrate end to a second substrate end, the plurality of dies are coupled along the substrate, the substrate includes a base pad in communication with a conductive trace of the EMIB, the base pad includes at least a first conductive material;', 'a cap in communication with a contact of the first array of contacts, the cap includes at least a second conductive material different from the first conductive material; and', 'an electromigration resistant via having a third conductive material different from the first and second conductive materials, the electromigration resistant via is configured to isolate each of the base pad and the cap from intermetallic compound growth., 'each via assembly of the plurality of via assemblies is ...

RFIC HAVING COAXIAL INTERCONNECT AND MOLDED LAYER

Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package. 1. A radio frequency integrated circuit , comprising:a die including a die pad on a die face;a redistribution layer over the die, wherein the redistribution layer includes a coaxial interconnect extending from the die pad orthogonal to the die face;a molded layer over the redistribution layer, wherein the molded layer includes a molding compound; andan antenna including a first antenna patch electrically coupled to the coaxial interconnect, and a second antenna patch mounted on the molded layer.2. The radio frequency integrated circuit of claim 1 , wherein the first antenna patch is mounted on the redistribution layer claim 1 , and wherein the molded layer is between the first antenna patch and the second antenna patch.3. The radio frequency integrated circuit of claim 2 , wherein the first antenna patch is between the redistribution layer and the molded layer.4. The radio frequency integrated circuit of claim 2 , wherein the redistribution layer is between the die and the first antenna patch claim 2 , and wherein the redistribution layer includes a lateral trace to carry an electrical signal between the coaxial interconnect and the first antenna patch.5. The radio frequency integrated circuit of claim 1 , wherein the die is embedded in the molded layer.6. The radio frequency integrated circuit of claim 1 , wherein the coaxial interconnect includes a signal trace extending from the die pad claim 1 , and a shield conductor extending from a ...

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES

An electroless nickel, electroless palladium, electroless tin stack and. associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process. 1. A method to form a solder bump comprising:forming a layer of a second material over a first material at a base of a trench in a solder resist layer, wherein the first material includes nickel and the second material includes palladium;depositing a third material that includes tin on the second material using an electroless deposition process; andforming a solder bump out of the third material using a reflow and deflux process.2. The method of claim 1 , further comprising forming a layer of the first material along the base of the trench in the solder resist layer.3. The method of claim 2 , wherein the first material contacts an electrode.4. The method of claim 3 , further comprising:forming the electrode; andforming the solder resist layer over the electrode.5. The method of claim 2 , wherein forming the layer of the first material along the base of the trench in the solder resist layer includes forming a layer of the first material along sidewalls of the trench in the solder resist layer.6. The method of claim 1 , wherein forming the layer of the second material further comprises forming a layer of the second material over the first material along sidewalls of the trench in the solder resist layer.7. The method of claim 1 , further comprising claim 1 , prior to forming the trench in the solder resist layer claim 1 , etching the solder resist layer to reduce a height of the solder resist layer.8. The method ...

ELECTRONIC SUBSTRATE HAVING AN EMBEDDED ETCH STOP TO CONTROL CAVITY DEPTH IN GLASS LAYERS THEREIN

An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. 1. An apparatus comprising:a first glass layer having a first surface and an opposing second surface;a second glass layer having a first surface and an opposing second surface; andan etch stop layer abutting the first surface of the first glass layer and abutting the first surface of the second glass layer, wherein the first glass layer includes an opening extending from the first surface of the first glass layer at the etch stop layer to the second surface of the first glass layer.2. The apparatus of claim 1 , wherein the etch stop layer comprises a light absorbing material.3. The apparatus of claim 1 , further comprising a bridge disposed with the opening of the first glass layer claim 1 , wherein the bridge is attached to the etch stop layer.4. The apparatus of claim 3 , further including a through-glass conductive via extending through the second glass layer and the etch stop layer claim 3 , wherein the through-glass conductive via is electrically attached to the bridge.5. The apparatus of claim 3 , wherein the bridge includes a through-bridge conductive via.6. The apparatus of claim 3 , wherein the bridge includes ...

MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND MAGNETIC CORE INDUCTORS

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor. 1. A microelectronic assembly , comprising:a glass substrate having a plurality of conductive through-glass vias (TGV); a first conductive TGV at least partially surrounded by a magnetic material; and', 'a second conductive TGV electrically coupled to the first TGV;, 'a magnetic core inductor includinga first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; anda second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.2. The microelectronic assembly of claim 1 , wherein the second conductive TGV of the magnetic core inductor is at least partially surrounded by a magnetic material.3. The microelectronic assembly of claim 1 , wherein the magnetic core inductor has a first surface and an opposing second surface claim 1 , and wherein the second conductive TGV is coupled to the first conductive TGV via a conductive pathway at the first surface of the magnetic core inductor.4. The microelectronic assembly of claim 1 , wherein the magnetic core inductor has a first surface and an opposing second surface claim 1 , and wherein the first surface of the magnetic core inductor is coupled to a package substrate.5. ...

HYBRID CONDUCTIVE VIAS FOR ELECTRONIC SUBSTRATES

An electronic substrate may be fabricated to include a fine pitch dielectric layer having an upper surface, a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer, and at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer. The hybrid conductive via is fabricated such that a portion thereof that extends through the fine pitch dielectric layer is smaller than a portion extending through the coarse pitch dielectric layer, which results in a stepped configuration, wherein a portion of the hybrid conductive via abuts the upper surface of the fine pitch dielectric layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection therebetween. 1. An apparatus comprising:a fine pitch dielectric layer having an upper surface;a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer; andat least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer wherein the hybrid conductive via resides on the upper surface of the fine pitch dielectric layer and wherein the hybrid conductive via comprises a single conductive material.2. The apparatus of claim 1 , wherein the conductive via comprises a fine via portion extending through the fine pitch dielectric layer and a coarse via portion extending through the coarse pitch dielectric layer claim 1 , and wherein an average width of the fine via portion of the conductive via is less than an average width of the coarse via portion of the conductive via.3. The apparatus of claim 2 , wherein the average width of the first portion of the conductive via is between about 10 percent and 15 percent of the average width of the second portion of ...

MICROELECTRONIC ASSEMBLIES HAVING INTEGRATED MAGNETIC CORE INDUCTORS

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor. 1. A microelectronic assembly , comprising:a first die having a first surface and an opposing second surface in a first dielectric layer; a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface of the magnetic core inductor, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and', 'a second conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface of the magnetic core inductor, coupled to the first conductive pillar; and, 'a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor includesa second die having a first surface and an opposing second surface, in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic ...

Methods and apparatus for a synthetic anti-ferromagnet structure with reduced temperature dependence

A synthetic antiferromagnet (SAF) structure includes a first ferromagnetic layer, a first insertion layer, a coupling layer, a second insertion layer, and a second ferromagnetic layer. The insertion layers comprise materials selected such that SAF exhibits reduced temperature dependence of antiferromagnetic coupling strength. The insertion layers may include CoFe or CoFeX alloys. The thickness of the insertion layers is selected such that they do not increase the uniaxial anisotropy or deteriorate any other properties.

In-plane inductors in ic packages

An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.