Wireless electronic puzzle lock

The wireless electronic trick lock is composed of wireless transmitting key and receiving unlocking mechanism. Its wireless transmitting key consists of EPROM, CPU coder, cipher code transmitting circuit and transmitting antenna, and its receiving unlocking mechanism consists of receiving antenna, receiving circuit, mixing demodulator, CPU code detector, EPROM and unlocking controller. The ciphercode can be written in by means of interface which can be connected with computer, so that said invented trick lock possesses the advantages of strong security, low error code rate, small volume and low cost, and has the extensive application range.

P type transversal bilateral diffusion metal oxide semiconductor tube capable of reducing hot carrier effect

The invention discloses a P-type lateral double-diffused metal-oxide transistor which is capable of reducing hot-carrier effect and comprises a P-type semiconductor substrate; an N-type well region is arranged on the P-type semiconductor substrate; a P-type well region and a P-type doped semiconductor area are arranged on the N-type well region; a P-type source area and an N-type contact area arearranged on the P-type well region; a P-type drain area is arranged on the P-type doped semiconductor area; and a field oxide layer, a metal layer, a gate oxide layer, a polysilicon grid and an oxidelayer are arranged on the upper surface of the device. The P-type lateral double-diffused metal-oxide transistor is characterized in that: a lightly-doped shallow P-type area is arranged in the N-type well region and positioned between the P-type well region and the P-type doped semiconductor area and covers a corner which is formed by the gate oxide layer and the P-type doped semiconductor area.

Silicon transverse device on N-type insulator for improving current density and preparation process thereof

The invention relates to a silicon transverse device on an N-type insulator for improving current density, which comprises a semiconductor substrate, wherein a buried oxide layer is arranged on the semiconductor substrate; a P-type epitaxial layer is arranged on the buried oxide layer; an N-type drift region and a P-type well region are arranged on the P-type epitaxial layer; an N-type source region and a P-type contact region are arranged on the surface of the P-type well region; an N-type buffer region and a P-type drain region are arranged on the N-type drift region; a gate oxide is also arranged on the surface of the P-type epitaxial layer; the N-type source region and the P-type contact region are arranged on the surface of the P-type well region; and a field oxide is arranged on theregion on the surface of the N-type drift region outside the P-type drain region. The invention is characterized in that the N-type buffer region of the silicon transverse device on the N-type insulator ...

N-type super-junction transverse double-diffusion metal oxide semiconductor tube

The invention discloses an N-type super-junction transverse double-diffusion metal oxide semiconductor tube, which comprises a P-type substrate, wherein the P-type substrate is provided with a super-junction structure and a P-type body region; the super-junction structure consists of an N-type epitaxial layer and a P-type semiconductor region embedded therein; the P-type body region is provided with an N-type source region, a P-type body contact region and a grid oxide layer; the super-junction structure is provided with an N-type drain region; a first type field oxide layer is arranged abovethe super-junction structure and positioned in a region beyond the N-type drain region; a polycrystalline silicon grid is arranged above the grid oxide layer and extends to the upper part of the first type field oxide layer from the upper part of the grid oxide layer; a second type field oxide layer is arranged above the N-type source region, the P-type body contact region, the N-type drain region, ...

Silicon carbide high pressure N-type metal oxide transistor with floating buried layer and method

The invention discloses a silicon carbide high pressure N-type metal oxide transistor with a floating buried layer, comprising a P-type silicon carbide substrate, on which a P-type epitaxial layer is arranged. The P-type epitaxial layer is internally provided with a source and an N-type drift region; the N-type drift region is internally provided with a drain and a P-type protective ring; the source is provided with a metal lead wire of the source; the drain is provided with a metal lead wires of the source and the drain; a grid oxide layer is arranged above the P-type epitaxial layer between the source and the N-type drift region and connected with the metal lead wire of the source; the surface of the P-type protective ring, the surface of the drain and the surface of the P-type epitaxial layer are provided with field oxide layers; the grid oxide layer is provided with a grid; the metal lead wire of the drain is provided with a metal field pole plate; an N-type floating buried layer is ...

High transient response digital control system and method of switch power supply

The invention discloses a high transient response digital control system and a method of a switch power supply, the control system comprises a sampling module, an AD conversion module, a data processing module, a fuzzy PID module and a DPWM module, the control system is connected with a controlled switch power supply to form a closed-loop system, the sampling module samples output of the switch power supply, sampling output is converted to digital signals through A/D conversion, continuous digital signals enter the data processing module to be digitally filtered and to be compared with a set voltage value, the generated deviation and deviation variance rate are supplied to the fuzzy PID module, a control algorithm is carried out in the fuzzy PID module, an appropriate duty ratio is submitted to the DPWM output module, and PWM signals of a switch control pipe are generated and output, therefore, the switch pipe of the digital power supply can be controlled better to be used for stabilizing ...

Stage background inhibiting infrared focal plane unit circuit

The invention relates to a stage background inhibiting infrared focal plane unit circuit which is characterized by comprising an injection circuit, an integrating capacitor circuit, a background subtracting current circuit and a row selection control circuit, wherein the output end of an infrared detector is connected with the input end of the injection circuit; the output end of the injection circuit is connected with the input end of the integrating capacitor circuit; the output end of the integrating capacitor circuit and the output end of the background subtracting current circuit are connected with the input end of the row selection control circuit; the output end of the row selection control circuit is connected with a following signal processing circuit; the first input end and the second input end of the background subtracting current circuit are respectively connected with bias voltage VB1 and bias voltage VB2; and the charge accumulated on an integrating capacitor by background ...

Composite red mud depositing separating washing method and tank

双栅高压N型金属氧化物半导体管

The double-grid high-voltage N-type MOS transistor contains at least one device unit including P-type substrate, buried N-type re-doped layer on the P-type substrate, N-type epitaxial layer on the buried layer, deep N-type drain connecting layer on the epitaxial layer, N-type source area on the connecting layer, field oxide layer in the passive device area on the epitaxial layer, P-well with N-type source area in the active device area on the epitaxial layer, polisilicon grid, grid oxide layer, field oxide layer, oxide layers, aluminum leads on N-type drain and source areas, longitudinal polysilicon grid inside hole beside the source area and P-well in the active device area of the epitaxial layer and longitudinal grid oxide layer between the longitudinal polysilicon grid and the hole.

Lead acid accumulator charging method and charger thereof

The present invention discloses a lead-acid battery charging method, multiple charging modes are set. In the normal mode, according to battery capacity, charge batteries in multi-stages. The corresponding charger is disclosed which comprising of: high-power switch power supply, switch circuit, impulse charge-discharge circuit, voltage and current detecting circuit, charge mode switch module and micro-processor. Comparing to present technique, the present invention sets multiple charge modes, charges in multi-stages, meets the charge requirement in all different conditions furthest, and benefits for prolonging the service life of lead-acid battery. The pulse charge-discharge circuit of present invention realizes discharge energy circumfluence by capacitance serial-parallel conversion, useshigh inductance converting steep wave pulse to ladder-type pulse, comparing to traditional pulse charge-discharge circuit using big resistance charge and discharge, reduces the energy loss and loss ofrapid ...

Device to realize Pascal's triangle numerical operation

The Pascal's triangle numerical operator is one for realizing N digital decimal frequency division output and with phase compensation and reduced phase tingle. The operator consists of several cascade accumulators, each of which comprises time delayer, complementor and full adder. The input terminal of the time delayer is connected to the output terminal of the forestage accumulator and output terminal connected to the input terminal of the accumulator; and input terminal of accumulator is connected to the output terminal of the complementor, the output terminal of the forestage accumulator and the signal input of the present stage. The time delayer consists of D trigger, the complementor of OR gate and XOR gate, and the full adder of adder circuit.

P type lateral insulated gate bipolar device for reducing hot carrier effect

The invention relates to a P type lateral insulated gate bipolar device for reducing the hot carrier effect, comprising an N type substrate. Buried oxide is arranged on the N type substrate, an N type epitaxial layer is arranged on the buried oxide, a P type well and an N well region are arranged on the N type epitaxial layer, a P type buffer well is arranged on the P type well, an N type positive region is arranged on the P type buffer well, a P type negative region and an N type physical contact region are arranged on the N well region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer arranged on the surface of the device. The P type lateral insulated gate bipolar device for reducing the hot carrier effect is characterized in that N type buried layers are arranged at the lower part of the N well region and on the buried oxide, and the N type buried layers are partially inserted into the N type epitaxial layer to integrally form a reverse L type N region ...

High-voltage N-type transversely double-diffusion metal oxide semiconductor transistor

Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor

The invention relates to a rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor which comprises a cell area, a terminal area and a transition area, wherein the terminal area is arranged at the outermost periphery of a chip; the transition area is positioned between the cell area and the terminal area; the bottoms of the cell area, the transition area and the terminal area (III) are provided with drain electrode metal; a heavy doping n-type silicon substrate is arranged on the drain electrode metal and used as a drain area of the chip; an n-type doping epitaxial layer is arranged on the heavy doping n-type silicon substrate; and a discontinuous p-type doping columnar semiconductor area is arranged in the n-type doping epitaxial layer. The rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor is characterized in that an n-type heavy doping semiconductor area is arranged in a second p-type doping semiconductor area in thetransition ...

High-voltage P-type metal oxide transistor and producing method thereof

Low foaming dispersed rosin size

Novel allocation plan of seed filter shop seed tank and vertical pan filter

The invention discloses a novel configuration proposal for a seed tank and a vertical disk filter in a seed filtering workshop during the production of aluminum oxide. The prior proposal that a plurality of filters correspond to a plurality of seed tanks is improved so as to obtain the novel configuration proposal that a single filter corresponds to a single seed tank, that is, six filters correspond to six seed tanks after the improvement. The novel configuration proposal reduces and even eliminates the phenomena of fed material skip, chute scarring, discharge trolley rail corrosion, difficult discharge and so on. The proposal has the advantages of easy production operation and equipment overhaul and clean workshop environment.

P type SOI lateral double-diffused metal-oxide semiconductor transistor

A laterally double diffused metal oxide semiconductor transistor of a P-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, a P-shaped doped semiconductor drift region is arranged on the buried oxide and an N-shaped well region is arranged above the P-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. A P-shaped source region and an N-shaped contact region are arranged in an N-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the P-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing ...

Measuring method and detecting device for winding voltage of switched reluctance motor

The invention discloses a measuring method and a detecting device for winding voltage of a switched reluctance motor. The method comprises the following steps of: measuring the virtual value of bus voltage through a proportional partial pressure sampling circuit to obtain the virtual value of the winding voltage when the switched reluctance motor is in a dual-pipe conduction working state and a CCC cut dual-pipe working state, and utilizing a forward and inverse voltage polarity detecting circuit of a winding to detect the direction of the winding voltage after the winding voltage passes through a single-pipe current-storing return circuit. The detecting device consists of a proportional partial pressure sampling circuit sequentially connected in series with the forward and inverse voltage polarity detecting circuit of the winding, a single-chip machine CPU and the single-pipe current-storing return circuit, wherein the proportional partial pressure sampling circuit is sequentially connected ...

High voltage N type SOI MOS transistor

A metal oxide semiconductor (MOS) of an N-shaped silicon-on-insulator (SOI) in high voltage comprises a semiconductor substrate. An insulating buried oxide, an N-shaped doped semiconductor area and a P well region are arranged on the semiconductor substrate, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the MOS. The MOS is characterized in that a blocking oxide is arranged on a buried oxide and positioned below the gate oxide, a channel region is formed between the blocking oxide and the gate oxide, a P-shaped inversion layer is arranged in the N-shaped doped semiconductor area and positioned on the lower surface of the field oxide between an N-shaped drain region and an N-shaped source region. Thanks to such a structure, cavities sensed from an interface on which the N-shaped doped semiconductor area and the buried oxide are connected gather on the bottom of the N-shaped doped semiconductor area, thus greatly increasing ...

Method for promoting efficiency of short distance radio work attendance device

Low foaming dispersed rosin size

The rosin size mainly for paper pulp is prepared with low-foaming compound emulsifier, low foaming stabilizer, modified resin and water. It has less foams and good gluing effect and its use can raisepaper quality, improve the operation of papermaking machine and reduce amount of treated circular water.

Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage

The invention relates to a consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage, which comprises a P-type semiconductor substrate, wherein an N-type buried layer, a P-type well region, an N-type well region and an N-type drift region are arranged on the P-type semiconductor substrate; a P-type contact region, an N-type source region and an N-type channelinjection region are arranged near the left side of the surface of the P-type well region; a P-type injection region is arranged in the P-type well region; the left end boundary of the P-type injection region is arranged below the N-type source region; the right end boundary of the P-type injection region is adjacent to the N-type drift region on a drain terminal; and the P-type contact region and a polycrystalline silicon electrode are connected through an interconnection metal cable to be used as a grid. The structure of the invention greatly reduces the threshold voltage of the consumptiontype ...

Power MOS pipe grid drive circuit and method for grid floating and level switching

The invention discloses a power MOS pipe grid drive circuit and method for grid floating and level switching. The drive circuit of the invention includes an upper pipe drive circuit and a lower pipe drive circuit, and is characterized in that the upper pipe drive circuit includes a first resistance, a second resistance, a third resistance and a fourth resistance, a bootstrap capacitance, a second capacitance, a first diode and a second diode, a first PNP type audion and a second PNP type audion, as well as a first NPN type audion; the lower pipe drive circuit includes a fifth resistance, a sixth resistance, a seventh resistance, an eighth resistance and a ninth resistance, a third capacitance and a fourth capacitance, a third diode, a third PNP type audion and a fourth PNP type audion as well as a second NPN type audion. The method can realize to convert grid drive level of upper and lower power MOS pipes, drive lower pipe grid and drive upper pipe grid floating. The invention does not ...

Method for improving stereo crosstalk

The invention provides a method for improving stereo crosstalk. The method adds a phase compensation module in a stereo decoding circuit to reduce the phase error between a pilot signal and a received stereo signal, and improve the stereo crosstalk. The phase compensation module consists of a phase error calculation circuit with a symmetrical internal structure, the circuit works out a compensation factor needed to compensate the phase error, and the decoded stereo signal is compensated by the compensation factor, so that the stereo crosstalk is optimized.

P type lateral insulated gate bipolar device for reducing hot carrier effect

The invention relates to a P type lateral insulated gate bipolar device for reducing the hot carrier effect, comprising an N type substrate. Buried oxide is arranged on the N type substrate, an N type epitaxial layer is arranged on the buried oxide, a P type well and an N well region are arranged on the N type epitaxial layer, a P type buffer well is arranged on the P type well, an N type positive region is arranged on the P type buffer well, a P type negative region and an N type physical contact region are arranged on the N well region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer arranged on the surface of the device. The P type lateral insulated gate bipolar device for reducing the hot carrier effect is characterized in that N type buried layers are arranged at the lower part of the N well region and on the buried oxide, and the N type buried layers are partially inserted into the N type epitaxial layer to integrally form a reverse L type Nregion ...

Synthetic apparatus of anti-flashover and protection for low-voltage three phase asynchronous motor

Disclosed is an anti-interference and comprehensive protection device for a low voltage three-phase asynchronous motor, which can realize the restarting of the low voltage three-phase asynchronous motor when the motor is shut down by the fluctuation of the low voltage power network, thereby solves the problem that the product line of industry manufacture enterprise can be shut down abnormally by the power-shaking. The invention is composed of the follows: 1, a processor, 2, a clock chip, 3, a battery, 4, a voltage comparator circuit, 5, a monitor circuit of a contactor, 6, a control circuit of a relay 7, a second control loop, 8, a switching power supply, and 9, a wire connection terminal. The invention can restart the motor when the power is switched on after the motor is shut down due to the power-shaking of the power network, can distinguish two different failures of power-shaking and long-time under-voltage, and can judge whether the motor is working before power-shaking. The anti-interference ...

Infrared focal plane read-out circuit unit circuit

The invention discloses a unit circuit of an infrared focal plane reading-out circuit, which is characterized in that the unit circuit comprises an integral capacitor selection unit, an integral/reset control unit, an input amplifier, a sampling keeping unit and a source following unit. The unit circuit utilizes the reset of the integral/reset control unit to provide constant infrared detector bias voltage inside the unit circuit, without requirement of external bias voltage; most transistors adopt P-typed MOS pipes, thus effectively reducing the noise of the unit circuit; a differential amplifier is replaced by a single-step amplifier, the power loss of the unit circuit is reduced, and the unit area is saved; two capacitor values are designed to be selected, thus meeting the requirement of different background conditions; the integral time can be suitably selected according to the current of different detectors.

Open window reading circuit of focal plane

The invention discloses a windowing read-out circuit of a focal plane. The invention is characterized in that the windowing read-out circuit comprises a data register, a line address selection circuit, a line window size control circuit, a column address selection circuit and a column window size control circuit. The invention has the advantages that the windowing read-out circuit of the focal plane of the invention can realize the opening of window arbitrarily, can read out from an assigned pixel, and can control the window size, the start address and the read-out order. The invention can output with a full pixel, can keep a big viewing field, and can perform windowing read-out by arbitrarily assigning one region in a picture, thereby greatly improving the output speed of a picture, and the invention can be used for read-out circuits of the focal plane of each wave band, such as a read-out circuit of an infrared focal plane, a read-out circuit of a CMOS picture sensor, a read-out circuit ...

Data multi-channel and clockwise/anticlockwise output control circuit

The invention discloses a data multi-route and consequent/inverse output control circuit which is characterized in that the output control circuit comprises a basic continuity signal generation circuit, a middle signal generation circuit, an output routes selection circuit and an output port circuit. By the arrangement of the basic continuity signal generation circuit, the middle signal generation circuit, the output routes selection circuit and the output port circuit, the setting of a receiving routes selection signal, a beginning bus selection signal and a consequent/inverse output control signal and a series of treatment, the data multi-route and consequent/inverse output control circuit of the invention can not only realize the output by a single route, double routes and four routes with the optional output routes, but also can specify an output beginning array and realize the consequent or inverse output of data, thus meeting the requirements for use under various working circumstances ...

Preparation method for optical anode of dye sensitization solar battery

The invention discloses a preparation method used for a dye sensitive solar battery photo-anode, comprising the steps as follows: preparation of TiO2 nanometer crystal slurry, preparation of TiO2 light scattering layer slurry and coating the TiO2 nanometer crystal slurry and the TiO2 light scattering layer slurry on an FTO electrode so as to prepare the dye sensitive solar battery photo-anode by sintering process. By adopting the method of the invention, the raw material is easily to be gained, the reaction temperature is low; more particularly, the PEG20000 and 2-ethylhexanol are used for preparing the TiO2 nanometer crystal slurry, thus greatly reducing the cost and improving the energy conversion efficiency simultaneously.

Clock switching circuit

The invention discloses a clock commutation circuit without burr, which is characterized by the following: comprising data selector, multistage three grades synchronous circuit, time delay circuit and gate controlling circuit; switching the imputing clock signal with the data selector; generating the clock signal with burr; synchronizing the three grades synchronous circuit and the outputting signal of the data selector; excluding the outputting signal of the first grade synchronous circuit and the third synchronous circuit in the gate controlling circuit; masking the burr of clock signal switching; delaying time for the clock signal with the time delay circuit; avoiding simultaneous roll-over of the clock signal edge and the electrical level of the synchronous circuit outputting; generating new burr. This invention can be used to the system with multipath clock signal.

Silicon carbide high pressure P-type metal oxide transistor with floating buried layer and method

The invention discloses a silicon carbide high pressure P-type metal oxide transistor with a floating buried layer, comprising an N-type silicon carbide substrate, on which an N-type epitaxial layer is arranged. The N-type epitaxial layer is internally provided with a source and a P-type drift region; the P-type drift region is internally provided with a drain and an N-type protective ring; the source is provided with a metal lead wire of the source; the drain is provided with the metal lead wire of the source and the drain; a grid oxide layer is arranged above the N-type epitaxial layer disposed between the source and the P-shaped drift region, and connected with the metal lead wire of the source; the surface of the N-type protective ring, the surface of the drain and the surface of the N-type epitaxial layer are provided with field oxide layers; the grid oxide layer is provided with a grid; the metal lead wire of the drain is provided with a metal field pole plate; a P-type floatingburied ...

Built-in type double-frequency mobile communication telephone antenna

Lateral double-diffused metallic oxide metallic oxide of silicon on N-type insulator

A lateral double-diffused metallic oxide metallic oxide of silicon on N-type insulator, including a substrate provided with a buried oxide layer that has a N-type doped semiconductor region, a P-well and a N-type drain region are disposed on the N-type doped semiconductor region, the P-well is provided with a N-type source region and a P-type contact region, surface of the P-well is provided with a gate oxide layer that extending to the N-type doped semiconductor region, the N-type source region on the P-well surface, the P-type contact region and regions outside the gate oxide layer, and regions outside the N-type drain region on surface of the N-type doped semiconductor region is provided with a field oxide layer, surface of the gate oxide layer is provided with a polysilicon gate that extending to surface of the field oxide layer, surface of the field oxide layer, the P-type contact region, N-type source region, the polysilicon gate and the N-type drain region are provided with oxide ...

Linearity high dynamic range infrared reading circuit

The invention relates to a linearity high dynamic range infrared reading circuit which comprises a unit circuit, a column readout stage, an output buffer stage, a time sequence generating circuit, a line option circuit and a row option circuit. The linearity high dynamic range infrared reading circuit is characterized in that the unit circuit includes an integral control unit used for controllingintegral time of the unit circuit, a reset control unit used for controlling integral capacity restoration in the unit circuit, an integral capacity optional unit used for selecting the integral capacity of the unit circuit, an optional integral capacity control signal generating unit and a transmission unit. In the integral process, the invention can automatically select the integral capacity, so that smaller integral capacity is adopted under the condition of less photocurrent, and larger integral capacity is adopted under the condition of more photocurrent. Therefore, the invention can reduce ...

Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time

The invention discloses a single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time, comprising a master pulse-width modulation signal generation circuit (1), a slave pulse-width modulation signal generation circuit (2) and an output enabling circuit (3), wherein the input ends of the master pulse-width modulation signal generation circuit (1) and the slave pulse-width modulation signal generation circuit (2) are connected with single-input dual-output pulse-width modulation signals (PWM_in); and the output ends of the master pulse-width modulation signal generation circuit (1) and the slave pulse-width modulation signal generation circuit (2) are respectively connected with the input end of the output enabling circuit (3). The single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time has easy implementation, good reliability and extremely low cost.

Low power dissipation CMOS type high-voltage drive circuit

The low power consumption CMOS high voltage drive circuit relates to a high voltage drive circuit used in outputting the drive. Between the output terminal of the level transformation stage and the input terminal of the high voltage output stage, there is an output buffer stage, which is composed of a high voltage PMOS tube and a high voltage NMOS tube. The source of the high voltage PMOS tube connects with the power supply and its gate electrode as the input terminal of the output buffer unit at the same stage connects with the output terminal of the output buffer unit at the upper stage. The source of the high NMOS tube connects with the ground and its gate electrode acts as the receiving terminal of the NO.3i sequence signal. The high voltage PMOS tube connects with the NMOS tube and they act as the output terminal of the output buffer unit at the same stage and connect with the input terminal of the output buffer unit at the lower stage. The input terminal of the output buffer unit ...

Isolated high-light load efficiency low-output voltage high-current switch power source

The invention discloses an isolated high-light load efficiency low-output voltage high-current switch power source which comprises an active clamping primary switching circuit (1), an insulating transformer (2), a synchronous rectification circuit (3), an output filter circuit (5), an output sample circuit (6), an error magnification isolation circuit (7), a pulse width modulation control circuit(10), an auxiliary follow current pipe (4), a load sensing circuit (8) and an isolation driver circuit (9). The invention greatly lowers the light load power consumption of the switching converter, and has the advantages of simple structure, low cost and high reliability.

Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor

The invention relates to a rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor which comprises a cell area, a terminal area and a transition area, wherein the terminal area is arranged at the outermost periphery of a chip; the transition area is positioned between the cell area and the terminal area; the bottoms of the cell area, the transition area and the terminal area (III) are provided with drain electrode metal; a heavy doping n-type silicon substrate is arranged on the drain electrode metal and used as a drain area of the chip; an n-type doping epitaxial layer is arranged on the heavy doping n-type silicon substrate; and a discontinuous p-type doping columnar semiconductor area is arranged in the n-type doping epitaxial layer. The rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor is characterized in that an n-type heavy doping semiconductor area is arranged in a second p-type doping semiconductor area in the transition ...

Lateral double-diffused metallic oxide metallic oxide of silicon on P-type insulator

A lateral double-diffused metallic oxide metallic oxide of silicon on P-type insulator, including a substrate provided with a buried oxide layer that has a P-type doped semiconductor region, a N-well and a P-type drain region are disposed on the P-type doped semiconductor region, the N-well is provided with a P-type source region and a N-type contact region, surface of the P-well is provided with a gate oxide layer that extending from the N-well to the P-type doped semiconductor region, the P-type source region on the N-well surface, the N-type contact region and regions outside the gate oxide layer, and regions outside the P-type drain region on surface of the P-type doped semiconductor region is provided with a field oxide layer, surface of the gate oxide layer is provided with a polysilicon gate that extending to surface of the field oxide layer, surface of the field oxide layer, the N-type contact region, P-type source region, the polysilicon gate and the P-type drain region are provided ...

Automatic layout method for storage sub-system internal storage of embedded microprocessor

Metal oxide semiconductor phase locked loop circuit

Storage control circuit with multiple-passage instruction pre-fetching function

The invention discloses a memory controlling circuit with multiple passage order pre-fetching function, which is characterized by the following: comprising two order pre-fetching buffer (L1, L2), SDRAM/DRAM logic controlled circuit, bus interface, address code converter, address comparator, SDRAM/DRAM read-write control circuit, slice out SDRAM/DRAM memory bank and so on; adopting ping-pong procedure to work with the two passage order pre-fetching buffer; reading the order in the slice out SDRAM/DRAM memory bank; filling the order pre-fetching buffer; removing the waiting time of CAS; adopting two groups of order pre-fetching buffer; decreasing the waiting time; adopting page non-hit punishing controlled circuit; decreasing precharge time.

Built-in protetive N-type high-voltage MOS transistors

An N-type high-voltage MOS transistor with built-in protection is composed of P-type substrate, source, P-type contact hole, field oxide layer, drain, polycrystal grid, grid oxide layer under polycrystal grid, the oxide layer on said contact hole, source, polycrystal grid, field oxide layer and drain, leading-out aluminium wires, N-type impurity area and P-type protecting trap in said impurity area under field oxide for higher breakdown voltage.

Voltage controlled oscillator

Angle-shaped regulating valve

The invention discloses an angle-shaped regulating valve. A middle interlayer is arranged in a valve body; an upper valve cavity is formed above the middle interlayer; a lower valve body is formed below the middle interlayer; the middle interlayer is provided with a guide sleeve; a valve core component capable of moving up and down relative to the guide sleeve is inserted into the guide sleeve; and the upper and lower valve cavity are communicated with each other by a through hole on the middle interlayer. The middle interlayer is embedded with the guide sleeve, so that the guide sleeve is close to a valve core; and a valve core handle is thickened, and guiding length is prolonged, so guiding rigidity is enhanced greatly, and valve core vibration is prevented.

双栅高压P型金属氧化物半导体管

The double-grid high-voltage P-type MOS transistor contains at least one device unit including N-type substrate, buried P-type re-doped layer on the substrate, P-type epitaxial layer on the buried layer, deep P-type drain connecting layer on the epitaxial layer, P-type source area on the connecting layer, field oxide layer in the passive device area on the epitaxial layer, N-well with P-type source area in the active device area on the epitaxial layer, polisilicon grid, grid oxide layer, field oxide layer, oxide layers, aluminum leads on P-type drain and source areas, longitudinal polysilicon grid inside hole beside the source area and N-well in the active device area of the epitaxial layer and longitudinal grid oxide layer between the longitudinal polysilicon grid and the hole.

High voltage P type SOI MOS transistor

A high voltage P type silicon-on-insulator metal oxide semiconductor pipe comprises a semiconductor substrate. An insulator buried oxide layer, a P type doped semiconductor area and an N well area are arranged on the semiconductor substrate, while a field oxide layer, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the device. The metal oxide semiconductor pipe is characterized in that a barrier oxide layer is arranged on a buried oxide layer and is positioned below the gate oxide; a channel area is formed between the barrier oxide layer and gate oxide; an N type inversion layer is arranged in the P type doped semiconductor area and is positioned on the lower surface of the field oxide layer between a P type drain area and a P type source area. With such a structure, electrons induced on an interface where the P type doped semiconductor area is connected with the buried oxide layer gather on the bottom of the P type doped semiconductor area ...

Silicon N-type semiconductor combined device on insulator for improving current density

The invention relates to a silicon N-type semiconductor combined device on an insulator for improving current density. The silicon N-type semiconductor combined device comprises a P-type substrate, wherein the P-type substrate is provided with a buried oxygen layer; the buried oxygen layer is provided with a P-type epitaxial layer, and the P-type epitaxial layer is divided into a region I and a region II; the region I is an insulated gate bipolar device region and comprises an N-type drift region, a P-type deep trap, a N-type buffer trap, a P-type drain region, an N-type source region and a P-type body contact region; a silicon face is correspondingly provided with a field oxide and a gate oxide, and the gate oxide is provided with a polysilicon gate; and the region II is a high-voltage triode region and comprises an N-type triode drift region, an N-type triode buffer trap, a P-type emitter region and an N-type base region. The silicon N-type semiconductor combined device is characterized ...

Generation method of spread spectrum clock dither signal

The invention discloses a generation method of a spread spectrum clock dither signal, comprising the following steps of: modulating the control voltage VL of a low-frequency signal to generate a low-frequency triangular wave VSAW1 through a first oscillator and modulating the control voltage VH of a high-frequency signal to generate a high-frequency triangular wave VSAW2 through a second oscillator; and generating a dither frequency CLK (Clock) signal by the low-frequency triangular wave VSAW1 and the control voltage VH of the high-frequency signal through the oscillators, or generating the dither CLK signal by the low-frequency triangular wave VSAW1 and the high-frequency triangular wave VSAW2 through a modulation module. In the invention, the two oscillators can be the same and the circuit is simple, thereby saving the cost.

Built-in protective N-type high-voltage MOS transistor

Silicon-on-insulator integrated great-current P-type combined semiconductor device

The invention relates to a silicon-on-insulator integrated great-current P-type combined semiconductor device, comprising an N-type substrate, an oxide-buried layer arranged on the N-type substrate and an N-type epitaxial layer arranged on the oxide-buried layer. The N-type epitaxial layer is divided into a region (I) and a region (II), wherein the region (I) comprises a P-type drift region, an N-type deep well, a P-type buffer well, an N-type drain region, a P-type source region and an N-type body contact region, wherein a silicon surface is provided with a field oxide layer and a gate oxide layer, the gate oxide layer is provided with a polysilicon gate; the region (II) comprises a P-type transistor drift region, an N-type deep well, a P-type triode buffer well, an N-type emitter region, a P-type base region, a P-type source region and an N-type body contact region, a silicon surface is provided with a field oxide layer and a gate oxide layer, and the gate oxide layer is provided with ...

P-type super-junction transverse double-diffusion metal oxide semiconductor tube

The invention discloses a P-type super-junction transverse double-diffusion metal oxide semiconductor tube, which comprises an N-type substrate, wherein the N-type substrate is provided with a super-junction structure and an N-type body region; the super-junction structure consists of a P-type epitaxial layer and an N-type semiconductor region embedded therein; the N-type body region is provided with a P-type source region, an N-type body contact region and a grid oxide layer; the super-junction structure is provided with a P-type drain region; a first type field oxide layer is arranged above the super-junction structure and positioned in a region beyond the P-type drain region; a polycrystalline silicon grid is arranged above the grid oxide layer and extends to the upper part of the first type field oxide layer from the upper part of the grid oxide layer; a second type field oxide layer is arranged above the P-type source region, the N-type body contact region, the P-type drain region, ...

Depletion type MOS tube steady voltage source

A depletion-type MOSFET stable voltage source is characterized in that the circuit is provided with a depletion-type N-MOSFET, a depletion-type P-MOSFET, a first positive temperature coefficient voltage generation circuit for generating a positive temperature coefficient voltage related to the threshold voltage of the depletion-type N-MOSFET, and a second positive temperature coefficient voltage generation circuit for generating a positive temperature coefficient voltage related to the threshold voltage of the depletion-type P-MOSFET; the two voltage values with positive temperature coefficient generated by the first and second positive temperature coefficient voltage generation circuits are is subtracted from each other to obtain a low-temperature drift stable voltage source through a stable voltage source generation circuit.

P-type super-junction laterally double diffused metal oxide semiconductor

The invention discloses a P-type super-junction laterally double diffused metal oxide semiconductor, comprising an N-type substrate. A super-junction structure and an N-type body region are arranged on the N-type substrate; the super-junction structure consists of a P-type region and an N-type region which are alternately distributed and are connected to the direction of the source region and the drain region; a P-type source region, an N-type body contact region and a gate oxide layer are arranged above the N-type body region; a P-type drain region is arranged above the super-junction structure; a first type field oxide layer is arranged at the region out of the P-type drain region and above the super-junction structure; a polysilicon gate is arranged above the gate oxide layer; a second type field oxide layer is arranged over the P-type source region, the N-type body contact region, the P-type drain region, the polysilicon gate and the first type field oxide layer; and metal lead wires ...

Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time

The invention discloses a single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time, comprising a master pulse-width modulation signal generation circuit (1), a slave pulse-width modulation signal generation circuit (2) and an output enabling circuit (3), wherein the input ends of the master pulse-width modulation signal generation circuit (1) and the slave pulse-width modulation signal generation circuit (2) are connected with single-input dual-output pulse-width modulation signals (PWM_in); and the output ends of the master pulse-width modulation signal generation circuit (1) and the slave pulse-width modulation signal generation circuit (2) are respectively connected with the input end of the output enabling circuit (3). The single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time has easy implementation, good reliability and extremely low cost.

Multi-channel and high-accuracy data acquisition unit

The invention discloses a multi-passage and high precision data collector, belonging to data collectors. The data collector comprises a data collection module, a power module, a micro processor module, a stimulation measure module and a signal selection module, wherein, the signal selection module comprises a passage selection circuit, a current selection circuit, a bus and a function selection circuit, and the stimulation measure module comprises an amplification circuit, an A/D conversion circuit, an external reference source circuit and an optical coupling isolation circuit. The data collector has high system automation and intelligence and the precision as high as one thousand which is higher than the current industrial standard; also the testing function is widely universal and the collection passage is various.

Inbuilt miicromicro farad stage capacitance intermittent microcurrent second-level time delay circuit

The invention discloses an inbuilt miicromicro farad stage capacitance intermittent microcurrent second-level time delay circuit, which is provided with a mirror image current source, a switching tube, a capacitance charging circuit, a burst pulse generating circuit and an output circuit, wherein the output end of the mirror image current source and the output end of the burst pulse generating circuit are respectively connected with two input ends of the switching tube; the output end of the switching tube is connected with the input end of the capacitance charging circuit; the output end of the capacitance charging circuit is connected with the input end of the output circuit; and the output end of the output circuit is connected with a subsequent signal processing circuit. When a mirror image source produces microcurrent to charge the capacitance by the switching tube, a burst pulse signal controls the switching on and off of the switching tube to realize the intermittent charging to ...

Multi-channel agricultural measuring device based on MCU

The invention relates to a multi-channel agricultural measuring device based on an MCU (Microprogrammed Control Unit), comprising a controller, a temperature and humidity sensor group, a first sensor group, a second sensor group and a liquid crystal display module, wherein the temperature and humidity sensor group is connected with the input end of the controller for supplying the temperature and humidity information of the ground surface, the atmosphere and leaf layers for the controller; the first sensor group is connected with the input end of the controller for supplying carbon dioxide concentration, soil temperature, soil moisture content and illumination information for the controller; the second sensor group is connected with the input end of the controller for supplying canopy temperature and canopy wind speed for the controller; and the liquid crystal display module is connected with the output end of the controller for displaying the received information of the controller. In ...

Method for improving balance of power-driven hanging basket working platform and electrical system

The invention discloses a method for improving balance of power-driven hanging basket working platform and an electrical system. The method comprise: comparing the given signal with the current detection and position detection signals fed back during running of left and right switched reluctance motors by a first reluctance motor controller and a second reluctance motor controller; sending the exact control information combined by the first reluctance motor controller and the second reluctance motor controller to the left and right switched reluctance motors to eliminate difference between the two motors so as to realize synchronization of the two motors. The electrical system comprises left and right hanging basket hoisting machines with the same structures, the first reluctance motor controller, the second reluctance motor controller, an ascending switch BTA, a descending switch FTA and a stop switch QA. The invention is characterized by exact synchronization, stable running, accurate ...

Signal peak-to-average ratio reduction method for orthogonal frequency division multiplexing (OFDM) system

The invention discloses a signal peak-to-average ratio reduction method for an orthogonal frequency division multiplexing (OFDM) system. A peak-to-average ratio is reduced by combining a constellation extension method and null sub-carriers. Regulation is performed on data sub-carriers according to constellation extension rules. Frequency domain filtering is performed on the null sub-carriers. In the method, amplitude-prelimited signal noises are processed to generate a peak cancellation vector in ways of regulating data on the data sub-carriers according to the constellation extension rules, performing a frequency domain filtering operation on the null sub-carriers, reserving noises of a null sub-carrier part and zero-setting the noises of a data sub-carrier part to completely transfer the noises to areas of the null sub-carriers and constellation extension without influencing judgment in a constellation diagram of a receiver to further reduce the peak-to-average ratio of a signal. By the ...

N type transversal bilateral diffusion metal oxide semiconductor tube capable of reducing hot carrier effect

The invention discloses an N-type lateral double-diffused metal-oxide transistor which can reduce the hot-carrier effect and comprises an N-type semiconductor substrate; a P-type well region is arranged on the N-type semiconductor substrate; an N-type well region and an N-type doped semiconductor area are arranged on the P-type well region; an N-type source area and a P-type contact area are arranged on the N-type well region; an N-type drain area is arranged on the N-type doped semiconductor area; a field oxide layer, a metal layer, a gate oxide layer, a polysilicon grid and an oxide layer are arranged on the upper surfaces of the devices. The N-type lateral double-diffused metal-oxide transistor is characterized in that: a lightly-doped shallow N-type area is arranged in the P-type wellregion and positioned between the N-type well region and the N-type doped semiconductor area and covers a corner which is formed by the gate oxide layer and the N-type doped semiconductor area.

CMOS power factor correction control circuit for electronic ballast

The invention discloses a CMOS power factor correction control circuit for an electronic ballast, which comprises an electromagnetic interference filter circuit which is used for receiving an input alternating current voltage, a rectifier bridge which is used for converting the alternating current voltage into a pulsating direct current voltage, a booster circuit and a load, wherein an alternating current power supply is input into the rectifier bridge after passing through the electromagnetic interference filter circuit; the rectifier bridge converts the input alternating current into the pulsating direct current to input the pulsating direct current into the booster circuit; and the pulsating direct current is boosted into the high-voltage direct current to be output to the load. The CMOS power factor correction control circuit for the electronic ballast is characterized in that a control circuit, which controls the on and off of a switching power valve in the booster circuit to allow ...

Self-excited oscillation type high power LED constant-current driving circuit

The invention provides a self-oscillation type high power LED constant-current drive circuit with low cost, high reliability and stability and high drive efficiency, the circuit comprises a rectifier and filter circuit, a switching circuit, a steady voltage constant current output circuit, a transformer, a self-oscillation type pulse width modulation signals generating circuit and a current feedback obstruction circuit, wherein the rectifier and filter circuit accesses commercial power into rectification, changes the commercial power into direct current, and then outputs commercial power to the switching circuit to switch in a self-oscillation type with high frequency, then high frequency voltage of the steady voltage constant current output circuit is transformed into direct voltage through the transformer to drive the LED, simultaneously sampling current signals produces jam signals through the current feedback obstruction circuit to control the switching circuit to work, the circuit ...

Isolated high-light load efficiency low-output voltage high-current switch power source

The invention discloses an isolated high-light load efficiency low-output voltage high-current switch power source which comprises an active clamping primary switching circuit (1), an insulating transformer (2), a synchronous rectification circuit (3), an output filter circuit (5), an output sample circuit (6), an error magnification isolation circuit (7), a pulse width modulation control circuit (10), an auxiliary follow current pipe (4), a load sensing circuit (8) and an isolation driver circuit (9). The invention greatly lowers the light load power consumption of the switching converter, and has the advantages of simple structure, low cost and high reliability.

Self-made mobile phone rechargeable card and method for associating rechargeable card password with product information

The invention relates to an enterprise independently made mobile phone rechargeable card. A making enterprise can retrieve, analyze and judge a rechargeable card password. The enterprise packs the rechargeable card together with the own products; after buying a product and opening the pack of the product, a user can obtain the rechargeable card; after the user sends a recharging short message to a server of the enterprise according to the operating instruction on the card, the server immediately processes a user request to complete the recharging and automatically replies a short message and feeds the product information packed together with the card back to the user for the user to verify authenticity simultaneously; and the server also stores and accumulates a recharging record of the mobile phone number of the user to facilitate customer marketing and market analysis. The method comprises the following main steps of: (1) generating the rechargeable card password and storing the rechargeable ...

高压N型横向双扩散金属氧化物半导体管

The high-voltage N-type transverse double-diffusion MOS transistor consists of source, drain, grid, field oxide, grid oxide and oxide layer. The grid oxide is on the source, drain and field oxide layer; and the grid is located between the grid oxide and the oxide layer. There are aluminum leads set on the grid, the source and the drain; P-type well set below the source; the source; the P-type well, the drain and the field oxide set on P-type substrate; and field plate connected to the source. The present invention introduces field plate connected to the source connected to ground to obtain low level. The lower the voltage on the field plate, the larger the depletion region formed on the surface of silicon owing to the action of the field plate, the higher the effect of weakening the surface electric field peak and the higher the puncture voltage.

Preparation process of upper silicon and deep silicon trench isolation structure for insulator

The invention provides a preparation process of an upper silicon and deep silicon trench isolation structure for an insulator, comprising the following steps: a. setting an embedded oxidation layer on a semiconductor substrate, setting N-type top monocrystalline silicon on the embedded oxidation layer, generating a surface oxidation layer on the N-type top monocrystalline silicon, coating photoresist on the surface of the surface oxidation layer, and etching a window with the same size as a deep silicon trench on the photoresist; b. corroding the naked surface oxidation layer and exposing theN-type top monocrystalline silicon to be etched; c. taking the surface oxidation layer as a masking layer for etching the N-type top monocrystalline silicon, and etching the deep silicon trench with the aspect ratio of 7:1.2-7:3 by a anisotropic plasma dry etching process; and completely corroding the surface oxidation layer and corroding the embedded oxidation layer so that the moving depth of the ...

Method for reducing drive chip high voltage drive power consumption and the circuit

Storage control circuit with multiple-passage instruction pre-fetching function

Silicon carbide high pressure N-type metal oxide transistor with floating buried layer and method

The invention discloses a silicon carbide high pressure N-type metal oxide transistor with a floating buried layer, comprising a P-type silicon carbide substrate, on which a P-type epitaxial layer is arranged. The P-type epitaxial layer is internally provided with a source and an N-type drift region; the N-type drift region is internally provided with a drain and a P-type protective ring; the source is provided with a metal lead wire of the source; the drain is provided with a metal lead wires of the source and the drain; a grid oxide layer is arranged above the P-type epitaxial layer betweenthe source and the N-type drift region and connected with the metal lead wire of the source; the surface of the P-type protective ring, the surface of the drain and the surface of the P-type epitaxial layer are provided with field oxide layers; the grid oxide layer is provided with a grid; the metal lead wire of the drain is provided with a metal field pole plate; an N-type floating buried layer is ...

高压P型金属氧化物半导体管

The high-voltage P-type MOS transistor consists of sourece, drain, grid, field oxide, grid oxide and oxide layer. The grid oxide is on the source, drain and field oxide layer with N-type epitaxial contact hole; and the grid is located between the grid oxide and the oxide layer. There are aluminum leads set on the grid, the source and the drain; P-type drift regions set below the field oxide and the drain; the source and the P-type drift regions set on P-type substrate; and field plate connected to the source. The present invention introduces field plate connected to the source to obtain power source level, or high level. The higher the voltage on the field plate, the larger the depletion region formed on the surface of silicon owing to the action of the field plate, the higher the effect of weakening the surface electric field peak and the higher the puncture voltage.

Capacitor bootstrap drive circuit and method of switched reluctance motor

The invention discloses a capacitor bootstrap drive circuit of a switched reluctance motor, consisting of an upper switching tube drive circuit and a lower switching tube drive circuit. The upper switching tube drive circuit consists of a first charging circuit, a first discharging circuit and a bootstrap capacitance circuit, and the lower switching tube drive circuit consists of a second charging circuit and a second discharging circuit. The invention also discloses a drive method using the drive circuit. By charging a bootstrap capacitor to the drive power supply voltage only when a lower switching tube is turned on and turning on an upper switching tube with the voltage of the bootstrap capacitor, the method avoids the problem that the motor works abnormally since the upper switching tube has a deficient grid voltage due to the voltage raising of a terminal b and is failed to be turned on when a phase winding of the motor is turned on. With the bootstrap drive circuit constituted by ...

A high voltage N-type MOS transistor and the corresponding manufacturing method

The invention discloses a high-voltage N-type metal oxide semiconductor, including a P-type substrate, a P-well drift region and an N-type drift region are arranged on the P-type substrate, a P-type contact hole, an N-type source and a field oxide layer are arranged on the P-well, an N-type drain and the filed oxide layer are arranged on the N-type drift region; the invention is characterized in that the thickness a grid oxide layer part which is positioned above the P-well is smaller than the grid oxide layer part which is positioned above the N-type drift region and a thin grid oxide layer and a thick thin grid oxide layer are respectively formed accordingly, a P-type impurity injection region is arranged in the P-well, and the P-type impurity injection region is positioned below the thin grid oxide layer. The invention further discloses a preparation method of the high-voltage N-type metal oxide semiconductor. The invention has the advantages that the invention can greatly reduce the ...

Inductive current induction circuit

The invention relates to an inductive current induction circuit, which is provided with a switching tube circuit, an inductive current generating circuit and an inductive voltage generating circuit, wherein the output end of the switching tube circuit is connected with the inductive current generating circuit of which the output end is connected with the inductive voltage generating circuit; the output end of the inductive voltage generating circuit outputs the inductive voltage; and the switching tube circuit, the inductive current generating circuit and the inductive voltage generating circuit are provided with the same common power supply input end and the same common input control signal. The inductive current induction circuit utilizes the principle that a PMOS tube in a linear area is approximately equivalent to a resistance, adopts a current mirror to reproduce the current, reduces the inductive current in proportion to induce the inductive current, converts the current and the voltage ...

N type SOI lateral double-diffused metal-oxide semiconductor transistor

A laterally double diffused metal oxide semiconductor transistor of an N-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, an N-shaped doped semiconductor drift region is arranged on the buried oxide and a P-shaped well region is arranged above the N-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. An N-shaped source region and a P-shaped contact region are arranged in a P-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the N-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing ...

Method for realizing shadow stack memory on picture and circuit thereof

The invention discloses a method and a circuit of realizing on-chip shadow stack memory which relate to a stack operation method inside a microprocessor and a storage circuit. The invention comprises an on-chip shadow stack memory, a configuration register, a chip selection circuit, an address compare circuit, an address decoding circuit, a storage controller, an attached memory and so on. By using a dynamic configuration method, the invention maps the data of a stack segment unit which is accessed with high frequency in the attached memory onto the on-chip shadow stack memory and accesses the on-chip shadow stack memory when the microprocessor is conducting the stack operation. Therefore, the problem that a memory page is deleted because of the stack accessing is avoided and the unnecessary page switching time is reduced. At the same time, by using the on-chip shadow stack memory, the storage power consumption is reduced; the running speed of the microprocessor is accelerated, thus leading ...

Heating and thermal insulation exsolution method for aluminum oxide high-pressure exsolution section

The invention discloses a heating and insulating method for the high pressure digestion workshop section of alumina. The invention is characterized in that mineral slurry is heated by steam level by level in an autoclave (1) with a heating tube bundle inside; heat insulation and dissolution of the mineral slurry is done in a heat insulation dwelling tank (2) without heating tube bundle; eighty percent to eighty five percent of the total amount of new steam needed is added to the autoclave (1) from the first level to the fifth level; disolution reaction is done in advance to ensure that the mineral slurry reaches disolution temperature in the autoclave (1) from the first level to the fifth level before entering the heat insulation dwelling tank (2). Compared with the prior art, the heatingand insulating method for the high pressure digestion workshop section of alumina has the advantages of more reasonable distribution of the new steam quantity, more effective rinsing of the autoclavewith ...

Multi electric potential field plate lateral high voltage N type MOS transistor

Disclosed relates to multi electric potential field electrode plate high-pressured N-typed metal oxide semiconductor of high-voltaged component, comprising N-typed substrate, P-typed epitaxial layer, source and drain, multi- silicon polycrystal, field oxide layer and oxide layer, silicon polycrystal field electrode plate above field oxide layer and between drain and silicon polycrystal gate , which is connected to drain. The invention brings in silicon polycrystal field electrode plate with the same electric potential of drain end, which makes the surface of floating area deviation area below silicon polycrystal field electrode plate in accumulation condition of current carrier, greatly reducing peak electric field between drain end and silicon polycrystal field electrode plate when in operation work condition and impact ionization of current carrier on drain end, so Kirk effect(the effect of breakdown voltage reduction caused by electric field accumulating under large current ) is notably ...

Short circuit self-protection circuit and method for insulated gate bipolar device

The invention relates to a short circuit self-protection circuit and a short circuit self-protection method for an insulated gate bipolar device. The protection circuit comprises a voltage detection circuit, a current detection circuit, a soft shut-off protection circuit and a gate voltage reduction protection circuit, wherein the voltage detection circuit and the current detection circuit are used for detecting a short circuit signal of the insulated gate bipolar device; the soft shut-off protection circuit and the gate voltage reduction protection circuit receive feedback signals and protect the insulated gate bipolar device in a two-step shut-off manner; the feedback signal of the voltage detection circuit and the feedback signal of one path of the current detection circuit are isolated from each other by using a pair of back-to-back diodes and connected with the gate voltage reduction protection circuit, so mutual interference is avoided; and the other path of the current detection ...

Silicon carbide high pressure P-type metal oxide transistor with floating buried layer and method

The invention discloses a silicon carbide high pressure P-type metal oxide transistor with a floating buried layer, comprising an N-type silicon carbide substrate, on which an N-type epitaxial layer is arranged. The N-type epitaxial layer is internally provided with a source and a P-type drift region; the P-type drift region is internally provided with a drain and an N-type protective ring; the source is provided with a metal lead wire of the source; the drain is provided with the metal lead wire of the source and the drain; a grid oxide layer is arranged above the N-type epitaxial layer disposed between the source and the P-shaped drift region, and connected with the metal lead wire of the source; the surface of the N-type protective ring, the surface of the drain and the surface of the N-type epitaxial layer are provided with field oxide layers; the grid oxide layer is provided with a grid; the metal lead wire of the drain is provided with a metal field pole plate; a P-type floating buried ...

Method for realizing shadow stack memory on picture and circuit thereof

Staged background suppression method of ultrared focal plane readout circuit

The invention relates to a staged background suppression method of an ultrared focal plane readout circuit. The staged background suppression method is characterized in that unit circuits in the ultrared focal plane readout circuit comprise an injection circuit, an integral capacitor circuit, a background current reduction circuit and a row-selection control circuit, wherein the output end of a detector is connected with the input end of the injection circuit; the output end of the injection circuit is connected with the input end of the integral capacitor circuit; the output end of the integral capacitor circuit, the output end of the background current reduction circuit and the input end of the row-selection control circuit are mutually connected; the input end of the background currentreduction circuit is connected with an input voltage VB; and the output end of the row-selection control circuit is connected with a subsequent signal-processing circuit. The background current reduction ...

Switch-level circuit with adaptive control of dead time

The invention relates to a switch-level circuit with adaptive control of dead time, which is used for lowering the switching loss in a switching power supply converter with synchronous rectification. By changing the dead time for opening a switch-level high-side control tube and a low-side synchronous rectification tube, the circuit minimizes the switching loss of the switching power supply. The circuit comprises the high-side control tube and the low-side synchronous rectification tube, wherein the high-side control tube and the low-side synchronous rectification tube are controlled by external control signals to be opened and closed, and the set duty ratio waveforms are output on switching nodes. The switch-level circuit also comprises a sampling circuit part and an adjusting circuit part, wherein the sampling circuit part is used for sensing the conduction time of a body diode of the synchronous rectification tube caused by the dead time and converting the signal into the voltage value ...

A high voltage N-type MOS transistor and the corresponding manufacturing method

The invention discloses a high-voltage N-type metal oxide semiconductor, including a P-type substrate, a P-well drift region and an N-type drift region are arranged on the P-type substrate, a P-type contact hole, an N-type source and a field oxide layer are arranged on the P-well, an N-type drain and the filed oxide layer are arranged on the N-type drift region; the invention is characterized in that the thickness a grid oxide layer part which is positioned above the P-well is smaller than the grid oxide layer part which is positioned above the N-type drift region and a thin grid oxide layer and a thick thin grid oxide layer are respectively formed accordingly, a P-type impurity injection region is arranged in the P-well, and the P-type impurity injection region is positioned below the thin grid oxide layer. The invention further discloses a preparation method of the high-voltage N-type metal oxide semiconductor. The invention has the advantages that the invention can greatly reduce the ...

Silicon N-type semiconductor combined device on insulator for improving current density

The invention relates to a silicon N-type semiconductor combined device on an insulator for improving current density. The silicon N-type semiconductor combined device comprises a P-type substrate, wherein the P-type substrate is provided with a buried oxygen layer; the buried oxygen layer is provided with a P-type epitaxial layer, and the P-type epitaxial layer is divided into a region I and a region II; the region I is an insulated gate bipolar device region and comprises an N-type drift region, a P-type deep trap, a N-type buffer trap, a P-type drain region, an N-type source region and a P-type body contact region; a silicon face is correspondingly provided with a field oxide and a gate oxide, and the gate oxide is provided with a polysilicon gate; and the region II is a high-voltage triode region and comprises an N-type triode drift region, an N-type triode buffer trap, a P-type emitter region and an N-type base region. The silicon N-type semiconductor combined device is characterized ...

Motor protector dual-machine linkage method and linkage device

The invention discloses a motor protector double-machine linkage method and a linkage device. The method comprises the following steps of: using a current sampling circuit to separately detect the current of the protected motor, and outputting the sampling current to a single chip machine by a protector; when the single chip machine judges that the motor is abnormal according to the sampling unit, driving a relay control circuit to stop or reversely rotate the motor, and simultaneously sending a synchronous control signal to the other motor linkage device to stop or reversely rotate the othermotor through a serial driving chip; when the abnormality does not occur, driving the relay control circuit to start the motor or not actuate, and simultaneously sending a synchronous control signal to the other motor linkage device to start the other motor or not actuate through the serial driving chip. The linkage device consists of a processor, a current sampling circuit, a serial chip, a relay control ...

Bit synchronizing method and bit synchronizer for Gaussian filtering minimum deviation keying demodulation circuit

The present invention is bit synchronizing method and bit synchronizer for Gaussian filtering minimum deviation keying demodulation circuit. The synchronizing method includes the equispaced sampling to input signal, cross zero level corresponding with digital number Vmean, Nstd=f1/f2, Nref recording the present sampled number; one counter N used to record the sample number within one bit being increased by 1 after each sample and reset for the sample of the next bit in finishing one bit; comparing N with Nref in finishing each sampling and finishing the present bit when N is not smaller than Nref or comparing Vsamp and Vmean in other case; comparing N and Nstd/2 when Vsamp=Vmean, regulating the present bit needed sample number to Nref=Nstd-1 when N is not smaller than Nref/2, or else to Nref=Nstd+1.

Switching power supply with fast transient response

The invention relates to a switching power supply with fast transient response, a hysteresis control loop circuit is increased in an original PWM control loop circuit of the switching power supply, and the hysteresis control loop circuit comprises a hysteresis controller and a control signal gate, wherein the hysteresis controller is used for detecting output voltage of the switching power supply and comparing the output voltage of the switching power supply with reference voltage. When current of a load of the switching power supply mutates, the output voltage of the switching power supply fluctuates. If the output voltage of the switching power supply is in the set range of hysteresis voltage (the reference voltage plus or minus (10-30mV)), the output end SELp and the output end SELn of the hysteresis controller are in low potential, and the control signal gate is used for selecting an output signal Qp1 and an output signal Qn1 of a PWM controller as input signals of a gate signal driving ...

Fault diagnosis method for power converter of switch reluctance motor

The invention relates to a fault diagnosis method for a power converter of a switch reluctance motor; current spectrum of the power converter phase of the switch reluctance motor is tested and used asfault characteristic quantity; and the proportion coefficient Lambada of relative spectrums ratio of the phase current is defined as the ratio of the amplitude of fundamental component of the phase current and the amplitude of direct current component of the phase current. If the coefficient of the relative spectrum ratio of all phase current is basically constant, the power converter does not occur fault; if the amplitudes of the direct current component and the fundamental component of a certain phase current are near to zero respectively, the phase occurs open fault; and compared with thecoefficient of the relative spectrum ratio of the phase current without fault, if the coefficient of the relative spectrum ratio of a certain phase current occurs obvious change, the phase occurs short fault ...

Preparation method for optical anode of dye sensitization solar battery

The invention discloses a preparation method used for a dye sensitive solar battery photo-anode, comprising the steps as follows: preparation of TiO2 nanometer crystal slurry, preparation of TiO2 light scattering layer slurry and coating the TiO2 nanometer crystal slurry and the TiO2 light scattering layer slurry on an FTO electrode so as to prepare the dye sensitive solar battery photo-anode by sintering process. By adopting the method of the invention, the raw material is easily to be gained, the reaction temperature is low; more particularly, the PEG20000 and 2-ethylhexanol are used for preparing the TiO2 nanometer crystal slurry, thus greatly reducing the cost and improving the energy conversion efficiency simultaneously.

High voltage N-shape metal oxide semiconductor tube and its preparing method

Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels

The invention relates to a semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels, comprising an N-type doped silicon substrate which is also used as a drain region, an N-type doped silicon epitaxial layer, a primitive cell region and a terminal region arranged at the periphery of the primitive cell region; the N-type doped silicon epitaxial layer is arranged on the N-type doped silicon substrate; the primitive cell region and the terminal region are arranged on the N-type doped silicon epitaxial layer; the terminal region comprises a first hyperconjugation structure and an N-type silicon doped semiconductor region, wherein the first hyperconjugation structure comprises a P-type column and a N-type column; an N-type heavily doped semiconductor region is arranged in the N-type silicon doped semiconductor region; the first hyperconjugation structure and the N-type silicon doped semiconductor region are respectively provided with a field oxidation ...

CMOS reference voltage source with adjustable output voltage

Preparation process of upper silicon and deep silicon trench isolation structure for insulator

The invention provides a preparation process of an upper silicon and deep silicon trench isolation structure for an insulator, comprising the following steps: a. setting an embedded oxidation layer on a semiconductor substrate, setting N-type top monocrystalline silicon on the embedded oxidation layer, generating a surface oxidation layer on the N-type top monocrystalline silicon, coating photoresist on the surface of the surface oxidation layer, and etching a window with the same size as a deep silicon trench on the photoresist; b. corroding the naked surface oxidation layer and exposing the N-type top monocrystalline silicon to be etched; c. taking the surface oxidation layer as a masking layer for etching the N-type top monocrystalline silicon, and etching the deep silicon trench with the aspect ratio of 7:1.2-7:3 by a anisotropic plasma dry etching process; and completely corroding the surface oxidation layer and corroding the embedded oxidation layer so that the moving depth of the ...

A high voltage P-type MOS transistor and the corresponding manufacturing method

The invention discloses a high-voltage P-type metal oxide semiconductor, including a P-type substrate, a deep N-well is arranged on the P-type substrate, an N-well drift region and a P-type drift region are arranged on the deep N-well, an N-type contact hole, a P-type source and a field oxide layer are arranged on the N-well, a P-type drain and the field oxide layer are arranged on the P-type drift region; the invention is characterized in that the thickness a grid oxide layer part which is positioned above the N-well is smaller than the grid oxide layer part which is positioned above the P-type drift region and a thin grid oxide layer and a thick thin grid oxide layer are respectively formed accordingly. The invention further discloses a preparation method of the high-voltage P-type metal oxide semiconductor. The invention has the advantages that the invention can greatly reduce the hot carrier injection phenomenon of a beak region and improve the overall service life of the device; the ...

High-gain complementary metal oxide operation amplifier

Panel display driving chip based on silicon on insulator (SOI) and preparation method thereof

The invention provides a panel display driving chip based on a silicon on insulator (SOI) material, which is composed of a high-voltage P-type transverse metal oxide transistor, a high-voltage N-type transverse metal oxide transistor, a high-voltage N-type transverse insulated gate bipolar transistor and a low-voltage device, wherein each high-voltage device is isolated by a double-groove structure filled with silicon dioxide, which starts from the oxygen buried layer and ends at the field oxide on the device surface via the N-type buried layer and the N-type epitaxial layer; and the connection region of the epitaxial layer and the oxygen buried layer is provided with the N-type buried layer. The preparation method comprises the following steps: making the oxygen buried layer, the N-type buried layer and the deposition epitaxial layer on the P-type substrate; making the high-voltage P wells of the high-voltage N-type transverse metal oxide transistor and the high-voltage N-type transverse ...

Method for improving stereo crosstalk

The invention provides a method for improving stereo crosstalk. The method adds a phase compensation module in a stereo decoding circuit to reduce the phase error between a pilot signal and a receivedstereo signal, and improve the stereo crosstalk. The phase compensation module consists of a phase error calculation circuit with a symmetrical internal structure, the circuit works out a compensation factor needed to compensate the phase error, and the decoded stereo signal is compensated by the compensation factor, so that the stereo crosstalk is optimized.

Pitching Machine Having Angle and Speed Adjustment Function

A pitching machine includes a stand unit, a direction adjusting device swivelably mounted on the stand unit, a base unit pivotally mounted on the direction adjusting device, two pitch adjusting devices mounted on the base unit, and an angle adjusting device pivotally mounted between the base unit and the direction adjusting device. The base unit includes a base frame, two side brackets, two screwed sockets, two rotation wheels, two drive motors, a guide track, and a push member. Thus, the inclined angle of each of the rotation wheels can be adjusted individually by each of the pitch adjusting devices so that the rotation wheels can be adapted to have different inclined angles. In addition, the angle adjusting device can move the base frame relative to the support arm to change the inclined angle of the base frame.

Pedal power generating device

A pedal power generating device includes a base having two supporting arms upwardly extending therefrom. The base has a gearbox mounted thereon. A pedal assembly is mounted between the two supporting arms. The pedal assembly has a pedal, a supporter extending from the pedal, a connecting rod assembled with the supporter and connected to the gearbox, and a twist spring mounted between the pedal and the two supporting arms. A transmitting assembly is mounted in the gearbox. The transmitting assembly includes a driver, a first gear train engaged with the driver, a second gear train engaged with the first gear train, and a steering gear set simultaneously engaging with the first gear train and the second gear train. A generator is mounted adjacent to the gearbox, and the generator has a rotor engaged with the second gear train.

HUMAN MONOCLONAL ANTIBODIES TO PROTEIN TYROSINE KINASE 7 (PTK7) AND METHODS FOR USING ANTI-PTK7 ANTIBODIES

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies. 1. An isolated nucleic acid molecule encoding an antibody or antigen-binding portion thereof , wherein the antibody:a) specifically binds to human PTK7; andb) binds to a Wilms' tumor cell line (ATCC Acc No. CRL-1441).2. The nucleic acid of claim 1 , wherein the antibody comprises a heavy chain variable region encoded by a nucleic acid sequence selected from the group consisting of: SEQ ID NOs: 41 claim 1 , 42 claim 1 , 43 claim 1 , and 44.3. The nucleic acid of claim 1 , wherein the antibody comprises a light chain variable region encoded by a nucleic acid sequence selected from the group consisting of SEQ ID NOs: 45 claim 1 , 46 claim 1 , 47 claim 1 , 48 claim 1 , 49 claim 1 , and 50.4. The nucleic acid molecule of claim 1 , wherein the antibody comprises heavy and light chain variable regions encoded by nucleic acid sequences selected from the group consisting of SEQ ID NO: 41 and SEQ ID NO: 45; SEQ ID NO: 41 and SEQ ID NO: 46; SEQ ID NO: 42 and SEQ ID NO: 47; SEQ ID NO: 43 and SEQ ID NO: 48; SEQ ID NO: 43 and SEQ ID NO: 49; and SEQ ID NO: 44 and SEQ ID NO: 50 claim 1 , respectively.5. An expression vector comprising the nucleic acid molecule of .6. A host cell comprising the expression vector of .7. A method for preparing an anti-PTK7 antibody which comprises expressing the antibody in the host cell of and isolating the antibody from ...

SWITCH LEVEL CIRCUIT WITH DEAD TIME SELF-ADAPTING CONTROL

A switch level circuit () with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor () and a low-side synchronous rectifying transistor (). The switch level circuit () includes the high-side control transistor () and the low-side synchronous rectifying transistor () which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit () also includes a control module for adjusting the dead time. The control module comprises a sampling circuit () for detecting the current dead time at the node (LX), an adjusting circuit () for buffering and converting the sampling voltage sampled by the sampling circuit (), and a controlled delay unit () equipped with an external control input terminal, wherein the controlled delay unit () delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor () as a control signal. The switch level circuit () has simple structure, better performance and wide application range. 1101110111011101011111011141310111617161511. A switch level circuit with self-adapting dead time control capability which includes a high-side control transistor () and a low-side synchronous rectifying transistor () , wherein , the source end of the high-side control transistor () is connected to the input voltage , and the source end of the low-side synchronous rectifying transistor () is grounded , the drain end of the high-side control transistor () is connected to the drain end of the low-side synchronous rectifying transistor () to form a switching node (LX) , the gate end of the high-side control transistor () , which is used as a controlled end of the high-side control transistor () , is used for the input of a first ...

Switching power supply with quick transient response

A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller ( 117 ) and a control signal gate ( 116 ) is added to the original PWM control loop of the switching power supply. The hysteretic controller ( 117 ) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller ( 117 ) are in a low potential, and the control signal gate ( 116 ) selects output signals (Qp 1 , Qn 1 ) from a PWM controller ( 101 ) as input signals of a gate signal drive circuit ( 106 ). If the fluctuation of the output voltage (Vout) of the switching power supply exceeds the setting range of the hysteretic voltage, an output terminal (SELp, SELn) of the hysteretic controller ( 117 ) outputs a high potential, and the control signal gate ( 116 ) selects output signals (Qp 2 , Qn 2 ) of the hysteretic controller ( 117 ) as input signals of the gate signal drive circuit ( 106 ), so the operation of switching tubes ( 111, 112 ) at the power lever ( 102 ) of the switching power supply is controlled to stabilize the output voltage (Vout).

Providing low-latency error correcting code capability for memory

A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

SILICON ON INSULATOR INTEGRATED HIGH-CURRENT N TYPE COMBINED SEMICONDUCTOR DEVICE

A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. It is characterized in that the N type base region is wrapped in the N type buffer region, and the drain electrode metal on the P type drain region is connected with the base electrode metal on the N type base region by a metal layer. In this invention, the current density of the device has been obviously improved without increasing the device area and reducing other performances of the device. 11211621112161112721112111210110221011022111211127070. A SOI integratable high-current N-type combined semiconductor device , comprising: a P-type silicon substrate (); a buried oxide layer () arranged on the P-type silicon substrate (); characterized in that a P-type deep trench () arranged above the center of the buried oxide layer (); an N-type annular source region () and a P-type body contact region () arranged on the P-type deep trench () , wherein , the N-type annular source region () surrounds outside of the P-type body contact region () , and a piece of source electrode metal () is arranged on the N-type source region () ...

ELECTRONIC DATA EXCHANGE SYSTEM AND METHOD OF EXCHANGING ELECTRONIC DATA

Electronic data exchange system includes a transmitting portable electronic device and a server. The transmitting portable electronic device has an application program. A user of the transmitting portable electronic device utilizes the application program to generate an electronic data transmission control command. The server includes a data base. The data base stores an electronic data album of the user. When the server transmits electronic data of the user to at least one receiving portable electronic device, and transmits electronic data of at least one user of the at least one receiving portable electronic device to the transmitting portable electronic device according to the electronic data transmission control command, the server updates the electronic data album according to the electronic data of the at least one user. 1. An electronic data exchange system , comprising:a transmitting portable electronic device having an electronic data exchange application program, wherein a user of the transmitting portable electronic device utilizes the electronic data exchange application program to generate an electronic data transmission control command; anda server comprising a data base, wherein the data base is used for storing an electronic data album of the user, wherein when the server transmits electronic data of the user to at least one receiving portable electronic device according to the electronic data transmission control command, and transmits electronic data of at least one user of the at least one receiving portable electronic device to the transmitting portable electronic device, the server updates the electronic data album of the user according to the electronic data of the at least one user;wherein the at least one receiving portable electronic device has the electronic data exchange application program, and the electronic data album comprises the electronic data of the user and electronic data of other people.2. The electronic data exchange system of ...

Film affixing apparatus

A film affixing apparatus for affixing a film to a workpiece includes a stand, a film provider, and an affixing device. The stand includes a work platform. The workpiece slides along the work platform under an external force. The film provider is mounted to the stand and dispenses rolls of film. The affixing device is mounted to the stand. The affixing device includes a pressing portion that faces the work platform. The film is unwound and passes over the pressing portion onto the workpiece on the work platform. The pressing portion presses the film onto the workpiece.

Machine for cutting object and sticking film

A machine for cutting off a redundant part of a workpiece and affixing film to a top surface of the workpiece includes a stand, a cutting device, and an affixing device. The stand has a work platform. The workpieces slide on the work platform. The cutting device includes a first blade. The film provider dispenses the film. The affixing device has a pressing portion facing the work platform. The workpiece slides to the cutting device and the affixing device. The film is unwound and passes over the pressing portion. The cutting device cuts off the redundant parts of the workpiece when the workpiece slides under the cutting device, and the pressing portion presses the film onto the top surface of the workpiece when the workpiece slides under the affixing device.

SYNCHRONOUS RECTIFYING APPARATUS AND CONTROLLING METHOD THEREOF

The present application provides a synchronous rectifying apparatus and a control method thereof, the apparatus comprising: a transformer, a primary circuit, a rectifying circuit, a self-driving circuit, a PWM control circuit and an auxiliary control module including at least one auxiliary control circuit and at least one auxiliary winding, wherein the auxiliary control circuit includes at least one auxiliary switch and is electrically coupled to the Pulse Width Modulation control circuit and the auxiliary winding via the auxiliary switch, and the auxiliary winding is electrically coupled to the transformer; wherein before the transfer switch of the primary circuit is controlled to be turned on by the switching control signal, the auxiliary switch is controlled to be turned on by the auxiliary control signal, and the synchronous rectifier of the rectifying circuit is controlled to be turned off through the self-driving signal. 1. A synchronous rectifying apparatus , comprising:a transformer including a primary winding and a secondary winding;a primary circuit including at least one transfer switch and being electrically coupled to the primary winding;a rectifying circuit including at least one synchronous rectifier and being electrically coupled to the secondary winding;a self-driving circuit electrically coupled to the rectifying circuit and outputting a self-driving signal;a Pulse Width Modulation control circuit electrically coupled to the primary circuit and outputting at least one switching control signal and at least one auxiliary control signal; andan auxiliary control module including at least one auxiliary control circuit and at least one auxiliary winding, wherein the auxiliary control circuit includes at least one auxiliary switch and is electrically coupled to the Pulse Width Modulation control circuit and the auxiliary winding via the auxiliary switch, and the auxiliary winding is electrically coupled to the transformer;wherein before the transfer ...

POWER CONVERSION MODULE

A power conversion module includes a high-voltage side, a low-voltage side, a magnetic element, a high-voltage side circuit, and a low-voltage side circuit. The first end includes a high-voltage positive terminal and a high-voltage negative terminal. The second end includes a low-voltage positive terminal and a low-voltage negative terminal. The magnetic element includes two first windings. The high-voltage side circuit is electrically connected with the high-voltage positive terminal and the high-voltage negative terminal. The low-voltage side circuit is electrically connected with the low-voltage positive terminal and the low-voltage negative terminal. At least one AC loop includes at least one of the first windings, at least one part of the high-voltage side circuit and the low-voltage side circuit. The high-voltage side circuit and the low-voltage side circuit are located at a same side with respect to the magnetic element. 1. A power conversion module , comprising:a first end comprising a high-voltage positive terminal and a high-voltage negative terminal;a second end comprising a low-voltage positive terminal and a low-voltage negative terminal, wherein the low-voltage negative terminal is electrically connected with the high-voltage negative terminal;a magnetic element comprising two first windings;a high-voltage side circuit electrically connected with the high-voltage positive terminal and the high-voltage negative terminal, and electrically connected with the two first windings of the magnetic element; anda low-voltage side circuit electrically connected with the low-voltage positive terminal and the low-voltage negative terminal, and electrically connected with the two first windings of the magnetic element,wherein the power conversion module comprises at least one alternating current (AC) loop defined by at least one of the first windings, at least one part of the high-voltage side circuit, and at least one part of the low-voltage side circuit, wherein ...

ELECTRONIC DEVICE AND PAIRING METHOD THEREOF

An electronic device and a pairing method including following steps are provided. A first touch operation performed on a first touch unit of a first electronic device is detected, and a first azimuth angle of a first pointing direction (defined by the first touch operation) with respect to a reference direction is obtained. The first azimuth angle is compared with a second azimuth angle to obtain an included angle between the first pointing direction and a second pointing direction. When a value obtained by subtracting 180 degrees from an absolute value of the included angle is smaller than a threshold, a pairing relationship is established between the first and second electronic devices. The second azimuth angle is an azimuth angle of the second pointing direction (defined by a second touch operation performed on a second touch unit of the second electronic device) with respect to the reference direction. 1. A pairing method of electronic devices , the pairing method comprising:detecting a first touch operation performed on a first touch unit of a first electronic device and obtaining a first azimuth angle of a first pointing direction with respect to a reference direction, wherein the first pointing direction is defined by the first touch operation; andcomparing the first azimuth angle with a second azimuth angle to obtain an included angle between the first pointing direction and a second pointing direction, and establishing a pairing relationship between the first electronic device and a second electronic device if a value obtained by subtracting 180 degrees from an absolute value of the included angle is smaller than a threshold,wherein the second azimuth angle is an azimuth angle of the second pointing direction with respect to the reference direction, and the second pointing direction is defined by a second touch operation performed on a second touch unit of the second electronic device.2. The pairing method as recited in claim 1 , wherein the step of ...

HETEROJUNCTION SEMICONDUCTOR DEVICE WITH LOW ON-RESISTANCE

A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

HUMAN MONOCLONAL ANTIBODIES TO O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer. 1. A method of treating or preventing a disease characterized by growth of tumor cells expressing O8E , comprising administering to a subject an isolated monoclonal antibody or antigen-binding portion thereof , in an amount effective to treat or prevent the disease , wherein the antibody or antigen binding portion thereof comprises a heavy chain variable region comprising CDR1 , CDR2 , and CDR3 domains; and a light chain variable region comprising CDR1 , CDR2 , and CDR3 domains , wherein the heavy chain variable region and light chain variable region CDR3 domains are selected from the group consisting of (a) a heavy chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:21; and a light chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:36 and conservative modifications thereof;(b) a heavy chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:22; and a light chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:37 and conservative modifications thereof;(c) a heavy chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:23; and a light chain variable region CDR3 comprising amino acids having the sequence set forth in SEQ ID NO:38 and conservative modifications thereof;(d) a heavy chain variable region CDR3 comprising amino acids having the sequence set forth ...

SIDE SNOWPLOW INCLUDING LAND LEVELER

A side snowplow including a land leveler, comprising: a rear mounted seat (), a hydraulic cylinder I (), a pull rod (), a snow-pushing board (), an oscillating rod (), a hydraulic cylinder II (), and a front mounted seat (). The rear mounted seat () is fixed on a rear portion of a rear rack of the land leveler and connected to the pull rod (); the hydraulic cylinder I () is hingedly connected to the rear mounted seat (), and the pull rod (); and the snow-pushing board () is positioned at a left side or a right side of the land leveler and inclines toward a direction that the land leveler moves, a rear end of the snow-pushing board () being connected to the hinge plate II (), a front end of the snow-pushing board () being connected to the hinge plate III (). 11347101112. A side snowplow including a land leveler , comprising: a rear mounted seat () , a hydraulic cylinder I () , a pull rod () , a snow-pushing board () , an oscillating rod () , a hydraulic cylinder II () , and a front mounted seat () , wherein:{'b': 1', '1', '2', '9, 'the rear mounted seat () is fixed on a rear portion of a rear rack of the land leveler, the rear mounted seat () being hingedly connected to a hinge plate I () through pins ();'}{'b': 4', '2', '4', '6', '5, 'one end of the pull rod () is hingedly connected to the hinge plate I () through pins, and another end of the pull rod () is hingedly connected to a hinge plate II () through fixed pins ();'}{'b': 3', '1', '3', '4, 'one end of the hydraulic cylinder I () is hingedly connected to the rear mounted seat (), and another end of the hydraulic cylinder I () is hingedly connected to the pull rod ();'}{'b': '12', 'the front mounted seat () is fixed on a front portion of the rear rack of the land leveler;'}{'b': 10', '12', '10', '8', '9, 'one end of the oscillating rod () is hingedly connected to the front mounted seat (), and another end of the oscillating rod () is hingedly connected to a hinge plate III () through the pins ();'}{'b': 11', '12 ...

Device for detaching a cover from a base

A device for detaching a cover adhesively attached to a base is provided. The device includes a support plate for supporting the base, and a suction plate applying an overall and uniform attracting action to the cover by means of a vacuum. The device further includes a driving unit to pull the suction plate away from the base. The device further includes a heating element to heat and soften adhesive, thereby weakening the adhesive bond between the base and the cover and allowing the release of the cover from the base.

MONOCLONAL ANTIBODIES AGAINST GLYPICAN-3

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to Glypican-3 with high affinity. Nucleic acid molecules encoding Glypican-3 antibodies, expression vectors, host cells and methods for expressing the Glypican-3 antibodies are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the Glypican-3 antibodies are also provided. Methods for detecting Glypican-3, as well as methods for treating various Glypican-3-related conditions, including hepatocellular cancer, are disclosed. 1. An isolated nucleic acid molecule encoding;(a) a heavy chain of an anti-Glypican-3 antibody, or antigen-binding portion thereof, wherein the heavy chain variable region comprises the amino acid sequence of SEQ ID NO: 19, 20 or 21; or(b) a light chain of an anti-Glypican-3 antibody, or antigen-binding portion thereof, wherein the light chain variable region comprises the amino acid sequence of SEQ ID NO: 22, 23 or 24.2. The nucleic acid molecule of claim 1 , wherein the heavy chain variable region comprises the amino acid sequence of SEQ ID NO: 19.3. The nucleic acid molecule of claim 1 , wherein the heavy chain variable region comprises the amino acid sequence of SEQ ID NO: 20.4. The nucleic acid molecule of claim 1 , wherein the heavy chain variable region comprises the amino acid sequence of SEQ ID NO: 21.5. The nucleic acid molecule of claim 1 , wherein the light chain variable region comprises the amino acid sequence of SEQ ID NO: 22.6. The nucleic acid molecule of claim 1 , wherein the light chain variable region comprises the amino acid sequence of SEQ ID NO: 23.7. The nucleic acid molecule of claim 1 , wherein the light chain variable region comprises the amino acid sequence of SEQ ID NO: 24.8. The nucleic acid molecule of claim 2 , comprising the nucleotide sequence of SEQ ID NO: 25.9. The nucleic acid molecule of claim 3 , comprising the nucleotide sequence of SEQ ...

Packet capture via packet tagging

Techniques are disclosed for capturing network traffic in a virtualized computing environment. A packet to be captured in the virtualized environment is identified. The packet is tagged using a pattern of one or more bits in a header of the packet. The pattern indicates that the packet is to be traced. The pattern is propagated to an outer layer during encapsulation of the packet. A header of the encapsulated packet includes the pattern of one or more bits. At least one network device is caused to mirror identified packets based on the reserved bit.

Voltage regulator module

A voltage regulator module with a vertical layout structure includes a circuit board assembly, an electroplated region and a magnetic core assembly. The circuit board assembly includes a printed circuit board and at least one switch element. The printed circuit board includes a first surface, a second surface, a plurality of lateral surfaces, an accommodation space and a conductive structure. The switch element is disposed on the first surface. A conduction part is formed on the second surface. The conductive structure is perpendicular to the printed circuit board and disposed within the accommodation space. The electroplated region is formed on the corresponding lateral surface, arranged between the conduction part and the first surface, and electrically connected with the conduction part and the switch element. The magnetic core assembly is accommodated within the accommodation space. Consequently, an inductor is defined by the conductive structure and the magnetic core assembly collaboratively.

ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT

An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area. 1. An isolation structure of high-voltage driving circuit , comprising: a P-type substrate; a P-type epitaxial layer arranged on the P-type substrate; a low-voltage region and a high-voltage region arranged on the P-type epitaxial layer; a HV-LV junction terminal region arranged between the low-voltage region and the high-voltage region; a first P-type junction isolation region arranged between the HV-LV junction terminal region and the low-voltage region , said first P-type junction isolation region being composed of a P-type buried layer and a first P-type well; a second P-type junction isolation region arranged in the interior zone of the first P-type junction isolation region and working with the first P-type junction isolation region to enclose an isolated region; a high-voltage insulated gate field effect transistor (IGFET) arranged in the isolated region and utilizing the HV-LV junction terminal region as its drift region; wherein , the high-voltage region is partially located in the isolated region , the partial high-voltage region in the isolated region comprises a first N-type deep well arranged in the P-type substrate and a first N-type well region arranged in the P-type epitaxial layer , and the N-type well region is on the top surface of the ...

ANTI-CD27 ANTIBODIES AND USES THEREOF

This disclosure provides isolated antibodies that bind specifically to CD27 with high affinity. The disclosure provides methods for treating a subject afflicted with a cancer comprising administering to the subject a therapeutically effective amount of an anti-CD27 antibody as monotherapy or in combination with a checkpoint inhibitor, such as an anti-PD-1, anti-PD-L1, or anti-CTLA-4 antibody. 1. A monoclonal antibody or an antigen-binding portion thereof that specifically binds to human CD27 and does not block binding of its CD70 ligand as measured by surface plasmon resonance (SPR) or flow cytometry , wherein the antibody or fragment thereof:{'sub': 'D', '(a) binds to human CD27 with a Kof about 100 nM or lower, about 90 nM or lower, about 80 nM or lower, about 70 nM or lower, about 60 nM or lower, about 50 nM or lower, about 40 nM or lower, between about 1 nM and about 100 nM, between about 10 nM and about 70 nM, between about 10 nM and about 50 nM, or between about 40 nM and about 45 nM, and/or'}{'sub': '50', '(b) induces NF-κB and MAPK signaling with an ECof about 0.5 nM or lower, about 0.4 nM or lower, about 0.3 nM or lower, between about 0.005 nM and about 0.5 nM, between about 0.01 nM and about 0.4 nM, or between about 0.02 nM and about 0.25 nM in naïve human T cells stimulated by an anti-CD3 antibody and an anti-CD28 antibody.'}2. A monoclonal antibody or an antigen-binding portion thereof that specifically binds to an epitope located within discontinuous regions spanning approximately amino acid residues 21-41 and 52-57 of human CD27 , a sequence of which is set forth as SEQ ID NO: 1 , as determined by hydrogen-deuterium exchange mass spectrometry (HDX-MS) and/or fast photochemical oxidation of proteins (FPOP) epitope mapping.3. A monoclonal antibody or an antigen-binding portion thereof that specifically binds to human CD27 , which:{'sub': 'H', '(a) comprises a heavy chain variable region (V) comprising a CDR1 comprising consecutively linked amino acids ...

Magnetic device and power converter with same

A magnetic device includes two common magnetic legs, a plurality of coupled magnetic legs, and two windings. The first winding includes a first input part, a first intermediate part and a first output part. The second winding includes a second input part, a second intermediate part and a second output part. The first input part is disposed between the first common magnetic leg and the first coupled magnetic leg. The second input part is disposed between the second common magnetic leg and the first coupled magnetic leg. The first intermediate part and the second intermediate part are disposed between every two adjacent coupled magnetic legs. The first output part is disposed between the first common magnetic leg and the last coupled magnetic leg. The second output part is disposed between the second common magnetic leg and the last coupled magnetic leg.

HUMAN MONOCLONAL ANTIBODIES TO O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer. 1. An isolated human monoclonal antibody or an antigen-binding portion thereof , wherein the antibody:{'sub': 'D', 'sup': '−7', '(a) binds to human O8E with a Kof 1×10M or less; and'}(b) binds to a breast cell carcinoma tumor cell line.2. The antibody of claim 1 , wherein said antibody is internalized.3. The antibody of claim 1 , wherein the breast cell carcinoma tumor cell line is SKBR3 cell line.4. The antibody of claim 1 , wherein said antibody lacks fucose residues.5. The antibody of claim 1 , which comprises a heavy chain variable region that comprises CDR1 claim 1 , CDR2 claim 1 , and CDR3 domains; and a light chain variable region that comprises CDR1 claim 1 , CDR2 claim 1 , and CDR3 domains claim 1 , wherein the heavy chain variable region and light chain variable region CDR1 claim 1 , CDR2 claim 1 , and CDR3 domains are selected from the group consisting of:(a) a heavy chain variable region CDR1 comprising SEQ ID NO: 1; a heavy chain variable region CDR2 comprising SEQ ID NO: 16; a heavy chain variable region CDR3 comprising SEQ ID NO: 21; a light chain variable region CDR1 comprising SEQ ID NO: 26; a light chain variable region CDR2 comprising SEQ ID NO: 31; and a light chain variable region CDR3 comprising SEQ ID NO: 36;(b) a heavy chain variable region CDR1 comprising SEQ ID NO: 12; a heavy chain variable region CDR2 comprising SEQ ID NO: 17; a heavy chain variable region CDR3 comprising SEQ ID NO: 22; a light chain variable region CDR1 ...

Wheel fastening system for direction-precise mobile robot with wheels

A wheel fastening system for a wheeled mobile robot includes a chassis, a motor, a wheel, a thrust bearing, a stud, and a screw. The chassis has a base and a cover. The cover covers the base. The motor is disposed in the chassis. The motor has a shaft. The wheel has a hub by which the wheel is centered on the shaft of the motor. The thrust bearing is an interference fit between the wheel and the chassis and provides axial support for the wheel. The stud passes through the hub of the wheel to couple to the shaft of the motor. The screw is coupled to the stud, and is clamped between the base and the cover of the chassis. The stud and the screw prevent the wheel from radially shifting relative to the shaft of the motor.

SELF-ADAPTIVE SYNCHRONOUS RECTIFICATION CONTROL SYSTEM AND METHOD OF ACTIVE CLAMP FLYBACK CONVERTER

The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter. 1. A self-adaptive synchronous rectification control system of an active clamp flyback converter , comprising:a sampling and signal processing circuit, a control circuit with a microcontroller as a core, and a gate driver, wherein an input end of the sampling and signal processing circuit is connected with a drain of a secondary synchronous rectifier of the active clamp flyback converter, a first output end and a second output end of the sampling and signal processing circuit are both connected with the control circuit with the microcontroller, an output end of the control circuit with the microcontroller is connected with an input end of the gate driver, and an output end of the gate driver is connected with a gate of the secondary synchronous rectifier of the active clamp flyback converter; wherein, a first comparator,', 'a second comparator,', 'a counter,', 'a register,', 'a control unit, and', 'a pulse width modulation (PWM) timer,, 'the control circuit with the microcontroller compriseswherein the first comparator, the second comparator and the PWM timer are actual ...

Distance sensor

A distance sensor includes an IR emitter, an IR receiver, and an annular support. The IR emitter includes a transmitter. The IR receiver includes a number of transceivers. The annular support includes a transmitter support and a transceiver support. The transmitter support is located centrally within the transceiver support. The transmitter is arranged on the transmitter support. The transmitter emits infrared signals through a top of the annular support to a transmission lens, and the transmission lens scatters the infrared light. The transceivers are arranged on the transceiver support and positioned around a periphery of the annular support to receive reflected infrared signals.

Power Module of Square Flat Pin-Free Packaging Structure

A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

GATE DRIVE CIRCUIT FOR REDUCING REVERSE RECOVERY CURRENT OF POWER DEVICE

The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device. 1. A gate drive circuit for reducing a reverse recovery current of a power device , comprising:a high-voltage LDMOS transistor, a drain of the high-voltage LDMOS transistor and a drain of the power device being jointly connected to a bus voltage, and a gate of the high-voltage LDMOS transistor and a gate of the power device being jointly connected to an output terminal of a drive circuit;a first diode, an anode of the first diode being connected to a source of the high-voltage LDMOS transistor, and a cathode of the first diode and a source of the power device being jointly connected to a ground;a switch transistor being in series connection with the source of the high-voltage LDMOS transistor, a current input terminal of the switch transistor and the source of the power device being connected to the ground, and a current output terminal of the switch transistor being connected to the source of the high- ...

Method and apparatus for multi-spray rrc process with dynamic control

A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

Medical apparatus for atomizing water, gas, and liquid medication

A medical apparatus is provided with a housing; a mixer including a gas reservoir; a water unit for flowing water to the mixer; a gas unit for flowing gas to the gas reservoir; a gas output for flowing gas from the gas reservoir to the mixer so that gas is mixed with water to form a first mixture, a line for carrying the first mixture; a valve disposed downstream of the line; Venturi tubes disposed downstream of the valve; medication units for containing liquid medication, each medication unit being in fluid communication with the corresponding Venturi tube; a mixing device disposed downstream of the Venturi tubes to atomize the liquid medication and the first mixture to form a second mixture; a control panel electrically connected to the gas reservoir, the mixer, the valve, the medication units, and the mixing device respectively; and an outlet.

HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR

A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor. 1. A high-current N-type SOI-LIGBT , comprising:a P-type silicon substrate;a buried oxide layer arranged on the P-type silicon substrate;an N-type epitaxial layer arranged on the buried oxide layer;an N-type central buffer well region arranged in the N-type epitaxial layer;a P-type emitter region arranged in the N-type central buffer well region;and a portion of emitter metal connected to the P-type emitter region;wherein:a first N-type base region and a second N-type base region are arranged in the N-type central buffer well region, and the first N-type base region and the second N-type base region are at two sides of the P-type emitter region and in symmetry to the P-type emitter region;a first portion of base metal is connected to the first N-type base region, a second portion of base metal is connected to the second N-type base region, a first P-type body region and a second P-type body region are arranged at two sides of the N-type central buffer well region respectively, and the first P-type body region and the ...

Breast support device for radiotherapy

A breast support device for radiation therapy includes a cuplike body with a through aperture. The cuplike body has a base portion and a compression portion connected continuously forming a concave inner surface, the compression portion is extended from the base portion, the concave inner surface have contours that fit over the female patient's breast as patient been in a predetermined posture. The through aperture is formed on the cuplike body to receive a portion of the female patient's breast through, it has a contour curve defined by a cutting plane and the contours of the patient's breast.

CONTROL METHOD FOR IMPROVING DYNAMIC RESPONSE OF SWITCH POWER

A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power. 1the sampling module comprises a sampling circuit and a sampling calculation module, the sampling circuit outputs a partial voltage through the switch power to obtain the information of the output voltage, and the sampling calculation module calculates the output voltage as Vo according to the result of the sampling circuit;the dynamic control module comprises a voltage monitoring module and a slope calculation module; the voltage monitoring module receives the sampling result of the output voltage Vo outputted by the sampling module and determines whether to adopt a dynamic mode according to the relationship between Vo and a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref respectively, wherein Vomin Подробнее

DC/DC CONVERTER AND CONTROL METHOD THEREOF

A DC/DC converter and a control method thereof are disclosed. The DC/DC converter comprises: an output voltage regulation circuit configured to regulate an output voltage of the DC/DC converter, so as to output a duty cycle regulation signal; a PWM generator electrically coupled to the output voltage regulation circuit and configured to generate a first duty cycle signal according to a first clock signal and the duty cycle regulation signal; a detection circuit configured to output a control signal according to a second clock signal and a feedback signal, wherein the feedback signal is configured to detect whether or not the transient change of an input voltage of the DC/DC converter occurs; and a CBC regulation circuit electrically coupled to the PWM generator and the detection circuit, and configured to receive the first duty cycle signal and the control signal and output a second duty cycle signal. 1. A DC/DC converter comprising:an output voltage regulation circuit configured to regulate an output voltage of the DC/DC converter, so as to output a duty cycle regulation signal;a PWM generator electrically coupled to the output voltage regulation circuit, and configured to generate a first duty cycle signal according to a first clock signal and the duty cycle regulation signal;a detection circuit configured to output a control signal according to a second clock signal and a feedback signal, wherein the second clock signal and the first clock signal keep the first duty cycle signal and the control signal in a same frequency, and the feedback signal is used to detect whether or not a transient change of an input voltage of the DC/DC converter occurs; anda CBC regulation circuit electrically coupled to the PWM generator and the detection circuit, and configured to output a second duty cycle signal according to the first duty cycle signal and the control signal.2. The DC/DC converter according to claim 1 , wherein the feedback signal is at least one selected from the ...

TRANSVERSE ULTRA-THIN INSULATED GATE BIPOLAR TRANSISTOR HAVING HIGH CURRENT DENSITY

A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module. 11122333464541151159678317617466787812118121188101212312812810121311121266787859147878159161212aaaababbbbbabbbaabbbbabbababaabbaabbab. A transverse ultra-thin insulated gate bipolar transistor having high current density , comprising: a P substrate () , wherein the P substrate () is provided with a buried oxide layer () thereon , the buried oxide layer () is provided with an N epitaxial layer () thereon , the thickness of the N epitaxial layer () is 0.1 to 1.5 μm , the N epitaxial layer () is provided with an N well region () and a P base region () therein , the N well region () is provided with an N buffer region () therein , the N well region () is provided with a field oxide layer () thereon , a boundary of the N buffer region () abuts against a boundary of the field oxide layer () , the N buffer region () is ...

INTEGRATED BOOTSTRAP HIGH-VOLTAGE DRIVER CHIP AND TECHNOLOGICAL STRUCTURE THEREOF

Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor C, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode Dand a second parasitic diode Dare provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal. 100100200200400500600700100800901000410040050050060060070070082008009009010010006007004005001007006005005. An integrated bootstrap high-voltage driver chip based on a driver circuit of a half-bridge structure , comprising a low-side channel logic circuit () and a high-side channel logic circuit () , wherein the high-side channel logic circuit () comprises a high-side signal input circuit () , a narrow pulse generation circuit () , a high-voltage level shift circuit () and a high-side channel high-basin logic circuit () composed of two pulse filtering circuits with the same structure , an RS trigger and a high-side signal output circuit; the low-side channel logic circuit () comprises a low-side signal input circuit () , a low-side delay circuit () and a low-side signal output circuit (); a high-side input signal HIN is connected to the input end of the high-side signal input circuit () , an output signal CIN of the high-side signal input circuit () is connected to the input end of the narrow pulse generation circuit () , a low-voltage set signal SET and a low-voltage reset signal RESET outputted by the narrow pulse generation circuit () are respectively connected to two input ends of the high-voltage level shift circuit () , a high-voltage set signal VRS and a high-voltage reset signal VRR outputted by the high-voltage level shift circuit () are respectively connected to two input ends of the high-side channel high-basin logic ...

DC/DC CONVERSION SYSTEM

The present disclosure relates to a DC/DC conversion system, including a plurality of switch conversion branches, each of the switch conversion branches includes: a primary side circuit, having an input end connected in parallel with an input capacitor; a transformer, having a primary winding coupled to the primary side circuit; and a secondary side circuit, coupled to a secondary winding of the transformer, wherein, input ends of the primary side circuits of the plurality of switch conversion branches are connected in series to form a system input end, output ends of the secondary side circuits of the plurality of switch conversion branches are connected in series to form a system output end, and a filter circuit is connected in parallel with the system output end. 1. A DC/DC conversion system , comprising: a primary side circuit, having an input end connected in parallel with an input capacitor;', 'a transformer, having a primary winding coupled to the primary side circuit; and', 'a secondary side circuit, coupled to a secondary winding of the transformer,, 'a plurality of switch conversion branches, each of the switch conversion branches compriseswherein, input ends of the primary side circuits of the plurality of switch conversion branches are connected in series to form a system input end, output ends of the secondary side circuits of the plurality of switch conversion branches are connected in series to form a system output end, and a filter circuit is connected in parallel with the system output end.2. The DC/DC conversion system according to claim 1 , wherein the primary side circuit comprises a full-bridge circuit or a half-bridge circuit.3. The DC/DC conversion system according to claim 2 , wherein in any two adjacent primary side circuits claim 2 , a phase difference between driving signals of switches at corresponding positions is 180 deg/S claim 2 , and S is a number of the plurality of switch conversion branches.4. The DC/DC conversion system according ...

ANTI-HUMAN mIgA ANTIBODIES CAPABLE OF LYSING mIgA-B LYMPHOCYTES AND DECREASING IgA PRODUCTION

Disclosed herein is an anti-migis-ααantibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, cause the lysis of mIgA-expressing B lymphocytes, and decrease IgA production by IgA-secreting B lymphocytes. Disclosed further is a pharmaceutical composition comprising the anti-migis-α antibody and a pharmaceutically acceptable carrier. Disclosed further is a method for lysing mIgA-expressing B lymphocytes and reducing IgA production in a human subject in vivo by employing an antibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, cause the lysis of mIgA-expressing B lymphocytes, and decrease IgA production by IgA-secreting B lymphocytes. Disclosed herein is also a method for treating a disease in a subject, comprising administering to the subject an antibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, thereby lysing mIgA-expressing B lymphocytes and reducing IgA production in the immune system of the subject. In addition, Disclosed also is use of said anti-migis-α antibody or said fragment thereof for treating a disease in a subject that can benefit from the elimination of mIgA-expressing cells or the reduction of IgA antibodies in the immune system.

Conductive substrate of a display device

A conductive substrate of a display device has an electrically insulating substrate and a plurality of rows of electrical pin connecting areas, a plurality of rows of patterned input voltage lines and a plurality of rows of patterned grounded lines formed on the electrically insulated substrate. Each of the rows of the electrical pin connecting areas includes a plurality of electrical pin connecting areas electrically isolated and spaced from each other in a line. The rows of the patterned input voltage lines are respectively adjacent to the rows of the electrical pin connecting areas, and the rows of the patterned grounded lines are respectively adjacent to the rows of the electrical pin connecting areas. Besides, two opposite sides of at least one row of the patterned input voltage lines are respectively electrically connected with the input voltage pin contacts of two neighboring rows of the electrical pin connecting areas while two opposite sides of at least one row of the patterned grounded lines are respectively electrically connected with the grounded pin contacts of two neighboring rows of the electrical pin connecting areas.

DC-TO-DC CONVERTER CIRCUIT AND CIRCUIT BOARD LAYOUT STRUCTURE FOR THE SAME

The present application discloses a DC-to-DC converter circuit and a circuit board layout structure for the same. The DC-to-DC converter circuit is electrically connected between a first power supply side and a second power supply side, and comprises a first branch with a primary side coupled to the first power supply side and a secondary side coupled to the second power supply side; a second branch with a primary side coupled to the first power supply side and a secondary side coupled to the second power supply side; and a first inductor. The secondary sides of the first branch and the second branch are connected in series via the first inductor. 1. A DC-to-DC converter circuit electrically connected between a first power supply side and a second power supply side , comprising:a first branch with a primary side coupled to the first power supply side and a secondary side coupled to the second power supply side;a second branch with a primary side coupled to the first power supply side and a secondary side coupled to the second power supply side; anda first inductor,wherein, the secondary sides of the first branch and the second branch are connected in series via the first inductor.2. The DC-to-DC converter circuit according to claim 1 , wherein a first transformer, comprising a primary winding and a secondary winding;', 'a first primary switching circuit with one end electrically connected to the primary winding of the first transformer and the other end electrically connected to the first power supply side; and', 'a first secondary rectifier circuit with one end electrically connected to the secondary winding of the first transformer and the other end electrically connected to the second power supply side and one end of the first inductor, and the second branch comprises:', 'a second transformer, comprising a primary winding and a secondary winding;', 'a second primary switching circuit with one end electrically connected to the primary winding of the second ...

Human monoclonal antibodies to cd70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human Monoclonal Antibodies To O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to protein tyrosine kinase 7 (PTK7)

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to CD70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Treating lung cancer using human monoclonal antibodies to protein tyrosine kinase 7 (PTK7)

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to cd70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to protein tyrosine kinase 7 ( ptk7 ) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and methods for using anti-ptk7 antibodies

HUMAN MONOCLONAL ANTIBODIES TO PROTEIN TYROSINE KINASE 7 (PTK7) AND METHODS FOR USING ANTI-PTK7 ANTIBODIES The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. lmmunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti PTK7 antibodies.No suitable figure.

Human monoclonal antibodies to cd70

Human monoclonal antibodies to CD70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to cd70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to CD70

Un anticuerpo monoclonal humano aislado o parte de unión a antígeno del mismo, que comprende: (a) una CDR1 de región variable de cadena pesada que comprende la secuencia de CDR1 como se muestra en la Figura 1A; (b) una CDR2 de región variable de cadena pesada que comprende la secuencia de CDR2 como se muestra en la Figura 1A; (c) una CDR3 de región variable de cadena pesada que comprende la secuencia de CDR3 como se muestra en la Figura 1A; (d) una CDR1 de región variable de cadena ligera que comprende la secuencia de CDR1 como se muestra en la Figura 1B; (e) una CDR2 de región variable de cadena ligera que comprende la secuencia de CDR2 como se muestra en la Figura 1B; y (f) una CDR3 de región variable de cadena ligera que comprende la secuencia de CDR3 como se muestra en la Figura 1B; en donde el anticuerpo se une específicamente a CD70. An isolated human monoclonal antibody or antigen binding part thereof, comprising: (a) a heavy chain variable region CDR1 comprising the CDR1 sequence as shown in Figure 1A; (b) a heavy chain variable region CDR2 comprising the CDR2 sequence as shown in Figure 1A; (c) a heavy chain variable region CDR3 comprising the CDR3 sequence as shown in Figure 1A; (d) a light chain variable region CDR1 comprising the CDR1 sequence as shown in Figure 1B; (e) a light chain variable region CDR2 comprising the CDR2 sequence as shown in Figure 1B; and (f) a light chain variable region CDR3 comprising the CDR3 sequence as shown in Figure 1B; wherein the antibody specifically binds to CD70.

Humane, monoklonale antistoffer mot CD70

Sammendrag Foreliggende beskrivelse tilveiebringer isolerte monoklonale antistoffer, spesielt humane monoklonale antistoffer, som spesifikt binder til CD70 med høy affinitet. Nukleinsyremolekyler som koder for antistoffene ifølge beskrivelsen, uttrykksvektorer, vertsceller og fremgangsmåter for å uttrykke antistoffene ifølge beskrivelsen er også tilveiebrakt. Immunkonjugater, bispesifikke molekyler og farmasøytiske preparater som omfatter antistoffene ifølge beskrivelsen er også tilveiebrakt. Beskrivelsen tilveiebringer også fremgangsmåter for behandling av kreft, autoimmunsykdom, betennelse og virale infeksjoner.

Human monoclonal antibodies to CD70

Disclosed is an isolated monoclonal antibody or antigen binding portion thereof comprising: a) a heavy chain variable region CDR1 comprising SEQ ID NO: 11; b) a heavy chain variable region CDR2 comprising SEQ ID NO: 16; c) a heavy chain variable region CDR3 comprising SEQ ID NO: 21; d) a light chain variable region CDR1 comprising SEQ ID NO: 26; e) a light chain variable region CDR2 comprising SEQ ID NO: 31; and f) a light chain variable region CDR3 comprising SEQ ID NO: 36. Also disclosed is the use of the antibody for the preparation of a medicament for the treatment or prevention of a disease characterized by growth of tumor cells expressing CD70 in a subject.

Human monoclonal antibodies to cd70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to cd70

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to CD70 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the disclosure are also provided. The disclosure also provides methods for treating cancer, autoimmune disease, inflammation and viral infections.

Human monoclonal antibodies to CD70

Human monoclonal antibodies to protein tyrosine kinase 7 ( PTK7 ) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to o8e

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to o8e

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to O8E

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to o8e

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Humane monoklonale antistoffer mot O8E

Sammendrag Den foreliggende beskrivelsen tilveiebringer isolerte monoklonale antistoffer, spesielt humane monoklonale antistoffer som spesifikt binder til 08E med høy affinitet. Nukleinsyremolekyler som koder for antistoffene ifølge denne beskrivelsen, uttrykksvektorer, vertsceller og fremgangsmåter for å uttrykke antistoffene ifølge denne beskrivelsen er også tilveiebrakt. Immunkonjugater, bi-spesifikke molekyler og farmasøytiske preparater som omfatter antistoffene ifølge denne beskrivelsen er også tilveiebrakt. Farmasøytiske preparatene i henhold til foreliggende oppfinnelse kan også anvendes for å behandle kreft.

Human monoclonal antibodies to O8E

Disclosed are human monoclonal antibodies that bind specifically to human O8E (also known as VTCN1). The antibodies can be used as therapeutic agents to treat tumours overexpressing O8E.

Human monoclonal antibodies to o8e

HUMAN MONOCLONAL ANTIBODIES TO 08E The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to 08E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer. Figure 20

Human monoclonal antibodies to o8e

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to O8E

Human monoclonal antibodies to o8e

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to O8E with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of this disclosure are also provided. This disclosure also provides methods for treating cancer.

Human monoclonal antibodies to protein tyrosine kinase 7 (PTK7) and methods for using anti-PTK7 antibodies

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

Human monoclonal antibodies to protein tyrosine kinase 7 ( PTK7 ) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

HUMAN MONOCLONAL ANTIBODIES FOR PROTEINTYROSINKINASE 7 (PTK7) AND THEIR USE

Human monoclonal antibodies against the protein Tyrosine Kinase 7 (PTK7) and its use

Un anticuerpo monoclonal humano aislado, o una porción de unión al antígeno del mismo, en donde el anticuerpo: (a) se une específicamente a PTK7 humana; y (b) se une a la línea celular tumoral de Wilms que tiene el Núm. de Acc. ATCC CRL-1441 con una CE50 de 4,0 nM o menos, en un análisis que comprende la incubación de 1 x 105 células con el anticuerpo a una concentración de partida de 30 μg/ml y la dilución seriada del anticuerpo a una dilución 1:10, y (c) se une al mismo epítopo en PTK7 humana como un anticuerpo de referencia que comprende: (i) una región variable de la cadena pesada que comprende la secuencia de aminoácidos del SEQ ID NO: 2 y 10 una región variable de la cadena ligera que comprende la secuencia de aminoácidos del SEQ ID NO: 7; o (ii) una región variable de la cadena pesada que comprende la secuencia de aminoácidos del SEQ ID NO: 3 y una región variable de la cadena ligera que comprende la secuencia de aminoácidos del SEQ ID NO: 8; o (iii) una región variable de la cadena pesada que comprende la secuencia de aminoácidos del SEQ ID NO: 4 y una región variable de la cadena ligera que comprende la secuencia de aminoácidos del SEQ ID NO: 10. An isolated human monoclonal antibody, or an antigen binding portion thereof, wherein the antibody: (a) specifically binds to human PTK7; and (b) binds to the Wilms tumor cell line that has Acc. No. ATCC CRL-1441 with an EC50 of 4.0 nM or less, in an analysis comprising incubation of 1 x 105 cells with the antibody at a starting concentration of 30 μg / ml and the serial dilution of the antibody at a 1:10 dilution, and (c) binds to the same epitope in human PTK7 as a reference antibody comprising: (i) a variable region of the heavy chain comprising the amino acid sequence of SEQ ID NO: 2 and 10 a variable region of the light chain comprising the amino acid sequence of SEQ ID NO: 7; or (ii) a variable region of the heavy chain comprising the amino acid sequence of SEQ ID NO: 3 and a variable region of the light ...

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

Humane monoklonale antistoffer mot protein tyrosin kinase 7 (PTK7) og fremgangsmater for anvendelse av anti-PTK7 antistoffer

Foreliggende oppfinnelse tilveiebringer isolerte monoklonale antistoffer, spesielt humane monoklonale antistoffer, som binder spesifikt til PTK7 med høy affinitet. Nukleinsyremolekyler som koder for antistoffene ifølge oppfinnelsen, ekspresjonsvektorer, vertsceller og fremgangsmåter for ekspresjon av antistoffene ifølge oppfinnelsen er også fremskaffet. Immunkonjugater, bispesifikke molekyler og farmasøytiske sammensetninger omfattende antistoffene ifølge oppfinnelsen er også fremskaffet. Foreliggende oppfinnelse tilveiebringer også fremgangsmåter for deteksjon av PTK7, så vel som fremgangsmåter for behandling av ulike sykdommer, omfattende kreft og infeksjonssykdommer, ved anvendelse av anti-PTK7-antistoffer.

Human monoclonal antibodies to protein tyrosine kinase 7 (PTK7) and methods for using anti-PTK7 antibodies

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

Anticorpos monoclonais humanos para a proteína tirosinacinase 7 (ptk7) e sua utilização

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

Izolovano humano monoklonsko antitelo, ili njegov antigen-vezujući deo, pri čemu se antitelo:(a) specifično vezuje za humani PTK7; i(b) vezuje za ćelijsku liniju Wilmsovog tumora koja ima ATCC Acc No. CRL-1441 sa vrednosšću EC50 od 4.0 nM ili manjom, u testu koji podrazumeva inkubaciju 1 x 105 ćelija sa antitelom u početnoj koncentraciji od 30μg/ml i serijskim razblaženjima antitela od 1:10 diluciji; i(c) vezuje za isti epitop na humanom PTK7 kao i referentno antitelo, imajući:(i) varijabilni region teškog lanca koji sadrži amino kiselinsku sekvencu SEQ IDNO:2 i varijabilni region lakog lanca koji sadrži amino kiselinsku sekvencu SEQ ID NO:7; ili(ii) varijabilni region teškog lanca koji sadrži amino kiselinsku sekvencu SEQ ID NO:3 i varijabilni region lakog lanca koji sadrži amino kiselinsku sekvencu SEQ ID NO:8; ili(iii) varijabilni region teškog lanca koji sadrži amino kiselinsku sekvencu SEQ ID NO:4 i varijabilni region lakog lanca koji sadrži amino kiselinsku sekvencu SEQ ID NO:10.Prijava sadrži još 12 patentnih zahteva. An isolated human monoclonal antibody, or antigen-binding portion thereof, wherein the antibody: (a) specifically binds to human PTK7; and (b) binds to a Wilms tumor cell line having ATCC Acc No. CRL-1441 with an EC50 value of 4.0 nM or less, in a test involving incubation of 1 x 105 cells with antibody at an initial concentration of 30μg / ml and serial dilutions of antibody of 1:10 dilution; and (c) binds to the same epitope on human PTK7 as the reference antibody, having: (i) a heavy chain variable region comprising the amino acid sequence of SEQ ID NO: 2 and a light chain variable region comprising the amino acid sequence of SEQ ID NO: 7; or (ii) a heavy chain variable region comprising the amino acid sequence of SEQ ID NO: 3 and a light chain variable region comprising the amino acid sequence of SEQ ID NO: 8; or (iii) a heavy chain variable region comprising the amino acid sequence of SEQ ID NO: 4 and a light chain variable region ...

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

Human monoclonal antibodies to protein tyrosine kinase 7 (PTK7) and their use

An antibody that binds to human protein tyrosine kinase 7 (PTK7) and comprises the heavy chain CDR1, CDR2 and CDR3 regions having SEQ ID NOs: 12, 16, and 20 respectively and the light chain CDR1, CDR2 and CDR3 regions having SEQ ID NOs: 25, 31 and 37. The antibody can be used to treat pancreatic or breast cancer.

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and methods for using anti-ptk7 antibodies

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 ( ptk7 ) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Human monoclonal antibodies to protein tyrosine kinase 7 ( PTK7 ) and their use

Human monoclonal antibodies to protein tyrosine kinase 7 (ptk7) and their use

The present invention provides isolated monoclonal antibodies, particularly human monoclonal antibodies, that specifically bind to PTK7 with high affinity. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for detecting PTK7, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PTK7 antibodies.

Monoclonal antibodies against glypican-3

Provided are isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to Glypican-3 with high affinity. Nucleic acid molecules encoding Glypican-3 antibodies, expression vectors, host cells and methods for expressing the Glypican-3 antibodies are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising Glypican-3 antibodies are also disclosed. Method for detecting Glypican-3, as well as methods for treating various Glypican-3 related conditions, including heptacellular cancer, are disclosed.

Monoclonal antibodies against glypican-3

The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to Glypican-3 with high affinity. Nucleic acid molecules encoding Glypican-3 antibodies, expression vectors, host cells and methods for expressing the Glypican-3 antibodies are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the Glypican-3 antibodies are also provided. Methods for detecting Glypican-3, as well as methods for treating various Glypican-3-related conditions, including hepatocellular cancer, are disclosed.

Anticuerpos monoclonales contra glipicano-3.

La presente invención se refiere a anticuerpos monoclonales aislados, particularmente anticuerpos monoclonales humanos que se enlazan específicamente a Glipicano-3 con alta afinidad. También se proporciona moléculas de acido nucleico que codifican anticuerpos Glipicano-3, ventores de expresión, células hospederas y métodos para expresar los anticuerpos Glipicano-3. También se proporcionan inmunoconjugados, moléculas biespecíficas y composiciones farmacéuticas que comprenden los anticuerpos Glipicano-2. Se describen métodos para detectar Glipicano-3 así como método para tratar varias condiciones relacionadas con Glipicano-3, que incluyen cáncer hepatocelular.

STACKING SYSTEM

A stacking system is disclosed and includes a circuit board, an integrated circuit, a voltage regulation module and a heat dissipation module. The integrated circuit and the voltage regulation module are opposite disposed on a first side and a second side of the circuit board. The heat dissipation module includes a first heat dissipation component and a second heat dissipation component located at a top surface of the integrated circuit and the bottom surface of the voltage regulation module. The second heat dissipation component includes a base and an extended arm. The base is in thermal contact with bottom surface of the voltage regulation module. The extended arm is extended from the base to the first heat dissipation component and in thermal contact with the first heat dissipation component.

Swivel hinge

A swivel hinge has a base plate, a first loop, a first rotating board, a second loop, a mounting member, a second rotating board, a pivot member, a third loop, a third rotating board, and a locking ring. When the display panel rotates relative to the main board in a same plane, the third rotating board will not rotate, only the first and second rotating boards rotate relative to the base plate and provide an anchor and limitation function. When a direction of a camera on the display is to be adjusted, the third rotating board rotates with the second rotating board, thus the camera can rotate according to the shooting angle.

Mobile phone cover hinge

A mobile phone cover hinge has a driven block slidably mounted in a sleeve that is securely received in the mobile phone body and a driving block rotatably mounted in the cover of the mobile phone. When the cover pivots in a first direction, the driving block pushes the driven block so as to compress the first spring received in the sleeve. When the cover pivots in a second direction opposite to the first direction, the compressed first spring will facilitate the cover to return to its original position.

Elastic hinge for a notebook computer

An elastic hinge for a notebook computer has an L-like seat secured on a body of the computer, with a hole of which a section is formed as a numeral “8”. A pintle has a first part extending through a barrel, and a second part extending through the hole of the seat. The barrel has two tubular portions for the pintle extending therethrough, and a plate extending from the tubular portions and secured on a monitor of the computer. A torsional spring is provided outside the second part. When a locking member of the computer is released, under the elastic force of the torsional spring, the pintle will be rotated to automatically raise the monitor about an angle of 30° relative to the body of the computer.

ANTI-HUMAN mIgA ANTIBODIES CAPABLE OF LYSING mIgA-B LYMPHOCYTES AND DECREASING IgA PRODUCTION

Disclosed herein is an anti-migis-α antibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, cause the lysis of mIgA-expressing B lymphocytes, and decrease IgA production by IgA-secreting B lymphocytes. Disclosed further is a pharmaceutical composition comprising the anti-migis-α antibody and a pharmaceutically acceptable carrier. Disclosed further is a method for lysing mIgA-expressing B lymphocytes and reducing IgA production in a human subject in vivo by employing an antibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, cause the lysis of mIgA-expressing B lymphocytes, and decrease IgA production by IgA-secreting B lymphocytes. Disclosed herein is also a method for treating a disease in a subject, comprising administering to the subject an antibody specific for the migis-α of human mα chain that can bind to mIgA on B lymphocytes, thereby lysing mIgA-expressing B lymphocytes and reducing IgA production in the immune system of the subject. In addition, Disclosed also is use of said anti-migis-α antibody or said fragment thereof for treating a disease in a subject that can benefit from the elimination of mIgA-expressing cells or the reduction of IgA antibodies in the immune system.

Hinge with an anti-bump feature

The hinge for a piece of portable electronic equipment with a cover and a base has a keyed pivot pin, a stationary leaf, a washer, a rotating positioning element, a stationary positioning element, a biasing member, and a fastener. The washer, rotating positioning element, stationary positioning element and biasing member are sequentially mounted on the keyed pivot pin and are held in place with the fastener. The rotating positioning element has detents corresponding to and simultaneously engaging protrusions on the stationary positioning element when the hinge is closed. Because the detents and protrusions are not symmetrically oriented respectively on the rotating and stationary positioning elements, the detents will only engage the protrusions in one position, a closed position. The protrusions on the stationary positioning element press against the rotating positioning element and hold the hinge open at any desired angle.