Selective precharging circuit for memory device with charging compensating structure

The invention discloses a storage device selective pre-charging circuit with a charging compensation structure. The selective pre-charging unit is composed of a pre-charging tube Mp1 and two or more than two bit line selection tube Mpi; the charging compensation unit is composed of a charging compensation tube Mp2 and a second phase inverter inv2; the source end of the pre-charging tube is connected to a power source and its leakage end is connected to an internal circuit; the pre-charging tube Mp1 is controlled by a pre-charging signal Fpre; one end of each bit line selection tube is connected to the bit line in a storage array and its another end is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2, the second phase inverter inv2 of the charging compensation unit as well as the input end of a first phase inverter inv2 in an output drive unit; the source end of the charging compensation tube Mp2 is connected to the power source and its leakage ...

Control circuit for randomization of overturning moment of register

The invention discloses a control circuit for the randomization of the overturning moment of a register. The randomization is realized by a signal timing sequence constraint condition computing method; and the randomization of the overturning moment of the register in a high-frequency clock domain relative to a low-frequency clock jump edge is realized by utilizing phase difference change among clock signals with different frequencies. The control circuit comprises two data transmission request under two different clock domains and a control unit of a response signal, wherein each request and the control unit of the response signal comprises two D triggers with functions of resetting and setting and a 2-input NOR gate.

GTL output circuit with auxiliary charging circuit

Network-on-chip oriented low delay router structure

The invention discloses a network-on-chip oriented low delay router structure, aiming to solve the problems that the existing router structure has relative large delay in forwarding fragments and can not make full use of storage resources in physical links. The invention consists of P numbered input units, P numbered output units and P numbered channel double buffer; each input unit consists of abuffer distributor, an input buffer and p numbered virtual output address queues; each output unit consists of a P:1 arbiter and a P:1 selector; the channel double buffer consists of a controller anda double buffer; the controller consists of a read pointer, a write pointer and a state machine; and the double buffer consists of two registers and a selector. The fragment transmission between routers adopts a ready-effective synchronous handshake protocol. By adopting the invention, both the delay in forwarding the fragments and the design complexity are reduced, the storage resources in the physical ...

Subword paralleling integer multiplying unit

The utility model discloses a sub-word parallel integer multiplier of which the data preprocessing module can extend the multiplicand and the multi-plicator as per the operator schema and the symbolic control signal, so as to produce four groups of the multiplicand and four groups of multi-plicator. The corrected value selection module can select and incorporate the corrected value according to the sign digit of the operator schema and the arithmetic product result. The input of the partial producing module comprises four groups of the multiplicand, four groups of multi-plicator and the control signal. The output thereof is the partial product. Each group of the partial producing module is composed of a group of the Booth encoding unit and a group of partial product selected cell; partial product compress tree mold block compress the partial product and the incorporated corrected value. The utility model has the simple structure and simplifies the algorithm as well as realizes the delay ...

Selective precharging circuit for memory device with charging compensating structure

The invention discloses a storage device selective pre-charging circuit with a charging compensation structure. The selective pre-charging unit is composed of a pre-charging tube Mp1 and two or more than two bit line selection tube Mpi; the charging compensation unit is composed of a charging compensation tube Mp2 and a second phase inverter inv2; the source end of the pre-charging tube is connected to a power source and its leakage end is connected to an internal circuit; the pre-charging tube Mp1 is controlled by a pre-charging signal Fpre; one end of each bit line selection tube is connected to the bit line in a storage array and its another end is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2, the second phase inverter inv2 of the charging compensation unit as well as the input end of a first phase inverter inv2 in an output drive unit; the source end of the charging compensation tube Mp2 is connected to the power source and its leakage ...

Multiple reading port register file level driving bit cell circuit

The invention discloses a multiple reading port register document level driving position unit circuit, which comprises a threestate memory body core unit composed of PMOS tube P1 and P2, NMOS tube N1, N2 and N3, a reading port unit, a writing port unit and a phase inverter link. The writing port unit is connected to the memory body core unit; the phase inverter link is composed of at least two phase inverters with different sizes; the input end of the phase inverter link is connected to the memory body core unit and its output end is connected to the reading port unit; the size of the phase inverter is gradually increased along the direction from the memory body core unit to the reading port unit. Therefore, the invention is able to reduce the driving load of core unit, reduce the size of core unit and ensure the correct reading of data.

Adjustment method of clock fifty percent idle percent based on phone mixing

The invention discloses a clock 50% duty ratio adjusting method which is based on phase systemization, steps are: (1) Pulse generating: source clock input is transmitted into narrow pulse signal by pulse generating circuit, frequency is kept; (2) half cycle delay: marrow pulse signal obtained in step (1) is delayed for half-cycle; (3) image delay: pulse signal delayed for half period is delayed for half period to obtain pulse signal whose period is a period from signal in step (1); (4) phase synthesizing: pulse signal in step (2) and step (3) are superposed to obtain pulse signal whose frequency is two times of source clock, clock signal whose phase is similar and duty ratio is 50% is as output signal. The invention can adjust 50% duty ratio for clock signal whose frequency and duty ratio are within definite range, capability of defend Voltage Temperatre interfere is strong, quality of clock wave output is high.

Network-on-chip oriented low delay router structure

The invention discloses a network-on-chip oriented low delay router structure, aiming to solve the problems that the existing router structure has relative large delay in forwarding fragments and can not make full use of storage resources in physical links. The invention consists of P numbered input units, P numbered output units and P numbered channel double buffer; each input unit consists of a buffer distributor, an input buffer and p numbered virtual output address queues; each output unit consists of a P:1 arbiter and a P:1 selector; the channel double buffer consists of a controller and a double buffer; the controller consists of a read pointer, a write pointer and a state machine; and the double buffer consists of two registers and a selector. The fragment transmission between routers adopts a ready-effective synchronous handshake protocol. By adopting the invention, both the delay in forwarding the fragments and the design complexity are reduced, the storage resources in the physical ...

GTL output circuit with auxiliary charging circuit

The invention discloses a GTL output circuit with auxiliary charging circuit, which includes input end IN, control end EO, NOT-AND gate NAND, charging tube NMOS, terminal resistance Z and output end, the control end connects with NOT-AND gate NAND via the first inverter INV1 and the second inverter INV2, and the input end connects the NOT-AND gate NAND via the third inverter INV3, and the NOT-AND gate NAND connects with the grid of driving tube NMOS via the fourth inverter INV4, the source pole of driving tube NMOS connects with ground, and the drain of driving tube NMOS connects with the output end OUT by terminal resistance Z, and said driving tube connects with auxiliary charging circuit in series, and the auxiliary charging circuit includes anti-phase delay cell and auxiliary charging tube PMOS, and the grip of said auxiliary charging tube PMOS connects with the grip of driving tube NMOS, and the drain of auxiliary charging tube PMOS connects with the terminal resistance Z, and the ...

Multiple reading port register file level driving bit cell circuit

The invention discloses a multiple reading port register document level driving position unit circuit, which comprises a threestate memory body core unit composed of PMOS tube P1 and P2, NMOS tube N1,N2 and N3, a reading port unit, a writing port unit and a phase inverter link. The writing port unit is connected to the memory body core unit; the phase inverter link is composed of at least two phase inverters with different sizes; the input end of the phase inverter link is connected to the memory body core unit and its output end is connected to the reading port unit; the size of the phase inverter is gradually increased along the direction from the memory body core unit to the reading port unit. Therefore, the invention is able to reduce the driving load of core unit, reduce the size ofcore unit and ensure the correct reading of data.

Band-gap reference source for realizing curvature correction through self-adaptive base current compensation

The invention relates to a band-gap reference source for realizing curvature correction through self-adaptive base current compensation, which is widely applied to various analog/digital-analogy hybrid integrated circuits, and the temperature stability of a reference voltage source/a current source determines the performance of the whole circuit. The equivalence (or proportion) of the current density of a triode collector is the basic condition for realizing band-gap reference, however, the shunting action of the base current of an emitter can affect the current density of the collector owning to essential attributes of a triode fluidic device, so as to affect the temperature stability of the band-gap reference. Aiming at the problem, the invention discloses a band-gap reference source which utilizes the self-adaptive base current compensation technology to realize the curvature correction, and the equivalence (or proportion) of the current density of the triode collector is ensured through ...

Adjustment method of clock fifty percent idle percent based on phase synthesis

The invention discloses a clock 50% duty ratio adjusting method which is based on phase systemization, steps are: (1) Pulse generating: source clock input is transmitted into narrow pulse signal by pulse generating circuit, frequency is kept; (2) half cycle delay: marrow pulse signal obtained in step (1) is delayed for half-cycle; (3) image delay: pulse signal delayed for half period is delayed for half period to obtain pulse signal whose period is a period from signal in step (1); (4) phase synthesizing: pulse signal in step (2) and step (3) are superposed to obtain pulse signal whose frequency is two times of source clock, clock signal whose phase is similar and duty ratio is 50% is as output signal. The invention can adjust 50% duty ratio for clock signal whose frequency and duty ratioare within definite range, capability of defend Voltage Temperatre interfere is strong, quality of clock wave output is high.

Low-overhead transient fault automatic correction circuit for high speed adder

Transient faults in a combinational logic become a major challenge for the VLSI (very large scale integrated circuit) design. As a typical component in the combinational logic, an adder is widely applied to an arithmetic unit. The invention discloses a low-overhead transient fault automatic correction circuit for a high speed adder. According to the structure, through developing the abundant inherent hardware redundancy and time redundancy existing in the adder circuit, automatic correction on the transient faults in the high speed adder can be realized with lower overhead, thus the fault-tolerant area and performance overheads can be obviously reduced; and through combining a fault correction technology based on a C unit and the inherent hardware redundancy and time redundancy, the transient fault correction capacity of the adder can be further enhanced. The adder provided by the invention has preferably compromised area-delay overhead compared with other structures.

High-gain onchip dipole antenna pair transmission structure for epitaxially growing diamond medium on silicon

An onchip dipole antenna can be widely applied to onchip or chip-to-chip wireless connection of a CMOS (Complementary Metal Oxide Semiconductor) chip, and the performance of a wireless interconnection system depends on the transmission gain of the onchip dipole antenna. Though, at present, a substrate of the onchip dipole antenna integrated on a low-resistivity silicon substrate has overlarge loss and is easy to interfere by a heat-radiating metal, therefore, the transmission gain of the onchip dipole antenna is generally lower. Aiming at the problem, the invention discloses a high-gain onchip dipole antenna pair transmission structure for epitaxially growing a diamond medium on a low-resistivity silicon substrate, which ensures that the transmission gain of an onchip dipole antenna pair is greatly increased. An electromagnetic wave propagation path between onchip dipole antenna pairs after the diamond medium epitaxially grows on silicon is described in the invention in a detailed manner ...