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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 237. Отображено 165.
29-12-2022 дата публикации

Fin Field-Effect Transistor Device and Method of Forming

Номер: US20220415715A1
Автор: Jeng-Wei Yu, Yi-Fang Pai, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

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Номер записи: 1
02-04-2020 дата публикации

FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20200105606A1
Автор: Tzu-Ching Lin, Chien-Chih Lin, Feng-Ching Chu, Li-Li Su, Chii-Horng Li, LIN TZU-CHING, LIN CHIEN-CHIH, CHU FENG-CHING, SU LI-LI, LI CHII-HORNG, Lin, Tzu-Ching, Lin, Chien-Chih, Chu, Feng-Ching, Su, Li-Li, Li, Chii-Horng
Принадлежит:

A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin adjacent to the gate structure; and forming a source/drain region in the recess, the source/drain region including a first layer, a second layer, and a third layer, where forming the source/drain region includes performing a first epitaxy process under first process conditions to form the first layer in the recess, the first layer extending along surfaces of the fin exposed by the recess; performing a second epitaxy process under second process conditions to form the second layer over the first layer; and performing a third epitaxy process under third process conditions to form the third layer over the second layer, the third layer filling the recess, where the first processing conditions, the second process conditions and the third process conditions are different. 1. A method of forming a semiconductor device , the method comprising:forming a fin protruding above a substrate;forming a gate structure over the fin;forming a recess in the fin adjacent to the gate structure; and performing a first epitaxy process under first process conditions to form the first layer in the recess, the first layer extending along surfaces of the fin exposed by the recess;', 'performing a second epitaxy process under second process conditions to form the second layer over the first layer; and', 'performing a third epitaxy process under third process conditions to form the third layer over the second layer, the third layer filling the recess, wherein the first processing conditions, the second process conditions and the third process conditions are different., 'forming a source/drain region in the recess, the source/drain region comprising a first layer, a second layer, and a third layer, wherein forming the source/drain region comprises2. The method of claim 1 , wherein the first layer claim 1 , the second layer claim 1 , and ...

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Номер записи: 2
01-12-2022 дата публикации

Epitaxy Regions with Large Landing Areas for Contact Plugs

Номер: US20220384437A1
Автор: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
Принадлежит:

A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

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Номер записи: 3
03-10-2023 дата публикации

Wafer susceptor with improved thermal characteristics

Номер: US0011773506B2
Автор: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Company, Ltd.

An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface. Alternatively, the substrate-retaining device includes a base portion having a circular surface and a cylindrical surface extending from the circular surface, where a ring portion having the contact ...

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Номер записи: 4
01-09-2020 дата публикации

V-shape recess profile for embedded source/drain epitaxy

Номер: US0010763366B2
Автор: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

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Номер записи: 5
17-11-2022 дата публикации

Semiconductor Device and Method

Номер: US20220367690A1
Автор: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
Принадлежит:

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

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Номер записи: 6
02-04-2020 дата публикации

Method of Epitaxy and Semiconductor Device

Номер: US20200105526A1
Автор: Chih-Yun Chin, Tzu-Hsiang Hsu, Yen-Ru Lee, Chii-Horng Li, CHIN CHIH-YUN, HSU TZU-HSIANG, LEE YEN-RU, LI CHII-HORNG, Chin, Chih-Yun, Hsu, Tzu-Hsiang, Lee, Yen-Ru, Li, Chii-Horng
Принадлежит:

A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer. 1. A transistor comprising a source-drain region , the source-drain region comprising:a first layer wherein a first average silicon content is between about 80% and 100%,a second layer wherein a second average silicon content is between zero and about 90% the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer,a third layer wherein a third average silicon content is between about 80% and 100%, anda fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.2. The transistor of claim 1 , wherein said transistor is a FinFET.3. The transistor of claim 2 , wherein the FinFET is p-type.4. The transistor of claim 1 , wherein at least one of the second and fourth layers is silicon germanium.5. The transistor of claim 1 , wherein a first average germanium content of the first layer is between zero and about 20% claim 1 ,a second average germanium content of the second layer is between about 10% and 100%, the second ...

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Номер записи: 7
04-08-2022 дата публикации

SOURCE/DRAIN REGIONS AND METHODS OF FORMING SAME

Номер: US20220246479A1
Автор: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
Принадлежит:

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

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Номер записи: 8
05-11-2019 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0010468482B2
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin, LEE YEN-RU, LI CHII-HORNG, KUO CHIEN-I, TING HENG-WEN, TAI JUNG-CHI, SU LI-LI, LIN TZU-CHING, Lee, Yen-Ru, Li, Chii-Horng, Kuo, Chien-I, Ting, Heng-Wen, Tai, Jung-Chi, Su, Li-Li, Lin, Tzu-Ching
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.

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Номер записи: 9
05-12-2013 дата публикации

Methods for Forming MOS Devices with Raised Source/Drain Regions

Номер: US20130323893A1
Автор: Harry-Hak-Lay Chuang, Sin-Hua Wu, Chung-Hau Fei, Ming Zhu, Bao-Ru Young, Yen-Ru Lee, Chii-Horng Li, Tze-Liang Lee
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor. 1. A method comprising:forming a first gate stack of a first Metal-Oxide-Semiconductor (MOS) device over a semiconductor substrate;forming a second gate stack of a second MOS device over the semiconductor substrate, wherein the first and the second MOS devices are of opposite conductivity types;performing a first epitaxy to form a source/drain stressor for the a second MOS device, wherein the source/drain stressor is adjacent to the second gate stack; andperforming a second epitaxy to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack, and wherein the second silicon layer overlaps the source/drain stressor.2. The method of further comprising:forming a mask covering the first gate stack and the first portion of the semiconductor substrate; andbefore the second epitaxy, performing a third epitaxy to grow a third silicon layer using the mask as a mask, wherein the third silicon layer is overlying the source/drain stressor and underlying the second silicon layer.3. The method of claim 2 , wherein a vacuum break occurs between the second epitaxy and the third epitaxy.4. The method of further comprising claim 2 , when the third epitaxy is performed claim 2 , in-situ doping an impurity into the third silicon ...

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Номер записи: 10
26-10-2023 дата публикации

FETS and Methods of Forming FETS

Номер: US20230343635A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
Принадлежит:

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

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Номер записи: 11
15-08-2019 дата публикации

FETS and Methods of Forming FETS

Номер: US20190252240A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
Принадлежит:

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate. 1. A semiconductor device comprising:a raised portion of a substrate, the raised portion of the substrate having a first top surface higher than a second top surface of the substrate;a first fin extending from the raised portion of the substrate, the first fin comprising a first semiconductor material;a second fin extending from the raised portion of the substrate, the second fin being adjacent the first fin, the second fin comprising the first semiconductor material;a first isolation region on the first top surface of the raised portion of the substrate and between the first fin and the second fin;a second isolation region along opposing sidewalls of the raised portion of the substrate;a first epitaxial region over the first fin, the first epitaxial region comprising a second semiconductor material different than the first semiconductor material, the first epitaxial region extending lower than an upper surface of the first isolation region;a second epitaxial region over the second fin, the second epitaxial region comprising the second semiconductor material, the second epitaxial region extending lower than the upper surface of the first isolation region;a gate structure along sidewalls and over upper surfaces of the first fin and the second fin; anda source/drain region in the first epitaxial region and the second epitaxial region.2. The semiconductor device of claim 1 , wherein the first epitaxial region is ...

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Номер записи: 12
27-10-2022 дата публикации

LOW GE ISOLATED EPITAXIAL LAYER GROWTH OVER NANO-SHEET ARCHITECTURE DESIGN FOR RP REDUCTION

Номер: US20220344516A1
Автор: Yan-Ting Lin, Yen-Ru Lee, Chien-Chang Su, Chih-Yun Chin, Chien-Wei Lee, Pang-Yen Tsai, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

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Номер записи: 13
20-05-2014 дата публикации

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

Номер: US0008728900B2
Автор: Harry Chuang, Mong-Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li, CHUANG HARRY, LIANG MONG-SONG, YANG WEN-CHIH, CHEN CHIEN-LIANG, LI CHII-HORNG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

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Номер записи: 14
14-09-2017 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20170263771A1
Автор: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok, LI CHII-HORNG, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, KWOK TSZ-MEI, Li Chii-Horng, Sung Hsueh-Chang, Li Kun-Mu, Lee Tze-Liang, Kwok Tsz-Mei
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;a first silicon germanium region having a first germanium percentage and disposed in the semiconductor substrate adjacent the gate stack;a capping layer over the first silicon germanium region, wherein the capping layer has a lower germanium percentage than the first silicon germanium region; anda silicide region extending into the capping layer, wherein the silicide region comprises a higher a germanium percentage than the capping layer.2. The integrated circuit structure of further comprising a second silicon germanium region under the first silicon germanium region claim 1 , wherein the second silicon germanium region has a lower germanium percentage than the first silicon germanium region claim 1 , and wherein the first silicon germanium region is disposed between the second silicon germanium region and the capping layer along a direction perpendicular to a major surface of the semiconductor substrate.3. The integrated circuit structure of claim 2 , wherein the second silicon germanium region has a lower p-type impurity concentration than the first silicon germanium region.4. The integrated circuit structure of claim 1 , wherein the capping layer has a higher p-type ...

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Номер записи: 15
31-08-2023 дата публикации

Transistor Source/Drain Regions and Methods of Forming the Same

Номер: US20230275123A1
Автор: Wei-Min Liu, Tsz-Mei Kwok, Hui-Lin Huang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.

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Номер записи: 16
09-04-2020 дата публикации

Semiconductor Device Convex Source/Drain Region

Номер: US20200111712A1
Автор: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su, LIN TZU-CHING, LI CHII-HORNG, KUO CHIEN-I, SU LI-LI, Lin, Tzu-Ching, Li, Chii-Horng, Kuo, Chien-I, Su, Li-Li
Принадлежит:

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas. 1. A semiconductor device comprising:a first fin on a substrate, the first fin having a first sidewall;a second fin on the substrate and neighboring the first fin, the second fin having a second sidewall, the first sidewall being on a side of the first fin opposite from the second fin, the second sidewall being on a side of the second fin opposite from the first fin;a gate structure over the first fin and the second fin; anda merged epitaxial source/drain region on and between the first fin and the second fin proximate the gate structure, wherein a top surface of the merged epitaxial source/drain region is convex extending continuously between a plane of the first sidewall and a plane of the second sidewall.2. The device of claim 1 , wherein the merged epitaxial source/drain region comprises:a first portion of the merged epitaxial source/drain region along a bottom surface and a side surface of a recess in the first fin and along a bottom surface and a side surface of a recess in the second fin; anda second portion of the merged epitaxial source/drain region over the first portion.3. The device of claim 2 , wherein the first portion of the merged epitaxial source/drain region has a raised height above and from a top surface of the first fin or the second fin claim 2 , the raised height being in a range of about 10 angstroms to about 70 angstroms.4. The device of further ...

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Номер записи: 17
07-02-2023 дата публикации

Source/drain structure for semiconductor device

Номер: US0011575026B2
Автор: Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee, Chih-Yun Chin, Chih-Hung Nien, Jing-Yi Yan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

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Номер записи: 18
16-11-2023 дата публикации

DOPING PROFILE FOR STRAINED SOURCE/DRAIN REGION

Номер: US20230369491A1
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
Принадлежит:

The present disclosure relates to an integrated chip. The integrated chip includes a gate structure arranged over a substrate and a source/drain region arranged within the substrate along a side of the gate structure. The source/drain region includes a first layer lining interior sidewalls and a horizontally extending surface of the substrate, and a second layer lining interior sidewalls and a horizontally extending surface of the first layer. The first layer has a dopant with a first dopant concentration that continually decreases from an outermost sidewall of the first layer facing the substrate to one of the interior sidewalls of the first layer.

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Номер записи: 19
22-01-2015 дата публикации

MOS Devices with Non-Uniform P-type Impurity Profile

Номер: US20150021688A1
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, SUNG HSUEH-CHANG, KWOK TSZ-MEI, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG
Принадлежит:

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack;a silicon germanium region in the opening, wherein the silicon germanium region has a first p-type impurity concentration; anda silicon cap substantially free from germanium over the silicon germanium region, wherein the silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.2. The integrated circuit structure of claim 1 , wherein a portion of the silicon germanium region is in contact with the silicon cap and the portion of the silicon germanium region has a highest p-type impurity concentration among all source and drain regions of a Metal-oxide-Semiconductor (MOS) device that comprises the silicon germanium region and the silicon cap.3. The integrated circuit structure of further comprising a silicide region extending into the silicon cap claim 1 , with the silicon cap comprising a first portion on a side of claim 1 , and at a same level as claim 1 , the silicide region.4. The integrated circuit structure of claim 3 , wherein the silicide region has a third p-type impurity concentration higher than the first p-type impurity concentration.5. The integrated circuit structure of further comprising a silicide region extending into the silicon ...

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Номер записи: 20
02-07-2015 дата публикации

Method to Reduce Etch Variation Using Ion Implantation

Номер: US20150187927A1
Автор: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses. 1. A method of forming a transistor device , comprising:forming first and second well regions within a semiconductor substrate, the first and second well regions having first and second etch rates, respectively, which are different from one another;selectively implanting dopants into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate; andetching both the first, selectively implanted well region and the second well region to form channel recesses having equal recess depths.2. The method of claim 1 , wherein the first well region has a first doping conductivity type and the second well region has a second doping conductivity type opposite the first doping conductivity type.3. The method of claim 2 , wherein the first well region is a p-well region and the dopants which are selectively implanted into the first well region comprise an n-type species to enhance the first etch rate.4. The method of claim 3 , wherein the n-type species that is selectively implanted into the first well region is arsenic or phosphorus.5. The method of claim 2 , wherein the first well region is a n-well region and the dopants which are selectively implanted into the first well region comprise a p-type species to retard the first etch rate.6. ...

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Номер записи: 21
15-12-2020 дата публикации

Semiconductor method and device

Номер: US0010867862B2
Автор: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, YEN CHENG-HSIUNG, MA TA-CHUN, SU CHIEN-CHANG, CHEN JUNG-JEN, JENG PEI-REN, LI CHII-HORNG, CHEN KEI-WEI, Yen, Cheng-Hsiung, Ma, Ta-Chun, Su, Chien-Chang, Chen, Jung-Jen, Jeng, Pei-Ren, Li, Chii-Horng, Chen, Kei-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

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Номер записи: 22
26-09-2013 дата публикации

Performing Enhanced Cleaning in the Formation of MOS Devices

Номер: US20130252392A1
Автор: Yu-Hung Cheng, Wu-Ping Huang, Chii-Horng Li, Tze-Liang Lee
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes etching a semiconductor substrate to form a recess, wherein the recess extends from a top surface of the semiconductor substrate into the semiconductor substrate. An enhanced cleaning is then performed to etch exposed portions of the semiconductor substrate. The exposed portions are in the recess. The enhanced cleaning is performed using process gases including hydrochloride (HCl) and germane (GeH4). After the enhanced cleaning, an epitaxy is performed to grow a semiconductor region in the recess.

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Номер записи: 23
27-08-2020 дата публикации

V-Shape Recess Profile for Embedded Source/Drain Epitaxy

Номер: US20200273993A1
Автор: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin, LI CHII-HORNG, CHEN CHIH-SHAN, TAI ROGER, LIN YIH-ANN, LEE YEN-RU, LIN TZU-CHING, Li, Chii-Horng, Chen, Chih-Shan, Tai, Roger, Lin, Yih-Ann, Lee, Yen-Ru, Lin, Tzu-Ching
Принадлежит:

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base. 1. A method of fabricating a semiconductor device , comprising:etching a portion of a fin of a FinFET device that is formed over a semiconductor material, thereby forming a recess in the semiconductor material; andepitaxially growing a source/drain of the FinFET device over the semiconductor material, wherein the source/drain is grown over, and fills in, the recess.2. The method of claim 1 , wherein after the epitaxially growing claim 1 , one or more voids are trapped between the source/drain and the semiconductor material.3. The method of claim 1 , wherein a portion of the source/drain filling the recess has a V-shape cross-sectional profile.4. The method of claim 3 , further comprising: forming a capping layer over the source/drain.5. The method of claim 4 , wherein the capping layer is formed on portions of the source/drain other than the portion filling the recess.6. The method of claim 1 , wherein the etching is performed such that a depth of the recess is greater than a maximum width of the recess.7. The method of claim 6 , wherein the depth is at least twice the maximum width.8. The method of claim 1 , further comprising: forming dielectric isolation structures before the etching claim 1 , wherein the recess is etched away from the dielectric isolation structures.9. The method of claim 8 , wherein the etching is performed such that a portion of the semiconductor material separates the recess from a nearest one of the dielectric isolation structures.10. The method of claim 8 , ...

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Номер записи: 24
25-07-2023 дата публикации

Semiconductor device and method for manufacture

Номер: US0011710777B2
Автор: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

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Номер записи: 25
23-06-2015 дата публикации

Performing enhanced cleaning in the formation of MOS devices

Номер: US0009064688B2
Автор: Yu-Hung Cheng, Wu-Ping Huang, Chii-Horng Li, Tze-Liang Lee, CHENG YU-HUNG, HUANG WU-PING, LI CHII-HORNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., CHENG YU-HUNG, HUANG WU-PING, LI CHII-HORNG, LEE TZE-LIANG, TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method includes etching a semiconductor substrate to form a recess, wherein the recess extends from a top surface of the semiconductor substrate into the semiconductor substrate. An enhanced cleaning is then performed to etch exposed portions of the semiconductor substrate. The exposed portions are in the recess. The enhanced cleaning is performed using process gases including hydrochloride (HCl) and germane (GeH4). After the enhanced cleaning, an epitaxy is performed to grow a semiconductor region in the recess.

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Номер записи: 26
30-01-2020 дата публикации

MOS DEVICES HAVING EPITAXY REGIONS WITH REDUCED FACETS

Номер: US20200035831A1
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, KWOK TSZ-MEI, Sung, Hsueh-Chang, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng, Kwok, Tsz-Mei
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. A semiconductor device comprising:a gate structure at a top surface of a semiconductor substrate; a first germanium comprising region;', 'a silicon germanium cap over the first germanium comprising region and above the semiconductor substrate, the silicon germanium cap having a lower germanium percentage than the first germanium comprising region; and, 'a source/drain region adjacent the gate structure, the source/drain region comprisinga silicide extending through the silicon germanium cap, wherein the silicide has a higher germanium percentage than the silicon germanium cap, and at least a portion of the silicide has a higher germanium percentage than a silicon percentage.2. The semiconductor device of further comprising a second germanium comprising region under the first germanium comprising region claim 1 , wherein the second germanium comprising region has a lower germanium concentration than the first germanium comprising region.3. The semiconductor device of claim 2 , wherein the first germanium comprising region contacts the silicon germanium cap claim 2 , and wherein a portion of the first germanium comprising region in contact with the silicon germanium cap has a highest germanium percentage among the first and the second germanium comprising regions.4. The semiconductor ...

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Номер записи: 27
13-02-2020 дата публикации

FETS and Methods of Forming FETS

Номер: US20200052098A1
Автор: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li, LIN TZU-CHING, KUO CHIEN-I, CHIANG WEI TE, LU WEI HAO, SU LI-LI, LI CHII-HORNG, Lin, Tzu-Ching, Kuo, Chien-I, Chiang, Wei Te, Lu, Wei Hao, Su, Li-Li, Li, Chii-Horng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

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Номер записи: 28
01-11-2018 дата публикации

CONTACT RESISTANCE CONTROL IN EPITAXIAL STRUCTURES OF FINFET

Номер: US20180315660A1
Автор: Cheng-Wen CHENG, Chii-Horng Li, Lilly Su, Tuoh Bin Ng, CHENG CHENG-WEN, LI CHII-HORNG, SU LILLY, NG TUOH BIN, CHENG, Cheng-Wen, Li, Chii-Horng, Su, Lilly, Ng, Tuoh Bin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other. 1. A semiconductor device , comprising:fin regions on a substrate;shallow trench isolation (STI) regions between the fin regions;a replacement gate structure over the fin regions and the STI regions;a merged epitaxial region; anda capping layer, on the merged epitaxial region, with a top surface having a distance between a highest point and a lowest point less than about 5 nm.2. The semiconductor device of claim 1 , wherein the capping layer is thicker along a [110] crystal direction of the capping layer than along a [001] or [111] crystal direction of the capping layer.3. The semiconductor device of claim 1 , wherein a thickness of the capping layer ranges from about 2 nm to about 7 nm.4. The semiconductor device of claim 1 , wherein the capping layer comprises an n-type epitaxial material.5. The semiconductor device of claim 1 , wherein the capping layer comprises silicon doped phosphorous with a phosphorous dopant concentration between about 1×10atoms/cmand about 1×10atoms/cm.6. The semiconductor device of claim 1 , wherein the merged epitaxial region comprises silicon doped ...

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Номер записи: 29
21-04-2015 дата публикации

Method of temperature determination for deposition reactors

Номер: US0009011599B2
Автор: Jhi-Cherng Lu, Jr-Hung Li, Chii-Horng Li, Pang-Yen Tsai, Bing-Hung Chen, Tze-Liang Lee, LU JHI-CHERNG, LI JR-HUNG, LI CHII-HORNG, TSAI PANG-YEN, CHEN BING-HUNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., LU JHI-CHERNG, LI JR-HUNG, LI CHII-HORNG, TSAI PANG-YEN, CHEN BING-HUNG, LEE TZE-LIANG, TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial ...

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Номер записи: 30
25-10-2022 дата публикации

Interfacial layer between Fin and source/drain region

Номер: US0011482620B2
Автор: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

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Номер записи: 31
15-06-2023 дата публикации

Nano-Structure Transistors with Air Inner Spacers and Methods Forming Same

Номер: US20230187524A1
Автор: Wei-Min Liu, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.

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Номер записи: 32
26-08-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD

Номер: US20210265350A1
Автор: Chih-Yun Chin, Yen-Ru Lee, Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Heng-Wen Ting, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess. 1. A method comprising:forming first devices in a first region of a substrate, wherein each first device has a first number of fins;forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins;forming first recesses in the fins of the first devices, wherein the first recesses have a first depth;after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth;growing a first epitaxial source/drain region in the first recesses; andgrowing a second epitaxial source/drain region in the second recess.2. The method of claim 1 , wherein the first number is less than the second number.3. The method of claim 2 , wherein the first number is one.4. The method of claim 1 , wherein each second device has four or more fins.5. The method of claim 1 , wherein the second depth is greater than the first depth.6. The method of claim 5 , wherein the second depth is between 5 nm and 20 nm greater than the first depth.7. The method of claim 1 , wherein forming the first recesses comprises performing a first ...

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Номер записи: 33
30-01-2020 дата публикации

Wafer Susceptor with Improved Thermal Characteristics

Номер: US20200032415A1
Автор: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li, LIN YI-HUNG, LI JR-HUNG, LU CHANG-SHEN, LEE TZE-LIANG, LI CHII-HORNG, Lin, Yi-Hung, Li, Jr-Hung, Lu, Chang-Shen, Lee, Tze-Liang, Li, Chii-Horng
Принадлежит:

An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface. Alternatively, the substrate-retaining device includes a base portion having a circular surface and a cylindrical surface extending from the circular surface, where a ring portion having the contact surface is disposed within the base portion. 1. An integrated circuit (IC) fabrication system comprising: a base portion having a bottom surface and a sidewall surface extending from the bottom surface and surrounding the bottom surface; and', 'a ring portion interfacing with the bottom surface and the sidewall surface of the base portion, wherein the ring portion includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting an outermost perimeter surface of the retained substrate., 'a substrate-retaining device configured to retain a substrate during an IC process, wherein the substrate-retaining device includes2. The IC fabrication system of claim 1 , wherein a first air gap is positioned between a first interface of the ring portion and the bottom surface of the base portion and a second interface of the ring portion and the sidewall surface of the base portion.3. The IC fabrication system of claim 2 , ...

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Номер записи: 34
09-08-2016 дата публикации

Semiconductor device and fabrication method thereof

Номер: US0009412868B2
Автор: Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Chii-Horng Li, Pang-Yen Tsai, Lilly Su, Yi-Hung Lin, Yu-Hung Cheng, LEE YEN-RU, YU MING-HUA, LEE TZE-LIANG, LI CHII-HORNG, TSAI PANG-YEN, SU LILLY, LIN YI-HUNG, CHENG YU-HUNG, Lee Yen-Ru, Yu Ming-Hua, Lee Tze-Liang, Li Chii-Horng, Tsai Pang-Yen, Su Lilly, Lin Yi-Hung, Cheng Yu-Hung
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.

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Номер записи: 35
02-04-2024 дата публикации

Semiconductor device

Номер: US0011948999B2
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.

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Номер записи: 36
22-04-2021 дата публикации

DOPING PROFILE FOR STRAINED SOURCE/DRAIN REGION

Номер: US20210119048A1
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, SUNG HSUEH-CHANG, KWOK TSZ-MEI, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, Sung, Hsueh-Chang, Kwok, Tsz-Mei, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng
Принадлежит:

The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

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Номер записи: 37
08-03-2016 дата публикации

Method to reduce etch variation using ion implantation

Номер: US0009281196B2
Автор: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

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Номер записи: 38
18-02-2010 дата публикации

Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors

Номер: US20100038692A1
Автор: Harry Chuang, Mong Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li, CHUANG HARRY, LIANG MONG SONG, YANG WEN-CHIH, CHEN CHIEN-LIANG, LI CHII-HORNG
Принадлежит:

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

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Номер записи: 39
09-02-2021 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0010916656B2
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, KWOK TSZ-MEI, Sung, Hsueh-Chang, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng, Kwok, Tsz-Mei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 40
26-12-2017 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0009853155B2
Автор: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok, LI CHII-HORNG, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, KWOK TSZ-MEI, Li Chii-Horng, Sung Hsueh-Chang, Li Kun-Mu, Lee Tze-Liang, Kwok Tsz-Mei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 41
19-02-2015 дата публикации

Germanium Barrier Embedded in MOS Devices

Номер: US20150048417A1
Автор: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee, KWOK TSZ-MEI, LI KUN-MU, SUNG HSUEH-CHANG, LI CHII-HORNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack;a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage;a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; anda third silicon germanium region over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.2. The integrated circuit structure of further comprising a silicon cap substantially free from germanium over the third silicon germanium region.3. The integrated circuit structure of further comprising a metal silicide region over and in contact with the silicon cap.4. The integrated circuit structure of claim 1 , wherein a difference between the second germanium percentage and the first germanium percentage is greater than about 10 percent.5. The integrated circuit structure of claim 1 , wherein a difference between the second ...

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Номер записи: 42
15-03-2016 дата публикации

Structure and method for semiconductor device

Номер: US0009287382B1
Автор: Yi-Jing Lee, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.

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Номер записи: 43
04-07-2017 дата публикации

Transistor strain-inducing scheme

Номер: US0009698243B2
Автор: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee, KWOK TSZ-MEI, SUNG HSUEH-CHANG, LI KUN-MU, LI CHII-HORNG, LEE TZE-LIANG, Kwok Tsz-Mei, Sung Hsueh-Chang, Li Kun-Mu, Li Chii-Horng, Lee Tze-Liang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

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Номер записи: 44
10-01-2019 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20190013405A1
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, KWOK TSZ-MEI, Sung, Hsueh-Chang, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng, Kwok, Tsz-Mei
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 120-. (canceled)21. A semiconductor device comprising:a semiconductor substrate;a gate structure; a first germanium comprising region;', 'a capping layer over the first germanium comprising region, the capping layer having a lower germanium percentage than the first germanium comprising region; and, 'a source/drain region adjacent the gate structure, the source/drain region comprisinga silicide extending through the capping layer, wherein a germanium percentage at a first point in the silicide is greater than a silicon percentage at the first point in the silicide.22. The semiconductor device of claim 21 , wherein a line extends from a second point outside of the silicide to the first point claim 21 , wherein the line is parallel to a major surface of the semiconductor substrate claim 21 , wherein a germanium percentage at the second point is lower than a silicon percentage at the second point.23. The semiconductor device of claim 21 , wherein the silicide extends higher than the first point in the silicide.24. The semiconductor device of claim 21 , wherein the source/drain region further comprises a second germanium comprising region under the first germanium comprising region claim 21 , wherein the second germanium comprising region has a lower germanium percentage than the first ...

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Номер записи: 45
01-12-2020 дата публикации

Method to reduce etch variation using ion implantation

Номер: US0010854729B2
Автор: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang, WANG TSAN-CHUN, FANG ZIWEI, LI CHII-HORNG, LEE TZE-LIANG, CHEN CHAO-CHENG, JANG SYUN-MING, Wang, Tsan-Chun, Fang, Ziwei, Li, Chii-Horng, Lee, Tze-Liang, Chen, Chao-Cheng, Jang, Syun-Ming
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

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Номер записи: 46
26-11-2019 дата публикации

Method to reduce etch variation using ion implantation

Номер: US0010490648B2
Автор: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang, WANG TSAN-CHUN, FANG ZIWEI, LI CHII-HORNG, LEE TZE-LIANG, CHEN CHAO-CHENG, JANG SYUN-MING, Wang, Tsan-Chun, Fang, Ziwei, Li, Chii-Horng, Lee, Tze-Liang, Chen, Chao-Cheng, Jang, Syun-Ming
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

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Номер записи: 47
24-02-2022 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20220059655A1
Автор: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
Принадлежит:

A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material. 1. A device comprising:a fin extending from a substrate;a gate stack over the fin; a first source/drain material having a germanium concentration of 30 to 50 atomic percent and having a thickness of less than 30 nm; and', 'a second source/drain material over the first source/drain material, the second source/drain material having a germanium concentration of 50 to 80 atomic percent and having a thickness of greater than 10 nm; and, 'a source/drain region in the fin adjacent the gate stack, the source/drain region comprisinga source/drain contact contacting the source/drain region.2. The device of claim 1 , wherein the first source/drain material comprises a first source/drain layer and a second source/drain layer over the first source/drain layer claim 1 , the first source/drain layer having a germanium concentration of 30 to 40 atomic percent and having a thickness of 1 to 10 nm claim 1 , the second source/drain layer having a germanium concentration of 40 to 50 atomic percent and a thickness of less than 25 nm.3. The device of claim 2 , wherein the first source/drain layer has a dopant concentration of less than 5×10atoms/cm claim 2 , wherein the second source/drain layer has a ...

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Номер записи: 48
11-05-2021 дата публикации

Semiconductor device convex source/drain region

Номер: US0011004745B2
Автор: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su, LIN TZU-CHING, LI CHII-HORNG, KUO CHIEN-I, SU LI-LI, Lin, Tzu-Ching, Li, Chii-Horng, Kuo, Chien-I, Su, Li-Li
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.

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Номер записи: 49
07-06-2016 дата публикации

Modulating germanium percentage in MOS devices

Номер: US0009362360B2
Автор: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee, KWOK TSZ-MEI, LI KUN-MU, SUNG HSUEH-CHANG, LI CHII-HORNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

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Номер записи: 50
24-11-2022 дата публикации

Interfacial Layer Between Fin and Source/Drain Region

Номер: US20220376049A1
Автор: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

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Номер записи: 51
06-09-2022 дата публикации

Semiconductor device and method

Номер: US0011437497B2
Автор: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Company, Ltd.

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

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Номер записи: 52
21-06-2022 дата публикации

Semiconductor method and device

Номер: US0011367660B2
Автор: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

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Номер записи: 53
30-11-2023 дата публикации

SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20230387273A1
Автор: Chia-Ao Chang, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

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Номер записи: 54
31-05-2018 дата публикации

ELONGATED SOURCE/DRAIN REGION STRUCTURE IN FINFET DEVICE

Номер: US20180151731A1
Автор: Wei-Yang Lee, Ting-Yeh Chen, Chii-Horng Li, Feng-Cheng Yang
Принадлежит:

A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region. 1. A semiconductor device comprising:a semiconductor substrate; andan n-type fin field effect transistor (FinFET) comprising:a fin structure;a gate stack comprising a gate dielectric and a gate electrode, the gate dielectric disposed in between the fin structure and the gate electrode; anda source/drain region comprising an epitaxial structure and an epitaxy coat covering the epitaxial structure, wherein the epitaxial structure is made of a material having a lattice constant larger than a channel region, and the epitaxy coat is made of a material having a lattice constant smaller than the channel region.2. The semiconductor device of claim 1 , wherein the epitaxy structure resembles an elongated bar extending along a <111> crystal orientation.3. The semiconductor device of claim 2 , wherein the epitaxy structure has a top portion claim 2 , and dopants from the epitaxy coat permeate into the top portion of the epitaxy structure.4. The semiconductor device of claim 3 , wherein the top portion of the epitaxy structure has a higher n-type stressor concentration than the remaining portion of the epitaxy structure.5. The semiconductor device of claim 3 , wherein the source/drain region shows a concentration gradient of the n-type stressor reducing gradually from the top portion.6. The semiconductor device of claim 1 , ...

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Номер записи: 55
22-11-2018 дата публикации

V-SHAPE RECESS PROFILE FOR EMBEDDED SOURCE/DRAIN EPITAXY

Номер: US20180337283A1
Автор: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin, LI CHII-HORNG, CHEN CHIH-SHAN, TAI ROGER, LIN YIH-ANN, LEE YEN-RU, LIN TZU-CHING, Li, Chii-Horng, Chen, Chih-Shan, Tai, Roger, Lin, Yih-Ann, Lee, Yen-Ru, Lin, Tzu-Ching
Принадлежит:

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base. 1. A semiconductor device , comprising:a semiconductor material;a source/drain of a transistor disposed over the semiconductor material;a first dielectric structure disposed over the semiconductor material; anda void disposed between the first dielectric structure and the source/drain.2. The semiconductor device of claim 1 , wherein the void contains air.3. The semiconductor device of claim 1 , wherein an upper surface of the first dielectric structure has a concave cross-sectional profile.4. The semiconductor device of claim 1 , further comprising: a second dielectric structure disposed over the semiconductor material claim 1 , wherein the second dielectric structure has a greater depth than the first dielectric structure.5. The semiconductor device of claim 4 , wherein a portion of the source/drain protrudes downwardly into the semiconductor material and is disposed between the first dielectric structure and the second dielectric structure.6. The semiconductor device of claim 5 , wherein the portion of the source/drain has a V-like cross-sectional profile.7. The semiconductor device of claim 5 , wherein at least a majority of a sidewall of the portion of the source/drain is free of being in direct physical contact with the second dielectric structure.8. The semiconductor device of claim 1 , wherein at least a portion of the void has an arched cross-sectional profile.9. The semiconductor device of claim 1 , further comprising: a capping layer disposed over the source/drain.10. The ...

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Номер записи: 56
04-08-2020 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0010734520B2
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, KWOK TSZ-MEI, Sung, Hsueh-Chang, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng, Kwok, Tsz-Mei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 57
23-11-2023 дата публикации

Source/Drain Regions and Methods of Forming Same

Номер: US20230377989A1
Автор: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
Принадлежит:

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

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Номер записи: 58
26-12-2023 дата публикации

Supportive layer in source/drains of FinFET devices

Номер: US0011855142B2
Автор: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

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Номер записи: 59
21-03-2024 дата публикации

SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES

Номер: US20240096958A1
Автор: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

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Номер записи: 60
28-08-2018 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0010062781B2
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok, SUNG HSUEH-CHANG, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, KWOK TSZ-MEI, Sung, Hsueh-Chang, Li, Kun-Mu, Lee, Tze-Liang, Li, Chii-Horng, Kwok, Tsz-Mei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 61
13-10-2022 дата публикации

Semiconductor Method and Device

Номер: US20220328358A1
Автор: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

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Номер записи: 62
15-06-2023 дата публикации

SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE

Номер: US20230187540A1
Автор: Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee, Chih-Yun Chin, Chih-Hung Nien, Jing-Yi Yan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

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Номер записи: 63
14-02-2023 дата публикации

Method for manufacturing semiconductor structure with enlarged volumes of source-drain regions

Номер: US0011581425B2
Автор: Tsung-Hsi Yang, Che-Yu Lin, Yi-Fang Pai, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.

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Номер записи: 64
09-08-2022 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0011411109B2
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 65
24-04-2018 дата публикации

Contact resistance control in epitaxial structures of finFET

Номер: US0009953875B1
Автор: Cheng-Wen Cheng, Chii-Horng Li, Lilly Su, Tuoh Bin Ng, CHENG CHENG-WEN, LI CHII-HORNG, SU LILLY, NG TUOH BIN, Cheng, Cheng-Wen, Li, Chii-Horng, Su, Lilly, Ng, Tuoh Bin
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.

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Номер записи: 66
05-03-2020 дата публикации

Semiconductor Device and Method of Forming Same

Номер: US20200075423A1
Автор: Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu, Chii-Horng Li, KWOK TSZ-MEI, YANG TSUNG-HSI, YU JENG-WEI, CHOU LI-WEI, YU MING-HUA, LI CHII-HORNG, Kwok, Tsz-Mei, Yang, Tsung-Hsi, Yu, Jeng-Wei, Chou, Li-Wei, Yu, Ming-Hua, Li, Chii-Horng
Принадлежит:

A semiconductor device includes a first semiconductor fin extending from a substrate, a first dielectric fin extending from the substrate adjacent a first side of the first semiconductor fin and a second dielectric fin extending from the substrate adjacent a second side of the first semiconductor fin, a first gate stack over and along sidewalls of the first semiconductor fin, the first dielectric fin, and the second dielectric fin, a first epitaxial source/drain region in the first semiconductor fin and extending from the first dielectric fin to the second dielectric fin, and an air gap between the first epitaxial source/drain region and the substrate, the air gap extending between the first dielectric fin and the second dielectric fin. 1. A method comprising:forming a semiconductor fin over a substrate;depositing a sacrificial layer over the semiconductor fin;depositing a first dielectric material over the sacrificial layer and over the substrate;removing the sacrificial layer, the remaining first dielectric material forming a first dielectric fin over the substrate, wherein the first dielectric fin is on a first side of the semiconductor fin;forming a first isolation region extending between the semiconductor fin and the first dielectric fin;forming a dummy gate structure over a first portion of the semiconductor fin;recessing a second portion of the semiconductor fin adjacent the dummy gate structure to form a first recess;performing an epitaxy process to form a epitaxial source/drain region in the first recess, wherein performing the epitaxy process forms an air gap between the epitaxial source/drain region and the first isolation region; anddepositing an insulating material over the epitaxial source/drain region, wherein after depositing the insulating material, an air gap is maintained between the epitaxial source/drain region and the first isolation region.2. The method of claim 1 , further comprising claim 1 , before performing the epitaxy process claim 1 , ...

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Номер записи: 67
21-06-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180175144A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.

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Номер записи: 68
04-03-2010 дата публикации

DUAL GATE STRUCTURE ON A SAME CHIP FOR HIGH-K METAL GATE TECHNOLOGY

Номер: US20100052072A1
Автор: Chii-Horng Li, Po-Nien Chen, Chung-Hau Fei, Chien-Liang Chen, Wen-Chih Yang, Harry Chuang, LI CHII-HORNG, CHEN PO-NIEN, FEI CHUNG-HAU, CHEN CHIEN-LIANG, YANG WEN-CHIH, CHUANG HARRY
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region.

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Номер записи: 69
03-03-2016 дата публикации

Wafer Susceptor with Improved Thermal Characteristics

Номер: US20160064268A1
Автор: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li
Принадлежит:

A substrate-retaining device with improved thermal uniformity is provided. In an exemplary embodiment, the substrate-retaining device includes a substantially circular first surface with a defined perimeter, a plurality of contact regions disposed at the perimeter, and a plurality of noncontact regions also disposed at the perimeter. The contact regions are interspersed with the noncontact regions. Within each of the noncontact regions, the first surface extends past where the first surface ends within each of the contact regions. In some such embodiments, each region of the plurality of contact regions includes a contact surface disposed above the first surface. 1. A substrate-retaining device comprising:a substantially circular first surface having a perimeter defined thereupon;a plurality of contact regions disposed at the perimeter; anda plurality of noncontact regions disposed at the perimeter and interspersed with the plurality of contact regions,wherein the contact regions extend above the noncontact regions towards a retained substrate,wherein the first surface within each of the noncontact regions extends past the first surface within each of the contact regions, andwherein a contact surface of each of the contact regions is configured to contact an edge of the retained substrate without contacting either of two surfaces of the retained substrate that extend from the edge.2. (canceled)3. The substrate-retaining device of claim 1 , wherein for each contact surface claim 1 , a portion radially outward is higher than a portion radially inward.4. The substrate-retaining device of further comprising a second surface extending from the first surface in each of the noncontact regions and claim 1 , within each of the contact regions claim 1 , extending from the respective contact surface.5. The substrate-retaining device of claim 4 , wherein the second surface terminates at a vertical location coplanar with a top surface of a retained substrate.6. The substrate- ...

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Номер записи: 70
02-03-2023 дата публикации

Semiconductor Devices and Methods of Manufacture

Номер: US20230064735A1
Автор: Chien-Wei Lee, Chii-Horng Li, Bang-Ting Yan, Bo-Yu Lai, Wei-Yang Lee, Chia-Pin Lin
Принадлежит:

Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

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Номер записи: 71
27-02-2018 дата публикации

V-shaped epitaxially formed semiconductor layer

Номер: US0009905646B2
Автор: Tsz-Mei Kwok, Ming-Hua Yu, Chii-Horng Li, KWOK TSZ MEI, YU MING HUA, LI CHII HORNG, Kwok Tsz-Mei, Yu Ming-Hua, Li Chii-Horng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.

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Номер записи: 72
01-05-2018 дата публикации

Honeycomb heaters for integrated circuit manufacturing

Номер: US0009960059B2
Автор: Yi-Hung Lin, Jr-Hung Li, Chii-Horng Li, Tze-Liang Lee, LIN YI-HUNG, LI JR-HUNG, LI CHII-HORNG, LEE TZE-LIANG, Lin, Yi-Hung, Li, Jr-Hung, Li, Chii-Horng, Lee, Tze-Liang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., LIN YI HUNG, LI JR HUNG, LI CHII HORNG, LEE TZE LIANG, TAIWAN SEMICONDUCTOR MFG CO LTD, Lin Yi-Hung, Li Jr-Hung, Li Chii-Horng, Lee Tze-Liang

A honeycomb heater includes a lamp housing having an outer edge that forms a partial circle. The lamp housing has an opening extending from a top surface to a bottom surface of the lamp housing. The opening further extends from the outer edge into a center region of the lamp housing. A plurality of lamps is distributed throughout the lamp housing, and is configured to emit light out of the top surface of the lamp housing.

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Номер записи: 73
21-09-2021 дата публикации

Semiconductor device convex source/drain region

Номер: US0011127637B2
Автор: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su, LIN TZU-CHING, LI CHII-HORNG, KUO CHIEN-I, SU LI-LI, Lin, Tzu-Ching, Li, Chii-Horng, Kuo, Chien-I, Su, Li-Li
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.

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Номер записи: 74
23-08-2016 дата публикации

Reducing variation by using combination epitaxy growth

Номер: US0009425287B2
Автор: Yu-Hung Cheng, Yi-Hung Lin, Tze-Liang Lee, Chii-Horng Li, CHENG YU-HUNG, LIN YI-HUNG, LEE TZE-LIANG, LI CHII-HORNG, Cheng Yu-Hung, Lin Yi-Hung, Lee Tze-Liang, Li Chii-Horng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

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Номер записи: 75
16-09-2014 дата публикации

Semiconductor device and fabrication method thereof

Номер: US0008835267B2
Автор: Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Chii-Horng Li, Pang-Yen Tsai, Lilly Su, Yi-Hung Lin, Yu-Hung Cheng, LEE YEN-RU, YU MING-HUA, LEE TZE-LIANG, LI CHII-HORNG, TSAI PANG-YEN, SU LILLY, LIN YI-HUNG, CHENG YU-HUNG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., LEE YEN-RU, YU MING-HUA, LEE TZE-LIANG, LI CHII-HORNG, TSAI PANG-YEN, SU LILLY, LIN YI-HUNG, CHENG YU-HUNG, TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.

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Номер записи: 76
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200035784A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin, LEE YEN-RU, LI CHII-HORNG, KUO CHIEN-I, TING HENG-WEN, TAI JUNG-CHI, SU LI-LI, LIN TZU-CHING, Lee, Yen-Ru, Li, Chii-Horng, Kuo, Chien-I, Ting, Heng-Wen, Tai, Jung-Chi, Su, Li-Li, Lin, Tzu-Ching
Принадлежит:

A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region. 1. A semiconductor device comprising:inter-device isolation structures; and a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin;', 'an intra-device isolation structure between the first semiconductor fin and the second semiconductor fin;', 'a source/drain structure comprising a first portion on the first semiconductor fin and comprising a second portion on the second semiconductor fin, wherein an air gap is between the intra-device isolation structure and the source/drain structure; and', 'a dielectric layer on the intra-device isolation structure, the dielectric layer extending continuously along an upper surface of the intra-device isolation structure from the first portion of the source/drain structure to the second portion of the source/drain structure, wherein upper surfaces of the inter-device isolation structures proximate to the crown active region are free of the dielectric layer., 'a crown active region between the inter-device isolation structures, wherein the crown ...

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Номер записи: 77
19-11-2019 дата публикации

Interfacial layer between fin and source/drain region

Номер: US0010483396B1
Автор: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu, CHIN CHIH-YUN, LI CHII-HORNG, LEE CHIEN-WEI, SUNG HSUEH-CHANG, TING HENG-WEN, TAI ROGER, JENG PEI-REN, HSU TZU-HSIANG, LEE YEN-RU, LIN YAN-TING, LIU DAVIE, Chin, Chih-Yun, Li, Chii-Horng, Lee, Chien-Wei, Sung, Hsueh-Chang, Ting, Heng-Wen, Tai, Roger, Jeng, Pei-Ren, Hsu, Tzu-Hsiang, Lee, Yen-Ru, Lin, Yan-Ting, Liu, Davie
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

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Номер записи: 78
17-06-2021 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20210184037A1
Автор: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. (canceled)2. A semiconductor device comprising:a first gate structure at a top surface of a semiconductor substrate;a second gate structure at the top surface of the semiconductor substrate;a source/drain region in the semiconductor substrate and between the first gate structure and the second gate structure, wherein the source/drain region comprises silicon germanium;a capping layer over the source/drain region; anda silicide, wherein a virtual line extending from the first gate structure to the second gate structure further extends through a portion of the capping layer and a portion of the silicide, and wherein the portion of the silicide that the virtual line extends through has a higher germanium concentration than the portion of the capping layer that the virtual line extends through.3. The semiconductor device of claim 2 , wherein the source/drain region comprises:a first germanium comprising region; anda second germanium comprising region over the first germanium comprising region, the second germanium comprising region having a greater concentration of germanium than the first germanium comprising region.4. The semiconductor device of claim 3 , wherein a germanium concentration of the second germanium comprising region is at least 45% at an interface between the capping layer ...

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Номер записи: 79
22-01-2015 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20150021696A1
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, SUNG HSUEH-CHANG, KWOK TSZ-MEI, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack;a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage;a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region comprises a portion in the opening, and wherein the second silicon germanium region has a second germanium percentage greater than the first germanium percentage; anda silicon cap substantially free from germanium over the second silicon germanium region.2. The integrated circuit structure of claim 1 , wherein the second silicon germanium region is in contact with the silicon cap claim 1 , and wherein a portion of the second silicon germanium region in contact with the silicon cap has a highest germanium percentage among the first and the second silicon germanium regions.3. The integrated circuit structure of further comprising a silicide region extending into the silicon cap claim 1 , with the silicon cap comprising a first portion on a side of claim 1 , and at a same level as claim 1 , the silicide region.4. The integrated ...

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Номер записи: 80
07-02-2013 дата публикации

Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors

Номер: US20130034946A1
Автор: Harry Chuang, Mong-Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li, CHUANG HARRY, LIANG MONG-SONG, YANG WEN-CHIH, CHEN CHIEN-LIANG, LI CHII-HORNG
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. 1. A method of forming an integrated circuit structure , the method comprising:forming a dielectric layer over a semiconductor substrate in a first region of the semiconductor substrate and a second region of the semiconductor substrate;forming a first layer over the dielectric layer in the first region and the second region;forming a second layer over the first layer in the second region, the second layer not being in the first region;patterning the first layer in the first region to form a first gate electrode of a first transistor device;patterning the first layer and the second layer in the second region to form a dummy gate of a second transistor device; andreplacing the dummy gate with a metal gate to form a second gate electrode for the second transistor device.2. The method of further comprising forming a resistor and a plate of a capacitor simultaneously with the patterning the first layer in the first region to form the first gate electrode.3. The method of further comprising:forming an additional dummy gate electrode of a third transistor device simultaneously with the second patterning; andreplacing the additional dummy gate with an additional metal gate to form a third gate electrode for the third transistor device, wherein the second transistor device and the ...

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Номер записи: 81
30-03-2017 дата публикации

Wafer Susceptor with Improved Thermal Characteristics

Номер: US20170088976A1
Автор: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li, LIN YI-HUNG, LI JR-HUNG, LU CHANG-SHEN, LEE TZE-LIANG, LI CHII-HORNG, Lin Yi-Hung, Li Jr-Hung, Lu Chang-Shen, Lee Tze-Liang, Li Chii-Horng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface. Alternatively, the substrate-retaining device includes a base portion having a circular surface and a cylindrical surface extending from the circular surface, where a ring portion having the contact surface is disposed within the base portion.

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Номер записи: 82
26-08-2021 дата публикации

FETS and Methods of Forming FETS

Номер: US20210265195A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
Принадлежит:

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate. 1. A semiconductor device comprising:a raised portion of a substrate, the raised portion of the substrate having a first top surface higher than a second top surface of the substrate;a first fin extending from the raised portion of the substrate, the first fin comprising a first semiconductor material;a second fin extending from the raised portion of the substrate, the second fin being adjacent the first fin, the second fin comprising the first semiconductor material;a first semiconductor layer on the first fin and a second semiconductor layer on the second fin, the first semiconductor layer and the second semiconductor layer having a first dopant concentration;a first isolation region on the first top surface of the raised portion of the substrate and between the first fin and the second fin;a second isolation region along opposing sidewalls of the raised portion of the substrate;a first epitaxial region over the first fin, the first epitaxial region comprising a second semiconductor material;a second epitaxial region over the second fin, the second epitaxial region comprising the second semiconductor material, wherein the first epitaxial region is merged with the second epitaxial region, wherein the first epitaxial region is on the first semiconductor layer and the second epitaxial region is on the second semiconductor layer, the first epitaxial region and the second epitaxial region having a second dopant ...

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Номер записи: 83
28-04-2022 дата публикации

Semiconductor Device and Method for Manufacture

Номер: US20220130979A1
Автор: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
Принадлежит:

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

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Номер записи: 84
10-09-2013 дата публикации

Method for fabricating a semiconductor device

Номер: US0008530316B2
Автор: Yu-Hung Cheng, Jhi-Cherng Lu, Ming-Hua Yu, Chii-Horng Li, Tze-Liang Lee, CHENG YU-HUNG, LU JHI-CHERNG, YU MING-HUA, LI CHII-HORNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., CHENG YU-HUNG, LU JHI-CHERNG, YU MING-HUA, LI CHII-HORNG, LEE TZE-LIANG, TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.

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Номер записи: 85
11-01-2018 дата публикации

Source and Drain Stressors with Recessed Top Surfaces

Номер: US20180012997A1
Автор: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

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Номер записи: 86
28-02-2017 дата публикации

Source and drain stressors with recessed top surfaces

Номер: US0009583483B2
Автор: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee, LI KUN-MU, KWOK TSZ-MEI, SUNG HSUEH-CHANG, LI CHII-HORNG, LEE TZE-LIANG, Li Kun-Mu, Kwok Tsz-Mei, Sung Hsueh-Chang, Li Chii-Horng, Lee Tze-Liang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

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Номер записи: 87
18-01-2024 дата публикации

SEMICONDUCTOR DEVICE AND METHOD

Номер: US20240021618A1
Автор: Chih-Yun Chin, Yen-Ru Lee, Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Heng-Wen Ting, Chii-Horng Li, Yee-Chia Yeo
Принадлежит:

A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess.

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Номер записи: 88
08-12-2015 дата публикации

MOS devices having epitaxy regions with reduced facets

Номер: US0009209175B2
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, SUNG HSUEH-CHANG, KWOK TSZ-MEI, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

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Номер записи: 89
06-09-2012 дата публикации

SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING

Номер: US20120225529A1
Автор: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, CHEN CHIEH-HAO, LIEN HAO-MING, LI SSU-YU, YEH JUN-LIN, LIN KANG-CHENG, HUANG KUO-TAI, LI CHII-HORNG, CHEN CHIEN-LIANG, FEI CHUNG-HAU, YANG WEN-CHIH, NG JIN-AUN, CHANG CHI HSIN, LIN CHUN MING, CHUANG HARRY
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

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Номер записи: 90
21-03-2017 дата публикации

MOS devices with non-uniform P-type impurity profile

Номер: US0009601619B2
Автор: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, SUNG HSUEH-CHANG, KWOK TSZ-MEI, LI KUN-MU, LEE TZE-LIANG, LI CHII-HORNG, Sung Hsueh-Chang, Kwok Tsz-Mei, Li Kun-Mu, Lee Tze-Liang, Li Chii-Horng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.

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Номер записи: 91
05-09-2017 дата публикации

Source and drain stressors with recessed top surfaces

Номер: US0009755077B2
Автор: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee, LI KUN-MU, KWOK TSZ-MEI, SUNG HSUEH-CHANG, LI CHII-HORNG, LEE TZE-LIANG, Li Kun-Mu, Kwok Tsz-Mei, Sung Hsueh-Chang, Li Chii-Horng, Lee Tze-Liang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

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Номер записи: 92
18-11-2014 дата публикации

Methods for forming MOS devices with raised source/drain regions

Номер: US0008889501B2
Автор: Harry-Hak-Lay Chuang, Sin-Hua Wu, Chung-Hau Fei, Ming Zhu, Bao-Ru Young, Yen-Ru Lee, Chii-Horng Li, Tze-Liang Lee, CHUANG HARRY-HAK-LAY, WU SIN-HUA, FEI CHUNG-HAU, ZHU MING, YOUNG BAO-RU, LEE YEN-RU, LI CHII-HORNG, LEE TZE-LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., CHUANG HARRY-HAK-LAY, WU SIN-HUA, FEI CHUNG-HAU, ZHU MING, YOUNG BAO-RU, LEE YEN-RU, LI CHII-HORNG, LEE TZE-LIANG, TAIWAN SEMICONDUCTOR MFG, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

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Номер записи: 93
05-03-2020 дата публикации

Semiconductor Method and Device

Номер: US20200075729A1
Автор: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, YEN CHENG-HSIUNG, MA TA-CHUN, SU CHIEN-CHANG, CHEN JUNG-JEN, JENG PEI-REN, LI CHII-HORNG, CHEN KEI-WEI, Yen, Cheng-Hsiung, Ma, Ta-Chun, Su, Chien-Chang, Chen, Jung-Jen, Jeng, Pei-Ren, Li, Chii-Horng, Chen, Kei-Wei
Принадлежит:

A device is manufactured by etching a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region. 1. A method of manufacturing a device , comprising:providing a substrate comprising silicon having a semiconductor fin protruding from a major surface;forming a liner and a shallow trench isolation (STI) region adjacent the semiconductor fin;depositing a cap over the semiconductor fin, wherein the resulting cap comprises a layer of crystalline silicon over the semiconductor fin and portions of amorphous silicon over the liner and STI region; andperforming an HCl etch bake process to remove the portions of amorphous silicon over the liner and the STI region.2. The method of claim 1 , wherein the semiconductor fin comprises SiGe.3. The method of claim 1 , wherein the liner comprises SiN or SiO.4. The method of claim 1 , wherein depositing a cap over the semiconductor fin takes place at a temperature of about 400° C. to about 470° C. and at a pressure of about 50 torr to about 200 torr.5. The method of claim 1 , wherein depositing a cap over the semiconductor fin is performed for a time interval between about 100 seconds to 200 seconds claim 1 , wherein the deposition is performed in an ambient comprising hydrogen.6. The method of claim 1 , wherein performing an HCl etch bake process comprises increasing the process temperature to about 550° C. to about 600° C.7. The method of claim 1 , wherein performing an HCl etch bake process comprises increasing the pressure to a range of from about 200 torr to about 500 ...

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Номер записи: 94
02-04-2020 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20200105876A1
Автор: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin, TING HENG-WEN, CHEN KEI-WEI, LI CHII-HORNG, JENG PEI-REN, SUNG HSUEH-CHANG, LEE YEN-RU, LIN CHUN-AN, Ting, Heng-Wen, Chen, Kei-Wei, Li, Chii-Horng, Jeng, Pei-Ren, Sung, Hsueh-Chang, Lee, Yen-Ru, Lin, Chun-An
Принадлежит:

A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material. 1. A method comprising:etching one or more semiconductor fins to form one or more recesses; and epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material comprising doped silicon germanium; and', 'conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material comprising doped silicon germanium and having a different composition than the first semiconductor material., 'forming source/drain regions in the one or more recesses, wherein the forming the source/drain regions comprises2. The method of claim 1 , wherein the one or more recesses comprises a first recess and a second recess claim 1 , wherein the first semiconductor material in the first recess merges with the first semiconductor material in the second recess during the epitaxially growing the first semiconductor material.3. The method of claim 2 , wherein the first semiconductor material comprises silicon germanium having an atomic percentage of germanium of 40 to 50 percent and a boron concentration of greater than 6×10atoms/cm.4 ...

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Номер записи: 95
30-06-2016 дата публикации

Structure and Method for Semiconductor Device

Номер: US20160190017A1
Автор: Yi-Jing Lee, Chii-Horng Li, Kun-Mu Li, Tze-Liang Lee, LEE YI-JING, LI CHII-HORNG, LI KUN-MU, LEE TZE-LIANG
Принадлежит:

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other. 1. A method of forming a semiconductor device , comprising:providing a semiconductor substrate with first and second device regions, wherein the first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions;etching a plurality of first recesses in the first S/D region and a plurality of second recesses in the second S/D regions;growing a first plurality of first epitaxial features in the first recesses and a second plurality of first epitaxial features in the second recesses; andgrowing a third plurality of second epitaxial features over the first plurality and a fourth plurality of second epitaxial features over the second plurality, wherein the first and third epitaxial features are different, and the second and fourth epitaxial features are different.2. The method of claim 1 , further comprising:growing a third epitaxial feature over the merged second epitaxial feature while keeping the fourth plurality separate from each other.3. The method of claim 2 , wherein each of the first claim 2 , second claim 2 , and third ...

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Номер записи: 96
26-10-2023 дата публикации

EPITAXIAL STRUCTURES GROWN ON MATERIAL WITH A CRYSTALLOGRAPHIC ORIENTATION OF {110}

Номер: US20230343819A1
Автор: Wei-Min Liu, Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo, Hui-Lin Huang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.

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Номер записи: 97
16-03-2017 дата публикации

FETS AND METHODS OF FORMING FETS

Номер: US20170076973A1
Автор: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Lilly Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li, LEE YEN-RU, LI CHII-HORNG, KUO CHIEN-I, SU LILLY, SU CHIEN-CHANG, TING HENG-WEN, TAI JUNG-CHI, LEE CHE-HUI, LI YING-WEI, Lee Yen-Ru, Li Chii-Horng, Kuo Chien-I, Su Lilly, Su Chien-Chang, Ting Heng-Wen, Tai Jung-Chi, Lee Che-Hui, Li Ying-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

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Номер записи: 98
13-08-2015 дата публикации

Modulating Germanium Percentage in MOS Devices

Номер: US20150228724A1
Автор: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate; a first silicon germanium region having a first germanium percentage; and', 'a second silicon germanium region having a second germanium percentage higher than the first germanium percentage, wherein the second silicon germanium region has a non-silicided portion proximate the first silicon germanium region and a silicided portion distal the first silicon germanium region, and having a non-silicided portion that extends at least partly along a sidewall of the silicided portion., 'a source region adjacent a first side of the gate stack, the source region including2. The integrated circuit of claim 1 , further comprising: a third silicon germanium region having a third germanium percentage equal to the first germanium percentage; and', 'a fourth silicon germanium region having a fourth germanium percentage equal to the second germanium percentage, wherein the fourth silicon germanium region has a second non-silicided portion proximate the third silicon germanium region and a second silicided portion distal the third silicon germanium region, and wherein the second non-silicided portion extends at least partly along a sidewall of the second silicided portion., 'a drain region adjacent a second side of the gate stack, the drain region ...

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Номер записи: 99
01-09-2016 дата публикации

MOS Device Having Source and Drain Regions With Embedded Germanium-Containing Diffusion Barrier

Номер: US20160254364A1
Автор: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee, KWOK TSZ-MEI, LI KUN-MU, SUNG HSUEH-CHANG, LI CHII-HORNG, LEE TZE-LIANG, Kwok Tsz-Mei, Li Kun-Mu, Sung Hsueh-Chang, Li Chii-Horng, Lee Tze-Liang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage. 1. A method comprising:forming a gate stack over a semiconductor substrate;forming an opening extending into the semiconductor substrate, wherein the opening is on a side of the gate stack;performing a first epitaxy to grow a first silicon germanium layer in the opening, wherein the first silicon germanium layer has a first germanium percentage;performing a second epitaxy to grow a second silicon germanium layer over the first silicon germanium layer, wherein the second silicon germanium layer has a second germanium percentage higher than the first germanium percentage; andperforming a third epitaxy to grow a third silicon germanium layer over the second silicon germanium layer, wherein the third silicon germanium layer has a third germanium percentage lower than the second germanium percentage, each of the first and the third silicon germanium layers having a continuously increased germanium percentage, with higher portions of each of the first and the third silicon germanium layers having germanium percentages higher than germanium percentages in respective lower portions.2. The method of further comprising:at a transition time from the first epitaxy to the second epitaxy, increasing a flow rate ratio of a flow rate of germanium-containing precursors to a ...

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Номер записи: 100
19-01-2012 дата публикации

METHOD OF TEMPERATURE DETERMINATION FOR DEPOSITION REACTORS

Номер: US20120012047A1
Автор: Chen Bing-Hung, Lee Tze-Liang, Li Chii-Horng, Li Jr-Hung, LU Jhi-Cherng, Tsai Pang-Yen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer. 1. A method of determining a temperature in a deposition reactor , comprising:a) depositing a first epitaxial layer of silicon germanium on a substrate;b) depositing a second epitaxial layer of silicon above the first epitaxial layer;c) measuring the thickness of the second epitaxial layer; andd) determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and a predetermined relationship between the thickness of the second epitaxial layer and the temperature in the deposition reactor.2. The method of claim 1 , further comprising:a) heating the deposition reactor; andb) generating a signal indicative of a temperature within the deposition reactor.3. The method of claim 2 , wherein the heating step includes:heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device.4. The method of claim 3 , further comprising:a) comparing the measured thickness ...

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Номер записи: 101
04-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20130082309A1
Автор: Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity. 1. A method for fabricating a semiconductor device , comprising:forming an isolation feature in a substrate;forming a gate stack over the substrate;forming a recess cavity in the substrate, wherein the recess cavity is horizontally positioned between the gate stack and the isolation feature;forming an epitaxial (epi) material in the recess cavity, wherein the epi material has a corner above the recess cavity; andproviding a treatment to redistribute at least a portion of the corner to be in the recess cavity.2. The method of claim 1 , further comprising:forming a cap layer over the epi material before the step of treatment.3. The method of claim 2 , wherein the cap layer is Si formed by an epi growth process.4. The method of claim 2 , wherein the cap layer is formed at a temperature lower than a temperature of the treatment.5. The method of claim 2 , the cap layer has a thickness not greater than about 5 nm.6. The method of claim 1 , wherein the epi material is SiGe.7. The method of claim 1 , wherein the epi material is formed at a temperature lower than a temperature of the treatment.8. The method of claim 1 , further comprising:forming a contact feature over the epi material after the treatment.9. The method of claim 1 , wherein the epi material has a (311) crystal plane after the treatment.10. The method of claim 1 , wherein the corner has a tip height ...

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Номер записи: 102
04-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20130084682A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, Lin Yi-Hung, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity. 1. A method for fabricating a semiconductor device , comprising:providing a substrate with a surface;forming an isolation feature in the substrate;forming a gate stack over the surface of the substrate;forming a recess cavity in the substrate, wherein the recess cavity is horizontally positioned between the gate stack and the isolation feature;forming an epitaxial (epi) material in the recess cavity, wherein the epi material has a corner above the recess cavity; andperforming an etching process to redistribute at least a portion of the corner to be in the recess cavity.2. The method of claim 1 , further comprising:forming a cap layer over the epi material before the step of etching.3. The method of claim 2 , wherein the cap layer is Si formed by an epi growth process.4. The method of claim 2 , wherein the step of etching is in-situ performed after forming the cap layer.5. The method of claim 1 , wherein the step of etching is performed using a chlorine-containing gas and a carrier gas.6. The method of claim 5 , wherein the chlorine-containing gas is Cland/or HCl.7. The method of claim 5 , wherein the carrier gas is Hand/or N.8. The method of claim 5 , wherein the chlorine-containing gas has a flow rate ranging from about 50 sccm to about 300 sccm and the carrier gas has a flow rate ranging from ...

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Номер записи: 103
16-05-2013 дата публикации

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

Номер: US20130122675A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Li Chii-Horng, LU Jhi-Cherng, Yu Ming-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle. 1. A method for fabricating a semiconductor device , comprising:growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure comprises forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device;forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer comprises forming the protection layer on the semiconductor particle; andremoving a portion of the protection layer, wherein removing the portion of the protection layer comprises fully removing the protection layer on the semiconductor particle and the semiconductor particle.2. The method of claim 1 , wherein growing the first semiconductor structure comprises:growing the first semiconductor structure on the surface of the substrate by homogeneous nucleation reactions; andforming the semiconductor particle on the second semiconductor structure by heterogeneous nucleation reactions.3. The method of claim 1 , wherein forming the ...

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Номер записи: 104
19-09-2013 дата публикации

STRAINED SEMICONDUCTOR DEVICE WITH FACETS

Номер: US20130244389A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Li Chii-Horng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiHCl, HCl, GeH, BH, and Has reaction gases. 1. A method for fabricating a semiconductor device , comprising:forming a gate stack over the major surface of a substrate;recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate; and{'sub': 2', '2', '4', '2', '6', '2, 'selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of from about 660 to 700° C. and under a pressure of from about 13 to 50 Torr, using SiHCl, HCl, GeH, BH, and Has reaction gases.'}2. The method of claim 1 , wherein the gate stack comprises at least one of a poly-silicon gate electrode or a metal gate electrode.3. The method of claim 1 , wherein the growth of the strained material is terminated before a top surface of the strained material grows above the major surface of the substrate.4. The method of claim 1 , wherein the growth of the strained material continues until a top surface of the strained material extends above the major surface of the substrate in one of the source and drain recess cavities.5. The method of claim 1 , wherein a ratio of a mass flow rate of the SiHClto a mass flow rate of the HCl is in the range of from about 0.8 to 1.5.6. The method of claim 1 , wherein a ratio of a mass flow rate of the SiHClto a mass flow rate of the GeHis in the range of from about 10 to 50.7. The ...

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Номер записи: 105
03-10-2013 дата публикации

Honey Cone Heaters for Integrated Circuit Manufacturing

Номер: US20130256292A1
Автор: Lee Tze-Liang, Li Chii-Horng, Li Jr-Hung, Lin Yi-Hung
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A honey cone heater includes a lamp housing having an outer edge that forms a partial circle. The lamp housing has an opening extending from a top surface to a bottom surface of the lamp housing. The opening further extends from the outer edge into a center region of the lamp housing. A plurality of lamps is distributed throughout the lamp housing, and is configured to emit light out of the top surface of the lamp housing. 1. An apparatus comprising: a lamp housing having an outer edge, wherein the outer edge forms a partial circle, wherein the lamp housing comprises an opening extending from a top surface to a bottom surface of the lamp housing, and wherein the opening extends from the outer edge into a center region of the lamp housing; and', 'a plurality of lamps distributed throughout the lamp housing, and is configured to emit light out of the top surface of the lamp housing., 'a honey cone heater comprising2. The apparatus of further comprising:a shaft penetrating through the center region of the lamp housing; anda susceptor over and connected to the shaft, wherein the shaft and the susceptor are configured to rotate.3. The apparatus of further comprising a spot lamp disposed in the opening claim 2 , wherein the spot lamp is configured to provide more heat to one region than to remaining regions of a wafer placed on the susceptor.4. The apparatus of claim 1 , wherein the lamp housing comprises:a first edge and a second edge facing the opening;a first pipe connected to spaces between the plurality of lamps through the first edge; anda second pipe connected to the spaces through the second edge, wherein the first and the second pipes are configured to conduct a coolant to flow through the spaces.5. The apparatus of claim 1 , wherein the lamp housing comprises a first edge and a second edge facing the opening claim 1 , wherein the first and the second edges form an angle between about 45 degrees and about 135 degrees.6. The apparatus of claim 1 , wherein the top ...

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Номер записи: 106
02-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200006533A1
Автор: Chen Jung-Jen, Chen Kei-Wei, Jeng Pei-Ren, Li Chii-Horng, Tsai Ji-Yin, Yeo Yee-Chia
Принадлежит:

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack. 1. A device comprising:a substrate;a first semiconductor region extending from the substrate, the first semiconductor region comprising silicon;a second semiconductor region on the first semiconductor region, the second semiconductor region comprising silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration;a gate stack on the second semiconductor region; andsource and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.2. The device of claim 1 , wherein edge portions of the first semiconductor region have a third germanium concentration claim 1 , a center portion of the first semiconductor region having a fourth germanium concentration less than the third germanium concentration.3. The device of claim 1 , wherein the gate stack comprises:a gate dielectric extending along the edge portions of the second semiconductor region and along a top surface of the second semiconductor region; anda gate electrode on the gate dielectric.4. The device of claim 1 , wherein the first semiconductor region has a first width claim 1 , the second semiconductor region has a ...

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Номер записи: 107
02-01-2020 дата публикации

Interfacial Layer Between Fin and Source/Drain Region

Номер: US20200006548A1
Автор: CHIN Chih-Yun, HSU Tzu-Hsiang, Jeng Pei-Ren, LEE CHIEN-WEI, Lee Yen-Ru, Li Chii-Horng, LIN YAN-TING, Liu Davie, SUNG Hsueh-Chang, Tai Roger, TING Heng-Wen
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium. 1. A method of manufacturing a semiconductor device , the method comprising:forming a fin and isolation regions on opposing sides of the fin, the fin protruding from a substrate;forming a dummy gate structure over the fin;forming a recess in the fin proximate the dummy gate structure;forming an interfacial layer in the recess, the interfacial layer comprising silicon germanium, wherein the interfacial layer has a silicon atomic percent content of about 90% or more; andgrowing an epitaxial source/drain region over the interfacial layer by epitaxial growth, wherein the interfacial layer completely separates the epitaxial source/drain region from the fin, wherein the interfacial layer has a higher silicon atomic percent content of silicon than the epitaxial source/drain region and the fin.2. The method of claim 1 , wherein a thickness of the interfacial layer is in a range from about 1 nm to about 4 nm.3. The method of claim 1 , wherein the interfacial layer encapsulates impurities on a surface of the fin.4. The method of claim 3 , wherein the impurities comprise chlorine claim 3 , oxygen claim 3 , carbon claim 3 , or fluorine.5. The method of claim 1 , wherein the interfacial layer has a surface roughness less than a surface of the recess.6. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a first fin and a second fin with an isolation region interposed between the first fin and the second fin;forming a dummy gate structure over the first fin and the second fin;forming a first recess in the first fin and a second recess in the second fin proximate ...

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Номер записи: 108
27-01-2022 дата публикации

Epitaxy Regions with Large Landing Areas for Contact Plugs

Номер: US20220028856A1
Автор: Chen Jui-Hsuan, KWOK Tsz-Mei, Li Chii-Horng, Pai Yi-Fang, Tai Jung-Chi, TING Heng-Wen, YANG Tsung-Hsi, Yen Cheng-Hsiung, Yeo Yee-Chia, Yu Jeng-Wei, Yu Ming-Hua
Принадлежит:

A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type. 1. A method comprising:forming a gate stack on a first portion of a semiconductor fin;removing a second portion of the semiconductor fin to form a recess; and performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer comprises straight-and-vertical edges; and', 'performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are of a same conductivity type., 'forming a source/drain region starting from the recess, wherein the forming the source/drain region comprises2. The method of claim 1 , wherein the straight-and-vertical edges are on (110) planes of the first semiconductor layer.3. The method of claim 1 , wherein the first semiconductor layer is grown from an underlying semiconductor strip claim 1 , with the underlying semiconductor strip being between opposing portions of shallow trench isolation regions claim 1 , and wherein a portion of the first semiconductor layer having the straight-and-vertical edges is wider than the underlying semiconductor strip.4. The method of claim 1 , wherein the source/drain region has a lower portion between opposing portions of shallow trench isolation regions claim 1 , and the straight-and-vertical edges belong to a portion of the first semiconductor layer ...

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Номер записи: 109
16-01-2020 дата публикации

METHOD TO REDUCE ETCH VARIATION USING ION IMPLANTATION

Номер: US20200020784A1
Автор: Chen Chao-Cheng, Fang Ziwei, Jang Syun-Ming, Lee Tze-Liang, Li Chii-Horng, Wang Tsan-Chun
Принадлежит:

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses. 1. A method of forming a transistor device , comprising:forming first and second doped regions within a semiconductor substrate, the first and second doped regions having first and second etch rates, respectively, which are different from one another for a pre-determined etch;selectively implanting dopant atoms into the first doped region to alter the first etch rate such that the altered first etch rate is substantially equal to the second etch rate; andetching both the first, selectively implanted doped region and the second doped region using the pre-determined etch to form recesses having equal recess depths.2. The method of claim 1 , further comprising:performing an epitaxial growth process to form one or more epitaxial layers having equal respective heights within the recesses.3. The method of claim 1 , wherein etching the first claim 1 , selectively implanted doped region and the second doped region removes substantially all of the selectively implanted dopants from the first selectively implanted doped region.4. The method of claim 1 , wherein the first doped region has a first doping type and the second doped region has a second claim 1 , opposite doping type.5. The method of claim 1 , wherein the first doped region has a first doping type at a first doping concentration and the ...

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Номер записи: 110
28-01-2016 дата публикации

Source/Drain Structures and Methods of Forming Same

Номер: US20160027877A1
Автор: Lee Tze-Liang, Lee Yi-Jing, Li Chii-Horng, Li Kun-Mu
Принадлежит:

The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack. The S/D feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer. The second semiconductor material layer is different to the first semiconductor material layer. The S/D also includes a third semiconductor material layer disposed over the second semiconductor material layer, which includes a tin (Sn) material. 1. A device comprising:a gate stack disposed over a substrate; a first semiconductor material layer;', 'a second semiconductor material layer disposed over the first semiconductor material layer, wherein the second semiconductor material layer is a different semiconductor material than the first semiconductor material layer; and', 'a third semiconductor material layer disposed over the second semiconductor material layer, wherein the third semiconductor material layer includes a tin (Sn) material., 'a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack, the feature including2. The device of claim 1 , wherein the first semiconductor material layer is completely embedded in the substrate.3. The device of claim 1 , wherein the first semiconductor material layer physically contacts the second semiconductor material layer claim 1 , andwherein the third semiconductor material layer physically contacts the second semiconductor material layer.4. The device of claim 1 , wherein:{'sub': x1', '1, 'the first semiconductor material layer includes epitaxially grown silicon germanium (SiGe), where xis Ge composition in atomic percent;'}{'sub': x1', 'x3', 'y', '2', '3, 'the second semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown epitaxially grown silicon germanium (SiGe) and ...

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Номер записи: 111
31-01-2019 дата публикации

Source and drain stressors with recessed top surfaces

Номер: US20190035931A1
Автор: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tsz-Mei Kwok, Tze-Liang Lee
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

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Номер записи: 112
12-02-2015 дата публикации

Modulating Germanium Percentage in MOS Devices

Номер: US20150041852A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY, LTD.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack;a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage;a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; anda metal silicide region over and in contact with the second silicon germanium region, wherein the second silicon germanium region comprises an upper portion on a side of, and is level with, the metal silicide region.2. The integrated circuit structure of further comprising:a silicon cap substantially free from germanium over the second silicon germanium region, wherein the metal silicide region penetrates through the silicon cap.3. The integrated circuit structure of claim 2 , wherein the second silicon germanium region has a first thickness claim 2 , and wherein the silicon cap has a second thickness greater than the first thickness.4. The integrated circuit structure of claim 1 , wherein the second silicon germanium region comprises a lower portion claim 1 , wherein a top surface of the lower portion is in ...

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Номер записи: 113
14-02-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20190051737A1
Автор: HSIAO Yang-Tai, KUO Chien-I, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tai Jung-Chi, TING Heng-Wen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a plurality of semiconductor fins, an epitaxy structure, a capping layer, and a contact. The epitaxy structure adjoins the semiconductor fins. The epitaxy structure has a plurality of protrusive portions. The capping layer is over a sidewall of the epitaxy structure. The contact is in contact with the epitaxy structure and the capping layer. The contact has a portion between the protrusive portions. The portion of the contact between the protrusive portions has a bottom in contact with the epitaxy structure. 1. A semiconductor device , comprising:a plurality of semiconductor fins;an epitaxy structure adjoining the semiconductor fins, wherein the epitaxy structure has a plurality of protrusive portions;a capping layer over a sidewall of the epitaxy structure; anda contact in contact with the epitaxy structure and the capping layer, wherein the contact has a portion between the protrusive portions, and said portion of the contact between the protrusive portions has a bottom in contact with the epitaxy structure.2. The semiconductor device of claim 1 , wherein the capping layer is conformal to the sidewall of the epitaxy structure.3. The semiconductor device of claim 1 , wherein the bottom of said portion of the contact between the protrusive portions is lower than an interface between the capping layer and the contact.4. The semiconductor device of claim 1 , wherein an entire top surface of the capping layer is in contact with the contact.5. The semiconductor device of claim 1 , wherein said portion of the contact between the protrusive portions tapers toward the epitaxy structure.6. The semiconductor device of claim 1 , further comprising:a first isolation structure between the semiconductor fins; anda second isolation structure and a third isolation structure, wherein the semiconductor fins are between the second isolation structure and the third isolation structure, and a bottom of the second isolation structure is lower than a ...

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Номер записи: 114
13-02-2020 дата публикации

V-Shape Recess Profile for Embedded Source/Drain Epitaxy

Номер: US20200052121A1
Автор: Chen Chih-Shan, Lee Yen-Ru, Li Chii-Horng, LIN TZU-CHING, Lin Yih-Ann, Tai Roger
Принадлежит:

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base. 1. A semiconductor device , comprising:a semiconductor material;an epi-layer disposed over the semiconductor material, wherein the epi-layer includes a protruding portion that protrudes into the semiconductor material, and wherein a lateral dimension of the protruding portion decreases as the protruding portion protrudes further into the semiconductor material; andan isolation structure disposed adjacent to the protruding portion of the epi-layer, wherein an upper surface of the isolation structure is disposed below an upper surface of the epi-layer.2. The semiconductor device of claim 1 , wherein the epi-layer is a source/drain of a transistor.3. The semiconductor device of claim 1 , wherein: a portion of the semiconductor material is disposed between the isolation structure and the protruding portion of the epi-layer.4. The semiconductor device of claim 3 , wherein the semiconductor material prevents a direct physical contact between the isolation structure and a substantial majority of a side surface of the protruding portion facing the isolation structure.5. The semiconductor device of claim 1 , wherein the protruding portion of the epi-layer has a cross-sectional profile that resembles a letter V.6. The semiconductor device of claim 1 , wherein a bottom surface of the isolation structure is disposed below a bottom surface of the protruding portion of the epi-layer.7. The semiconductor device of claim 1 , wherein the upper surface of the isolation structure is recessed downwardly.8. ...

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Номер записи: 115
05-03-2015 дата публикации

Source and Drain Stressors with Recessed Top Surfaces

Номер: US20150061024A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion. 1. An integrated circuit structure comprising:a semiconductor substrate;a first gate stack over the semiconductor substrate; anda first silicon germanium region extending into the semiconductor substrate and adjacent to the first gate stack, wherein the first silicon germanium region comprises a first top surface, with a center portion of the first top surface recessed from edge portions of the first top surface to form a recess, and wherein the edge portions are on opposite sides of the center portion.2. The integrated circuit structure of further comprising a silicon cap over the first silicon germanium region claim 1 , wherein the silicon cap is in physical contact with the first top surface.3. The integrated circuit structure of further comprising:a second gate stack over the semiconductor substrate;a second opening extending into the semiconductor substrate, wherein the second opening is adjacent to the second gate stack; anda second silicon germanium region in the second opening, wherein the second silicon germanium region comprises a second top surface, and wherein the second top surface does not have recessed center portions.4. The integrated circuit structure of claim 3 , wherein the first silicon germanium region is between the first gate stack and a third gate stack claim 3 , with no additional gate stack between the first gate stack and the third gate stack claim 3 , wherein the second silicon germanium region is between the second gate stack and a fourth gate stack claim 3 , with no additional gate stack between the first gate stack and the fourth gate ...

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Номер записи: 116
08-03-2018 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20180069123A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate structure on the semiconductor substrate;a silicon germanium region in the semiconductor substrate adjacent the gate structure, wherein an upper portion of the silicon germanium region has a higher germanium percentage than a lower portion of the silicon germanium region;a silicon-comprising capping layer over the silicon germanium region, wherein the silicon-comprising capping layer has a lower germanium percentage than the upper portion of the silicon germanium region; anda silicide extending through the silicon-comprising capping layer, wherein the silicide further extends below an interface between the silicon-comprising capping layer and the silicon germanium region.2. The integrated circuit structure of claim 1 , wherein silicide has a greater germanium percentage than the silicon-comprising capping layer.3. The integrated circuit structure of claim 1 , wherein the silicon-comprising capping layer and the silicon germanium region further each comprise p-type impurities.4. The integrated circuit structure of claim 3 , wherein a p-type impurity concentration of the silicon-comprising capping layer is greater than a p-type impurity concentration of the silicon germanium region.5. The integrated circuit ...

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Номер записи: 117
16-03-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170077222A1
Автор: KUO Chien-I, Lee Yen-Ru, Li Chii-Horng, LIN TZU-CHING, SU Lilly, Tai Jung-Chi, TING Heng-Wen
Принадлежит:

A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structure, and an epitaxy structure. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structure is disposed on the semiconductor fins. At least one void is present between the first isolation structure and the epitaxy structure. 1. A semiconductor device comprising:a substrate having a plurality of semiconductor fins therein;at least one first isolation structure disposed between the semiconductor fins;at least two second isolation structures, wherein the semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure; andan epitaxy structure disposed on the semiconductor fins, wherein at least one void is present between the first isolation structure and the epitaxy structure.2. The semiconductor device of claim 1 , wherein the epitaxy structure has a top surface claim 1 , and at least one portion of the top surface of the epitaxy structure is recessed.3. The semiconductor device of claim 1 , wherein the epitaxy structure has a bottom surface adjacent to the void claim 1 , and at least one portion of the bottom surface of the epitaxy structure is recessed to form the void.4. The semiconductor device of claim 1 , wherein the epitaxy structure has at least one groove therein.5. The semiconductor device of claim 1 , wherein the epitaxy structure comprises a plurality of epitaxy portions spaced from each other and respectively disposed on the semiconductor fins.6. The semiconductor device of claim 5 , wherein the epitaxy portions are facet shaped.7. The semiconductor ...

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Номер записи: 118
16-03-2017 дата публикации

FINFET DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20170077228A1
Автор: HSIAO Yang-Tai, KUO Chien-I, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tai Jung-Chi, TING Heng-Wen
Принадлежит:

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins. The source/drain structure has a top portion with a W-shape cross section for forming a contact landing region. The semiconductor device may further include a plurality of capping layers located on a plurality of recessed portions of the top portion. 1. A semiconductor device , comprising:a semiconductor substrate;a source structure located on the semiconductor substrate;a drain structure located on the semiconductor substrate; anda plurality of semiconductor fins protruding from the semiconductor substrate, wherein the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure;wherein each of the source structure and the drain structure has a top portion with a W-shape cross section for forming a contact landing region.2. The semiconductor device of claim 1 , wherein the top portion has a plurality of protrusive portions corresponding to the semiconductor fins in a one-to-one manner.3. The semiconductor device of claim 1 , wherein heights of the protrusive portions are greater than or equal to heights of the semiconductor fins.4. The semiconductor device of claim 1 , wherein the top portion comprises a plurality of recessed portions claim 1 , and each of the recessed portion has a side wall inclined at an angle relative to horizontal claim 1 , and the angle is in a range substantially from 30 degrees to 65 degrees.5. The semiconductor device of claim 1 , further comprising a plurality of capping layers located in a plurality of recessed portions of the top portion.6. The semiconductor device of claim 5 , wherein the capping layers comprise a low concentration III-V semiconductor claim 5 , and each of the source structure and the ...

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Номер записи: 119
16-03-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170077300A1
Автор: CHIN Chih-Yun, HSU Tzu-Hsiang, Lee Yen-Ru, Li Chii-Horng, TING Heng-Wen
Принадлежит:

A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile. 1. A semiconductor device comprising:a substrate having a plurality of semiconductor fins therein;at least one first isolation structure disposed between the semiconductor fins;at least two second isolation structures, wherein the semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure; anda plurality of epitaxy structures respectively disposed on the semiconductor fins, wherein the epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile.2. The semiconductor device of claim 1 , wherein said at least one of the epitaxy structures comprises:a top portion having a first width; anda body portion disposed between the top portion and one of the semiconductor fins, wherein the body portion has a second width shorter than the first width.3. The semiconductor device of claim 2 , wherein the top portion of said at least one of the epitaxy structures further has a height claim 2 , and a ratio of the height to the first width of the top portion ranges from about 0.5 to about 4.4. The semiconductor device of claim 2 , wherein the top portion is elliptic cylindrical shaped or cylindrical shaped.5. The ...

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Номер записи: 120
18-03-2021 дата публикации

Supportive Layer in Source/Drains of FinFET Devices

Номер: US20210083052A1
Автор: CHIN Chih-Yun, Jeng Pei-Ren, Lee Yen-Ru, Li Chii-Horng, LIN YAN-TING, Tai Jung-Chi
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content. 1. A method of manufacturing a semiconductor device , the method comprising:forming a fin on a substrate;forming a gate structure on the fin;patterning a plurality of recesses in the fin proximate the gate structure;forming a first source/drain in one of the pluralities of recesses in the fin, the first source/drain comprising a first bottom layer, a first supportive layer, and a first top layer; andforming a second source/drain in another one of the pluralities of recesses in the fin, the second source/drain comprising a second bottom layer, a second supportive layer, and a second top layer, wherein the first supportive layer and the second supportive layer have a different property than the first bottom layer, the first top layer, the second bottom layer, and the second top layer, the different property being selected from a group consisting of a different material, a different natural lattice constant, a different dopant concentration, and a different alloy percent content.2. The method of claim 1 , wherein the fin comprises silicon germanium.3. The method of claim 1 , wherein a height of the first source/drain and the second source/drain is in range from about 50 nm to about 100 nm.4. The method of claim 1 , wherein forming the first source/drain and the second source/drain comprises forming a first capping layer over the first top layer and a second capping layer over the second top layer.5. The method of claim 4 , ...

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Номер записи: 121
18-03-2021 дата публикации

METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND EPITAXIAL MATERIALS

Номер: US20210083115A1
Автор: Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит:

A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first gate stack over a substrate;etching the substrate to define a cavity;growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane;growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane; andtreating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.2. The method of claim 1 , further comprising forming an isolation structure in the substrate.3. The method of claim 2 , wherein etching the substrate comprises defining the cavity adjacent to the isolation structure.4. The method of claim 2 , wherein etching the substrate comprises exposing a sidewall of the isolation structure.5. The method of claim 1 , wherein treating the second epi material comprises heating the second epi material.6. The method of claim 5 , wherein heating the second epi material comprises heating the second epi material at a temperature ranging from about ...

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Номер записи: 122
22-03-2018 дата публикации

FETS and Methods of Forming FETS

Номер: US20180082883A1
Автор: Che-Hui Lee, Chien-Chang Su, Chien-I Kuo, Chii-Horng Li, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Yen-Ru LEE, Ying-Wei Li
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

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Номер записи: 123
24-03-2016 дата публикации

MOS Devices Having Epitaxy Regions with Reduced Facets

Номер: US20160087078A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 1. A method comprising:forming a gate stack over a semiconductor substrate;forming an opening extending into the semiconductor substrate, wherein the opening is on a side of the gate stack;performing a first epitaxy to grow a first silicon germanium region in the opening, wherein the first silicon germanium region has a first germanium percentage;performing a second epitaxy to grow a second silicon germanium region over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage greater than the first germanium percentage;performing a third epitaxy to grow a silicon cap substantially free from germanium over the second silicon germanium region; andforming a silicide region extending into the silicon cap, wherein the silicide region comprises a higher a germanium percentage than the silicon cap.2. The method of claim 1 , wherein a germanium percent is continuously and gradually increased during at least one of the first epitaxy and the second epitaxy.3. The method of further comprising claim 1 , during the third epitaxy claim 1 , in-situ doping a p-type impurity.4. The method of claim 1 , wherein during the third epitaxy claim 1 , no germanium is introduced into the silicon cap.5. The method of further comprising:after forming the ...

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Номер записи: 124
02-04-2015 дата публикации

Semiconductor device and fabrication method thereof

Номер: US20150091103A1
Автор: Chii-Horng Li, Lilly SU, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru LEE
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.

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Номер записи: 125
01-04-2021 дата публикации

Semiconductor Method and Device

Номер: US20210098308A1
Автор: Chen Jung-Jen, Chen Kei-Wei, Jeng Pei-Ren, Li Chii-Horng, Ma Ta-Chun, Su Chien-Chang, Yen Cheng-Hsiung
Принадлежит:

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region. 1. A semiconductor structure , comprising: a bottom fin portion, the bottom fin portion being a first semiconductor material;', 'a top fin portion on the bottom fin portion, the top fin portion being a second semiconductor material, the second semiconductor material being different from the first semiconductor material; and', 'a cap layer comprising a semiconductor material, the cap layer covering a top surface and sidewalls of the top fin portion;, 'a semiconductor fin, comprisinga liner covering a lower portion of a sidewall of the bottom fin portion, a top surface of the liner being below a top surface of the bottom fin portion; anda gate structure extending over the cap layer.2. The semiconductor structure of claim 1 , wherein the cap layer is crystalline silicon.3. The semiconductor structure of claim 1 , wherein the cap layer has a thickness in a range of 1 Å to 10 Å.4. The semiconductor structure of claim 1 , wherein the liner comprises SiN.5. The semiconductor structure of claim 1 , wherein the liner has a thickness in a range of 0.2 Å to 100 Å.6. The semiconductor structure of claim 1 , wherein the top fin portion has a height in a range of 40 nm to 60 nm.7. The semiconductor structure of claim 1 , wherein the top fin portion has a width in a range of 5 nm to 10 nm.8. A semiconductor structure claim 1 , comprising: a lower portion of the semiconductor fin, the lower portion being a first ...

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Номер записи: 126
26-03-2020 дата публикации

Source/drain recess in a semiconductor device

Номер: US20200098919A1
Автор: Chao-Cheng Chen, Chii-Horng Li, Eric Peng, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

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Номер записи: 127
19-04-2018 дата публикации

SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND EPITAXIAL MATERIALS

Номер: US20180108777A1
Автор: Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит:

A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane. 1. A semiconductor device , comprising:a first gate stack over a substrate;a first epitaxial (epi) material in the substrate, wherein the first epi material includes a first upper surface having a first crystal plane;a second epi material on the first epi material, wherein the second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane; anda cap layer over the second epi material, wherein the cap layer extends above a top surface of the substrate.2. The semiconductor device of claim 1 , wherein the cap layer extends below the top surface of the substrate.3. The semiconductor device of claim 1 , wherein a material of the cap layer is a same material as the first epi material.4. The semiconductor device of claim 1 , wherein a thickness of the cap layer ranges from about 1 nanometer (nm) to about 5 nm.5. The semiconductor device of claim 1 , further comprising a contact feature over the first epi material.6. The semiconductor device of claim 5 , wherein a thickness of the contact feature ranges from about 150 Angstroms to about 200 Angstroms.7. The semiconductor device of claim 1 , wherein a top surface of the first epi material is below a top surface of the substrate and at least a portion of a top surface of the second epi material is above the top surface of the substrate.8. A semiconductor ...

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Номер записи: 128
11-04-2019 дата публикации

FETs and Methods of Forming FETs

Номер: US20190109217A1
Автор: Chiang Wei Te, KUO Chien-I, Li Chii-Horng, LIN TZU-CHING, Lu Wei Hao, Su Li-Li
Принадлежит:

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions. 1. A structure comprising:a raised portion of a substrate;a first fin over the raised portion of the substrate;a second fin over the substrate, the second fin being adjacent the first fin;an isolation region surrounding the first fin and the second fin;a gate structure along sidewalls and over upper surfaces of the first fin and the second fin;a source/drain region on the first fin and the second fin adjacent the gate structure, the source/drain region having a non-faceted top surface; andan air gap separating the source/drain region from a top surface of the raised portion of the substrate.2. The structure of claim 1 , wherein the non-faceted top surface of the source/drain region is higher than top surfaces of the first fin and the second fin in an area between the first fin and the second fin.3. The structure of claim 1 , wherein the source/drain region further comprises sides having faceted surfaces claim 1 , each of the sides having two facets that are non-perpendicular and non-parallel to a major surface of the substrate and another facet that is perpendicular to the major surface of the ...

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Номер записи: 129
18-04-2019 дата публикации

MOS Devices with Non-Uniform P-type Impurity Profile

Номер: US20190115470A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. 1. A method comprising:forming a first gate stack and a second gate stack over a semiconductor substrate;etching a portion of the semiconductor substrate between the first gate stack and the second gate stack to form an opening extending into the semiconductor substrate;forming a silicon germanium region in the opening, wherein upper portions of the silicon germanium region have germanium concentrations higher than or equal to respective lower portions of the silicon germanium region, and the upper portions of the silicon germanium region comprise a p-type impurity having p-type impurity concentrations higher than or equal to the respective lower portions of the silicon germanium region, with a top layer of the silicon germanium region having a higher p-type impurity concentration than a bottom layer of the silicon germanium region; andforming a silicon cap over and contacting the silicon germanium region.2. The method of claim 1 , wherein the silicon germanium region is formed through selective epitaxy growth claim 1 , and the p-type impurity is in-situ doped when the silicon germanium region is deposited.3. The method of claim 1 , wherein the forming the silicon germanium region comprises:performing a first epitaxy to grow a first silicon germanium layer in the opening, wherein the first silicon germanium layer has a first p-type impurity concentration; andperforming a second epitaxy to grow a second silicon ...

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Номер записи: 130
09-04-2020 дата публикации

Semiconductor Device Convex Source/Drain Region

Номер: US20200111711A1
Автор: KUO Chien-I, Li Chii-Horng, LIN TZU-CHING, Su Li-Li
Принадлежит:

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first fin and a second fin protruding from a substrate;forming an isolation region between the first fin and the second fin;forming a first gate structure extending over the first fin and the second fin;removing at least a first portion of the first fin and at least a second portion of the second fin to form a first recess and a second recess, respectively, along a first side of the first gate structure; and performing a first epitaxial process to form a first inner portion in the first recess and a second inner portion in the second recess, wherein an upper surface of the first inner portion and an upper surface of the second inner portion are convex; and', 'performing a second epitaxial process to form an outer portion over the first inner portion and the second inner portion, wherein the first epitaxial process is different than the second epitaxial process, wherein the outer portion has a convex surface extending from directly above a first highest point of the first inner portion to directly above a second highest point of the second inner portion., 'forming a source/drain region along the first side of the first gate structure, wherein forming the source/drain region comprises2. The method of claim 1 , wherein the first epitaxial process comprises a first remote plasma chemical vapor ...

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Номер записи: 131
04-05-2017 дата публикации

FINFET DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20170125410A1
Автор: KUO Chien-I, Li Chii-Horng, LI Ying-Wei, Su Chien-Chang, SU Lilly
Принадлежит:

A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure. 1. A semiconductor device , comprising:a semiconductor substrate;at least one first isolation structure located on the semiconductor substrate;at least one second isolation structure located on the semiconductor substrate;a source structure located on the semiconductor substrate and the first isolation structure, wherein at least one first air gap is located between the source structure and the first isolation structure;a drain structure located on the semiconductor substrate and the second isolation structure, wherein at least one second air gap is located between the drain structure and the second isolation structure; anda plurality of semiconductor fins protruding from the semiconductor substrate, wherein the semiconductor fins are spaced apart from each other and connected to the source structure and the drain structure.2. The semiconductor device of claim 1 , wherein the source structure comprises a plurality of sub-portions corresponding to the semiconductor fins in a one-to-one manner claim 1 , and the first isolation structure is located between the ...

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Номер записи: 132
25-08-2022 дата публикации

Nanosheet semiconductor device and method for manufacturing the same

Номер: US20220271171A1
Автор: Bang-Ting Yan, Chien-Chang Su, Chien-I Kuo, Chien-Wei Lee, Chih Teng HSU, Chih-Chiang Chang, Chii-Horng Li, Yan-Ting Lin, Yee-Chia Yeo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

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Номер записи: 133
30-04-2020 дата публикации

Semiconductor Device and Method

Номер: US20200135467A1
Автор: Chau Cheng-Po, Chen Jung-Jen, Chen Kei-Wei, Jeng Pei-Ren, Li Chii-Horng, Li Yi-Cheng, Liang Pin-Ju, Ma Ta-Chun, Yen Cheng-Hsiung
Принадлежит:

In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin. 1. A method comprising:forming a first fin extending from a substrate, the substrate comprising silicon, the first fin comprising silicon germanium;forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region;removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process;desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; andexchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.2. The method of claim 1 , wherein desorbing the hydrogen and exchanging the silicon are performed with a thermal treatment process.3. The method of claim 2 , wherein the thermal treatment process comprises:placing the first fin in a hydrogen-starved environment;annealing the first fin until the silicon germanium of the first fin is at sorption equilibrium; andremoving the desorbed hydrogen from the hydrogen-starved environment while the silicon germanium of the first fin is at sorption equilibrium.4. The method of claim 3 , wherein the hydrogen-starved environment includes nitrogen ...

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Номер записи: 134
02-06-2016 дата публикации

TRANSISTOR STRAIN-INDUCING SCHEME

Номер: US20160155819A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess. 1. A method of forming a transistor device , comprising:forming a substantially v-shaped source/drain recess within a semiconductor substrate;forming outer un-doped strain-inducing regions in outermost lateral tips of the substantially v-shaped source/drain recess, the outer un-doped strain-inducing regions having a first strain-inducing component at a first concentration; andforming an intermediate un-doped strain-inducing region which extends along a lower angled sidewall of the substantially v-shaped source/drain recess and which extends between the outer un-doped strain-inducing regions without completely filling the substantially v-shaped source/drain recess, the intermediate un-doped strain-inducing region having a second strain-inducing component at a second concentration that differs from the first concentration.2. The method of claim 1 , further comprising:forming a doped source/drain region over the intermediate un-doped strain-inducing region to fill the substantially v-shaped source/drain recess.3. The method of claim 1 , further comprising:while the outer un-doped strain-inducing regions are being formed, concurrently forming a lower un-doped strain-inducing region in a lowermost portion of the substantially v-shaped source/drain recess.4. The method of claim 3 , wherein forming the outer un-doped strain-inducing regions and lower un-doped strain-inducing region comprises ...

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Номер записи: 135
15-09-2022 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH REDUCED NODULE DEFECTS

Номер: US20220293415A1
Автор: CHANG Chih-Chiang, CHEN Chien-Hung, HUANG Ting-Yi, Li Chii-Horng, Lin Che-Yu, YANG Tsung-Hsi, Yeo Yee-Chia, Yu Ming-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion. 1. A method for eliminating nodule defects which are formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure , the method comprisingapplying to the semiconductor structure a plasma which has a higher selectivity to etch the nodule defects relative to the semiconductor region, to thereby eliminate the nodule defects.2. The method of claim 1 , wherein the plasma is generated from a gas source including hydrogen.3. The method of claim 2 , wherein a flow rate of the hydrogen is controlled in a range from 10 sccm to 2000 sccm.4. The method of claim 2 , wherein the gas source further includes a carrier gas selected from helium claim 2 , argon claim 2 , and a combination thereof.5. The method of claim 4 , wherein a flow rate of the carrier gas is controlled in a range from 50 sccm to 6000 sccm.6. The method of claim 1 , wherein the plasma is operated under a temperature ranging from 90° C. to 600° C.7. The method of claim 1 , wherein the plasma is operated under a pressure ranging from 0.05 torr to 6 torr.8. The method of claim 1 , wherein the plasma is generated by a plasma generation source selected from a transformer-coupled plasma generator claim 1 , an inductively coupled plasma system claim 1 , a magnetically enhanced reactive ion etching system claim 1 , an electron cyclotron resonance system claim 1 , or a remote plasma generator.9. A method for manufacturing a semiconductor structure claim 1 , comprising:forming two first recesses in two first regions ...

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Номер записи: 136
15-09-2022 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH ENLARGED VOLUMES OF SOURCE-DRAIN REGIONS

Номер: US20220293773A1
Автор: Jeng Pei-Ren, Li Chii-Horng, Lin Che-Yu, Pai Yi-Fang, YANG Tsung-Hsi, Yeo Yee-Chia
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure. 1. A method for smoothing a surface of a semiconductor portion of a semiconductor structure , comprising:forming an intentional oxide layer on the surface of the semiconductor portion;forming a treated layer in the semiconductor portion and inwardly of the intentional oxide layer; andremoving the intentional oxide layer and the treated layer so as to permit the semiconductor portion to have a smoothed surface.2. The method of claim 1 , wherein the treated layer is formed by applying free radicals to penetrate the intentional oxide layer and to attack the semiconductor portion.3. The method of claim 2 , wherein the free radicals include hydrogen radicals.4. The method of claim 1 , wherein the intentional oxide layer has a thickness not greater than 10 Å.5. The method of claim 1 , wherein the intentional oxide layer is formed using a natural oxidation process claim 1 , an oxygen treatment process claim 1 , an ozone treatment process claim 1 , a chemical oxidation process claim 1 , a thermal chemical vapor deposition process claim 1 , a thermal oxidation process claim 1 , or combinations thereof.6. The method of claim 1 , wherein removing the intentional oxide layer and the treated layer is implemented using an HF vapor etching claim 1 , an NHvapor etching claim 1 , an NHplasma etching claim 1 , an NFvapor etching claim 1 , an NFplasma etching claim 1 , a wet diluted HF etching claim 1 , or combinations thereof.7. A method for manufacturing a semiconductor structure claim 1 , comprising:forming a ...

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Номер записи: 137
31-05-2018 дата публикации

FETS AND METHODS OF FORMING FETS

Номер: US20180151703A1
Автор: Chiang Wei Te, KUO Chien-I, Li Chii-Horng, LIN TZU-CHING, Lu Wei Hao, Su Li-Li
Принадлежит:

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions. 1. A method comprising:forming a raised portion of a substrate;forming fins on the raised portion of the substrate;forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins;forming a gate structure over the fins; and epitaxially growing a first epitaxial layer on the fin adjacent the gate structure;', 'etching back the first epitaxial layer;', 'epitaxially growing a second epitaxial layer on the etched first epitaxial layer; and', 'etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions., 'forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions comprises2. The method of further comprising an air gap separating at least one source/drain region from the first portion of the isolation region.3. The method of further comprising:forming a gate seal spacer on sidewalls of the gate ...

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Номер записи: 138
09-06-2016 дата публикации

Selective Etching in the Formation of Epitaxy Regions in MOS Devices

Номер: US20160163827A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Li Chii-Horng
Принадлежит:

A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region. 1. A method comprising:forming a gate stack over a semiconductor substrate, the semiconductor substrate having a top surface;epitaxially growing a first semiconductor material from exposed surfaces of the semiconductor substrate in a recess of the semiconductor substrate;after the step of epitaxially growing a first semiconductor material, selectively etching-back the first semiconductor material, wherein after the selective etch-back is performed, at least a portion of a top surface of the first semiconductor material is at or above the top surface of the semiconductor substrate; andepitaxially growing a second semiconductor material adjoining the first semiconductor material, the second semiconductor material substantially only growing on the first semiconductor material.2. The method of further comprising:etching the recess in the semiconductor substrate and adjacent the gate stack, the recess creating exposed surfaces of the semiconductor substrate in the recess.3. The method of claim 1 , wherein selectively etching-back uses process gases comprising a first gas for growing the first semiconductor material claim 1 , and a second gas for etching the first semiconductor material.4. The method of claim 3 , wherein the first gas comprises germane (GeH) and dichloro silane (DCS) claim 3 , and the second gas comprises hydrogen chloride (HCl) claim 3 , HF claim 3 , Cl claim 3 , CFH claim ...

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Номер записи: 139
22-09-2022 дата публикации

SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE

Номер: US20220302281A1
Автор: CHIN Chih-Yun, LEE CHIEN-WEI, Lee Yen-Ru, Li Chii-Horng, NIEN Chih-Hung, TING Heng-Wen, YAN Jing Yi, Yeo Yee-Chia
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants. 1. A method , comprising:providing a substrate;forming a first epitaxial layer over the substrate, wherein forming the first epitaxial layer comprises doping the first epitaxial layer with a. first dopant having a first concentration;forming a second epitaxial layer over the first epitaxial layer, wherein forming the second epitaxial layer comprises doping the second epitaxial layer with a second dopant having a second concentration greater than the first concentration; andprecipitating the second dopant to form a cluster of the second dopant in the second epitaxial layer.2. The method of claim 1 , wherein forming the first epitaxial layer comprises epitaxially growing a first silicon germanium layer with a first germanium concentration claim 1 , and wherein forming the second epitaxial layer comprises epitaxially growing a second silicon germanium layer with a second germanium concentration greater than the first germanium concentration.3. The method of claim 1 , wherein doping the first and the second epitaxial layers comprises flowing a precursor gas containing boron during a deposition process.4. The method of claim 1 , wherein the second concentration is greater than about 5×10/cm claim 1 , and wherein precipitating the second dopant comprises forming a silicide layer in the second epitaxial layer.5. The method of claim 4 , wherein forming the silicide layer comprises forming the silicide layer proximate to the first epitaxial layer claim 4 , and wherein a separation between the silicide layer and the first epitaxial layer is less than about 5 nm.6. The method of claim 1 , further comprising ...

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Номер записи: 140
24-06-2021 дата публикации

Interfacial Layer Between Fin and Source/Drain Region

Номер: US20210193831A1
Автор: CHIN Chih-Yun, HSU Tzu-Hsiang, Jeng Pei-Ren, LEE CHIEN-WEI, Lee Yen-Ru, Li Chii-Horng, LIN YAN-TING, Liu Davie, SUNG Hsueh-Chang, Tai Roger, TING Heng-Wen
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium. 1. A semiconductor device , comprising:a first fin and a second fin with an isolation region interposed between the first fin and the second fin;a first recess in the first fin and a second recess in the second fin;a first interfacial layer in the first recess and a second interfacial layer in the second recess, the first interfacial layer being a discrete layer from the second interfacial layer; andan epitaxial source/drain region over the first interfacial layer and the second interfacial layer, wherein the first interfacial layer and the second interfacial layer have an atomic percent content of germanium lower than the first fin, the second fin, and the epitaxial source/drain region, wherein the epitaxial source/drain region comprises SiGe with an atomic percent content of germanium in a range from about 25% to about 70%.2. The semiconductor device of claim 1 , wherein a surface roughness of the first interfacial layer is less than a surface roughness of the first recess in the first fin.3. The semiconductor device of claim 1 , wherein the first interfacial layer has a silicon atomic percent content in a range from about 90% to about 99.9%.4. The semiconductor device of claim 1 , wherein the first fin and the second fin comprises SiGe with an atomic percent content of germanium in a range from about 5% to about 40%.5. The semiconductor device of claim 1 , wherein the epitaxial source/drain region comprises a first SiGe layer over the first interfacial layer and a second SiGe layer over the first SiGe layer claim 1 , wherein the first SiGe layer and the second SiGe layer have a ...

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Номер записи: 141
16-06-2016 дата публикации

METHOD TO REDUCE ETCH VARIATION USING ION IMPLANTATION

Номер: US20160172466A1
Автор: Chen Chao-Cheng, Fang Ziwei, Jang Syun-Ming, Lee Tze-Liang, Li Chii-Horng, Wang Tsan-Chun
Принадлежит:

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses. 1. A method , comprising:providing a semiconductor substrate that includes first and second regions, the first and second regions having first and second etch rates, respectively, which are different from one another for a pre-determined etch;selectively implanting dopants into the first region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate; andconcurrently etching both the first, selectively implanted region and the second region using the pre-determined etch to form recesses having equal recess depths.2. The method of claim 1 , further comprising:performing an epitaxial growth process to form one or more epitaxial layers having equal respective heights within the recesses.3. The method of claim 1 , wherein concurrently etching the first claim 1 , selectively implanted region and the second region completely removes the selectively implanted dopants from the first selectively implanted region.4. The method of claim 1 , wherein the first region has a first doping type and the second region has a second claim 1 , opposite doping type.5. The method of claim 1 , wherein the first region has a first doping type at a first doping concentration and the second region has the first doping type at a second doping concentration that differs ...

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Номер записи: 142
11-09-2014 дата публикации

Engineered Source/Drain Region for N-Type MOSFET

Номер: US20140252468A1
Автор: CHEN Jyh-Huei, HUANG Chun-Hung, Li Chii-Horng, Lu Wei-Yuan, SU Lilly
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.

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Номер записи: 143
15-06-2017 дата публикации

Source and Drain Stressors with Recessed Top Surfaces

Номер: US20170170319A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion. 1. A method comprising:forming a first gate stack over a semiconductor substrate;forming a first opening extending into the semiconductor substrate, wherein the first opening is adjacent to the first gate stack; andperforming an epitaxy to grow a first semiconductor region in the first opening, wherein the first semiconductor region comprises a different material than the semiconductor substrate, wherein the first semiconductor region comprises a first top surface extending above an interface between the first gate stack and the semiconductor substrate, wherein performing the epitaxy comprises controlling epitaxy parameters so that a center portion of the first top surface is recessed lower than first and second portions of the first top surface to form a recess, and wherein the first and second portions are on opposite sides of the center portion.2. The method of claim 1 , wherein the first semiconductor region comprises silicon germanium.3. The method of further comprising:forming a second gate stack over the semiconductor substrate;patterning a second opening extending into the semiconductor substrate, wherein the second opening is adjacent to the second gate stack; andgrowing a second semiconductor region in the second opening, wherein the second semiconductor region comprises a different material than the semiconductor substrate, wherein the second semiconductor region comprises a second top surface, and wherein the second top surface has no recess in a respective center region of the second semiconductor region.4. The method of claim 3 , wherein growing the ...

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Номер записи: 144
30-05-2019 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190164835A1
Автор: Li Chii-Horng, LU Wei-Hao, NG Tuoh-Bin, Pai Yi-Fang, Su Li-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation. 115-. (canceled)16. A method for fabricating a semiconductor device structure , comprising:forming a first fin structure over a substrate;forming an isolation feature over the substrate;forming a gate structure over the first fin structure and the isolation feature;recessing a portion of the first fin structure that is not directly below the gate structure to form a first recess extending into a portion of the isolation feature that is not directly below the gate structure; andepitaxially growing a first semiconductor layer in the first recess of the first fin structure at a first temperature in a range of about 400° C. to about 700° C. so that the first semiconductor layer has a surface with [110] plane orientation, wherein the first semiconductor layer has a first dopant concentration of P.17. The method as claimed in claim 16 , further comprising:epitaxially growing a second semiconductor layer covering the first semiconductor layer at the first temperature so that the second semiconductor layer has a surface with [110] plane orientation, wherein the second semiconductor layer has a second dopant concentration of P that is greater than the first dopant concentration of P.18. The method as claimed in claim ...

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Номер записи: 145
30-05-2019 дата публикации

FINFET DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20190164964A1
Автор: KUO Chien-I, Li Chii-Horng, LI Ying-Wei, Su Chien-Chang, SU Lilly
Принадлежит:

A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure. 1. A method for fabricating a FinFET device , comprising:forming a first semiconductor fin and a second semiconductor fin protruding from a semiconductor substrate;forming an isolation structure between the first semiconductor fin and the second semiconductor fin;forming a first gate structure over a first portion of the first semiconductor fin and a first portion of the second semiconductor fin;removing a second portion of the first semiconductor fin that is not protected by the first gate structure to define a first groove and removing a second portion of the second semiconductor fin that is not protected by the first gate structure to define a second groove; andforming a source/drain structure in the first groove, in the second groove, and over the isolation structure, wherein a gap is defined between the source/drain structure and the isolation structure.2. The method of claim 1 , wherein forming the source/drain structure comprises epitaxially growing the source/drain structure.3. The method of claim 2 , wherein epitaxially growing the source/drain ...

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Номер записи: 146
30-05-2019 дата публикации

SEMICONDUCTOR DEVICE SOURCE/DRAIN REGION WITH ARSENIC-CONTAINING BARRIER REGION

Номер: US20190165100A1
Автор: Chan Chia-Ling, Chiang Wei Te, Fu Shao-Fu, KUO Chien-I, Li Chii-Horng, Lu Wei Hao, Pai Yi-Fang, Su Li-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration. 1. A method of manufacturing a semiconductor device , the method comprising: forming a barrier region along a bottom surface and side surface of a recess in the active area, the barrier region comprising arsenic having a first dopant concentration; and', 'forming an epitaxial material on the barrier region in the recess, the epitaxial material comprising phosphorous having a second dopant concentration., 'forming an active area on a substrate, the active area including a source/drain region, wherein the source/drain area is formed comprising2. The method of claim 1 , wherein forming the barrier region comprises epitaxially growing the barrier region claim 1 , the barrier region being in situ doped with the arsenic during the epitaxial growth.3. The method of claim 1 , wherein forming the barrier region comprises plasma doping the active area through the bottom surface and side surface of the recess with the arsenic.4. The method of claim 1 , wherein forming the barrier region comprises epitaxially growing the barrier region using a chemical vapor deposition (CVD) process claim 1 , the barrier region being a SiAs layer.5. The method of claim 1 , wherein the active area comprises a fin claim 1 , and the transistor is a n-channel Fin Field ...

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Номер записи: 147
25-06-2015 дата публикации

Germanium Profile for Channel Strain

Номер: US20150179796A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation. 1. A transistor device , comprising:a gate structure disposed onto a semiconductor substrate; anda strained source/drain region comprising a strain inducing material disposed at a position adjoining the gate structure within a source/drain recess located in the semiconductor substrate;wherein the strain inducing material comprises a strain inducing component having a discontinuous concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess.2. The transistor device of claim 1 , wherein the discontinuous concentration profile comprises at least two discontinuities.3. The transistor device of claim 1 ,wherein the strain inducing material comprises silicon germanium (SiGe); andwherein the strain inducing component comprises germanium (Ge).4. The transistor device of claim 1 , wherein the strain inducing material comprises a first distinct epitaxial layer abutting a bottom of the source/drain recess and comprising a first strain inducing component concentration profile that changes from a high concentration at a first position to a low concentration at a second position overlying the first position.5. The transistor device of claim 1 , ...

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Номер записи: 148
22-06-2017 дата публикации

MOS Devices with Non-Uniform P-type Impurity Profile

Номер: US20170179287A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. 1. An integrated circuit structure comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack;a silicon germanium region in the recess, wherein the silicon germanium region has a first p-type impurity concentration; anda silicon cap substantially free from germanium over the silicon germanium region, wherein the silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.2. The integrated circuit structure of claim 1 , wherein a portion of the silicon germanium region is in contact with the silicon cap claim 1 , and the portion of the silicon germanium region has a highest p-type impurity concentration among all source and drain regions of a Metal-oxide-Semiconductor (MOS) device that comprises the silicon germanium region and the silicon cap.3. The integrated circuit structure of further comprising forming a silicide region extending into the silicon cap claim 1 , with the silicon cap comprising a remaining portion on a side of the silicide region.4. The integrated circuit structure of claim 3 , wherein the silicide region has a third p-type impurity concentration higher than the first p-type impurity concentration.5. The integrated circuit structure of further comprising a silicide region extending into the silicon cap and the silicon germanium ...

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Номер записи: 149
30-06-2016 дата публикации

V-Shaped Epitaxially Formed Semiconductor Layer

Номер: US20160190250A1
Автор: KWOK Tsz-Mei, Li Chii-Horng, Yu Ming-Hua
Принадлежит:

The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature. 1. A method comprising:forming a recess in a source/drain (S/D) region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material;epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess; andremoving a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.2. The method of claim 1 , further comprising forming a silicide feature in the v-shape valley.3. The method of claim 1 , further comprising forming a contact feature on the silicide feature.4. The method of claim 1 , wherein after removing the portion of the S/D feature to form the v-shaped valley extending into the S/D feature claim 1 , the S/D feature includes a first surface aligned in a [111] crystalline orientation and a second surface aligned in the [111] crystalline orientation.5. The method of claim 4 , wherein the first surface intersects the second surface.6. The method of claim 1 , wherein the first semiconductor material is different than the second semiconductor material.7. The method of claim 1 , further comprising forming a gate stack over the semiconductor substrate.8. A method comprising:forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material;epitaxially growing a second semiconductor material and a third semiconductor material within the recess to form a S/D feature; andremoving a portion of the S/ ...

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Номер записи: 150
06-07-2017 дата публикации

V-Shaped Epitaxially Formed Semiconductor Layer

Номер: US20170194434A1
Автор: KWOK Tsz-Mei, Li Chii-Horng, Yu Ming-Hua
Принадлежит:

The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature. 1. A device comprising:a gate stack disposed over a semiconductor substrate; and a first semiconductor material including a dopant at a first concentration;', 'a second semiconductor material disposed over the first semiconductor material, the second semiconductor material including the dopant at a second concentration that is greater than the first concentration; and', 'a third semiconductor material disposed over the second semiconductor material, the third semiconductor material including the dopant at a third concentration that is less than the second concentration, wherein a top surface of the third semiconductor material defines a recess., 'a source/drain feature disposed in the semiconductor substrate adjacent the gate stack, wherein the source/drain feature includes2. The device of claim 1 , further comprising a silicide feature disposed within the recess such that the silicide feature physically contacts the top surface of the third semiconductor material.3. The device of claim 2 , further comprising a contact disposed directly on the silicide feature.4111111. The device of claim 1 , wherein the top surface of the third semiconductor material includes a first portion aligned in a [] crystalline orientation and a second portion aligned in the [] crystalline orientation.5111111. The device of claim 4 , wherein the first portion aligned in the [] crystalline orientation intersects the second portion aligned in the [] crystalline orientation.6. The device of claim 1 , wherein the ...

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Номер записи: 151
03-08-2017 дата публикации

V-Shape Recess Profile for Embedded Source/Drain Epitaxy

Номер: US20170222053A1
Автор: Chen Chih-Shan, Lee Yen-Ru, Li Chii-Horng, LIN TZU-CHING, Lin Yih-Ann, Tai Roger
Принадлежит:

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base. 1. A semiconductor device , comprising:a semiconductor layer;an isolation structure formed in the semiconductor layer; andan epi-layer component formed on the semiconductor layer;wherein:the epi-layer component includes a first portion that extends into the semiconductor layer;a lateral dimension of the first portion of the epi-layer component decreases as the first portion extends further into the semiconductor layer; anda substantial majority of a side surface of the first portion of the epi-layer component is free of being in direct contact with the isolation structure.2. The semiconductor device of claim 1 , wherein the first portion of the epi-layer component has a cross-sectional profile that resembles a letter V.3. The semiconductor device of claim 2 , wherein the epi-layer component defines an upwardly-facing angle that is less than about 120 degrees.4. The semiconductor device of claim 1 , wherein:the first portion of the epi-layer component has a depth and a width; andthe depth is greater than about ½ of the width.5. The semiconductor device of claim 1 , wherein the epi-layer component includes a source/drain of a FinFET transistor.6. The semiconductor device of claim 1 , wherein the epi-layer component includes a second portion that is disposed over the first portion.7. The semiconductor device of claim 6 , wherein:the epi-layer component includes a plurality of first portions; andthe second portion is disposed above the plurality of first portions.8. The semiconductor device ...

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Номер записи: 152
20-08-2015 дата публикации

Transistor Strain-Inducing Scheme

Номер: US20150236157A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess. 1. A transistor device , comprising:a gate structure disposed on a semiconductor substrate;a source/drain recess arranged in the semiconductor substrate alongside the gate structure;a doped strain-inducing region disposed within the source/drain recess, wherein the doped strain-inducing region comprises a compound semiconductor material that is doped with n-type or p-type dopant impurities; andan un-doped strain-inducing region disposed within the source/drain recess under the doped strain-inducing region, wherein the un-doped strain-inducing region comprises the compound semiconductor material, and a stoichiometry of elements is different at different locations within the un-doped strain-inducing region.2. The transistor device of claim 1 , wherein the source/drain recess defines a recess surface having planar surfaces with different planar orientations claim 1 , and wherein the un-doped strain-inducing region comprises different strain-inducing component concentrations near the different planar surfaces claim 1 , respectively.3. The transistor device of claim 1 , wherein the compound semiconductor material comprises silicon germanium (SiGe).4. The transistor device of claim 1 , wherein the doped strain-inducing region comprises silicon germanium (SiGe) doped with boron.5. The transistor device of claim 1 , wherein the un-doped strain-inducing region comprises:a first un-doped strain-inducing ...

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Номер записи: 153
24-08-2017 дата публикации

DOPING PROFILE FOR STRAINED SOURCE/DRAIN REGION

Номер: US20170243975A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile. 1. A transistor device , comprising:a gate structure arranged over a semiconductor substrate;a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure and comprising a first layer and a second layer over the first layer; andwherein the first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.2. The transistor device of claim 1 , wherein the second non-zero concentration profile increases as a distance from the first layer increases.3. The transistor device of claim 1 , wherein the strained source/drain region further comprises:a third layer arranged over the second layer and having a third concentration profile of the strain inducing component that is discontinuous with the second non-zero concentration profile.4. The transistor device of claim 3 , wherein the third concentration profile has a concentration of the strain inducing component that is substantially zero.5. The transistor device of claim 1 , wherein the first layer contacts the second ...

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Номер записи: 154
01-09-2016 дата публикации

Modulating Germanium Percentage in MOS Devices

Номер: US20160254381A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region. 1. An integrated circuit structure comprising:a semiconductor substrate;a recess in the semiconductor substrate;a first silicon germanium region substantially filling the recess and having a topmost surface extending above a topmost surface of the substrate, wherein the first silicon germanium region has a first germanium percentage;a second silicon germanium region on the topmost surface of the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage; anda metal silicide above and extending partly into the second silicon germanium region.2. The integrated circuit of claim 1 , wherein the first germanium percentage is from about 30 percent to about 60 percent and wherein the second germanium percentage is from about 35 percent to about 80 percent.3. The integrated circuit of claim 1 , wherein the first silicon germanium region further includes impurities at an impurity concentration of from about 5E18/cmto about 5E21/cm.4. The integrated circuit of claim 3 , wherein the impurities are boron.5. The integrated circuit of claim 1 , wherein the metal silicide has a substantially cup shaped form.6. The integrated circuit of claim 1 , wherein the germanium percentage in the first silicon germanium region is substantially uniform through the first silicon ...

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Номер записи: 155
20-11-2014 дата публикации

Reducing Variation by Using Combination Epitaxy Growth

Номер: US20140342522A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Li Chii-Horng, Lin Yi-Hung
Принадлежит:

A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio. 1. A method comprising:forming a first recess and a second recess in a semiconductor substrate; and performing a first growth step, wherein in the first growth step, a selective growth is performed to grow a first semiconductor material in the first recess, and simultaneously, a selective etching is performed in the second recess; and', 'after the first growth step, performing a second growth step to simultaneously grow a second semiconductor material in the first recess and the second recess., 'performing a selective epitaxial growth to grow a semiconductor material in the first recess and the second recess, wherein the selective epitaxial growth comprises2. The method of claim 1 , wherein in the second growth step claim 1 , a first growth rate of the semiconductor material in the first recess is lower than a second growth rate of the semiconductor material in the second recess.3. The method of claim 2 , wherein the first recess is greater in area than the second recess.4. The method of claim 3 , wherein the first recess is the largest recess in the semiconductor substrate claim 3 , and the second recess is the smallest recess in the semiconductor substrate.5. The method of claim 1 , wherein the first semiconductor material is grown with a first etch-to-growth (E/G) ratio greater than a uniform growth E/G ratio claim 1 , and the ...

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Номер записи: 156
24-09-2015 дата публикации

BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE

Номер: US20150270397A1
Автор: Chen Chao-Cheng, Hao Hsieh-Ying, Jang Syun-Ming, Lee Tze-Liang, Li Chii-Horng, Lo Shih-Hao, Peng Eric, Yu Ming-Hua
Принадлежит:

A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess. 1. A device , comprising:a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack; a first profile having substantially vertical sidewalls; and', 'a second profile contiguous with and below the first profile, wherein the first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile;, 'a recess in the semiconductor substrate adjacent the gate stack, the recess havingwherein the recess is filled with a semiconductor material; andwherein the pair of spacers are disposed overly the semiconductor substrate adjacent the recess.2. The device of claim 1 , wherein one of the substantially vertical sidewalls of the first profile is substantially collinear with an edge of one spacer of the pair of spacers.3. The device of claim 1 , wherein the second profile has a rounded-shaped bottom region.4. The device of claim 1 , wherein the second profile has a v-shaped bottom region.5. The device of claim 1 , wherein the semiconductor material is an epitaxial semiconductor material.6. The device of claim 1 , wherein the semiconductor material is at least one of silicon germanium (SiGe) and silicon carbide (SiC).7. A ...

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Номер записи: 157
21-09-2017 дата публикации

TRANSISTOR STRAIN-INDUCING SCHEME

Номер: US20170271478A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

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Номер записи: 158
18-12-2014 дата публикации

Semiconductor device and fabrication method thereof

Номер: US20140367768A1
Автор: Chii-Horng Li, Lilly SU, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru LEE, Yi-Hung Lin, Yu-Hung Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.

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Номер записи: 159
03-11-2016 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20160322499A1
Автор: Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит:

A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane. 1. A semiconductor device , comprising:a first gate stack and a second gate stack over a substrate;an isolation structure in the substrate, wherein the first gate stack is between the isolation structure and the second gate stack;a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, wherein the first epi material includes a first upper surface having a first crystal plane; anda second epi material in the substrate between the first gate stack and the second gate stack, wherein the second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and the first crystal plane is different from both the second crystal plane and the third crystal plane.2. The semiconductor device of claim 1 , wherein the first upper surface is not parallel to the second crystal plane and the third crystal plane.3. The semiconductor device of claim 1 , wherein the first epi material includes a first lower surface having a fourth crystal plane claim 1 , the first lower surface being adjacent to a bottom surface and the fourth crystal plane being parallel to the second crystal plane of the second epi material.4. The semiconductor ...

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Номер записи: 160
01-11-2018 дата публикации

Source/drain recess in a semiconductor device

Номер: US20180315855A1
Автор: Chao-Cheng Chen, Chii-Horng Li, Eric Peng, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

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Номер записи: 161
17-11-2016 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20160336448A1
Автор: Cheng Yu-Hung, Lee Tze-Liang, Lee Yen-Ru, Li Chii-Horng, Lin Yi-Hung, SU Lilly, Tsai Pang-Yen, Yu Ming-Hua
Принадлежит:

A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane. 1. A method of fabricating a semiconductor device , comprising:forming an isolation feature in a substrate;forming a first gate stack and a second gate stack over the substrate;forming a first recess cavity and a second recess cavity in the substrate, wherein the first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack;growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, wherein a topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane; andetching the first epi material and the second epi material, wherein the topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.2. The method of claim 1 , wherein etching the first epi material comprises increasing an amount of the first epi material in the first recess cavity.3. ...

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Номер записи: 162
17-10-2019 дата публикации

Supportive Layer in Source/Drains of FinFET Devices

Номер: US20190319098A1
Автор: CHIN Chih-Yun, Jeng Pei-Ren, Lee Yen-Ru, Li Chii-Horng, LIN YAN-TING, Tai Roger
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content. 1. A semiconductor structure comprising:a fin on a substrate;a gate structure over the fin; and a bottom layer,', 'a supportive layer over the bottom layer, and', 'a top layer over the supportive layer, wherein the supportive layer has a different property than the bottom layer and the top layer, the different property selected from a group consisting of a different material, a different natural lattice constant, a different dopant concentration, and a different alloy percent content., 'a source/drain in the fin proximate the gate structure, the source/drain comprising2. The semiconductor structure of claim 1 , wherein the supportive layer comprises a material selected from a group consisting of silicon claim 1 , silicon germanium claim 1 , boron doped silicon germanium claim 1 , phosphorus doped silicon claim 1 , phosphorus doped silicon germanium claim 1 , arsenic doped silicon claim 1 , and arsenic doped silicon germanium.3. The semiconductor structure of claim 1 , wherein the bottom layer has a thickness in a range from about 30 nm to about 50 nm and the top layer has a thickness in a range from about 15 nm to about 45 nm.4. The semiconductor structure of claim 1 , wherein the fin comprises silicon germanium.5. The semiconductor structure of claim 1 , wherein the bottom layer of the source/drain comprises p-doped silicon germanium having a first germanium atomic percent content and wherein the top layer comprises p- ...

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Номер записи: 163
03-12-2015 дата публикации

TRANSISTOR STRUCTURE INCLUDING EPITAXIAL CHANNEL LAYERS AND RAISED SOURCE/DRAIN REGIONS

Номер: US20150349065A1
Автор: Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu
Принадлежит:

The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers. 1. An integrated circuit device , comprising:a semiconductor body comprising p-doped regions and n-doped regions; epitaxial grown n-type raised source/drain regions;', 'epitaxial grown channel regions;', 'gate electrodes; and', 'gate dielectrics separating the gate electrodes from the epitaxial grown channel regions of the n-channel MOSFETs;, 'n-channel MOSFETs formed over the p-doped regions of the semiconductor body and comprising epitaxial grown p-type raised source/drain regions;', 'epitaxial grown channel regions;', 'gate electrodes; and', 'gate dielectrics separating the gate electrodes from the epitaxial grown channel regions of the p-channel MOSFETs; and, 'p-channel MOSFETs formed over the n-doped regions of the semiconductor body and comprisingan epitaxially grown diffusion barrier layer separating the epitaxial grown channel regions of the n-channel MOSFETS from the p-doped regions of the semiconductor body and separating the epitaxial grown channel regions of the p-channel MOSFETS from the n-doped regions of the semiconductor body.2. The device of claim 1 , wherein the epitaxially grown diffusion barrier layer has the same composition where it separates the epitaxial grown channel regions of the n-channel MOSFETS from the p-doped regions of the semiconductor as it does where it separates the epitaxial grown channel regions of the p-channel MOSFETS from the n-doped regions of the semiconductor body.3. ...

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Номер записи: 164
29-10-2020 дата публикации

Source and Drain Stressors with Recessed Top Surfaces

Номер: US20200343381A1
Автор: KWOK Tsz-Mei, Lee Tze-Liang, Li Chii-Horng, Li Kun-Mu, SUNG Hsueh-Chang
Принадлежит:

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion. 1. A device comprising:a semiconductor substrate; a first gate stack on a top surface of the semiconductor substrate; and', 'a first silicon germanium region, a first top surface of the first silicon germanium region extending continuously from a first point to a third point through a second point, the first point and the third point of the first top surface are each above the top surface of the semiconductor substrate, and the second point of the first top surface is below the top surface of the semiconductor substrate; and, 'a first transistor in a first region of the device, the first transistor comprisinga second transistor in a second region of the device, a pattern density of first gate stacks in the first region being less than a pattern density of second gate stacks in the second region, the second transistor comprising a second silicon germanium region, a second top surface of the second silicon germanium region having a different profile than the first top surface of the first silicon germanium region.2. The device of claim 1 , wherein a center point of the second top surface is above the top surface of the semiconductor substrate.3. The device of claim 2 , wherein the center point of the second top surface is above edges of the second top surface.4. The device of claim 1 , wherein the second point is a center point of the first top surface.5. The device of further comprising a first semiconductor cap over and contacting the first top surface of the first silicon germanium region claim 1 , wherein the first semiconductor cap has a germanium percentage ...

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Номер записи: 165