Mobile phone

Battery cover latch mechanism and portable electronic device using same

A battery cover latching mechanism used in portable electronic device (10) is described including a cover member (11), a housing member (12), a latch base (14), a latch member (13), and a return member (15). The latch base can be securely attached to the housing member. The latch member is mounted on the latch base and movable relative to the latch base to latch the cover member to the housing member. The return member drives the latch member to move in such a manner that the movement of the latch member detaches the cover member away from the housing member.

Digitally controlled delay line circuit and method

A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes a first inverter configured to selectively propagate the signal along the first signal path, a second inverter configured to selectively propagate the signal along the second signal path, and a third inverter configured to selectively propagate the signal from the first signal path to the second signal path. Each of the first and third inverters has a tunable selection configuration corresponding to greater than three output states.

Source/Drain Formation with Reduced Selective Loss Defects

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

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Advanced structure for self-aligned contact and method for producing the same

Methods of forming a SAC cap with SiN U-shaped and oxide T-shaped structures and the resulting devices are provided. Embodiments include forming a substrate with a trench and a plurality of gate structures; forming a nitride liner over portions of the substrate and along sidewalls of each gate structure; forming an ILD between each gate structure and in the trench; recessing each gate structure between the ILD; forming a U-shaped nitride liner over each recessed gate structure; forming an a-Si layer over the nitride liner and the U-shaped nitride liner; removing portions of the nitride liner, the U-shaped nitride liner and the a-Si layer; forming a W layer over portions of the substrate adjacent to and between the a-Si layer; forming an oxide liner over the nitride liner, the U-shaped nitride liner and along sidewalls of the W layer; and forming an oxide layer over portions of the oxide liner.

Optical imaging system with encapsulation and tether

A tethered imaging camera encapsulated in a shell lens element of such camera enables viewing from inside and imaging of a biological organ in/from a variety of directions. A portion of camera's optical system together with light source(s) and optical detector mutually cooperated by housing structure inside the shell are moveable/re-orientable within the shell to vary a desired view of the object space without interruption of imaging process. A tether carries electrical but not optical signals to and from the camera and controllable traction cords to move the camera, and a hand-control unit and/or electronic circuitry configured to operate the camera and power its movements. Method(s) of using optical, optoelectronic, and optoelectromechanical sub-systems of the camera.

Housing and method for making the same

A housing includes a substrate and a decorative layer formed on one surface of the substrate. The decorative layer includes two colored ink coatings, each of which is partially interlaced with the other and has a color depth decreasing from one end thereof towards the other colored ink coating to another end thereof and partially mixed with the other colored ink coating.

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Method of density-controlled floorplan design for integrated circuits and integrated circuits

A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.

Digitally controlled delay line circuit and method

A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS

Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches. 1. A method comprising:forming a trench in a material;forming a conductor in a lower portion of the trench;performing a first atomic layer deposition (ALD) of a first liner material to line a middle portion and an upper portion of the trench, the middle portion is between the lower portion and the upper portion;flowing a fill material comprising an insulator to fill the middle portion and the upper portion of the trench;removing the fill material from the upper portion of the trench to leave the fill material in the middle portion of the trench; andperforming a second ALD of a second material to fill the upper portion of the trench with the second material.2. The method according to claim 1 , wherein the first liner material is formed on the conductor.3. The method according to claim 1 , wherein the first liner material comprises silicon combined with at least one of nitrogen claim 1 , oxygen claim 1 , and carbon.4. The method according to claim 1 , wherein the fill material comprises a flowable combination of silicon claim 1 , oxygen claim 1 , and carbon.5. The method according to claim 1 , wherein the second material comprises a combination of silicon and nitrogen.6. The method according to claim 1 , wherein the removing the fill material from the upper portion of the trench comprises reactive ion etching (RIE).7. (canceled)8. A ...

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Key assembly and portable electronic device using the same

A key assembly comprises a base plate, two elastic elements and a key body. Each elastic element has a securing portion and two compressing portions protruding from two ends of the securing portion. The securing portions are latched to the base plate. The key body is slidably mounted to the base plate between the two elastic elements. The key body includes a first key section resisting one of the two elastic elements and a second key section resisting another elastic element. When the first key section slides toward and compresses the corresponding elastic element, the second key section slide away from the corresponding elastic element.

Vertical light emitting diode chip package with electrical detection position

The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

METHOD FOR MANUFACTURING MOLDED ARTICLE

A method for manufacturing a molded article (10) is provided. is provided. The method includes steps as follows. A substrate (11) and a textured layer (12) are molded and the textured layer is formed on the substrate. A leather coating layer (13) is coated on the substrate and the leather coating layer is mixed with the textured layer.

Capacitor Array Layout Arrangement for High Matching Methodology

Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed. 1. A capacitor array arranged on a semiconductor substrate and comprising:an array of unit capacitors arranged in a series of rows and columns;an interconnect structure to couple unit capacitors of the array to establish a plurality of capacitor elements, wherein the respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances;wherein, in establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate.2. The capacitor array of claim 1 , wherein the substantially identical sub-arrays are equal in size when tiled over the semiconductor substrate.3. The capacitor array of claim 2 , wherein the substantially identical sub-arrays have the same angular orientation when tiled over the semiconductor substrate.4. The capacitor array of claim 1 , wherein the sub-arrays are made up of respective unit capacitors in respective sub-array locations claim 1 , and wherein at least approximately 87% of the unit capacitors are in the same sub-array locations for a first sub-array and a second sub-array.5. The capacitor array of claim 1 , wherein the sub-arrays are made up of respective unit capacitors in respective sub-array locations claim 1 , and wherein at least ...

Accessory strap fixing structure and portable electronic device using the same

A portable electronic device includes a main body and a accessory strap fixing structure. The main body defines an assembling slot therein. The accessory strap fixing structure is rotatably assembled within the assembling slot and includes a hanging frame, a supporting frame, a hinged portion, and a latching portion. The hanging frame includes a hanging portion disposed thereon for hanging a accessory strap thereto. The two ends of the supporting frame are connected to two ends of the hanging frame respectively. The hinged portion is formed at one joint of the hanging frame and the supporting frame, for being rotatably hinged to the main body and accommodated within the assembling slot. The latching portion is formed adjacent to the other joint of the hanging frame and the supporting frame, and configured for detachably latching within the assembling slot.

OPTICAL SENSING DEVICE HAVING INCLINED REFLECTIVE SURFACE

Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.

KEYBOARD STRUCTURE AND ELECTRONIC DEVICE USING THE SAME

A keyboard structure, comprises a housing having at least one post, a key assembly, and at least one connecting portion comprising a ring, the ring coils around the post to connect the key assembly to the housing. The invention also discloses an electronic device using the keyboard structure.

Key assembly and portable electronic device using the same

A key assembly comprises a base plate and two keys. The base plate has an opening defined therein and two opposite first inner walls formed in the opening, each first inner wall has two mating space defined therein and spaced from each other. Each key has two opposite sidewalls, each sidewall has a shaft protruding therefrom and corresponding to the mating spaces, the shafts is rotatably received in the mating spaces.

NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT

The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

Battery cover latch mechanism and portable electronic device using same

A battery cover latch mechanism (10) used in portable electronic device (100) is described including a cover member (11), a housing member (12), a latching assembly (13), and a return member (16). The latching assembly slides between a released position and a latched position. The return member is secured to the cover member including two elastic sheets (136) elastically resisting a same side of the latching assembly. The elastic sheets connect with each other. The elastic sheet is used to return the latching assembly towards the latched position.

Semiconductor devices and methods of forming the same

An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.

Conductive elastic sheet structure and electronic device using the same

The invention discloses a conductive elastic sheet structure mounted on a metallic cover of an electronic device eliminates static electricity. The conductive elastic sheet structure includes a main panel, a first extending portion, and a second extending portion. The main panel includes a first side wall, and a second side wall opposite to the first side wall. The first extending portion and the second extending portion extend from the side edges of the first side wall and the second side wall respectively, and each forms a sharp angle with the main panel. The first extending portion and the second extending portion extend from two opposite sides of the main panel respectively. The invention also provides an electronic device using the conductive elastic sheet structure.

Graded dummy insertion

Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

GRADED DUMMY INSERTION

Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example. 1. A computer-implemented method for graded dummy insertion associated with semiconductor fabrication , comprising:inserting, adjacent a first region comprising one or more active cells, a first dummy region associated with a first graded pattern density that is less than a first pattern density associated with the first region; andinserting, between the first dummy region and a second region, a second dummy region associated with a second graded pattern density that is less than the first graded pattern density and greater than a second pattern density associated with the second region.2. The method of claim 1 , comprising inserting a third dummy region between the first dummy region and the second dummy region claim 1 , the third dummy region associated with an third graded pattern density that is less than the first graded pattern density and greater than the second graded pattern density.3. The method of claim 1 , comprising determining at least one of the first graded pattern density or the second graded pattern density based at least in part on a linear function ...

RISE TIME AND FALL TIME MEASUREMENT

Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal. 1. A timing measurement system for determining a transition time of a circuit , comprising: receive a circuit signal from a circuit;', 'evaluate the circuit signal based upon a first control voltage to create a first output waveform; and', 'evaluate the circuit signal based upon a second control voltage to create a second output waveform; and, 'a comparator configured to 'evaluate the first output waveform and the second output waveform to determine a transition time of the circuit.', 'a time converter component configured to2. The timing measurement system of claim 1 , the circuit comprising at least one of a digital circuit claim 1 , an analog circuit claim 1 , or a mixed-signal circuit.3. The timing measurement system of claim 1 , the transition time comprising a rise time.4. The timing measurement system of claim 1 , the transition time comprising a fall time.5. The timing measurement system of claim 1 , the circuit operating based upon an input provided by a source external to the timing measurement system.6. The timing measurement system of claim 1 , the circuit comprised within an integrated circuit within which the timing measurement system is embedded.7. The timing ...

Bandgap reference circuit, control circuit, and associated control method

A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.

Hinge apparatus for foldable electronic device

A hinge apparatus includes a hinge assembly (30) and an enclosure (40). The hinge assembly includes a sleeve (31). The enclosure forms two elastic portions (46) therein. The hinge assembly is slidably received in the enclosure, and the sleeve is clamped between the elastic portions. The enclosure defines an opening (42) configured for exposing the hinge assembly from the enclosure.

High heat dissipation light emitting diode package structure having at least two light cups and lateral light emission

A present invention includes at least two light cups and a composite material base. The composite material base comprises a first surface, a second surface and a third surface adjacent to the first surface, and a fourth surface opposite to the first surface. The at least two light cups are formed on the first surface. At least two first metal plates and at least two second metal plates having different polarities and corresponding to the quantity of the light cups are provided on the second surface. One ends of the at least two first and second metal plates individually pass through the composite material base and extend into the light cup to form two electrode contacts, and the other ends of the at least two first metal plates extend to the fourth surface to form an exposed heat dissipation structure.

Side key assembly and electronic device using the same

A side key assembly is mounted on a housing (60) which comprises a sidewall (610). A socket (62) is formed in the sidewall (610) of the housing. The side key assembly includes a button (70), two switches (80) and the socket. The button includes an operating portion (710), two touching blocks (740) and at least one elastic arm (750). The operating portion is slidingly received in the socket. One end of the at least one elastic arm connects with the operating portion while the other end is firmly fixed on the housing. Each switch includes a contact portion. Each contact portion is positioned adjacent to a corresponding touching block. Each switch is turned on when the corresponding touching block is moved to touch the contact portion thereof.

Protecting assembly for a camera

A protecting assembly (20) for a camera used in a portable electronic device (10) is provided. The protecting assembly (20) includes a positioning member (14) fixed to a body section (11) of the electronic device (10) and a protecting member (16). The protecting member (16) is mounted on the positioning member (14) and arranged over the camera (12). A process for protecting a camera using the protecting assembly (20) is also provided.

Battery cover latch mechanism and portable electronic device using same

A battery cover latch mechanism (10) used in portable electronic device (100) is described including a cover member (113), a housing member (111), a latch member (1137), a pressing member (15), and a releasing member (17). The latch member is used to latch the cover member to the housing member. The releasing member can be elastic deformed such that the pressing member moves and deforms the releasing member to release the cover member from the housing member.

Source/Drain Formation with Reduced Selective Loss Defects

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

IDENTIFYING ACTUAL COWORKERS FOR A PARTICULAR JOB LISTING

A system and method for determining likely co-workers for a particular job listing is disclosed. The social networking system receives a request for a particular job listing from a client system associated with a first member of a social networking system. The social networking system determines one or more likely co-workers for a job described in the particular job listing. The social networking system communicates the particular job listing and member information for the determined one or more likely co-workers to the client system for display. 1. A method comprising:receiving a request for a particular job listing from a client system associated with a first member of a social networking system;determining one or more likely co-workers for a job described in the particular job listing; andcommunicating the particular job listing and member information for the determined one or more likely co-workers to the client system for display.2. The method of claim 1 , further comprising claim 1 , after receiving the request for the particular job listing claim 1 , determining a source organization associated with the particular job listing.3. The method of claim 1 , further comprising claim 1 , after receiving the request for the particular job listing claim 1 , transmitting a user-selectable likely co-worker link for display in a user interface at the client system.4. The method of claim 3 , further comprising claim 3 , prior to determining the one or more likely co-workers for the job described in the particular job listing claim 3 , receiving claim 3 , from the client system claim 3 , a request for likely co-worker information claim 3 , wherein the request is generated by selection of the user-selectable likely co-worker link.5. The method of claim 1 , further comprising receiving claim 1 , from a member of the social networking system claim 1 , job listing data for inclusion in a job listing database associated with the social networking system.6. The method of claim 5 ...

Short current-free effective capacitance test circuit and method

A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path.

Packaging Methods, Material Dispensing Methods and Apparatuses, and Automated Measurement Systems

Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

Series FinFET Implementation Schemes

A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET.

SLIDING MECHANISM AND PORTABLE ELECTRONIC DEVICE HAVING THE SAME

A sliding mechanism (40) includes a base plate (42), a first sliding plate (44), as second sliding plate (46), and a elastic element (48). The first sliding plate (44) is slidably mounted on the first sliding plate (44) and located adjacent to one side of the base plate (42). The second sliding plate (46) is slidably mounted on the second sliding plate (46) and located adjacent to an opposite side of the base plate (42). The elastic element (48) provides force for driving the first sliding plate (44) and the second sliding plate (46) to slide relative to the base plate (42) and in opposite directions.

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MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS

Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches. 1. An integrated circuit structure comprising:a trench in a material;a conductor in a lower portion of the trench;a first liner material lining a middle portion and an upper portion of the trench, the middle portion is between the lower portion and the upper portion;a fill material comprising an insulator in the middle portion of the trench; anda second material filling the upper portion of the trench.2. The integrated circuit structure according to claim 1 , wherein the first liner material contacts the conductor.3. The integrated circuit structure according to claim 1 , wherein the first liner material comprises silicon combined with at least one of nitrogen claim 1 , oxygen claim 1 , and carbon.4. The integrated circuit structure according to claim 1 , wherein the fill material comprises a flowable combination of silicon claim 1 , oxygen claim 1 , and carbon.5. The integrated circuit structure according to claim 1 , wherein the second material comprises a combination of silicon and nitrogen.6. The integrated circuit structure according to claim 1 , wherein the fill material has a dielectric constant lower than 3.0.7. The integrated circuit structure according to claim 1 , wherein the fill material has characteristics resulting from reactive ion etching (RIE).8. An integrated circuit structure comprising:a trench in a material;a ...

Source and drain epitaxy re-shaping

The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

Automatic generation of sub-cells for an analog integrated circuit

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Cover latch mechanism and portable electronic device using same

A cover latching mechanism (100) used in a portable electronic device is described including a latching base (20), a cover member (10), a latching member (40), and a releasing member (30). The cover member has a latching protrusion (14) arranged on it. The latching member is used to latch the cover member to the latching base and defines a latch space (464) and a release space (462). The cover member can be latched to the latching base by latching the latching protrusion into the latch space, and then be released from the latching base by the releasing member engaging into the release space.

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Differential amplifier without common mode feedback

A differential amplifier without common feedback is disclosed. The amplifier has a low gain fully differential amplifier and a high gain fully differential amplifier connected in parallel with the low gain fully differential amplifier. When first and second inputs feed into the low and high gain fully differential amplifiers, the low gain fully differential amplifier is used to bias the high gain fully differential amplifier so that a first and second voltage output generated by the high gain fully differential amplifier is stable during a common mode operation without being impacted by fluctuation of the inputs.

MATERIAL COMBINATIONS FOR POLISH STOPS AND GATE CAPS

Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process. 112-. (canceled)13. A structure comprising:a semiconductor substrate having a top surface;a gate electrode disposed on the top surface of the semiconductor substrate, the gate electrode having a top surface;a plurality of sidewall spacers including respective sections located above the top surface of the gate electrode, the respective sections of the sidewall spacers providing a border for a space arranged over the top surface of the gate electrode;a first liner disposed in the space over the top surface of the gate electrode, the first liner comprised of a dielectric material; anda dielectric cap disposed in the space over the first liner,wherein the first liner is a conformal layer that includes a horizontal section on the top surface of the gate electrode and respective vertical sections on the respective sections of the sidewall spacers.14. The structure of wherein the first liner is comprised of carbon-incorporated silicon oxide claim 13 , titanium oxide claim 13 , hafnium oxide claim 13 , or aluminum oxide claim 13 , and the dielectric cap is comprised of silicon nitride.1516-. (canceled)17. The structure of further comprising:a second liner in the space ...

Chamfered replacement gate structures

The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials.

Light-guide board assembly and portable electronic device using same

A light-guide board assembly includes a light-guide board, a shielding board disposed on the light-guide board, and a plurality of light-guide poles. The light-guide board defines a plurality of engaging holes, a plurality of light-focusing slots and a plurality of channels. One end of each light-guide pole is received in a corresponding engaging hole. The light-focusing slots focus light to strengthen the light emitted from the light-guide slots. Each engaging hole communicates with one adjacent engaging hole or an adjacent light-focusing slot through a channel.

Meta-hardened flip-flop

Some embodiments relate to a flip-flop having a data input terminal, a data output terminal and a clock terminal. The flip-flop includes a master latch, a slave latch, and an isolation element coupled between the master latch output and slave latch. The isolation element is arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch. In some embodiments, the master latch includes one or more drive enhancement elements on its feedforward and feedback paths. The slave latch can also include one or more drive enhancement elements on its feedforward and feedback paths. These drive enhancement elements, particularly in combination with the isolation element, may help to reduce the setup and hold times and enhance meta-stability resistance of the flip-flop relative to conventional implementations. Other embodiments are also disclosed.

Cover mechanism and electronic device using same

An electronic device using a cover mechanism to cover a hole is described. The cover mechanism includes a base member, a locking member, and a cover member. The cover member can be locked to the base member by locking of the cover member to the locking member when the cover member is in a locked position. The cover member can expose the hole and physically attach to the locking member when the cover member is in an opened position. The cover member can move relative to the locking member when the cover member is in a released position.

Analog cells utilizing complementary mosfet pairs

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

EPITAXIAL FEATURES IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME

A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing a portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing a semiconductor layer in the recess, and forming a first dielectric layer interposing the semiconductor layer and the dummy gate structure. The semiconductor layer covers at least a portion of the first dielectric layer. The method also includes modifying a shape of the semiconductor layer to expose the portion of the first dielectric layer, depositing a second dielectric layer covering the semiconductor layer and the portion of the first dielectric layer, and replacing the dummy gate structure with a metal gate structure.

AUTOMATIC GENERATION OF SUB-CELLS FOR AN ANALOG INTEGRATED CIRCUIT

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Portable electronic device

Battery cover latching assembly

A battery cover latching assembly, detachably securing a battery cover to a housing, includes a button, battery cover, elastic member arranged between the button and the housing, and a resisting member resisting the battery cover away from the housing. The button includes a locking portion. The battery cover includes a corresponding locking member. The locking portion is slidably received in the housing to clamp or release the locking member.

Rise time and fall time measurement

Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal.

Battery cover assembly for portable electronic device

A battery cover assembly for a portable electronic device is disclosed including a base member, a first cover member mating with the base member, a second cover member positioned between the base member and the first cover member, a third cover member engaging with the first cover member, a camera assembly secured to the base member, and a locking assembly engaging with the third cover member. The first cover member can horizontally rotate along the second cover member. The first cover member is rotatably attached to, and cannot be detached from the base member.

Side key assembly for portable electronic device

A side key assembly includes a metallic dome, an insulating layer and a decorative layer. The insulating layer is laminated on the dome. The decorative layer is laminated on the insulating layer.

Optical sensing device having inclined reflective surface

Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.

Stylus

Box structure for data storage device

A box structure for a data storage device is assembled in a chassis having a connector. The box structure includes a frame module, a holder, a stop assembly, and an operation handle. The frame module is provided for accommodating the data storage device. The holder is assembled on one side of the frame module. A damper is disposed between the holder and the frame module, the damper enables the holder to move along the frame module. A stop assembly is disposed at one end of the frame module. The stop assembly includes a stopper and a movable block in contact with the stopper, and the movable block is movable to release the stopper. The operation handle is pivotally connected to the frame module and is rotatable to form an open angle to push the movable block to move.

Side keypad assembly and portable electronic device using the same

A side keypad assembly includes a pressing surface, an opposite mating surface. The pressing surface includes a plurality of keypads protruded thereon. The mating surface includes a plurality of stepped columns protruded thereon corresponding to the plurality of keypads respectively and a plurality of separating protrusions corresponding to the conjoint portions between every two keypads respectively. The invention also provides a portable electronic device using the side keypad assembly.

Mobile phone

Enlarged sacrificial gate caps for forming self-aligned contacts

Methods of forming a sacrificial gate cap and a self-aligned contact for a device structure. A gate electrode is arranged between a first sidewall spacer and a second sidewall spacer. A top surface of the gate electrode is recessed to open a space above the top surface of the recessed gate electrode that partially exposes the first and second sidewall spacers. Respective sections of the first and second sidewall spacers, which are arranged above the top surface of the recessed gate electrode, are removed in order to increase a width of the space. A sacrificial cap is formed in the widened space.

Integration scheme for gate height control and void free RMG fill

A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Key assembly and portable electronic device using the same

A key assembly comprises a base plate, two elastic elements and a key body. The elastic elements are both mounted to the base plate, and the elastic elements are spaced from and opposite to each other. The key body is slidably mounted to the base plate between the two elastic elements. The key body includes a first key section and a second key section connected with the first key section. The first key section has an arcuate first contacting portion formed thereon. The second key section has an arcuate second contacting portion formed thereon. The first key section resists one of the two elastic elements, the second key section resisting another elastic element. When the first key section slides toward and compresses the elastic element that resists the first key section, the second key section slide away from the elastic element that resists the second key section.

RECOMMENDATIONS BASED ON SKILLS GAP IDENTIFICATION

System and methods for generating recommendations based on a determined skill gap are disclosed. A social networking system determines an employment role associated with a particular job listing, wherein the particular job listing has an associated source organization. The social networking system identifies one or more similar members associated with the source organization and having an employment role similar to the determined employment role. The social networking system generates a composite list of skills associated with the one or more similar members. The social networking system compares the skills included in the composite list of skills with a list of skills associated with the particular job listing to determine a list of missing skills. 1. A method comprising:determining an employment role associated with a particular job listing, wherein the particular job listing has an associated source organization;identifying one or more similar members associated with the source organization and having an employment role similar to the determined employment role;generating a composite list of skills associated with the one or more similar members; andcomparing the skills included in the composite list of skills with a list of skills associated with the particular job listing to determine a list of missing skills.2. The method of claim 1 , wherein determining the employment role associated with the particular job listing further comprises:analyzing the particular job listing to determine a list of required skills associated with the particular job listing.3. The method of claim 2 , wherein analyzing the particular job listing to determine the list of required skills associated with the particular job listing further comprises:parsing a text of the particular job listing to identify one or more keywords; andcomparing the one or more keywords to a reference list of skills to determine one or more associated skills.4. The method of claim 1 , further comprising: ...

Surface light source LED device

A surface light source LED device includes a circuit board, at least one power input and at least two LED bar elements, the at least two LED bar elements are arranged in a staggered manner, and each of the LED bar elements includes a plurality of LED bars arranged linearly on the circuit board. Each of the LED bars has a straight strip structure and has a plurality of LED dies of the same type provided inside. The plurality of LED dies is arranged linearly at equal intervals.

Cover latch mechanism and portable electronic device using same

A cover latching mechanism (100) used in a portable electronic device is described including a latching base (20), a cover member (10), and a latching member (30). The cover member has a latching protrusion (14) arranged thereon. The latching member is used to latch the cover member to the latching base and defines a latch space (338) and a release space (337). The cover member can be latched to the latching base by a movement of the latching protrusion from the release space into the latch space, and then be released from the latching base by an opposite movement of the latching protrusion from the latch space into the release space, the two movements being caused by pushing or pulling the cover member along the latching base.

Light source module, backlight module and display device

A light source module includes a back plate and light-emitting units. The back plate includes a bottom plate and a sidewall. An included angle is formed between an outer side surface of the sidewall and a horizontal plane where the bottom plate is located, and the included angle is an acute angle. An optical distance is defined between a top end of the sidewall and the horizontal plane. The light-emitting units are arranged in the back plate. The light-emitting units which are closest to the sidewall are defined as target light-emitting units, and each of the target light-emitting units has a radiation angle, and each of the target light-emitting units is separated from the sidewall by a distance. The first horizontal distance is determined by a tangent function of a complementary angle of the radiation angle, the second horizontal distance is determined by a tangent function of the included angle.

Keyboard structure and electronic device using the same

A keyboard structure includes a housing having at least one post, a key assembly, and at least one connecting part. The key assembly includes a number of keypads and a keymat, the keymat defining a first through hole, a second through hole and a groove. The connecting part includes a ring, a protruding post and a connecting portion connecting the protruding post to the ring, the connecting part received in the first through hole, the second through hole and the groove, and then fixed on the keymat. The post passes through the key assembly and the ring coils around the post to connect the key assembly to the housing.

Backlight module and liquid crystal display

A backlight module and a liquid crystal display are described. The backlight module includes a light guide plate, a light source and a prism sheet. The light guide plate includes a light-emitting surface, a light-incident surface and an axis. The light-incident surface is connected to the light-emitting surface. The axis is normal to the light-incident surface. The light source emits light towards the light-incident surface. The prism sheet is disposed on the light guide plate and includes a first optical surface and a plurality of prism structures which are disposed on the first optical surface. Each of the prism structures has a first surface and a second surface. The first surface and the second surface are connected to form a ridge. The ridge is vertical to the light-incident surface, or an angle included between the ridge and the axis is smaller than or equal to 20 degrees.

Bandgap reference circuit, control circuit, and associated method thereof

A bandgap reference circuit includes: a current generating circuit, a start-up circuit, a switch circuit, and a control circuit. The current generating circuit is arranged to generate a reference current according to a control signal on a control node. The start-up circuit is coupled to the current generating circuit and arranged to generate a trigger signal and output the trigger signal as the control signal when the bandgap reference circuit starts up. The switch circuit is coupled to the current generating circuit and arranged to generate a bandgap voltage according to the reference current, and the bandgap voltage is outputted to a regulator coupled to the bandgap reference circuit. The control circuit is coupled to the control node and the switch circuit and arranged to generate a switch control signal according to the trigger signal, and the switch control signal controls a switch status of the switch circuit.

Portable electronic device

A portable electronic device comprises a cover and a body. The cover comprises a first end wall, a second end wall opposite to the first end wall, and a sidewall connecting the first end wall and the second end wall. The sidewall defines a sliding slot. Two ends of the sliding slot respectively extend to the first end wall and the second end wall. The body comprises a protrusion formed thereon. The protrusion is slidably received in the sliding slot. The protrusion slides to the first end wall or the second end wall, whereby the cover hinges on the protrusion relative to the body.

Battery cover latching assembly

A battery cover latching assembly comprises a battery housing member, a battery cover and a plurality of latching members. The battery cover is mounted to the battery housing and has a first surface facing the battery housing member. The battery cover has a plurality of latching portions protruding from the first surface. The latching members are mounted to the battery housing member respectively corresponding to the latching portions of the battery cover. Each latching member has a plurality of hooks corresponding to the latching portions, the hooks are latched with the latching portions.

ARRAY MODELING FOR ONE OR MORE ANALOG DEVICES

Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example. 1. A method for creating an array model for analog device modeling , comprising:creating a mean array comprising one or more mean elements, a mean element of the one or more mean elements of the mean array associated with an array set of coordinates within an array model, the mean element comprising a mean value indicative of a mean of an analog device characteristic for one or more analog devices at a physical set of coordinates mapped from the array set of coordinates, the physical set of coordinates indicative of a physical location of the one or more analog devices within a circuit layout;creating a standard deviation array comprising one or more standard deviation elements, a standard deviation element of the one or more standard deviation elements of the standard deviation array associated with the array set of coordinates within the array model, the standard deviation element comprising a standard deviation value indicative of a standard deviation of the analog device characteristic for the one or more analog devices at the physical set of coordinates; andcreating the array model based on the mean array and the ...

Electro-migration barrier for Cu interconnect

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.

Circuit and method for measuring the gain of an operational amplifier

A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.

Cover mechanism and electronic device using same

An electronic device using a cover mechanism to cover a hole is described. The cover mechanism includes a base member, a cover member and a retaining member. The cover member is fixed with the retaining member and moves between a closed position and an opened position. In the closed position, the cover member is elastically, partially deformed to lock to the base member. In the opened position, the cover member can be elastically bent to expose the hole while still being physically attached to the base member.

Device and method for image control

An image control device and an image control method are provided. The image control device includes a control command output port, an image input port, a processor and an image output unit. The control command output port transmits a scene switching command to an image source device; the image input port receives an image stream from the image source device; the processor is coupled to the image input port and the control command output port to retrieve a first image and a second image from the image stream, wherein the second image corresponds to the scene switching command; the image output unit is coupled to the processor and outputs the first image and the second image, wherein the first image is displayed in a first display area and the second image is displayed in a second display area.

Analog cells utilizing complementary mosfet pairs

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Mobile phone

Mobile phone

OPTICAL IMAGING SYSTEM WITH ENCAPSULATION AND TETHER

A tethered imaging camera encapsulated in a shell lens element of such camera enables viewing from inside and imaging of a biological organ in/from a variety of directions. A portion of camera's optical system together with light source(s) and optical detector mutually cooperated by housing structure inside the shell are moveable/re-orientable within the shell to vary a desired view of the object space without interruption of imaging process. A tether carries electrical but not optical signals to and from the camera and controllable traction cords to move the camera, and a hand-control unit and/or electronic circuitry configured to operate the camera and power its movements. Method(s) of using optical, optoelectronic, and optoelectromechanical sub-systems of the camera.

Mobile phone

Mobile phone

Waterproof electronic device

A waterproof electronic device includes an upper shell and a lower shell configured for detachably and hermetically assembling with the upper shell. At least one of the upper shell and lower shell comprising a rubber layer disposed thereon to hermetically assemble with each other. The invention further provides a method for making the waterproof electronic device.

Key assembly and portable electronic device using the same

A key assembly comprises a base plate, a connecting member, a first key and a second key. The base plate has an opening defined therein. The connecting member is rotatably accommodated in the opening. The first key is rotatably hinged one side of the connecting member. The second key is rotatably hinged another side of the connecting member opposite to the first key. When the first key or the second key is pressed, the pressed key is rotated toward the base plate and rotates the connecting member, and the connecting member rotates the non-pressed key away from the base plate.

Scan flip-flop circuit having fast setup time

A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.

Battery cover assembly for portable electronic device

A battery cover assembly for a portable electronic device includes a housing, a battery cover, and a pivot member. The housing forms a first latch portion and a second latch portion, the first latch portion and the second latch portion being arranged at a circle. The battery cover forms a first engaging portion and a second engaging portion engaging with the first latch portion and a second latch portion to allow the battery cover to releasably latch to the housing. The pivot member rotatably connects the battery cover to the housing.

AUTOMATIC GENERATION OF SUB-CELLS FOR AN ANALOG INTEGRATED CIRCUIT

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells. 1. A method of fabricating an analog integrated circuit , the method comprising:receiving partition information for the analog integrated circuit, wherein the partition information defines types of sub-cells within the analog integrated circuit;determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of the integrated circuit, the first direction and the second direction being orthogonal to each other;partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations; andmerging the plurality of sub-cells to produce a layout diagram of the analog integrated circuit.2. The method of claim 1 , further comprising verifying each sub-cell in the plurality of sub-cells prior to merging the sub-cells.3. The method of claim 2 , wherein verifying each sub-cell in the plurality of sub-cells comprises performing design rule checks on each sub-cell in the plurality of sub-cells.4. The method of claim 2 , wherein verifying each sub-cell in the plurality of sub-cells comprises performing a layout versus layout check on each sub-cell in the plurality of sub- ...

Cover lens with touch-sensing function and method for fabricating the same

A cover lens with touch-sensing function is provided, which is combined onto an external side of an electronic device and allows the touch-sensing and protection for the electronic device. The provided cover lens is constructed by a tempered substrate, a pattern layer and a touch-sensing layer, where the pattern layer is formed on a first surface of the tempered substrate so as to provide the cover lens with an appearance of periphery-like pattern. The touch-sensing layer is also formed on the first surface of the tempered substrate. The present invention also provides a touch display having such cover lens and the fabricating method thereof.

UART interface circuit and UART data capturing method

An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

Mobile phone

OPTICAL IMAGING SYSTEM WITH ENCAPSULATION AND TETHER

A tethered imaging camera encapsulated in a shell lens element of such camera enables viewing from inside and imaging of a biological organ in/from a variety of directions. A portion of camera's optical system together with light source(s) and optical detector mutually cooperated by housing structure inside the shell are moveable/re-orientable within the shell to vary a desired view of the object space without interruption of imaging process. A tether carries electrical but not optical signals to and from the camera and controllable traction cords to move the camera, and a hand-control unit and/or electronic circuitry configured to operate the camera and power its movements. Method(s) of using optical, optoelectronic, and optoelectromechanical sub-systems of the camera.

LED package with multiple test pads and parallel circuit elements

A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

COVER MECHANISM AND ELECTRONIC DEVICE USING SAME

An electronic device using a cover mechanism to cover a hole is described. The cover mechanism includes a base member, a cover member and a retaining member. The cover member is fixed with the retaining member and moves between a closed position and an opened position. In the closed position, the cover member is elastically, partially deformed to lock to the base member. In the opened position, the cover member can be elastically bent to expose the hole while still being physically attached to the base member.

Electro-migration barrier for Cu interconnect

The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.

Method for Measuring Capacitances of Capacitors

A capacitor measurement circuit for measuring a capacitance of a test capacitor includes a first transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; and a current-measuring device configured to measure a first charging current and a second charging current of the test capacitors. The first and the second charging currents flow to the test capacitor in opposite directions.

Usb hub and power management method thereof

A USB HUB is provided. The USB HUB comprises a wireless communication module, a storage module, a USB interface connected to a host outside of the USB HUB and a HUB controller. The storage module stores a driver program of the wireless communication module. The USB interface transfers data with the host. The HUB controller is coupled to the USB interface, the wireless communication module and the storage module. The HUB controller disables the storage module and enables the wireless communication module when the driver program has been installed in the host.

SCAN FLIP-FLOP CIRCUIT HAVING FAST SETUP TIME

A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode. 1. A scan flip-flop circuit comprising:an input stage for providing a data signal to a data node, wherein the input stage comprises first and second stacks of transistors devices coupled to the data node, the first stack receiving a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node;a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal;a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; anda scan and clock control logic module, the scan and clock control logic module controlling the first stack to input the data input signal to the data node during normal operation mode.2. The scan flip-flop circuit of claim 1 , wherein the scan and clock control logic module controls the first stack to input the data input signal to the data node only when a clock signal is logical high and a scan enable signal represents normal ...

Methods and Apparatus for Time to Current Conversion

A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided. 1. A method , comprising:coupling a known signal to an impedance;observing a current through the impedance for a number of cycles to establish a first average current corresponding to a time related parameter of the known signal;coupling an unknown periodic signal to the impedance;observing the current through the impedance for a number of cycles to establish a second average current corresponding to a time related parameter of the unknown periodic signal; anddetermining a timing characteristic of the unknown signal by comparing the first and second currents.2. The method of claim 1 , wherein the known signal is a clock signal with a known frequency.3. The method of claim 1 , wherein the impedance is a linear impedance.4. The method of claim 3 , wherein the impedance is a resistor.5. The method of claim 1 , wherein the impedance is a non-linear impedance.6. The method of claim 1 , wherein the known signal is a DC voltage.7. The method of claim 1 , wherein the known signal is a time varying periodic signal of a fixed duty cycle.8. The method of claim 1 , wherein ...

PULSE GENERATOR

A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal. 1. A circuit , comprising:a first logic gate configured to receive a clock signal at a first input; anda latch disposed in a feedback loop of the first logic gate, the latch configured to output a feedback signal to a second input of the first logic gate in response to a signal output by the first logic gate and the clock signal,wherein the circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.2. The circuit of claim 1 , wherein the latch includes a second logic gate that is cross-coupled to a third logic gate.3. The circuit of claim 2 , wherein the first claim 2 , second claim 2 , and third logic gates are NAND gates.4. The circuit of claim 2 , wherein the first claim 2 , second claim 2 , and third logic gates are NOR gates.5. The circuit of claim 2 , wherein a first input coupled to an input of the first logic gate, and', 'a second input coupled to an output of the third logic gate and to an input of the first logic gate; and, 'the second logic gate includes a first input coupled to an output of the second logic gate, and', 'a second input configured to receive the clock signal., 'the third logic gate includes6. The circuit of claim 5 , wherein the third logic gate includes a third input configured to receive a pulse mode signal for switching the circuit between a first mode in which the pulsed signal output tracks the clock signal and a second mode in which the pulsed signal differs from the clock signal.7. The circuit of claim 5 , further comprising an ...

SWITCHING METHOD FOR ELECTRONIC DEVICE

A switching method for an electronic device having sensing regions is mentioned. The switching method is configured to detect signals received by the electronic device, so as to switch the states of the electronic device. The switching method comprises receiving a first signal at a first moment and receiving a second signal at a second moment, wherein the first signal is generated by touching a first sensing region and the second signal is generated by touching a second sensing region; measuring a triggering duration and determining whether the triggering duration is consistent with a predetermined duration, when the first signal and the second signal are inputted simultaneously; switching the electronic device from a first state to a second state, if the triggering duration is consistent with the predetermined duration; and maintaining the electronic device in the first state, if the triggering duration is not consistent with the predetermined duration. 1. A switching method for an electronic device having a plurality of sensing regions , the switching method being configured to detect signals received by the electronic device and switch the states of the electronic device , the switching method comprising:receiving a first signal at a first moment and receiving a second signal at a second moment, the first signal being generated by touching a first sensing region and the second signal being generated by touching a second sensing region;measuring a triggering duration and determining whether the triggering duration being consistent with a predetermined duration, when the first signal and the second signal being inputted simultaneously;switching the electronic device from a first state to a second state, when the triggering duration is consistent with the predetermined duration; andmaintaining the electronic device in the first state, if the triggering duration is not consistent with the predetermined duration.2. The switching method according to claim 1 , wherein ...

INSTALLATION STRUCTURE OF COUNTERTOP FAUCET

An installation structure of countertop faucet includes a base having an insertion section extending through a mounting hole formed in a counter to engage a locking nut to be secured. The insertion section has a top end forming a receiving bore of which a circumferential wall forming two positioning holes communicating with the receiving bore. Each positioning hole receives therein a releasing module. The bottom of the base forms two water inlet passages communicating with the receiving bore and receiving stop valves therein and coupled to couplers for connection with water inlet tubes. A faucet has a joint section received in the receiving bore and having water guide tubes fit into the water inlet passages. The joint section forms two receiving apertures receiving therein positioning modules respectively engageable with the positioning holes to fix the faucet and being released by the releasing module to detach the faucet from the base. 1. An installation structure of countertop faucet , comprising:a base, which comprises a seat that is adapted to abut an underside of a top of a counter and an insertion section having a reduced diameter and extending through a mounting hole of the counter to partially project beyond the counter , the insertion section having a top end in which a receiving bore is formed and delimited by a circumferential wall that has an outside surface forming an external thread section and two positioning holes that are formed in and extending through the circumferential wall at a location above the external thread section to be in communication with the receiving bore, the seat having a bottom surface in which two water inlet passages are formed to communicate with the receiving bore;a locking nut, which is fit to and engages the external thread section of the insertion section in order to cooperate with the seat to clamp the counter;a faucet, which comprises a joint section that is receivable in the receiving bore, the joint section having a ...

DEVICE PERFORMANCE ENHANCEMENT

Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example. 1. A method for enhancing performance of a device , comprising:forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region; andforming a device exhibiting enhanced performance by connecting a gate to the active region.2. The method of claim 1 , forming the device comprising connecting the extended dummy region comprising a non-desired profile to the gate.3. The method of claim 1 , connecting the gate to the active region comprising connecting a dummy gate to the active region.4. The method of claim 3 , comprising biasing at least one of the dummy gate or the extended dummy region.5. The method of claim 3 , comprising floating at least one of the dummy gate or the extended dummy region.6. The method of claim 3 , comprising at least one of:{'sub': 'DD', 'connecting the dummy gate to V; or'}{'sub': 'SS', 'connecting the dummy gate to V.'}7. The method of claim 1 , comprising at least one of:{'sub': 'DD', 'connecting the extended dummy region to V; or'}{'sub': 'SS', 'connecting the extended dummy region to V.'}8. The method of ...

SURFACE LIGHT SOURCE LED DEVICE

A surface light source LED device includes a circuit board, at least one power input and at least two LED bar elements, the at least two LED bar elements are arranged in a staggered manner, and each of the LED bar elements includes a plurality of LED bars arranged linearly on the circuit board. Each of the LED bars has a straight strip structure and has a plurality of LED dies of the same type provided inside. The plurality of LED dies is arranged linearly at equal intervals. 1. A surface light source LED (light-emitting diode) device , comprising:a circuit board having an connection circuit disposed on an upper layer of the circuit board;at least one power input electrically coupled to the circuit board; andat least two LED bar elements disposed on the circuit board and electrically coupled to the at least one power input; wherein each of the at least two LED bar elements includes a plurality of LED bars linearly arranged on the circuit board; each of the plurality of LED bars has a straight strip structure, and includes a plurality of LED dies of the same type disposed therein, the plurality of LED dies are arranged with equal intervals there between, the equal intervals are between 0.15 mm and 2.8 mm;wherein intervals between each of the plurality of LED bars are the same as the equal intervals between each of the plurality of LED dies; each of the plurality of LED bars has a wide-angle lens disposed thereon such that a cross-sectional light-emitting angle of each of the plurality of LED bars is diffused; and wherein the wide-angle lens is integrally formed during the molding of each of the plurality of LED bars, and covers upon the plurality of LED dies of each of the plurality of LED bars;wherein each one of the wide-angle lens of the plurality of LED bars has an upper surface, the cross section of the upper surface is a double-arced shape, the two sides surfaces of the wide-angle lens are perpendicular shape, and the wide-angle lens is in a strip structure; ...

CAP STRUCTURE

The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure. 1. A method comprising:forming a gate structure composed of conductive gate material;forming a first capping material on the conductive gate material;forming sidewall spacers on the gate structure and the first capping material;recessing the first capping material below the sidewall spacers; andforming a second capping material on the first capping material, the second capping material overhanging the sidewall spacers.2. The method of claim 1 , further comprising planarizing or etching back the second capping material to overhang the sidewall spacers claim 1 , and forming a T-shaped capping structure composed of the first capping material and the second capping material.3. The method of claim 2 , wherein the first capping material is nitride material and the second capping material is an etch resistant material that is a different material than the nitride material.4. The method of claim 1 , wherein the first capping material is formed directly on the conductive gate material and comprises a recessed portion between the sidewall spacers on the gate structure.5. The method of claim 4 , wherein the second capping material is formed within the recessed portion of the first capping material and extends over and in direct contact with a top surface of the sidewall spacers on the gate structure.6. The method of claim 5 , wherein the second capping material is T-shaped and the second capping material is a top material that is resistant to etch chemistries and which overhangs over the sidewall spacers.7. The method of claim 6 , wherein the first capping material ...

TOUCH DISPLAY DEVICE

A touch display device is disclosed, which comprises: a display; a touch panel disposed on the display; and a protective layer disposed on the touch panel, wherein at least one of the high refractive layer is disposed between the protective layer and the touch panel, and the high refractive layer has a refractive index greater than 1.5 and less than 2.0. 1. A touch display device , comprising:a display;a touch panel disposed on the display; anda protective layer disposed on the touch panel,wherein at least one of the high refractive layer is disposed between the protective layer and the touch panel, and the high refractive layer has a refractive index greater than 1.5 and less than 2.0.2. The touch display device of claim 1 , wherein at least one of the high refractive layer comprises a polarizer disposed on a surface of the protective layer.3. The touch display device of claim 1 , wherein at least one of the high refractive layer comprises a polarizer disposed on a surface of the touch panel.4. The touch display device of claim 1 , wherein at least one of the high refractive layer comprises an adhesive layer disposed on a surface of the protective layer.5. The touch display device of claim 1 , wherein at least one of the high refractive layer comprises an adhesive layer disposed on a surface of the touch panel.6. The touch display device of claim 1 , wherein at least one of the high refractive layer comprises a plurality of adhesive layers.7. The touch display device of claim 6 , wherein a polarizer is disposed between the adhesive layers.8. The touch display device of claim 5 , wherein the adhesive layer is an optical clear adhesive (OCA) claim 5 , or an optical clear resin (OCR).9. The touch display device of claim 6 , wherein the adhesive layer is an optical clear adhesive (OCA) claim 6 , or an optical clear resin (OCR).10. The touch display device of claim 7 , wherein the adhesive layer is an optical clear adhesive (OCA) claim 7 , or an optical clear resin (OCR ...

LIGHT GUIDE PLATE WITH MULTI-DIRECTIONAL STRUCTURES

A light guide plate with multi-directional structures includes a main body, a plurality of first microstructures and a plurality of second microstructures. The main body includes a light-incident surface, a light-emitting surface and a reflecting surface. The light-incident surface connects the light-emitting surface and the reflecting surface. The first microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a first extending direction. The second microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a second extending direction. The second microstructures and the first microstructures are disposed on the same plane and intersect with each other. Each of the second microstructures is a single stripe pattern, and has a width which becomes gradually smaller from one end of the second microstructure near the light-incident surface to the other end of the second microstructure away from the light-incident surface. 1. A light guide plate with multi-directional structures , the light guide plate comprising: a light-incident surface;', 'a light-emitting surface; and', 'a reflecting surface opposite to the light-emitting surface, wherein the light-incident surface connects the light-emitting surface and the reflecting surface;, 'a main body, comprisinga plurality of first microstructures disposed on the light-emitting surface or the reflecting surface, wherein the first microstructures are arranged along a first extending direction;a plurality of second microstructures disposed on the light-emitting surface or the reflecting surface, wherein the second microstructures are arranged along a second extending direction, wherein the second microstructures and the first microstructures are disposed on the same plane and intersect with each other, wherein each of the second microstructures is in a single stripe pattern, and has a width which becomes gradually smaller from one end of ...

ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT

The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer. 1. An integrated circuit device , comprising:a substrate;a conductive metal interconnect line arranged within a dielectric material disposed over the substrate;an interfacial layer in contact with an upper surface of the conductive metal interconnect line;an upper dielectric layer arranged over the interfacial layer; anda middle dielectric layer arranged between the upper dielectric layer and the interfacial layer.2. The integrated circuit device of claim 1 , further comprising:a liner arranged along one or more surfaces of the conductive metal interconnect line not contacting the interfacial layer.3. The integrated circuit device of claim 2 , wherein the middle dielectric layer contacts the liner.4. The integrated circuit device of claim 1 , wherein the middle dielectric layer laterally and vertically contacts the interfacial layer.5. The integrated circuit device of claim 1 , wherein the middle dielectric layer laterally and vertically contacts the upper dielectric layer.6. An integrated circuit device claim 1 , comprising:a conductive metal interconnect line arranged within an inter-level dielectric material;an interfacial layer extending over an upper surface of the conductive metal interconnect line;a liner arranged along one or more surfaces of the conductive metal interconnect line not contacting the interfacial layer;a second dielectric layer overlying the interfacial layer and the liner; anda second inter-level dielectric material ...

METHODS, APPARATUS, AND SYSTEM TO CONTROL GATE HEIGHT AND CAP THICKNESS ACROSS MULTIPLE GATES

At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner. 1. A method , comprising:forming a first gate having a first width and comprising a first gate metal having a first height; and first spacers on the sides of the first gate and having a first spacer height greater than the first height;forming a second gate having a second width and comprising a second gate metal having a second height, wherein the first width is less than the second width and the first height is greater than the second height; and second spacers on the sides of the second gate and having a second spacer height greater than the second height;filling a first region between the first spacers on the sides of the first gate and above the first gate metal with a third spacer material;depositing conformally the third spacer material in a second region between the second spacers on the sides of the second gate, and on a top of the second gate metal;removing the third spacer material from the top of the second gate metal, wherein the first gate metal remains covered by the third spacer material; andadding metal to the second gate metal, thereby raising the top of the second gate metal to about the first height.2. The method of claim 1 , further comprising:filling the first region and the second region with a cap spacer.3. The method of claim 1 , wherein the first gate comprises a first liner disposed below and to the sides ...

DEVICE AND METHOD FOR MEASURING CHARACTERISTICS OF A WAFER

A device for measuring characteristics of a wafer is provided. The device comprises a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit. 1. A device for measuring characteristics of a wafer , comprising:a first circuit on the wafer and having a first number of parallelly connected oscillators; anda second circuit on the wafer and having the first number of parallelly connected oscillators; whereinthe second circuit is electrically connected to the first circuit, and a first portion of the second circuit is disconnected from a second portion of the second circuit.2. The device of claim 1 , further comprising a third circuit on the wafer and having the first number of parallelly connected oscillators.3. The device of claim 1 , further comprising a first driver coupled with the first circuit and the second circuit claim 1 , wherein the first driver is configured to receive a first clock signal and a second clock signal.4. The device of claim 3 , further comprising a second driver coupled with the third circuit claim 3 , wherein the second driver is configured to receive the first clock signal and the second clock signal.5. The device of claim 3 , wherein a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal.6. The device of claim 3 , wherein a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal.7. The device of claim 1 , wherein the first portion of the second circuit is formed during the front-end-of-line of the wafer claim 1 , and the second portion of the second circuit is formed during the back-end-of-line of the wafer.8. The device of claim 1 , wherein a first portion of the first circuit is disconnected from a second portion of ...

BACKLIGHT MODULE AND LIQUID CRYSTAL DISPLAY

A backlight module and a liquid crystal display are described. The backlight module includes a light guide plate, a light source and a prism sheet. The light guide plate includes a light-emitting surface, a light-incident surface and an axis. The light-incident surface is connected to the light-emitting surface. The axis is normal to the light-incident surface. The light source emits light towards the light-incident surface. The prism sheet is disposed on the light guide plate and includes a first optical surface and a plurality of prism structures which are disposed on the first optical surface. Each of the prism structures has a first surface and a second surface. The first surface and the second surface are connected to form a ridge. The ridge is vertical to the light-incident surface, or an angle included between the ridge and the axis is smaller than or equal to 20 degrees. 1. A backlight module , comprising: a light-emitting surface;', 'a light-incident surface connected to the light-emitting surface, and', 'an axis normal to the light-incident surface;, 'a light, guide plate, comprisinga light source emitting light towards the light-incident surface; and a first optical surface facing the light-emitting surface; and', 'a plurality of prism structures disposed on the first optical surface, wherein each of the prism structures has a first surface and a second surface, and the first surface and the second surface are connected to form a ridge, wherein the ridge is vertical to the light-incident surface of the light guide plate, or an angle included between the ridge and the axis is smaller than or equal to 20 degrees., 'a prism sheet disposed on the light guide plate, the prism sheet comprising2. The backlight module of claim 1 , wherein a first angle is included between the first optical surface and the first surface of each of the prism structures claim 1 , and a second angle is included between the first optical surface and the second surface of each of the ...

HANDLE STRUCTURE AND SERVER USING THE SAME

A handle structure includes a holding member, a press member, and a hook. The holding member includes a holding portion and a space formed in the holding portion. The press member includes a press portion and a plurality of adjustment holes. The press portion is movably disposed in the space. The adjustment holes are disposed on the other end of the press member opposite to the press portion. The hook includes a clasp portion and at least one fastening hole. The fastening hole is adjustably positioned corresponding to any of the adjustment holes, and the clasp portion is movable along with the movement of the press portion, wherein the clasp portion protrudes out of the holding member. The hook moves by pressing the press portion. 1. A handle structure , comprising:a holding member including a holding portion and a space formed in the holding portion;a press member including a press portion and a plurality of adjustment holes, the press portion being movably disposed in the space, wherein each of the adjustment holes is disposed on an end of the press member opposite to the press portion; anda hook including a clasp portion and at least one fastening hole, the at least one fastening hole being adjustably positioned corresponding to any of the adjustment holes, the clasp portion being movable along with the movement of the press portion, wherein the clasp portion protrudes out of the holding member.2. The handle structure of claim 1 , further comprising a first fastening element claim 1 , a second fastening element claim 1 , and a resilient element claim 1 , the first fastening element fastening the press member to the holding member claim 1 , the second fastening element passing through the at least one fastening hole to be positioned in a corresponding one of the adjustment holes claim 1 , the resilient element being disposed between the holding member and the press member.3. The handle structure of claim 2 , wherein the holding portion further includes two ...

ELECTRO-MIGRATION BARRIER FOR INTERCONNECT

The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric. 1. An integrated circuit , comprising:a conductive interconnect disposed on a dielectric over a substrate;a first liner arranged along an upper surface of the conductive interconnect;a barrier layer arranged along a lower surface of the conductive interconnect and contacting an upper surface of the dielectric, wherein the barrier layer and the first liner surround the conductive interconnect; anda second liner located over the first liner and having a lower surface contacting the upper surface of the dielectric.2. The integrated circuit of claim 1 , wherein the first liner is completely confined above the upper surface of the conductive interconnect.3. The integrated circuit of claim 1 , wherein the second liner is arranged directly between a bottommost surface of the first liner and the upper surface of the dielectric.4. The integrated circuit of claim 1 , wherein the second liner comprises an upper surface that protrudes laterally outward from a bottom of a sidewall of the second liner facing the conductive interconnect.5. The integrated circuit of claim 4 , wherein the upper surface is laterally between the sidewall of the second liner and a sidewall of the conductive interconnect.6. The integrated circuit of claim 1 ,wherein the barrier layer extends along a bottommost surface and sidewalls of the conductive interconnect; andwherein the first liner contacts sidewalls of the barrier layer, upper surfaces of the barrier layer, and the ...

FREQUENCY SYNTHESIZER

A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value. 1. A frequency synthesizer comprising:a reference oscillator configured to generate a first clock signal with a reference frequency;a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value, the divider controller configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain a controller output value; anda divider configured to receive the first clock signal and the controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.2. The frequency synthesizer of claim 1 , wherein the divider controller is configured to communicate error information to the reference oscillator in a feedback loop to enable the reference oscillator to adjust the frequency of the first clock signal.3. The frequency synthesizer of claim 2 , wherein the reference oscillator is a digitally controller oscillator.4. The frequency synthesizer of claim 3 , wherein the digitally controlled oscillator is configured to adjust the frequency of the first clock signal in a predetermined frequency value.5. The frequency synthesizer of claim 1 , ...

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

A semiconductor structure and a method of fabricating the semiconductor structure are disclosed herein. The semiconductor structure includes a substrate, a strain-inducing layer and an epitaxy structure. The strain-inducing layer is disposed on the substrate, and the epitaxy structure is embedded in the strain-inducing layer and not in contact with the substrate. 1. A semiconductor structure , comprising:a substrate;a strain-inducing layer disposed on the substrate;a gate dielectric layer disposed on the strain-inducing layer, wherein the gate dielectric layer and the strain-inducing layer are in contact;a gate electrode disposed on the gate dielectric layer; andan epitaxy structure embedded in the strain-inducing layer and not in contact with the substrate.2. The semiconductor structure of claim 1 , wherein the strain-inducing layer and the epitaxy structure comprises germanium (Ge) claim 1 , silicon germanium (SiGe) claim 1 , or a combination thereof.3. The semiconductor structure of claim 2 , wherein the strain-inducing layer and the epitaxy structure are formed of silicon germanium.4. The semiconductor structure of claim 3 , wherein the silicon germanium of the epitaxy structure is higher than the silicon germanium of the strain-inducing layer in germanium percentage.5. The semiconductor structure of claim 3 , further comprising a cap layer on the epitaxy structure.6. The semiconductor structure of claim 5 , wherein the cap layer is formed of silicon germanium claim 5 , and the silicon germanium of the epitaxy structure being higher than the silicon germanium of the cap layer in germanium percentage.7. The semiconductor structure of claim 3 , wherein the epitaxy structure is a bi-layer structure claim 3 , comprising:a first portion; anda second portion surrounding the first portion and in contact with the strain-inducing layer, and the silicon germanium of the first portion being higher than the silicon germanium of the second portion in germanium percentage.8. ...

SHORT CURRENT-FREE EFFECTIVE CAPACITANCE TEST CIRCUIT AND METHOD

A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path. 1. A method comprising:determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter along a first communication path, the first communication path being divided into a second communication path and a third communication path, the second communication path having connectivity to a first voltage source, a first ground path and the inverter, the third communication path having connectivity to the first voltage source, the first ground path and the inverter;determining a first current associated with the third communication path; anddetermining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the first current and the frequency of the oscillator signal communicated to the inverter along the third communication path.2. The method of claim 1 , further comprising:generating a non-overlapping clock to facilitate communicating the oscillator signal along the third communication path and an out-of-phase signal along the second communication path,wherein the effective capacitance is determined by excluding the out-of-phase signal from the effective capacitance determination.3. The method of claim 1 , ...

GATE STACK PROCESSES AND STRUCTURES

Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer. 1. A method for forming a field-effect transistor , the method comprising:forming a gate cavity in a dielectric layer that includes a bottom surface and a plurality of sidewalls extending to the bottom surface;forming a gate dielectric layer at the sidewalls and the bottom surface of the gate cavity;depositing a first work function metal layer on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity; andafter the first work function metal layer is deposited, forming a fill metal layer inside the gate cavity,wherein the fill metal layer is formed in direct contact with the first work function metal layer.2. The method of wherein forming the fill metal layer inside the gate cavity that is in direct contact with the first work function metal layer comprises:conformally depositing a first fluorine-free tungsten layer on the first work function metal layer.3. The method of wherein forming the fill metal layer inside the gate cavity that is in direct contact with the first work function metal layer further comprises:depositing a conductor layer on the first fluorine-free tungsten layer,wherein the conductor layer fills empty space remaining inside the gate cavity after the first fluorine-free tungsten layer is deposited.4. The method of wherein the first fluorine-free tungsten layer is formed ...

HEATING DEVICE WITH ALARM FUNCTION

A heating device with an alarm function includes an alarm unit, an input module, a heating unit, a temperature sensor, and a controller. The input module is used for setting a target temperature and an alarm activation time. The heating unit is used for heating a container. The temperature sensor is used for sensing a current temperature of the container. The controller controls the heating unit to heat the container when a current time reaches a predetermined time previous to the alarm activation time. The controller selectively controls the heating unit to stop heating the container or keep the current temperature at the target temperature when the current temperature reaches the target temperature or when the current time reaches the alarm activation time. The controller controls the alarm unit to output an alarm when the current time reaches the alarm activation time. 1. A heating device with an alarm function comprising:an alarm unit;an input module for setting a target temperature and an alarm activation time;a heating unit for heating a container;a temperature sensor for sensing a current temperature of the container; anda controller electrically connected to the alarm unit, the input module, the heating unit, and the temperature sensor, the controller having a timer for providing a current time;wherein the controller controls the heating unit to heat the container when the current time reaches a predetermined time previous to the alarm activation time, determines whether the current temperature reaches the target temperature, and determines whether the current time reaches the alarm activation time; the controller selectively controls the heating unit to stop heating the container or keep the current temperature at the target temperature when the current temperature reaches the target temperature or when the current time reaches the alarm activation time; and the controller controls the alarm unit to output an alarm when the current time reaches the alarm ...

ON-CHIP OSCILLOSCOPE

A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal. 1. A device , comprising:a control circuit configured to delay a voltage signal to generate a first control signal; anda scope circuit configured to be operated in one of a first mode and a second mode according to the first control signal,wherein in the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.2. The device of claim 1 , wherein the scope circuit comprises:a transmission gate, wherein in the first mode, the transmission gate is configured to be turned on to transmit the voltage signal.3. The device of claim 2 , wherein in the second mode claim 2 , the transmission gate is configured to be turned off.4. The device of claim 1 , wherein the scope circuit comprises:a first switch, wherein in the second mode, the first switch is configured to be turned on.5. The device of claim 4 , wherein in the first mode claim 4 , the first switch is configured to be turned off.6. The device of claim 1 , wherein the control circuit comprises:a delay unit configured to delay the voltage signal, to generate a second control signal, wherein the delay unit is controlled according to a control voltage.7. The device of claim 1 , wherein the control circuit is further configured to generate a second control signal claim 1 , the first control signal and the second control signal are different ...

Nanosheet semiconductor device and method for manufacturing the same

A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Mask inspection device and method thereof

Provided herein is a mask inspection device, including an inspection base, a shift platform, a rotating platform, a bearing platform, a laser ranging module, a vertical shift module, a processing module, and an image capturing module. A mask, which is carried and held by the bearing platform, includes a dust-proof film, each region of which is measured by the laser ranging module for generating a distance measuring signal; each distance measuring signal is utilized to control the movement of the vertical shift module, such that image capturing module can take an inspection image of that region. Based on the distance measuring signals and inspection images, height information of the dust-proof film and inspection information can be acquired. Also provided herein is a method applicable to said mask inspection device.

MASK INSPECTION DEVICE AND METHOD THEREOF

A mask inspection device and method thereof are provided. In the mask inspection device, an image capturing module is controlled to capture an image of the object to be inspected, and when the captured image does not match a predetermined correction image, a horizontal position of the bearing module which holds the object is adjusted; when the captured image matches the predetermined correction image, a light emission element projects a spot light towards the object, and the image capturing module captures an image in a mask region of the object, so as to produce a mask inspection image. The mask inspection information can be obtained from a two-dimensional image of the mask inspection image, and an abnormal image of the mask inspection image is inspected to generate mask abnormal information. 1. A mask inspection device , comprising:a device main body, a surface of which is movably disposed with a rotational shift unit, and a surface of the rotational shift unit is disposed with a light emission element;a bearing module suspended on the surface of the rotational shift unit, wherein an inspected object is movably carried on other surface of the bearing module opposing to the surface of the bearing module facing the rotational shift unit, and a main body of the bearing module has an opening;a first image capturing module suspended on the surface of the device main body; anda control module electrically connected with the rotational shift unit and the first image capturing module, wherein the control module receives a correcting inspection signal and accordingly controls the first image capturing module to capture the image of the inspected object so as to generate an inspection image; wherein after receiving the inspection image, when the control module determines that the inspection image does not match a predetermined correction image, the control module controls the rotational shift unit to rotate horizontally so as to adjust the horizontal position and a ...

SUBSTRATE INSPECTION DEVICE AND METHOD THEREOF

A substrate inspection device is provided, which includes a main body, a bearing module, an illuminating and camera module and a control module. A mask is held by the bearing module, which has an opening. The illuminating and image capturing module is disposed on the lifting unit. After receiving the first detecting signal, the control module accordingly drives the lifting unit to shift towards the first direction, such that the illuminating and image capturing module moves closer to the substrate. The control module then controls the shifting unit to drive the light-emitting component to project a first spot-light on the substrate through the opening, and controls the shifting unit to move by a step manner so as to carry the bearing module. The control module also controls the illuminating and image capturing module to capture images the first regions of the substrate and to generate the first images. 1. A substrate inspection device , comprising:a device main body, on a surface of which is movably disposed with a shifting unit and above the surface of which is suspended a lifting unit, wherein a light emission element is disposed on a surface of the shifting unit;a bearing module, which is suspended above the surface of the shifting unit and has an opening, wherein a plurality of clamping units are movably disposed on a surface on an opposite side from a surface opposing to the shifting unit and can movably clamp a substrate;an illuminating and image capturing module, which is disposed on the lifting unit; anda control module, which is electrically connected to the shifting unit, the lifting unit, and the illuminating and image capturing module, wherein the control module receives a first inspection signal and accordingly drives the lifting unit to move in a first direction, such that the illuminating and image capturing module moves closer to the substrate, and the control module controls the shifting unit to drive the light emission element to project a first ...

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width. 1. A semiconductor structure , comprising: a first fin structure;', 'first fin spacers covering sidewalls of the first fin structure and having a first height; and', 'a first epitaxy structure disposed in the first fin structure, and a portion of the first epitaxy structure being above the first fin spacers and having a first width; and, 'a device region, comprising a second fin structure, wherein a height of the second fin structure is greater than a height of the first fin structure;', 'second fin spacers covering sidewalls of the second fin structure and having a second height, and the second height of the second fin spacers being greater than the first height of the first fin spacers; and', 'a second epitaxy structure disposed in the second fin structure, a portion of the second epitaxy structure being above the second fin spacers and having a second width, and the second width being less than the first width., 'a test region, comprising2. The semiconductor structure of claim 1 , wherein a top of the first epitaxy structure and a top of the second epitaxy structure are on the same level.3. The semiconductor structure of claim 1 , further comprising cap layers respectively covering the first epitaxy structure and the second epitaxy ...

BANDGAP REFERENCE CIRCUIT, CONTROL CIRCUIT, AND ASSOCIATED CONTROL METHOD

A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal. 1. A bandgap reference circuit , comprising:a current generating circuit, triggered by a trigger signal generated when the bandgap reference circuit starts up, the current generating circuit being arranged to generate a reference current according to the trigger signal;a switch circuit, controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator, the switch circuit being arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current; anda control circuit, coupled to the current generating circuit and the switch circuit, wherein the control circuit is arranged to generate the switch control signal according to the trigger signal.2. The bandgap reference circuit of claim 1 , wherein a trigger time point of the switch control signal is later than a trigger time point of the trigger signal.3. The bandgap reference circuit of claim 1 , wherein the control circuit is arranged to generate the switch control signal by ...

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH REDUCED NODULE DEFECTS

A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion. 1. A method for eliminating nodule defects which are formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure , the method comprisingapplying to the semiconductor structure a plasma which has a higher selectivity to etch the nodule defects relative to the semiconductor region, to thereby eliminate the nodule defects.2. The method of claim 1 , wherein the plasma is generated from a gas source including hydrogen.3. The method of claim 2 , wherein a flow rate of the hydrogen is controlled in a range from 10 sccm to 2000 sccm.4. The method of claim 2 , wherein the gas source further includes a carrier gas selected from helium claim 2 , argon claim 2 , and a combination thereof.5. The method of claim 4 , wherein a flow rate of the carrier gas is controlled in a range from 50 sccm to 6000 sccm.6. The method of claim 1 , wherein the plasma is operated under a temperature ranging from 90° C. to 600° C.7. The method of claim 1 , wherein the plasma is operated under a pressure ranging from 0.05 torr to 6 torr.8. The method of claim 1 , wherein the plasma is generated by a plasma generation source selected from a transformer-coupled plasma generator claim 1 , an inductively coupled plasma system claim 1 , a magnetically enhanced reactive ion etching system claim 1 , an electron cyclotron resonance system claim 1 , or a remote plasma generator.9. A method for manufacturing a semiconductor structure claim 1 , comprising:forming two first recesses in two first regions ...

ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer. 1. A method of forming an integrated circuit device , comprising:forming a conductive line over a substrate and in contact with a liner; an interfacial layer contacting the conductive line, wherein the interfacial layer and the liner collectively completely surround the conductive line;', 'a middle layer contacting the interfacial layer; and', 'an upper layer contacting the middle layer; and, 'forming a dielectric barrier layer on the conductive line, the dielectric barrier layer includingforming an inter-level dielectric layer along sidewalls of the upper layer.2. The method of claim 1 , wherein the conductive line and the liner are formed over a lower dielectric layer claim 1 , the middle layer contacting the lower dielectric layer.3. The method of claim 1 , wherein the interfacial layer has a bottommost surface that is over a topmost surface of the liner.4. The method of claim 1 , wherein the middle layer has a bottommost surface that is over a topmost surface of the liner.5. The method of claim 1 , wherein the middle layer contacts the liner.6. The method of claim 1 , wherein a horizontal plane that is parallel to an upper surface of the conductive line extends through sidewalls of the conductive line claim 1 , the interfacial layer claim 1 , and the middle layer.7. The method of claim 1 , wherein the middle layer contacts a bottom surface of the ...

DETERMINING AND DISPLAYING SIMILAR EMPLOYEES BASED ON EMPLOYMENT ROLE

A system and method for determining similar members in an organization is disclosed. In some example embodiments, the social networking system receives a request for a particular job listing from a client system associated with a first member of a social networking system. The social networking system determines a first employment role for a job associated with the particular job listing. The social networking system identifies a source organization for the particular job listing. The social networking system identifies one or more similar members, wherein each identified similar member is associated with the source organization and has an employment role similar to the first employment role. The social networking system communicates the particular job listing and the identified one or more similar members to the client system for display. 1. A method comprising:receiving a request for a particular job listing from a client system associated with a first member of a social networking system;determining a first employment role for a job associated with the particular job listing;identifying a source organization for the particular job listing;identifying one or more similar members, wherein each identified similar member is associated with the source organization and has an employment role similar to the first employment role; andcommunicating the particular job listing and the identified one or more similar members to the client system for display.2. The method of claim 1 , wherein determining the first employment role for the job associated with the particular job listing further comprises:analyzing the particular job listing to determine a list of required skills associated with the job.3. The method of claim 2 , wherein analyzing the particular job listing to determine the list of required skills for the job further comprises:parsing a text of the particular job listing to identify one or more keywords; andcomparing the one or more keywords to a reference list of ...

CIRCUIT AND METHOD FOR BANDWIDTH MEASUREMENT

A circuit for measuring a bandwidth of an amplifier includes first and second capacitors, first through third switches, and a pulse generator. First terminals of the capacitors are coupled to an amplifier input, and a second terminal of the second capacitor is coupled to an amplifier output. The first switch has a control terminal and terminals coupled to a first input node and a second terminal of the first capacitor. The second switch has a control terminal and terminals coupled to the amplifier input and output. The third switch has a control terminal, a first terminal, and a second terminal coupled to the second terminal of the first capacitor. The pulse generator has a first output coupled to the control terminal of the third switch, and is configured to vary a pulse width of a pulse signal supplied from the first output to the control terminal of the third switch. 1. A circuit for measuring a bandwidth of an amplifier , the circuit comprising:a first capacitor having a first terminal coupled to a first input of the amplifier, and a second terminal;a second capacitor having a first terminal coupled to the first input of the amplifier, and a second terminal coupled to a first output of the amplifier;a first switch having a first terminal coupled to a first input node, a second terminal coupled to the second terminal of the first capacitor, and a control terminal;a second switch having a first terminal coupled to the first input of the amplifier, a second terminal coupled to the first output of the amplifier, and a control terminal;a third switch having a first terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal; anda pulse generator having a first output coupled to the control terminal of the third switch, the pulse generator configured to vary a pulse width of a first pulse signal supplied from the first output to the control terminal of the third switch.2. The circuit of claim 1 , further comprising:a third ...

Electro-Migration Barrier for Cu Interconnect

Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.

DEPOSITION INJECTION MASKING

In deposition devices, a precursor is directed at a substrate within a deposition chamber, and a block plate comprising a set of block plate apertures adjusts the direction and volume of the outflowing precursor. However, arrangements of block plate apertures that are suitable for some deposition scenarios (such as one type of precursor) are unsuitable for other deposition scenarios, resulting in precursor deposition that is undesirably thick, thin, or inconsistent. A set of block plate masks positioned over respective zones of the block plate are adjustable to align a set of masking apertures with respect to the block plate apertures, such as by operating a block plate motor to rotate a ring-shaped block plate mask over a cylindrical zone of the block plate. This configuration enables adjustable exposure of the block plate apertures to control the adjusted outflow of precursor through the block plate. 1. A deposition device , comprising:a deposition chamber;a substrate stage positioning a substrate within the deposition chamber;a precursor source controllably injecting a precursor into the deposition chamber;a block plate comprising block plate apertures directing injection of the precursor at the substrate; andat least one block mask comprising masking apertures and positioned to cover a zone of the block plate with an alignment of the masking apertures and the block plate apertures to alter directing the injection of the precursor at the substrate.2. The deposition device of :the deposition device further comprising a deposition chamber lid;the precursor source controllably injecting the precursor downward through the block plate positioned in the deposition chamber lid; andthe at least one block mask positioned above the block plate in the deposition chamber lid.3. The deposition device of :the block plate comprising a first disc; andat least one block mask comprising a second disc positioned to cover a circular zone of the block plate and rotatable to select an ...

ANALOG CELLS UTILIZING COMPLEMENTARY MOSFET PAIRS

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells. 1. A system for developing an electronic architectural design layout for circuitry of an electronic device , the system comprising:a memory that stores a plurality of categories of circuits, each category of circuits from among the plurality of categories of circuits being associated with a corresponding common configuration from among a plurality of common configurations; and assign a circuit from among a plurality of circuits of the circuitry to a category of circuits from among the plurality of categories of circuits that is associated with a similar corresponding common configuration as a configuration of the circuit,', 'designate a placement site from among the electronic architectural design layout as being assigned to the category of circuits, and', 'place a standard cell from among a plurality of standard cells that is associated with the category of circuits into the placement site., 'a processor configured to execute a placing and routing application, the placing and routing application, when executed by the processor, configuring the processor to2. The system of claim 1 , wherein the placing and routing application claim 1 , when executed by the processor claim 1 ...

On-chip oscilloscope

A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.

Light source module, backlight module and display device

A light source module includes a back plate and light-emitting units. The back plate includes a bottom plate and a sidewall. An included angle is formed between an outer side surface of the sidewall and a horizontal plane where the bottom plate is located, and the included angle is an acute angle. An optical distance is defined between a top end of the sidewall and the horizontal plane. The light-emitting units are arranged in the back plate. The light-emitting units which are closest to the sidewall are defined as target light-emitting units, and each of the target light-emitting units has a radiation angle, and each of the target light-emitting units is separated from the sidewall by a distance. The first horizontal distance is determined by a tangent function of a complementary angle of the radiation angle, the second horizontal distance is determined by a tangent function of the included angle.

ENCAPSULATED OPTO-ELECTRONIC SYSTEM FOR CO-DIRECTIONAL IMAGING IN MULTIPLE FIELDS OF VIEW

A tethered opto-electronic imaging system encapsulated in an optically-transmissible housing capsule/shell and configured to image object space in multiple fields-of-view (FOVs) to form a visually-perceivable representation of the object space in which sub-images representing different FOVs remain co-directional regardless of mutual repositioning of the object and the imaging system. The capsule/shell of the system is a functionally-required portion of the train of optical components that aggregately define and form a lens of the optical imaging system. The tether is devoid of any functional optical channel or element. When different FOVs are supported by the same optical detector, co-directionality of formed sub-images images is achieved due via judicious spatial re-distribution of irradiance of an acquired sub-image to form a transformed sub-image while maintaining aspect ratios of dimensions of corresponding pixels of the acquired and transformed sub-images. Methodology of transformation of images utilizing radial redistribution of image irradiance. 1. An optoelectronic system comprising: an optical detector system,', 'a first lens facing a first portion of the housing shell that has a first non-zero optical power, a combination of the first lens and the first portion of the housing shell defining a front optical imaging system, wherein the front optical imaging system has a first optical axis and a front field of view (FFOV) and is configured to form a first image at the optical detector system;', 'a second lens facing a second portion of the housing shell that has a second non-zero optical power, a combination of the second lens and the second portion of the housing shell defining a lateral optical imaging system, wherein the lateral optical imaging system has a second optical axis and a lateral field of view (LFOV) and is configured to form a second image at the optical detector system., 'a housing shell having a shell axis and first and second optically- ...

CAP STRUCTURE

The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure. 1. A structure , comprising:a gate structure composed of conductive gate material;sidewall spacers on the gate structure, extending above the conductive gate material; anda capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.2. The structure of claim 1 , wherein the capping material is T-shaped and is composed of a bilayer of material.3. The structure of claim 2 , wherein the bilayer of material includes a top material that is resistant to etch chemistries and which overhangs over the sidewall spacers.4. The structure of claim 3 , wherein the top material is SiOC.5. The structure of claim 3 , wherein the top material overhangs the sidewall spacers and an etch stop material on the sidewall spacers.6. The structure of claim 3 , wherein the top layer is SiOC and a bottom layer which directly contacts the conductive gate material and is located between the sidewall spacers is a nitride material.7. The structure of claim 1 , further comprising contacts adjacent to the gate structure claim 1 , the contacts being separated from the conductive gate material of the gate structure by at least the sidewall spacers and the capping material which overhangs the sidewall spacers.8. The structure of claim 1 , wherein the capping material is planar with interlevel dielectric material.9. A structure claim 1 , comprising:a gate structure composed of conductive gate material;sidewall spacers on the gate structure;an etch stop layer on the sidewall spacers; anda T-shaped bilayer cap on the conductive gate material and ...

CIRCUIT AND METHOD FOR MEASURING THE GAIN OF AN OPERATIONAL AMPLIFIER

A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier. 1. A circuit for measuring the gain of an operational amplifier , the circuit comprising:a first operational amplifier having an original gain and including a first input terminal and a second input terminal;a first resistive device coupled between the first input terminal and the second input terminal of the first operational amplifier; anda second resistive device coupled to the second input terminal of the first operational amplifier, the first resistive device and the second resistive device being configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.321. The circuit of claim 2 , wherein the resistance R is N times the resistance R claim 2 , N being a positive integer.4. The circuit of further comprising a second operational amplifier including a first input terminal and an output claim 1 , the first input terminal of the second operational amplifier being coupled to an output of the first operational amplifier claim 1 , wherein the second resistive device is coupled between the second input terminal of the first operational amplifier and the output of the second operational amplifier.5. The circuit of claim 4 , wherein the output of the second operational amplifier is coupled to a voltage division ...

BANDGAP REFERENCE CIRCUIT, CONTROL CIRCUIT, AND ASSOCIATED CONTROL METHOD

A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit. 1. A bandgap reference circuit , comprising:a current generating circuit, arranged to be triggered by a trigger signal to mirror a base current to generate a first current and a second current, the trigger signal being generated when the bandgap reference circuit starts up, the current generating circuit being arranged to output the first current when triggered by the triggered signal;a switch circuit, controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator, the switch circuit being arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage to the regulator; anda control circuit, coupled to the current generating circuit and the switch circuit, the control circuit being arranged to, when the first current outputted from the current generating circuit reduces to a predetermined level, ...

Light guide plate with multi-directional structures

A light guide plate with multi-directional structures includes a main body, a plurality of first microstructures and a plurality of second microstructures. The main body includes a light-incident surface, a light-emitting surface and a reflecting surface. The light-incident surface connects the light-emitting surface and the reflecting surface. The first, microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a first extending direction The second microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a second extending direction. The second microstructures and the first microstructures are disposed on the same plane and intersect with each other. Each of the second microstructures is a single stripe pattern, and has a width which becomes gradually smaller from one end of the second microstructure near the light-incident surface to the other end of the second microstructure away from the light-incident surface.

INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL

A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal. 1. A device comprising:an interlayer dielectric (ILD) over a silicon (Si) fin;first and second cavities in the ILD, each over and perpendicular to the Si fin;a high-K dielectric layer on side and bottom surfaces of the first and second cavities;a p-type work function (pWF) metal layer over the high-K dielectric layer in the first and second cavities;an n-type work function (nWF) metal layer over the pWF metal layer and over edges of the pWF metal layer in the first cavity and over the high-K dielectric layer in the second cavity;a barrier metal layer over the nWF metal layer and over edges of the nWF layer,wherein the first and second cavities comprise a low-resistive metal filling with a bump at a center of each cavity.2. The device according to claim 1 , wherein the high-K dielectric layer has a thickness of 5 angstrom (Å) to 25 Å.3. The device according to claim 1 , wherein the low-resistive metal bump extends to a height of 14 nm to 40 nm above the Si fin.4. The device according to claim 1 , wherein the pWF metal layer has a thickness of 5 Å to 50 Å.5. The device according to claim 1 , wherein the barrier metal layer has a ...

METHOD, APPARATUS AND SYSTEM FOR PROVIDING NITRIDE CAP LAYER IN REPLACEMENT METAL GATE STRUCTURE

We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the gate structure cavity above the at least one metal layer. We also disclose at least one method and at least one system by which the semiconductor device may be formed. The UV cured HDP nitride cap layer may be substantially free of voids or seams, and as a result, the semiconductor device may have a reduced Vt shift relative to comparable semiconductor devices known in the art. 1. A method , comprising:providing a semiconductor device comprising at least one gate structure disposed above a semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer;depositing a high density plasma (HDP) nitride cap layer in the gate structure cavity above the metal layer; andperforming an ultraviolet (UV) cure of the nitride cap layer.2. The method of claim 1 , wherein depositing the HDP nitride cap layer further comprises depositing the HDP nitride cap layer above and outside the gate structure cavity.3. The method of claim 2 , further comprising chemical mechanical polishing (CMP) the semiconductor device claim 2 , whereby a top of the HDP nitride cap layer is at substantially the same height as a top of the gate structure.4. The method of claim 1 , wherein the pitch between adjacent gate structures is 10 nm or 7 nm.51. The method of gate claim 1 , further comprising forming the gate structure cavity; depositing at least one metal layer in and above the gate structure cavity; chemical mechanical polishing (CMP) the semiconductor device claim 1 , whereby a top of the at least one metal layer is at substantially the same height as a top of the gate structure; and recessing the at ...

CIRCUIT AND METHOD FOR BANDWIDTH MEASUREMENT

A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier. 1. A circuit for measuring a bandwidth of an amplifier , the circuit comprising:a switch-capacitor circuit coupled to an output and an input of the amplifier, the switch-capacitor circuit switchable between a sampling mode and an amplification mode; and switch the switch-capacitor circuit between the sampling mode and the amplification mode;', 'control the amplification mode to have various durations, and', 'determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier., 'a controller coupled to the switch-capacitor circuit and the output of the amplifier, the controller configured to'}2. The circuit of claim 1 , wherein the controller is configured to determine the bandwidth based on differences among the various durations of the amplification mode claim 1 , and based on differences among the corresponding voltages at the output of the amplifier.4. The circuit of claim 1 , wherein the controller comprises a pulse generator configured to generate a pulse signal having various pulse widths corresponding to the various durations of the amplification mode.5. The circuit of claim 1 , wherein the controller further comprisesa first circuit configured to measure capacitance ...

METHOD OF DENSITY-CONTROLLED FLOORPLAN DESIGN FOR INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS

A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule. 1. A method of density-controlled floorplan design for integrated circuits having a plurality of blocks , comprising:positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block; andchanging at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.2. The method of wherein the portion of the pattern density insensitive block is repositioned closer to the pattern density sensitive block.3. The method of wherein pattern density of the portion of the pattern density insensitive block is changed.4. The method of wherein the portion of the pattern density insensitive block is repositioned closer to the pattern density sensitive block and pattern density of the portion of the pattern density insensitive block is changed.5. The method of wherein the at least one pattern density rule specifies one of a minimum claim 1 , a maximum or predetermined pattern density between the pattern density sensitive block and the pattern density insensitive block.6. The method of wherein the at least one pattern density rule specifies a maximum pattern density change per unit distance.7. The method of wherein the at least one pattern density rule specifies a maximum pattern density change per unit distance.8. A system having a processor configured to execute instructions to perform a method of density-controlled floorplan design for integrated circuits having a plurality of blocks claim 6 , comprising:positioning decoupling capacitor (DCAP) cells at least ...

CHAMFERED REPLACEMENT GATE STRUCTURES

The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials. 1. A structure , comprising:a recessed gate dielectric material in a trench structure;a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material;a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials;a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure;a capping material over the gate metal and the plurality of additional workfunction materials; anda metal material between the plurality of additional workfunction materials and the plurality of recessed workfunction materials,wherein the metal material includes a stepped feature transitioning within the plurality of recessed workfunction materials.2. (canceled)3. The structure of claim 1 , wherein a top layer of the plurality of additional workfunction materials is TiN.4. The structure ...

SOURCE AND DRAIN EPITAXY RE-SHAPING

The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions. 1. A method of laterally etching an epitaxial layer , the method comprising:forming a plurality of fins on a substrate, wherein each of the plurality of fins has a first width;forming source/drain regions comprising a first epitaxial layer and a second epitaxial layer on the plurality of fins, wherein each source/drain region has a second width;selectively etching the second epitaxial layer of each source/drain region to decrease the second width of the source/drain regions; andgrowing an epitaxial capping layer over the source/drain regions.2. The method of claim 1 , wherein a height of each of the source/drain regions is between 40 and 80 nm.3. The method of claim 1 , wherein the selectively etching the second epitaxial layer comprises an in-situ etching with hydrochloric acid (HCl) claim 1 , germane (GeH) claim 1 , and chlorine (Cl) claim 1 , and wherein a flow rate for HCl is 40 to 1000 sccm claim 1 , a flow rate for GeHis 0 to 1000 sccm claim 1 , and a flow rate for Clis 0 to 100 sccm.4. The method of claim 3 , wherein the in-situ etching is performed at a process temperature ...

LIGHT GUIDE PLATE WITH MULTI-DIRECTIONAL STRUCTURES

A light guide plate with multi-directional structures includes a main body, a plurality of first microstructures and a plurality of second microstructures. The main body includes a light-incident surface, a light-emitting surface and a reflecting surface. The light-incident surface connects the light-emitting surface and the reflecting surface. The first microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a first extending direction. The second microstructures are disposed on the light-emitting surface or the reflecting surface and arranged along a second extending direction. The second microstructures and the first microstructures are disposed on the same plane and intersect with each other. Each of the second microstructures is a single stripe pattern, and has a width which becomes gradually smaller from one end of the second microstructure near the light-incident surface to the other end of the second microstructure away from the light-incident surface. 1. A light guide plate , comprising:a main body comprising a light-incident surface and an optical surface connected to the light-incident surface;a plurality of striped structures disposed on the optical surface; anda plurality of light-adjusting structures disposed between the striped structures, wherein each of the light-adjusting structures comprises a first light active surface and a second light active surface connected to the first light active surface;wherein the first light active surface faces towards the light-incident surface, and the second light active surface faces towards a side of the main body opposite to the light-incident surface, and the first light active surface and the second light active surface are inclined relative to opposite sides and are formed in non-symmetrical shape;wherein a first angle is formed between the first light active surface and the optical surface, and a second angle is formed between the second light active surface ...

SLIM LINEAR LED LIGHTING DEVICE

A slim linear LED lighting device is provided, including: a printed circuit board on which a connecting circuit is provided, at least one power input component, and a plurality of LED Bars. The LED Bar is formed by a plurality of the same kind of LED chips, and has a slim strip-shaped condensing lens structure integrally formed in the LED Bar packaging process by molding process to control the beam angle of the LED Bar and therefore the light distribution of the slim linear LED lighting device. The LED Bar's condensing lens has a small cross-sectional dimension; therefore the effective utilization factor of the light is improved as the slim linear LED lighting device is applied to a linear automotive lamp designed with a thin light blade structure. 1. A slim linear LED lighting device , comprising:a printed circuit board of which an upper layer is provided with a connecting circuit;at least one power input component; anda plurality of LED Bars;wherein the said power input component and the said LED Bars are mounted on the said printed circuit board, the said LED Bars are linearly arranged on the said printed circuit board, and electrically connected to the said power input component through the said connecting circuit provided on the said printed circuit board;wherein the said LED Bar consists a plurality of the same kind of LED chips arranged linearly and apart equidistantly on an upper layer of a substrate in a spacing of 0.2 mm to 3.0 mm; wherein the said substrate has electrically conductive layers on the upper layer and the bottom layer to enable the said LED Bar to be mounted on the printed circuit board by SMT process;wherein the said LED Bar is packaged by molding process and has a slim strip-shaped condensing lens structure, so that the beam angle of the said LED Bar perpendicular to the longitudinal direction that the plurality of LED chips are lined up is condensed to be between 10 and 80 degrees, and the slim strip-shaped condensing lens structure is ...

METHOD OF FORMING SEMICONDUCTOR MATERIAL IN TRENCHES HAVING DIFFERENT WIDTHS, AND RELATED STRUCTURES

The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench. 1. A method comprising:forming a first fill material in a first trench and a second trench, the first and second trench positioned in a dielectric material on a substrate, and a width of the first trench being greater than a width of the second trench;removing a first portion of the first fill material from the first trench and the second trench;forming a second fill material above a remaining portion of the first fill material in the first trench and the second trench such that the second fill material completely fills at least the second trench;removing a first portion of the second fill material in the first trench to expose an upper surface of the remaining portion of the first fill material in the first trench; and a lower region having an uppermost extent that is substantially co-planar with an upper surface of the remaining portion of the first fill material in the second trench, and', 'two upper regions positioned on the lower region., 'removing a portion of the remaining portion of the first fill material in the first trench such that the remaining portion of the first ...

Integrated circuit

Locking device for fastening cover with chest shell

A lock tool (21) actuates each retaining portion (26) to slide towards a base end (11). A lock retainer (41) is retained at a time when the lock tool is at a locking position. The lock tool actuates the retaining portions to slide towards other end of base to enable lock retainer to remain in unlocking state. Linking portions (23) fastened with the lock tool ends displace according to locking and unlocking positions of the lock tool. The retaining portions are movably located at the ends of lock tool set (20). The lock retainer is swiveled to join with lock retainer seat (31) to actuate a slide block (36) to move to a position.

LINKAGE FOR TRUNK OR LUGGAGE

Cover latching mechanism

A cover latching mechanism is provided including a base member, a cover member, and a button assembly. The base member includes an elastic hook. The cover member is detachable assembled to the base member. The button assembly is fixed to the cover member and movable relative to the cover member to latch to or release from the elastic hook. The button assembly includes a button member having a positioning arm and a sleeve portion and further defining a elastic hooking hole. The elastic hook engages into the elastic hooking hole so that the elastic hook latches the button assembly with the base member. The positioning arm secures the button assembly to the cover member. The restoring member can be deformed when the button assembly pressed, so that the elastic hook releases out of the elastic hooking hole.

Light guiding mechanism for portable electronic device

A light guiding mechanism for portable electronic device includes a cover, a light guiding module and four light sources. The cover includes a light transmitting region. The light guiding module includes a light guide plate having a first diagonal line and a second diagonal line. The light guide plate defines a first through hole. The light guide plate includes a light reflecting region around the first through hole. The light reflecting region includes a plurality of protrusions symmetrically positioned relative to the first diagonal line and the second diagonal line. Adjacent protrusions have a space therebetween. The size of the space uniformly increases with increasing distance from the first through hole. Light emitted from the light sources is repeatedly reflected by the protrusions and then passes the light transmitting region of the cover.

Semiconductor structure and fabricating method thereof

A semiconductor structure and a method of fabricating the semiconductor structure are disclosed herein. The semiconductor structure includes a substrate, a strain-inducing layer and an epitaxy structure. The strain-inducing layer is disposed on the substrate, and the epitaxy structure is embedded in the strain-inducing layer and not in contact with the substrate.

Accessory strap securing mechanism

An accessory strap securing mechanism positioned on a portable electronic device to assemble an accessory strap thereon, the accessory strap securing mechanism includes an assembling portion and a securing member. The assembling portion is formed in the portable electronic device. The securing member includes a holding portion. The holding portion is received in the assembling portion. The holding portion includes a hook and a projection. The securing member is rotatable to allow the accessory strap to be coiled around the holding portion and a distal end of the accessory strap attached to the projection.

Key button structure for electronic device

A key button structure ( 10 ) for using in a portable electronic device ( 100 ) is provided. The key button structure ( 10 ) include a housing ( 14 ) having a joining portion ( 1428 ) formed on the outer wall ( 1422 ) of the housing ( 14 ) and a key body ( 124 ) have a mating portion ( 1245 ) formed thereon corresponding with the joining portion ( 1428 ).

Method for designing phase-lock loop circuits

A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

Variable optical attenuator

A variable optical attenuator includes a base ( 12 ), an attenuating means ( 11 ), a first collimator ( 13 ) retaining an input fiber ( 18 ), a second collimator ( 14 ) retaining an output fiber ( 20 ) and an optical baffle ( 116 ). The attenuating means has four anamorphic prisms ( 111,112,113,114 ). The optical baffle is driven to move into light path of the first collimator and is expanded by two anamorphic prisms to block a part of the light beam. Thereafter, the retaining part of the light path passes through other two anamorphic prisms and shrinks to form a parallel light beam received by the second collimator.

Phase-locked loop circuit with a mixed mode loop filter

A phase-locked loop circuit includes a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a frequency or phase difference therebetween. A digital charge pump coupled to the phase and frequency detector generates a charge control signal in response to the detected signal. A mixed mode loop filter coupled to the digital charge pump filters the charge control signal and generates an oscillation control signal. A voltage controlled oscillator is coupled to the mixed mode loop filter for generating the output signal of the phase-locked loop circuit by adjusting its oscillation frequency in response to the oscillation control signal. The mixed mode loop filter has both digital and analog characteristics in carrying out filtering the charge control signal, thereby reducing a layout area for the same to be implemented on a semiconductor substrate.

Circuitry and method for reducing environmental noise

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Side key assembly for portable electronic device

A side key assembly comprises a base plate, a first push button and a second push button. The base plate has an opening defined therein and two opposite sidewalls defined in the opening. The first push button is rotatably assembled to the base in the opening, and the first push button is situated adjacent to one of the sidewalls. The second push button is rotatably assembled to the first push button in the opening and the second push button is situated adjacent to another sidewall.

Portable electronic device

A portable electronic device ( 20 ) comprises a housing ( 22 ), a battery ( 26 ), a battery cover ( 28 ) and a trigger mechanism ( 24 ). The housing ( 22 ) have a battery chamber ( 222 ) defined therein. The battery cover ( 28 ) have a mating portion ( 2822 ) formed thereon. The battery ( 268 ) assembled in the battery chamber ( 222 ) with the battery cover ( 28 ) covering thereon. and The trigger mechanism ( 24 ) comprise an expanding portion ( 242 ), a securing portion ( 244 ), and a resisting portion ( 246 ), the securing portion ( 244 ) have two ends respectively connecting the expanding portion ( 242 ) and the resisting portion ( 246 ), the mating portion ( 2822 ) is configured for securely engaging with the securing portion ( 244 ) so as to restrain the expanding portion from expanding. The expanding portion ( 242 ) is secured within the battery chamber ( 222 ). The resisting portion ( 246 ) is configured for resisting against the battery ( 26 ). When the mating portion ( 2822 ) disengages from the securing portion ( 244 ), the expanding portion ( 242 ) expands and the resisting portion ( 246 ) ejects the battery ( 26 ) from the battery chamber ( 222 ).

Cover mechanism and electronic device using same

An electronic device ( 100 ) using a cover mechanism ( 30 ) to cover its hole ( 14 ) of its housing ( 10 ) is described. The cover mechanism includes a cover ( 20 ) and a locking structure ( 11 ). The cover has a latching portion ( 23 ) and a locking portion ( 21 ), both of which include a resilient part. The locking structure is configured for associating with the locking portion and the latching portion. Thus, the cover is latched to the housing to cover the hole by deforming the resilient parts. After the cover is unlatched from the housing by a sudden pulling force, the locking portion still physically connects to the locking structure. After the cover is unlatched from the housing by a normal pulling force, the locking portion has no physically relationship with the locking structure.

Slide mechanism for slide-type portable electronic device

A slide mechanism ( 100 ) used in portable electronic device ( 300 ) is described including a main plate ( 10 ), a slide plate ( 20 ), two sliders ( 40 ), and two guiders ( 30 ). The slide plate is installed on the main plate and slidable relative to the main plate. The sliders are securely attached to the slide plate, and the guiders are securely attached to the main plate deformably guiding the sliders to move along it. When the slide plate slides along the main plate, the sliders and the guiders compress with each other, thereby generating deformations therebetween and driving the sliding of the slide plate along the main plate.

Method for manufacturing semiconductor structure with reduced nodule defects

A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.

Sliding key within a portable electronic device

A key assembly comprises a base plate, two elastic elements and a key body. The elastic elements are both mounted to the base plate, and the elastic elements are spaced from and opposite to each other. The key body is slidably mounted to the base plate between the two elastic elements, the key body includes a first key section and a second key section connected with the first key section. The first key section has a first arcuate contacting portion formed thereon, the second key section has a second arcuate contacting portion formed thereon. One of the elastic elements is mounted to the first key section, another one of the elastic elements is mounted to the second key section. When the first key section slides toward and compresses said one of the elastic elements, the second key section slide away from and stretches said another one of the elastic elements.

Methods and apparatus for time to current conversion

A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.

Connector cover structure and the electronic device using the same

Light source module and method for manufacturing the same, and backlight module and display device using the same

A light source module and a method for manufacturing the same, and a backlight module and a display device using the same are provided. The method includes the following steps. A reference light source module is provided. The reference light source module comprises a substrate and plural light-emitting units arranged on the substrate. Then, plural optical trends between every two adjacent light-emitting units are obtained. Then, plural optical ratios between every two adjacent light-emitting units are calculated, in which each of the optical ratios is a ratio of each of the optical trends to a total reference optical trend of the reference light source module. Then, plural target distances are calculated according to the optical ratios and plural initial distances between every two adjacent light-emitting units are adjusted according to the target distances, thereby forming a target light source module.

Differential amplifier without common mode feedback

A differential amplifier without common feedback is disclosed. The amplifier has a low gain fully differential amplifier and a high gain fully differential amplifier connected in parallel with the low gain fully differential amplifier. When first and second inputs feed into the low and high gain fully differential amplifiers, the low gain fully differential amplifier is used to bias the high gain fully differential amplifier so that a first and second voltage output generated by the high gain fully differential amplifier is stable during a common mode operation without being impacted by fluctuation of the inputs.

Housing for mobile devices

A housing includes a transparent substrate, a first decorative layer made of a partially transparent ink coating having a shiny powdery component mixed therein, and a second decorative layer made of a colored ink coating.

Battery cover latching assembly

A battery cover latching assembly, detachably securing a battery cover to a housing, includes a button, battery cover, elastic member arranged between the button and the housing, and a resisting member resisting the battery cover away from the housing. The button includes a locking portion. The battery cover includes a corresponding locking member. The locking portion is slidably received in the housing to clamp or release the locking member.

Circuitry and method for reducing environmental noise

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Cover mechanism and electronic device using same

An electronic device using a cover mechanism to cover a hole is described. The cover mechanism includes a locking member slidably mounted on a base member and a cover member. The cover member can be locked to the base member by locking of the cover member to the locking member in a locked position, can rotate around the locking member in a released position, and can expose the hole and physically attach to the locking member in an opened position.

Key assembly for portable electronic device using the same

A key assembly comprises a connecting element, a first key and a second key. The first key includes a first body member and a first elastic member protruding from one end of the first body member, another end of the first body member connects with the connecting element. The second key includes a second body member and a second elastic member protruding from one end of the second body member, and another end of the second body member connects with the connecting element. The first elastic member provides a returning force for the first body member, and the second elastic member provides a returning force for the second body member.

Method for producing housing

Cover mechanism and electronic device using same

A portable electronic ( 200 ) device using a cover mechanism ( 100 ) to close off two or more interface holes ( 3512, 3522 and 353 ) is described. The portable electronic device includes a base portion ( 30 ). The cover mechanism includes a first cover member ( 50 ) and a second cover member ( 70 ). The first cover member has a first cover portion ( 51 ) to close off one or more interface holes. The second cover member has a second cover portion ( 71 ) to close off another one or more interface holes. The second cover member is latched to the base, and the first cover member is latched to the base and the second cover member.

Housing and method for making the same

A housing includes a substrate and a decorative layer formed on one surface of the substrate. The decorative layer includes two colored ink coatings, each of which is partially interlaced with the other and has a color depth decreasing from one end thereof towards the other colored ink coating to another end thereof and partially mixed with the other colored ink coating.

Method for manufacturing a housing

A method for manufacturing a housing ( 100 ) out of a transparent housing including an inner surface ( 10 ) and an outer surface ( 20 ), is described. Ink is printed on the inner surface ( 10 ) to form a ink area ( 50 ) defining a window area ( 40 ). The window area ( 40 ) and the ink area ( 50 ) are shielded and a painting process carried out on non-shielded portions of the inner surface ( 10 ). Finally, non-conductive vacuum metallization is carried out on the outer surface ( 20 ) to form the manufactured housing ( 100 ).