ВОССТАНОВЛЕНИЕ ДАННЫХ И СИНХРОНИЗАЦИИ (CDR) ПОВЫШЕННОГО УРОВНЯ В ПАССИВНЫХ ОПТИЧЕСКИХ СЕТЯХ (PON)

СПОСОБ И УСТРОЙСТВО ДЛЯ ГИБРИДНОЙ КОРРЕКЦИИ С РЕШАЮЩЕЙ ОБРАТНОЙ СВЯЗЬЮ

... 1. Способ гибридной коррекции с решающей обратной связью посредством определения коэффициентов фильтров в эквалайзере с решающей обратной связью, содержащем фильтр с прямой связью и фильтр с обратной связью, каждый их которых характеризуется множеством коэффициентов, заключающийся в том, что выбирают функцию стоимости для эквалайзера с решающей обратной связью, причем функция стоимости представляет собой среднеквадратическую ошибку (MSE) между выходным сигналом эквалайзера в предположении безошибочной обратной связи и целевым выходным сигналом эквалайзера плюс модифицированная мера энергии коэффициентов фильтра с обратной связью, и корректируют множество коэффициентов до тех пор, пока не будет удовлетворено условие сходимости, нацеленное на минимизацию функции стоимости. 2. Способ по п.1, отличающийся тем, что множество коэффициентов соответствует множеству отводов фильтра, а модифицированная мера энергии является функцией по меньшей мере одного из отводов фильтра. 3. Способ по п.1, отличающийся ...

Entzerrer, der in entscheidungsrückgekoppelter Form oder fraktionierter Form arbeiten kann

Verfahren zur Verbesserung der DFE-Leistungen in einem Trelliskodierten System

VERFAHREN UND EINRICHTUNG ZUR VERARBEITUNG EINES SIGNALS IN EINER TELEKOMMUNIKATIONSEINRICHTUNG

KOMBINIERTE KREUZPOLARISATIONSINTERFERENZKOMPENSATION UND INTERSYMBOLINTERFERENZENTZERRUNG FUER ERDGEBUNDENE DIGITALE FUNKSYSTEME.

Verfahren und System zur Interferenzunterdrückung für TDMA- und/oder FDMA-Übertragung

VERFAHREN UND VORRICHTUNG ZUM VERARBEITEN VON DATEN ZUR ÜBERTRAGUNG IN EINEM MEHRKANALIGEN KOMMUNIKATIONSSYSTEM UNTER VERWENDUNG EINER SELEKTIVEN KANALÜBERTRAGUNG

ADAPTIVE ENTZERRUNGSEINRICHTUNG MIT MEHREREN MODEN

Efficient tracking of decision-feedback equaliser coefficients

Preloading for equalisers

EQUALIZERS

Method of Interference Suppression in Mobile Communications.

An interference suppression device (1) comprises a joint detection decision feedback equaliser (3) comprising a first wanted filter (8) and a first interferer filter (9), a joint decision device (12), a second wanted filter (14, 15) and a second interferer filter (13, 16); wherein a received signal is input (7) to the first filters, wherein a filtered wanted signal and a filtered interferer signal are input to the joint decision device; wherein each output of the joint decision device is filtered in the respective second filters and subtracted (10, 11) from the respective input signals to optimise the output of the joint decision device; and wherein an estimated interferer signal is output (17) for further processing. An interference suppression system incorporating the device and a method of suppressing interference are also provided.

DATA TRANSMISSION SYSTEM

In a data transmission system data is sent, after suitable conversion, as a ternary analog type signal. Using two-wire twisted pairs and hybrids, echo cancellation and feedback equalization are needed. Synchronization between the two ends, e.g. of a 144 Kb/sec. subscriber's loop is maintained by a low amplitude pilot tone sent with the data, and detects at the same time as the data is detected. Detection and elimination of this pilot tone use coefficient generation circuitry similar to those used in the equalizer and echo canceller.

OFDM receiver with time domain channel estimation

Adaptive filters and equalisers

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

RECEIVER FOR OPTICAL SIGNALS WITH A VITERBIENTZERRER AND A SIMILAR ONE, ELECTRONIC ENTZERRER

VERFAHREN ZUR AUFBEREITUNG VON SIGNALEN FÜR DIE SIGNALÜBERTRAGUNG IM BASISBAND

PROCEDURE AND DEVICE FOR THE ENTZERREN AND DECREASING CROSS MODULATION

ENTZERRUNGSMETHODE SIGNALS PASSING IN A RECEIVER FOR A CHANNEL.

PROCEDURE AND DEVICE FOR PROCESSING FROM DATA TO THE TRANSMISSION IN A MULTI-CANAL COMMUNICATION SYSTEM USING A SELECTIVE CHANNEL TRANSMISSION

DYNAMIC REGISTER WITH THE ABILITY FOR THE EXAMINATION OF THE QUIESCENT CURRENT ADMISSION (IDDQ)

OFDM RECEIVER WITH ADAPTIVE ENTZERRER

PROCEDURE AND SYSTEM FOR THE INTERFERENCE SUPPRESSION FOR TDMA AND/OR FDMA TRANSMISSION

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ENTZERRER FOR SCANNING VALUE WAYS DECISION FEEDBACK WITHIN THE TRANSFORMATION RANGE

ADAPTIVE EQUALIZER

EQUALIZER/FORWARD ERROR CORRECTION AUTOMATIC MODE SELECTOR

SINGLE CLOCK RECEIVER

A BODY-BIASED SLICER DESIGN FOR PREDICTIVE DECISION FEEDBACK EQUALIZERS

... 73957/ S1421 A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC. 2062656vl Ln) mW +C ...

Digital video signal processing system including a rejection filter

Adaptive filters and equalisers

ADAPTIVE EQUALIZER

ADAPTIVE EQUALIZER

ARRANGEMENT FOR CORRECTING PULSE DISTORTION IN HOMOCHRONOUS DATA TRANSMISSION

DFE TO FFE EQUALIZATION COEFFICIENT CONVERSION PROCESS FOR DOCSIS 2.0

DECISION FEEDBACK EQUALIZER FOR DIGITAL TV AND METHOD THEREOF

... ²²The conventional decision feedback equalizer has a drawback that can't decide ²symbols correctly because a simple²slicer is used as a symbol detector. A decision feedback equalizer as a symbol ²detector uses a Trellis Coded Modulation (TCM)²decoder whose Trace Back depth is 1 (TBD=1), to thereby decide symbols ²correctly without decoding delay.² ...

SINGLE-CARRIER RECEIVER HAVING A CHANNEL EQUALIZER INTERACTING WITH A TRELLIS DECODER AND A CHANNEL EQUALIZATION METHOD THEREFOR

A channel equalizer for a single-carrier receiver interacting with a Trellis decoder and a channel equalization method therefor. The channel equalizer includes a first equalizer having a first feed forward (FF) unit for eliminating a pre-ghost of an input signal and a first feedback (FB) unit for eliminating a post-ghost of the input signal, a Trellis decoder for Trellis-decoding an output signal of the first equalizer, and a second equalizer having a second FF unit for eliminating the pre-ghost of the input signal and a second FB unit for eliminating the post-ghost of the input signal based on a signal decoded by the Trellis decoder. The first and second equalizers, interacting with the Trellis decoder, enable the equalization performance and speed of the channel equalizer to be enhanced.

VSB RECEPTION SYSTEM WITH ENHANCED SIGNAL DETECTION FOR PROCESSING SUPPLEMENTAL DATA

A digital television (DTV) receiver comprises a demodulator configured to demodulate a DTV signal containing first service data multiplexed with second service data. A first decoder is configured to decode the demodulated DTV signal for first error correction, in order to correct errors in the first and second service data that occurred during reception of the DTV signal. A data separator is configured to separate the first service data and the second service data from the decoded DTV signal and a second decoder is configured to further decode the separated first service data for second error correction in order to additionally correct errors in the first service data that occurred during the reception of the DTV signal.

RECEIVER CAPABLE OF IMPROVING SIGNAL-TO-NOISE RATIO IN REPRODUCING DIGITAL SIGNAL

... 17 In a receiver comprising a filter section for filtering a transmitted digital signal into a filtered digital signal and an equalizer section for equalizing the filtered digital signal into an equalized digital signal as a reproduced digital signal in response to controllable tap gains supplied from a control arrangement, the equalizer section comprises a first arrangement for filtering the filtered digital signal in response to predetermined ones of the controllable tap gains to produce an intermediate digital signal and a second arrangement for equalizing the intermediate digital signal into the equalized digital signal in response to remaining ones of the controllable tap gains except for the predetermined controllable tap gains to produce the reproduced digital signal. The control arrangement controls the predetermined tap gains so as to minimize noise power of a noise signal accompanying the filtered digital signal and the remaining controllable tap gains and to equalize the intermediate ...

SPATIO-TEMPORAL EQUALISATION USING CHOLESKY FACTORISATION AND SYSTOLIC ARRAYS

A spatio-temporal equaliser is described, for use with adaptive antenna arrays, in base stations of cellular systems, and in the presence of time- varying channels and/or non-stationary interferers. The beamforming coefficients and the coefficients of the decision feedback equaliser are jointly adapted, using a single error function, with processing based on Cholesky factorisation techniques. The processing procedes from the midamble outwards, and is implemented as a systolic array.

DECISION FEEDBACK EQUALIZER AND TRANSCEIVER

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

DECISION FEEDBACK EQUALIZER AND TRANSCEIVER

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

DECISION FEEDBACK EQUALIZER

An improved decision feedback equalizer for use with digital communications. The equalizer includes an error detector, a process controller, a parameter selector and a data buffer for temporarily storing a digital data signal received from a communication channel. The error detector determines whether the equalizer is accurately tracking changes in the communication channel's characteristics or is lost. When the error detector determines that the equalizer is lost, the process controller responsively generates control signals for initiating an optimal retraining/recovery method for the prevailing conditions. In some retraining/recovery methods, data is temporarily stored in the buffer. The stored data is later retrieved and processed once the equalizer is retrained. Retraining is performed using a retraining signal received via the communication channel or, if available, a portion of the data signal which is suitable for retraining, thereby permitting more rapid resumption of data reception ...

EQUALIZER

ORDER RECURSIVE LATTICE DECISION FEEDBACK EQUALIZATION FOR DIGITAL CELLULAR RADIO

COMBATING SIGNAL INTERFERENCE IN DIGITAL TRANSMISSION

A device and method for removing signal interference from a digital signal by using an adaptive filter which tunes to the periodic components of the interfering signal. The output of the adaptive filter is then subtracted from the received signal to produce an error signal. This error signal is then used to recursively update the taps of the adaptive filter. The invention also relates to the use of the adaptive filter in conjunction with a DFE.

DECISION FEEDBACK EQUALIZER FOR A DIGITAL SIGNAL RECEIVING SYSTEM

The adder subtracts the estimated echo from the input symbol to generate the demodulated symbol, and the Trellis decoder applies Trellis decoding onto the demodulated symbol to generate maximum likelihood transmission symbol sequence. The feedback register stores estimated transmission symbol values for a feedback filter, and A coefficient register stores coefficient values for the feedback filter. The feedback register updating unit generates the estimated transmission symbol and the estimated transmission symbol value corresponding to the next time point based on the demodulated symbol, the maximum likelihood transmission symbol sequence and the estimated transmission symbol corresponding to a current time point, and updates the values stored in the feedback register by using the estimated transmission symbol value corresponding to the next time point. The coefficient updating unit updates the values stored in the coefficient register based on the demodulated symbol and the estimated ...

Entzerrer für einen Kanal, dessen Übertragungseigenschaften zeitlichen Änderungen unterworfen sein können

PROCEDIMENTO E DISPOSITIVO BY L'EQUALIZZAZIONE NON LINEAR DI SEGNALI NUMERICI.

Procedure for the transmission of digital data.

PROCEDURE FOR THE ENTERPRISE OF A DATA LINK.

用于N天线系统的联合定时恢复和均衡

... 位于数字接收机前端的定时恢复环路包括：一个抽样速率转换器，其接收以第一抽样速率的符号流，且响应于一个定时恢复(TR)控制信号而输出以第二抽样速率的符号流；一个根据以第二抽样速率的符号流来生成被均衡的反馈信号的前向均衡器，和一个根据被均衡的反馈信号而生成TR控制信号的定时恢复电路。如果需要，该定时恢复环路可以包括一个将抽样速率转换器电耦合到该前向均衡器的载波恢复电路，和一个将载波恢复电路电耦合到该前向均衡器的有限冲激响应(FIR)滤波器。在一个示例情形中，FIR滤波器是一个平方根升余弦滤波器。还描述了一个根据被均衡的反馈信号和对应的定时恢复控制信号来控制该定时恢复环路的方法。 ...

PROCESS AND EQUALIZATION BY SEGMENTATIONS OF THE DATA

Procédé et dispositif d'égalisation de données dans un récepteur, les données ayant transitées dans un canal de transmission, le signal reçu comportant une ou plusieurs trames, une trame comportant au moins une probe et un bloc de données. Le procédé détermine au moins une probe fictive dans le bloc de données en utilisant au moins une partie des probes disponibles dans les trames avant et après la trame considérée, une étape de détermination de la réponse impulsionnelle intermédiaire associée à la ou aux probes fictives et la combinaison desdites réponses impulsionnelles intermédiaires.

IMPROVEMENTS WITH the DEVICES Of ADAPTIVE EQUALIZATION FOR NUMERICAL RECEIVERS DESYSTEMES OF COMMUNICATION

IMPROVED METHOD FOR CONTINUOUS-PHASE MODULATION AND TRANSMITTER FOR IMPLEMENTING SAID METHOD

Procédé de modulation à phase continue comprenant les étapes suivantes : • Recevoir (101) une séquence de symboles a(n) de données numériques à émettre, • Transformer (102) la séquence de symboles a(n) à émettre en une séquence de symboles b(n) transformée, dont chaque symbole b(n) est égal à la somme d'un symbole à émettre a(n) et d'un facteur correctif égal à une transformation Tf appliquée à une pluralité d'écarts (a(n)-a(n-1)) entre deux symboles consécutifs à émettre, la transformation Tf appliquée étant une combinaison c d'au moins deux écarts entre deux symboles consécutifs de la séquence à émettre, transformés par l'application d'une fonction non linéaire f, • Filtrer (103) la séquence de symboles b(n) transformés par un filtre de mise en forme et moduler (104) la séquence filtrée par un modulateur de phase, • Ladite transformation Tf étant déterminée de sorte à minimiser l'interférence entre les symboles modulés et filtrés par un filtre de réception.

EQUALIZER OF NEGATIVE FEEDBACK OF DECISION AND PROCESS OF UPDATE OF the COEFFICIENTS Of INDEX OF THIS ONE

L'égaliseur de contre-réaction de décision conforme à la présente invention comprend : - un premier égaliseur comprenant une pluralité de coefficients d'index afin de réduire un bruit d'interférence d'un canal dans un signal d'entrée, - un calculateur de signal, - un second égaliseur comprenant une pluralité de coefficients d'index pour générer un signal de contre-réaction afin de réduire un bruit d'interférence restant, - un calculateur de valeurs de mise à jour, - et un contrôleur de mise à jour (60) destiné à commander la mise à jour des coefficients d'index. Conformément à la présente invention, du fait que les coefficients d'index de l'égaliseur de pré-compensation (24) et de l'égaliseur de contre-réaction (40) sont initialisés en alternance, il est possible de faire converger de façon stable les coefficients d'index respectifs sans les faire diverger et de réduire la puissance utilisée pour mettre à jour les coefficients d'index d'une moitié dans un état stable.

PROCESS AND DEVICE OF DETECTION OF the SEQUENCE Of TRAINING Of a SELF-ADAPTING EQUALIZER

DISTORTION CORRECTING DEVICES FOR PARTIAL RESPONSE SIGNALS

ЕGАLISЕUR DЕ СОNТRЕ-RЕАСТIОN DЕ DЕСISIОN ЕТ РRОСЕDЕ DЕ МISЕ А JОUR DЕS СОЕFFIСIЕNТS D'INDЕХ DЕ СЕLUI-СI

L'égаlisеur dе соntrе-réасtiоn dе déсisiоn соnfоrmе à lа présеntе invеntiоn соmprеnd : - un prеmiеr égаlisеur соmprеnаnt unе plurаlité dе соеffiсiеnts d'indех аfin dе réduirе un bruit d'intеrférеnсе d'un саnаl dаns un signаl d'еntréе, - un саlсulаtеur dе signаl, - un sесоnd égаlisеur соmprеnаnt unе plurаlité dе соеffiсiеnts d'indех pоur générеr un signаl dе соntrе-réасtiоn аfin dе réduirе un bruit d'intеrférеnсе rеstаnt, - un саlсulаtеur dе vаlеurs dе misе à jоur, - еt un соntrôlеur dе misе à jоur (60) dеstiné à соmmаndеr lа misе à jоur dеs соеffiсiеnts d'indех. Соnfоrmémеnt à lа présеntе invеntiоn, du fаit quе lеs соеffiсiеnts d'indех dе l'égаlisеur dе pré-соmpеnsаtiоn (24) еt dе l'égаlisеur dе соntrе-réасtiоn (40) sоnt initiаlisés еn аltеrnаnсе, il еst pоssiblе dе fаirе соnvеrgеr dе fаçоn stаblе lеs соеffiсiеnts d'indех rеspесtifs sаns lеs fаirе divеrgеr еt dе réduirе lа puissаnсе utiliséе pоur mеttrе à jоur lеs соеffiсiеnts d'indех d'unе mоitié dаns un étаt stаblе.

ADAPTIVE CHANNEL EQUALIZER HAVING A TRAINING MODE

Adaptive equalizer having a variable step size influenced by output from a trellis decoder

Transmitting/receiving system and data processing method

Decision feedback equalizer

저전력 및 고성능 수신기에 대한 오프셋 캘리브레이션

... 저전력 및 고성능 수신기들에 대한 오프셋 캘리브레이션을 제공하기 위한 시스템들 및 방법들이 본 명세서에서 설명된다. 일 실시예에 있어서, 오프셋 캘리브레이션을 위한 방법은 제1 전압을 샘플 래치의 제1 입력부에 입력하는 단계 및 제2 전압 및 오프셋 소거 전압을 샘플 래치의 제2 입력부에 입력하는 단계를 포함한다. 그 방법은 또한, 오프셋 소거 전압을 조절하는 단계, 오프셋 소거 전압이 조절됨에 따라 샘플 래치의 출력을 관찰하는 단계, 및 샘플 래치의 출력에서 준안정 상태 (1과 0 사이에서 토글) 가 관찰되는 오프셋 소거 전압의 값을 기록하는 단계를 포함한다. 그 방법은 전압 레벨들 중 각각의 전압 레벨에 대해 오프셋 소거 전압을 결정하기 위해 제1 전압에 대한 복수의 상이한 전압 레벨들 중 각각의 전압 레벨에 대해 수행될 수도 있다.

SEGMENTED EQUALIZER, ESPECIALLY WITH REGARDS TO ACCOMPLISHING FAST CONVERGENCE TIME, LOW SELF NOISE, AND LOW EXECUTION OR LOW MANUFACTURING COST

PURPOSE: A segmented equalizer is provided to reduce self noise and multi-path effects when being used in wireless data transmission environments, and to increase convergence speed. CONSTITUTION: A segmented equalizer(500) includes a plurality of feed forward equalizer segments(502). Each of the feed forward equalizer segments(502) includes a filter block for filtering delayed samples, in response to the delayed samples of an input signal{v.sub.n(n is an index of each sample)} and by using updated coefficients based on step size generated for each of the equalizer segments(502). © KIPO 2007 ...

고속 통신 시스템

... 정보 비트를 수신하고 벡터 코드워드를 표시하는 기저대역 인코딩 심볼들의 집합을 발생하도록 각각 구성된 복수의 인코더와; 기저대역 인코딩 심볼들의 대응하는 집합에서 동작하고, 각각의 고유한 캐리어 주파수를 이용하여 캐리어 변조된 인코딩 심볼들의 집합을 발생하도록 각각 구성된 하나 이상의 변조 회로와; 캐리어 변조된 인코딩 심볼들의 각 심볼과 적어도 하나의 기저대역 인코딩 심볼 집합의 합을 각각 표시하는 배선 특유 출력들의 집합을 발생하도록 구성된 합산 회로를 이용하여, 기저대역 및 캐리어 변조 벡터 코드워드를 전송하는 장치 및 방법이 개시된다.

클록 임베디드 벡터 시그널링 코드

... 단위 송신 간격당 보증된 수의 천이를 제공하는 벡터 시그널링 코드가 그들의 생성 및 사용을 위한 방법 및 시스템과 함께 제공된다. 제공되는 아키텍처는 복수의 통신 서브시스템을 포함할 수 있고, 각각의 통신 서브시스템은 그 자신의 통신 배선 그룹 또는 서브채널, 클록 임베디드 시그널링 코드, 원하는 코드 천이 밀도를 보증하기 위한 전처리 및 후처리 스테이지, 및 서브시스템들 간에 데이터 요소들을 최초 배분하고 그 다음에 그 수신된 서브시스템 요소로부터 수신 데이터를 재구성하는 글로벌 인코딩 및 디코딩 스테이지를 갖는다.

결정 피드백 등화기

... 장치는, 제1 클록(도 3의 ADC 출력 클록)에 기반하여 생성된 병렬 신호(도 4의 214)를 수신하도록 구성된 결정 피드백 등화기(도 2의 206; 도 4의 206)를 포함한다. 결정 피드백 등화기는, 제1 클록의 제1 클록 사이클(도 3의 306) 동안 병렬 신호에 의해 제공된 병렬 심볼들의 제1 세트(도 3의 ADC[0:N-1]) 중 제1 심볼(도 3의 ADC[0])을 수신하도록 구성된 제1 등화 블록(도 4의 DFE[0])을 포함한다. 결정 피드백 등화는, 제1 결정(도 4의 422, D[0])을 제2 등화 블록에 제공하기 위해 제1 심볼에 대하여 제1 등화 블록에 의해 수행된다. 제2 등화 블록(도 4의 DFE[1])은, 병렬 심볼들의 제1 세트 중 제2 심볼(도 3의 ADC[1])을 수신하고, 제1 클록 사이클 동안 제2 결정(도 4의 422, D[1])을 제공하기 위해 제1 등화 블록으로부터 수신된 제1 결정을 사용하여 제2 심볼에 대한 결정 피드백 등화를 수행하도록 구성된다.

Method and device of symbol decision and digital receivers

Unequalized clock data recovery for serial I/O receiver

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

BESLUTSAATERKOPPLAD OLINJAER UTJAEMNARE

MESH AD-HOC NETWORK CHANNEL ADAPTIVE EQUALIZER

Disclosed is a MESH ad-hoc network channel adaptive equalizer, comprising: a linear equalizer and a decision feedback equalizer; the linear equalizer comprises a time-delay unit, a tap coefficient unit, an adder, and a sample decider; the tap coefficient unit consists of a noise generation module and a multiplier; the output of each tap coefficient unit is connected to the adder; the equalized output of the adder is connected to the sample decider; the decision feedback equalizer comprises a forward filter and a feedback filter; the feedback filter comprises a tap coefficient unit and a time-delay unit; the equalized output of the adder is connected to the input of the time-delay unit; the output of the time-delay unit is connected to the input of the tap coefficient unit; and the output of each tap coefficient unit is connected to the adder. The present invention has a time-variant characteristic for tracking a communication channel in real time, overcomes the interference between symbols ...

LOW-COMPLEXITY, HIGHLY-SPECTRALLY-EFFICIENT COMMUNICATIONS

A system may comprise circuitry that includes a sequence estimation circuit and a non-linearity modeling circuit. The circuitry may be operable to receive a single-carrier signal that was generated by passage of symbols through a partial response filter and through a non-linear circuit. The circuitry may be operable to generate estimated values of the symbols using the sequence estimation circuit and using the non-linearity modeling circuit. An output of the non-linearity modeling circuit may be equal to a corresponding input of the non-linearity modeling circuit modified according to a non-linear model that approximates the non-linearity of the non-linear circuit through which the received signal passed.

HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

RADIO RECEIVER HAVING A CHANNEL EQUALIZER AND METHOD THEREFOR

A radio receiver (10) for receiving a signal is provided. The radio receiver (10) comprises an equalizer (22) configured to perform a constant modulus algorithm initialized using a first set of coefficients on the received signal and for generating an equalized signal (23). The radio receiver (10) further comprises a demodulator (24) coupled to the equalizer (22) for demodulating the equalized signal (23). The radio receiver (10) further comprises a lowpass filter (30) coupled to the demodulator (24) for lowpass filtering the demodulated signal to detect a spurious signal and to generate an offset signal (31). The radio receiver (10) further comprises a coefficient generator (32) coupled to the lowpass filter (30) and configured to compare the offset signal (31) to a predetermined threshold, and if the offset signal (31) satisfies a predetermined condition in relation to the predetermined threshold, then to generate a second set of coefficients for re-initializing the constant modulus algorithm ...

CHANNEL EQUALIZER, CHANNEL EQUALIZATION METHOD, AND TAP COEFFICIENT UPDATING METHOD

A channel equalizer to equalize a signal received over a transmission channel, includes a feedforward filter to filter the received signal, a level determination unit to determine a first level value among a plurality of predetermined amplitude levels based on an amplitude of an output signal of the feedforward filter, and an error calculation unit to calculate a first error value based on the amplitude of the output signal of the feedforward filter and the first level value and to output the first error value to the feedforward filter so that the feedforward filter updates a tap coefficient thereof using the first error value. As such, the channel equalizer is capable of operating independently of a phase error by using the amplitude of the received signal in channel equalization, whereby a variety of designs can be available for the channel equalizer regardless of a sequence of a carrier recovery operation and a channel equalization operation.

DUAL-MODE EQUALIZER IN AN ATSC-DTV RECEIVER

A receiver comprises an equalizer that has at least two coefficient modes of operation, in a first coefficient mode, the equalizer starts with a preset non-zero value in the main tap; while in a second coefficient mode, the equalizer starts such that all taps are set equal to the same value, e.g., a value of zero.

ADAPTATION OF PRE-EQUALISERS

Adaptive equalization methods used with precoded systems dominated by inter-symbol interference (ISI) is disclosed. The adaptive equalizers monitor the output of a DFE and compare it to a reference for updating a pre-coder in response to the comparison. To accomplish this, the adaptive equalizer includes a feed forward equalizer receiving a signal from a communication channel, the feed forward equalizer equalizing variations in pre-cursor intersymbol interference resulting from changes in characteristics of the channel and providing an output signal to an error correction decoder, a decision circuit, coupled to the feed forward equalizer, for generating error vectors in response to the output signal of the feed forward equalizer and a decision feedback equalizer, coupled to the decision circuit, the decision feedback equalizer monitoring the pre-cursor intersymbol interference of the channel, determining when the transmitter coefficients to the pre-coder warrant updating, and generating ...

CCK DEMODULATION VIA SYMBOL DECISION FEEDBACK EQUALIZER

Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter (70), a feedback intersymbol interference (ISI) canceller (78), a transform unit (72), a phase rotation estimator and corrector (76), a pattern-dependent bias canceller (80, 81, 82), and a maximum picker (84) for symbol decisions (86). The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.

OPERATING FREQUENCY REDUCTION FOR TRANSVERSAL FIR FILTER

A method and system for reducing the frequency of operation for a transversal Finite Impulse Response (FIR) filter is disclosed. In the preferred embodiment, the transversal filter operates in such a way that it has an even and odd row of data, which are latched on rising and falling edges of the clock respectively. This allows the clock frequency to be reduced by a factor of 2, and thus allows the use of more power efficient latches. A reduction in the frequency of operation causes the high speed latches within the transversal filter to hold the data bits twice as long as is required, which changes the desired impulse response of the FIR filter. A circuit is required to select the appropriate data bits from the output of the appropriate half-speed latch, and subsequently scale it to apply the co-efficient gain. Each of the subsystems is analog, and operates in accordance with a synchronous clock system. In a more general embodiment of the invention, the data is provided to Q shift registers ...

METHOD AND APPARATUS FOR IMPLEMENTING ADAPTIVE TOMLINSON-HARASHIMA PRECODING IN A DIGITAL DATA LINK

The invention relates to a method for implementing adaptive Tomlinson-Harashima precoding using a digital data communications link. According to the method, the outgoing bit stream is coded into symbols, channel distortion is corrected by precoding (TML) the symbols, the precoded symbols are sent over a data communications channel (2, CHN), in which case the symbols, which have passed through the channel (2, CHN) and signal processing means for the receiver are reconstructed to form a bit stream. According to the invention, updated precoder coefficient parameter values are formed with the aid of an error variable (e), which is dependent on the symbol decisions (S') of the receiver, the output signal of a decision-feedback equalizer, and a signal (Q) that is formed from the received signal by compensating the effect of the precoder transfer function of the received signal with an inverse precoder transfer functions.

On-chip jitter evaluation for SerDes

An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.

Backplane emulation technique for automated testing

The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.

Serial link voltage margin determination in mission mode

This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Hybrid equalization system

A hybrid equalization system includes an equalization device, a target channel impulse response device, a maximum likelihood sequence estimation device and a multiplexer. The equalization device receives a sampled baseband signal and performs an equalization operation thereon for generating first estimated symbols. The target channel impulse response device convolutes the first estimated symbol and a predetermined target channel response function for generating a training symbol corresponding to a target channel. The maximum likelihood sequence estimation device performs a maximum likelihood sequence estimation on the sampled baseband signal trained by first estimated symbols based on the target channel impulse response for generating second estimated symbols. The multiplexer selects the first estimated symbol or the second estimated symbol as an output of the hybrid equalization system according to a selection signal.

Decision directed timing recovery using multi-phase detection

A set of one or more samples is received. Using a first signal processor associated with a first phase offset, a first decision and a first error value are generated using the set of samples. Using a second signal processor associated with a second phase offset, a second decision and a second error value are generated using the set of samples. This includes interpolating the set of samples to obtain a set of interpolated samples at the second phase offset and generating the second decision and the second error value using the set of interpolated samples at the second phase offset. A selection associated with the first decision and the second decision is made based at least in part on the first error value and the second error value.

Analog Continuous-Time Phase Equalizer for Data Transmission

In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals.

Detection and mitigation of interference in a receiver

A novel receiver architecture optimizes receiver performance in the presence of interference. In various embodiments, power estimation circuits are used with variable selectivity to determine the exact nature of the interference and to optimize the performance correspondingly. The variable selectivity is achieved using stages of filtering with progressively narrower bandwidths. Also, the actual method of optimizing the receiver performance is novel compared to the prior art in that the gain settings and the baseband filter order (stages to be used) will be optimized based on the nature of the interference as determined by the power detector measurements. For a device such as a cellular phone that operates in a dynamic and changing environment where interference is variable, embodiments advantageously provide the capability to modify the receiver's operational state depending on the interference.

Techniques for setting feedback coefficients of a pam-n decision feedback equalizer

A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.

Pattern detector for serializer-deserializer adaptation

In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Extension of ethernet phy to channels with bridged tap wires

In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Interference Cancellation with Time-Varying Interference and/or Distortion

A communications receiver includes a noise analyzer to characterize the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions. The noise analyzer may provide a selection signal indicating the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions to be used by the communications receiver. In an exemplary embodiment, the communications receiver selects at least one set of filter coefficients to compensate for the interference and/or distortion impressed onto a transmitted communications signal in the presence of a particular time-varying interference and/or distortion condition. In another exemplary embodiment, the communications receiver selects a corresponding interference cancellation filter hank to compensate for the interference and/or distortion impressed onto a transmitted communications signal in the presence of the particular time-varying interference and/or distortion condition.

Receiver Having Limiter-Enhanced Data Eye Openings

A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Decision feedback equalizer

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer. 1sampling a data signal having a voltage value at an expected edge time of the data signal:generating a first alpha value and a second alpha value in dependence upon the voltage value;adjusting the data signal by the first alpha value to derive a first adjusted signal;adjusting the data signal by the second alpha value to derive a second adjusted signal;sampling the first adjusted signal to output a first data value;sampling the second adjusted signal to output a second data value; andselecting between the first data value and the second data value as a function of a prior received data value to determine a received data value.. A method comprising: This application is a Continuation of U.S. application Ser. No. 12/513,898, filed Dec. 23, 2009, which is the national phase entry of International Application No. PCT/U.S.2007/023600, filed Nov. 9,2007, which claims benefit of priority to U.S. Provisional Application No. 60/859,820, filed Nov. 16, 2006; all of the priority claims are hereby incorporated by Reference in their entirety for all purposes.The performance of conventional digital systems is limited by the transmission interconnection ...

RECEPTION DEVICE AND RECEPTION METHOD

The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission. 1. A reception device comprising:a time domain equalization unit which equalizes a received signal in a time domain;a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain; andan equalization method control unit which performs control of switching between the time domain equalization unit and the frequency domain equalization unit.2. The reception device according to claim 1 , wherein the received signal is a signal defined according to a GB20600-2006 standard claim 1 , and claim 1 , when a C3780 signal defined according to the GB20600-2006 standard is received claim 1 , the frequency equalization unit equalizes the received signal and claim 1 , when a C1 signal defined according to the GB20600-2006 standard is received claim 1 , the equalization method control unit switches between the time domain equalization unit and the frequency domain equalization unit to equalize the received signal.3. The reception device according to claim 1 , wherein the frequency domain equalization unit comprises:a FFT operating unit which converts the received signal into a frequency domain signal; anda distortion compensation unit which compensates for distortion of the ...

WIRELESS COMMUNICATION DEVICE AND WIRELESS COMMUNICATION METHOD

A demodulation section demodulates a received signal. A decoding section decodes an output from the demodulation section. A buffer temporarily stores a portion of the received signal. A header analyzing section gives the buffer timing at which demodulation and decoding of a payload of the received signal are initiated, on the basis of a result of combination of a plurality of header sequences included in a header of the received signal and results of processing of the demodulation section and the decoding section. An improved SNR is achieved by means of combination of the plurality of header sequences, so that an iterative decoding count used for decoding the header become smaller. 1. A wireless communication device configured to receive a signal with a frame format including a plurality of header sequences , comprising:a demodulation section configured to demodulate the plurality of header sequences; anda decoding section configured to decode the modulated header sequences, to thereby acquire header information of the signal.2. The wireless communication device according to claim 1 , further comprising:a combining section configured to combine the plurality of header sequences, whereinthe demodulation section demodulates the combined plurality of header sequences.3. The wireless communication device according to claim 1 ,wherein the header sequences are subjected to error correction coding by means of LDPC coding,wherein the demodulation section calculates soft decision values of the error correction coded header sequences; andwherein the decoding section subjects the calculated soft decision values of the header sequences to error correction decoding.4. The wireless communication device according to claim 3 , further comprising:a buffer configured to store a payload of the signal until the header information is acquired by iterative decoding, whereinthe demodulation section demodulates the stored payload, to thus calculate a soft decision value of the payload; and ...

CLOCK RECOVERY FOR OPTICAL TRANSMISSION SYSTEMS

A receiver for an optical communications system which corrects distortion of a received signal. A clock recovery system utilising a feedback and feedforward system are provided. The feedback loop comprises a phase detector and a clock source, while the feedforward loop comprises the phase detector and a delay element for delaying the output of distortion correction system. The feedback loop has a significantly lower bandwidth than the feedforward path. There are also provided methods of optimising tap weights and of acquiring initial tap weights. 1. A method of initially acquiring tap weights for a finite impulse response (FIR) filter used to correct distortion in an optical communication receiver , the method comprising:acquiring and storing a series of samples of a received optical signal; andapplying a blind optimization algorithm to the series of samples to obtain an estimate of tap weights for the FIR filter in order to equalize the received optical signal.2. The method according to claim 1 , further comprising transferring the series of samples to a digital processing system and performing the blind optimization in the digital processing system.3. The method according to claim 1 , wherein the blind optimization algorithm is applied in both forwards and backwards directions to the series of samples.4. The method according to claim 1 , further comprising transferring the estimated tap weights to the FIR filter.5. The method according to claim 4 , further comprising correcting distortion in the received optical signal with the FIR filter.6. The method according to claim 4 , further comprising the activating a clock recovery system in the optical communication receiver. The method according to claim 4 , further comprising:acquiring and storing a further series of samples of the received optical signal; andapplying a blind optimization algorithm to the further series of samples to obtain an improved estimate of the tap weights.87. The method according to claim ...

HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI. 1a differential input port to receive a differential signal representing a series of symbols, the input port including a pair of pads;termination elements coupled to the pads to terminate the differential signal;continuous-time gain-control and equalization circuitry coupled to the pads, the circuitry to control gain and equalize a frequency range encompassing interference from a most-recently received symbol in the series of symbols;a decision-feedback equalizer coupled to the gain-control and equalization circuitry, the equalizer to equalize a frequency range only encompassing interference from arising from symbols other than the most-recently received symbol in the series;a data sampler to produce data samples from an equalized signal representing equalization by the gain-control and equalization circuitry and the decision-feedback equalizer; andan adaptation engine to generate a gain control value to adjust the gain provided by the gain-control and equalization circuitry and an equalization-control value to adjust a low-frequency gain of the gain-control and equalization circuitry relative to a high-frequency gain of the gain-control and equalization circuitry.. An integrated-circuit receiver to receive a series of symbols over a communication channel, the receiver comprising: The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.The performance of many digital systems is limited by the interconnection bandwidth within and between integrated ...

Equalizer

An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.

CONTINUOUS PHASE MODULATION METHOD AND EMITTER IMPLEMENTING SAID METHOD

A continuous phase modulation method comprises the following steps: receiving a sequence of digital data symbols a(n) to be emitted; transforming the sequence of symbols a(n) to be emitted into a transformed sequence of symbols b(n), each symbol b(n) of which is equal to the sum of a symbol a(n) to be emitted and of a corrective factor equal to a transformation Tf applied to a plurality of differences (a(n)-a(n−1)) between two consecutive symbols to be emitted, the transformation Tf applied being a combination c of at least two differences between two consecutive symbols of the sequence to be emitted, transformed by the application of a non-linear function ƒ; filtering the sequence of transformed symbols b(n) with a shaping filter and modulating the filtered sequence with a phase modulator; said transformation Tf being defined so as to minimize interference between modulated symbols filtered by a receiving filter. 1. A continuous phase modulation method comprising the following steps:receiving a sequence of digital data symbols a(n) to be emitted;transforming the sequence of symbols a(n) to be emitted into a transformed sequence of symbols b(n), each symbol b(n) of which is equal to the sum of a symbol a(n) to be emitted and of a corrective factor equal to a transformation Tf applied to a plurality of differences (a(n)-a(n−1)) between two consecutive symbols to be emitted, the transformation Tf applied being a combination c of at least two differences between two consecutive symbols of the sequence to be emitted, transformed by the application of a non-linear function ƒ;filtering the sequence of transformed symbols b(n) with a shaping filter; andmodulating the sequence of filtered symbols with a phase modulator in order to obtain a sequence of modulated symbols,said transformation Tf being defined so as to minimize interference between modulated symbols filtered by a receiving filter.2. The continuous phase modulation method as claimed in claim 1 , in which said ...

SAMPLER CIRCUIT WITH CURRENT INJECTION FOR PRE-AMPLIFICATION

Some embodiments include apparatus and methods using an input unit including a first transistor to receive a first signal of a differential signal pair, a second transistor to receive a second signal of the differential signal pair, and a third transistor to receive a clock signal, with the third transistor coupled to the first and second transistors at a node. The input unit includes a circuit component to form a first circuit path between the node and a supply node during a first phase of the clock signal. The third transistor is to form a second circuit path between the node and the supply node during a second phase of the clock signal. The apparatus includes an output unit coupled to the first and second transistors to generate output information based on voltages of the first and second signals during the second phase of the clock signal. 1. An apparatus comprising:a first transistor to receive a first signal of a differential signal pair;a second transistor to receive a second signal of the differential signal pair;a third transistor to receive a clock signal, the third transistor coupled to the first and second transistors at a node, the third transistor including a terminal directly coupled to a supply node;a circuit component to form a first circuit path between the node and the supply node during a first phase of the clock signal, and the third transistor to form a second circuit path between the node and the supply node during a second phase of the clock signal; andan output unit coupled to the first and second transistors to generate output information based on voltages of the first and second signals during the second phase of the clock signal.2. The apparatus of claim 1 , wherein the circuit component includes a current source coupled between the node and the supply node.3. The apparatus of claim 1 , wherein the output unit includes a transistor between the first transistor and a first node claim 1 , and another transistor between the second transistor ...

LOW POWER EQUALIZER AND ITS TRAINING

Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal. 1. An apparatus comprises:a pad to receive an input signal;an electro-static discharge (ESD) unit coupled to a pad; anda linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.2. The apparatus of further comprises:samplers, coupled to the LE, operable to perform LE equalization training and a function of an un-rolled decision feedback equalizer (DFE).3. The apparatus of claim 2 , wherein the samplers include:offset samplers; anda non-offset sampler or samplers.4. The apparatus of further comprises logic to select output of the offset samplers when two adjacent bits of the input signal are the same.5. The apparatus of further comprises logic to select output of the non-offset sampler or samplers when two adjacent bits of the input signal are different.6. The apparatus of further comprises logic to set offset of offset samplers to a sum of the first post-cursor residual ISI tap and the first pre-cursor residual ISI tap.7. The apparatus of further comprises logic to tune offset of the offset samplers to maximize signal integrity of the received input signal.8. The apparatus of further comprises logic to train the LE.9. The apparatus of claim 8 , wherein the logic to train the LE by modifying an error function of the LE to ignore data when two adjacent bits of the input signal are the same.10. The apparatus of claim 1 , wherein the logic to train ...

High-speed signaling systems with adaptable pre-emphasis and equalization

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Margin Test Methods and Circuits

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing. 1. (canceled)2. A receiver circuit comprising: a sampler input terminal to receive a series of symbols;', 'a sampler reference terminal to receive a reference signal against which to compare the series of symbols; and', 'a sampler timing terminal to receive a timing signal;', 'the sampler to sample the series of symbols with reference to the reference signal in time with the timing signal to produce a series of samples;, 'a sampler having a first comparison-logic input terminal coupled to the sampler to receive the series of samples;', 'a second comparison-logic input terminal; and', 'a comparison-logic output terminal;, 'comparison logic having a first multiplexer input terminal coupled to the sampler to receive the series of samples;', 'a second multiplexer input terminal; and', 'a multiplexer output terminal; and, 'a multiplexer having a shift-register input terminal coupled to the multiplexer output terminal; and', 'at least one shift-register output terminal coupled to the second multiplexer input terminal and the second comparison-logic input terminal., 'a shift register having3. The receiver circuit of claim 2 , ...

CLOCK DATA RECOVERY WITH DECISION FEEDBACK EQUALIZATION

Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern. 1. A method comprising:generating a sub-channel output by combining signals received via a plurality of wires, the sub-channel output generated according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors;generating two decisions by sampling the sub-channel output at respective speculative decision feedback equalization (DFE) decision thresholds of a pair of speculative DFE decision thresholds, the two decisions generated at a sampling instant determined by a sampling clock;determining, from the two decisions, (i) a data decision of the sub-channel output generated using a first speculative DFE decision threshold of the pair of speculative DFE decision thresholds according to a historical data decision, and (ii) an edge trajectory sample of the sub-channel output generated using a second speculative DFE decision threshold of the pair of speculative DFE decision thresholds responsive to detection of a predetermined transitional data pattern;generating a phase-error signal based on the edge trajectory sample and the historical data decision; andproviding the phase-error signal to a clock recovery circuit to adjust the sampling instant of the sampling clock to align the second speculative DFE decision threshold with a trajectory of the data signal at the sampling instant.2. The method of claim 1 , wherein the phase-error signal is an early/late logic ...

METHOD FOR REMOVING SPATIAL AND TEMPORAL MULTI-PATH INTERFERENCE FOR A RECEIVER OF FREQUENCY-MODULATED RADIO SIGNALS

A method for decreasing multi-path interference, for a vehicle radio receiver including at least two radio reception antennas that each receive a plurality of radio signals composed of time-shifted radio signals resulting from a multi-path effect. The plurality of radio signals combined to deliver a combined radio signal yto be played, with: y=W[, X+, X] at time n, where xand xare vectors the components of which correspond to the plurality of signals received by the first antenna and by the second antenna, respectively, Gand Gare scalars the components of which are the complex weights of a spatial filter and wis the transpose matrix of a vector the components of which are the complex weights of a temporal filter. The method includes implementation of an iterative adaptation algorithm to determine the complex weights of the spatial filter and the complex weights of the temporal filter. 3. The method as claimed in claim 2 , wherein said iterative adaptation algorithm is a constant modulus adaptation algorithm configured to minimize the cost function.6. The method as claimed in claim 1 , wherein the temporal filter is an impulse response filter.7. A radio receiver comprising a microcontroller configured to implement the method as claimed in .8. A motor vehicle comprising a radio receiver as claimed in . This application is the U.S. National Phase Application of PCT International Application No. PCT/FR2018/051249, filed May 31, 2018, which claims priority to French Patent Application No. 1754868, filed Jun. 1, 2017, the contents of such applications being incorporated by reference herein.The invention relates to the field of the reception of frequency-modulated radio signals, in particular in mobile radio receivers exposed to the effect of multi-paths, which is known to those skilled in the art.More precisely, the present invention relates to a method for removing reflected radio waves resulting from the multi-path effect in a receiver of frequency-modulated radio ...

Symbol-Rate Phase Detector for Multi-PAM Receiver

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation. 1. A multi-PAM receiver comprising:an input node to receive an input signal expressing a series of symbols, including an immediate symbol representing an analog immediate-symbol value and a prior symbol representing an analog prior-symbol value, each value representing multiple bits, including a most-significant bit (MSB) and a least-significant bit (LSB);a multi-PAM equalizer coupled to the input node, the multi-PAM equalizer to issue an immediate MSB decision and an immediate LSB decision responsive to the immediate-symbol value and a prior MSB decision and a prior LSB decision responsive to the prior-symbol value; anda phase detector to issue a phase-error signal responsive to the analog immediate-symbol value, the analog prior-symbol value, the immediate MSB decision, and the prior MSB decision.2. The receiver of claim 1 , wherein the MSB represents a first power of two.3. The receiver of claim 1 , the multi-PAM equalizer including an MSB filter tap and an LSB filter tap claim 1 , the receiver further comprising adaptation circuit to derive an MSB tap value for the filter tap.4. The receiver of . wherein the adaptation circuit derives the MSB tap value from the immediate MSB decision and the prior MSB decision.5. The receiver of claim 1 , the multi-PAM equalizer including an MSB filter tap and an LSB filter tap claim 1 , the receiver further comprising adaptation circuit to derive an MSB tap matrix from the immediate MSB decision and the prior MSB decision.6. The receiver ...

ADAPTATION OF CROSSING DFE TAP WEIGHT

A method comprises receiving an input signal at an input of a receiver and retrieving a data sample signal and an error sample signal from the input signal. The method also comprises applying an adaptive procedure to generate a feedback code using the data sample signal and the error sample signal for feeding back into a decision feedback equalization (DFE) module. Further, it comprises converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight for the DFE module. Finally, it comprises generating an edge sample signal by applying DFE to the input signal using the DFE module, wherein the DFE is based on the tap weight. 1. An apparatus comprising:a first module coupled to an input signal and operable to generate an edge signal using a first clock signal; anda second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein a parameter of said first module is operable to be adapted, and wherein said parameter is further operable to influence a settling point of said data sampling phase signal.2. The apparatus of claim 1 , wherein said first module is a decision feedback equalizer.3. The apparatus of further comprising:a third module operable to generate a data sample signal using a second clock signal; anda fourth module operable to generate an error sample signal using a third clock signal, wherein said parameter is operable to be adapted based on said data sample signal and said error sample signal.4. The apparatus of claim 1 , wherein said parameter is operable to be adapted towards a goal claim 1 , wherein said goal is selected from a group consisting of: minimizing a precursor ISI claim 1 , maximizing vertical eye margin claim 1 , minimizing horizontal eye margin claim 1 , minimizing bit error rate claim 1 , and maximizing signal to noise ratio.5. The apparatus of wherein said first module further comprises: a first preamplifier;', 'a first ...

DECISION FEEDBACK EQUALIZER CIRCUIT WITH TRANSISTOR MOBILITY CHANGE COMPENSATION

An apparatus is described. The apparatus includes a decision feedback equalizer circuit having a summation circuit. The summation circuit has a differential pair that includes first and second transistors coupled to a current source. The current source is to draw a current through the first and second transistors. The decision feedback circuit also includes a circuit to adjust the current to compensate for a change in electron mobility of at least one transistor of the current source. 1. An apparatus , comprising:a decision feedback equalizer circuit comprising a summation circuit, said summation circuit comprising a differential pair comprising first and second transistors coupled to a current source, said current source to draw a current through said first and second transistors, said decision feedback equalizer circuit comprising a circuit to linearly adjust said current to compensate for a change in electron mobility of at least one transistor of said current source.2. The apparatus of wherein said circuit comprises bias circuitry to bias a transistor in the triode region.3. The apparatus of wherein said circuitry comprises a plurality of transistors having their respective conductive channels coupled in series claim 2 , said bias circuitry to provide a reference voltage across said plurality of transistors claim 2 , said transistor being one of said transistors.4. The apparatus of wherein said reference voltage is a fraction of said circuit's supply voltage.5. The apparatus of wherein said summation circuit comprises a second differential pair comprising third and fourth transistors coupled to a second current source claim 1 , said second current source to draw a second current through said second and third transistors claim 1 , said second current source coupled to said circuit so that said second current is compensated for a change in mobility of at least one transistor of said second current source.6. The apparatus of wherein said second differential pair is ...

DECISION FEEDBACK EQUALIZER

A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a first latch, a second latch, a first feedback path, and a second feedback path. The first latch is configured to latch data received from the summing node. The second latch is configured to latch data received from the first latch. The first feedback path is configured to receive data from the second latch and to provide data to the summing node of the equalization path. The second feedback path is configured to receive data from the first latch and to provide data to the summing node of the other equalization path. The second feedback path provides up to a symbol interval for propagation of data between the summing nodes. 1. A decision feedback equalizer (DFE) circuit , comprising: a summing node;', 'a first latch configured to latch data received from the summing node;', 'a second latch configured to latch data received from the first latch;', 'a first feedback path configured to receive data from the second latch and to provide data to the summing node of the equalization path; and', 'a second feedback path configured to receive data from the first latch and to provide data to the summing node of the other equalization path;', 'wherein the second feedback path provides up to a symbol interval for propagation of data between the summing nodes., 'a first equalization path and a second equalization path, each equalization path comprising2. The DFE circuit of claim 1 , wherein the first feedback path of each equalization path comprises a third latch configured to latch data received from the second latch of the equalization path.3. The DFE circuit of claim 1 , wherein the second feedback path of each equalization path comprises one of:a third latch configured to latch data received from the first latch of the equalization path; anda multiplexer configured to selectably route data received from the first latch ...

CLOCK AND DATA RECOVERY ARCHITECTURE WITH ADAPTIVE DIGITAL PHASE SKEW

In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank. 1. A method for producing sample decisions with a digital signal processing-based SERDES device , the method comprising the steps of:converting a received analog signal to a digital signal by an analog to digital converter in response to a sample clock;equalizing the digital signal by a feed forward equalizer followed by a decision feedback equalizer;selecting as inputs for a phase detector either the digital signal from the analog to digital converter or the equalized signal from the feed forward equalizer;computing a phase difference signal by the phase detector;adjusting, in response to the phase difference signal, a phase of the sample clock applied to the analog to digital converter;providing a phase skew to an equalized digital signal from the feed forward equalizer by a first interpolation filter bank inserted between the feed forward equalizer and the decision feedback equalizer;generating a control signal to control the phase skew provided by the first interpolation filter bank by a phase skew adaptation loop using an output of the decision feedback ...

CONTROL DEVICE, CONTROL METHOD AND CONTROL SYSTEM

A control device includes: an output circuit configured to output a first signal to a first point on a first conductive wire wired on a substrate; a reception circuit configured to receive the first signal that is transmitted through the first conductive wire, from a second point on the first conductive wire, as a second signal; and a decision circuit configured to decide a compensation value of first attenuation of a third signal that is input to a second conductive wire that is wired on the substrate and different from the first conductive wire by referring to information on second attenuation of the first signal based on a waveform of the second signal. 1. A control device comprising:an output circuit configured to output a first signal to a first point on a first conductive wire wired on a substrate;a reception circuit configured to receive the first signal that is transmitted through the first conductive wire, from a second point on the first conductive wire, as a second signal; anda decision circuit configured to decide a compensation value of first attenuation of a third signal that is input to a second conductive wire that is wired on the substrate and different from the first conductive wire by referring to information on second attenuation of the first signal based on a waveform of the second signal.2. The control device according to claim 1 , whereinthe decision circuit configured to decide a first amplitude of the third signal by referring to the information on the second attenuation.3. The control device according to claim 1 , whereinthe decision circuit configured to decide a combination of a first amplitude of the third signal and the compensation value of the first attenuation by referring to correspondence information in which the information on the second attenuation and the combination of the first amplitude and the compensation value of the first attenuation.4. The control device according to claim 1 , whereinthe output circuit includes:a ...

SYSTEM AND METHOD FOR CANCELLING STRONG SIGNALS FROM COMBINED WEAK AND STRONG SIGNALS IN COMMUNICATIONS SYSTEMS

A receiver for cancelling strong signals from combined weak and strong signals includes: a first circuitry for inputting a weak and strong signal as an input; a parametric cancellation circuit for inputting a representation of the strong signal and an output of the first circuitry to produce a cancellation signal; a second circuitry electrically coupled to the parametric cancellation circuit for inputting the cancellation signal to produce a modulated output; a demodulator electronically coupled to the second circuitry for demodulating the modulated output to produce a demodulated output and an error signal, where the demodulated output is the data contained in the weak signal; and an adaptation logic circuit for inputting the representation of the strong signal, the demodulated output and the error signal to adaptively produce parameters for the parametric cancellation circuit. The parametric cancellation circuit further inputs the error signal and the parameters to produce the cancellation signal. 1. A receiver for cancelling strong signals from combined weak and strong signals comprising:a first circuitry for inputting a weak and strong signal as an input;a parametric cancellation circuit for inputting a representation of the strong signal and an output of the first circuitry to produce a cancellation signal;a second circuitry electrically coupled to the parametric cancellation circuit for inputting the cancellation signal to produce a modulated output;a demodulator electronically coupled to the second circuitry for demodulating the modulated output to produce a demodulated output and an error signal, wherein the demodulated output is the data contained in the weak signal; and 'the parametric cancellation circuit further inputs the error signal and the parameters to produce the cancellation signal.', 'an adaptation logic circuit for inputting the representation of the strong signal, the demodulated output and the error signal to adaptively produce parameters for ...

RECEIVER WITH SELECTABLE DIGITAL EQUALIZATION FILTER OPTIONS

A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths. 1. A device , comprising: analog front-end circuitry; and', 'a digital signal processing (DSP) circuit, wherein the DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform equalization operations based on the selected filter option, and wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths., 'a receiver having2. The device of claim 1 , wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on an automatic gain control index value and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.3. The device of claim 1 , wherein the plurality of DEQ filter options are based on an odd tap symmetric finite impulse response (FIR) filter with selectable coefficients.4. The device of claim 1 , wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a sweeping operation that determines which of a plurality of different sets of DEQ filter coefficients optimizes a performance metric.5. The device of claim 1 , wherein the performance metric is at least one of a decision feedback equalizer (DFE) coefficient metric claim 1 , a mean-square-error (MSE) noise metric claim 1 , and a pre-cursor value.6. The device of ...

Decision Feedback Equalizer

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

OPTICAL DOMAIN EQUALIZATION FOR COHERENT OPTICAL RECEIVERS

An optical coherent receiver includes an optical hybrid (OH) configured to mix signal and reference light, and two back-end optical ports. An optical equalizing network interconnects two 180° OH output ports with the two back-end optical ports so that each back-end optical port receives light from each of the two OH output ports. Optical signals from each of the two back-end optical ports are converted to electrical signals that are fed to a differential amplifier. Adjusting coupling ratios and/or optical delays in the optical equalizing network reduces an OSNR penalty of a lower-bandwidth differential amplifier. 120-. (canceled)21. An optical coherent receiver comprising:first and second back-end optical ports;an optical hybrid (OH) comprising a first input OH port, a second input OH port, a first output OH port, and a second output OH port; and,an optical equalizer network optically interconnecting each of the first and second output OH ports with each of the first and second back-end optical ports.22. The optical coherent receiver of claim 21 , wherein the OH is configured to direct light received in the first input OH port and light received in the second input OH ports into each of the first and second output OH ports with a relative phase shift that increments by 180° from the first output OH ports to the second output OH port.23. The optical coherent receiver of claim 22 , wherein the optical equalizer network is configured so that in operation light received at each of the first and second back-end optical ports from one of the first and second output OH ports is delayed by a time delay τ relative to light received from the other of the first and second output OH ports.24. The optical coherent receiver of wherein the optical equalizer network comprises a first optical delay element disposed in an optical path between the first output OH port and one of the first and second back-end optical ports claim 23 , and a second optical time delay element disposed in ...

Wireless vehicular communications involving retransmission of messages

Embodiments are directed to methods and apparatuses for wireless vehicular communications involving retransmission of messages. A method for communicating by vehicular communications circuitry of a device includes, in a wireless communications network in which a message is broadcasted by vehicular communications circuitry of a device for asynchronous receptions by other circuitry in one or more devices configured to wirelessly communicate according to a communications protocol, monitoring a channel busy ratio associated with channels in a designated range of frequency pertaining to the wireless communications network. The method further includes assessing whether to retransmit the message as a function of the channel busy ratio, and in response to the channel busy ratio being outside a threshold, retransmitting the message according to the communications protocol.

ELECTRIC SIGNAL TRANSMISSION APPARATUS

A decision feedback equalizer of an electric signal transmission apparatus has an average peak value determiner that receives an output of an adder and a threshold value set by a program. An average peak value of the output of the adder), compares a magnitude relation of the detected average peak value and the threshold value, increases the reference value of the output of a reference value generation circuit from an initial value set by the program and causes resolutions of DACs to become coarse from the initial value, when the average peak value is larger than the threshold value, and decreases the reference value of the output of the reference value generation circuit from the initial value set by the program and causes the resolutions of the DACs to become fine from the initial value, when the average peak value is smaller than the threshold value. 1. An electric signal transmission apparatus having a decision feedback equalizer ,wherein the decision feedback equalizer hasan adder that receives a reception signal and adds taps of filters to the reception signal,a comparator that determines the positive/negative of an output of the adder and outputs a determination result,a shift register that delays an output of the comparator by the integral multiple of a cycle of an input clock,a reference circuit that switches a reference value of an output according to an input control signal,digital-to-analog converters that execute digital-to-analog conversion on tap coefficients of the filters,multipliers that output the taps of the filters obtained by multiplying outputs of the digital-to-analog converters and an output of the shift register to the adder,a filter coefficient adjuster that receives the output of the adder, the output of the comparator, and the output of the shift register, outputs the tap coefficients of the filters to the digital-to-analog converters, and adjusts the tap coefficients of the filters by a feedback loop, andan average peak value determiner ...

High-speed receiver architecture

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

SYNCHRONIZATION OF ADAPTIVE FILTER SWITCHING AND CHANNEL EQUALIZATION IN FULL DUPLEX (FDX) CABLE MODEMS

Synchronizing methods and architectures for cable modems to transmit and receive Full Duplex (FDX) resource block allocations (RBAs) using filter switching and coordinated updating of equalization coefficients. A cable modem including a block of switchable filters, an analog front end (AFE) and a PHY/MAC System on a Chip (SoC) tuner to, at least in part, provide signals to switch the switchable filters in accordance with the RBA changes and synchronize updating tuner equalizations to match filter switching in a coordinated manner by marking received data at the AFE. 1. In a cable modem having an analog front end (AFE) , a PHY and MAC , that operates in full duplex (FDX) mode , and having a switchable filter block and variable equalizer coefficients in the PHY , a processor configured to:receive a command by the medium access control (MAC) from the cable modem; andtrigger the MAC to send a filter switch control signal to the analog front end based on the received command to;cause the AFE, in response to the filter switch control signal, to switch a filter path and insert a filter switching mark in one or more samples received; andcause the PHY to change its variable equalizer coefficients to reflect current calibration data for the switched filter path in substantial synchronization with receiving samples including the filter switching mark from the AFE.2. The processor of wherein the received command comprises a resource block allocation (RBA) change from a cable modem termination system (CMTS).3. The processor of wherein the cable modem is a data over cable service interface specification (DOCSIS) 3.1 FDX compliant modem.4. The processor of wherein the filter switching mark is inserted with the one or more samples received and passed from the AFE to the PHY via a high speed serial interface framing structure.5. The processor of wherein the filter switching mark includes a filter configuration identifier corresponding to the switched filter path and an offset of the ...

EQUALIZER ADJUSTING DEVICE, EQUALIZER ADJUSTING METHOD, RECEIVER, AND SIGNAL TRANSMITTING AND RECEIVING SYSTEM

An equalizer adjusting device includes a comparator, an inequality counter, an adjuster, and the like. The comparator performs magnitude comparison between a voltage value Vout of each bit output from an equalizer and a threshold value MonLVL and outputs a logical value MonSMP according to a result of the comparison. The inequality counter inputs a logical value DatSMP output from a sampler in accordance with the result of magnitude comparison between the voltage value Vout of each bit and a reference value, and the logical value MonSMP output from the comparator and counts events in which the logical value DatSMP and the logical value MonSMP differ from each other, every period. The adjuster adjusts a gain of the equalizer and the threshold value MonLVL of the comparator based on a counted value of the inequality counter. 1. An equalizer adjusting device adjusting a gain of an equalizer that adjusts frequency characteristics of an input data array and outputs the adjusted data array to a sampler , the device comprising:a comparator which outputs a logical value according to a result of magnitude comparison between a voltage value of a bit and a threshold value for each bit of the data array output from the equalizer;an inequality counter which counts events in which a logical value output from the sampler in accordance with the result of magnitude comparison between the voltage value of the bit and a reference value, and the logical value output from the comparator differ from each other, every period for each bit of the data array output from the equalizer; andan adjuster which adjusts the threshold value in the comparator in a direction in which a difference between the threshold value and the reference value in the sampler increases when a counted value of the inequality counter is zero, and adjusts the gain of the equalizer when the counted value of the inequality counter is not zero,wherein a counting operation of the inequality counter and an adjusting ...

Pam data communication with reflection cancellation

The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well.

METHODS AND SYSTEMS FOR HIGH BANDWIDTH COMMUNICATIONS INTERFACE

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code. 1. An apparatus comprising:a pair of ground planes arranged in parallel;a dielectric medium disposed in between the pair of ground planes; anda set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors comprising (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.2. The apparatus of claim 1 , further comprising conductive vias connecting the pair of ground planes.3. The apparatus of claim 1 , wherein signal conductors in the first and second pairs of signal conductors are equidistant from each other.4. The apparatus of claim 1 , wherein the first pair of signal conductors has a periodic offset along a length of the dielectric medium with respect to the second pair of signal conductors.5. The apparatus of claim 1 , wherein the vector signaling code comprises all permutations of {+1 claim 1 , −⅓ claim 1 , −⅓ claim 1 , −⅓} and {−1 claim 1 , ⅓ claim 1 , ⅓ claim 1 , ⅓}.6. A method comprisingobtaining a plurality of signals via a ...

RADIO FREQUENCY IMPAIRMENTS COMPENSATOR FOR BROADBAND QUADRATURE-CONVERSION ARCHITECTURES

A Radio Frequency Impairments (RFI) compensator and a process to remove RFI is disclosed. The RFI compensator including: a conjugator to conjugate a signal {tilde over (x)}[n] to provide a signal {tilde over (x)}*[n]; and a filter to apply coefficients that equalize a linear distortion of the signal {tilde over (x)}[n] and reject an interfering image of the signal {tilde over (x)}*[n]. The signal {tilde over (x)}[n] maybe a single wideband carrier or may include multiple carriers at different carrier frequencies. 1. A Radio Frequency Impairments (RFI) compensator comprising:a conjugator to conjugate a signal {tilde over (x)}[n] to provide a signal {tilde over (x)}*[n]; anda filter to apply coefficients that equalize a linear distortion of the signal {tilde over (x)}[n], and reject an interfering image of the signal {tilde over (x)}*[n],{'sub': 1', 'N, 'wherein the signal {tilde over (x)}[n] comprises a multi-carrier signal comprising N signals having carrier frequencies fto f, and N is greater than 1.'}2. The RFI compensator of claim 1 , wherein the filter comprises N filters and each of the N filters applies coefficients associated with a respective one of the carrier frequencies fto f.3. The RFI compensator of claim 1 , further comprising N complex mixers and N adders claim 1 ,{'sub': 1', 'N, 'wherein each of N adders adds a DC offset β associated with a respective one of the carrier frequencies fto ffrom an output of a respective one of the N filters, and'}{'sup': j2π{circumflex over (δ)}', {'sub2': 'f'}, '·nT', {'sub2': 's'}], 'sub': 1', 'N, 'each of the N complex mixers removes an estimated frequency error eassociated with a respective one of the carrier frequencies fto ffrom an output of a respective one the N adders.'}4. The RFI compensator of claim 1 , further comprising:a known signal {tilde over (z)}[n]; and{'sub': 1', 'N, 'N coefficient calculators to calculate N coefficients for each of N filters based on the known signal {tilde over (z)}[n] and a ...

Systems and Methods for Back Channel Adaptation in a Serial Transfer

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for clock recovery in a data receiver.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value. 1. (canceled)2. A method of compensating for inter-symbol interference (ISI) in a received data signal , comprising:sampling the data signal, the data signal exhibiting a single-bit response with a data cursor d representing a first ISI component and an edge cursor e exhibiting a second ISI component;{'sub': DATA', 'EDGE, 'determining a data equalizer coefficient value αbased on a determined edge equalizer coefficient value αthat corresponds to the edge cursor e; and'}{'sub': 'DATA', 'applying the determined data equalizer coefficient value αto compensate for the first ISI component of the ISI.'}3. The method according to claim 2 , wherein the determining comprises adaptively updating the edge equalizer coefficient value αduring operation.4. The method according to claim 2 , wherein the sampling comprises sampling the data signal with multiple edge samplers to generate multiple edge-sampled outputs.5. The method according to claim 4 , further comprising selecting from among the multiple edge-sampled outputs based on a detected data bit pattern.6. The method according to claim 2 , wherein the applying the determined data equalizer coefficient value αincludes:applying respective determined data equalizer coefficients along parallel alternative decision paths; ...

Signal receiving device for Ethernet and control method thereof

This invention discloses a signal receiving device for Ethernet and a control method thereof. The signal receiving device includes a gain control circuit, an alien near-end crosstalk canceller, a noise canceller, and a DFE. The gain control circuit adjusts an input signal of the signal receiving device according to a setting parameter. The alien near-end crosstalk canceller cancels an alien near-end crosstalk interference. The noise canceller uses a first filter to cancel noises. The DFE uses a second filter to cancel an inter-symbol interference of the input signal. The method includes steps of: temporarily stopping the gain control circuit from updating the setting parameter before a seed collision occurs, and temporarily stopping one of the noise canceller and the decision feedback canceller from updating the first filter coefficient of the first filter or the second filter coefficient of the second filter temporarily during the seed collision. 1. A signal receiving device installed at a target channel of a target port for receiving an input signal , comprising:a gain control circuit for adjusting the input signal according to a setting parameter;an alien NEXT canceller for cancelling an alien NEXT interference from a port adjacent to the target port;a noise canceller using a first filter to cancel a noise interference of the target channel, wherein a first filter coefficient of the first filter is updated according to the setting parameter;a DFE using a second filter to cancel an inter-symbol interference of the input signal, wherein the second filter has a second filter coefficient; anda control circuit, coupled to the gain control circuit, the alien NEXT canceller, the noise canceller and the DFE, for temporarily stopping the gain control circuit from updating the setting parameter prior to a seed collision and temporarily stopping one of the noise canceller and the DFE from updating the first filter coefficient or the second filter coefficient during the seed ...

EQUALIZER WITH PERTURBATION EFFECT BASED ADAPTATION

Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature. 1. An equalizer that comprises:a discrete-time, finite impulse response (“FIR”) filter to convert an input signal to a filtered signal;a decision element to determine channel symbols represented by the filtered signal;an error module to measure equalization error relative to the represented channel symbols, and to derive residual intersymbol interference (“ISI”) estimates for multiple offsets between the equalization error and the represented channel symbols; andan adaptation module to perturb tap coefficients of the filter to measure a perturbed residual ISI from each of the tap coefficients for each of the multiple offsets.2. The equalizer of claim 1 , wherein the adaption module uses the perturbed residual ISI to estimate an error gradient for each of the tap coefficients.3. The equalizer of claim 2 , wherein the adaptation module interpolates between the estimated error gradient and a precalculated perturbation effect based update.4. The equalizer of claim 1 , wherein the adaptation module uses the perturbed residual ISI to form a residual ISI difference matrix.5. The equalizer of claim 4 , wherein the adaptation module combines the residual ISI difference matrix with a precalculated ...

APPARATUS HAVING A DATA RECEIVER WITH A REAL TIME CLOCK DECODING DECISION FEEDBACK EQUALIZER

Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed. 1. A clocked receiver comprising:a first set of two or more data latches coupled to receive an analog input data signal and to receive multiple analog reference voltages, with each data latch of the first set coupled to receive an analog reference voltage of the multiple analog reference voltages different from an analog reference voltage of the multiple analog reference voltages received by other data latches of the first set; anda second set of two or more data latches coupled to receive the analog input data signal and the multiple analog reference voltages received by the first set, with each data latch of the second set coupled to receive an analog reference voltage of the multiple analog reference voltages different from an analog reference voltage of the multiple analog reference voltages received by other data latches of the second set; anda decoder structured to provide enable signals to the first set to activate only one data latch of the first set corresponding to one analog reference voltage of the reference voltages based at least on a value of a previous bit from one of the data latches of the ...

Wireless backhaul

In the subject system, a receiver includes a feed forward circuit, a phase recovery circuit, and a feedback circuit. The feed forward circuit compensates for near reflections and provides an input to the phase recovery circuit and the feedback circuit. The phase recovery circuit performs phase recovery and provides phase recovery information to the feedback circuit. The feedback circuit adjusts and/or corrects a received symbol based at least in part on the received phase recovery information.

METHODS AND SYSTEMS FOR PROVIDING MULTI-STAGE DISTRIBUTED DECISION FEEDBACK EQUALIZATION

Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock. 1. A method comprising:setting a differential output of a multi-input summation latch in a pre-charged state by pre-charging two or more sets of nodes connected to respective sets of input field effect transistors (FETs) of the multi-input summation latch, the two or more sets of nodes comprising (i) a set of data signal nodes connected to a first set of input FETs of the respective sets of input FETs and (ii) a set of decision feedback equalization (DFE) correction nodes connected to a second set of input FETs of the respective sets of input FETs;in response to a sampling clock, generating an integrated differential data voltage signal at the first set of input FETs of the multi-input summation latch by discharging the set of data signal nodes according to a respective set of FETs of a discrete time integration stage receiving a differential input voltage signal and generating an integrated aggregate differential DFE correction voltage signal at the second set of input FETs of the multi-input summation latch by discharging the set of DFE correction nodes according to a respective set of FETs of the discrete time integration stage receiving a ...

METHODS, SYSTEMS AND APPARATUS FOR HYBRID SIGNAL PROCESSING FOR PULSE AMPLITUDE MODULATION

A method to implement hybrid signal processing includes steps for receiving an analog signal at a receiver frontend, sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend. Then, processing the plurality of analog sampled signals using interleaved feed-forward equalizers (FFEs) to provide FFE interleaved sampled signal values corresponding to each of the sampling circuitries. Then, processing the analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain DFE interleaved sampled signal values, summing each of the FFE interleaved sampled signal values with output from one of the DFE interleaved sampled signal values to provide equalizer output signal values, and digitizing the equalizer output signal values to provide digital data bits corresponding to each of the equalizer output signal values. Implementations of the method as a hybrid communication system, system-on-a-chip, and computer readable memory are also disclosed. 1. A method to implement hybrid signal processing , the method comprising:receiving an analog signal at a receiver frontend;sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend;processing the plurality of analog sampled signals at a plurality of interleaved feed-forward equalizers (FFEs) to provide a plurality of FFE interleaved sampled signal values corresponding to each of the plurality of the sampling circuitries;processing the plurality of analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain a plurality of DFE interleaved sampled signal values;summing each of the FFE interleaved sampled signal values with a corresponding output from one of the DFE interleaved sampled signal values to provide a plurality of equalizer output signal values; anddigitizing the plurality of equalizer output signals to provide ...

Interference Cancellation in Microwave Backhaul Systems

A first microwave backhaul assembly comprises a first antenna, a front-end circuit, an inter-backhaul-assembly interface circuit, and an interference cancellation circuit. The first antenna is operable to receive a first microwave signal. The front-end circuit is operable to convert the first microwave signal to a lower-frequency digital signal, wherein the lower-frequency digital signal has energy of a second microwave signal and energy of a third microwave signal. The inter-backhaul-assembly interface circuit is operable to receive information from a second microwave backhaul assembly. The interference cancellation circuit is operable to use the information received via the inter-backhaul-assembly interface circuit during processing of the lower-frequency digital signal to remove, from the first microwave signal, the energy of the third microwave signal. The information received via the inter-backhaul-assembly interface may comprise a signal having energy of the second microwave signal. 1. A system comprising:a first receiver operable to output a digital signal comprising a desired signal with interference;an interface operable to receive information from a second receiver; andan interference cancellation circuit operable to use the information received via the interface to reduce the interference.2. The system of claim 1 , wherein the information received via the interface comprises a signal having energy at the frequency of the desired signal.3. The system of claim 1 , wherein the information received via the interface comprises a signal having energy at the frequency of the interference.4. The system of claim 1 , wherein the information received via the interface comprises an indication of an amount of energy of the interference received by the second receiver.5. The system of claim 1 , wherein:the desired signal is destined for the first receiver; andthe interference is related to a signal destined for the second receiver.6. The system of claim 1 , wherein one ...

ADAPTIVE EQUALIZER, ADAPTIVE EQUALIZATION METHOD AND RECEIVER

An adaptive equalizer, an adaptive equalization method and receiver are disclosed where the adaptive equalizer is used for performing adaptive equalization processing on a frequency-domain signal, a channel used by the frequency-domain signal containing multiple subcarriers, the adaptive equalizer comprises: an equalizer coefficient generating unit configured to, for each subcarrier, generate an equalizer coefficient to which the subcarrier corresponds according to channel information and a step length of the subcarrier; where different subcarriers correspond to different step lengths and an equalization processing unit configured to, for each subcarrier, perform equalization processing on a signal in the subcarrier by using the equalizer coefficient. 1. An adaptive equalizer , used to perform adaptive equalization processing on a frequency-domain signal with a channel used by the frequency-domain signal containing multiple subcarriers , the adaptive equalizer comprising:an equalizer coefficient generating unit configured to, for each subcarrier, generate an equalizer coefficient to which the subcarrier corresponds according to channel information and a step length of the subcarrier where different subcarriers correspond to different step lengths; andan equalization processing unit configured to, for each subcarrier, perform equalization processing on a subcarrier signal in the subcarrier by using the equalizer coefficient.2. The adaptive equalizer according to claim 1 , wherein the equalizer coefficient generating unit comprises:a first equalizer coefficient generating unit configured to generate an initial equalizer coefficient to which the subcarrier corresponds according to the channel information of the subcarrier, for use in performing initial equalization processing on the subcarrier signal in the subcarrier; anda second equalizer coefficient generating unit configured to, according to a current equalizer coefficient used in this current equalization ...

CO-CHANNEL SPATIAL SEPARATION USING MATCHED DOPPLER FILTERING

Systems () and methods for co-channel separation of communication signals. The methods involve: simultaneously receiving a plurality of communication signals transmitted at disparate relative Doppler frequencies from different locations within a multi-access system; performing matched filtering operations to pre-process each of the plurality of communication signals so as to generate pre-processed digitized samples using a priori information contained in pre-ambles () of messages present within the plurality of communication signals; using estimated signal parameters to detect the plurality of communication signals from the pre-processed digitized samples; and demodulating the plurality of communication signals without using a Viterbi decoder. 1. A method for co-channel separation of communication signals , comprising:simultaneously receiving a plurality of communication signals transmitted at disparate relative Doppler frequencies from different locations within a multi-access system;performing matched filtering operations to pre-process each of the plurality of communication signals so as to generate pre-processed digitized samples using a priori information contained in pre-ambles of messages present within the plurality of communication signals;using estimated signal parameters to detect the plurality of communication signals from the pre-processed digitized samples; anddemodulating the plurality of communication signals using a Reduced State Sequence Estimation (“RSSE”) demodulation technique.2. The method according to claim 1 , wherein the plurality of pre-processed digitized samples are generated by estimating at least one of the following signal parameters: a signal's Time Of Arrival (“TOA”); a Doppler frequency; a phase; and a Signal-to-Noise Ratio (“SNR”).3. The method according to claim 1 , wherein the estimated signal parameters are determined using the a priori information contained in the pre-ambles of the messages.4. The method according to claim 1 , ...

JITTER AND EYE CONTOUR AT BER MEASUREMENTS AFTER DFE

A method of employing a Decision Feedback Equalizer (DFE) in a test and measurement system. The method includes obtaining an input signal data associated with an input signal suffering from inter-symbol interference (ISI). A bit sequence encoded in the input signal data is determined to support assigning portions of the input signal data into sets based on the corresponding bit sequences. The DFE is applied to each set by employing a DFE slicer pattern corresponding to each set, which results in obtaining a DFE adjusted waveform histogram/PDF/waveform database graph for each set adjusted for ISI and accurately captures jitter suppression. The DFE adjusted waveform histogram/PDF/waveform database graphs are normalized and combined into a final histogram/PDF/waveform database graph for determining an eye contour of an eye diagram and jitter measurements. 1. A test and measurement system comprising:an input port structured to receive an input signal via a channel suffering from inter-symbol interference (ISI); and determine bit sequences encoded in the input signal;', 'assign portions of the input signal into sets based on the corresponding bit sequences;', 'apply a Decision Feedback Equalizer (DFE) to graphs for each set by employing a DFE slicer pattern corresponding to each set in order to obtain DFE adjusted graphs that accurately capture jitter suppression; and', 'normalize and combine the DFE adjusted graphs., 'a processor configured to2. The test and measurement system of claim 1 , in which the processor is further configured to select a number of the sets based on a number of DFE taps employed in the DFE.3. The test and measurement system of claim 2 , in which the number of sets is selected as 2where N is the number of DFE taps employed in the DFE.4. The test and measurement system of claim 1 , in which the processor is further configured to generate a histogram for each set prior to applying the DFE claim 1 , such that the DFE adjusted graphs include set ...

RECEIVER WITH ENHANCED ISI MITIGATION

A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI. 1. A device having a signaling pad to receive an input signal , the device comprising:a transversal filter to receive the input signal from the signaling pad and generate an intermediate signal;a circuit to equalize and sample the intermediate signal, and to thereby generate a digital output.2. The device of where the transversal filter includes at least one pre-cursor tap.3. The device of where the transversal filter is formed by at least one electrostatic discharge (ESD) structure.4. The device of where the transversal filter includes at least one post-cursor tap.5. The device of where the circuit includes a sampler circuit and a linear equalizer claim 1 , the linear equalizer coupled to the transversal filter to receive the intermediate signal claim 1 , the sampler circuit coupled to the linear equalizer to receive an output of the linear equalizer and generate the digital output therefrom.6. The device of where the circuit includes a sampling phase offset circuit claim 5 , to shift a sampling phase used by the sampler circuit to sample at a data eye point less subject to precursor intersymbol interference (ISI).7. The device of where the circuit includes a sampling phase offset circuit claim 5 , to shift a sampling phase used by the sampler circuit away from a point of maximum voltage margin to sample at a data eye point less subject to precursor intersymbol interference (ISI).8. The device of further comprising a decision feedback equalizer (DFE) circuit to adjust at least one of sampling or the intermediate signal to compensate for a previously-resolved digital symbol.9. The device of where the circuit includes a ...

Reception device, reception signal processing method, control circuit, and recording medium

A reception device includes an equalization processing unit including a linear filter unit and a nonlinear filter unit and performing equalization process on a reception signal; a linear propagation channel estimation unit making propagation channel estimation using a known signal included in a reception signal to calculate a filter coefficient of the linear filter unit; and a synchronization processing unit performing synchronization process of correcting frequency deviation based on a signal output by the equalization processing unit, and when a predetermined condition is satisfied after executing first equalization process of outputting a reception signal filtered by the linear filter unit to the synchronization processing unit, the equalization processing unit starts second equalization process that is an adaptive equalization process of outputting a result of addition of a reception signal filtered by the linear filter unit and a reception signal filtered by the nonlinear filter unit to the synchronization processing unit.

EMISSION CONTROL FOR RECEIVER OPERATING OVER UTP CABLES IN AUTOMOTIVE ENVIRONMENT

A transceiver system includes a transmitter circuit having a line driver with a programmable signal level to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable. The transceiver system further includes a physical layer (PHY) receiver. The PHY receiver includes a high-pass filter (HPF), an adaptive feed-forward equalizer (FFE) block and a noise aware adaptation block. The HPF rejects transient noise of a received signal, and the FFE block receives a digital signal and adaptively filters out narrowband continuous wave (CW) noise using an adaptation signal. The digital signal is based on the received signal, and the noise aware adaptation block receives an error signal and generates the adaptation signal. The error signal is generated based on an equalized signal of the FFE block and an estimated signal. The combined transmit and receive circuitry allow lowering emission while rejecting strong receiver automotive noises. 1. A transceiver system comprising:a transmitter circuit including a line driver configurable to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable; and a high-pass filter (HPF) configured to reject transient noise of a received signal;', 'a noise aware adaptation block configured to receive an error signal and to generate an adaptation signal;', 'an error shaping block configured to shape the error signal to generate a shaped error signal; and', 'an adaptive feed-forward equalizer (FFE) block configured to receive a digital signal and to adaptively filter out narrowband continuous wave (CW) noise using the adaptation signal, the digital signal being based on the received signal,', 'wherein the error signal is generated based on an equalized signal of the FFE block and an estimated signal., 'a physical layer (PHY) receiver, wherein the PHY receiver comprises2. (canceled)3. The transceiver system of claim 1 , wherein the PHY ...

Apparatuses and methodologies for decision feedback equalization using particle swarm optimization

Methods and apparatuses are provided for channel equalization in a communication system. The method includes initializing, using processing circuitry, filter coefficients of an adaptive decision feedback equalizer randomly in a predetermined search space. Further, the method includes updating, using the processing circuitry, the filter coefficients. The filter coefficients are updated using a least mean square recursion when the filter coefficients are stagnant. The filter coefficients are updated using a particle swarm optimization procedure when the filter coefficients are not stagnant. Further, the updating step is repeated until a predetermined stopping criteria is met. Further, the method includes, filtering, using the processing circuitry, a received signal using the filter coefficients.

USING DECISION FEEDBACK PHASE ERROR CORRECTION

Methods and systems are provided for using error related feedback during signal processing. During handling of an input signal, each of a plurality of sub-carriers in the input signal is processed, and error-related information for each one of the plurality of sub-carriers is determined based on the processing. Aggregate error-related information is generated based on error-related information of each of one of the plurality of sub-carriers, and subsequent processing of at least one of the sub-carriers is adjusted based on the aggregate error-related information. The error-related information may comprise phase error-related information. Adjustments to subsequent processing of one or more of the sub-carriers may be determined based on processing-related information corresponding to different stages during processing of each of the plurality of sub-carriers. 120-. (canceled)21. A system , comprising: process each of a plurality of sub-carriers in an input signal; and', 'determine, based on the processing, error-related information for each one of the plurality of sub-carriers; and, 'one or more processing circuits operable to generate aggregate error-related information based on error-related information of each of one of the plurality of sub-carriers; and', 'adjust subsequent processing of at least one of the plurality of sub-carriers based on the aggregate error-related information., 'an aggregate error circuit operable to22. The system of claim 21 , wherein the error-related information comprises phase error-related information.23. The system of claim 21 , wherein the error-related information comprises information corresponding to hard or soft decisions on each symbol made during processing each of a plurality of sub-carriers.24. The system of claim 21 , wherein the error-related information comprises information corresponding to error-corrected decisions on each symbol made during processing each of a plurality of sub-carriers.25. The system of claim 21 , ...

DeSerializer DC Offset Adaptation Based On Decision Feedback Equalizer Adaptation

An apparatus for processing data includes a decision feedback equalizer configured to sample an analog signal to yield digital data and a DC offset adaptation circuit. The decision feedback equalizer is configured to sample the equalized signal using at least one data latch at a first data latch threshold value and at a second data latch threshold value. The DC off set adaptation circuit is configured to calculate a DC off set in the analog signal based on the first data latch threshold value and on the second data latch threshold value.

Systems, Circuits and Methods for Adapting Parameters of a Linear Equalizer in a Receiver

A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized. 120-. (canceled)21. A receiver comprising:a decision feedback equalizer comprising a coefficient; anda logic module configured to adapt the coefficient of the decision feedback equalizer based on decisions generated by the decision feedback equalizer until a bit-error rate is minimized.22. The receiver of claim 21 , wherein the decision feedback equalizer comprises:a data slicer configured to generate data decisions; andan error slicer configured to generate error decisions,wherein the decisions generated by the decision feedback equalizer comprise the data decisions and the error decisions.23. The receiver of claim 21 , wherein the logic module is further configured to calculate the bit-error rate based on the decisions generated by the decision feedback equalizer.24. The receiver of claim 21 , wherein the coefficient comprises a differential digital to analog converter.25. The receiver of claim 21 , wherein the coefficient spans half of a maximum swing of an input to the decision feedback equalizer.26. The receiver of claim 25 , wherein the decision feedback equalizer further comprises another coefficient claim 25 , which spans half the span of the coefficient.27. The receiver of claim 21 , wherein the logic module is further configured to adapt the coefficient using a steepest descent algorithm.28. The receiver of claim 21 , wherein the logic module is further configured to adapt the coefficient using a least means square algorithm.29. The ...

METHOD AND APPARATUS FOR EQUALIZING SIGNALS

A system and apparatus are disclosed for a method and apparatus for equalizing signals. An apparatus that incorporates teachings of the present disclosure may include, for example, an equalizer having a channel estimation calculator for calculating a time domain channel estimation from a baseband signal, a Fast Fourier Transform processor for translating the time domain channel estimation to a frequency domain channel estimation, a tap weight calculator for calculating a frequency domain tap weight according to the frequency domain channel estimation, an inverse Fast Fourier Transform processor for translating the frequency domain tap weight calculation to a time domain tap weight calculation, and a filter for equalizing the baseband signal according to the time domain tap weight calculation. 1. A communications device , comprising:a transceiver operating in a wideband code division multiple access high speed downlink packet access communication system;a memory that stores computer instructions; and converting a carrier signal to a baseband signal;', 'calculating a time domain channel estimation from the baseband signal;', 'translating the time domain channel estimation to produce a frequency domain channel estimation;', 'performing a frequency domain tap weight calculation according to the frequency domain channel estimation;', 'translating the frequency domain channel estimation to a time domain tap weight calculation;', 'equalizing the baseband signal according to the time domain tap weight calculation to provide an equalized signal; and', 'restoring signal integrity to the baseband signal based on the equalized signal as a restored baseband signal., 'a controller coupled to the memory and the transceiver, wherein the controller, responsive to executing the computer instructions, performs operations comprising2. The communications device of claim 1 , further comprising an audio system.3. The communications device of claim 2 , wherein the audio system is ...

Adaptive Modal PAM2/PAM4 In-Phase (I) Quadrature (Q) Phase Detector For A Receiver

A phase detector includes data detection logic for detecting data in a communication signal, amplitude detection logic for processing modulation chosen from any of a PAM2 and a PAM4 communication modality, in-phase edge detection logic for detecting in-phase edge information in the communication signal, quadrature edge detection logic for detecting quadrature edge information in the communication signal, and mixing logic for determining an amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel. 1. A phase detector , comprising:data detection logic for detecting data in a communication signal;amplitude detection logic for processing modulation of a PAM2 and a PAM4 communication modality;in-phase edge detection logic for detecting in-phase edge information in the communication signal;quadrature edge detection logic for detecting quadrature edge information in the communication signal substantially simultaneous with the detection of the in-phase edge information; andmixing logic for determining a variable amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.2. The phase detector of claim 1 , wherein the data detection logic comprises data sampler logic configured to generate a digital data signal.3. The phase detector of claim 2 , wherein the in-phase edge detection logic comprises in-phase sampler logic configured to generate a digital in-phase edge signal.4. The phase detector of claim 2 , wherein the quadrature edge detection logic comprises quadrature sampler logic configured to generate a digital quadrature edge signal.5. The phase detector of claim 2 , wherein the mixing logic determines an amount of in-phase edge information and quadrature edge information to be applied based on channel loss.6. The phase detector of claim 5 , wherein the channel loss is determined by bit ...

SYMBOL AND TIMING RECOVERY APPARATUS AND RELATED METHODS

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output. 1. An apparatus comprising:a feed forward equalizer (FFE) with a FFE output;adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output;a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output;a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input; anda timing error detector (TED) with a first TED input coupled to the MUX output.2. The apparatus of claim 1 , wherein the adder circuitry has a second adder output claim 1 , the DFE has a DFE input claim 1 , the TED has a second TED input claim 1 , and further including slicer circuitry with a slicer input claim 1 , a first slicer output claim 1 , and a second slicer output claim 1 , the slicer input coupled to the second adder output claim 1 , the first slicer output coupled to the DFE input claim 1 , the second slicer output coupled to the second TED input.3. The apparatus of claim 1 , wherein the MUX is a first MUX claim 1 , the MUX output is a first MUX output claim 1 , the DFE has a first DFE output and a second DFE output claim 1 , and the TED includes:a second MUX with a third MUX input, a fourth MUX input, a fifth MUX input, a second MUX output, the third MUX input coupled to the first DFE output, the fourth MUX ...

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

METHOD FOR PERFORMING DATA SAMPLING CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS

A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver. 1. A method for performing data sampling control in an electronic device , the method comprising the steps of:detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; andwhen the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver, wherein the phase shift clock is a derivative of the normal clock.2. The method of claim 1 , wherein a phase difference between a phase of a data sampler clock of a data sampler in the DFE receiver and that of the normal clock is a constant; and ...

Two-dimensional (2D) decision feedback equalizer (DFE) slicer within communication systems

A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. For example, the device's processor receives one or more signals from a communication channel. The processor then processes the one or more signals to generate 2D DFE soft slicer outputs and to decode the one or more signals based on the 2D DFE soft slicer outputs to generate estimates of information encoded within the one or more signals. The processor may process the 2D DFE soft slicer outputs to generate 2D DFE hard decisions and then generates other estimates of the information encoded based on the 2D DFE hard decisions. 1. A communication device comprising: receive a plurality of signals from a communication channel;', 'process the plurality of signals to generate a plurality of two-dimensional (2D) decision feedback equalizer (DFE) soft slicer outputs; and', 'decode the plurality of signals based on the plurality of 2D DFE soft slicer outputs to generate estimates of information encoded within the plurality of signals., 'a processor configured to2. The communication device of claim 1 , wherein the processor is further configured to:process the plurality of signals using a 2D DFE to determine a plurality of 2D DFE configuration parameters; andgenerate the plurality of 2D DFE soft slicer outputs using a 2D DFE function based on the plurality of 2D DFE configuration parameters, a 2D constellation of the plurality of signals that includes a plurality of constellation points arranged respectively in predetermined locations, and a cost function that is based on at least one of noise or interference associated ...

SIGNAL PROCESSING DEVICE AND ASSOCIATED EQUALIZATION CIRCUIT AND SIGNAL PROCESSING METHOD

A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal. 1. A signal processing device for a receiver , comprising:a descrambler, descrambling an input signal to generate a descrambled signal;a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal;an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; anda decoder, decoding the equalized signal to obtain data included in the input signal.wherein the equalization module comprises:a first scrambler, scrambling the phase recovered signal to generate a scrambled phase recovered signal;an equalization circuit, performing the equalization according to the scrambled phase recovered signal to generate a scrambled equalized signal; anda first descrambler, descrambling the scrambled equalized signal to generate the equalized signal.2. The signal processing device according to claim 1 , further comprising:a frontend circuit, converting a radio-frequency signal to a baseband signal;a timing recovery circuit, performing timing recovery on the baseband signal to generate a timing recovered signal; anda frame synchronization circuit, performing frame synchronization according to the timing recovered signal to generate a frame synchronized signal;wherein, the descrambler is coupled between the frame synchronization circuit and the phase recovery circuit, and the input signal is the frame synchronized signal.3. (canceled)4. The signal processing device according to claim 1 , wherein the ...

Apparatus and method for un-delayed decision feedback with sample and hold at selected timing

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs. 1. (canceled)2. An apparatus , comprising:first sampling circuitry to sample incoming data symbols, each having a state of at least two alternative logic states, and to responsively produce a first output;second sampling circuitry to sample incoming data symbols, each having a state of at least two alternative logic states, and to responsively produce a second output;wherein the sampling by the second sampling circuitry is dependent on the first output, and the first output is directly provided to the second sampling circuitry without the use of an intervening clocked delay element;a latch to also receive the second output from the second sampling circuitry and to output data samples according to timing provided by a sampling clock; andcircuitry to select the timing provided by the sampling clock.3. The apparatus of claim 2 , wherein:the apparatus further comprises calibration circuitry, to measure timing of at least one critical timing path associated with sampling, and to responsively establish at least one value; andthe circuitry to select the timing is to select the timing in dependence on the at least one value from the calibration circuitry.4. The apparatus of claim 3 , wherein the circuitry is to intermittently re-measure the timing of the at least one critical path claim 3 , and is to responsively update the at least one value as- ...

DECISION FEEDBACK EQUALIZER AND RECEIVER CIRCUIT

A plurality of comparator circuits output results of comparing a pulse amplitude modulated input signal having four or more values with a plurality of first thresholds. A selection section decides a value of the input signal at certain timing by selecting one of the comparison results on the basis of a result of deciding a value of the input signal at previous timing. A threshold setting section generates the first thresholds from a plurality of third thresholds obtained by adding an offset value based on magnitude of inter-symbol interference corresponding to each value to one of second thresholds whose number is based on the number of values, on the basis of an average value of third thresholds greater than a second threshold or third thresholds smaller than the second threshold and an adjustment value based on the decision result and sets the first thresholds in the comparator circuits. 1. A decision feedback equalizer comprising:a plurality of comparator circuits which output comparison results of comparisons between a pulse amplitude modulated input signal with four or more values and a plurality of first thresholds;a selection section which decides a value of the input signal at first timing by selecting one of the comparison results outputted from the plurality of comparator circuits on the basis of a decision result of a value of the input signal at second timing before the first timing; anda threshold setting section which generates the plurality of first thresholds from a plurality of third thresholds obtained by adding an offset value based on a magnitude of an inter-symbol interference corresponding to each of the values to one of a plurality of second thresholds whose number is based on a number of the values, based on a first average value of the plurality of third thresholds greater than a second threshold or a second average value of the plurality of third thresholds smaller than the second threshold and an adjustment value based on the decision ...

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer;a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; anda circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.. A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising: The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities, both of which lead to inter-symbol interference (ISI). Attempts to address these ...

LOW-COMPLEXITY, HIGHLY-SPECTRALLY-EFFICIENT COMMUNICATIONS

A system may comprise circuitry that includes a sequence estimation circuit and a non-linearity modeling circuit. The circuitry may be operable to receive a single-carrier signal that was generated by passage of symbols through a partial response filter and through a non-linear circuit. The circuitry may be operable to generate estimated values of the symbols using the sequence estimation circuit and using the non-linearity modeling circuit. An output of the non-linearity modeling circuit may be equal to a corresponding input of the non-linearity modeling circuit modified according to a non-linear model that approximates the non-linearity of the non-linear circuit through which the received signal passed. 120-. (canceled)21. A method comprising: receiving a first sample of a first signal;', 'generating, by said sequence estimation circuit, a first symbol vector based on said first sample of said signal;', 'generating a partial response feedback signal based on said first symbol vector;', 'receiving a second sample of said first signal; and', 'processing said second sample of said first signal based on said partial response feedback signal., 'in a receiver comprising a sequence estimation circuit22. The method of claim 21 , wherein:said first signal is non-linearly-distorted as a result of non-linearity of said signal path;said receiver comprises a non-linearity modeling circuit; andsaid method comprises determining, via said non-linearity modeling circuit, a model of said non-linearity of said signal path.23. The method of claim 22 , wherein said model of said non-linearity of said signal path is represented as a polynomial or exponential expression.24. The method of claim 21 , wherein symbols of said symbol vector are N-QAM symbols and N is an integer.25. The method of claim 21 , wherein said generating said partial response feedback signal comprises performing the following:convolving said first symbol vector with a plurality of tap coefficients.26. The method of ...

COMPENSATION FACTOR REDUCTION IN AN UNROLLED DECISION FEEDBACK EQUALIZER

An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The Kpossible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the Kcombinations of previous history bits into R sampler selections. 1. A method of operating an unrolled Decision Feedback Equalizer (DFE) having a plurality of input samplers , the method comprising:{'sup': N', 'N, 'a) creating a reduced set of compensation factors (R) based on an original set of compensation factors (K) for the unrolled DFE, where R Подробнее

Wireless communication apparatus and one-path state determination method

A wireless communication apparatus includes a wireless unit configured to receive a radio signal; and a signal processing unit configured to detect a phase shift between a detection timing of a path relevant to the received signal at the wireless unit and a path timing of the received signal, to calculate interference power by a first path having a maximum power value based on the phase shift, to calculate power of one or more second paths other than the first path based on the interference power, and to determine whether the received signal is received in a one-path state or a multi-path state based on the power value of the first path and the power values of the one or more second paths.

SIGNAL RECEIVING DEVICE AND EQUALIZER TUNING METHOD THEREOF

A signal receiving device and an equalizer tuning method thereof are provided. A first equalizer receives an input signal and generates a first equalized signal by compensating the input signal according to a first equalization parameter. A second equalizer generates a second equalized signal by compensating the first equalized signal according to a second equalization parameter. A clock and data recovery circuit recovers the second equalized signal to generate an output signal. An equalizing controller receives the input signal and outputs a first control signal and a second control signal, to adjust the first equalization parameter according to the first control signal and adjust the second equalization parameter according to the second control signal. The equalizing controller detects a first pattern symbol and a second pattern symbol from the output signal and tunes the second equalization parameter according to the number of the first pattern symbol and the second pattern symbol. 1. A signal receiving device , comprising:a first equalizer, receiving an input signal, and generating a first equalized signal by compensating the input signal according to a first equalization parameter;a second equalizer, coupled to the first equalizer, and generating a second equalized signal by compensating the first equalized signal according to a second equalization parameter;a clock and data recovery circuit, coupled to the second equalizer, recovering the second equalized signal to generate an output signal; andan equalization controller, receiving the output signal, and outputting a first control signal and a second control signal to adjust the first equalization parameter according to the first control signal and adjust the second equalization parameter according to the second control signal,wherein the equalization controller detects a first pattern symbol and a second pattern symbol from the output signal and adjusts the second equalization parameter according to the ...

DECISION FEEDBACK EQUALIZATION PROCESSING DEVICE AND METHOD

The present application disclosed a decision feedback equalization processing device and method. The device comprises: a channel estimator for receiving an input signal, and determining, based on the input signal, an input signal autocorrelation matrix R, an input-output signal cross-correlation matrix Rand an input-output signal cross-correlation vector r; a tap coefficient calculator for receiving R, Rand r, and calculating a feed-forward equalizer (FFE) tap coefficient vector g and a feedback equalizer (FBE) tap coefficient vector f, wherein at least one of the FFE tap coefficient vector g and the FBE tap coefficient vector f is calculated using a conjugate gradient descent algorithm. The tap coefficient calculator comprises: a circulant matrix construction unit and a fast Fourier transformation (FFT) calculating unit. And the device further comprises a decision feedback equalizer for receiving from the tap coefficient calculator the FFE tap coefficient vector g and the FBE tap coefficient vector f, and performing equalization on the input signal and generating an equalized output signal. 1. A decision feedback equalization (DFE) processing device comprising:{'sub': yy', 'yx', 'yx, 'a channel estimator for receiving an input signal, and determining, based on the input signal, an input signal autocorrelation matrix R, an input-output signal cross-correlation matrix Rand an input-output signal cross-correlation vector r;'}{'sub': yy', 'yx', 'yx', 'yy', 'yx', 'yx, 'a tap coefficient calculator for receiving from the channel estimator the input signal autocorrelation matrix R, the input-output signal cross-correlation matrix Rand the input-output signal cross-correlation vector r, and calculating a feed-forward equalizer (FFE) tap coefficient vector g and a feedback equalizer (FBE) tap coefficient vector f based on the input signal autocorrelation matrix R, the input-output signal cross-correlation matrix Rand the input-output signal cross-correlation vector r, ...

Compensation of common mode voltage drop of sensing amplifier output due to decision feedback equalizer (dfe) taps

A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

TURBO RECEIVERS FOR SINGLE-INPUT SINGLE-OUTPUT UNDERWATER ACOUSTIC COMMUNICATIONS

Systems and methods for underwater communication using a SISO acoustic channel. An acoustic receiver may receive a signal comprising information encoded in at least one transmitted symbol. Using a Bi-SDFE, the at least one transmitted symbol is estimated. The Bi-SDFE may include a SDFE and a time-reversed SDFE that each output bit extrinsic LLRs, which are combined into combined bit extrinsic LLRs. The estimated symbol is then mapped to the combined bit extrinsic LLRs, the result of which is de-interleaved. Iterative bit extrinsic LLRs are generated with a MAP and/or soft-decision decoder using the mapped, combined bit extrinsic LLRs as a priori LLRs for the Bi-SDFE in another iterative estimation. The iterative bit extrinsic LLRs are interleaved and transmitted for use by the Bi-SDFE in another iterative estimation. After a plurality of iterations, a hard decision of the transmitted symbol is generated with the MAP and/or soft-decision decoder. 1. A method for underwater communication using a acoustic channel , the method comprising:(a) receiving at an acoustic receiver a signal comprising information encoded in at least one transmitted symbol;(b) estimating, using a turbo equalizer, the at least one transmitted symbol and a priori log likelihood ratios (“LLRs”), wherein the turbo equalizer comprises a SDFE and a time-reversed SDFE that each output bit extrinsic LLRs that are combined into combined bit extrinsic LLRs;(c) mapping the estimated, transmitted symbol to the combined bit extrinsic LLRs;(d) adding the estimated a priori LLRs to the combined bit extrinsic LLRs to obtain first a posteriori LLRs;(d) de-interleaving the first a posteriori LLRs;(e) generating iterative bit extrinsic LLRs with a MAP decoder;(f) adding the iterative bit extrinsic LLRs to the estimated a priori LLRs to obtain second a posteriori LLRs;(g) interleaving the second a posteriori LLRs for use by the turbo equalizer in another iterative estimation of the at least one transmitted symbol; ...

SYNCHRONIZATION OF ADAPTIVE FILTER SWITCHING AND CHANNEL EQUALIZATION IN FULL DUPLEX (FDX) CABLE MODEMS

Synchronizing methods and architectures for cable modems to transmit and receive Full Duplex (FDX) resource block allocations (RBAs) using filter switching and coordinated updating of equalization coefficients. A cable modem including a block of switchable filters, an analog front end (AFE) and a PHY/MAC System on a Chip (SoC) tuner to, at least in part, provide signals to switch the switchable filters in accordance with the RBA changes and synchronize updating tuner equalizations to match filter switching in a coordinated manner by marking received data at the AFE. 1. In a cable modem having an analog front end (AFE) , a physical layer modulator (PHY) and a medium access control circuitry (MAC) , that operates in full duplex (FDX) mode , and having a switchable filter block and variable equalizer coefficients in the PHY , a processor configured to:receive a command at the MAC from the cable modem, wherein the received command comprises a resource block allocation (RBA) change from a cable modem termination system (CMTS), wherein the RBA change comprises altering a first allocation of downstream and upstream transmission channels to a second, different allocation of downstream and upstream transmission channels, wherein altering the allocation comprises changing a channel from a downstream transmission direction to an upstream transmission direction, or vice-versa; and cause the AFE, in response to the filter switch control signal, to switch a filter path and insert a filter switching mark in one or more samples received; and', 'cause the PHY to change its variable equalizer coefficients to reflect current calibration data for the switched filter path in substantial synchronization with receiving samples including the filter switching mark from the AFE., 'trigger the MAC to send a filter switch control signal to the analog front end based on the received command to2. (canceled)3. The processor of wherein the cable modem is a data over cable service interface ...

Receiver for High Speed Communication Channel

A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal. 1. A receiver for data recovery from a channel signal of a communications channel , comprising: a plurality of comparators to generate a thermometer code based on a plurality of reference voltages and an analog signal generated from the channel signal, and', 'a code conversion circuit to convert the thermometer code into the quantized code using thermometer to binary conversion;, 'a quantization circuit to generate a quantized code corresponding to the channel signal, the quantization circuit comprisinga first decision circuit to recover, in a first signal processing mode, digital data for the channel signal based on the quantized code corresponding to the channel signal;a second decision circuit to recover, in a second signal processing mode, the digital data for the channel signal based on the quantized code corresponding to the channel signal; anda controller to select between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal,wherein in the first signal processing mode, the controller turns off at least some of the comparators of the plurality of comparators based on the parameter indicative of the signal quality of the channel signal.2. The receiver of claim 1 , wherein the ...

METHOD FOR PERFORMING LOOP UNROLLED DECISION FEEDBACK EQUALIZATION IN AN ELECTRONIC DEVICE WITH AID OF VOLTAGE FEEDFORWARD, AND ASSOCIATED APPARATUS

A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively. 1. A method for performing loop unrolled decision feedback equalization (DFE) in an electronic device , the method comprising the steps of:receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in the electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver;broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward a plurality of comparators in the DFE receiver;utilizing the plurality of comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate a plurality of comparison results; andselectively adjusting the tap control signal and the offset control signal according to the plurality of comparison results, in order to control ...

Mimo system-based signal detection method and device, and storage medium

Disclosed are a Multiple-Input Multiple-Output (MIMO) system-based signal detection method. The method includes: performing a scaling calculation on a first covariance matrix according to first main diagonal elements in the first covariance matrix to obtain a second covariance matrix; obtaining a whitening matrix according to the second covariance matrix; taking the whitening matrix, a vector of a receiving signal and a channel matrix as input parameters, and inputting the parameters into a mathematical model for a whitening operation and perform a whitening calculation to obtain an operation result; and detecting a transmit signal in a MIMO system according to the operation result to obtain a detection result. Also disclosed are a MIMO system-based signal detection device and a computer storage medium.

Optical Communication Module

An optic module for use with a host is disclosed that includes a port configured to accept an optical connector connected to fiber optic cables which carry optic signals. A receiver module is configured to receive an incoming optic signal and convert the received optic signal to a received electrical signal while a transimpedance amplifier amplifies the received electrical signal. An electrical interface is configured to electrically interface the optic module with the host thereby providing the amplified received electrical signal to a digital signal processor in the host. On the transmit side, an optic device driver receives an outgoing electrical signal from the host, after processing by a digital signal processor in the host, for amplification while a transmit module is configured to convert the outgoing electrical signal to an outgoing optic signal and transmit the outgoing optic signal on an optic fiber. 1. An optic module and host configured for data communication comprising: a housing having an interior space;', 'a port configured receive an optical connector, the optical connector attached to a fiber optic cable which carries an optic signal;', 'a receiver optic unit configured to receive and convert the optic signal to a receiver signal;', 'a transimpedance amplifier configured to amplify the receiver signal to create an amplified signal and provide an incoming signal to the host;', 'a driver configured to receive and amplify an outgoing electrical signal to be transmitted as an electrical signal, the outgoing electrical signal received from the host;', 'a transmitter optic unit configured to receive and convert the amplifier version of the outgoing electrical signal from the driver to an optic signal, the optic signal transmitted from the transmitter optic unit;, 'An optic module comprising;'} a port having an electrical interface, the port configured to receive the optic module and establish an electrical connection to the optic module;', receive and ...

PIPELINE MULTIPLEXER LOOP ARCHITECTURE FOR DECISION FEEDBACK EQUALIZER CIRCUITS

Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage for generating a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage including a multiplexer circuit for selecting at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches. 1. A decision feedback circuit comprising: a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and', 'a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches;, 'a plurality of decision feedback equalizer (DFE) branches, each DFE branch includingwhere for at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches, wherein the intermediate value is an output from a first multiplexer in the second DFE branch, where the output of the first multiplexer is an input to a second multiplexer in the multiplexer circuit of the second DFE branch.2. The decision feedback circuit of claim ...

Sequence Estimation Device and Method

A sequence estimation device includes a grouping unit, a sequence estimation unit and a combination unit. The grouping unit groups a first plurality of equalized signals into a plurality of equalized signal groups according to a grouping rule. The sequence estimation unit, coupled to the grouping unit, processes the plurality of equalized signal groups according to a sequence estimation rule to obtain a plurality of estimated signal groups, respectively. The combination unit, coupled to the sequence estimation unit, permutes the plurality of estimated signal groups to a plurality of estimated signals according to the grouping rule. 1. A sequence estimation device of a communications receiver , comprising:a grouping circuit, configured to receive a first plurality of equalized signals, and to group the first plurality of equalized signals into a plurality equalized signal groups according to a grouping rule;a sequence estimation circuit, coupled to the grouping circuit, configured to process the plurality of equalized signal groups according to a sequence estimation rule to obtain a plurality of estimated signal groups; anda combination circuit, coupled to the sequence estimation circuit, configured to permute the plurality of estimated signal groups to a plurality of estimated signals according to the grouping rule.2. The sequence estimation device according to claim 1 , wherein the grouping rule causes differences between indices of adjacent equalized signals in each of the plurality of equalized signal groups to be the same.3. The sequence estimation device according to claim 1 , wherein the sequence estimation rule is a maximum-likelihood sequence estimation (MLSE) rule.4. The sequence estimation device according to claim 3 , wherein the sequence estimation circuit performs a Viterbi algorithm to process the plurality of equalized signal groups according to the MLSE rule to obtain the plurality of estimated signal groups claim 3 , respectively.5. The sequence ...

Selectable-tap Equalizer

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. 142-. (canceled)43. An integrated circuit to couple to a signal path , the integrated circuit comprising:a receiver to receive a first sequence of symbols arriving via the signal path;a transmitter to transmit a second sequence of symbols via the signal path; andcircuitry to equalize reception of symbols of the first sequence by the receiver according to values of the second sequence of symbols.44. The integrated circuit of claim 43 , wherein the symbols of the first sequence are respective bits and wherein the symbols of the second sequence are respective bits.45. The integrated circuit of claim 43 , wherein:the integrated circuit further comprises circuitry to buffer values of the symbols of the second sequence prior to transmission; andthe circuitry is to equalize the first sequence of symbols according to ones of the values of the symbols of the second sequence which have not yet been transmitted.46. The integrated circuit of claim 43 , wherein:the integrated circuit comprises a shift register to shift symbols;the circuitry comprises at least one tap coupled to the shift register to receive therefrom a value of one of the symbols shifted by the shift register; andthe circuitry is to equalize the reception of the symbols of the first sequence according to the value of the ...

Auto-zero receiver with integrated dfe, vga and eye monitor

An apparatus includes a first half-cell, a second half-cell, a multiplexer and a decision feedback equalizer. The first input stage may be configured to present a first differential input to the first auto-zero stage and the second auto-zero stage. The second input stage may be configured to present a second differential input to the third auto-zero stage and the fourth auto-zero stage. The multiplexer may be configured to receive a first output from the first auto-zero stage, receive a second output from the third auto-zero stage and present a decision feedback input comprising one of the first output and the second output. The decision feedback equalizer may be configured to generate a feedback signal in response to the decision feedback input and present the feedback signal to the first feedback buffer and the second feedback buffer.

Fast detection/mitigation and recovery for severe emi conditions in automotive area networks

A vehicle communication network device includes a transceiver configured to communicatively couple with a remote transceiver of another vehicle communication network device via a wired media and processing circuitry coupled to the transceiver. The device detects interference on the wired media that exceeds an interference threshold level. Upon the detection, the device enters a quiet mode during which no data is transmitted on the wired media. After exiting the quiet mode, the device enters an idle mode during which known data is transmitted on the wired media and during which the device receives known data from the remote transceiver. The device retrains its transceiver based upon the known data and after retraining the transceiver, exchanges data with the remote transceiver. The device may also buffer data for transmission, upon the detection, determine buffered data that was likely corrupted by the interference, and after retraining, retransmit the determined buffered data.

INFORMATION PROCESSING SYSTEM, STORAGE DEVICE, AND CALIBRATION METHOD

An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register. 1. An information processing system , comprising:a host; anda storage device configured to transmit a first pulse signal to the host through a transmission line and receive a second pulse signal from the host through the transmission line, wherein{'claim-text': ['a first register configured to store a value of a first parameter, and', 'a first correction circuit configured to adjust a first duty ratio of the first pulse signal according to the value of the first parameter in the first register; and'], '#text': 'the storage device comprises:'}{'claim-text': ['measure a plurality the first duty ratios of the first pulse signal as output from the storage device with the value of the first parameter being set in the first register to a plurality of different values;', 'derive a first optimum value of the first parameter based on the measured first duty ratios adjusted according to the plurality of different values of the first parameter; and', 'transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.'], '#text': 'the host comprises a first calibration processor configured to:'}2. The information processing system ...

APPARATUS AND METHOD FOR CHANNEL EQUALIZATION BASED ON ERROR DETECTION

An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence. 1. An apparatus comprising:an equalization circuit configured to generate a first data sequence and a first equalized signal from an input signal received through a channel;an error prediction circuit configured to predict an error based on the first equalized signal;a sequence estimation circuit configured, when the error is predicted, to generate a second data sequence from the first data sequence and the predicted error; anda selection circuit configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.2. The apparatus of claim 1 , wherein the error prediction circuit is further configured to determine that the error is predicted when a level of the first equalized signal at a center of a unit interval (UI) is within at least one range.3. The apparatus of claim 2 , wherein the at least one range includes at least one threshold for determining a symbol value.4. (canceled)5. The apparatus of claim 1 , wherein the sequence estimation circuit includes a partial equalizer configured to generate the second data sequence by setting at least one symbol value from a non-equalized signal corresponding to the input signal.6. The apparatus ...

Apparatus, system, and method for reducing a number of intersymbol interference components to be suppressed

An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.

TURBO RECEIVERS FOR MULTIPLE-INPUT MULTIPLE-OUTPUT UNDERWATER ACOUSTIC COMMUNICATIONS

Systems and methods for underwater communication using a MIMO acoustic channel. An acoustic receiver may receive a signal comprising information encoded in at least one transmitted symbol. Using a two-layer iterative process, the at least one transmitted symbol is estimated. The first layer of the two-layer process uses iterative exchanges of soft-decisions between an adaptive turbo equalizer and a MAP decoder. The second layer of the two-layer process uses a data-reuse procedure that adapts an equalizer vector of both a feedforward filter and a serial interference cancellation filter of the adaptive turbo equalizer using a posteriori soft decisions of the at least one transmitted symbol. After a plurality of iterations, a hard decision of the bits encoded on the at least one transmitted symbol is output from the MAP decoder. 1. A method for underwater communication using a multiple-input multiple-output (“MIMO”) acoustic channel , the method comprising:receiving at an acoustic receiver a signal comprising bits of information encoded in one or more transmitted symbols, wherein the acoustic receiver includes an adaptive turbo equalizer and a MAP decoder;for each of the one or more transmitted symbols, after a two-layer iterative process is completed outputting from the MAP decoder a hard decision of the bits of information encoded in each of the one or more transmitted symbols;the two-layer iterative process includes both an iterative exchange of information between the adaptive turbo equalizer and the MAP decoder (a “Turbo Iteration”) and an iterative adaptation of both a feedforward filter and a serial interference cancellation filter of the adaptive turbo equalizer based upon a posteriori soft decisions of a respective block of the one or more transmitted symbols (a “Equalizer Iteration”); (A) equalizing the received signal with the adaptive turbo equalizer to estimate each symbol within the respective block of the one or more transmitted symbols;', '(B) sending ...

COMMUNICATION APPARATUS AND COMMUNICATION METHOD

A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal. 1. A communication apparatus , comprising:an input terminal configured to receive a time-varying data signal;an output terminal; andan interference reduction circuit coupled between the input terminal and the output terminal, the interference reduction circuit configured to acquire first partial data, at a first time, of the data signal and to generate a first level-shifted result and a second level-shifted result according to the first partial data,wherein the interference reduction circuit is further configured to acquire second partial data, at a second time, of the data signal, and to select one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and to transmit the selected result to the output terminal.2. The communication apparatus of claim 1 , wherein the interference reduction circuit comprises:a first shifter circuit configured to sum up the first partial data and a first shift, in order to generate a first level-shifted result; anda second shifter circuit configured to sum up the first partial data and a second shift, in order to generate a ...

HIGH SPEED COMMUNICATIONS SYSTEM

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols. 1. A method comprising:receiving, at a plurality of orthogonal subchannel multi-input comparators (MICs), a set of wire-specific inputs, each wire-specific input carrying a combination of a respective baseband symbol of a baseband codeword and at least one respective carrier-modulated symbol of at least one carrier-modulated codeword; andgenerating a plurality of superposition subchannel signals, each superposition subchannel signal generated by a corresponding orthogonal subchannel MIC forming a respective subchannel-specific linear combination of the set of wire-specific inputs, each superposition subchannel signal comprising a respective superposition of (i) a baseband subchannel signal and (ii) one or more carrier-modulated subchannel signals, the baseband subchannel signal and the one or more carrier-modulated subchannel signals associated with the baseband codeword and the at least one respective carrier-modulated codeword, respectively; andparsing, using a plurality of filters, each superposition subchannel signal of the plurality of superposition subchannel signals into the baseband subchannel signal and one or more temporally misaligned carrier-modulated subchannel signals, and separately sampling the baseband subchannel signal and the one or more temporally ...

Partial Response Equalizer and Related Method

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs. 1. (canceled)2. An integrated circuit (IC) , comprising:a plurality of multiplexers, each multiplexer to choose according to a selection signal between at least two different selection choices, and to responsively output one of the selection choices as an output signal;the output signal for each multiplexer directly forming the selection signal for another of the multiplexers, without any intervening clocked delay elements; andcircuitry respective to each of the multiplexers to sample the output signal from the respective multiplexer, and to provide a sampled output signal;wherein the sampled output signal from each of the multiplexers is sampled according to a selected sampling phase, the selected sampling phase established dependent on at least one programmed value.3. The IC of claim 2 , wherein the IC further comprises:calibration circuitry, to measure timing of at least one critical timing path associated with the multiplexers, and to responsively establish the at least one programmed value; anda circuit to receive the at least one programmed value from the calibration circuitry and to store the at least one programmed value.4. The IC of claim 3 , wherein the calibration circuitry is to intermittently re-measure the timing of the at least one critical path during operation of the IC claim 3 , and is to responsively update the at least ...

Unequalized clock data recovery for serial i/o receiver

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. 1. A receiver device , the device comprising: an analog demultiplexer configured to receive the input signal;', 'a plurality of ADC channels electrically coupled to the analog demultiplexer, each of the plurality of ADC channels having an input track-and-hold stage coupled to the analog demultiplexer and an ADC stage electrically coupled to the input track-and-hold stage; and', 'a digital retimer electrically coupled to the ADC stage of each of the plurality of ADC channels., 'an interleaved analog-to-digital converter (ADC) configured to generate signal samples from an input signal, the interleaved ADC including'}2. The device of wherein the analog demultiplexer is configured to demultiplex and time interleave the input signal to the plurality of ADC channels; andwherein the digital retimer is configured to retime and multiplex signals from the plurality of ADC channels into one or more higher data rate signals.3. The device of wherein each of the ADC stages of the plurality of ADC channels includes a plurality of low resolution ADC stages.4. The device of wherein each low resolution ADC stage includesa 1-bit ADC electrically coupled to an input of the ADC stage;a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit ADC;an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage;a residue amplifier electrically coupled to the analog subtractor; anda track-and ...

METHOD AND APPARATUS FOR DETERMINING A SET OF OPTIMAL COEFFICIENTS

The disclosed systems, structures, and methods are directed to a method for determining a set of N optimal coefficients to be supplied to an equalizer, the equalizer being employed in at least one of a serializer and a deserializer, the method comprising: receiving N different parameters, searching an initial set of N coefficients on an N-dimensional performance surface, in accordance with a genetic algorithm, wherein the N-dimensional performance surface corresponds to various coefficients in the N parameters, and fine tuning the initial set of N coefficients to provide the set of N optimal coefficients, in accordance with a gradient descent algorithm. 1. A method for determining a set of N optimal coefficients to be supplied to an equalizer , the equalizer being employed in at least one of a serializer and a deserializer , the method comprising:receiving N different operational parameters, each operational parameter including a plurality of coefficients; randomly selecting k sets of coefficients from the N operational parameters;', {'sub': '1', 'selecting first top sets sof coefficients from N operational parameters, in accordance with a cost function;'}, {'sub': 2', '1, 'evolving second sets sof coefficients in accordance with the first top sets sof coefficients;'}, {'sub': 3', '3', '2, 'randomly selecting other sets of coefficients in a controlled random manner and providing third sets sof coefficients, wherein the third sets sof coefficients includes the first set of coefficients Si and the second set of coefficients sand the other sets of coefficients;'}, {'sub': '4', 'randomly selecting fourth m sets sof coefficients from the N operational parameters; and'}, {'sub': 3', '4, 'providing the initial set of N coefficients in accordance with the third sets sof coefficients and the fourth sets sof coefficients; and'}], 'searching an initial set of N coefficients on an N-dimensional performance surface, in accordance with a genetic algorithm, wherein the N- ...

NON-LINEAR EQUALIZER IN COMMUNICATION RECEIVER DEVICES

Disclosed are methods, systems, devices, apparatus, media, design structures, and other implementations, including a method is that includes receiving, at a receiver device, a signal transmitted from a remote wireless device, with the signal including a training sequence, and updating, based on the training sequence, one or more adjustable characteristics for a non-linear equalizer of the receiver device, with the one or more adjustable characteristics controlling signal non-linear compensation processing to correct non-linear distortions affecting communication signals transmitted from the remote wireless device. In some embodiments, the method may further include updating, based on the training sequence, additional one or more adjustable characteristics for a linear equalizer of the receiver device, with the additional one or more adjustable characteristics controlling signal linear compensation processing to correct linear distortions affecting the communication signals. 1. A method comprising:receiving, at a receiver device, a signal transmitted from a remote wireless device, wherein the signal comprises a training sequence; andupdating, based on the training sequence, one or more adjustable characteristics for a non-linear equalizer of the receiver device, the one or more adjustable characteristics controlling signal non-linear compensation processing to correct non-linear distortions affecting communication signals transmitted from the remote wireless device.2. The method of claim 1 , further comprising:updating, based on the training sequence, additional one or more adjustable characteristics for a linear equalizer of the receiver device, the additional one or more adjustable characteristics controlling signal linear compensation processing to correct linear distortions affecting the communication signals.3. The method of claim 2 , wherein updating the additional one or more adjustable characteristics for the linear equalizer comprises:deriving channel ...

BI-LEVEL ADAPTIVE EQUALIZER

At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts. 1. A circuit , comprising:an equalizer comprising an input terminal configured to receive a data signal and an output terminal, wherein the equalizer is configured to receive an equalizer setting and generate an equalized signal according to the data signal and the equalizer setting;a comparator comprising a first input terminal coupled to the output terminal of the equalizer, a second input terminal configured to receive a plurality of threshold signals, and an output terminal at which the comparator is configured to output a comparison result indicating a result of a comparison between the equalized signal and a respective threshold signal of the plurality of threshold signals under current consideration;a counter comprising an input terminal and an output terminal and being configured to count a number of rising edges of the comparison result; and control the equalizer to apply a short conductor equalizer setting;', 'determine a relationship among counts output by the counter for multiple of the plurality of threshold signals; and', 'control the equalizer ...