RRAM CELL BOTTOM ELECTRODE FORMATION

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved. 1. A method of forming a resistive random access memory (RRAM) cell , comprising:forming a bottom electrode layer over a lower metal interconnect layer;forming a dielectric data storage layer having a variable resistance onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer; andforming a top electrode layer over the dielectric data storage layer.2. The method of claim 1 , wherein forming the bottom electrode layer comprises:performing a first atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode layer.3. The method of claim 1 , wherein forming the bottom electrode layer comprises:performing a physical vapor deposition (PVD) process to form a first bottom electrode layer; andperforming a first ALD process to form a second bottom electrode layer over the first bottom electrode layer.4. The method of claim 3 , wherein the first bottom electrode layer has a first thickness and the second bottom electrode layer has a second thickness that is less than the first thickness.5. The method of claim 1 , further comprising:patterning the top electrode layer to form a top electrode; andforming an upper metal interconnect layer onto the top electrode.6. The method of claim 5 , ...

RRAM cell bottom electrode formation

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Formation of getter layer for memory device

An embodiment of a memory device is disclosed. The memory device includes a multi-stack dielectric layer over a substrate; a first conductive layer over the multi-stack dielectric layer; a second conductive layer over the first conductive layer; a getter layer over the second conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride; and an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the first conductive layer.

Magnetic tunnel junction (MTJ) in magnetic random access memory

Methods and apparatuses for a magnetic tunnel junction (MTJ) which can be used in a magnetic random access memory cell are disclosed. The MTJ comprises a free layer and an insulator layer. The MTJ further comprises a pinned layer with a first region, a second region, and a third region. The second region is of a first length and of a first thickness, and the first region and the third region are of a second length and of a second thickness. A ratio of the first thickness to the second thickness may be larger than 1.2. A ratio of the second length to the first length is larger than 0.5. The first thickness may be larger than a spin diffusion length of a material for the pinned layer. So formed MTJ results in increased tunneling magnetic resistance ratio and reduced critical switch current of the MTJ. The invention provides magnetic tunnel junction (MTJ) in the magnetic random access memory.

Semiconductor device and integrated inductor

A semiconductor structure includes a first magnetic layer, an insulative oxide layer, an oxygen trapping layer and a cap layer. The insulative oxide layer is over the first magnetic layer. The oxygen trapping layer is over the insulative oxide layer. The oxygen concentration of the oxygen trapping layer is less than an oxygen concentration of the insulative oxide layer. The cap layer is over the oxygen trapping layer.

Multi-step method of forming a metal film

The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes).

Network system with remote wake-up mechanism and remote wake-up method thereof

A network system with remote wake-up mechanism and a remote wake-up method thereof. The network system includes: a first network device in a first local area network; a second network device in a second local area network, wherein the first local area network and the second local area network are different; and, a match server in a wide area network, wherein the first network device and the second network device perform data transmission through the match server.

Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same

A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.

FORMATION OF GETTER LAYER FOR MEMORY DEVICE

A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature. 1. A method comprising:providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature;forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature;forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride; andforming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.2. The method of claim 1 , wherein the semiconductor device is a split-gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) storage device.3. The method of claim 2 , wherein the semiconductor device feature includes at least one of: a source feature of the SG-MONOS storage device claim 2 , a drain feature of the SG-MONOS storage device claim 2 , a control gate feature of the SG-MONOS storage device claim 2 , and a select feature of the SG-MONOS storage device.4. The method of claim 1 , wherein the first layer of the getter layer is formed of zirconium.5. The method of claim 1 , wherein the first layer of the getter layer is formed of hafnium.6. The method of claim 1 , wherein the first layer of the ...

Piezoelectric loudspeaker

The present invention discloses a piezoelectric loudspeaker. The piezoelectric loudspeaker comprises a sound producing plate, a resonant sound-box, a surround and a reflective sound-box. The sound producing plate comprises a piezoelectric ceramic element. The resonant sound-box includes a first opening comprising a first carrying part. The sound producing plate is disposed on the first carrying part. A cavity resonator is formed between the sound producing plate and the resonant sound-box. The surround is disposed between the first carrying part and the sound producing plate. The reflective sound-box includes a second opening and a reflective output opening. The second opening comprises a second carrying part. The resonant sound-box is disposed on the second carrying part. A reflective cavity body is formed between the resonant sound-box and the reflective sound-box, and the reflective cavity body is connected the reflective output opening.

Signal detection method and signal receiving device for enhancing reliability of code rate search

A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

NETWORK DEVICE AND NETWORK CONNECTING METHOD FOR BUILDING UP NETWORK CONNECTION VIA HIGH DEFINITION MULTIMEDIA INTERFACE

A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result. 1. A network device for building up a network connection via a high-definition multimedia interface (HDMI) , the network device comprising:a scrambler, arranged for generating a transmission signal according to a first seed;a descrambler, arranged for decoding a receiving signal to generate a second seed;a comparator, for generating a comparing result according to the first seed and the second seed; anda control unit, arranged for controlling the network connection according to the comparing result.2. The network device of claim 1 , wherein the comparator comprises:a reference value determining unit, arranged for determining at least one seed position reference value; anda computing unit, arranged for generating the comparing result according to the at least one seed position reference value, the first seed, and the second seed.3. The network device of claim 1 , wherein the comparator comprises:a seed position lookup table provider, arranged for providing a seed position lookup table; anda computing unit, arranged for generating the comparing result according to the seed position lookup table, the first seed, and the second seed.4. The network device of claim 1 , wherein the network device further comprises a receiving unit claim 1 , arranged for receiving the receiving signal; and when the comparing result indicates that a time distance between the first seed and the second seed is smaller than a threshold claim 1 , the control unit generates a ...

LIQUID CRYSTAL DISPLAY WITH COLOR LIGHT GUIDE PANEL

An LCD including a backlight module and an LCD panel is provided. The LCD panel includes a color light guide panel, suitable for differentiating an incident light into multiple color lights. The color light guide panel includes a substrate and a color light output structure. The substrate has multiple pixel regions, and the color light output structure is disposed in each of the pixel regions. The color light output structure includes first˜fourth nano-patterns. The incident light is scattered by the first nano-pattern for producing a first color light, scattered by the second nano-pattern for producing a second color light, scattered by the third nano-pattern for producing a third color light, and scattered by the fourth nano-pattern for producing a fourth color light. The color light guide panel can output uniform and high luminous first˜fourth color light, and the LCD can display high quality image. 1. An LCD , comprising:a backlight module, for providing an incident light; and an active device array substrate;', 'an opposite substrate, disposed oppositely to the active device array substrate; and', 'a liquid crystal layer, disposed between the active device array substrate and the opposite substrate;, 'an LCD panel, disposed above the backlight module, the LCD panel comprising a first nano-pattern, scattering the incident light for producing a first color light;', 'a second nano-pattern, scattering the incident light for producing a second color light; and', 'a third nano-pattern, scattering the incident light for producing a third color light,, 'a color light output structure, disposed on the active device array substrate or the opposite substrate for differentiating the incident light into multiple color lights, and the color light output structure comprisingwherein the color light output structure further comprises a fourth nano-pattern, the incident light is scattered by the fourth nano-pattern for producing a fourth color light, and the fourth nano-pattern ...

REMOTE WAKE MECHANISM FOR A NETWORK SYSTEM AND REMOTE WAKE METHOD THEREOF

A network system with wake-up on LAN (WOL) mechanism and a wake-up on LAN method are disclosed. The network system includes: a first network device in a first local area network; a second network device in a second local area network, wherein the first local area network and the second local area network are different; and, a match server in a wide area network, wherein the first network device and the second network device perform data transmission through the match server. 1. A network system , comprising:a first network device in a first local area network (LAN);a second network device in a second local area network, wherein the first local area network are different local area networks; anda match server in a wide area network, wherein the first network device and the second network device perform data transmission through the match server.2. The system according to claim 1 , wherein the first network device logs in to the match server to set a wake-up packet pattern claim 1 , and wherein when the second network device attempts to access data in the first network device claim 1 , a user is required to log in to the match server to input the wake-up packet pattern to thereby enable the first network device to authenticate and determine whether to be woken up and transmit data.3. The system according to claim 1 , further comprising:a third network device, wherein the third network device and the first network device are in the same local area network.4. The system according to claim 3 , wherein the first network device includes an embedded Green Cloud Ethernet card claim 3 , the second network device is a device capable of connecting to internet claim 3 , and the third network device is compliant with wake-up on LAN (WOL) technology.5. The system according to claim 3 , wherein after the second network device logs in to the match server and sends a media access control (MAC) address of the third network device to the first network device claim 3 , the first network ...

MAGNETIC LOGIC DEVICE

The present disclosure provides for magnetic logic devices and methods of operating such a device. In one embodiment, the device includes a bottom electrode configured to receive a first input current and a second input current, a bottom magnetic layer disposed over the bottom electrode, a nonmagnetic layer disposed over the bottom magnetic layer, a top magnetic layer disposed over the nonmagnetic layer, and a top electrode disposed over the top magnetic layer, the top electrode and the bottom electrode configured to provide an output voltage which is dependent on the first and second input currents and which follows an AND gate logic or an OR gate logic. 1. A magnetic logic device , comprising:a bottom electrode configured to receive a first input current and a second input current;a bottom magnetic layer disposed over the bottom electrode;a nonmagnetic layer disposed over the bottom magnetic layer;a top magnetic layer disposed over the nonmagnetic layer; anda top electrode disposed over the top magnetic layer, the top electrode and the bottom electrode configured to provide an output voltage which is dependent on the first and second input currents and which follows an AND gate logic or an OR gate logic.2. The device of claim 1 , wherein the bottom electrode includes a first input current lead claim 1 , a second input current lead claim 1 , and a bottom voltage lead claim 1 , and wherein the top electrode includes an output current lead and a top voltage lead.3. The device of claim 1 , wherein an initial magnetization alignment of the bottom and top magnetic layers is antiparallel claim 1 , and further wherein the output voltage is dependent on the magnetization alignment of the bottom and top magnetic layers.4. The device of claim 3 , wherein the output voltage is a first binary level when the first and second input currents are each 0 or less than half a critical current required to switch the magnetization direction of the top magnetic layer claim 3 , and when ...

Double patterning method using tilt-angle deposition

Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.

TECHNIQUE FOR SMOOTHING AN INTERFACE BETWEEN LAYERS OF A SEMICONDUCTOR DEVICE

The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer. 1. A semiconductor memory device , comprising:a pinning layer having an anti-ferromagnetic material and disposed over a first electrode;a pinned layer disposed over the pinning layer;a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material;a barrier layer disposed on the composite layer;a free layer disposed over the barrier layer; anda second electrode disposed over the free layer.2. The device of claim 1 , wherein the magnetic material of the composite layer includes a ferromagnetic material.3. The device of claim 2 , wherein:the magnetic material of the composite layer includes cobalt and iron; andthe non-magnetic material of the composite layer includes one of magnesium and aluminum.4. The device of claim 2 , wherein the barrier layer includes one of magnesium and aluminum.5. The device of claim 2 , wherein the pinned layer includes a ferromagnetic layer containing cobalt and iron.6. The device of claim 1 , wherein the pinned layer includes:a first ferromagnetic layer;a spacer layer disposed on the first ferromagnetic layer; anda second ferromagnetic layer disposed on the spacer layer.7. The device of claim 5 , wherein the spacer layer includes a material selected from the group consisting of ruthenium (Ru) claim 5 , titanium (Ti) claim 5 , tantalum (Ta) claim 5 , copper (Cu) claim 5 , and silver (Ag).8. The device of claim 5 , wherein each of the first and second ...

METHOD AND STRUCTURE FOR A MRAM DEVICE WITH A BILAYER PASSIVATION

The present disclosure provides a magnetoresistive random access memory (MRAM) device. The MRAM device includes a magnetic tunnel junction (MTJ) stack on a substrate; and a dual-layer passivation layer disposed around the MTJ stack. The dual-layer passivation layer includes an oxygen-free film formed adjacent sidewalls of the MTJ stack; and a moisture-blocking film formed around the oxygen-free film. 1. A magnetoresistive random access memory (MRAM) device comprising:a magnetic tunnel junction (MTJ) stack on a substrate; and an oxygen-free film formed adjacent sidewalls of the MTJ stack, and', 'a moisture-blocking film formed around the oxygen-free film., 'a dual-layer passivation layer disposed around the MTJ stack, the dual-layer passivation layer including2. The device of wherein:the oxygen-free film includes an oxygen-free dielectric material; andthe moisture-blocking layer includes a metal oxide.3. The device of claim 1 , wherein:the oxygen-free film includes one of silicon nitride and silicon carbide; andthe moisture-blocking layer includes one of aluminum oxide (AlO), tantalum oxide (TaO), and titanium oxide (TiO).4. The device of wherein:the oxygen-free film includes SiN formed by radical chemical vapor deposition (CVD); andthe moisture-blocking layer includes AlO formed by physical vapor deposition (PVD).5. The device of claim 1 , further comprising a silicon oxide layer over the dual-passivation layer and formed by plasma-enhanced CVD.6. The device of claim 1 , wherein the MTJ stack includes:a pinning layer having an anti-ferromagnetic material;a pinned layer disposed over the pinning layer and having a first ferromagnetic material;a barrier layer disposed on the pinned layer and having a non-magnetic material; anda free layer disposed over the barrier layer and having a second ferromagnetic material.7. The device of claim 6 , wherein the pinned layer includes:a first ferromagnetic layer;a second ferromagnetic layer disposed on the first ferromagnetic ...

MAGNETIC DEVICE FABRICATION

The present disclosure provides for magnetic devices and methods of fabricating such a device. In one embodiment, a magnetic device includes a first elliptical pillar of first material layers; a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers. The second elliptical pillar is smaller than the first elliptical pillar in size. 1. A magnetic device , comprising:a first elliptical pillar of first material layers;a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers,wherein the second elliptical pillar is smaller than the first elliptical pillar in size.2. The magnetic device of claim 1 , wherein the second elliptical pillar has major and minor axes smaller than the major and minor axes of the first elliptical pillar.3. The magnetic device of claim 1 , whereinthe first material layers include a bottom magnetic layer disposed, a nonmagnetic layer disposed over the bottom magnetic layer, and a passive layer disposed over the nonmagnetic layer; andthe second material layers include a top magnetic layer disposed over the nonmagnetic layer, and a capping layer disposed over the top magnetic layer.4. The magnetic device of claim 3 , wherein the first material layers further include an antimagnetic layer adjacent the bottom magnetic layer.6. The magnetic device of claim 3 , wherein the first material layers further include a bottom electrode underlying the bottom magnetic layer.7. The magnetic device of claim 3 , wherein the second material layers further include a top electrode disposed over the capping layer.8. The magnetic device of claim 1 , wherein the passive layer contacts sidewall of the second elliptical pillar.9. A magnetic device claim 1 , comprising: a bottom magnetic layer, and', 'a nonmagnetic layer disposed over the bottom magnetic layer;, 'a first elliptical pillar includinga ...

Magnetic Tunnel Junction (MTJ) Structure in Magnetic Random Access Memory

Methods and apparatuses for a magnetic tunnel junction (MTJ) which can be used in as a magnetic random access memory cell are disclosed. The MTJ comprises a free layer and an insulator layer. The MTJ further comprises a pinned layer with a first region, a second region, and a third region. The second region is of a first length and of a first thickness, and the first region and the third region are of a second length and of a second thickness. A ratio of the first thickness to the second thickness may be larger than 1.2. A ratio of the second length to the first length is larger than 0.5. The first thickness may be larger than a spin diffusion length of a material for the pinned layer. So formed MTJ results in increased tunneling magnetic resistance ratio and reduced critical switch current of the MTJ. 1. A structure for a magnetic random access memory cell comprising:a free layer of a first length;an insulator layer next to the free layer; anda pinned layer comprising a first region, a second region, and a third region, wherein the second region is next to the insulator layer and adjacent to the first region and the third region, the second region is of the first length and of a first thickness larger than a spin diffusion length (SDL) of a material within the pinned layer, and the first region and the third region are of a second length and of a second thickness smaller than the first thickness.2. The structure of claim 1 , wherein a ratio of the first thickness to the second thickness is about larger than 1.2.3. The structure of claim 1 , wherein a ratio of the second length to the first length is larger than 0.5.4. The structure of claim 1 , wherein the free layer comprises CoFeB claim 1 , NiFe claim 1 , Co claim 1 , Fe claim 1 , Ni claim 1 , FeB claim 1 , or FePt.5. The structure of claim 1 , wherein the pinned layer comprises CoFe claim 1 , CoFeB claim 1 , or CoFeB/Ru/CoFeB/PtMn.6. The structure of claim 1 , wherein the insulator layer comprises MgO or Al2O3.7 ...

Signal Processing Method and Associated Apparatus

A signal processing apparatus for receiving a spectral line of an original signal includes a starting point determining module, a searching module and a symbol rate determining module. The starting point determining module finds a maximum energy in the spectral line and determines at least one search starting point according to the maximum energy. From the at least one search starting point, the searching module searches along the spectral line towards a region with a lower energy for at least one minimum energy satisfying a predetermined condition. The symbol rate determining module determines a symbol rate of the original signal according to the at least one minimum energy.

SIGNAL PROCESSING APPARATUS AND ASSOCIATED METHOD

A signal processing apparatus includes an initial detecting module, a mixer, a symbol rate detecting module, a judging module and a correcting module. The initial detecting module determines an initial carrier frequency offset of an input signal according to a spectrum of the input signal. The mixer adjusts the input signal according to the initial carrier frequency offset to generate a frequency-compensated signal. The symbol rate detecting module determines a symbol rate of the input signal. The judging module judges whether the initial carrier frequency offset is correct according to the frequency-compensated signal. When a judgment result of the judging module is negative, the correcting module determines a corrected carrier frequency offset according to the symbol rate and the spectrum. 1. A signal processing apparatus , comprising:an initial detecting module, for determining an initial carrier frequency offset of an input signal according to a spectrum of the input signal;a mixer, for adjusting the input signal according to the initial carrier frequency offset to generate a frequency-compensated signal;a symbol rate detecting module, for determining a symbol rate of the input signal;a judging module, for performing a phase recovery on the frequency-compensated signal, and judges whether the initial carrier frequency offset is correct as a judgement result according to whether the phase recovery renders a phase locking; anda correcting module, coupled to the mixer, for selectively determining a corrected carrier frequency offset according to the symbol rate and the spectrum and providing the corrected carrier frequency offset to the mixer based on the judgment result.2. The apparatus according to claim 1 , wherein when the judgment result of the judging module is negative claim 1 , the correcting module selects a frequency segment having a width corresponding to the symbol rate from the spectrum claim 1 , and renders the corrected carrier frequency offset with ...

Apparatus and Method for Correcting Phase Error

An apparatus for correcting a phase error is provided. The apparatus includes an error estimating module and a correcting module. The error estimating module receives a phase-shift keying signal, and calculates a phase error according to the phase-shift keying signal, a plurality of known candidate signals and Bayesian estimation. The correcting module corrects the phase-shift keying signal according to the phase error. 1. A phase error correcting apparatus , applied to a phase-shift keying communication system , the apparatus comprising:an error estimating module, for receiving a phase-shift keying signal comprising an original signal and a noise signal, and calculating a phase error caused by the noise signal according to the phase-shift keying signal and a plurality of candidate signals using Bayesian estimation; wherein the original signal represents one of the plurality of candidate signals; anda correcting module, for correcting the phase-shift keying signal according to the phase error.2. The apparatus according to claim 1 , wherein the error estimating module associates a quadratic of a difference of the original signal and an estimated signal corresponding to the phase-shift keying signal to a Bayesian risk claim 1 , and calculates the phase error toward minimizing the Bayesian risk claim 1 , in a way that a phase difference of the corrected phase-shift keying signal and the original signal is minimized.5. The apparatus according to claim 4 , further comprising:a low-pass filter, for filtering the phase error to generate a filtered result; anda numerically-controlled oscillator (NCO), for generating an output signal according to the filtered result for the correcting module to adjust a phase of the phase-shift keying signal.6. The apparatus according to claim 5 , further comprising:a control module, for adjusting the low-pass filter;wherein, when the control module determines a thermal noise index is higher than a first threshold, the control module lowers ...

APPARATUS AND METHOD FOR DETECTING SPECTRUM INVERSION

An apparatus for detecting spectrum inversion includes a different correlator and a determining module. The differential correlator performs an odd-order differential correlation on an input signal and a known signal to generate a differential correlation result. When the input signal is determined as corresponding to a target signal of the known signal, the determining module detects spectrum inversion in the input signal according to the phase of the differential correlation result. 1. An apparatus for detecting spectrum inversion , comprising:{'sub': 'm1', 'a differential correlator, configured to perform an odd-order differential correlation on an input signal and a known signal to generate a first differential correlation result d; and'}{'sub': 'm1', 'a determining module, coupled to the differential correlator, for detecting spectrum inversion in the input signal according to a phase of the first differential correlation result dwhen the input signal is determined as a target signal corresponding to the known signal.'}2. The apparatus according to claim 1 , wherein the determining module determines whether the input signal is the target signal according to an absolute value of the first differential correlation result d.4. The apparatus according to claim 3 , further comprising:a control module, for determining the order m1 employed by the differential correlator according to a channel environment passed by the input signal; wherein the control module selects the greater order m1 as the channel environment gets poorer.5. The apparatus according to claim 1 , wherein the differential correlator further generates a second differential correlation result dcorresponding to a different odd-order; and the determining module detects the spectrum inversion in the input signal according to the phase of the first differential correlation result dand a phase of the second differential correlation result d.6. The apparatus according to claim 5 , wherein the determining ...

IMAGE PROJECTION DEVICE AND DETECTION METHOD THEREOF

A detection method of an image projection device is disclosed. A projection beam is projected on a plurality of projection regions within a projection range, wherein the projection beam carries different features when the projection beam is projected on different projection regions. A reflected beam from the projection range is received and converted to an electrical signal. The feature existing in the electrical signal is analyzed. The projection region corresponding to the feature is determined to identify which of the projection regions is/are blocked by an object. 1. A detection method of an image projection device , comprising:projecting a projection beam on a projection range having a plurality of projection regions, the projection beam projecting on different projection regions having different features;receiving and converting a reflected beam reflected from the projection range to obtain an electrical signal;analyzing the feature existing in the electrical signal; anddetermining which of the projection regions is/are blocked by an object.2. The detection method according to claim 1 , wherein claim 1 , the feature is a feature of waveform claim 1 , and the projection beam projecting on different projection regions has different waveforms.3. The detection method according to claim 1 , wherein claim 1 , the feature is a feature of frequency claim 1 , and the projection beam projecting on different projection regions has different frequencies.4. The detection method according to claim 1 , wherein claim 1 , the feature is a feature of phase claim 1 , and the projection beam projecting on different projection regions has different phases.5. The detection method according to claim 1 , wherein claim 1 , the image projection device receives a plurality of reflected beams claim 1 , analyzes the features existing in the corresponding electrical signals claim 1 , and determines movement of the object according to an appearing order of the features.6. An image ...

MAGNETORESISTIVE RANDOM ACCESS MEMORY CELL AND FABRICATING THE SAME

The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials. 1. A semiconductor memory device , comprising:a pinning layer over a first electrode;a pinned layer disposed over the pinning layer;a tunneling layer disposed over the pinned layer;a free layer disposed over the tunneling layer;a capping layer disposed over the free layer; anda second electrode disposed over the capping layer.2. The device of claim 1 , wherein the pinning layer includes anti-ferromagnetic (AFM) materials selected from the group consisting of platinum manganese (PtMn) claim 1 , iridium manganese (IrMn) claim 1 , rhodium manganese (RhMn) claim 1 , and iron manganese (FeMn).3. The device of claim 1 , wherein the pinned layer includes ferromagnetic materials selected from the group consisting of cobalt-iron-boron (CoFeB) claim 1 , cobalt-iron-tantalum (CoFeTa) claim 1 , nickel iron (NiFe) claim 1 , cobalt (Co) claim 1 , cobalt iron (CoFe) claim 1 , cobalt platinum (CoPt) claim 1 , cobalt palladium (CoPd) claim 1 , iron platinum (FePt) claim 1 , and alloys thereof.4. The device of claim 3 , wherein the pinned layer includes:a first ferromagnetic sub-layer;a spacer sub-layer disposed on the first ferromagnetic sub-layer; anda second ferromagnetic sub-layer disposed on the spacer sub-layer.5. The device of claim 1 , wherein the tunneling layer includes materials selected from the group consisting of magnesium (Mg) claim 1 , magnesium oxide (MgO) claim 1 , aluminum oxide (AlO) claim 1 , aluminum nitride (AlN) claim 1 , and aluminum oxynitride (AlON).6. The device of claim 1 , wherein the free layer includes ferromagnetic ...

MULTIPLE METAL LAYER SEMICONDUCTOR DEVICE AND LOW TEMPERATURE STACKING METHOD OF FABRICATING THE SAME

A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process. 1. A method of fabricating a semiconductor device , the method comprising:providing a first substrate comprising a conductive element disposed therein;providing an interface surface atop the conductive element, the interface surface comprising a metal layer coupled to the conductive element;conducting a polishing process on the interface surface of the first substrate.providing a second substrate comprising a conductive element disposed therein;providing an interface surface atop the conductive element of the second substrate, the interface surface of the second substrate comprising a metal layer coupled to the conductive element of the second substrate;conducting a polishing process on the interface surface of the second substrate; andstacking the second substrate atop the first substrate, wherein the interface surfaces of the first and second substrates contact one another.2. A method as defined in claim 1 , further comprising:bonding the interface surfaces of the first and second substrates together using a hybrid bonding process.3. A method as defined in claim 2 , further comprising fabricating the metal layers of the first and second substrates using identical or different metals.4. A method as defined in claim 2 , wherein bonding the interface surfaces ...

ELECTRONIC VARIABLE SUSPENSION SYSTEM

An electronic variable suspension system applicable to a motorcycle includes a plurality of sensors, a suspension unit, an actuation unit, and a control unit. The sensors are disposed in a front portion and/or rear portion of the motorcycle to sense acceleration, displacement, or frequency so as to generate a plurality of sensing signals. The suspension unit includes front and rear suspension devices disposed in the motorcycle. The actuation unit includes front and rear actuation devices coupled to the front suspension device and the rear suspension device, respectively. The control unit generates at least a control signal according to the sensing signals. The actuation unit changes a damping value and/or a preload value of the front suspension device and/or the rear suspension device according to the at least a control signal. 1. An electronic variable suspension system , applicable to a motorcycle , the electronic variable suspension system comprising:a plurality of sensor disposed in at least one of a front portion and a rear portion of the motorcycle to sense one of acceleration, displacement, and frequency so as to generate a plurality of sensing signals;a suspension unit comprising a front suspension device and a rear suspension device, disposed in the motorcycle;an actuation unit comprising a front actuation device and a rear actuation device, coupled to the front suspension device and the rear suspension device, respectively; anda control unit electrically coupled to the sensors and the actuation unit to generate at least a control signal according to the sensing signals,wherein the actuation unit changes at least one of a damping value and a preload value of at least one of the front suspension device and the rear suspension device according to the at least a control signal.2. The electronic variable suspension system of claim 1 , wherein:the control unit outputs at least a first control signal to the rear actuation device; andafter the rear actuation ...

HARNESS SYSTEM WITH A BUCKLE RESTRAINING FUNCTION

A harness system with a buckle restraining function includes an upper buckle, an upper strap and a restraining assembly. The upper strap slidably passes through the upper buckle, and the upper strap includes a shoulder portion and a waist portion divided by the upper buckle. The restraining assembly utilizes an anti-sliding structure having a higher coefficient of friction to engage with the upper strap and further utilizes a stopping component to abut against the upper buckle. Therefore, the present invention can effectively restrain a sliding movement of the upper buckle relative to the upper strap and toward the shoulder portion by engagement of the anti-sliding structure and the upper strap and abutment of the stopping component and the upper buckle, which prevents an excessive decrease of a length of the shoulder portion of the upper strap and prevents a potential risk of injury of the passenger's upper body. 1. A harness system with a buckle restraining function , the harness system comprising:an upper buckle;an upper strap slidably passing through the upper buckle, and the upper strap comprising a shoulder portion and a waist portion divided by the upper buckle; anda restraining assembly configured to restrain a sliding movement of the upper buckle relative to the upper strap and toward the shoulder portion when the waist portion of the upper strap is forced by a passenger's body during a collision or an emergency brake of a vehicle.2. The harness system of claim 1 , wherein a through slot is formed on the upper buckle claim 1 , the restraining assembly comprises an anti-sliding structure and a beam structure disposed on the upper buckle claim 1 , the through slot comprises a first portion and a second portion divided by the beam structure claim 1 , the first portion is adjacent to the shoulder portion claim 1 , the second portion is adjacent to the waist portion claim 1 , and the upper strap passes through the first portion from bottom to top and passes ...

NETWORK SWITCH AND NETWORK SWITCH SYSTEM THEREOF

A network switch and a network switch system thereof are provided. The network switch includes a plurality of connection ports and a processing circuit. When any of the connection ports receives a first abnormal message packet and one of the connection ports is in a disabled state, the processing circuit sets the connection port in the disabled state to switch to an enabled state, and the processing circuit does not forward the first abnormal message packet in the single loop network. When one of the connection ports is abnormal and each of the connection ports forming the single loop network is in the enabled state, the processing circuit sets the abnormal connection port to switch to the disabled state, and transmits a second abnormal message packet to other network switches in the single loop network through another connection port that is not abnormal. 1. A network switch adapted for forming a single loop network , the network switch comprising:a plurality of connection ports, wherein each of the connection ports is in an enabled state or a disabled state by default to form the single loop network, each of the connection ports in the enabled state receives a data packet in the single loop network and forwards the data packet, and each of the connection ports in the disabled state receives the data packet in the single loop network but does not forward the data packet; anda processing circuit coupled to the connection ports and configured to determine whether the connection ports forming the single loop network are abnormal and determine whether any of the connection ports forming the single loop network receives a first abnormal message packet from other network switches, wherein when any of the connection ports receives the first abnormal message packet and one of the connection ports forming the single loop network is in the disabled state, the processing circuit sets the connection port in the disabled state to switch to the enabled state, and the processing ...

DETECTION CIRCUIT

A detection circuit is provided. A detection signal corresponding to an equivalent capacitance value of a micro-electro-mechanical system is generated by an oscillator, and the equivalent capacitance value of the micro-electro-mechanical system varies with a location of the micro-electro-mechanical system. 1. A detection circuit , suitable for detecting a location of a micro-electro-mechanical system , comprising:an oscillator having an input terminal coupled to the micro-electro-mechanical system, and generating a first oscillation signal according to an equivalent capacitance value of the micro-electro-mechanical system;a phase lock loop unit performing a phase lock to the first oscillation signal to output a phase lock control signal;a first low pass filter unit being coupled to the phase lock loop unit, and performing a low pass filtration to the phase lock control signal to generate a filter signal; andan amplifying unit being coupled to the first low pass filter unit, and amplifying the filter signal to generate a detection signal.2. The detection circuit of claim 1 , wherein the oscillator comprises:an inverting unit having an input terminal coupled to the micro-electro-mechanical system;a second low pass filter unit being coupled between the input terminal and an output terminal of the inverting unit;a feedback resistor being coupled between the input terminal and the output terminal of the inverting unit; anda buffer unit being coupled between the output terminal of the inverting unit and the phase lock loop unit, and buffering a voltage outputted by the inverting unit.3. The detection circuit of claim 2 , further comprising:a blocking capacitor coupled between the micro-electro-mechanical system and the input terminal of the inverting unit.4. The detection circuit of claim 2 , wherein the second low pass filter unit comprises:a resistor having a terminal coupled to the output terminal of the inverting unit;a capacitor coupled between another terminal of ...

Magnetoresistive Random Access Memory Cell and Fabricating the Same

The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials. 1. A device comprising:a magnetic tunnel junction device disposed between an upper electrode and a lower electrode, wherein the magnetic tunnel junction device includes:a plurality of layers; anda capping layer disposed on the plurality of layers,wherein the capping layer is configured to provide an etch resistance that protects a free layer and a tunneling layer of the plurality of layers of the magnetic tunnel junction device from edge damage during an etching process,wherein the capping layer includes at least one of: a metal nitride or a metal oxide, andwherein a concentration of at least one of: oxygen or nitrogen within the capping layer is determined by a target tunneling magnetoresistance (TMR) and resistance area (RA) of the magnetic tunnel junction device.2. The device of claim 1 , wherein the capping layer includes at least one of: beryllium claim 1 , magnesium claim 1 , aluminum claim 1 , titanium claim 1 , tungsten claim 1 , germanium claim 1 , or platinum.3. The device of claim 1 , wherein the capping layer has a thickness between about 3 angstroms and about 20 angstroms.4. The device of claim 1 , wherein the tunneling layer includes at least one of: magnesium claim 1 , magnesium oxide claim 1 , aluminum oxide claim 1 , aluminum nitride claim 1 , or aluminum oxynitride.5. The device of claim 1 , wherein the plurality of layers further includes:a pinning layer disposed on the lower electrode; anda pinned structure disposed on the pinning layer and below the tunneling layer.6. The device of claim 5 , wherein the pinned ...

SIGNAL PROCESSING DEVICE AND ASSOCIATED EQUALIZATION CIRCUIT AND SIGNAL PROCESSING METHOD

A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal. 1. A signal processing device for a receiver , comprising:a descrambler, descrambling an input signal to generate a descrambled signal;a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal;an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; anda decoder, decoding the equalized signal to obtain data included in the input signal.wherein the equalization module comprises:a first scrambler, scrambling the phase recovered signal to generate a scrambled phase recovered signal;an equalization circuit, performing the equalization according to the scrambled phase recovered signal to generate a scrambled equalized signal; anda first descrambler, descrambling the scrambled equalized signal to generate the equalized signal.2. The signal processing device according to claim 1 , further comprising:a frontend circuit, converting a radio-frequency signal to a baseband signal;a timing recovery circuit, performing timing recovery on the baseband signal to generate a timing recovered signal; anda frame synchronization circuit, performing frame synchronization according to the timing recovered signal to generate a frame synchronized signal;wherein, the descrambler is coupled between the frame synchronization circuit and the phase recovery circuit, and the input signal is the frame synchronized signal.3. (canceled)4. The signal processing device according to claim 1 , wherein the ...

ROLL-OFF PARAMETER DETERMINING METHOD AND MODULE

A roll-off parameter determining module disposed at a receiving terminal is provided. The receiving terminal receives first roll-off information of a first frame and second roll-off information of a second frame. The first frame is adjacent to the second frame. The module for determining a roll-off parameter includes: a register unit; a first determining unit, determining whether one of the first roll-off information and the second roll-off information includes a first data type, and generating a first roll-off parameter indicator; a second determining unit, determining whether one of the first roll-off information and the second roll-off information includes a second data type and outputting a second roll-off parameter indicator; and a look-up table (LUT) unit, looking up an LUT according to the first roll-off parameter indicator and a second roll-off parameter indicator to output a roll-off parameter. 1. A roll-off parameter determining device , disposed at a receiving terminal , the receiving terminal comprising an analyzing module , the analyzing module analyzing a first frame and a second frame to identify first roll-off information in the first frame and second roll-off information in the second frame , the first frame being adjacent to the second frame , the roll-off parameter determining device comprising:a register unit, storing the first roll-off information;a first determining unit, determining whether one of the first roll-off information and the second roll-off information comprises a first data type according to the first roll-off information received from the register unit and the second roll-off information received from the analyzing module to generate a first roll-off parameter indicator;a second determining unit, determining whether at least one of the first roll-off information and the second roll-off information comprises a second data type according to the first roll-off information received from the register unit and the second roll-off ...

HARNESS SYSTEM WITH A BUCKLE RESTRAINING FUNCTION

A harness system includes an upper buckle, an upper strap and a restraining assembly including an anti-sliding structure and a beam structure. A through slot is formed on the upper buckle. The upper strap passes through the through slot. The beam structure is slidably disposed on the upper buckle. The anti-sliding structure is disposed on at least one of the beam structure and a wall of the through slot. The upper strap is engaged by the anti-sliding structure for restraining a sliding movement of the upper buckle relative to the upper strap and toward a shoulder portion when the upper strap is forced to drive the beam structure to slide relative to the upper buckle and toward the wall of the through slot. 1. A harness system with a buckle restraining function , the harness system comprising:an upper buckle;an upper strap slidably passing through the upper buckle, and the upper strap comprising a shoulder portion and a waist portion divided by the upper buckle; anda restraining assembly configured to restrain a sliding movement of the upper buckle relative to the upper strap and toward the shoulder portion when the waist portion of the upper strap is forced by a passenger's body during a collision or an emergency brake of a vehicle;wherein a through slot is formed on the upper buckle, the restraining assembly comprises an anti-sliding structure and a beam structure slidably disposed on the upper buckle, the upper strap passes through the through slot, the beam structure is slidably disposed on the upper buckle, the anti-sliding structure is disposed on at least one of the beam structure and a wall of the through slot, and the upper strap is engaged by the anti-sliding structure for restraining the sliding movement of the upper buckle relative to the upper strap and toward the shoulder portion when the upper strap is forced to drive the beam structure to slide relative to the upper buckle toward the wall of the through slot.2. The harness system of claim 1 , wherein ...

INSPECTION OF CIRCUIT BOARDS FOR UNAUTHORIZED MODIFICATIONS

A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board. 1. A method of inspecting circuit boards for unauthorized modifications , the method comprising:acquiring an image of a target circuit board to generate a target image and of a gold circuit board to generate a gold image, the gold circuit board being a known-good circuit board;locating a plurality of fiducial points on the target image and on the gold image;performing perspective transformation on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference;after performing perspective transformation on the target image and on the gold image, identifying an anomalous section of pixels of the target image, the anomalous section of pixels of the target image having intensities that are different from intensities of a corresponding section of pixels of the gold image; andissuing an alert in response to identifying the anomalous section of pixels.2. The method of claim 1 , wherein identifying the anomalous section of pixels of the target image comprises:subtracting intensities of pixels of the target image from intensities of pixels of the gold image to generate a difference image; andidentifying, on the difference image, pixels that have non-zero intensities.3. The method of claim 2 , further comprising: ...

PHASE ERROR DETECTING MODULE AND PHASE ERROR DETECTION METHOD

A phase error detection module includes: a constellation point selector, generating a constellation point selection signal according to a position and a radius of data of an input signal in a constellation diagram; a symbol estimator, selecting a part of all of a plurality of constellation points in the constellation diagram according to the constellation point selection signal, as a plurality of reference constellation points for calculating an estimated symbol corresponding to the data of the input signal, and a quantity of the reference constellation points is smaller than a quantity of all of the constellation points of the constellation diagram; and a phase estimator, calculating an estimated phase error of the input signal according to the data of the input signal and the estimated symbol. 1. A phase error detection module , comprising:a constellation point selector, generating a constellation point selection signal according to a position and a radius of data of an input signal in a constellation diagram;a symbol estimator, selecting, according to the constellation point selection signal, a part of all of a plurality of constellation points of the constellation diagram, as a plurality of reference constellation points for calculating an estimated symbol corresponding to the data of the input signal, and a quantity of the plurality of reference constellation points is smaller than a quantity of all of the plurality of constellation points; anda phase evaluator, calculating an estimated phase error of the input signal according to the data of the input signal and the estimated symbol,wherein the constellation diagram is divided into a plurality of areas, and the constellation point selector comprises:an area determiner, determining in which one of the plurality of areas the position of the data of the input signal is located in the constellation diagram to generate an area indication signal;a radius comparator, determining whether the radius of the data of the ...

Symbol rate estimating device and method and adjacent channel interference detecting device

A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.

CHANNEL SCANNING METHOD FOR DIGITAL VIDEO BROADCASTING SATELLITE SIGNAL

A channel scanning method for Digital Video Broadcasting—Satellite (DVB-S) signals is provided. The method includes: scanning a radio frequency (RF) signal according to a normal frequency step; when the Nchannel is detected, obtaining a difference between a low boundary of an Nchannel and a high boundary of an (N−1)channel; and, when the difference is within a predetermined bandwidth range, scanning the RF signal between the high boundary of the (N−1)channel and the low boundary of the Nth channel according to a narrow frequency step. The normal frequency step is greater than the narrow frequency step. 1. A channel scanning method for a Digital Video Broadcasting—Satellite (DVB-S) signal , comprising:scanning a radio frequency (RF) signal according to a normal frequency step;{'sup': th', 'th', 'th, 'when an Nchannel is detected, obtaining a difference between a low boundary of the Nchannel and a high boundary of an (N−1)channel; and'}{'sup': th', 'th, 'when the difference is within a predetermined bandwidth range, scanning the RF signal between the high boundary of the (N−1)channel and the low boundary of the Nchannel according to a narrow frequency step;'}wherein, the normal frequency step is greater than the narrow frequency step.2. The channel scanning method according to claim 1 , wherein the step of scanning the RF signal according to the normal frequency step detects the RF signal within a first adjustment interval corresponding to a tuner center frequency.3. The channel scanning method according to claim 2 , wherein the step of scanning the RF signal according to the normal frequency step further comprises:when no channel signal is detected from the RF signal, relocating the tuner center frequency and the corresponding first adjustment interval by the normal frequency step, and again detecting the RF signal.4. The channel scanning method according to claim 2 , further comprising:{'sup': th', 'th, 'when the difference falls out of the predetermined bandwidth ...

PIEZOELECTRIC LOUDSPEAKER

The present invention discloses a piezoelectric loudspeaker. The piezoelectric loudspeaker comprises a sound producing plate, a resonant sound-box, a surround and a reflective sound-box. The sound producing plate comprises a piezoelectric ceramic element. The resonant sound-box includes a first opening comprising a first carrying part. The sound producing plate is disposed on the first carrying part. A cavity resonator is formed between the sound producing plate and the resonant sound-box. The surround is disposed between the first carrying part and the sound producing plate. The reflective sound-box includes a second opening and a reflective output opening. The second opening comprises a second carrying part. The resonant sound-box is disposed on the second carrying part. A reflective cavity body is formed between the resonant sound-box and the reflective sound-box, and the reflective cavity body is connected the reflective output opening. 1. A piezoelectric loudspeaker , comprising:a sound producing plate including at least one piezoelectric ceramic element being able to vibrate the sound producing plate;a resonant sound-box including a first opening comprising a first carrying part, the sound producing plate being disposed on the first carrying part, and a cavity resonator being formed between the sound producing plate and the resonant sound-box;a surround disposed between the first carrying part and the sound producing plate; anda reflective sound-box including a second opening and a reflective output opening, a second carrying part formed on a partial of an inner edge of the seconding opening, the resonant sound-box being disposed on the second carrying part, a reflective cavity body being formed between the resonant sound-box and the reflective sound-box, the reflective output opening being disposed on a side of the reflective sound-box, and the reflective cavity body being communicating with the reflective output opening.2. The piezoelectric loudspeaker of ...

Laser projector and method of detecting scanning angle range of laser beam thereof

A method of detecting a scanning angle range of a laser beam of a laser projector is provided. First, a photo sensor is disposed between first and second positions on a projection mirror. Then, a laser beam emitted from the laser projector scans back and forth between the first and second positions, so that the photo sensor receives the laser beam sequentially at first and second scanning time points to generate first and second sensing signals, respectively. If an actual time interval between the first and second sensing signals conforms to an expected time interval, an actual scanning angle range of the laser beam is determined as normal. If the actual time interval does not conform to the expected time interval, the actual scanning angle range of the laser beam is determined as abnormal and the laser projector stops emitting the laser beam. A laser projector is also provided.

PACKET OUTPUTTING DEVICE AND PACKET OUTPUTTING METHOD

A packet output device includes: a first extracting unit, extracting a plurality of first packets and a plurality of first null packet values corresponding to a first channel; a first buffer, storing the first packets and the first null packet values; a second extracting unit, extracting a plurality of second packets and a plurality of second null packet values corresponding to a second channel; a second buffer, storing the second packets and the second null packet values; and a packet outputting unit, selecting, according to the first null packet values and the second null packet values, one of the first packets and the second packets as an output packet. 1. A packet output device , comprising:a first extracting unit, extracting a plurality of first packets and a plurality of first null packet values corresponding to a first channel, wherein the plurality of first packets respectively correspond to the plurality of first null packet values;a first buffer, storing the plurality of first packets and the plurality of first null packet values;a second extracting unit, extracting a plurality of second packets and a plurality of second null packet values corresponding to a second channel, wherein the plurality of second packets respectively correspond to the plurality of second null packet values;a second buffer, storing the plurality of second packets and the plurality of second null packet values; anda packet outputting unit, selecting, according to the plurality of first null packet values and the plurality of second null packet values, one of the plurality of first packets and the plurality of second packets as an output packet.2. The packet output device according to claim 1 , wherein the packet outputting unit comprises:a determining circuit, determining which of a first null packet value corresponding the first channel and a second null packet value corresponding to the second channel is 0 to generate a packet output signal; andan outputting circuit, selecting a ...

SYMBOL RATE ESTIMATION DEVICE AND SYMBOL RATE ESTIMATION METHOD

A symbol rate estimation device includes: a power spectrum density (PSD) generating unit, estimating a power of an input signal to generate a PSD; a cut-off frequency index outputting unit, outputting a cut-off frequency index according to the power; and a symbol rate calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index. 1. A symbol rate estimation device , comprising:a power spectrum density (PSD) generating unit, estimating a power of an input signal to generate a PSD, which includes a plurality of powers respectively corresponding to a plurality of frequency indices;a cut-off frequency index outputting unit, outputting a cut-off frequency index according to the PSD; anda symbol rate calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.2. The symbol rate estimation device according to claim 1 , wherein the cut-off frequency outputting unit comprises:a maximum power outputting unit, outputting a maximum power according to the PSD;a noise power outputting unit, outputting a noise power according to the PSD;a cut-off power calculating unit, calculating a cut-off power according to the maximum power and the noise power; andan index outputting unit, outputting a frequency index corresponding to the cut-off power as the cut-off frequency index.3. The symbol rate estimation device according to claim 2 , wherein the maximum power outputting unit comprises:a first accumulating unit, accumulating powers corresponding to (N1+1) frequency indices by regarding a reference frequency index as a center to output a middle power sum;a second accumulating unit, accumulating powers corresponding to (N2+1) frequency indices on a left side of the reference frequency index to output a left-hand power sum;a third accumulating unit, accumulating powers corresponding to (N3+1) frequency indices on a right side of the reference frequency index to output a right-hand power sum; anda ...

PYRAZOLO[4,3-C]Quinoline Derivatives For Inhibition Of Beta-Glucuronidase

The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota β-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma. 2. The method as claimed in claim 1 , wherein the subject is receiving at least one treatment claim 1 , and the at least one treatment is selected from the group consisting of angiogenic inhibitors claim 1 , chemotherapy claim 1 , radiation claim 1 , surgery and a combination thereof.3. The method as claimed in claim 1 , wherein the compound claim 1 , the pharmaceutical acceptable salt of the compound claim 1 , or the solvate of the compound is administered in combination with an additional therapeutic agent including one selected from the group consisting of an anti-cancer agent metabolized through glucuronidation claim 1 , an immunopotentiator and an immunomodulator.4. The method as claimed in claim 3 , wherein the compound claim 3 , the pharmaceutical acceptable salt of the compound claim 3 , or the solvate of the compound is administered in combination with the additional therapeutic agent in one of two states being simultaneously and separately. The application is a divisional of U.S. patent application Ser. No. 15/577,201, filed on Nov. 27, 2017, which is a 371 of International Application No. PCT/US2016/034379, filed on May 26, 2016, which claims the benefit of U.S. Provisional Patent Application No. 62/166,322, filed on May 26, 2015, the disclosures of which are incorporated herein in their entirety by reference.The present invention relates to a new compound for inhibition of (3-glucuronidase. Particularly, the present invention provides a pyrazolo[4,3-c ...

ERROR LIMITING METHOD, ERROR LIMITER AND DIGITAL RECEIVING CIRCUIT

An error limiting method includes: receiving a first signal and a first error signal, wherein the first error signal is associated with the first signal and a first symbol corresponding to the first signal; calculating a first magnitude value of the first signal; and decreasing an error energy of the first error signal according to the first magnitude value of the first signal to generate a second error signal, and outputting the second error signal to an error feedback circuit. 1. An error limiting method , applied to an error limiter of a digital receiving circuit , the error limiting method comprising:receiving a first signal and a first error signal, wherein the first error signal is associated with the first signal and a first symbol corresponding to the first signal;calculating a first magnitude value of the first signal; andadjusting an error energy of the first error signal according to the first magnitude value of the first signal to generate a second error signal;wherein, the error limiter outputs the second error signal to an error feedback circuit of the digital receiving circuit.2. The error limiting method according to claim 1 , wherein the step of generating the second error signal according to the first magnitude value of the first signal comprises:determining whether the first magnitude value is in an interval among a plurality of intervals, wherein the plurality of intervals correspond a plurality of thresholds that are not entirely equal; andwhen the first magnitude value is in a first interval among the plurality of intervals, generating the second error signal according to the first error signal and a first threshold among a plurality of thresholds that corresponds to the first interval.3. The error limiting method according to claim 2 , wherein when the first magnitude value is in the first interval claim 2 , the step of generating the second error signal according to the first error signal and the first threshold comprises:determining whether ...

Aptamers for targeting coagulation factor xiii and uses thereof

Provided herein is an aptamer specific to coagulation factor XIII (FXIII) and its uses thereof. Accordingly, the present aptamer is useful as a bio-tool to label thrombi, and/or as a targeting molecule to deliver drugs to thrombotic area. Therefore, the present disclosure also pertains to methods for treating diseases associated with FXIII, such as thrombosis.

SIGNAL RECEIVING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A signal processing apparatus includes an oscillation circuit, an interpolation circuit, a matching filter, a high-pass filter and a timing recovery circuit. The oscillation circuit generates a clock signal. The interpolation circuit performs interpolation on an input signal according to the clock signal to generate an interpolation sample result. The matching filter demodulates the interpolation sample result to generate an output signal. The high-pass filter performs high-pass filtering on the interpolation sample result to generate a filtered result. The timing recovery circuit receives the filtered result, and performs timing recovery according to the filtered result. 1. A signal receiving apparatus , comprising:an oscillation circuit, generating a clock signal;an interpolation circuit, performing interpolation on an input signal according to the clock signal to generate an interpolation sample result;a matching filter, demodulating the interpolation sample result to generate an output signal;a high-pass filter, performing high-pass filtering on the interpolation sample result to generate a filtered signal; anda timing recovering circuit, receiving the filtered signal, and performing timing recovery according to the filtered signal,wherein the high-pass filter is implemented to share a part of a circuit with the matching filter, and [{'sup': th', 'th, 'a delay circuit, generating N number of delayed signals for the interpolation sample result, wherein a delay amount corresponding to an (i+1)delayed signal is greater than a delay amount corresponding to an idelayed signal, i is an integer index between 1 and (N−1), and N is an integer greater than 1;'}, {'sup': th', 'th', 'th, 'a multiplication circuit, multiplying the idelayed signal by an iweight to generate an iweighted result;'}, 'a first addition circuit, summing up the interpolation sample result and the delayed signals having the integer index i in even numbers to generate a first summation value;', 'a ...

METHOD OF FILTERING PACKETS IN NETWORK SWITCH AND RELATED FILTER

A method for packet filtering in a network switch includes: utilizing an access control list circuit to filter received packets, wherein the access control list circuit compares header information of the received packets with an access control list to filter the received packets, where the access control list has at least one entry, and rule information in the entry includes only a portion of an IP address; and utilizing a routing circuit to further filter packets that pass the access control list circuit, wherein the routing circuit compares header information of the packets that pass the access control list circuit with a routing table to filter the packets, wherein the routing table has at least one entry, and rule information in the entry includes an entire IP address. 1. A method for packet filtering in a network switch , comprising:utilizing an access control list circuit to filter received packets, wherein the access control list circuit compares header information of the received packets with an access control list to filter the received packets, where the access control list has at least one entry, and rule information associated with IP address in the at least one entry includes only partial content of an IP address and the partial content of the IP address does not overlap with partial contents of IP addresses of other access control lists in the network switch; andutilizing a routing circuit to further filter packets that pass the access control list circuit, wherein the routing circuit compares header information of the packets that pass the access control list circuit with a routing table to filter the packets, wherein the routing table has at least one entry, and rule information associated with IP address in the at least entry of the routing table includes entire content of an IP address.2. The method of claim 1 , wherein the access control list circuit and the routing circuit are respectively arranged in different hardware stages of the network ...

LOOP BANDWIDTH ADJUSTING METHOD FOR PHASE LOCKED-LOOP UNIT AND ASSOCIATED LOOP BANDWIDTH ADJUSTING UNIT AND PHASE RECOVERY MODULE

A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit. 1. A loop bandwidth adjusting method , for a phase-locked loop (PLL) unit of a phase recovery module in a wireless communication system , comprising:adjusting an operating bandwidth of the PLL unit to a first bandwidth;measuring a plurality of first phase errors between a compensated input signal and a reference clock signal, and obtaining a first statistical value of the plurality of first phase errors, wherein the compensated input signal is generated according to an input signal and a phase compensating signal generated by the PLL unit;adjusting the operating bandwidth of the PLL unit to a second bandwidth;measuring a plurality of second phase errors between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the plurality of second phase errors; andadjusting the operating bandwidth according to the first statistical value and the second statistical value;wherein, the first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower ...

Elongated Magnetoresistive Tunnel Junction Structure

A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction.

MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode. 1. A semiconductor device comprising:a first conductive feature on a semiconductor substrate;a bottom electrode on the first conductive feature;a magnetic tunnel junction (MTJ) stack on the bottom electrode;a top electrode on the MTJ stack; and a first passivation layer contacting a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode, the first passivation layer comprising a first dielectric material;', 'a second passivation layer on the first passivation layer, the second passivation layer comprising a conductive material; and', 'a third passivation layer on the second passivation layer, the second passivation layer comprising the first dielectric material., 'a spacer comprising2. The semiconductor device of claim 1 , wherein the first dielectric material is silicon nitride.3. The semiconductor device of claim 1 , wherein the conductive material comprises tantalum or magnesium.4. The semiconductor device of claim 1 , wherein the first passivation layer has a thickness in a range of 10 Å to 50 Å.5. The semiconductor device of claim 1 , wherein the second passivation layer has a thickness in a range of 5 Å to 20 Å.6. The semiconductor device of claim 1 , wherein the third passivation layer has a thickness in a range of 30 Å to 250 Å.7. The semiconductor device of claim 1 , wherein a thickness of the second passivation layer is less than a thickness of the first passivation layer and less than a thickness of the third passivation layer.8. The semiconductor device of claim 1 , further comprising a dielectric layer on ...

Pyrazolo[4,3-c]quinoline derivatives for inhibition of beta-glucuronidase

The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota β-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma.

Multiple Metal Layer Semiconductor Device and Low Temperature Stacking Method of Fabricating the Same

A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.

SEMICONDUCTOR DEVICE AND INTEGRATED INDUCTOR

A semiconductor structure includes a first magnetic layer, an insulative oxide layer, an oxygen trapping layer and a cap layer. The insulative oxide layer is over the first magnetic layer. The oxygen trapping layer is over the insulative oxide layer. The oxygen concentration of the oxygen trapping layer is less than an oxygen concentration of the insulative oxide layer. The cap layer is over the oxygen trapping layer. 1. A semiconductor structure , comprising:a first magnetic layer;an insulative oxide layer over the first magnetic layer;an oxygen trapping layer over the insulative oxide layer, wherein the insulative oxide layer and the oxygen trapping layer comprise the same elements and different composition ratios, and an oxygen concentration of the oxygen trapping layer is less than an oxygen concentration of the insulative oxide layer; anda cap layer over the oxygen trapping layer.2. The semiconductor structure of claim 1 , wherein the first magnetic layer comprises an alloy comprising cobalt claim 1 , zirconium claim 1 , and at least one of tantalum claim 1 , niobium or rhenium.3. The semiconductor structure of claim 1 , wherein the insulative oxide layer comprises an oxide of cobalt claim 1 , zirconium and at least one of tantalum claim 1 , niobium or rhenium claim 1 , and the oxygen trapping layer comprises an oxide of cobalt claim 1 , zirconium claim 1 , and at least one of tantalum claim 1 , niobium or rhenium.4. (canceled)5. The semiconductor structure of claim 1 , wherein a ratio of the oxygen concentration of the oxygen trapping layer to the oxygen concentration of the insulative oxide layer ranges from about 10% to about 40%.6. The semiconductor structure of claim 1 , wherein the cap layer is a conductive layer.7. The semiconductor structure of claim 6 , wherein the conductive layer comprises tantalum.8. The semiconductor structure of claim 1 , further comprising a second magnetic layer between the oxygen trapping layer and the cap layer.9. The ...

MULTI-STEP METHOD OF FORMING A METAL FILM

The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes). 1. An integrated chip , comprising:a semiconductor substrate; anda titanium nitride film disposed over the semiconductor substrate and comprising a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride, wherein the grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film.2. The integrated chip of claim 1 , wherein the plurality of titanium nitride layers comprise:a first titanium nitride layer having a first plurality of grain boundaries; anda second titanium nitride layer disposed onto the first titanium nitride layer and having a second plurality of grain boundaries that are discontinuous with the first plurality of grain boundaries.3. The integrated chip of claim 1 , wherein the titanium nitride film further comprises a metal under-layer that is not titanium nitride and which is disposed between the semiconductor substrate and the plurality of titanium nitride layers.4. The integrated chip of claim 3 , wherein the metal under-layer is titanium.5. The integrated chip of claim 1 , ...

Code Activation Device

The present disclosure illustrates a code activation device used to transmit an activation signal to a back-end device, so as to activate the back-end device. The code activation device comprises a sensing module and a processing module. The sensing module comprises a sensor unit, and the sensor unit generates sensing signals according to a preset action of a trigger object. The processing module connected to the sensing module receives the sensing signals, generates a sensing beat according to interval periods between the sensing signals, and determines whether the sensing beat matches a preset beat, wherein the processing module generates the activation signal when the sensing beat matches the preset beat. 1. A code activation device , used to transmit an activation signal to a back-end device , so as to activate the back-end device , wherein the code activation device comprises:a sensing module, comprising a sensor unit, the sensor unit generates sensing signals according to a preset action of a trigger object; anda processing module, connected to the sensing module, receiving the sensing signals, generating a sensing beat according to interval periods between the sensing signals, and determining whether the sensing beat matches a preset beat, wherein the processing module generates the activation signal when the sensing beat matches the preset beat.2. The code activation device according to claim 1 , wherein the sensor unit is an infrared ray sensor unit.3. The code activation device according to claim 1 , wherein the sensor unit is a piezoelectric sensor unit.4. The code activation device according to claim 1 , wherein the sensor unit is a touch sensor unit or a beat sensor unit.5. The code activation device according to claim 1 , wherein the processing module comprises a transmitting unit for receiving the sensing signals and transmitting the activation signal to the back-end device.6. The code activation device according to claim 1 , wherein the processing ...

RRAM CELL BOTTOM ELECTRODE FORMATION

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved. 1. A method of forming a resistive random access memory (RRAM) cell , comprising:forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process that forms at least a top portion of the bottom electrode;forming a dielectric data storage layer having a variable resistance onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode;forming a top electrode over the dielectric data storage layer; andforming an upper metal interconnect layer over the top electrode.2. The method of claim 1 , wherein forming the bottom electrode comprises:depositing a first bottom electrode layer using a physical vapor deposition (PVD) process; anddepositing a second bottom electrode layer onto and in direct contact with the first bottom electrode layer using the ALD process.3. The method of claim 2 , wherein the second bottom electrode layer has a thickness in a range of between approximately 15 angstroms and approximately 30 angstroms.4. The method of claim 1 , wherein the bottom electrode comprises ...

Bandwidth adjustment method and associated bandwidth adjustment circuit and phase recovery module

A bandwidth adjustment method includes obtaining an upper bandwidth limit and a lower bandwidth limit according to an initial upper bandwidth limit and an initial lower bandwidth limit, obtaining an optimum bandwidth according to the upper bandwidth limit and the lower bandwidth limit, and adjusting the initial upper bandwidth limit and the initial lower and width limit according to the optimum bandwidth.

CARRIER FREQUENCY OFFSET ESTIMATION DEVICE AND CARRIER FREQUENCY OFFSET ESTIMATION METHOD

A carrier frequency offset (CFO) estimation device includes an echo cancelling unit, performing echo cancellation on an input signal to generate an echo-cancelled signal; and a CFO estimating unit, performing CFO estimation on the echo-cancelled signal to generate an estimated CFO. 1. A carrier frequency offset (CFO) device , comprising:an echo cancelling unit, performing echo cancellation on a received signal to generate an echo-cancelled signal; anda CFO estimating unit, performing CFO estimation on the echo-cancelled signal to generate an estimated CFO.2. The CFO estimation device according to claim 1 , wherein the echo cancelling unit is a whitening filter.3. The CFO estimation device according to claim 2 , wherein the whitening filter comprises:a shift register, storing a plurality of symbols of the received signal;a first multiplication unit, respectively multiplying the plurality of symbols by a plurality of coefficients to generate a plurality of first products;a summing unit, summing up the plurality of first products to generate a product sum; anda subtraction unit, performing a subtraction calculation according to the product sum and a selected symbol of the received signal to generate the echo-cancelled signal.4. The CFO estimation device according to claim 3 , further comprising:a coefficient providing unit, updating the plurality of coefficients according to the echo-cancelled signal and the plurality of symbols to generate a plurality of updated coefficients.5. The CFO estimation device according to claim 3 , wherein the coefficient providing unit comprises:a conjugate unit, performing a conjugate operation on the plurality of symbols to generate a plurality of conjugate symbols;a second multiplication unit, respectively multiplying the plurality of conjugate symbols by the echo-cancelled signal and a step size to generate a plurality of coefficient adjustment values; andan adding unit, adding the plurality of coefficient adjustment values to the ...

Equalization enhancing module, demodulation system and equalization enhancing method

An equalization enhancing module includes: a multiplication unit, multiplying a plurality of equalized signals by a scaling coefficient to obtain a plurality of scaled signals; a determination unit, coupled to the multiplication unit, determining whether the plurality of scaled signals are located in a predetermined region to generate a plurality of determination results; a ratio calculating unit, coupled to the determination unit, calculating an inner ratio associated with a ratio of the plurality of scaled signals located in the predetermined region; and a coefficient calculating unit, coupled to the ratio calculating unit, calculating the scaling coefficient according to the inner ratio.

Phase calibration method and associated phase locked loop circuit

A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.

Variable linked braking system controlled by motorcycle speed

A variable linked braking system controlled by motorcycle speed includes a brake master cylinder; a hydraulic pressure proportion variable valve connected to the brake master cylinder by an oil path; front and rear brake units connected to the hydraulic pressure proportion variable valve by first and second oil paths, respectively; a hydraulic pressure proportion controller for controlling the hydraulic pressure proportion variable valve; a motorcycle speed sensor for converting a sensed motorcycle speed into a speed signal and sending the speed signal to the hydraulic pressure proportion controller; and a brake switch for starting the brake master cylinder and sending a brake signal to the hydraulic pressure proportion controller for controlling the hydraulic pressure distribution proportion of the hydraulic pressure proportion variable valve so that the ratio of braking force of the front brake unit to braking force of the rear brake unit increases with the motorcycle speed.

DECODING CIRCUIT APPLIED TO MULTIMEDIA APPARATUS AND ASSOCIATED DECODING METHOD

A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals. 1. A decoding circuit , applied to a multimedia apparatus , for decoding encoded data to generate system information , the decoding circuit comprising:a plurality of processing circuits, individually processing the encoded data to generate a plurality of processed signals, the plurality of processing circuits respectively corresponding to a plurality of bit combinations of a part of the system information; anda determination circuit, coupled to the plurality of processing circuits, determining the system information according to the plurality of processed signals.2. The decoding circuit according to claim 1 , wherein the part of the system information comprises N bits claim 1 , and a quantity of the plurality of processing circuits is a square of N.3. The decoding circuit according to claim 1 , wherein the multimedia apparatus is compliant with a Digital Video Broadcasting (DVB) system claim 1 , and the encoded data is a physical layer signaling (PLS) code.4. The decoding circuit according to claim 3 , wherein the part of the system information comprises a first bit and a second bit claim 3 , the first bit is for indicating that the encoded data is compliant with one of a Digital Video Broadcasting-Satellite Second Generation (DVB-S2) system and a Digital Video Broadcasting-Satellite Second Generation Extension (DVB-S2X) system claim 3 , and the second bit is for indicating whether the encoded data includes pilot data.5. The decoding circuit ...

VARIABLE LINKED BRAKING SYSTEM CONTROLLED BY MOTORCYCLE LEAN ANGLE

A variable linked braking system controlled by motorcycle lean angle includes a brake master cylinder; a hydraulic pressure proportion variable valve connected to the brake master cylinder; a front brake unit and a rear brake unit, both connected to the hydraulic pressure proportion variable valve; a hydraulic pressure proportion controller for controlling the hydraulic pressure proportion variable valve; a motorcycle lean angle sensor for sensing a motorcycle lean angle and sending a signal thereof to the hydraulic pressure proportion controller; and a brake switch for starting the brake master cylinder and sending a brake signal to the hydraulic pressure proportion controller for controlling the hydraulic pressure proportion variable valve so that the braking force ratio of the front brake unit to the rear brake unit decreases as the motorcycle lean angle increases, thereby enhancing the stability and traction of a motorcycle being braked in a turn. 1. A variable linked braking system controlled by motorcycle lean angle , comprising:a brake master cylinder;a hydraulic pressure proportion variable valve connected to the brake master cylinder by an oil path;a front brake unit connected to the hydraulic pressure proportion variable valve by a first oil path;a rear brake unit connected to the hydraulic pressure proportion variable valve by a second oil path;a hydraulic pressure proportion controller for controlling a hydraulic pressure distribution proportion of the hydraulic pressure proportion variable valve;a motorcycle lean angle sensor for sensing a motorcycle lean angle, converting the sensed motorcycle lean angle into a lean angle signal, and sending the lean angle signal to the hydraulic pressure proportion controller; anda brake switch for starting the brake master cylinder and sending a brake signal to the hydraulic pressure proportion controller, the hydraulic pressure proportion controller controlling the hydraulic pressure distribution proportion of the ...

ELECTRONIC CONTINUOUSLY VARIABLE TRANSMISSION (ECVT) SYSTEM AND CONTROL METHOD FOR THE SAME

An electronic continuously variable transmission (ECVT) system applicable to a motorcycle includes a first speed sensor, second speed sensor, continuously variable transmission (CVT) and control unit. The control unit receives a user control signal and accordingly controls a speed-changing state of the CVT. While the motorcycle is operating in a manual-operation mode, the control unit predicts, according to the user control signal, a first speed signal sent from the first speed sensor, and a second speed signal sent from the second speed sensor, whether the next gear indicated by the shift request signal will cause the motorcycle to move unsteadily. If so, the control unit ignores the shift request signal and refuses to perform gear shifting. If not, the control unit sends at least a shift control signal to the CVT so that the CVT performs gear shifting. 1. An electronic continuously variable transmission (ECVT) system , applicable to a motorcycle , the ECVT system comprising:a first speed sensor, disposed in a front portion of the motorcycle, to sense a front-wheel speed of the motorcycle and send a first speed signal;a second speed sensor, disposed in a rear portion of the motorcycle, to sense a rear-wheel speed of the motorcycle and send a second speed signal;a continuously variable transmission (CVT) for transforming and transmitting a driving power of an engine of the motorcycle to a rear wheel of the motorcycle; anda control unit, electrically coupled to the first speed sensor, the second speed sensor and the CVT, to receive a user control signal and accordingly control a speed-changing state of the CVT, predict, according to the shift request signal, the first traveling speed signal and the second traveling speed signal, whether a next gear indicated by the shift request signal will cause the motorcycle to move unsteadily,', 'ignore the shift request signal such that the CVT does not perform gear shifting if the control unit predicts that the next gear ...

Signal detection method and signal receiving device for enhancing reliability of code rate search

A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

Manufacturing method for a car safety seat

A manufacturing method for a car safety seat includes the following steps: providing a mold and disposing a main body of the car safety seat into the mold, and injecting a foam material into a cavity of the mold and foaming the foam material so as to form a flexible layer integrated with the main body. A pressure in the cavity is between 1.5 bar and 5.0 bar. The manufacturing method disposes the main body into the mold and directly forms a flexible layer on the main body, so that the flexible layer ensures safety and comfort of the car safety seat while saves the necessity to dispose a seat pad or a cushion and fixing structures on the main body, and thereby reduces the cost and the work-hour of assembly, and the overall weight of the car safety seat can be reduced by omitting the fixing structures.

Echo Cancellation Circuit, Receiver Applied to Digital Communication System and Echo Cancellation Method

An echo cancellation circuit includes: a delay module, receiving an input signal and delaying the input signal to generate a plurality of delayed signals; a multiplication module, multiplying the plurality of delayed signals by a plurality of coefficients to generate a plurality of multiplication results, respectively; a summing circuit, performing a summation on the plurality of multiplication results to generate a summation signal; a subtraction circuit, receiving a first delay signal and generating a subtracted signal according to the first delayed signal and the summation signal; and a coefficient calculating circuit, calculating the plurality of coefficients according to the subtracted signal. The echo cancellation circuit outputs an output signal as the subtracted signal. 1. An echo cancellation circuit , applied to a receiver to cancel a pre-echo signal from a channel , comprising:a delay module, receiving an input signal, delaying the input signal to generate a plurality of delayed signals;a multiplication module, coupled to the delay module, multiplying the plurality of delayed signals by a plurality of coefficients to generate a plurality of multiplication results, respectively;a summation circuit, coupled to the multiplication module, performing a summation on the plurality of multiplication results to generate a summation signal;a subtraction circuit, coupled to the delay module and the summation circuit, receiving a first delayed signal among the plurality of delayed signals, generating a subtracted signal according to the first delayed signal and the summation signal; anda coefficient calculating circuit, coupled to the subtraction circuit, calculating the plurality of coefficients according to the subtracted signal.2. The echo cancellation circuit according to claim 1 , wherein the delay module comprises a plurality of buffers respectively outputting the plurality of delayed signals.3. The echo cancellation circuit according to claim 2 , wherein the ...

MANUFACTURING METHOD FOR A CHILD CARRYING DEVICE

A manufacturing method for a child carrying device includes the following steps: providing a mold and disposing a main body of the child carrying device into the mold, and injecting a foam material into a cavity of the mold and foaming the foam material so as to form a flexible layer integrated with the main body. The manufacturing method disposes the main body into the mold and directly forms a flexible layer on the main body, so that the flexible layer ensures safety and comfort of the child carrying device while saves the necessity to dispose a seat pad or a cushion and fixing structures on the main body, and thereby reduces the cost and the work-hour of assembly, and the overall weight of the child carrying device can be reduced by omitting the fixing structures. 1. A manufacturing method for a child carrying device , the manufacturing method comprising:providing a mold and disposing a main body of the child carrying device into the mold; andinjecting a foam material into a cavity of the mold and foaming the foam material in the cavity of the mold so as to form a flexible layer integrated with the main body, wherein an average particle diameter of the foam material after being foamed is from 1 mm to 10 mm.2. The manufacturing method of claim 1 , wherein the pressure in the cavity is from 2.0 bar to 4.0 bar during the foaming process.3. The manufacturing method of claim 1 , wherein a wall thickness of the main body is substantially 1.5 mm.4. The manufacturing method of claim 1 , further comprising:injecting a vapor into the cavity of the mold after injecting the foam material into the cavity, for combining the foam material with the main body by temperature and the pressure.5. The manufacturing method of claim 1 , further comprising:cooling the formed flexible layer; anddemolding the mold to draw the child carrying device comprising the main body and the flexible layer manually or by an ejector pin.6. The manufacturing method of claim 5 , further comprising: ...

PHASE COMPENSATION METHOD AND ASSOCIATED PHASE-LOCKED LOOP MODULE

A phase compensation method applied to a phase-locked loop (PLL) module of a communication device includes determining to output one of a maximum likelihood (ML) phase to an oscillator of the PLL module and a data-aided (DA) phase error to a filter of the PLL module according to an input signal. The ML phase is a phase generated from estimating known data in the input signal by using a ML method, and the DA phase error is a phase error generate from estimating the known data in the input signal by using a DA method. 1. A phase compensation method , applied to a phase-locked loop (PLL) module of a communication device , comprising:determining, according to an input signal, to output one of a maximum likelihood (ML) phase to an oscillator of the PLL module and a data-aided (DA) phase error to a filter of the PLL module;wherein, the ML phase is a phase generated from estimating known data in the input signal by a ML method, and the DA phase error is a phase error generated from estimating the known data in the input signal by a DA method.2. The phase compensation method according to claim 1 , wherein the step of determining to output one of the ML phase to the oscillator of the PLL module and the DA phase error to the filter of the PLL module comprises:determining whether a signal-to-noise ratio (SNR) of the input signal is smaller than an SNR threshold; andoutputting the DA phase error to the filter when the SNR of the input signal is smaller than the SNR threshold.3. The phase compensation method according to claim 2 , wherein the step of determining to output one of the ML phase to the oscillator of the PLL module and the DA phase error to the filter of the PLL module further comprises:outputting the ML phase to the oscillator when the SNR of the input signal is not smaller than the SNR threshold.4. The phase compensation method according to claim 2 , further comprising:determining whether a phase noise of the input signal is smaller than a phase noise threshold; ...

HEAD MOUNTED DEVICE

A head mounted device for a helmet includes a connection module, a flexible bracket, a power supply seat and a function module. While the flexible bracket is moved relative to the connection module, a position of the power supply seat relative to the helmet is adjusted. While the function module is moved relative to the power supply seat, an orientation of the function unit is adjusted. 1. A head mounted device for a helmet , the head mounted device comprising:a connection module comprising a connection part and a fixing part, wherein the connection part is detachably connected with the helmet, and the fixing part is connected with the connection part;a flexible bracket locked on the helmet and adjustably connected with the fixing part;a power supply seat located at a first end of the flexible bracket; anda function module adjustably connected with the power supply seat, wherein the function module comprises a function unit,wherein while the flexible bracket is moved relative to the connection module, a position of the power supply seat relative to the helmet is adjusted, wherein while the function module is moved relative to the power supply seat, an orientation of the function unit is adjusted.2. The head mounted device according to claim 1 , wherein the head mounted device further comprises an energy storage module claim 1 , wherein the energy storage module is located at a second end of the flexible bracket that is opposed to the power supply seat claim 1 , and the energy storage module is electrically connected with the power supply seat to provide electricity to the function module.3. The head mounted device according to claim 1 , wherein the power supply seat comprises an accommodation space claim 1 , and the function module is accommodated within the accommodation space.4. The head mounted device according to claim 3 , wherein the power supply seat further comprises a first metal contact claim 3 , and the first metal contact is disposed within the ...

NETWORK SWITCH AND ABNORMITY DETECTING METHOD

A network switch is configured to receive packet data. The network switch includes a memory and a processor. The memory is configured to store an access control list and an abnormity detecting program, filter the packet data according to the access control list, and perform an abnormity detecting procedure on the packet data according to the abnormity detecting program. When at least one abnormity event occurs in one of a plurality of time intervals, a counting value increases. When the counting value reaches a counting threshold value, the memory sends an abnormity notification to the processor and the processor performs an abnormity processing procedure on the packet data. 1. A network switch configured to receive packet data , wherein the network switch comprises:a memory configured to store an access control list and an abnormity detecting program, filter the packet data according to the access control list, and perform an abnormity detecting procedure on the packet data according to the abnormity detecting program; anda processor, wherein when at least one abnormity event occurs in one of a plurality of time intervals, a counting value increases,wherein when the counting value reaches a counting threshold value, the memory sends an abnormity notification to the processor and the processor performs an abnormity processing procedure on the packet data.2. The network switch of claim 1 , wherein the abnormity event is that a flow value of the packet data reaches an upper limit value.3. The network switch of claim 2 , further comprising:at least one register configured to store a length of each of the time intervals, the counting threshold value, or the upper limit value.4. The network switch of claim 3 , wherein the length of each of the time intervals claim 3 , the counting threshold value claim 3 , or the upper limit value is updated according to a setting command corresponding to an input of a user.5. The network switch of claim 1 , wherein the processor is ...

RRAM cell bottom electrode formation

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Bridgeless power factor correction converter with zero current detection circuit

A critical conduction mode (CRM) bridgeless PFC system includes a PFC converter connected to an Alternating Current (AC) source, a zero-current detection (ZCD) circuit for detecting a zero-current state of the PFC converter, a zero-voltage switching (ZVS) detection circuit, and a processor. Voltage divider circuits receive a first voltage and a supply voltage from the PFC converter and the AC source. The ZCD circuit receives divided voltages generated by the voltage divider circuits and generates a ZCD signal. The ZCD signal is used by the ZVS detection circuit to generate a ZVS flag, which is used by the processor to control switching of first through fourth transistors of the PFC converter.

Screwdriver with Extendable Shaft and Bit Storage

A screwdriver includes a shank, a ratchet assembly, and a handle. The shank includes a shank extender that in an extended position lengthens the shank and in a retracted position is stored within the handle of the screwdriver. The ratchet assembly includes a knob and is configured to drive in the same direction the knob is turned. The screwdriver includes a locking mechanism to prevent unwanted movement of the shank between the extended and retracted positions. The handle of the screwdriver includes a storage space to hold alternative screwdriver bits and a stabilizing component to decrease movement of the handle when the storage portion is in an extended or open position. In a closed position the handle surrounds the alternate bits and in an open position the alternate bits are exposed.

Piezoelectric speaker

Pyrazolo[4,3-c]quinoline derivatives inhibition β-glucuronidase

本發明提供一種新穎的吡唑並[4,3- c ]喹啉衍生物，對微生物β-葡萄醣醛酸酶展現專一地抑制活性，以提供有效的活性以預防癌症的化療導致的腹瀉(CID)。因此，本發明的化合物可作為(1)抑制化療佐劑以預防化療導致的腹瀉(CID)並增加癌症的化療效果；(2)預防致癌物質誘發的大腸癌之健康食品補充劑。

Piezoelectric loudspeaker

本發明係揭露一種壓電喇叭，其包含發聲基板、共振音箱、懸邊結構及反射音箱。發聲基板包含壓電陶瓷元件。共振音箱具有第一開口，第一開口包含第一承載部，發聲基板設於第一承載部，發聲基板與共振音箱之間形成共振腔體。懸邊結構設於第一承載部與發聲基板之間。反射音箱具有第二開口及反射輸出口，第二開口包含第二承載部，共振音箱設於第二承載部，共振音箱與反射音箱之間形成反射腔體，且反射腔體連通反射輸出口。

USB connector

Color light guide panel and liquid crystal display

A color light guide panel, suitable for differentiating an incident light into multiple color lights is provided. The color light guide panel includes a substrate and a color light output structure. The substrate has multiple pixel regions, and the color light output structure is disposed in each of the pixel regions. The color light output structure includes a first nano-pattern, a second nano-pattern and a third nano-pattern. The incident light is scattered by the first nano-pattern for producing a first color light, scattered by the second nano-pattern for producing a second color light, and scattered by the third nano-pattern for producing a third color light. The color light guide panel can output uniform and high luminous first, second and third color light. Moreover, a liquid crystal display device having the above color light output structure is also provided.

Herstellungsverfahren für einen Fahrzeugkindersitz

Herstellungsverfahren für einen Fahrzeugkindersitz (1), wobei das Herstellungsverfahren umfasst:Bereitstellen einer Form und Anordnen eines Hauptkörpers (11) des Fahrzeugkindersitzes (1) in der Form; undEinspritzen eines Schaumstoffs in einen Hohlraum der Form und Aufschäumen des Schaumstoffs im Hohlraum der Form zum Bilden einer flexiblen Schicht (12), die mit dem Hauptkörper (11) integriert ist, wobei ein Druck im Hohlraum der Form während eines Aufschäumungsprozesses zwischen 1,5 bar und 5,0 bar liegt.

HDMI device and power-saving method for immediately switching HDMI ports

A power-saving method for an HDMI device is provided. The method includes detecting color depth information of video data from an HDMI source which is connected to the HDMI port, deriving a horizontal length for each line by fragment of a picture frame according to the color depth information, generating a plurality of synchronization signals according to the horizontal length for each line by fragment, and powering on the HDMI port, according to the synchronization signals, for a predetermined time period to obtain encrypted information from the HDMI source, and powering off the HDMI port after the predetermined time period.

Decoding circuit applied to multimedia apparatus and associated decoding method

A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.

Configurable control loop arrangement

A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

Head mounted device

A head mounted device for a helmet includes a connection module, a flexible bracket, a power supply seat and a function module. While the flexible bracket is moved relative to the connection module, a position of the power supply seat relative to the helmet is adjusted. While the function module is moved relative to the power supply seat, an orientation of the function unit is adjusted.

Configurable control loop arrangement

A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

信號處理裝置及信號處理方法

本案所提供之信號處理裝置包含一起點決定模組、一搜尋模組及一符號率決定模組，用以接收對應於一原始信號之一頻譜線。該起點決定模組係用以找出該頻譜線中之一最大能量，並根據該最大能量決定至少一搜尋起點。該搜尋模組係用以自該至少一搜尋起點沿著該頻譜線往能量較低處搜尋符合一預設條件之至少一最小能量。該符號率決定模組係用以根據該至少一最小能量決定該原始信號之符號率。

Control method and time aware bridge device for seamless precision time protocol

A control method and a time aware bridge device for a seamless Precision Time Protocol (PTP) are provided. The control method includes: utilizing the time aware bridge device to pre-configure a first control signal source as a master control signal source, and pre-configure a second control signal source as a backup control signal source; utilizing the time aware bridge device to determine whether one or more packets from the master control signal source conform to at least one predetermined rule to generate a determination result; and selectively configuring the second control signal source as the master control signal source according to the determination result.

Color light guide panel and liquid crystal display

A color light guide panel, suitable for differentiating an incident light into multiple color lights is provided. The color light guide panel includes a substrate and a color light output structure. The substrate has multiple pixel regions, and the color light output structure is disposed in each of the pixel regions. The color light output structure includes a first nano-pattern, a second nano-pattern and a third nano-pattern. The incident light is scattered by the first nano-pattern for producing a first color light, scattered by the second nano-pattern for producing a second color light, and scattered by the third nano-pattern for producing a third color light. The color light guide panel can output uniform and high luminous first, second and third color light. Moreover, a liquid crystal display device having the above color light output structure is also provided.

Steuerungsverfahren und time-aware-Bridge-Vorrichtung für ein übergangsloses Präzisionszeitprotokoll

Ein Steuerungsverfahren und eine time-aware-Bridge-Vorrichtung für ein übergangsloses Präzisionszeitprotokoll, PTP, werden zur Verfügung gestellt. Das Steuerungsverfahren umfasst: Verwenden der time-aware-Bridge-Vorrichtung, um eine erste Steuerungssignalquelle als eine Master-Steuerungssignalquelle vorzukonfigurieren, und eine zweite Steuerungssignalquelle als eine Ersatz-Steuerungssignalquelle vorzukonfigurieren (410); Verwenden der time-aware-Bridge-Vorrichtung, um festzustellen, ob ein oder mehrere Pakete von der Master-Steuerungssignalquelle mit mindestens einer vorbestimmten Regel konform sind, um ein Feststellungsergebnis zu generieren (420); und selektives Konfigurieren der zweiten Steuerungssignalquelle als die Master-Steuerungssignalquelle gemäß dem Feststellungsergebnis (430).

Signal receiving apparatus and signal processing method thereof

A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.

オートバイ車速制御の可変式連動ブレーキシステム

【課題】オートバイのブレーキをかけたときの安定性を高める、オートバイ車速制御の可変式連動ブレーキシステムを提供する。【解決手段】オートバイ車速制御の可変式連動ブレーキシステムは、マスターシリンダ１、油圧比率可変式弁体２、前ブレーキユニット３、後ブレーキユニット４、油圧比率制御器５、オートバイ車速センサ６及びブレーキスイッチ８を備える。油圧比率可変式弁体２は、油路１１を介してマスターシリンダ１に接続される。前ブレーキユニット３は、第１の油路３１を介して油圧比率可変式弁体２に接続される。後ブレーキユニット４は、第２の油路４１を介して油圧比率可変式弁体２に接続される。油圧比率制御器５は、油圧比率可変式弁体２の油圧分配比率を制御する。オートバイ車速センサ６は、オートバイ車速６１を油圧比率制御器５へ電気的に伝送する。【選択図】図１

Channel hiatus correction method and HDMI device

A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Methods and compostions for inhibiting coronaviral replication

Provided herein are methods and compositions for inhibiting p97, for the treatment of a coronavirus infection in a subject, or a symptom thereof. Upon treatment, the coronavirus infection, or a symptom thereof is reduced in the subject.

Herstellungsverfahren für einen Fahrzeugkindersitz

Ein Herstellungsverfahren für einen Fahrzeugkindersitz (1) umfasst die folgenden Schritte: Bereitstellen einer Form und Anordnen eines Hauptkörpers (11) des Fahrzeugkindersitzes (1) in der Form, und Einspritzen eines Schaumstoffs in einen Hohlraum der Form und Aufschäumen des Schaumstoffs zum Bilden einer flexiblen Schicht (12), die in den Hauptkörper (11) integriert ist. Ein Druck im Hohlraum liegt zwischen 1,5 bar und 5,0 bar. Das Herstellungsverfahren ordnet den Hauptkörper (11) in der Form an und bildet eine flexible Schicht (12) direkt auf dem Hauptkörper (11), sodass die flexible Schicht (12) die Sicherheit und den Komfort des Fahrzeugkindersitzes (1) gewährleistet, ohne dass ein Sitzpolster oder Kissen und Fixierstrukturen am Hauptkörper (11) angeordnet werden müssen, und reduziert dadurch die Kosten und die Arbeitszeit der Fertigung, und zudem kann das Gesamtgewicht des Fahrzeugkindersitzes (1) durch den Wegfall der Fixierstrukturen reduziert werden.

Manufacturing method for a car safety seat

Semiconductor device and method of forming the same

A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Screwdriver with extendable shaft and bit storage

A screwdriver includes a shank, a ratchet assembly, and a handle. The shank includes a shank extender that in an extended position lengthens the shank and in a retracted position is stored within the handle of the screwdriver. The ratchet assembly includes a knob and is configured to drive in the same direction the knob is turned. The screwdriver includes a locking mechanism to prevent unwanted movement of the shank between the extended and retracted positions. The handle of the screwdriver includes a storage space to hold alternative screwdriver bits and a stabilizing component to decrease movement of the handle when the storage portion is in an extended or open position. In a closed position the handle surrounds the alternate bits and in an open position the alternate bits are exposed.

Ｃｖｔシステム及びその制御方法

【課題】ユーザが手動で操作できる手動モードを有し、ユーザが安全に運転することができる、ＣＶＴシステム及びその制御方法を提供する。 【解決手段】ＣＶＴシステム１０は、第１の車速計１１０、第２の車速計１２０、無段変速装置１３０及び制御ユニット１４０を備えるとともに、自動二輪車に用いる。第１の車速計１１０は、自動二輪車の前側に配設され、自動二輪車の前輪速度を検出して第１の車速信号を出力する。第２の車速計１２０は、自動二輪車の後側に配設され、自動二輪車の後輪速度を検出して第２の車速信号を出力する。無段変速装置１３０は、自動二輪車のエンジンの動力を変換して自動二輪車の後輪へ動力を伝達する。制御ユニット１４０は、第１の車速計１１０、第２の車速計１２０及び無段変速装置１３０と電気的に接続され、ユーザ制御信号を受信し、無段変速装置１３０の変速状態を制御する。 【選択図】図１

Network device and network connecting method for building up network connection via high definition multimedia interface