ELEKTRONIKGEHÄUSE MIT LEITERRAHMEN MIT VERBESSERTER ADHAESION

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Elektrischer Schaltungsapparat

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Druckkontakt-Halbleiterbauelement mit Blindsegment

Jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) wird als Blindsegment verwendet. Eine obere Oberfläche eines vorstehenden Teils (OMPP, IMPP) jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) ist mit einer Isolierschicht (1S + 1P) bedeckt, und zwischen einer oberen Oberfläche der Isolierschicht (1S + 1P) und einer unteren Oberfläche (2BS) einer Katodenentlastungsplatte ist ein Abstand (CL) vorhanden. Alle anderen Segmente (SG), mit Ausnahme der äußersten und der innersten, besitzen einen vorstehenden Teil, auf dem eine Katodenelektrode (1K-AL) ausgebildet ist. Die Dicke (T1) der Katodenelektrode (1K-AL) ist so bemessen, dass eine obere Oberfläche der Katodenelektrode (1K-AL) mit der unteren Oberfläche (2BS) der Katodenentlastungsplatte in Kontakt kommen kann.

Verfahren zum Verbinden eines Chips mit einem Substrat unter Verwendung einer isotropen Verbindungsschicht und Verbundsystem aus Chip und Substrat

The invention relates to a method and a system whereby a chip (1) is coupled to a substrate (4), said chip having at least two bond pads (2) arranged on the same side at a distance from each other, and said substrate having at least two contact bond pads (5) arranged on the same side. An isotropic adhesive is applied to the side of the chips (1) where the bond pads (2) are arranged, or to the side of the substrate (4) where the contact bond pads (5) are arranged. The chip (1) and the substrate (4) are aligned in relation to each other so that the bond pads (2) of the chip (1) and the contact bond pads (5) of the substrates (4) are opposite each other. After the coupling, which occurs by bringing together the chip (1) and the substrate (2), a totally flat isotropic coupling layer (3) of adhesive is formed.

Electrical assembly comprises cooler structure and electrical component on metal-ceramic substrate having electrical module, where electrical module comprises two metal-ceramic substrates

Electrical assembly comprises cooler structure and an electrical component (6) on a metal-ceramic substrate (4,5) having electrical module. The electrical module comprises two metal-ceramic substrates, where each substrate includes a ceramic layer (7,10), which are provided with partially structured metal plating (9,12). An active cooler (2,3) and an electrical component are also provided between two metal-ceramic substrates, which are thermally connected.

Copper wire for bonding a semiconductor device

The present invention eliminates the problems associated with the use of oxygen-free copper and other high-purity copper materials as bonding wires. At least one rare earth element, or at least one element selected from the group consisting of Mg, Ca, Ti, Zr, Hf, Li, Na, K, Rb and Cs, or the combination of at least one rare earth element and at least one elemented selected from the above-specified group is incorporated in high-purity copper as a refining component in an amount of 0.1-100 ppm on a weight basis, and the high-purity copper is subsequently refined by zone melting. The very fine wire drawn from the so refined high-purity copper has the advantage that it can be employed in high-speed ball bonding of a semiconductor chip with a minimum chance of damaging the bonding pad on the chip by the ball forming at the tip of the wire.

A method and apparatus for forming an under bump metallization structure

Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350 {C to approximately 550 {C.

TIN SILVER BRAZING DENTS DURING THE ELECTRONICS PRODUCTION

SEMICONDUCTOR RADIATION EMITTER PACKING

Lead frames with improved adhesion

METHOD OF WELDING OF CONNECTION WIRES TO MICROCIRCUIT CONTACTS

PHN.9872 10 27.4.81 "Method of forming a wire bond" A method of forming a wire bond between a contact place on an electronic microcircuit (17) and a connection conductor (18), in which a wire (6) of aluminium or an aluminium alloy is used which is passed through a capillary (5) in which a ball is formed at the end of the wire by means of a spark discharge between the wire (6) and an electrode (11), which spark discharge takes place in a protective gas atmosphere in which a first electric spark discharge is produced between two auxiliary electrodes (12, 13) as a result of which the protective gas is ionised and a plasma is formed, after which due to the low resistance in the plasma an electric spark discharge takes place between the electrode (11) and the wire (6) at a voltage between 25 V and 200 V, by which spark discharge a ball is formed at the end of the wire, while the wire is then bonded to a contact place on the electronic microcircuit and then to the connection conductor by means ...

HIGH SPEED, HIGH VOLTAGE TRANSISTOR

ELECTRONIC DEVICE PACKAGING

Signalumformungseinrichtung mit einem Körper aus Halbleitermaterial.

Verfahren zur Herstellung eines zusammengesetzten elektrischen Leiters

Raddrizzatore in miniatura

Verfahren zur Herstellung eines Kondensators und nach dem Verfahren hergestellter Kondensator

Verfahren zum Herstellen eines Metallüberzuges auf einem Molybdän enthaltenden Körper, nach diesem Verfahren hergestellter Körper und Verwendung eines solchen Körpers

Trägerkörper für einen Halbleiterkörper einer Halbleitervorrichtung und Verfahren zu seiner Herstellung

Halbleiterbauelement

PROCEDURE FOR GLUING ON CONSTRUCTION UNITS A DOCUMENT OF MEANS THIXOTROPEN OF MATERIAL.

PROCEDURE FOR THE PRODUCTION OF A WIRE COMMUNICATION.

PROCEDURE FOR THE PRODUCTION OF FINE WIRE AND DEVICE FOR ITS EXECUTION.

Purifying wire from a Gold-Legierung, procedure for its production and its use.

Purifying wire from a Gold-Legierung, procedure for its production and its use.

CONTACT UNIT

RF-coupled digital isolator

An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second groundthat is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.

半导体模块

... 本发明在其上以层叠方式安装有二个半导体芯片的半导体模块中，实现了上部半导体芯片的下表面接地电极的接地增强和小型化。下部半导体芯片被固定到形成在模块板上表面中的凹陷底部，且上部半导体芯片被固定到由形成在凹陷周围模块板上表面上的导体制成的支持体的上表面。外部电极端子和散热焊点被形成在模块板的下表面上。连接到散热焊点的多个通道被形成在凹陷底部中。支持体被形成在连接到散热焊点的通道上。散热焊点假设为接地电位。诸如芯片电阻器、芯片电容器、以及芯片固定线圈的类芯片电子部件，被安装在模块板的上表面上。半导体芯片被导电金属丝连接到模块板的布线。上部半导体芯片的下表面接地电极经由通道被连接到假设为接地电位的散热焊点。 ...

MANUFACTORING PROCESS OF FIELD-EFFECT TRANSISTORS

The method of depositing metal on layers of film-forming oxidizable metals and noble metal contacts provided with such connections[...]

Semiconductor device with multi-layered metal interconnections

METHODS OF MAKING SEMICONDUCTOR COMPONENTS

PERFECTIONNEMENTS AUX TRANSISTORS A EFFET DE CHAMP ET A LEUR FABRICATION

L'invention concerne un procédé de fabrication d'un transistor à effet de champ consistant, successivement, à former une couche 4 de matière semi-conductrice (par exemple GaAs) à la surface d'un premier substrat 1 en matière semi-conductrice (par exemple également GaAs), à former une électrode de goulot 7 sur une face de la couche active, à appliquer un second substrat 11 de matière isolante sur une face de cette structure, à éliminer le premier substrat, et à former les électrodes de cathode et d'anode sur la face de la couche active opposée à l'électrode de goulot. Facultativement, l'élimination du premier substrat par attaque corrosive sélective est facilitée par l'addition d'une couche intermédiaire 2 en GaAlAs entre le premier et le second substrats. Une seconde électrode de goulot pourra être formée sur la face de la couche active opposée à celle portant la première électrode de goulot. Le procédé convient particulièrement à la fabrication des T.E.C. pour hautes fréquences.

MANUFACTORING PROCESS OF FIELD-EFFECT TRANSISTORS AND TRANSISTORS THUS OBTAINED

SEMICONDUCTOR STORAGE UNIT, PROCESS FOR MANUFACTURING THE SAME, AND METHOD OF FORMING PACKAGE RESIN

반도체 기판 위에 형성된 트랜지스터층과, 트랜지스터층의 상방에 형성된 강유전체 커패시터층과, 강유전체 커패시터층의 상방에 형성된 배선층과, 패시베이션막(passivation film)을 구비하는 강유전체 커패시터이다. 또한, 강유전체 커패시터층과 패시베이션막과의 사이에, 수분 및 수소의 하층으로의 투과를 억제하는 배리어막이 적어도 １층 형성되고, 패시베이션막은 노볼락 수지를 함유하는 것을 특징으로 한다. A ferroelectric capacitor comprising a transistor layer formed on a semiconductor substrate, a ferroelectric capacitor layer formed above the transistor layer, a wiring layer formed above the ferroelectric capacitor layer, and a passivation film. Further, between the ferroelectric capacitor layer and the passivation film, at least one barrier film for suppressing the permeation of moisture and hydrogen to the lower layer is formed, and the passivation film contains a novolak resin. 노볼락 수지, 패시베이션막, 강유전체 커패시터 Novolak Resin, Passivation Film, Ferroelectric Capacitor

METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION BARRIER, CAPABLE OF REDUCING THE DIFFUSION OF THE THERMAL AGITATIONS OF THE BOTTOM CONDUCTOR

PURPOSE: Methods for forming a semiconductor device are provided to minimize the diffusion of the thermal agitations of the bottom conductor and the upper part electric conductor which are formed on/under the diffusion barrier film. CONSTITUTION: The formation method of the semiconductor device includes the step of forming interlayer insulating film(102) on the substrate including a bottom conductor; the step of building up the opening which exposes the bottom conductor through the interlayer insulating film; the step of forming diffusion barrier film(120) including the plasma treatment layer and plasma raw layer(110) on the substrate having the opening. The diffusion barrier film is formed of the metal nitride through the metal-organic chemical vapor deposition. © KIPO 2009 ...

Condensateur utilisant une electrode de métal filmogène.

LED package

According to one embodiment, an LED package includes a first and a second lead frame, an LED chip and a resin body. The first and second lead frames are apart from each other. The LED chip is provided above the first and second lead frames, and has one terminal connected to the first lead frame and another terminal connected to the second lead frame. The wire connects the one terminal to the first lead frame. The resin body covers the first and second lead frames, the LED chip, and the wire. The first lead frame includes a base portion and a plurality of extending portions. As viewed from above, a bonding position of the wire is located inside one of polygonal regions connecting between roots of the two or more of the extending portions. An appearance of the resin body is a part of an appearance of the LED package.

Light emitting apparatus and method for manufacturing light emitting apparatus

A light emitting device in which the bottom face of a cup portion has an opening, one electrode of the light emitting device is connected electrically with the cup portion and the other electrode is connected electrically with a lead brought into the inner space of the cup portion from the outside through the opening of the cup portion. Since each electrode of the light emitting device can be connected electrically with the lead without using a bonding wire, occurrence of shadow or unevenness in light reflecting the shape of the bonding wire is prevented and luminous efficiency is enhanced. When the lead is not brought into the inner space of the cup portion from the outside but the lead on the outside of the cup portion and the electrode of the light emitting device are connected electrically by means of a bonding wire brought inside through the opening of the cup portion, the light emitted from the light emitting device is prevented from being intercepted partially by the bonding wire ...

Copper interconnection with conductive polymer layer and method of forming the same

A conductive polymer between two metallic layers, acts as a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

SEMICONDUCTOR DEVICE AND MEMORY MODULE

Semiconductor device

In a semiconductor device which is assembled by making use of a lead frame 1 with a heat radiation plate 3 in which the lead frame 1 and the heat radiation plate 3 made of copper or copper alloy are joined by an adhesive layer 2 formed on a surface of the heat radiation plate 3 and at least a part of the inner leads 1a of the lead frame 1 is applied of a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of inconveniences such as leakage and shorting due to ion migration can be prevented.

CIRCUIT BOARD INCORPORATING FUNCTIONAL ELEMENT, METHOD FOR MANUFACTURING THE CIRCUIT BOARD, AND ELECTRONIC DEVICE

A circuit board is provided with a functional element; a wiring board incorporating the functional element; and first and second wiring layers. The first and second wiring layers are formed on front and rear surface sections on the circuit board by sandwiching the functional element, and each of the first and second wiring layers includes at least one conductive layer. The surface of each pattern wiring of the outermost layer of the first wiring layer is exposed, and the surface of a first insulating layer, which insulates the pattern wirings of the outermost layer one from another, is protruded from the surface of each pattern wiring of the outermost layer. Each pattern wiring of the second wiring layer and an electrode terminal of the functional element are connected, and the surface of the second insulating layer insulating electrode terminals one from another and the surface of the electrode terminal adjacent to the surface of the second insulating layer are substantially within a same ...

ADHESION METHOD USING GRAY-SCALE PHOTOLITHOGRAPHY

A method for adhering substrates using gray-scale photolithography includes: (a) applying a photopatternable composition to a surface of a substrate to form a film; (b) exposing a portion of the film to radiation having a wavelength of from 150 to 800 nm through a gray-scale photomask to produce an exposed film having non-exposed regions covering at least a portion of the surface; (c) heating the exposed film for an amount of time such that the exposed regions are substantially insoluble in a developing solvent and the non–exposed regions are soluble in the developing solvent; (d) removing the non-exposed regions of the heated film with the developing solvent to form a patterned film; (e) heating the patterned film for an amount of time sufficient to form a cured patterned film having a surface; (f) activating the surface of the cured patterned film and a surface of an adherend; (g) contacting the activated. surface of the cured patterned film with the activated surface of the adherend.

ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME

Disclosed is an adhesive for connection of circuit members, which is interposed between a semiconductor chip having a projected connection terminal and a substrate provided with a wiring pattern, and pressed and heated therebetween for electrically connecting the connection terminal and the wiring pattern facing each other and bonding the semiconductor chip with the substrate. This adhesive for connection of circuit members contains a resin composition containing a thermoplastic resin, a crosslinkable resin and a curing agent for having the crosslinkable resin form a crosslinking structure, and complex oxide particles dispersed in the resin composition.

CONTACT NODE

Cette invention se rapporte à la fabrication de connexions à demeure lors de la production d'appareils à base de composants micro-électroniques et de dispositifs à semiconducteurs. Cette invention concerne plus précisément des noeuds de contact qui permettent d'assembler, entre autres, des structures de commutation multicouches pour des modules polycristallins, et de monter des cristaux de circuits intégrés à grande échelle sur une structure de commutation lors de la fabrication desdits modules polycristallins. Ce noeud de contact comprend au moins deux contacts métallisés qui sont connectés à des pistes électroconductrices (2, 6) disposées sur les surfaces de couches de commutation (3, 7). Ces couches sont à base d'un matériau diélectrique, sont superposées et sont connectées entre elles électriquement et mécaniquement par un matériau liant électroconducteur (8). Le noeud de contact consiste en une épissure qui relie, d'une part, le contact consistant en une plage métallisée (1) connectée ...

BRAZEABLE MATALLIZATIONS FOR DIAMOND COMPONENTS

A multilayer brazeable metallization structure for diamond components and method for producing it are described. The brazeable metallization finds particular application for the attachment of diamond components such as heat spreaders in electronic packages that incorporate high power semiconductor devices. In the present invention, a diamond component is provided with a multilayer coating of metals including a first layer of chromium for adhesion, a second barrier layer of a refractory metal for a barrier that may be alloyed with chromium, and a top layer of copper, silver or gold for wetting. This top layer is thick (greater than 5 microns), without sacrificing resistance to delamination, particularly at brazing conditions. The refractory metals for the second layer include tungsten, molybdenum, tantalum and niobium, or tungsten-chromium alloy. This multilayer metallization structure provides a robust interface between diamond and standard brazing alloys which are used to join the diamond ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

MICROPAD FOR BONDING AND A METHOD THEREFOR

A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Adhesion method using gray-scale photolithography

A method for adhering substrates using gray-scale photolithography includes: (a) applying a photopatternable corn-position to a surface of a substrate to form a film; (b) exposing a portion of the film to radiation having a wavelength of from 150 to 800 nm through a gray-scale photomask to produce an exposed film having non-exposed regions covering at least a portion of the surface; (c) heating the exposed film for an amount of time such that the exposed regions are substantially insoluble in a developing solvent and the nonexposed regions are soluble in the developing solvent; (d) removing the non-exposed regions of the heated film with the developing solvent to form a patterned film; (e) heating the patterned film for an amount of time sufficient to form a cured patterned film having a surface; (f) activating the surface of the cured patterned film and a surface of an adherend; (g) contacting the activated surface of the cured patterned film with the activated surface of the adherend.

TIN-SILVER SOLDER BUMPING IN ELECTRONICS MANUFACTURE

A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.

Power semiconductor switching devices, power converters, integrated circuit assemblies, Integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Wire bonding tool

A wire bonding tool is disclosed which comprises a metal or cermet stem and a silicon nitride containing tip. The tip is made of a silicon nitride containing composite which is electrically conducting. One end of the tip is fixedly mounted to one end of the stem.

Thermally and electrically conductive adhesive material and method of bonding with same

The present invention discloses a thermally and electrically conductive adhesive material comprising a hardened adhesive, and a non-solidified filler containing a liquid metal dispersed in separate spaced regions of the adhesive. The hardened adhesive provides a mechanical bond whereas the filler provides continuous thermal and electrical metal bridges, each bridge extending through the adhesive and contacting the bonded surfaces. The method includes (a) dispersing a filler containing a liquid metal into an unhardened adhesive, (b) contacting the unhardened adhesive and the filler in non-solidified state to the surfaces resulting in separate spaced regions of the non-solidified filler contacting both surfaces, and (c) hardening the adhesive.

Semiconductor device and radio communication device

A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.

Automatic wiring method for semiconductor package enabling design of high-speed wiring for semiconductor package with reduced labor

An automatic wiring method for a semiconductor package includes: a provisional wiring step for sequentially specifying a plurality of lines of the terminals from the innermost periphery to the outermost periphery of bonding pads, connecting the bonding pads to predetermined vias present on the specified line of the terminal with line segments, and provisionally determining a wiring route for each line of the terminal such that the line segment passes through between the vias in each line of the terminal at equal intervals; and a wiring formation step for forming the wiring based on a design rule such that the wiring pattern passes through between the lines of the terminals with uniform intervals between wires based on the provisionally wired wiring routes.

Circuit board

A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.

SEMICONDUCTOR DEVICE INCLUDING A DC-DC CONVERTER

The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

SEMICONDUCTOR CHIP, SEMICONDUCTOR MOUNTING MODULE, MOBILE COMMUNICATION DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR CHIP

A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device comprising the steps of (1) applying an underfill composition to a surface of a silicon wafer, (2) dicing the silicon wafer into chips, (3) positioning the chip, and (4) bonding the chip to the substrate, characterized in that the underfill composition consists of a first underfill composition and a second underfill composition, the step (1) comprises the steps of (i) applying the first underfill composition on the surface of the silicon wafer and then bringing the applied first underfill composition into a B-stage to form a layer of the first underfill composition having a thickness ranging from 0.5 to 1.0 time the height of the solder bump, and (ii) applying the second underfill composition on the B-stage first underfill composition layer and bringing the applied second underfill composition into a B-stage to form a layer wherein a total thickness of the B-stage first underfill composition and the B-stage second underfill composition ranges ...

Au BONDING WIRE FOR SEMICONDUCTOR ELEMENT

Issues to be solved Au bonding wire for semiconductor device should be provided in circumstances such as reducing the diameter of bonding wire to less than 23 µm, squashed ball with superior roundness should be formed and with strong tensile strength endurable against wire flow. Means as solution Au bonding wire for semiconductor device, consisting of Au matrix and functional additives, containing: said Au matrix alloy including 3-15 mass ppm of Be, 3-40 mass ppm of Ca, and 3-20 mass ppm of La and roundness of squashed ball said Au alloy is 0.95 -1.05.

Alloy layer and metallurgy structure for establishing electrical contact

Buffer-less de-skewing for symbol combination in a CDMA demodulator

A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

BASELESS SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a baseless semiconductor device and its manufacturing method for effectively decreasing the whole thickness and area. SOLUTION: A connection bump 11 is provided as a conduction member for electrically connecting an electronic element and an electronic circuit to an outside device on the working face 100 of a semiconductor chip 10 having the electronic element and the electronic circuit, coated by a first resin body 12 so that the connection bump 11 exposes an end 110 on the working face 100, and the end 110 of the connection bump 11 and the outer surface 120 of the first resin body 12 are on the same flat face. COPYRIGHT: (C)2002,JPO ...

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse (2) eingebetteten Halbleiterbauteilkomponenten (3) mit folgenden Schritten: Bereitstellen der Halbleiterbauteilkomponenten (3), Aufbringen einer Haftvermittlerschicht (5) nasschemisch unmittelbar auf die Oberfläche (4) der Halbleiterbauteilkomponenten (3), wobei das nasschemische Aufbringen so ausgebildet ist, dass als Halbleiterbauteilkomponenten (3) – ein Verdrahtungssubstrat (7) mit strukturierter Metallbeschichtung (8), – ein Keramiksubstrat mit strukturierten Metalllagen, – eine Leiterplatte (9) mit strukturierter Metallbeschichtung (8), – innere Flachleiter (10), die außerhalb der Kunststoffgehäusemasse (2) in Außenflachleiter (11) als Außenkontakte übergehen, – ein Halbleiterchip und – innere Flipchip-Kontakte und/oder Bondverbindungsdrähte (14) als Verbindungselemente (13) beschichtet werden können, ohne dass das Beschichtungsverfahren jeweils geändert werden muss, wobei eine Haftvermittlerschicht ( ...

Verwendung von präkeramischen Polymeren als Klebstoffe für Elektronik

Verfahren zur Anbringung von Edelmetallkontakten auf Schichten aus filmbildenden oxydierbaren Metallen und mit solchen Anschluessen versehener Duennschichtwiderstand

METHOD AND DEVICE FOR MAKING MICROWIRE

VERFAHREN ZUM BEFESTIGEN VON PLAETTCHEN.

Wiring method for semiconductor package

Pb-wire

A pb alloy wire which is used for electrically connecting (1) a superconductor chip and an external lead, or (2) one superconductor chip and another superconductor chip with each other through a wire bonding process and more particularly through a nail head bonding process or a wedge bonding process into a thin wire shape using a liquid quenching process. The alloy, which has Pb as its main constituent may include at least one of Cu, Ge, Ga, Se, Ag, In, Sn, Sb, Te, Au, Te, Bi, Pd and Pt.

PROCESS FOR MOUNTING COMPONENTS ON A BASE BY MEANS OF THIXOTROPIC MATERIAL

Semiconductor devices and method of manufacturing them

Alloys for use in the manufacture of PN junction rectifiers (see Group XXXVI) consist of tin or lead containing 1/2 % by weight of antimony, and aluminium containing 1-5% by weight of gallium.

POWER TRANSISTOR WITH INTERNALLY COMBINED LOW-PASS AND BAND-PASS FILTER ADAPTOR STAGES

PROCEDURE AND DEVICE FOR THE REGULATION OF THE PRODUCTION OF WIRE BONDS

HARDSOLDERABLE METALLIZATIONS FOR DIAMOND CONSTRUCTION UNITS

SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME AND LIGHT-EMITTING APPARATUS USING SAME

THERMAL INTERFACE MATERIALS AND METHODS FOR THEIR PREPARATION AND USE

Moldless semiconductor device and photovoltaic device module making use of the same

METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS

CONTACT TECHNIQUE FOR ELECTRICAL CIRCUITRY

CONTACT TECHNIQUE FOR ELECTRICAL CIRCUITRY . In electrical circuitry, and particularly superconducting circuitry including Josephson tunnelling devices, it is often necessary to provide solder contacts to electrical lines, where the electrical lines would be destroyed if there were interdiffusion between the lines and the solder. To avoid this problem, a laterally extending metallic layer is used as a diffusion barrier between the solder land and the electrical line which can be a superconducting line. The diffusion barrier is comprised of a refractory metal which has a first portion electrically contacting the solder land and a second, laterally displaced portion electrically contacting the electrical line. An insulating protective layer on the diffusion barrier layer separates the solder land and the electrical line. In a specific embodiment, the superconducting electrical line is comprised of an alloy of lead while the diffusion barrier is comprised of niobium, and the solder alloy is ...

SOLDER INTERCONNECTIONS AND METHODS FOR MAKING SAME

КОНТАКТНЫЙ УЗЕЛ

Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и полупроводниковых приборов, а конкретно к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ), а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит, по крайней мере, два металлизированных контакта, связанных с токоведущими дорожками (2, 6), размещенными на поверхностях коммутационных слоев (3, 7), выполненных на основе из диэлектрического материала, совмещенных друг с другом и соединенных между собой электрически и механически электропроводящим связующим материалом (8). Контактный узел представляет собой стык между контактом, изготовленным в виде металлизированной контактной площадки (1), связанной с токоведущими дорожками (2) на поверхности нижележащего коммутационного слоя (3), и ответным контактом, выполненным ...

Circuitry component fabricating method

Semiconductor device for the transmission of signals

Composite structure semiconductrice presenting of the electro-optical or piezoelectric effects

Device semiconductor

METHODS AND MATERIALS USEFUL FOR CHIP STACKING, CHIP AND WAFER BONDING

Au BONDING WIRE FOR SEMICONDUCTOR ELEMENT

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.

SEMICONDUCTOR POWER DEVICE METAL STRUCTURE AND METHOD OF FORMATION

In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1091) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1091) impart a lower peak stress than a comparably sized continuous power metal structure (90).

Field effect devices and their fabrication

A method of fabricating a field effect transistor comprising the steps of forming an active layer of semiconductor material (GaAs) over a surface of a first substrate of semiconductor material (GaAs), applying a second substrate of insulating material, e.g. glass, over the surface of the active layer, removing the first substrate so that the active layer is now supported on the insulating second substrate, and forming source, drain and gate electrodes over the free surface of the active layer. To facilitate removal of the GaAs first substrate by selective etching, a buffer layer of GaAlAs resistant to the GaAs etchant, may be formed between the active layer and the first substrate, which buffer layer is removed, following removal of first substrate, using a selective etchant to which the GaAs active layer is resistant. The technique is particularly applicable to high frequency FETs requiring a very thin active channel region interfaced to a substrate having good insulating properties.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates

The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1is formed in the same layer as that of a second layer wiring and the pattern P1is formed in the same layer as that of a first layer wiring. Further, the pattern P is formed in the same layer as that of a gate electrode, and the pattern P is formed in the same layer as that of an element isolation region. 128-. (canceled)29. A semiconductor device comprising:a semiconductor substrate;an integrated circuit region in which a plurality of MISFETs are formed;an alignment mark region in which an alignment mark is formed;a first wiring layer formed over the integrated circuit region and the alignment mark region;a second wiring layer formed over the first wiring layer; anda plurality of STI regions formed in the semiconductor substrate and in the alignment mark region, a plurality of first wirings formed in the integrated circuit region, and which are electrically coupled to the plurality of MISFETs; and', 'a plurality of dummy wiring regions formed in the alignment mark region, and which are not electrically coupled to the plurality of MISFETs,, 'wherein the first wiring layer comprises the alignment mark formed in the alignment mark region; and', 'a plurality of second wirings formed in the integrated circuit region,, 'wherein the second wiring layer comprises a first dummy wiring region disposed to overlap with the alignment mark; and', 'a second dummy wiring region disposed to not overlap with the alignment ...

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P 1 a is formed in the same layer as that of a second layer wiring and the pattern P 1 b is formed in the same layer as that of a first layer wiring. Further, the pattern P 2 is formed in the same layer as that of a gate electrode, and the pattern P 3 is formed in the same layer as that of an element isolation region.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive. 1. A semiconductor device comprising:a semiconductor substrate; anda metal film formed on the semiconductor substrate, whereinthe metal film includes a Ni base and a material having condensation energy higher than that of Ni.2. The semiconductor device according to claim 1 , whereinthe material having condensation energy higher than that of Ni is any of Sc, Ti, V, Cr, Fe, Co, Zr, Nb, Mo, Hf, Ta, W, B, and P.3. The semiconductor device according to claim 1 , wherein{'sub': x', 'y, 'the material having condensation energy higher than that of Ni is a stoichiometric material represented by NiP, where each of x and y is an integer.'}4. The semiconductor device according to claim 1 , wherein{'sub': '3', 'the material having condensation energy higher than that of Ni is a NiP particle.'}5. The semiconductor device according to claim 4 , wherein{'sub': '3', 'the NiP particle is uniformly distributed in the Ni base.'}6. The semiconductor device according to claim 1 , further comprising:another metal film made of Al or Cu and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.7. The semiconductor device according to claim 1 , further comprising:another metal film made of Ti and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.8. The semiconductor device according to claim 1 , further ...

Semiconductor device and a method of manufacturing the same

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

METHOD OF FABRICATION, DEVICE STRUCTURE AND SUBMOUNT COMPRISING DIAMOND ON METAL SUBSTRATE FOR THERMAL DISSIPATION

A method of fabrication, a device structure and a submount comprising high thermal conductivity (HTC) diamond on a HTC metal substrate, for thermal dissipation, are disclosed. The surface roughness of the diamond layer is controlled by depositing diamond on a sacrificial substrate, such as a polished silicon wafer, having a specific surface roughness. Following deposition of the diamond layer, an adhesion layer, e.g. comprising a refractory metal, such as tantalum, and at least one layer of HTC metal is provided. The HTC metal substrate is preferably copper or silver, and may be provided by electroforming metal onto a thin sputtered base layer, and optionally bonding another metal layer. The electrically non-conductive diamond layer has a smooth exposed surface, preferably ≦10 nm RMS, suitable for patterning of contact metallization and/or bonding to a semiconductor device. Methods are also disclosed for patterning the diamond on metal substrate to facilitate dicing. 1. A method for fabricating a device structure comprising a diamond on metal substrate for thermal dissipation , by steps comprising:providing a sacrificial silicon substrate having a surface of a selected surface roughness,providing thereon a layer of high thermal conductivity (HTC) diamond; providing an adhesion layer on the layer of diamond;providing thereon at least one layer of high thermal conductivity (HTC) metal to form an HTC metal substrate; andremoving the sacrificial substrate.2. A method according to whereinthe sacrificial substrate has a surface roughness of ≦10 nm RMS, andthe step of providing the layer of HTC diamond comprises depositing a layer of HTC diamond having a grain size ≧100 nm.3. A method according to wherein the step of providing the layer of HTC diamond comprises providing a layer of non-conductive diamond.4. A method according to wherein the HTC metal layer is selected from the group consisting of copper claim 1 , silver claim 1 , an alloy of copper claim 1 , an alloy of ...

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS

In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. 1. A layer stack , comprising:a carrier;an integrated circuit contact provided on the carrier;a back side terminal provided on or in the carrier on a side thereof opposite to the integrated circuit contact;a first metal disposed over the carrier and over the back side terminal, and providing an electrical contact to the back side terminal;a second metal disposed over the first metal; anda solder material disposed over the second metal, or a material disposed over the second metal for providing contact to a solder that is supplied by an external source;wherein the second metal has a melting temperature of at least 1800° C. and is an adhesive layer to the solder material and is substantially indissolvable in the solder material during a soldering process.2. The layer stack of claim 1 ,wherein the first metal comprises a metal selected from a group of metals consisting of aluminum; titanium; and an alloy of the mentioned metals.3. The layer stack of claim 1 ,wherein the second metal comprises a metal selected from a group of metals consisting of: tungsten (W), tantalum (Ta), molybdenum (Mo), chromium (Cr), and vanadium (V).4. The layer stack of claim 1 ,wherein the second metal comprises a plurality of metal components;wherein a first metal component of the plurality of metal components comprises a metal selected from a group of metals consisting of: tungsten; tantalum; molybdenum; chromium; niobium; and hafnium; andwherein a second metal component ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING INTERLAYER INSULATING FILMS HAVING DIFFERENT YOUNG'S MODULUS

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to apart of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved. 1. A semiconductor device comprising:a semiconductor substrate;a MISFET formed on the semiconductor substrate;a contact interlayer insulating film covering the MISFET formed on the semiconductor substrate;a first plug formed in the contact interlayer insulating film and electrically connected to the MISFET;a first interlayer insulating film formed on the contact interlayer insulating film;a first layer wiring formed in the first interlayer insulating film and electrically connected to the first plug;a second interlayer insulating film formed on the first interlayer insulating film;a second plug formed in the second interlayer insulating film and electrically connected to the first layer wiring; anda second layer wiring formed in the second interlayer insulating film and electrically connected to the second plug,wherein the contact interlayer insulating film is formed of a high-dielectric-constant film having the highest dielectric constant among the contact interlayer insulating film, the first interlayer insulating film and the second ...

SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES

A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer. 1. A bonded structure comprising a vertical stack of a first substrate and a second substrate , wherein said first substrate includes a first silicon oxide layer embedding first metal pads predominantly including copper and said second substrate includes a second silicon oxide layer embedding second metal pads predominantly including copper ,wherein horizontal surfaces of said first metal pads are bonded to surfaces of said second metal pads,wherein one of said first metal pads and one of said second metal pads are bonded to each other at an interface as a vertically contacting pair of metal pads,wherein a metal oxide portion is embedded within a peripheral portion of a metal pad in said vertically contacting pair, and said metal oxide portion comprises an oxide of a dopant metal that is not present at a portion of said interface at which copper-containing material portions of metal pads are bonded to each other.2. The bonded structure of claim 1 , wherein each metal pad in said vertically contacting pair is physically exposed to a cavity by which a horizontal surface of said first silicon oxide layer is spaced from a horizontal surface of said second ...

FLEXIBLE HERMETIC MEMBRANES WITH ELECTRICALLY CONDUCTING VIAS

Disclosed herein are electrically conductive and hermetic vias disposed within an insulator substrate of a feedthrough assembly and methods for making and using the same. Such aspects of the present invention consequently provide for the miniaturization of feedthrough assemblies inasmuch as the feedthrough components of the present invention are capable of supporting very small and hermetic conductively filled via holes in the absence of additional components, such as, for example, terminal pins, leadwires, and the like. 1. A feedthrough assembly , comprising:(a) a ferrule comprising an electrically conductive material, the ferrule comprising a ferrule opening, wherein the ferrule is configured to be attachable to an opening in a housing of a medical device;(b) an insulator at least partially residing in the ferrule opening, wherein a gold braze hermetically seals the insulator to the ferrule, and wherein the insulator has a thickness extending between an insulator first side and an insulator second side, and further wherein at least one via hole extends through the thickness of the insulator, the at least one via hole being provided with a via hole metallization to form at least one metallized via hole; and(c) a conductive fill residing at least partially within the at least one metallized via hole, wherein the conductive fill hermetically seals and forms a conductive pathway between the insulator first side and the insulator second side to form an electrically conductive hermetic via.2. The feedthrough assembly of claim 1 , wherein the conductive fill is a substantially pure gold body.3. The feedthrough assembly of claim 1 , wherein an adhesion layer contacts an internal surface of the at least one via hole claim 1 , and a wetting layer resides at least partially on the adhesion layer to form the via hole metallization of the at least one metallized via hole.4. The feedthrough assembly of claim 3 , wherein the wetting layer contacts the conductive fill to form the ...

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device in the form of a rectangle having first and second short sides and first and second long sides , comprising:a plurality of wiring layers formed over a semiconductor substrate;first and second wirings formed at an uppermost layer of the wiring layers and extending along the first long side;an insulating film formed over the first and second wirings;first and second openings formed in the insulating film;a first bump electrode formed over the first and second wirings, arranged nearer to the first long side than to the second long side and connected to the first wiring through the first opening; anda second bump electrode formed over the first and second wirings, arranged nearer the first long side than to the second long side and connected to the second wiring through the second opening, wherein:the first wiring is arranged between the second wiring and the first long side, anda second distance between the second opening and the first long side is larger than a first distance between the first opening and the first long side.2. The semiconductor device according to claim 1 ,wherein the first wiring is different from the second wiring.3. The semiconductor device according to claim 1 , wherein:the first bump electrode is not connected to the second wiring, andthe second bump electrode is not connected to the first wiring.4. The ...

Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures

Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments methods may include contacting a substrate with a first reactant comprising a transition metal precursor, contacting the substrate with a second reactant comprising a niobium precursor and contacting the substrate with a third reactant comprising a nitrogen precursor. In some embodiments related semiconductor device structures may include a semiconductor body and an electrode comprising a transition metal niobium nitride disposed over the semiconductor body.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are spaced ...

EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE ENCAPSULATED BY THE SAME

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature. 1. An epoxy resin composition for encapsulating a semiconductor device , the composition comprising:a base resin;a filler;a colorant; anda thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.2. The epoxy resin composition as claimed in claim 1 , wherein the thermochromic pigment is a metal oxalate pigment.4. The epoxy resin composition as claimed in claim 3 , wherein the metal element is an alkali metal claim 3 , an alkali earth metal claim 3 , a group XIII element claim 3 , a group XIV element claim 3 , a group XI element claim 3 , a group XII element claim 3 , a group III element claim 3 , a group IV element claim 3 , a group V element claim 3 , a group VI element claim 3 , a group VII element claim 3 , a group VIII element claim 3 , a group IX element claim 3 , or a group X element.5. The epoxy resin composition as claimed in claim 1 , wherein the predetermined temperature at which the thermochromic pigment undergoes the irreversible color change is about 260° C. or higher.6. The epoxy resin composition as claimed in claim 1 , wherein the thermochromic pigment is present in the epoxy resin composition in an amount of about 0.01 wt % to about 5 wt % claim 1 , based on a total weight of the epoxy resin composition.7. The epoxy resin composition as claimed in claim 1 , wherein the colorant includes sodium claim 1 , calcium claim 1 , aluminum claim 1 , tin claim 1 , gold claim 1 , zinc claim 1 , yttrium claim 1 , titanium claim 1 , tantalum claim 1 , chromium claim 1 , manganese claim 1 , iron claim 1 , ...

Pharmacologically active compounds with two covalently linked active principles (sodium channnel blocker/p2y2 receptor agonist) for the treatment of mucosal surfaces

Compounds of the general formula P1-L-P2; wherein 'P1' is a pyrazinoylguanidine sodium channel blocker, 'L' is a linking group, and 'P2' is either (i) a pyrazinoylguanidine sodium channel blocker or (ii) a P2Y2 receptor agonist, are disclosed. Pharmaceutical formulations containing the same and methods of use thereof to hydrate mucosal surfaces such as airway mucosal surfaces are also disclosed.

Chip interconnect and packaging deposition methods and structures

The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

Semiconductor device and manufacturing method thereof

An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24 a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.

Semiconductor device and manufacturing method thereof

An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24 a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.

Kit for the assembly of a metal electronic package

A kit for the assembly of an adhesively sealed package designed to encase an electronic device is provided. The kit comprises a metallic base and cover components which are adapted to receive a polymeric adhesive. At least those portions of the base and cover component which will contact the polymeric adhesive are provided with a coating of a second metal or oxide. In one embodiment, first, second and third dry film adhesives are tacked to the base and cover components.

Chip interconnect and packaging deposition methods and structures

The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

Superconducting bonds for thin film devices

A method of bonding a superconductive ribbon lead to a superconductive bonding pad connected to superconducting circuitry. The thin ribbon is first coated with a fresh layer of the same material from which it is made and then a very thin layer of a noble metal is applied over that fresh layer. The bonding pad is also prepared with a very thin layer of the noble metal. Those coated surfaces are placed in facing contact and ultrasonically bonded.

Copper bonding wire for semiconductor packaging

Provided is a copper bonding wire formed of a high purity copper of 99.999% or more including at least one of P and Nb within a range between 20 wt ppm and 100 wt ppm and at least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra within a range between 1 wt ppm and 100 wt ppm. Here, a total content of the added elements is restricted within a range between 20 wt ppm and 200 wt ppm, and a residual amount of the copper bonding wire is a high purity copper of 99.98% or more. As a result, metal squeeze out and chip cratering can be reduced in a general semiconductor chip and a low dielectric semiconductor chip. Also, a short tail of the copper bonding wire occurring during bonding of the copper bonding wire to a lead finger can be reduced.

Power semiconductor module

A power semiconductor module has a controllable semiconductor chip ( 50 ), a first printed circuit board ( 1 ), a second printed circuit board ( 2 ), and also has one or a plurality of passive components ( 13, 18 ). The first printed circuit board ( 1 ) may have a conductor track structure ( 12, 13, 14 ), and the second printed circuit board ( 2 ) may have a conductor track structure ( 21, 22, 23, 24 ). Furthermore, an opening ( 19 ) in which the semiconductor chip ( 50 ) is arranged can be provided in the first printed circuit board ( 1 ). Furthermore, at least one passive component ( 13, 18 ) can be arranged on the first printed circuit board ( 1 ) or on the second printed circuit board ( 2).

Flexible interconnect film including resistor and capacitor layers

A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures

Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments methods may include contacting a substrate with a first reactant comprising a transition metal precursor, contacting the substrate with a second reactant comprising a niobium precursor and contacting the substrate with a third reactant comprising a nitrogen precursor. In some embodiments related semiconductor device structures may include a semiconductor body and an electrode comprising a transition metal niobium nitride disposed over the semiconductor body.

连接膜、以及接合体及其制造方法

本发明的目的在于提供一种在导电性粒子的补充效率及导通可靠性两方面均优异的连接膜，以及接合体及其制造方法。所述连接膜是将第1电路元件和第2电路元件以电形式连接在一起的连接膜，所述第2电路元件在面向第1电路元件的一面形成含有氮原子的膜；所述连接膜具备位于所述第1电路元件一侧的第1层和位于第2电路元件一侧的第2层，所述第1层含有阳离子系固化剂及环氧树脂；所述第2层含有自由基系固化剂、丙烯酸树脂及环氧化合物；所述第1和第2层中的任意一层为含有导电性粒子的含导电性粒子有机树脂层，所述第1和第2层中的另一层为没有导电性的绝缘性有机树脂层；所述含有导电性粒子有机树脂层的最低熔融粘度是所述绝缘性有机树脂层的最低熔融粘度的10倍以上。

Epoxy resin composition for encapsulating semiconductor device and semiconductor device encapsulated by the same

본 발명은 베이스 수지, 충전제, 착색제 및 열감응성 변색 안료를 포함하고, 상기 열감응성 변색 안료는 온도 증가에 의하여 비가역적으로 색상이 변화하는 반도체 소자 밀봉용 에폭시 수지 조성물 및 상기 조성물로 밀봉된 반도체 장치에 관한 것이다. The present invention relates to an epoxy resin composition for sealing a semiconductor device, which comprises a base resin, a filler, a colorant and a thermosensitive discoloring pigment, wherein the thermosensitive discoloration pigment irreversibly changes color by temperature increase, and a semiconductor device .

Contact assembly

FIELD: non-split joints for microelectronic and semiconductor devices. SUBSTANCE: contact assembly has at least two metal-coated contacts coupled with current-carrying tracks placed on switching-layer surfaces on insulating substrate, joined together, and interconnected electrically and mechanically by means of electricity conducting binder. Contact assembly is, essentially, joint between metal-coated contact pad coupled with current-carrying tracks on surface of lower switching layer and mating contact made in the form of metal-coated hole in insulating layer. EFFECT: enlarged functional capabilities of contact assembly. 23 cl, 6 dwg зб с ПЧ ГЭ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (19) (51) МПК ВИ” 2134 498 13) СЛ Н 05 К 1/41, 3/36, 3/42, 13/04, Н 01 В 4/00, 9/09 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 98121773109, 08.12.1998 (24) Дата начала действия патента: 08.12.1998 (46) Дата публикации: 10.08.1999 (56) Ссылки: Моряков О.С. Технология полупроводниковых приборов и изделий микроэлектроники. - М.: Высшая школа, 1990, с.38-40. ОЕ 4040226 05, 17.06.92. ЕР 0493103 А2, 01.07.92. ЗЦ 1739529 АЛ, 07.06.92. $ 1757138 АЛ, 23.08.92. (98) Адрес для переписки: 117333, Москва, Ленинский пр-т, 60/2-160, Таран А.И. (71) Заявитель: Таран Александр Иванович (72) Изобретатель: Таран А.И. (73) Патентообладатель: Таран Александр Иванович (54) КОНТАКТНЫЙ УЗЕЛ (57) Реферат: Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и — полупроводниковых приборов, а конкретно - к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ)а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит по крайней мере два металлизированных контакта, связанных с токоведущими дорожками, размещенными на поверхностях коммутационных слоев, ...

线路元件

本发明提供一种线路元件，包括：半导体基底；第一线圈，位于该半导体基底上；第一环状金属结构，位于该半导体基底上，其中该第一环状金属结构环绕该第一线圈，且该第一环状金属结构与该第一线圈的最外圈之间的第一间隔的最短距离除以该第一线圈的相邻圈之间的第二间隔的最短距离得到的值介于0.1至10之间。本发明的顶层线圈可以承受高电压高电流，且控制顶层线圈的电流变化可以感应底层线圈。

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다. An embodiment relates to a light emitting device package. A light emitting device package according to an exemplary embodiment of the present invention includes a light emitting element located on a first lead frame and having an electrode pad on an upper surface thereof, a second lead frame spaced apart from the first lead frame, And a first bonding ball located on a first lead frame and spaced apart from a first contact where the first wire and the second lead frame are in contact with each other on the first lead frame and the first bonding ball, The first lead frame and the second lead frame, and electrically connect the first wire and the second lead frame. In the light emitting device package according to the embodiment, when the wire bonding is used, the wire bonding is prevented by fixing the wire by bonding the wire, and the wire can be electrically connected to the lead frame through the bonding ball, And has an effect of improving the reliability.

접촉노드

본 발명은 마이크로전자공학 부품 및 반도체 디바이스에 기초한 장비의 제조시 영구적인 연결부를 제조하는 것에 관한 것으로, 특히 마이크로칩 모듈(MCM)의 제조시 LSIC 칩의 장착공정이 수행될 뿐만 아니라 MCM을 위한 다층 연결플레이트의 조립공정을 위한 접촉 노드에 관한 것이다. 상기 접촉노드는 유전체 재질의 베이스위에 형성되고 상호 정렬되며 도전성 바인딩재에 의해 전기적 및 기계적으로 상호연결된 연결층 표면상에 배치된 도전성 경로에 연결된 적어도 두개의 메탈라이즈 접촉부를 포함한다. 상기 접촉노드는 연결층 표면상의 도전성 경로에 연결된 메탈라이즈 접촉패드 형태로 형성된 접촉부와, 상기 패드와 접합되고 상부 연결층의 메탈라이즈 홀 형태로 형성된 각각의 접촉부 사이의 접합부 형태로 형성되며, 상기 메탈라이즈 홀의 하측 엣지부는 하부 연결층 표면상의 메탈라이즈 접촉패드를 향해 있고, 상기 메탈라이즈 홀의 상측 엣지부는 상부 연결층의 상측면위 도전층 경로에 연결된다.

지르코늄산화막과 니오븀산화막을 포함하는 유전막을구비한 반도체소자 및 그의 제조 방법

본 발명은 10Å 이하의 EOT를 갖고 누설전류 특성이 우수한 유전막의 제조 방법, 유전막을 구비한 반도체소자 및 그의 제조 방법을 제공하기 위한 것으로, 본 발명의 유전막의 제조 방법은 원자층증착법(ALD)을 이용하여 ZrO 2 과 Nb 2 O 5 가 나노스케일 단위로 혼합된 [ZrO 2 ] x [Nb 2 O 5 ] (1-x) 구조를 형성하여 유전막을 형성하고, 상술한 본 발명은 Al 2 O 3 , ZrO 2 , Ta 2 O 5 , TiO 2 보다 전기적 특성이 우수한 비정질 [ZrO 2 ] x [Nb 2 O 5 ] (1-x) 유전막을 단원자증착법에 의해 형성함으로써 EOT가 10Å 미만의 값을 요구하는 65nm 급 이하의 DRAM 캐패시터의 형성이 가능하다. 유전막, 나노스케일, 누설전류, EOT, 니오븀, 지르코늄

Method of depositing niobium nitride thin films

본 발명의 일 실시예에 의하면, 니오븀 질화물 박막의 형성 방법은, 기판에 니오븀 할로젠 이온 화합물을 공급하여 상기 기판의 표면에 선택적으로 흡착시키는 흡착 단계; 그리고 상기 기판에 질소 소스를 공급하여 상기 니오븀 할로젠 이온 화합물과 반응시키고 니오븀 질화물을 형성하는 질화 단계를 포함한다. According to an embodiment of the present invention, a method for forming a niobium nitride thin film includes an adsorption step of supplying a niobium halogen ion compound to a substrate and selectively adsorbing it on the surface of the substrate; and a nitridation step of supplying a nitrogen source to the substrate to react with the niobium halogen ion compound to form niobium nitride.

Bonding use copper wire of semiconductor element

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Insulated gate bipolar transistor, semiconductor device, manufacturing method of insulated gate bipolar transistor and manufacturing method of semiconductor device

본 발명은 절연 게이트형 바이폴라 트랜지스터, 그것을 이용한 반도체 장치, 및 이들의 제조 방법에 관한 것으로, 특히 환류 전류를 바이패스하기 위한 프리휠 다이오드의 접속을 필요로 하지 않는 것을 목적으로 한다. 그리고, 상기 목적을 달성하기 위해서, P + 콜렉터층(11)과 접합을 형성하는 N + 버퍼층(12)의 불순물 농도를 높게 함으로써, N 베이스층(12, 13)과 P + 콜렉터층(11)에 의해 형성되는 기생 다이오드(D)의 애밸런치 항복 전압이 낮게 억제된다. 그에 따라, IGBT(101)의 역 내압이 콜렉터·에미터간 포화 전압(V CE(sat) )의 5배 이하로 저감된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor, a semiconductor device using the same, and a method for manufacturing the same, and in particular, does not require the connection of a freewheel diode for bypassing the reflux current. And,, P + collector layer 11 and by the junction increase the impurity concentration of the N + buffer layer 12 is formed, N base layer 12 and 13 and the P + collector layer 11. In order to achieve the above object The avalanche breakdown voltage of the parasitic diode D formed by this is suppressed low. Thereby, the reverse breakdown voltage of the IGBT 101 is reduced to five times or less of the collector-emitter saturation voltage V CE (sat) .

Bond pad of semiconductor device and method for fabrication thereof

구리패턴을 사용한 다마신 기법으로 반도체 소자의 본드패드를 형성할 때, 디싱(dishing)을 억제하고, 본드패드의 도전능력을 개선할 수 있는 반도체 소자의 본드패드 및 그 형성방법에 관해 개시한다. 본 발명은 제1 및 제2 구리패턴을 불규칙한 격자형태로 형성하고, 상기 제1 및 제2 구리패턴을 상하방향으로 서로 연결할 수 있도록 만들어진 제1 및 제2 절연막 패턴과, 상기 제1 및 제2 구리패턴을 평면적으로 서로 연결할 수 있는 배선연결 구조 및 상기 제1 및 제2 구리패턴 상부에 형성되는 도전능력 개선층을 제공한다. 따라서, 격자모양의 제1 및 제2 구리패턴때문에 제1 및 제2 구리패턴을 다마신 기법으로 평탄화할 때 발생하는 디싱현상을 억제하고, 제1 및 제2 구리패턴을 상하방향 및 평면방향으로 서로 연결시키고, 제1 및 제2 구리패턴 위에 추가로 도전능력 개선층을 형성함으로써 본드패드의 도전특성을 개선할 수 있다. A method of forming a bond pad of a semiconductor device and a method of forming the same, which can suppress dishing and improve the conductivity of the bond pad when forming a bond pad of a semiconductor device using a damascene technique using a copper pattern. According to an embodiment of the present invention, first and second copper patterns may be formed in an irregular lattice shape, and the first and second insulating patterns may be connected to each other in the vertical direction. A wiring connection structure capable of connecting copper patterns to each other in a planar manner and a conductive improvement layer formed on the first and second copper patterns are provided. Therefore, the dishing phenomenon caused when the first and second copper patterns are planarized by the damascene technique due to the lattice-shaped first and second copper patterns is suppressed, and the first and second copper patterns are moved in the vertical direction and the planar direction. The conductive properties of the bond pads may be improved by connecting to each other and further forming a conductivity improving layer on the first and second copper patterns.

Contact elements and contact devices

전류가 접촉 소자와 접촉 부재 사이에 흐르게 하기 위해 접촉 부재 (2) 에 대하여 전기 접촉을 이루기 위한 접촉 소자 (1) 는 상기 접촉 부재에 대하여 적용되는 접촉층 (4) 으로 코팅된 하나 이상의 접촉 표면을 갖는 본체 (3) 를 포함한다. 접촉층은 비결정성 탄소 매트릭스 및 그 사이에 끼워진 하나 이상의 금속 탄화물의 나노 크기, 즉 1 ~ 100 ㎚ 범위의 치수를 갖는 결정을 갖는 나노복합 막을 포함한다 The contact element 1 for making electrical contact with respect to the contact element 2 in order to allow a current to flow between the contact element and the contact element comprises at least one contact surface coated with a contact layer 4 applied to the contact element. It has a main body 3 which has. The contact layer comprises a nanocomposite film having a amorphous carbon matrix and crystals having a nano size of one or more metal carbides sandwiched therebetween, i.e., a dimension in the range of 1 to 100 nm.

Methods of forming thin film and integrated circuit device using niobium compound

다음 식 Nb(R 5 Cp) 2 (L) (식중, 각각의 R 은 독립적으로 H, C1 내지 C6의 알킬기, 또는 R 1 3 Si 이고, 여기서, 각각의 R 1 은 독립적으로 H 또는 C1 내지 C6의 알킬기이고, Cp는 시클로펜타디에닐기이고, L 은 포름아미디네이트 (N R , R' -fmd), 아미디네이트 (N R , R' R''-amd), 및 구아니디네이트 (N R , R' , N R'' , R''' -gnd) 중에서 선택됨)의 니오븀 화합물을 포함하는 전구체 조성물과 반응물을 공급하여 니오븀 함유막을 형성한다. next expression Nb(R 5 Cp) 2 (L) (wherein each R is independently H, a C1 to C6 alkyl group, or R 1 3 Si , wherein each R 1 is independently H or a C1 to C6 alkyl group, and Cp is a cyclopentadienyl group, L is formamidinate (N R , R'-fmd), amidinate (N R , R ' R ' '-amd), and guanidinate (N R , R' , N R'' , R ''' -gnd)) of a precursor composition including a niobium compound and a reactant are supplied to form a niobium-containing layer.

Semiconductor device and manufacturing method thereof

Methods and materials useful for chip stacking, chip and wafer bonding

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Methods and materials useful for chip stacking, chip and wafer bonding

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Methods and materials useful for chip stacking, chip and wafer bonding

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Methods and materials useful for chip stacking, chip and wafer bonding

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Copper bonding wire for semiconductor packaging

P 및 Nb 중의 적어도 어느 하나가 20-100 중량ppm으로 첨가된 99.999% 이상의 고순도 구리(Cu)에 Zr, Sn, Be，Nd, Sc, Ga, Fr 및 Ra 중의 적어도 어느 하나가 1-100 중량ppm의 범위로 첨가된 것으로, 첨가원소의 전체 함유량이 20-200 중량ppm으로 제한되고 잔여량은 99.98% 이상의 고순도 구리로 구성되는 구리 본딩 와이어를 개시한다. 이러한 구리 본딩 와이어는 일반적인 반도체 칩뿐만 아니라 저유전체 반도체 칩에서도 패드 밀림 및 칩 패임 현상을 감소시키고 리드 핑거와의 접합시 발생하는 구리 본딩 와이어의 길이 부족 현상을 감소시킨다.  At least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra is 1-100 ppm by weight to 99.999% or more of high purity copper (Cu) in which at least one of P and Nb is added by 20-100 ppm by weight In addition, the present invention discloses a copper bonding wire in which the total content of added elements is limited to 20-200 ppm by weight and the remaining amount is composed of high purity copper of 99.98% or more. Such copper bonding wires reduce pad push and chip dents in low dielectric semiconductor chips as well as general semiconductor chips, and reduce the shortage of copper bonding wires generated when bonding the lead fingers.

Component And Method For The Production Thereof

회로 기판(1)에 주로 구리로 구성된 층(2)이 제공된다. 와이어(3)가 주로 구리로 된 층(2)에 와이어 본딩과 금속간 화합물 형성에 의하여 연결되므로, 주로 구리층(2)에 적층되는 단단한 층(5)은 본딩 영역에서 깨진다. 단단한 층(5)은 80℃ 이상의 온도에서 안정하다. 이 온도에서 상기 층은 산소 확산 장벽으로 작용하며, 정상적인 환경하에서 형성되는 알루미늄 산화물 층과 유사한 방식으로 알루미늄에 작용한다. 회로 기판, 와이어, 본딩 영역, 산소 확산 장벽, 산화물 The circuit board 1 is provided with a layer 2 consisting mainly of copper. Since the wire 3 is connected to the layer 2 mainly made of copper by wire bonding and intermetallic compound formation, the rigid layer 5 mainly laminated to the copper layer 2 is broken in the bonding region. The rigid layer 5 is stable at temperatures of at least 80 ° C. At this temperature the layer acts as an oxygen diffusion barrier and acts on aluminum in a manner similar to the aluminum oxide layer formed under normal circumstances. Circuit board, wire, bonding area, oxygen diffusion barrier, oxide

Manufacturing method of semiconductor device

Printed wiring board and method for manufacturing printed wiring board

本発明では、接着性を有する絶縁基材及びこの絶縁基材の一方の面に形成された導電層からなる少なくとも一の配線付き基材と、この導電層に接続され絶縁基材を貫通している導電性ペーストからなる貫通電極と、再配線部を有するＩＣチップとを備え、ＩＣチップが、再配線部を貫通電極に接続させて配線付き基材の層間接着材中に埋め込まれており、ＩＣチップの再配線部の反対側の面に接着層を介して支持基板が配置されており、再配線部と配線付き基材とが再配線層を構成している。このため、本発明では、容易な工程により作製でき、また、コストの上昇や歩留まりの低下を招来することがなく、高精細な部品を実装した多層のプリント配線基板を提供できる。 In the present invention, an insulating base material having adhesiveness and at least one base material with wiring composed of a conductive layer formed on one surface of the insulating base material, and being connected to the conductive layer and penetrating the insulating base material A through-electrode made of a conductive paste and an IC chip having a rewiring portion, and the IC chip is embedded in an interlayer adhesive of a substrate with wiring by connecting the rewiring portion to the through-electrode, A support substrate is disposed on the surface opposite to the rewiring portion of the IC chip via an adhesive layer, and the rewiring portion and the substrate with wiring form a rewiring layer. Therefore, according to the present invention, it is possible to provide a multilayer printed wiring board on which high-definition components are mounted, which can be manufactured by an easy process and does not cause an increase in cost and a decrease in yield.

Semiconductor device and method of manufacturing the same

【課題】 光の発光、または受光を行う従来の半導体装置では、フィラーの無い透明な樹脂で封止されるため、熱膨張係数αの不一致から信頼性に欠けていた。 【解決手段】 半導体チップ６の表面、特に受光または発光を行う領域に透過手段９を設ける事により、他はフィラーの入った絶縁樹脂１１で封止できる。よってＳｉの熱膨張係数α（Ｓｉ）に近づけることができる。更には、支持基板２がガラス繊維やガラスフィラーが入ったものであれば、支持基板２とも熱膨張係数を近づけることができ、反りの発生を抑止することができる。また、表面に保護膜１０を設け、金型の内壁に当接可能な透過手段９を用意すれば、この保護膜１０が透過手段の傷を防止することができ、更に光の通過領域を保護膜１０で囲んで設けられているので、ここの領域に前記封止樹脂の浸入を防止することができる。 【選択図】図１

Method of forming a semiconductor metallization system and its structure

Module with embedded semiconductor and method of fabricating the module

提供一种内置半导体IC模块，使用电极节距非常窄的半导体IC来构成内置半导体IC模块。该内置半导体IC模块包括：树脂层(140、150)；贯通树脂层(140、150)设置的柱电极(120)；以及为埋入在树脂层(140)和树脂层(150)之间而被固定的、通过研磨而薄膜化的半导体IC(130)。在本发明中，由于在将设置于半导体IC(130)中的柱状凸起(132)相对于柱电极(120)进行定位，所以柱状凸起(132)的平面位置实质上被固定，因此，可使用100μm以下、特别是60μm左右的电极节距非常窄的半导体IC。

Copper alloy bonding wire for semiconductor devices

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device copper bonding wire which has a reduced material cost, is excellent in a superior ball bonding shape, wire bonding property etc. , and has a good loop formability, and a superior mass productivity. <P>SOLUTION: The semiconductor-device copper-alloy bonding wire contains at least one kind of Mg and P in total of 10 to 700 mass ppm, and oxygen within a range from 6 to 30 mass ppm. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Semiconductor light-emitting device, method for manufacturing same and light-emitting apparatus using same

A nitride semiconductor light-emitting device comprising a multilayer portion deposited on a substrate and having an n-type semiconductor layer, an active layer and a p-type semiconductor layer, wherein the multilayer portion emits light. The lateral surface of the multilayer portion is a slope including the surface of the n-type semiconductor layer, and an n electrode is formed on the surface of the n-type semiconductor layer. With the above-described device structure, the luminous efficiency and light-output efficiency are increased.

Method and apparatus for bonding components leads to pads located on a non-rigid substrate

Component leads are bonded to pads disposed on a non-rigid substrate by the application of a combination of laser energy and ultrasonic energy. The pads preferably are bare copper pads, without a noble metal coating or a chemical pretreatment, and the non-rigid substrate is preferably an epoxy printed circuit board.

Semiconductor radiation emitter package

A semiconductor optical radiation package includes a leadframe, at least one semiconductor optical radiation emitter and an encapsulant. The leadframe has a heat extraction member, which supports the semiconductor optical emitter and provides one or more thermal paths for removing heat generated within the emitter to the ambient environment, as well as at least two electrical leads for providing electrical coupling to the semiconductor optical radiation emitter. The encapsulant covers and protects the emitter and optional wire bonds from damage and allows radiation to be emitted from the emitter into the ambient environment. The semiconductor optical radiation package provides high emitted flux and is preferably compatible with automated processing techniques.

Circuitry component

本发明提供一种线路元件，包括：半导体基底；第一线圈，位于该半导体基底上；第一环状金属结构，位于该半导体基底上，其中该第一环状金属结构环绕该第一线圈，且该第一环状金属结构与该第一线圈的最外圈之间的第一间隔的最短距离除以该第一线圈的相邻圈之间的第二间隔的最短距离得到的值介于0.1至10之间。本发明的顶层线圈可以承受高电压高电流，且控制顶层线圈的电流变化可以感应底层线圈。

Driving chip and display apparatus having the same

결합 신뢰성을 향상시킬 수 있는 구동 칩 및 이를 갖는 표시장치가 개시되어 있다. 구동 칩은 내부에 형성된 구동 회로를 포함하는 베이스 몸체, 베이스 몸체의 일면에 4열 이상으로 형성되며, 각 열은 베이스 몸체의 길이 방향을 따라 배열되는 도전 범프, 베이스 몸체의 일면에 형성되어 구동 회로와 도전 범프를 전기적으로 연결하는 도전 배선을 포함한다. 도전 범프는 도전 배선을 통하여 구동 회로와 대응되는 셀 영역에 형성된다. 따라서, 도전 범프 간의 이격 거리 및 각 도전 범프의 크기가 증가되어 표시패널과의 결합 신뢰성을 향상시킬 수 있다. Disclosed are a driving chip capable of improving coupling reliability and a display device having the same. The driving chip is formed in the base body including a drive circuit formed therein, four or more rows on one surface of the base body, each row is formed on one surface of the base body, the conductive bumps arranged along the longitudinal direction of the base body, the driving circuit And conductive wires for electrically connecting the conductive bumps with each other. The conductive bumps are formed in the cell region corresponding to the driving circuit through the conductive wirings. Therefore, the separation distance between the conductive bumps and the size of each conductive bump may be increased, thereby improving coupling reliability with the display panel.

Method for producing semiconductor chips and method for producing a via in a semiconductor substrate

Verfahren zum Herstellen von Halbleiterchips, wobei das Verfahren umfasst: Bereitstellen eines Halbleiter-Wafers; Ausbilden einer Metallschicht auf dem Halbleiter-Wafer durch Plasmaabscheidung von bereits hergestellten Metallpartikeln auf dem Halbleiter-Wafer, wobei die Metallpartikel aus Kupfer und/oder Aluminium hergestellte Kerne und die Kerne umgebende Schalen umfassen, wobei die Schalen aus Silber, Gold, Palladium, Titan, Tantal und/oder Niob hergestellt sind; und Zersägen des Halbleiter-Wafers, wodurch die Halbleiterchips getrennt werden. A method of manufacturing semiconductor chips, the method comprising: Providing a semiconductor wafer; Forming a metal layer on the semiconductor wafer by plasma deposition of already produced metal particles on the semiconductor wafer, the metal particles comprising cores made of copper and / or aluminum and shells surrounding the cores, the shells of silver, gold, palladium, titanium, Tantalum and / or niobium are made; and Sawing the semiconductor wafer, thereby separating the semiconductor chips.

Functional element built-in circuit board, manufacturing method thereof, and electronic device

回路基板は、機能素子と、機能素子を内蔵する配線基板と、機能素子を挟んで回路基板の表裏の各表面部分に形成され、各１層以上の導体層を含む第１及び第２配線層とを備る。第１配線層の最外層の各パターン配線の表面が露出し、且つ、最外層の各パターン配線間を絶縁する第１絶縁層の表面が、前記最外層の各パターン配線の表面よりも突出している。第２配線層の各パターン配線と機能素子の電極端子とが接続され、電極端子間を絶縁する第２絶縁層の表面と、その表面に隣接する電極端子の表面とがほぼ同一平面内にある。 The circuit board is formed on each surface portion of the front and back surfaces of the circuit board with the functional element sandwiched between the functional element, the wiring board incorporating the functional element, and first and second wiring layers each including one or more conductor layers And prepare. The surface of each pattern wiring in the outermost layer of the first wiring layer is exposed, and the surface of the first insulating layer that insulates between the pattern wirings in the outermost layer protrudes from the surface of each pattern wiring in the outermost layer. Yes. Each pattern wiring of the second wiring layer and the electrode terminal of the functional element are connected, and the surface of the second insulating layer that insulates between the electrode terminals and the surface of the electrode terminal adjacent to the surface are in the same plane. .

Bga semiconductor package and method of fabricating the same

A ball grid array semiconductor package and its manufacturing method are provided to significantly reduce the size of a circuit board by forming a connector with conductive particles, a reflowed metal layer having a low-melting point or a plating layer. A semiconductor chip(SC) has a bond pad(210). A circuit board(CB) has a base board(100) with a through-hole exposing the board pad, and a conductive layer pattern(105) positioned on a sidewall of the through-hole. A connector(221) is positioned in the through-hole to electrically connect the conductive layer pattern with the board pad. A sealing layer(230) is positioned on the connector to cover the connector. The connector is conductive particles, and the conductive particles are positioned only on a portion of a lower portion of the through-hole.

Semiconductor device and preparation there of and bonding wire used there of

내용 없음. No content.

Pressure contact type semiconductor device, ring-shaped gate terminal thereof, and power application device

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다.

Au bonding wire

Connection terminal, semiconductor package using connection terminal, and method of manufacturing semiconductor package

The connection reliability of connecting terminals with displacement gold plating films is improved by connecting terminals comprising a conductive layer, an electroless nickel plating film, a first palladium plating film which is a displacement or electroless palladium plating film with a purity of 99% by mass or greater, a second palladium plating film which is an electroless palladium plating film with a purity of at least 90% by mass and less than 99% by mass, and a displacement gold plating film, wherein the electroless nickel plating film, the first palladium plating film, the second palladium plating film and the displacement gold plating film are laminated in that order on one side of the conductive layer, and the displacement gold plating film is situated on the uppermost surface layer on the opposite side from the conductive layer.

Flux cored wire for gas shielded arc welding

[과제] 필릿 용접에 있어서, 용접 작업성이 우수하고, 내기공성, 비드 형상 및 슬래그 박리성의 모두가 양호한 가스 실드 아크 용접용 플럭스 내장 와이어를 제공한다. [해결수단] 가스 실드 아크 용접용 플럭스 내장 와이어를, 와이어 전체 질량당, Ti: 1.0∼4.0질량%, Si: 0.5∼2.5질량%, Zr: 0.1∼0.6질량%, Mn: 2.0∼3.0질량%, C: 0.02∼0.10질량%, S: 0.005∼0030질량%, Bi: 0.005∼0.040질량%, Na: 0.01∼0.20질량%, K: 0.01∼0.20질량%, F: 0.01∼0.20질량%, Al: 0.05∼0.50질량%, Mg: 0.05∼0.50질량%를 함유함과 더불어, 수학식 1∼3을 만족시키는 조성으로 한다. [수학식 1] [수학식 2] [수학식 3] PROBLEM TO BE SOLVED: To provide a flux-built-in wire for gas shielded arc welding which is excellent in welding workability and satisfactory in porosity, bead shape and slag releasability in fillet welding. A flux-built-in wire for gas shielded arc welding is composed of 1.0 to 4.0 mass% of Ti, 0.5 to 2.5 mass% of Si, 0.1 to 0.6 mass% of Zr, 2.0 to 3.0 mass% of Mn, 0.01 to 0.20% by mass of Na, 0.01 to 0.20% by mass of K, 0.01 to 0.20% by mass of F, 0.01 to 0.20% by mass of Al, 0.02 to 0.10% by mass of C, 0.005 to 0.0030% by mass of S, 0.005 to 0.040% : 0.05 to 0.50% by mass, Mg: 0.05 to 0.50% by mass, and satisfies the following formulas (1) to (3). [Equation 1] &Quot; (2) &quot; &Quot; (3) &quot;

Au-Ag based alloy wire for a semiconductor package

높은 건조 신뢰성뿐만 아니라 높은 고습 신뢰성을 갖는 반도체 패키지용 금-은 합금계 와이어가 제공된다. 본 발명에 따른 반도체 패키지용 와이어는 금(Au)에 10 내지 40 중량%의 은(Ag)을 첨가한 금-은 합금계에, 팔라듐(Pd) 및 백금(Pt)으로 이루어지는 1군 원소들 중 적어도 1종 이상의 원소를 5 내지 15 중량% 함유하는 제 1 첨가 성분을 포함하여 형성된다. There is provided a gold-silver alloy based wire for semiconductor packages having high dry reliability as well as high high humidity reliability. The wire for a semiconductor package according to the present invention is a gold-silver alloy system in which 10 to 40% by weight of silver (Ag) is added to gold (Au), among the group 1 elements consisting of palladium (Pd) and platinum (Pt). It is formed including a first additive component containing 5 to 15% by weight of at least one or more elements.

Semiconductor devices

本发明公开了半导体器件。特别是提供一种在构成LCD驱动器的长方形形状的半导体芯片中，通过改进短边方向的平面配置方案以缩短半导体芯片尺寸的技术。具体是：构成LCD驱动器的半导体芯片CHP2中，多个输入保护电路3a～3c布置在多个输入用突起电极IBMP中的一部分输入用突起电极IBMP的下层。另一方面，在多个输入用突起电极IBMP中的其他的输入用突起电极IBMP的下层不配置输入保护电路3a～3c，而是配置有SRAM2a～2c(内部电路)。

Nitride semiconductor device

Method for producing an electronic component and electronic component produced by this method

Für ein elektronisches Bauteil mit einem auf einem Halbleiter-Substrat integrierten Schaltkreis und der wärmeleitenden Verbindung des Substrats durch Verlöten mit einem als Wärmesenke dienenden Träger wird vorgeschlagen, in der gebräuchlichen Rückseitenmetallisierung des Substrats eine erste, dickere Au-Schicht 23, nach dieser eine Barrierenschicht 24 und als letzte Schicht eine dünnere, zweite Au-Schicht 25 abzuscheiden, wobei das Material der Barrierenschicht so gewählt ist, dass die Barrierenschicht beim Lötvorgang eine Diffusionsbarriere gegen das Vordringen von Sn bzw. AuSn aus einer flüssigen Au-Sn-Phase im Bereich der zweiten Au-Schicht in die erste Au-Schicht 23 verhindert.

Method for producing an electronic component and component produced according to said method

The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au-Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Method for the production of an electronic component and electronic component produced according to this method

The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer ( 23 ) in the conventional back-side metallization of the substrate, thereafter a barrier coating ( 24 ), and, as the last layer, a thinner, second Au layer ( 25 ), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer ( 23 ) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Electronic component of a high frequency current suppression type and bonding wire for the same

고주파에서 이용될 때에도 전자기 간섭이 발생하는 것을 방지하기 위하여 고주파 전류를 와전하게 억제할 수 있는 고주파 전류 억제형 전자 부품을 제공하기 위하여, 그리고 상기 전자 부품용 접합 와이어를 제공하기 위하여, 반도체 집적 회로 소자(IC)(17)는 고주파에서 이용시 고속으로 동작하고 소정 수의 단자(19)에는 단자들 자체를 통과하는 고주파 전류를 감쇠시키는 고주파 전류 억제기(21)가 제공된다. 이러한 고주파 전류 억제기(21)는 03 내지 20μm 두께를 가진 박막 필름 자기 물질이며 각각의 단자(19)의 전체 표면상에 배치되는데, 상기 단자의 전체 표면은 반도체 집적 회로 소자(IC)(17)를 장착하기 위한 인쇄회로기판(23)상에 장착될 장착 부분 및 인쇄회로기판(23)상에 배치된 도전성 패턴에 대한 접속 부분을 포함하는 에지를 커버한다. IC(17)를 인쇄회로기판(23)에 장착할 때 땜납(27)에 의하여 상부 단부가 도전성 패턴(17)과 연결될 때, 상기 장착 부분 근처는 몇십 MHz 이하인 사용 주파수 대역에서 전도성을 가진다.

Manufacturing method of a semiconductor device

一种半导体器件的制造方法。提高采用倒装片安装方法的半导体器件的密封方法的产量。在模塑过程中，其中在模塑装置的空腔内压为负压的状态下、用密封树脂将通过凸起电极安装在基板母体的零部件安装表面上的多个半导体晶片(IC)一起密封，通过模具的下模和上模而夹紧基板母体时的夹紧压力在注入密封树脂的初始阶段被设定为相对较小的压力，并且在密封树脂已经覆盖了沿树脂注入方向的最终阶段中的半导体晶片IC时切换成相对较高的压力。

Interconnection structure and its forming method

一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构包括两层、三层或四层焊球受限冶金，该焊球受限冶金包括粘合/反应阻挡层，并且具有与含锡无铅焊料的组分反应的焊料可润湿层，从而在焊接的过程中可焊接层可以全部被消耗掉，但是，在焊接的过程中阻挡层在其被放置成与无铅焊料接触之后保留下来。一个或多个无铅焊球，其选择性地位于所述焊料可润湿层上，所述无铅焊球包含作为主要组分的锡和一种或多种合金组分。

Connecting film, bonded body and method for manufacturing the bonded body

도전성 입자의 보충 효율 및 도통 신뢰성 양쪽 모두가 우수한 접속 필름, 및 접합체 및 그 제조 방법을 제공하는 것을 목적으로 한다. 상기 접속 필름은, 제1 회로 부재와, 상기 제1 회로 부재와 대향하는 면에 질소 원자를 함유하는 막이 형성된 제2 회로 부재를 전기적으로 접속하는 접속 필름으로서, 상기 제1 회로 부재측에 배치되는 제1 층과, 상기 제2 회로 부재측에 배치되는 제2 층을 구비하고, 상기 제1 층은 양이온계 경화제 및 에폭시 수지를 함유하며, 상기 제2 층은 라디칼계 경화제, 아크릴 수지 및 에폭시 화합물을 함유하고, 상기 제1 및 제2 층 중 어느 하나는, 도전성 입자를 함유하는 도전성 입자 함유 유기 수지층이며, 상기 제1 및 제2 층의 다른 하나는, 도전성을 갖지 않는 절연성 유기 수지층이고, 상기 도전성 입자 함유 유기 수지층의 최저 용융 점도는, 상기 절연성 유기 수지층의 최저 용융 점도의 10배 이상이다.

Patent JPS6119106B2

Method for forming bump on electrode pad with use of double-layered film

본 발명의 전극 패드상에의 범프 형성방법은 기재와 다수의 전극 패드를 포함하는 배선기판 위에 적어도 하기 (a) 내지 (d)의 공정; The bump forming method on the electrode pad of the present invention comprises at least the following steps (a) to (d) on a wiring board including a substrate and a plurality of electrode pads; (a) 배선기판 위에, 하층이 알칼리 가용성이면서 비감방사선성 수지 조성물을 포함하고, 상층이 네가티브형 감방사선성 수지 조성물을 포함하는 2층 적층막을 형성한 후, 전극 패드의 대응위치에 개구 패턴을 형성하는 공정, (a) After forming a two-layer laminated film on the wiring board, wherein the lower layer contains an alkali-soluble non-radiative resin composition and the upper layer comprises a negative radiation-sensitive resin composition, the opening pattern is formed at a corresponding position of the electrode pad. Forming process, (b) 상기 개구 패턴 내에 저융점 금속을 도입하는 공정, (b) introducing a low melting point metal into the opening pattern; (c) 프레스 또는 가열처리함으로써 상기 저융점 금속을 리플로해서 범프를 형성하는 공정, 및 (c) a step of reflowing the low melting metal to form a bump by press or heat treatment, and (d) 상기 2층 적층막을 기판으로부터 박리·제거하는 공정 (d) peeling and removing the two-layer laminated film from the substrate; 을 행하는 것을 특징으로 한다. 이와 같이 특성이 다른 2층 적층막을 이용함으로써, 고해상성과 박리용이성의 양립이 가능해진다. It is characterized by performing. Thus, by using a two-layer laminated film having different properties, both high resolution and easy peelability can be achieved. 전극 패드, 범프 형성방법, 배선 기판, 개구 패턴, 2층 적층막, 네가티브형 감방사선성 수지 조성물, 비감방사선성 수지 조성물, 드라이 필름, 레지스트 Electrode pad, bump forming method, wiring board, opening pattern, two-layer laminated film, negative radiation-sensitive resin composition, non-radiation-sensitive resin composition, dry film, resist

Method for producing an electronic component and component produced according to said method

The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au-Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Separation method of semiconductor device

It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100 . An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107 , thereby forming a high frequency module or the like.

Semiconductor device

(57)【要約】 【目的】半導体集積回路素子の多ピン化、小型化、高機 能化などの進歩に対応できる半導体集積回路素子および 半導体集積回路素子パッケージの電極端子と電子回路の 端子との接続構造を、信頼性の高い方法で実現するこ と。 【構成】半導体集積回路素子および半導体集積回路素子 パッケージの各電極端子と、少なくとも銅、銅合金およ びそれらの酸化物からなる銅はくを用いて製造された電 子回路上の端子を半田などを介して接続した半導体装置 で、その銅はくは、接着基材との接着面に金属、合金、 酸化物、水酸化物、および水和物から選ばれる一層以上 の被覆層を有し、その上にシラザン系化合物の加熱加湿 分解により生成したシリカ層がある。接着基材は高強 度、高伸び性もつ合成樹脂層で、銅はくと積層基材を接 着する。半導体側の端子から数えて半田などの接続層、 銅はく層、金属被覆層、シリカ層、接着基材層および積 層基材層からなる少なくとも六乃至七層の接続層構成を 持つ半導体装置。

Semiconductor package and method of manufacturing the same

A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

PROCESS FOR MANUFACTURING MICROWIRES, DEVICE FOR CARRYING OUT SAID METHOD AND MICROWIRES OBTAINED BY SAID PROCESS

Metal electrode capacitor forming a film

Method of hybridization and positioning of an opto-electronic component and application of this method to the positioning of this component with respect to an integrated optical guide.

Procédé d'hybridation et de positionnement d'un composant opto-électronique sur un substrat et application de ce procédé au positionnement d'une diode laser par rapport à un guide optique. Ce procédé consiste à former des cales d'épaisseur (24) sur le substrat (6) dont la hauteur fixe le positionnement vertical du composant (2), ce dernier étant équipé de plots (32) en un premier matériau, former des plots (26) en un second matériau sur le substrat, former sur les plots de second matériau une galette (28) de soudure en un matériau fusible apte à mouiller à l'état fondu les premier et second matériaux et pas leur environnement, mettre le composant au contact de la galette de soudure de façon que les plots du composant recouvrent la galette, la hauteur de la cale d'épaisseur étant inférieure à l'épaisseur séparant le composant du substrat, porter l'ensemble à la température de fusion des galettes et ramener l'ensemble à une température inférieure à leur température de fusion. Method of hybridization and positioning of an opto-electronic component on a substrate and application of this method to the positioning of a laser diode relative to an optical guide. This process consists in forming shims (24) on the substrate (6), the height of which fixes the vertical positioning of the component (2), the latter being equipped with pads (32) in a first material, forming pads ( 26) in a second material on the substrate, form on the pads of the second material a solder plate (28) in a fusible material capable of wetting in the molten state the first and second materials and not their environment, put the component in contact of the solder plate so that the pads of the component cover the plate, the height of the shim being less than the thickness separating the component from the substrate, bring the assembly to the melting temperature of the plates and bring back the whole at a temperature below their melting point.

Semiconductor devices and method for making them

Patent FR2311430B1

Difficulties in forming a ball on the end of a wire of aluminium or aluminium alloy for ball bonding are overcome by applying between the wire and an electrode a low voltage, typically 30 volts, and bringing the wire and electrode into temporary contact to fuse the wire and initiate a spark discharge which results in the formation of a ball on the wire end. The spark discharge takes place in a shielding gas to avoid oxidation of the ball.

FIELD-EFFECT TRANSISTOR FOR MICROWAVE IN CONTACT WITH ELECTRODES THROUGH THE SUPPORT

A microwave field effect transistor (FET) comprises source, gate, and drain electrodes deposited on an epitaxial layer grown on a semi-insulating substrate. The FET has lowered thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxial layer. The chip, comprising the substrate, epitaxial layer, and top electrodes, is mounted on a heat sink. The chip's underside, including the bottom surface of the plated through source contact, is conductively bonded to the top surface of the heat sink.

Thin film capacitor and method for manufacturing the same, electronic device and circuit board

IMPROVEMENTS TO FIELD EFFECT TRANSISTORS AND THEIR MANUFACTURING

L'invention concerne un procédé de fabrication d'un transistor à effet de champ consistant, successivement, à former une couche 4 de matière semi-conductrice (par exemple GaAs) à la surface d'un premier substrat 1 en matière semi-conductrice (par exemple également GaAs), à former une électrode de goulot 7 sur une face de la couche active, à appliquer un second substrat 11 de matière isolante sur une face de cette structure, à éliminer le premier substrat, et à former les électrodes de cathode et d'anode sur la face de la couche active opposée à l'électrode de goulot. Facultativement, l'élimination du premier substrat par attaque corrosive sélective est facilitée par l'addition d'une couche intermédiaire 2 en GaAlAs entre le premier et le second substrats. Une seconde électrode de goulot pourra être formée sur la face de la couche active opposée à celle portant la première électrode de goulot. Le procédé convient particulièrement à la fabrication des T.E.C. pour hautes fréquences. The invention relates to a method of manufacturing a field effect transistor consisting, in succession, of forming a layer 4 of semiconductor material (for example GaAs) on the surface of a first substrate 1 of semiconductor material ( for example also GaAs), in forming a neck electrode 7 on one face of the active layer, in applying a second substrate 11 of insulating material on one face of this structure, in removing the first substrate, and in forming the cathode electrodes and anode on the face of the active layer opposite the neck electrode. Optionally, the removal of the first substrate by selective corrosive attack is facilitated by the addition of an intermediate layer 2 of GaAlAs between the first and the second substrates. A second neck electrode may be formed on the face of the active layer opposite to that carrying the first neck electrode. The process is particularly suitable for the manufacture of T.E.C. for high frequencies.

Tin-silver solder bumping during electronics is made

一种用于在制造微电子仪器的凸点下金属结构上形成焊接凸点的方法包括使凸点下金属结构暴露于电解槽，其中该电解槽包括一种Sn 2+ 离子源，一种Ag + 离子源，一种硫脲化合物和/或一种季铵盐表面活性剂；并且为电解槽提供一种外部电子源从而将锡银合金沉积在凸点下金属结构上面。