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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 122756. Отображено 100.
05-01-2012 дата публикации

Semiconductor device

Номер: US20120001243A1
Автор: Kiyoshi Kato
Принадлежит: Semiconductor Energy Laboratory Co Ltd

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

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Номер записи: 1
05-01-2012 дата публикации

Semiconductor Constructions

Номер: US20120001299A1
Автор: Todd Jackson Plum
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

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Номер записи: 2
05-01-2012 дата публикации

Grounding switch method and apparatus

Номер: US20120002821A1
Автор: Christian Larsen, Lorenzo Crespi
Принадлежит: Conexant Systems LLC

A grounding switch is described which operates properly even in the presence of negative voltages on a signal line. The grounding switch uses isolated field effect transistors that have their substrates tied to different voltages. The isolated field effect transistor has a gate voltage and substrate voltage which can be pulled down to a negative voltage when the signal line has a negative voltage allowing the switch to remain open even with a negative voltage.

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Номер записи: 3
05-01-2012 дата публикации

Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby

Номер: US20120003800A1
Автор: Changhyun LEE, Hansoo Kim, Jaehoon Jang, Kihyun Kim, Sunghoi Hur, Sunil Shim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

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Номер записи: 4
02-07-2018 дата публикации

Интегральный датчик перегрева ключа

Номер: RU0000180943U1
Автор: Андрей Михайлович Цырлов, Михаил Александрович Черкасов
Принадлежит: Акционерное общество "Протон" (АО "Протон")

Полезная модель относится к коммутационной технике и может быть использована в качестве встроенного устройства контроля управления силовым ключевым устройством. Технический результат заключается в точном контроле перегрева тепловыделяющего кристалла ключевого МОП транзистора, расположенного на одном кристалле с сенсором.Для достижения данного технического результата встроенный температурный датчик, формирователь опорного напряжения, аналоговый компаратор сигналов и схема управления затвором МОП транзистора выполнены в едином КМОП базисе и располагаются на одном кристалле с ключевым МОП транзистором, при этом настройка и регулировка температуры перегрева устанавливаются посредством дополнительного вывода. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 180 943 U1 (51) МПК H02H 9/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G01K 7/00 (2006.01); H01L 27/00 (2006.01); H03M 1/00 (2006.01); H02H 9/00 (2006.01); H03K 17/00 (2006.01) (21)(22) Заявка: 2017132135, 13.09.2017 13.09.2017 (73) Патентообладатель(и): Акционерное общество "Протон" (АО "Протон") (RU) Дата регистрации: 02.07.2018 (56) Список документов, цитированных в отчете о поиске: RU 2244936 C2, 20.01.2005. RU (45) Опубликовано: 02.07.2018 Бюл. № 19 1 8 0 9 4 3 R U (54) ИНТЕГРАЛЬНЫЙ ДАТЧИК ПЕРЕГРЕВА КЛЮЧА (57) Реферат: Полезная модель относится к коммутационной формирователь опорного напряжения, технике и может быть использована в качестве аналоговый компаратор сигналов и схема встроенного устройства контроля управления управления затвором МОП транзистора силовым ключевым устройством. Технический выполнены в едином КМОП базисе и результат заключается в точном контроле располагаются на одном кристалле с ключевым перегрева тепловыделяющего кристалла МОП транзистором, при этом настройка и ключевого МОП транзистора, расположенного регулировка температуры перегрева на одном кристалле с сенсором. устанавливаются посредством дополнительного Для достижения ...

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Номер записи: 5
03-08-2018 дата публикации

Элемент памяти на основе ассиметричных мемристорных наноструктур

Номер: RU0000182101U1
Автор: Владимир Александрович Смирнов, Марина Владимировна Ильина, Олег Алексеевич Агеев, Роман Викторович Томинов
Принадлежит: федеральное государственное автономное образовательное учреждение высшего образования "Южный федеральный университет" (Южный федеральный университет)

Полезная модель относится к области электроники и вычислительной техники, конкретно к электрически перепрограммируемым запоминающим устройствам, и может быть использована при создании интегральных схем с наноразмерными элементами памяти. Элемент памяти на основе асимметричных мемристорных наноструктур состоит из изолирующей подложки, нижнего проводящего контакта, запоминающего слоя и верхнего проводящего контакта. При этом запоминающий слой выполнен в виде асимметричных мемристорных наноструктур, имеющих форму усеченного конуса. Технический результат заключается в увеличении быстродействия элемента памяти. 3 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 182 101 U1 (51) МПК H01L 27/00 (2006.01) B82B 1/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 27/00 (2018.05); B82B 1/00 (2018.05) (21)(22) Заявка: 2018112923, 09.04.2018 (24) Дата начала отсчета срока действия патента: Дата регистрации: 03.08.2018 (45) Опубликовано: 03.08.2018 Бюл. № 22 2016380192 A1, 29.12.2016. US 2005243630 A1, 03.11.2005. RU 2602765 C1, 20.11.2016. (54) ЭЛЕМЕНТ ПАМЯТИ НА ОСНОВЕ АССИМЕТРИЧНЫХ МЕМРИСТОРНЫХ НАНОСТРУКТУР (57) Реферат: Полезная модель относится к области нижнего проводящего контакта, запоминающего электроники и вычислительной техники, слоя и верхнего проводящего контакта. При этом конкретно к электрически перепрограммируемым запоминающий слой выполнен в виде запоминающим устройствам, и может быть асимметричных мемристорных наноструктур, использована при создании интегральных схем с имеющих форму усеченного конуса. Технический наноразмерными элементами памяти. Элемент результат заключается в увеличении памяти на основе асимметричных мемристорных быстродействия элемента памяти. 3 ил. наноструктур состоит из изолирующей подложки, R U 1 8 2 1 0 1 (56) Список документов, цитированных в отчете о поиске: RU 148262 U1, 27.11.2014. US Стр.: 1 U 1 U 1 Адрес для переписки: 347922, Ростовская обл., г. Таганрог, Некрасовский ...

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Номер записи: 6
17-09-2021 дата публикации

Ограничитель СВЧ мощности

Номер: RU0000206619U1
Автор: Артём Меджлумович Сарибекян, Руслан Робертович Кинзябулатов
Принадлежит: Общество с ограниченной ответственностью "АРГУС-ЭТ"

Полезная модель относится к радиотехнике и может быть использован в качестве защитного устройства на входе приемных каналов электронной аппаратуры для защиты от сигналов высокого уровня СВЧ-мощности, а также сигналов с частотами вне рабочей полосы пропускания. Ограничитель выполнен на основе микрополосковой линии в виде каскадов с pin-диодами, причем один из каскадов соединен с землей через дроссель, один конец линии является входом ограничителя, а другой конец - его выходом. Входной полосок микрополосковой линии дополнительно соединен с двумя разомкнутыми микрополосками, концы которых соединены с анодами дополнительных pin-диодов, катоды которых соединены с землей, а катоды pin-диодов в остальных каскадах также соединены с землей. Достигаемым техническим результатом является увеличение быстродействия ограничителя СВЧ-мощности. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 206 619 U1 (51) МПК H01L 27/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 27/00 (2021.05) (21)(22) Заявка: 2021115031, 25.05.2021 (24) Дата начала отсчета срока действия патента: (73) Патентообладатель(и): Общество с ограниченной ответственностью "Аргус-ЭТ" (RU) Дата регистрации: 17.09.2021 (56) Список документов, цитированных в отчете о поиске: RU 2097877 C1, 27.11.1997. RU 2258278 C2, 10.08.2005. US 20020180552 A1, 05.12.2002. US 0008918068 B1, 23.12.2014. (45) Опубликовано: 17.09.2021 Бюл. № 26 2 0 6 6 1 9 R U (54) Ограничитель СВЧ мощности (57) Реферат: Полезная модель относится к радиотехнике и может быть использован в качестве защитного устройства на входе приемных каналов электронной аппаратуры для защиты от сигналов высокого уровня СВЧ-мощности, а также сигналов с частотами вне рабочей полосы пропускания. Ограничитель выполнен на основе микрополосковой линии в виде каскадов с pinдиодами, причем один из каскадов соединен с землей через дроссель, один конец линии является Стр.: 1 входом ограничителя, а другой конец - его ...

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Номер записи: 7
12-01-2012 дата публикации

Reconfigurable Multilayer Circuit

Номер: US20120007038A1
Автор: Dmitri Borisovich Strukov, R. Stanley Williams, Yevgeniy Eugene Shteyn
Принадлежит: Hewlett Packard Development Co LP

A reconfigurable multilayer circuit ( 400 ) includes a complimentary metal-oxide-semiconductor (CMOS) layer ( 210 ) having control circuitry, logic gates ( 515 ), and at least two crossbar arrays ( 205, 420 ) which overlie the CMOS layer ( 210 ). The at least two crossbar arrays ( 205, 420 ) are configured by the control circuitry and form reconfigurable interconnections between the logic gates ( 515 ) within the CMOS layer ( 210 ).

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Номер записи: 8
12-01-2012 дата публикации

Nitride-based semiconductor device and method for manufacturing the same

Номер: US20120007049A1
Автор: Jung Hee Lee, Ki Yeol Park, Woo Chul Jeon, Young Hwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

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Номер записи: 9
19-01-2012 дата публикации

Semiconductor device

Номер: US20120012837A1
Автор: Kiyoshi Kato, Shuhei Nagatsuka, Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t a /t b )×(ε ra /ε rb )<0.1, where t a represents the thickness of the gate insulating layer, t b represents the thickness of the insulating layer, ε ra represents the dielectric constant of the gate insulating layer, and ε rb represents the dielectric constant of the insulating layer.

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Номер записи: 10
19-01-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120012944A1
Автор: Jae-Yun YI
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

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Номер записи: 11
19-01-2012 дата публикации

Lateral transient voltage suppressor for low-voltage applications

Номер: US20120012974A1
Автор: Che-Hao Chuang, Kun-Hsien LIN, Ryan Hsin-Chin Jiang
Принадлежит: Amazing Microelectronic Corp

A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.

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Номер записи: 12
19-01-2012 дата публикации

Capacitors and methods of forming

Номер: US20120012982A1
Автор: Boyi Yang, Jacek Korec, Jun Wang, Shuming Xu
Принадлежит: Texas Instruments Inc

Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers.

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Номер записи: 13
26-01-2012 дата публикации

Signal processing device and photodetection device

Номер: US20120018621A1
Автор: Hiroo Yamamoto, Makoto Kobayashi, Seiichiro Mizuno
Принадлежит: Hamamatsu Photonics KK

In a signal processing device of an embodiment, an integration circuit accumulates a charge from a photodiode in an integrating capacitor element, and outputs a voltage value according to the amount of charge. A comparator circuit, when the voltage value from the integration circuit has reached a reference value, outputs a saturation signal. A charge injection circuit, in response to the saturation signal, injects an opposite polarity of charge into the integrating capacitor element. A counter circuit performs counting based on the saturation signal. A holding circuit holds the voltage value from the integration circuit. An amplifier circuit outputs a voltage value that is K times (where K>1) larger than the voltage value held by the holding circuit. An A/D converter circuit sets a voltage value that is K times larger than the reference value as the maximum input voltage value, that is, a full-scale value, and outputs a digital value corresponding to the voltage value from the amplifier circuit.

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Номер записи: 14
26-01-2012 дата публикации

Electrostatic discharge protection device and method for fabricating the same

Номер: US20120018775A1
Автор: Lijie Zhang, Ru Huang
Принадлежит: PEKING UNIVERSITY

The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

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Номер записи: 15
26-01-2012 дата публикации

Esd protection device with vertical transistor structure

Номер: US20120018778A1
Автор: Kun-Hsien LIN, Ryan Hsin-Chin Jiang, Zi-Ping Chen
Принадлежит: Amazing Microelectronic Corp

A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P + substrate), a n-type well (N well) in the P + substrate, a heavily doped p-type diffusion (P + diffusion) in the N well, a heavily doped n-type diffusion (N + diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P + substrate. A bond pad is connected to both the P + and N + diffusions, and a ground is coupled to the P + substrate. Another P + diffusion is implanted in the N well or another N + diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P + substrate and the N well, to bypass a negative ESD stress on the bond pad.

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Номер записи: 16
26-01-2012 дата публикации

Forming bipolar transistor through fast epi-growth on polysilicon

Номер: US20120018811A1
Автор: Chih-Ping Chao, Der-Chyang Yeh, Hua-Chou Tseng, Li-Weng Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.

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Номер записи: 17
26-01-2012 дата публикации

Array configuration and readout scheme

Номер: US20120022795A1
Автор: Jeremy JORDAN, Kim Johnson, Mark Milgrew, Peter Levine
Принадлежит: Life Technologies Corp

The described embodiments may provide a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be coupled to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be coupled to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants.

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Номер записи: 18
02-02-2012 дата публикации

Semiconductor wafer, method of producing semiconductor wafer, and electronic device

Номер: US20120025268A1
Автор: Osamu Ichikawa
Принадлежит: Sumitomo Chemical Co Ltd

There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.

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Номер записи: 19
02-02-2012 дата публикации

Temperature monitoring in a semiconductor device by using a pn junction based on silicon/germanium materials

Номер: US20120025276A1
Автор: Anthony Mowry, Gert Burbach, Markus Forsberg, Rolf Stephan
Принадлежит: Advanced Micro Devices Inc

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

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Номер записи: 20
02-02-2012 дата публикации

Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer

Номер: US20120025345A1
Автор: Alan B. Botula, Alvin J. Joseph, James A. Slinkman, Randy L. Wolf
Принадлежит: International Business Machines Corp

A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

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Номер записи: 21
02-02-2012 дата публикации

Semiconductor device and semiconductor package including the same

Номер: US20120025349A1
Автор: Hyun-seok Kim, Hyung-Dong Lee, Jun-Ho Lee
Принадлежит: Individual

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

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Номер записи: 22
02-02-2012 дата публикации

Semiconductor device having switching element and free wheel diode and method for controlling the same

Номер: US20120025874A1
Автор: Hirotaka Saikaku, Hitoshi Yamaguchi, Jun Sakakibara, Makoto Kuwahara, Masakiyo Sumitomo, Rie Taguchi, Shoji Mizuno, Tetsuo Fujii, Tsuyoshi Yamamoto, Yoshiyuki Hattori
Принадлежит: Denso Corp

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

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Номер записи: 23
02-02-2012 дата публикации

Method of manufacturing semiconductor device using acid diffusion

Номер: US20120028434A1
Автор: Hyoung-hee KIM, Hyung-Rae Lee, Kyung-Hwan Yoon, So-Ra Han, Tae-hoi Park, Yool Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

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Номер записи: 24
02-02-2012 дата публикации

Method of manufacturing a semiconductor device

Номер: US20120028471A1
Автор: Hidetami Yaegashi, Kazuo Yabe, Kenichi Oyama
Принадлежит: Tokyo Electron Ltd

A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.

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Номер записи: 25
09-02-2012 дата публикации

Trench mosfet having floating dummy cells for avalanche improvement

Номер: US20120032261A1
Автор: Fu-Yuan Hsieh
Принадлежит: Force Mos Technology Co Ltd

A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

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Номер записи: 26
09-02-2012 дата публикации

Depletion mode field effect transistor for esd protection

Номер: US20120032270A1
Автор: Josef Muenz, Yohichi Okumura
Принадлежит: Texas Instruments Inc

A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18 D (D) is formed inside the gate electrode, and source regions 18 S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

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Номер записи: 27
09-02-2012 дата публикации

N-well/p-well strap structures

Номер: US20120032276A1
Автор: Andy Lee, Bradley Jensen, Dustin Do, Giles V. Powell, Swee Aun Lau, Thomas H. White, Wuu-Cherng Lin
Принадлежит: Altera Corp

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

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Номер записи: 28
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

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Номер записи: 29
09-02-2012 дата публикации

Semiconductor Device and Power Supply Unit Utilizing the Same

Номер: US20120032713A1
Автор: Atsushi Kitagawa
Принадлежит: ROHM CO LTD

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

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Номер записи: 30
09-02-2012 дата публикации

Semiconductor integrated device

Номер: US20120032730A1
Автор: Jun Koyama
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

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Номер записи: 31
09-02-2012 дата публикации

Semiconductor device manufacturing method

Номер: US20120034785A1
Автор: Hisataka Hayashi, Tsubasa IMAMURA, Yusuke KASAHARA
Принадлежит: Individual

According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).

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Номер записи: 32
16-02-2012 дата публикации

Semiconductor device with less power supply noise

Номер: US20120037959A1
Автор: Tetsuya Katou
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

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Номер записи: 33
16-02-2012 дата публикации

Reduced process sensitivity of electrode-semiconductor rectifiers

Номер: US20120037982A1
Автор: John L. Benjamin, Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs
Принадлежит: Individual

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

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Номер записи: 34
16-02-2012 дата публикации

Low capacitance precision resistor

Номер: US20120038026A1
Автор: Steven R. Soss
Принадлежит: Globalfoundries Inc

A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.

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Номер записи: 35
23-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120043587A1
Автор: Tsuyoshi Takahashi
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.

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Номер записи: 36
23-02-2012 дата публикации

Electrostatic discharge (esd) protection device, method of fabricating the device, and electronic apparatus including the device

Номер: US20120043643A1
Автор: Dong-Ryul Chang, Oh-kyunm Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

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Номер записи: 37
01-03-2012 дата публикации

Display device

Номер: US20120049184A1
Автор: Atsushi Umezaki, Hiroyuki Miyake
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

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Номер записи: 38
01-03-2012 дата публикации

Light emitting device

Номер: US20120049208A1
Автор: Chao Hsing Chen, Chien Fu Shen, Hsin Mao Liu, Schang Jing Hon, Tsun Kai Ko
Принадлежит: Individual

The present disclosure provides a light emitting device, including a serially-connected LED array including a plurality of LED cells on a single substrate, including a first LED cell, a second LED cell, and a serially-connected LED sub-array including at least three LED cells intervening the first and second LED cell, wherein each of the first and second LED cell including a first side and a second side that the first side of the first LED cell and/or the second LED cell neighboring to the LED sub-array, and the second side of the first LED cell neighboring to the second side of the second LED cell; a trench between the second sides of the first and second LED cells; and a protecting structure formed near the trench to prevent the light-emitting device from being damaged near the trench by a surge voltage higher than a normal operating voltage of the light emitting device.

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Номер записи: 39
01-03-2012 дата публикации

Vertical gated access transistor

Номер: US20120049246A1
Автор: Werner Juengling
Принадлежит: Micron Technology Inc

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

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Номер записи: 40
01-03-2012 дата публикации

Semiconductor devices and method of manufacturing the same

Номер: US20120049267A1
Автор: Young Kyun Jung
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

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Номер записи: 41
01-03-2012 дата публикации

High Voltage Semiconductor Devices

Номер: US20120049279A1
Автор: Cornelius Christian Russ, Harald Gossner, Maryam Shojaei Baghini, Mayank Shrivastava, Ramgopal Rao
Принадлежит: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY, INFINEON TECHNOLOGIES AG

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

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Номер записи: 42
01-03-2012 дата публикации

Nanolithographic method of manufacturing an embedded passive device for a microelectronic application, and microelectronic device containing same

Номер: US20120050940A1
Автор: Nachiket Raravikar, Rahul Panat
Принадлежит: Individual

A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate ( 110, 210, 310 ), nanolithographically forming a first section ( 121, 221, 321 ) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections ( 122, 222, 322 ) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

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Номер записи: 43
01-03-2012 дата публикации

Variable Capacitance Integrated Electronic Circuit Module

Номер: US20120052926A1
Автор: Guillaume Herault, Hervé Marie
Принадлежит: Individual

A digitally controlled variable capacitance integrated electronic circuit module ( 100 ) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block ( 11 ) which can be switched between two individual capacitance values, a control block ( 12 ), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions ( 110, 120 ) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

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Номер записи: 44
08-03-2012 дата публикации

Bidirectional silicon-controlled rectifier

Номер: US20120056238A1
Автор: Ming-Dou Ker, Ryan Hsin-Chin Jiang, Wen-Yi Chen
Принадлежит: Individual

A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.

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Номер записи: 45
08-03-2012 дата публикации

Power Supply Shunt

Номер: US20120057260A1
Автор: John Wood Poulton
Принадлежит: RAMBUS INC

A power supply shunt for an electronic circuit. The power supply shunt includes at least two Field Effect Transistors (FETs), a first of the FETs having its drain coupled to a terminal of an electronic circuit and its source coupled to another of the FETs, and a second of the FETs having its source coupled to ground and its drain coupled to another of the FETs. The first FET has a bulk terminal that floats with respect to ground.

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Номер записи: 46
08-03-2012 дата публикации

Methods of forming and programming an electronically programmable resistor

Номер: US20120058611A1
Автор: Benjamin T. Voegeli, Kimball M. Watson
Принадлежит: International Business Machines Corp

Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.

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Номер записи: 47
15-03-2012 дата публикации

Semiconductor on insulator (xoi) for high performance field effect transistors

Номер: US20120061728A1
Автор: Ali Javey, Hyunhyub Ko, Kuniharu Takei
Принадлежит: UNIVERSITY OF CALIFORNIA

Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO 2 substrate, thereby assembling an XOI substrate. The transfer process can be conducted through a stamping method or a bonding method. Multiple transfers can be carried out to form heterogenous compound semiconductor devices. The single-crystalline semiconductor can be II-IV or III-V compound semiconductor, such as InAs. A thermal oxide layer can be grown on the patterned single crystalline semiconductor, providing improved electrical characteristics and interface properties. In addition, strain tuning is accomplished via a capping layer formed on the single-crystalline semiconductor before transferring the single-crystalline semiconductor to the target substrate.

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Номер записи: 48
15-03-2012 дата публикации

Semiconductor device

Номер: US20120061747A1
Автор: Hitoshi Shinohara, Keiko Kawamura, Takeshi Uchihara, Yosefu Fujiki, Yusuke Kawaguchi
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.

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Номер записи: 49
15-03-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120064690A1
Автор: Takakazu Kiyomura, Toshiyuki Hirota
Принадлежит: Elpida Memory Inc

A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film.

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Номер записи: 50
22-03-2012 дата публикации

Low impedance transmisson line

Номер: US20120068238A1
Автор: Baher S. Haroun, Brian P. Ginsburg, Eunyoung Seok, Srinath M. Ramaswamy, Vijay B. Rentala
Принадлежит: Texas Instruments Inc

Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown.

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Номер записи: 51
22-03-2012 дата публикации

Conductive layers for hafnium silicon oxynitride

Номер: US20120068272A1
Автор: Kie Y. Ahn, Leonard Forbes
Принадлежит: Individual

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

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Номер записи: 52
22-03-2012 дата публикации

Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer

Номер: US20120068303A1
Автор: Hyung Sun Yook, Poh Ching Sim, Tsui Ping Chu
Принадлежит: Individual

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

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Номер записи: 53
22-03-2012 дата публикации

Field modulating plate and circuit

Номер: US20120068772A1
Автор: Ronaldus Johannus Martinus van Boxtel, Saad Kheder Murad
Принадлежит: Individual

Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.

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Номер записи: 54
29-03-2012 дата публикации

Semiconductor module including a switch and non-central diode

Номер: US20120074428A1
Автор: Gourab Majumdar, Kiyoshi Arai
Принадлежит: Mitsubishi Electric Corp

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

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Номер записи: 55
29-03-2012 дата публикации

3D Integrated circuit in planar process

Номер: US20120074505A1
Автор: Hang Yin, WenBo TIAN, Zhao Wang
Принадлежит: Vimicro Corp

Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

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Номер записи: 56
29-03-2012 дата публикации

Low Voltage Electrostatic Discharge Protection

Номер: US20120075758A1
Автор: William PUGSLEY
Принадлежит: Cambridge Silicon Radio Ltd

A protection circuit for protecting components from an electrostatic discharge at a node in an integrated circuit having a first set of electronic components of a first voltage sensitivity, the protection circuit comprising: detection circuitry arranged to detect an electrostatic discharge at the node; a first switching device connected between the first set of components and the node; and a second switching device connected between the node and ground; wherein, when an electrostatic discharge is detected at the node, the first switching device is configured to isolate the first set of components from the node and the second switching device is configured to provide a current path from said node to ground.

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Номер записи: 57
29-03-2012 дата публикации

DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES

Номер: US20120077287A1
Автор: Rajni J. Aggarwal, Scott R. Summerfelt
Принадлежит: Texas Instruments Inc

A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

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Номер записи: 58
29-03-2012 дата публикации

High-voltage tolerant voltage regulator

Номер: US20120077551A1
Автор: Florinel G. Balteanu, Jakub F. Pingot, Peter Harris Robert Popplewell
Принадлежит: Skyworks Solutions Inc

Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

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Номер записи: 59
05-04-2012 дата публикации

Semiconductor device

Номер: US20120080718A1
Автор: Akitaka SOENO
Принадлежит: Toyota Motor Corp

The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

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Номер записи: 60
05-04-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120080750A1
Автор: Gyung Tae Kim, Kang Youl Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias.

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Номер записи: 61
05-04-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120083079A1
Автор: Junji Oh
Принадлежит: Fujitsu Semiconductor Ltd

The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.

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Номер записи: 62
12-04-2012 дата публикации

Semiconductor device

Номер: US20120086063A1
Автор: Koji Taniguchi
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region; a bit line extending over the memory cell region and the peripheral circuit region, the bit line including a first portion in the peripheral circuit region; and a sense amplifier in the peripheral circuit region. The sense amplifier includes a transistor having a gate electrode which includes the first portion of the bit line.

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Номер записи: 63
12-04-2012 дата публикации

Semiconductor device and structure

Номер: US20120088367A1
Автор: Deepak C. Sekar, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

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Номер записи: 64
19-04-2012 дата публикации

Electrostatic Discharge Protection Circuit

Номер: US20120092798A1
Автор: Hsin-Yen Hwang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An electrostatic discharge (ESD) protection structure comprises a high voltage P type implanted region disposed underneath an N+ region. The high voltage P type implanted region and the N+ region form a reverse diode or a Zener diode depending on different doping densities. The ESD protection structure further comprises a plurality of P+ and N+ regions. The high voltage P type implanted region and the P+ and N+ regions form a semiconductor device having a breakdown characteristic. In one embodiment, the semiconductor device may be a bipolar PNP transistor. The bipolar PNP transistor and a Zener diode in series connection form an ESD protection circuit. In another embodiment, the semiconductor device may be a Silicon-Controlled Rectifier (SCR), which is series-connected with a reverse diode. Both embodiments provide a reliable ESD protection.

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Номер записи: 65
19-04-2012 дата публикации

Hybrid-mode ldmos

Номер: US20120094458A1
Автор: Jun Cai
Принадлежит: Fairchild Semiconductor Corp

An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

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Номер записи: 66
26-04-2012 дата публикации

Structure for shorting line connecting signal lines of flat panel display device

Номер: US20120097426A1
Автор: Euihyun Chung, Jiwon Kang, Wanjin SEO
Принадлежит: LG Display Co Ltd

A shorting line connecting first and second signal lines arranged in parallel with each other in a flat panel display device is disclosed. The shorting line includes a first branch portion connected with the first signal line and branched from the first signal line toward the second signal line; a second branch portion connected with the second signal line and extended from the second signal line toward the first signal line; and a connection portion connecting the first branch portion to the second branch portion, wherein one end of the connection portion is connected with the first branch portion at a first angle, and another end of the connection portion is connected with the second branch portion at a second angle.

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Номер записи: 67
26-04-2012 дата публикации

Dummy gate for a high voltage transistor device

Номер: US20120098063A1
Автор: Han-Chung Lin, Yung-Chih Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

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Номер записи: 68
26-04-2012 дата публикации

Resistive element and manufacturing method therefor

Номер: US20120098635A1
Автор: Keita Kumamoto
Принадлежит: Renesas Electronics Corp

A higher precision resistive element suppresses variation of the resistance value due to variation of film thickness. A resistive element includes a first portion having a first film thickness and a first width, and a second portion having the first film thickness and a second width determined by the first width. The sum of the first and second widths is constant. The first portion has an upper surface at a position at which a height from the bottom surface of the resistive element first portion is a first height. The resistive element second portion has an upper surface of the resistive element second portion at a position at which a height from a surface including the bottom surface of the resistive element first portion is the first height. The resistive element first portion and the resistive element second portion are coupled to each other via a coupling portion.

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Номер записи: 69
26-04-2012 дата публикации

Electrostatic discharge protection circuit

Номер: US20120099230A1
Автор: Jung-Eon Moon
Принадлежит: Hynix Semiconductor Inc

An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.

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Номер записи: 70
26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Автор: Kazuhiko Shimakawa, Ryotaro Azuma
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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Номер записи: 71
03-05-2012 дата публикации

Bi-directional scr esd device

Номер: US20120104459A1
Автор: Chih-Feng Huang
Принадлежит: RICHTEK TECHNOLOGY CORP

The present invention discloses a bi-directional SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a second well and a third well both located in the first well and both having a second conductivity type, the second well and the third well being separated from each other; a first high density doped region of the first conductivity type and a second high density doped region of the second conductivity type located in the second well; and a third high density doped region of the first conductivity type and a fourth high density doped region of the second conductivity type located in the third well.

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Номер записи: 72
03-05-2012 дата публикации

Three-dimensional semiconductor devices and methods of fabricating the same

Номер: US20120108048A1
Автор: Chang Sup Mun, Hyo Jung Kim, Jae Joo Shim, Jong Heun Lim, Kyung Hyun KIM
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.

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Номер записи: 73
03-05-2012 дата публикации

Split-Layer Design for Double Patterning Lithography

Номер: US20120110521A1
Автор: Kanak B. Agarwal, Lars W. Liebmann, Sani R. Nassif
Принадлежит: International Business Machines Corp

A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

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Номер записи: 74
10-05-2012 дата публикации

Method and system for manufacturing copper-based capacitor

Номер: US20120112315A1
Автор: LIN Huang, Yung Feng Lin, Zhen Chen
Принадлежит: Semiconductor Manufacturing International Shanghai Corp

Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer.

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Номер записи: 75
17-05-2012 дата публикации

3d semiconductor devices and methods of fabricating same

Номер: US20120119287A1
Автор: Hansoo Kim, Jintaek Park, Juhyuck Chung, Sang-Yong Park, Wonseok Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

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Номер записи: 76
17-05-2012 дата публикации

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

Номер: US20120119306A1
Автор: Alex Kalnitsky, Chia-Yi Su, Chien-Chih Ho, Chih-Ping Chao, Chun-Hung Chen, Harry-Hak-Lay Chuang, Hua-Chou Tseng, Jye-Yen Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

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Номер записи: 77
17-05-2012 дата публикации

Heater design for heat-trimmed thin film resistors

Номер: US20120119872A1
Автор: Calvin Leung, Olivier Le Neel
Принадлежит: STMICROELECTRONICS PTE LTD

A heater design for post-process trimming of thin-film transistors is described. The heater incorporates low sheet-resistance material deposited in non-active connecting regions of the heater to reduce heat generation and power consumption in areas distant from active heating members of the heater. The heating members are proximal to a thin-film resistor. The resistance of the thin-film resistor can be trimmed permanently to a desired value by applying short current pulses to the heater. Optimization of a heater design is described. Trimming currents can be as low as 20 mA.

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Номер записи: 78
17-05-2012 дата публикации

Semiconductor memory device

Номер: US20120120706A1
Автор: Takeshi Ohgami
Принадлежит: Elpida Memory Inc

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

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Номер записи: 79
24-05-2012 дата публикации

Non-volatile memory device and method of manufacturing the same

Номер: US20120126308A1
Автор: Beom Yong KIM, Kee Jeung Lee, Ki Hong Lee, Kwon Hong
Принадлежит: Individual

A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

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Номер записи: 80
24-05-2012 дата публикации

Semiconductor device having data bus

Номер: US20120127773A1
Автор: Hisayuki Nagamine, Takamitsu Onda
Принадлежит: Elpida Memory Inc

A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

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Номер записи: 81
24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Paul Lim, Ze&#39;ev Wurman, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

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Номер записи: 82
24-05-2012 дата публикации

Method of forming e-fuse in replacement metal gate manufacturing process

Номер: US20120129312A1
Автор: Gerald L. Leake, Henry K. Utomo, Ying Li
Принадлежит: International Business Machines Corp

Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.

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Номер записи: 83
31-05-2012 дата публикации

Semiconductor device

Номер: US20120132964A1
Автор: Kaoru Saigoh, Masashi Shima, Nobuhiro Misawa, Takao Sasaki
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.

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Номер записи: 84
31-05-2012 дата публикации

Oxide terminated trench mosfet with three or four masks

Номер: US20120132988A1
Автор: Anup Bhalla, Sik Lui
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

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Номер записи: 85
31-05-2012 дата публикации

Three dimensional integrated deep trench decoupling capacitors

Номер: US20120133023A1
Автор: Geng Wang, Kangguo Cheng, Ravi M. Todi, Roger A. Booth, Jr.
Принадлежит: International Business Machines Corp

A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.

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Номер записи: 86
31-05-2012 дата публикации

Semiconductor device

Номер: US20120135356A1
Автор: Makoto Sakuma, Takuya Futatsuyama
Принадлежит: Individual

A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

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Номер записи: 87
31-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120135601A1
Автор: Bok-yeon Won, Jong-Chul Park, Sang-Sup Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

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Номер записи: 88
07-06-2012 дата публикации

1t mim memory for embedded ram application in soc

Номер: US20120139022A1
Автор: Chen-Jong Wang, Chien-Hua Huang, Chun-Yao Chen, Chung S. Wang, Kun-Lung Chen, PING Yang, Shou-Gwo Wuu, Yi-Ching Lin
Принадлежит: Individual

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

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Номер записи: 89
07-06-2012 дата публикации

Poly Resistor and Metal Gate Fabrication and Structure

Номер: US20120139049A1
Автор: Narasimhulu Kanike
Принадлежит: International Business Machines Corp

A method is provided for fabricating a microelectronic device and a resistor on a substrate. The method can include forming device regions in a monocrystalline semiconductor region of a substrate, in which the device regions have edges defined according to a first semiconductor feature overlying a major surface of the semiconductor region. A dielectric region is formed having a planarized surface overlying the semiconductor region and overlying a second semiconductor feature disposed above a surface of an isolation region in the substrate. The surface of the isolation region can be disposed below the major surface. The method can further include removing at least a portion of the first semiconductor feature exposed at the planarized surface of the dielectric region to form an opening and forming a gate at least partially within the opening. Thereafter, further processing can include forming electrically conductive contacts extending through apertures in the dielectric region to the second semiconductor feature and the device regions, respectively. The step of forming electrically conductive contacts may include forming silicide regions contacting portions of the second semiconductor feature and the device regions, respectively. In such way, the method can define a resistor having a current path through the second semiconductor feature, and a microelectronic device including the gate and the device regions.

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Номер записи: 90
07-06-2012 дата публикации

Semiconductor device

Номер: US20120139055A1
Автор: Takayuki Yamada, Yoshihiro Sato
Принадлежит: Panasonic Corp

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

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Номер записи: 91
07-06-2012 дата публикации

Diode

Номер: US20120139079A1
Автор: Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Shinya Sakurai, Takashi Suzuki
Принадлежит: Denso Corp

A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

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Номер записи: 92
07-06-2012 дата публикации

Method of forming a high capacitance diode

Номер: US20120142171A1
Автор: David D. Marreiro, Earl D. Fuchs, Gordon M. Grivna, Sudhama C. Shastri
Принадлежит: Individual

In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

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Номер записи: 93
14-06-2012 дата публикации

Jfet devices with increased barrier height and methods of making the same

Номер: US20120146049A1
Автор: Chandra Mouli
Принадлежит: Micron Technology Inc

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

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Номер записи: 94
14-06-2012 дата публикации

High-voltage transistor device with integrated resistor

Номер: US20120146105A1
Автор: Sujit Banerjee, Vijay Parthasarathy
Принадлежит: Power Integrations Inc

A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

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Номер записи: 95
14-06-2012 дата публикации

Applying trenched transient voltage suppressor (tvs) technology for distributed low pass filters

Номер: US20120146717A1
Автор: Madhur Bobde
Принадлежит: Madhur Bobde

An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

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Номер записи: 96
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 97
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Автор: Roy E. Scheuerlein, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 98
14-06-2012 дата публикации

Semiconductor device manufacturing method that allows rework rate in manufacturing step to decrease

Номер: US20120149135A1
Автор: Shinji Yanagi, Takashi Sugimura
Принадлежит: Elpida Memory Inc

A semiconductor device manufacturing method includes: forming a first pattern in a first film to be processed on a semiconductor substrate; measuring a first distance, which is a dimension in a predetermined direction in the first pattern; forming a second film to be processed on the first pattern; forming a second pattern in a photoresist formed on the second film to be processed; and measuring a second distance, which is a dimension in a predetermined direction in the second pattern. Whether or not the second pattern is defective is determined based on either the first distance or a value calculated from the first and second distances.

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Номер записи: 99
14-06-2012 дата публикации

Schottky diode switch and memory units containing the same

Номер: US20120149183A1
Автор: Dadi Setiadi, Insik Jin, Nurul Amin, Venugopalan Vaithyanathan, WEI Tian, Young Pil Kim
Принадлежит: SEAGATE TECHNOLOGY LLC

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

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Номер записи: 100