Новаторское многослойное барьерное покрытие, способ его изготовления и композиция

Изобретение относится к многослойным барьерным материалам для защиты от диффузии паров и/или газов и касается многослойного барьерного покрытия, способа его изготовления и композиции. Барьерное покрытие содержит: барьерный материал, имеющий в составе дефекты; покрытие, полностью покрывающее дефекты барьерного материала, при этом дефекты включают выемки внутри барьерного материала и существенное количество упомянутого покрытия не выступает внутри упомянутых выемок. В рабочем состоянии упомянутого многослойного барьерного покрытия наличие покрытия уменьшает или предотвращает диффузию паров и/или молекул газа через выемки внутри упомянутого барьерного материала. Изобретение обеспечивает создание барьерного покрытия, защищающего чувствительные продукты от проникновения влаги и нежелательных газов окружающей среды. 4 н. и 13 з.п. ф-лы, 4 ил.

ИНКАПСУЛИРУЮЩАЯ БАРЬЕРНАЯ МНОГОСЛОЙНАЯ СТРУКТУРА

... 1. Инкапсулирующая барьерная многослойная структура, способная инкапсулировать изделие, чувствительное к влаге и/или кислороду, и содержащая многослойную пленку, включающую:- один или более барьерный слой с низкой влаго- и/или кислородопроницаемостью, и- один или более герметизирующий слой, расположенный в контакте с поверхностью по меньшей мере одного барьерного слоя и тем самым закрывающий и/или закупоривающий дефекты, присутствующие в барьерном слое,при этом указанный один или более герметизирующий слой содержит множество инкапсулированных наночастиц, реакционноспособных в том смысле, что они способны взаимодействовать с влагой и/или кислородом, замедляя проникновение влаги и/или кислорода.2. Инкапсулирующая барьерная многослойная структура по п. 1, отличающаяся тем, что указанный один или более герметизирующий слой по меньшей мере по существу состоит из инкапсулированных реакционноспособных наночастиц.3. Инкапсулирующая барьерная многослойная структура по п. 1 или 2, отличающаяся тем ...

МОНТАЖНЫЙ КОРПУС ЭЛЕКТРИЧЕСКОГО ЭЛЕМЕНТА, МАТРИЧНЫЙ КОРПУС И ЭЛЕКТРИЧЕСКОЕ УСТРОЙСТВО

Verfahren zur Herstellung von Hexahydropyrimidinderivaten

VERFAHREN ZUR HERSTELLUNG VON HALBLEITERANORDNUNGEN

Verfahren zum Herstellen von Halbleiteranordnungen

Flammhemmende Harzzusammensetzung und die daraus hergestellte Halbleitervorrichtung

Halbleitervorrichtung mit durch darauf erzeugte Passivierungsfilme gesteuerten Oberflaechenladungen und Verfahren zu ihrer Herstellung

Schottky-Diode und Verfahren zu ihrer Herstellung

Halbleiteranordnung

INTEGRIERTE HALBLEITERSCHALTUNG MIT MINDESTENS DREI IN REIHE ANGEORDNETEN FELDEFFEKTTRANSISTOREN MIT ISOLIERTER STEUERELEKTRODE

VERBESSERTE POLYARYLENETHERZUSAMMENSETZUNGEN UND VERFAHREN ZU IHRER HERSTELLUNG

VERFAHREN ZUM HERSTELLEN VON HALBLEITERBAUELEMENTEN

Verfahren zur Herstellung von Siliconformkörpern aus durch Licht vernetzbaren Siliconmischungen

Gegenstand der Erfindung ist ein Verfahren zur Herstellung von Siliconformkörpern, bei dem 1) eine durch Licht vernetzbare Siliconmischung geformt wird, 2) danach die geformte Siliconmischung mit Licht von 200 bis 500 nm bestrahlt wird, um diese so vorzuvernetzen, dass diese ihre Form bei einer Temperatur T beibehält und 3) danach die geformte und bestrahlte Siliconmischung bei der Temperatur T thermisch zu Formkörpern ausgehärtet wird.

VERFAHREN ZUR HERSTELLUNG GEAETZTER MUSTER

SEMICONDUCTOR DEVICE

... 1280943 Semi-conductor devices LICENTIA PATENT-VERWALTUNGS GmbH 25 Sept 1970 [27 Sept 1969] 45768/70 Heading H1K A semi-conductor device comprises a monocrystalline semi-conductor body with at least two regions of differing conductivity type, and a passivation layer on its surface, the layer being capable of assuming two different resistivity states. The layer may be of vitreous material, the states being of high resistivity, and low resistivity, both of which states are stable. In an embodiment a silicon body 17, including diffused regions 12, 13, is used to form a transistor, the surface being covered by vapour deposition or cathodic sputtering with a vitreous layer 5 of silicon dioxide, boron trioxide, or phosphorus pentoxide and oxides of copper or tungsten. The layer as formed is in its high resistivity state and is a few microns thick. Contacts are made to the layer over the desied regions of the body, and each junction forwardly biased by voltages at the contacts. When the voltage ...

METHOD FOR PASSIVATING MESA PN JUNCTION STRUCTURES

... 1300186 Semi-conductor devices MOTOROLA Inc 25 June 1971 [22 July 1970] 29961/71 Heading H1K In a method of passivating a mesa PN junction device, a PN junction is formed in a silicon body, a layer 20 of silicon nitride is deposited on the body, a masking layer 18 of silicon dioxide is deposited over this and the silicon nitride is etched away except over that portion of the body which will become the top of the mesa, the silicon dioxide mask is removed, the silicon body is then etched away using the silicon nitride as a mask to form the mesa, a silicon dioxide layer is grown over the sides of the mesa by a thermal method, the silicon nitride layer is removed, and a metal contact layer is formed in its place.

PROTECTIVE COATINGS FOR FIELD EFFECT TRANSISTORS

... 1457318 Semiconductor devices INTERNATIONAL BUSINESS MACHINES CORP 8 April 1974 [3 May 1973] 15433/74 Heading H1K Undesired effects caused by light incident on a field effect transistor are mitigated by the provision on its surface of a multi-layer dielectric mirror. As described the mirror consists of a plurality of layers of alternately high and low refractive index material with high index layers adjacent both the substrate and the ambient. Zinc and antimony sulphides, calcium and magnesium fluorides, silicon, titania and silicon nitride may be used in the mirror, the materials being chosen for compatibility and to have a refractive index ratio of # 1À3-1. In a single IGFET structure based on P-type silicon the mirror, comprising 29 layers alternately of zinc sulphide and cryolite (though smaller numbers of layers are almost as effective) may constitute the gate dielectric or if the device is a MOSFET may overlie the gate. In a display structure (Fig. 5) comprising an array of MOSFETs ...

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICES

METHODS OF MAKING SEMICONDUCTOR DEVICES

... 1366892 Semi-conductor devices WESTERN ELECTRIC CO Inc 25 Aug 1971 [26 Aug 1970] 39786/71 Heading H1K Openings are provided in an otherwise continuous dopant-containing layer 88, e.. of silicon oxide, on a semi-conductor body, another layer 89 is formed thereon and the dopant, e.g. B for a PSi body as shown, is diffused from the layer 88 into the body. In the arrangement shown this produces a graded P+ surface layer in the body. The openings in the layer 88 are used to define areas of the semi-conductor surface into which another dopant is introduced. In Fig. 11 this other dopant, which may be P, diffuses from the doped oxide layer 89 at the same time as the diffusion from the layer 88, thereby forming N+ regions 82, 83, the former region being annular and surrounding the latter. The layer 89 is then removed using an etchant which preferentially attacks it, and the openings in the layer 88 and further openings made therein are used to provide access for emitter, base and ...

SEMICONDUCTOR ARRANGENTS

... 1369930 Semi-conductor devices SIEMENS AG 23 June 1972 [22 Sept 1971] 29478/72 Heading H1K A semi-conductor device has a protective insulating layer comprising a first sub-layer 2 of silicon dioxide, and at least one further sublayer 12 of silicon nitride, beryllium oxide, or an oxide of a Group III element, a window 3 being present at the device surface in the first sublayer, the further sub-layer extending over the periphery of the window at 13 and into contact with the semi-conductor surface exposed at the window. An electrode 15 contacts the surface in the window, the window exposing a doped region 8 whose PN junction is covered by the first sub-layer. The device includes an auxiliary window 5, surrounding the first, and having a doped region 10 therebelow, the periphery of the first sub-layer again being protected by the further sub-layer. A plurality of devices are formed simultaneously, and separated by scribing and breaking at 7 beyond the auxiliary window. Diode construction is ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION

... 1,242,896. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 11 Sept., 1968 [26 Sept., 1967], No. 43132/68. Heading H1K. The source and drain regions 28, 29 of an IGFET are formed by selectively removing a central portion of a single initial region formed in a substrate 19 of the opposite conductivity type by diffusion or epitaxy, e.g. into an etched recess, the portion to be removed being defined by an aperture in a relatively thick dielectric layer 23, and subsequently providing a relatively thin gate insulation layer 27 over the channel region of the substrate 19 thus exposed. Source, drain and gate electrodes 34, 36, 37 are then provided, the last-mentioned of these being insulated from the source and drain regions 28, 29 by the relatively thick dielectric layer 23. The device threshold voltage may be adjusted by diffusing a dopant into the channel region prior to deposition of the gate insulation 27. The substrate 19 is preferably of Si, suitable source and drain dopants being B, P, As ...

FORMATION OF ELECTRICALLY INSULATING LAYERS IN SEMICONDUCTING MATERIALS

... 1334520 Semi-conductor devices UNITED KINGDOM ATOMIC ENERGY AUTHORITY 9 July 1971 [12 June 1970] 28706/70 Heading H1K An insulating layer 15 is formed in a semiconductor body 13, e.g. to provide component isolation in an integrated circuit, by providing the body 13 initially with a concentration of substitutional impurity atoms, bombarding the body 13 with ions to create a region of radiation damage within the body and to release a proportion of the impurity atoms from their substitutional sites, and heating the body 13 to cause the released impurity atoms to migrate to and precipitate in the radiation damaged region, there to form a layer 15 of insulating material. Additional impurity atoms may be released by irradiating with electrons of selected low energy simultaneously with or subsequently to the ion bombardment. For Si the impurity atoms may be C, the insulating layer 15 then being rich in SiC. Suitable ions are protons, helium, carbon or, less advantageously, oxygen. The invention ...

Semiconductor Device having Insulating Films and Method of Making Same.

... 1,188,950. Semi-conductor devices. HITACHI Ltd. 16 June, 1967, No. 51863/69. Divided out of 1,188,949. Heading H1K. Boron is diffused into an N-type Si wafer 1 through holes in an oxide layer 2 (Fig. 2a, not shown) and the holes subsequently covered with a thinner oxide film (8). Conventional photo-resist and etching techniques are used to expose the two diffused regions and a portion of the wafer lying between the regions and all the exposed portions are covered with very thin oxide films 14, 15, 16 (Figs. 2b, 2c and 2d, not shown). Again, by photo-resist and etching techniques the two diffused regions are exposed either by complete or partial removal of the very thin oxide films 14, 16 whilst leaving the portion 15 covered (Figs. 2e and 2f, not shown) and aluminium electrodes 18, 19, 20 deposited in the exposed portions and over the very thin oxide film 15 to give an IGFET. In an alternative embodiment (Fig. 2h, not shown), portions of the very thin oxide film 14, 16 remain in the final ...

The manufacture of semi-conductor devices

METHOD OF MAKING A SEMICONDUCTOR DEVICE

... 1353185 Semi-conductor devices LICENTIA PATENT-VERWALTUNGS GmbH 5 May 1971 [5 May 1970] 13241/71 Heading H1K A method of manufacturing a semi-conductor device, which includes forming openings in an insulating layer 2 on a semi-conductor body 1 using a photosensitive layer as an etching mask is characterized by the application of a metal layer 5 of aluminium, gold or titanium between the insulating and photosensitive layers. In a diode embodiment a silicon body 1 including a diffused region 4 has an insulating layer 2, e.g. of silicon dioxide, formed thereon followed by the metal layer 5. Following the photolithographic etching step which produces an opening to the body an electrode layer 8 is deposited over the layer 5 and the exposed body surface. The layer 8 may be of aluminium, gold, titanium, chromium or platinum. The layers 8 and 5 are then etched to the desired electrode configuration as shown. A further layer of a getter or passivation material may also be used between the insulating ...

A method of masking the surface of a substrate

A pattern of e.g. silicon oxide or nitride is formed on a substrate of e.g. silicon by first evaporating a coating of Ag, Au or Cu in discrete areas on the substrate, depositing the silicon oxide or nitride by decomposition from a vapour using a glow discharge over the whole surface, and then removing the evaporated layer and the corresponding part of the film by ultrasonic vibration in a liquid e.g. water or a weak acid, e.g. nitric.

SEMICONDUCTOR DEVICE

... 1,221,868. Semi-conductor device. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 20 May, 1968 [20 May, 1967], No. 23963/68. Heading HlK. A passivated semi-conductor device has a field relief electrode of semi-conductor material disposed on the insulating passivating layer and extending to within less than 5 Á from the window or windows therein. Such a device may be made by first pyrolytically depositing silica on a germanium wafer and then vapour depositing intrinsic germanium to a depth of 1 Á with the wafer held at 280-300‹ C. A diode junction is then completed by diffusing impurity through a window formed in the layers by standard photoresist and etching techniques. To form a transistor a second diffusion is effected through a window formed in a silicon nitride masking layer. In a modification in which the field relief electrode consists of silicon it is overlain by a further passivating layer of silica.

METHOD OF MAKING BARRIER LAYER DEVICES AND DEVICES SO MADE

... 1291450 Semi-conductor devices WESTERN ELECTRIC CO Inc 21 Nov 1969 [22 Nov 1968] 56973/69 Heading H1K An insulating guard ring 12 defining the periphery of a planar rectifying barrier in a semiconductor device is formed by bombardment with ions to a depth beyond that of the rectifying barrier so as to convert the bombarded semi-conductor material to insulating material. Suitable ions for use with Si, Ga or III-V compounds are oxygen, nitrogen, carbon or mixtures thereof. The barrier may be a metal/ semi-conductor contact (e.g. Al on Si, Pd on Ge or Au on GaAs) or a contact between Si and a silicide of a metal such as Ni, Ti, Zr, Hf or a Pt-group metal, where the silicide is produced by heating after depositing a layer of the appropriate metal. In the latter case a localized area of the silicide (52), Fig. 5 (not shown), is then covered by a masking layer (54) of metal such as Al, Ti, Zr, Pt-Ti-Au or Cr-Au, and the entire surface is subjected to bombardment, e.g. with oxygen ions, to form ...

METHOD OF ETCHING MULTILAYERED ARTICLES

... 1527106 Etching TELETYPE CORP 9 Oct 1975 [10 Oct 1974] 41356/75 Heading B6J A layer of SiO 2 is etched with buffered HF, e.g. HF + NH 4 F, the underlying aluminium layer being passivated by the HF. The passivated layer is then treated with a substantially HF-free solution of NH 4 F to prevent deterioration thereof. Etching of the SiO 2 may be through apertures in a photoresist mask.

FLAME RETARDING RESIN COMPOSITION AND FROM THIS IT MANUFACTURE SEMICONDUCTOR DEVICE

Procedure for manufacturing electrically isolated contact contacts consisting of aluminum

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE SEMICONDUCTOR BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

SOLVENT-MODIFIED RESIN COMPOSITIONS AND USE PROCEDURES FOR IT

HARDENABLE SILICONE COMPOSITION AND ELECTRONICS CONSTRUCTION UNIT

FLAME RETARDING RESIN COMPOSITION AND FROM THIS IT MANUFACTURE SEMICONDUCTOR DEVICE

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE HALF OF LEADER BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

HARDENABLE SILICONE COMPOSITION AND ELECTRONIC COMPONENTS

RESIN MATERIAL FOR INSERTING A LEADER FRAMEWORK AND THEREBY POURED ELEMENT

EPOXY RESIN MIXTURES FOR PREPREGS AND COMPOSITE MATERIALS

Field-effect transistor with insulating gate electrode

STRENGTHENED EPOXY/POLYANHYDRID COMPOSITION FOR UNTERFÜLLUNG WITHOUT FLOW

Curable epoxy-based compositions

METHOD OF PRODUCING A SEMICONDUCTOR ARRANGEMENT

COATING OF SEMICONDUCTOR CRYSTALS

LIQUID RESIN COMPOSITION AND SEMICONDUCTOR DEVICE USING THE SAME

Disclosed are a liquid resin composition which comprises a liquid epoxy resin (A), an amine hardener (B), core-shell rubber particles (C), and an inorganic filler (D), wherein the solid components account for 65 wt.% or more of the whole liquid resin composition, and a semiconductor device produced using the liquid resin composition.

METHOD OF FABRICATING SEMICONDUCTOR DEVICES

METHOD OF DEPOSITING THIN FILM UTILIZING A LIFT-OFF MASK

METHOD OF GROWING COMPOUND SEMICONDUCTOR FILMS ON AN AMORPHOUS SUBSTRATE

SEMICONDUCTOR DEVICE

Provided is a technology of suppressing semiconductor breakage due to a temperature change. For flip chip mounting a silicon chip on a build-up multilayer substrate employing a structure having a thinned core material, t he core material having a small linear expansion coefficient is used for the multilayer substrate, the linear expansion coefficient of an underfill material and a glass transition point are suitably designed, corresponding t o the thickness and the linear expansion coefficient of the core material. Thu s, a stress inside a semiconductor package generated by deformation or the like of the multilayer substrate due to the temperature change is modified, and breakage of the semiconductor package due to the temperature change is suppressed.

SEMICONDUCTOR DEVICE

The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.

UV-CURABLE INORGANIC-ORGANIC HYBRID RESIN AND METHOD FOR PREPARATION THEREOF

The present invention relates to a method for preparation of an ultraviolet (UV)-curable inorganic-organic hybrid resin containing about or less than 4% volatiles and less than 30% organic residues. The UV-curable inorganic-organic hybrid resin obtained according to this method can be UV-cured within a markedly very short time and enables, upon curing, the formation of a transparent shrink- and crack-free glass-like product having high optical quality, high thermal stability and good bonding properties. In view of these properties, this hybrid resin can be used in various applications such as electro-optic, microelectronic, stereolithography and biophotonic applications.

METHOD OF MAKING HETEROJUNCTION BIPOLAR TRANSISTOR

A method of manufacturing a heterojunction bipolar transistor is disclosed. On a base layer of a first semiconductor which contains at least one of gallium and arsenic as a constituent element, an emitter layer of a second semiconductor which contains at least one of gallium and arsenic as a constituent element and which has a band gap larger than that of the first semiconductor is formed. predetermined regions of the emitter layer and an upper portion of the base layer is removed to obtain a mesa structure. Then, a surface of a junction region of the base layer and the emitter layer which is exposed of the edge of the mesa structure by using sulfide. After the surface passivation, the surface of the junction region is covered with an insulating film.

Halbleiterkörper

Dispositif électrique comprenant un corps en matériau semi-conducteur.

Diode à basse impédance et procédé de fabrication de cette diode

Verfahren zur Herstellung eines Schutzüberzuges aus Glas

Circuit électronique semi-conducteur intégré et procédé de fabrication dudit circuit

Verfahren zum Herstellen eines Germaniumtransistors

Halbleiteranordnung

Halbleitervorrichtung

Verfahren zum Herstellen von elektrisch isolierten, aus Aluminium bestehenden Anschlüssen oder Verbindungen

Verfahren zur Herstellung eines Germanium-Halbleiterbauelements

Elektrische Schaltung mit einem elektrisch isolierenden Träger und Verfahren zu deren Herstellung

Verfahren zum Abscheiden einer Folge von teils aus Siliciumoxid, teils aus Siliciumnitrid bestehenden Schutzschichten an der Oberfläche eines Halbleiterkörpers

Verfahren zur Herstellung einer planaren doppeldiffundierten Halbleiteranordnung

Verfahren zum Herstellen einer Halbleiteranordnung

Feldeffekttransistor

Halbleiterschaltung und Verfahren zu deren Herstellung

Verfahren zum Abscheiden einer Dünnschicht

Procedimento per fabbricare semiconduttori discreti o circuiti integrati, e semiconduttore o circuito integrato ottenuto mediante detto procedimento

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

Verfahren zum gleichzeitigen Herstellen von mindestens zwei übereinstimmenden Halbleiterbauelementen aus einer einzigen Halbleiterscheibe

Halbleiteranordnung

Monolithische Halbleitervorrichtung und Verfahren zu deren Herstellung

Verfahren und Apparatur zur Erzeugung und Unterhaltung eines Glasplasmas

Halbleiterschaltelement

Verfahren zur Ausbildung einer dünnen Schicht

Halbleitervorrichtung mit mindestens einem Übergang zwischen Zonen verschiedenen Leitfähigkeitstyps

Speichermatrix

Verfahren zur Herstellung eines Halbleiterbauelements

Verfahren zum Herstellen einer Planardiode oder eines Planartransistors

Elektronenstrahl-Bildaufnahmeröhre

Verfahren zur Herstellung einer Halbleitervorrichtung und gemäss diesem Verfahren hergestellte Halbleitervorrichtung

Verfahren zum Herstellen eines Halbleitergleichrichters und nach diesem Verfahren hergestellter Halbleitergleichrichter

Metall-Halbleiterdiode

Optoelektronische Vorrichtung mit mindestens einem Feldeffekttransistor

Feldeffekttransistor mit isolierter Torelektrode

Halbleiterbauelement

Verfahren zum Herstellen einer auf einem elektrisch isolierenden Fremdsubstrat befindlichen integrierten Halbleiterschaltung

Halbleiteranordnung und Verfahren zur Herstellung der Halbleiteranordnung

Verfahren zum Herstellen von homogenen Schutzschichten aus Siliziumnitrid

Verfahren zum Herstellen einer Verbundhalbleiteranordnung

Verfahren zur Herstellung einer Halbleitervorrichtung

Verfahren zur Herstellung von Feldeffekttransistoren

Clathrate, curing agent, cure accelerator, epoxy resin composition, and epoxy resin composition for encapsulation of semiconductor

It is an object of the present invention to provide a clathrate that suppresses a curing reaction at low temperature to promote an improvement in storage stability (one-component stability), and can effectively cure a resin by heating treatment. A clathrate suitable for the clathrate is a clathrate containing (b1) at least one selected from the group consisting of an aliphatic polyvalent carboxylic acid, 5-nitroisophthalic acid, 5-tert-butylisophthalic acid, 5-hydroxyisophthalic acid, isophthalic acid, and benzophenone-4,4′-dicarboxylic acid; and (b2) at least one selected from the group consisting of an imidazole compound represented by the following formula (I), and 1,8-diazabicyclo[5.4.0]undecene-7, at a molar ratio of 1:1.

Resin-Encapsulated Semiconductor Device

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Semiconductor device with protective films and manufacturing method thereof

A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Authentication device, authentication method, and an information storage medium storing a program

There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Method for manufacturing electronic parts device and resin composition for electronic parts encapsulation

The present invention relates to a method for manufacturing an electronic parts device allowing for easy overmolding and underfilling without requiring a jig for preventing leakage of the melted resin composition, and a resin composition sheet for electronic parts encapsulation used therein.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Semiconductor package integrated with conformal shield and antenna

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Flexible underfill compositions for enhanced reliability

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Epoxy Resin Composition

The present invention provides an epoxy resin composition comprising epoxy resin, phenolic resin, a cure accelerator and an inorganic filler; said epoxy resin comprises: (1) 20-50% of Formula I; (2) 10-40% of Formula II; and (3) 0-30% of Formula III and/or 0-40% of Formula IV, wherein Formula III and Formula IV are not 0% simultaneously; and wherein, R 1 and R 2 are independently hydrogen or alkyl of C 1 -C 6 ; n is an integer from 0 to 50 in Formula I; the ratio of the number of phenolic hydroxyls in said phenolic resin to the number of epoxy groups in the epoxy resin mixture is 0.8-1.3; all said percentages are percentages relative to the total mass of the epoxy resin mixture.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Atomic layer deposition encapsulation for power amplifiers in rf circuits

Power amplifiers and methods of coating a protective film of alumina (Al 2 O 3 ) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device which is excellent in high-temperature high-humidity reliability without decreasing moldability and curability is provided. The method includes sealing a semiconductor element in resin using a semiconductor-sealing epoxy resin composition; and then performing a heating treatment. The semiconductor-sealing epoxy resin composition contains (A) an epoxy resin of formula (1): wherein X is a single bond, —CH 2 —, —S— or —O—; and R 1 to R 4 , which may be the same as or different, are each —H or —CH 3 , (B) a phenolic resin, (C) an amine-based curing accelerator, and (D) an inorganic filler. The heating treatment is performed under heat treatment conditions defined by a region in which a relationship t≧3.3×10 −5 exp(2871/T) is satisfied where t is heat treatment time in minutes and T is heat treatment temperature in ° C. and where 185≦T≦300.

Use of Ionomeric Silicone Thermoplastic Elastomers in Electronic Devices

This invention relates to the use of a thermoplastic elastomer comprising at least one silicone ionomer in the formation of electronic devices.

Wafer mold material and method for manufacturing semiconductor apparatus

The invention provides a wafer mold material for collectively subjecting a wafer having semiconductor devices on a surface thereof to resin molding, wherein the wafer mold material has a resin layer containing a filler and at least any one of an acrylic resin, a silicone resin having an epoxy group, an urethane resin, and a polyimide silicone resin, and the wafer mold material is formed into a film-like shape. There can be a wafer mold material that enables collective molding (wafer molding) with respect to a wafer having semiconductor devices formed thereon, has excellent transference performance with respect to a large-diameter thin-film wafer, can provide a flexible hardened material with low-stress properties, and can be preferably used as a mold material in a wafer level package with less warp of a formed (molded) wafer.

Acrylate composition

The invention provides a composition containing (A) one or more (meth)acrylate compounds selected from among a (meth)acryl-modified silicone fluid, a long-chain alkyl(meth)acrylate, and a polyalkylene glycol(meth)acrylate having a number average molecular weight of 400 or more; (B) a (meth)acrylate compound having an alicyclic hydrocarbon group which has six or more carbon atoms and which is bonded to the compound via an ester bond; (C) (meth)acrylic acid or a (meth)acrylate compound having a polar group; and (D) a radical polymerization initiator. The composition is suitably employed as a raw material for, for example, an encapsulating material or a lens, exhibits transparency and heat resistance comparable to conventional levels, and provides a cured product exhibiting excellent adhesion to a base member surrounding the cured product.

Packaged semiconductor chips with array

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Underfill for high density interconnect flip chips

Underfill materials include inorganic fill materials (e.g., functionalized CNT's, organo clay, ZnO) that are functionalized reactive with other organic constituents (e.g., organics with epoxy groups, amine groups, or PMDA). The underfill materials also beneficially include polyhedral oligomeric silsesquioxane and/or dendritic siloxane groups that are functionalized with a reactive group (e.g., glycidyl) that reacts with other components of an epoxy system of the underfill.

Composition for patternable adhesive film, patternable adhesive film, and method of manufacturing semiconductor package using the same

A composition for a patternable adhesive film, a patternable adhesive film having the same, and a method of manufacturing a semiconductor package using the patternable adhesive film are provided. The composition contains a binder resin, a radical-polymerizable acrylate monomer, a photo-radical initiator, and a thermal-radical initiator without an epoxy resin. The composition may have good patternability, adhesiveness, and low-temperature stability, and be rapidly cured at a low temperature.

Methods for vacuum assisted underfilling

Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

Solventless one liquid type cyanate ester-epoxy composite resin composition

The present invention is a solventless one liquid type cyanate ester-epoxy resin composition having high thermal resistance as well as excellent storage stability and curing properties, which contains (A) cyanate ester, (B) epoxy resin, (C) guanidine compounds and (D) at least one kind of phenol compounds selected from a group consisting of phenol compounds represented by the following general formulae. In the general formulae, 1 is an integer selected from 0 to 4, R 1 represents an unsubstituted or fluorine-substituted monovalent hydrocarbon group. General formula:

Manufacturing method of semiconductor device, semiconductor device and mobile communication device

A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Epoxy resin composition for encapsulating semiconductor, semiconductor device, and mold releasing agent

Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

Semiconductor devices and methods of manufacturing semiconductor devices

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Semiconductor device

Disclosed is a semiconductor device configured by encapsulating a semiconductor element, partially or entirely covered with a polyimide, using an epoxy resin composition for encapsulating semiconductor device which contains an epoxy resin (A), a phenol resin (B), a curing accelerator (C), an inorganic filler (D), and a silane coupling agent (E) represented by the formula (1): (in the formula (1), each of R 1 , R 2 and R 3 represents a C 1-4 hydrocarbon group, all of them may be the same or different from each other, and n represents an integer from 0 to 2), and/or a hydrolytic condensate thereof.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Bridging arrangement and method for manufacturing a bridging arrangement

A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

Surface treatment method for germanium based device

The present invention provides a surface treatment method for germanium based device. Through performing surface pretreatment to the germanium based device by using an aqueous solution of ammonium fluoride as a passivant, the interface state may be reduced, the formation of natural oxidation layer at the germanium surface may be inhibited, the regeneration of natural oxidation layer and the out-diffusion of the germanium based substrate material can be effectively inhibited, and the thermal stability of the metal germanide may also be increased significantly, so that the interface quality of the germanium based device is improved easily and effectively, which are advantageous to improve the performance of the germanium based transistor.

Circuit module and manufacturing method for the same

A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.

Polymide resin composition, adhesive agent and laminate each comprising same, and device

Provided are a polyimide resin composition containing a polyimide obtained by the condensation of: a diamine component containing an aromatic diamine (A) represented by the general formula (1-1) or the like, a silicone diamine (B) represented by the general formula (2) and an aliphatic diamine (C) represented by the general formula (3); and an acid anhydride component containing a specific aromatic tetracarboxylic dianhydride (D); and a laminate and a device using the polyimide resin composition.

Polymer Composition for Microelectronic Assembly

Embodiments in accordance with the present invention encompass polymer compositions that are useful in the assembly of microelectronic components onto a variety of substrate materials. Such polymer compositions providing for both holding the microelectronic components at desired positions on a substrate, providing fluxing for the solder bonding of such components to the substrate and remaining in place as an underfill for such components.

Epoxy resin composition for encapsulating semiconductor device and semiconductor device encapsulated with the same

An epoxy resin composition for encapsulating a semiconductor device includes a curing agent, a curing accelerator, inorganic fillers, and an epoxy resin, the epoxy resin including a first resin represented by Formula 1: wherein R1 and R2 are each independently hydrogen or a C1 to C4 linear or branched alkyl group, and n is a value from 1 to 9 on average.

Silicone composition for sealing light emitting element, and light emitting device

One embodiment is related to a silicone composition for sealing a light emitting element, the composition comprising: (A) a vinyl group-containing organopolysiloxane having a three-dimensional network structure; (B) an organohydrogenpolysiloxane which has at least two hydrogen atoms, each hydrogen atom being bonded to a silicon atom per molecule; and (C) a hydrosilylation catalyst.

Epoxy resin composition

A low temperature curable epoxy resin composition which comprises: an epoxy component that contains an epoxy compound having per molecule at least two epoxy groups and that is liquid at 25° C.; an aromatic amine based curing agent that contains an aromatic amine compound having per molecule at least two amino groups directly bonded to the aromatic ring and that is liquid at 25° C.; and Mg(II) acetylacetonate as a cure accelerator. The composition, which contains a novel cure accelerator using a metal complex, exhibits high stability at room temperature while lowering a cure temperature or shortening a cure time.

Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same

The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following components (A) to (D): (A) an epoxy resin; (B) a phenol resin; (C) an inorganic filler, and (D) a silicone compound containing an alkoxy group directly bonded to silicon atom in an amount of 10 to 45 wt % based on the entire silicone compound and having a specific gravity of 1.10 to 1.30.

Epoxy resin composition for semiconductor encapsulant and semiconductor device using the same

According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R 1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.

Silicone resin sheet, producing method thereof, encapsulating sheet, and light emitting diode device

A method for producing a silicone resin sheet includes the steps of forming a first coating layer by applying a first silicone resin composition which contains a first organopolysiloxane and a second organopolysiloxane; forming a precursor layer from the first coating layer by reacting the first organopolysiloxane with the second organopolysiloxane so as to have a conversion ratio of 5 to 40%; and forming a second layer on at least one surface in a thickness direction of the precursor layer by applying a second silicone resin composition which contains a third organopolysiloxane, a fourth organopolysiloxane, a hydrosilylation catalyst, and a curing retardant containing tetraalkylammonium hydroxide.

GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Provided is a glass composition for protecting a semiconductor junction which contains at least SiO, AlO, ZnO, CaO and 3 mol % to 10 mol % of BO, and substantially contains none of Pb, P, As, Sb, Li, Na and K. It is preferable that a content of SiOfalls within a range of 32 mol % to 48 mol %, a content of AlOfalls within a range of 9 mol % to 13 mol %, a content of ZnO falls within a range of 18 mol % to 28 mol %, a content of CaO falls within a range of 15 mol % to 23 mol %, and a content of BOfalls within a range of 3 mol % to 10 mol %. 1. A glass composition for protecting a semiconductor junction , wherein the glass composition contains at least SiO , AlO , ZnO , CaO and 3 mol % to 10 mol % of BO , and substantially contains none of Pb , P , As , Sb , Li , Na and K.2. A glass composition for protecting a semiconductor junction according to claim 1 , wherein{'sub': '2', 'a content of SiOfalls within a range of 32 mol % to 48 mol %,'}{'sub': 2', '3, 'a content of AlOfalls within a range of 9 mol % to 13 mol %,'}a content of ZnO falls within a range of 18 mol % to 28 mol %,a content of CaO falls within a range of 15 mol % to 23 mol %, and{'sub': 2', '3, 'a content of BOfalls within a range of 3 mol % to 10 mol %.'}3. A method of manufacturing a semiconductor device comprising:a first step of preparing a semiconductor element having a pn junction exposure part where a pn junction is exposed; anda second step of forming a glass layer such that the glass layer covers the pn junction exposure part in this order, wherein{'sub': 2', '2', '3', '2', '3, 'in the second step, the glass layer is formed using a glass composition for protecting a semiconductor junction which contains at least SiO, AlO, ZnO, CaO and 3 mol % to 10 mol % of BO, and substantially contains none of Pb, P, As, Sb, Li, Na and K.'}4. A method of manufacturing a semiconductor device according to claim 3 , whereinthe first step includes: a step of preparing a semiconductor base body having a pn junction ...

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

CURABLE RESIN COMPOSITION, CURABLE RESIN COMPOSITION TABLET, MOLDED BODY, SEMICONDUCTOR PACKAGE, SEMICONDUCTOR COMPONENT AND LIGHT EMITTING DIODE

The present invention aims to provide a curable resin composition which gives a cured product having a low linear expansion coefficient. The curable resin composition of the present invention contains, as essential components, (A) an organic compound having at least two carbon-carbon double bonds reactive with SiH groups per molecule, (B) a compound containing at least two SiH groups per molecule, (C) a hydrosilylation catalyst, (D) a silicone compound having at least one carbon-carbon double bond reactive with a SiH group per molecule, and (E) an inorganic filler. 1. A curable resin composition comprising , as essential components ,(A) an organic compound having at least two carbon-carbon double bonds reactive with SiH groups per molecule,(B) a compound containing at least two SiH groups per molecule,(C) a hydrosilylation catalyst,(D) a silicone compound having at least one carbon-carbon double bond reactive with a SiH group per molecule, and(E) an inorganic filler.2. The curable resin composition according to claim 1 ,wherein the component (D) is a linear polysiloxane containing a vinyl group at a terminal thereof.3. The curable resin composition according to claim 1 ,wherein the component (D) has a weight average molecular weight of at least 1,000 but not more than 1,000,000.4. The curable resin composition according to claim 1 ,wherein the component (E) is spherical silica.5. The curable resin composition according to claim 1 , further comprising(F) a white pigment.6. The curable resin composition according to claim 5 ,wherein the component (F) has an average particle size of 1.0 μm or less.7. The curable resin composition according to claim 5 ,wherein the component (F) is titanium oxide.8. The curable resin composition according to claim 7 ,wherein the component (F) is titanium oxide that is surface-treated with an organosiloxane.9. The curable resin composition according to claim 7 ,wherein the component (F) is titanium oxide that is surface-treated with an ...

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

LEAD-FREE GLASS FOR SEMICONDUCTOR ENCAPSULATION

The technical task of the present invention is to provide a lead-free glass for semiconductor encapsulation, which is easy to automate an appearance inspection, and furthermore, has excellent refinability and encapsulatability of semiconductor devices. In the lead-free glass for semiconductor encapsulation according to the present invention, a temperature at which the viscosity of glass is 10dPa·s is 670° C. or lower, and, as a glass composition, the content of CeOis from 0.01 to 6% by mass, and the content of SbOis 0.1% by mass or less. 1. A lead-free glass for semiconductor encapsulation , wherein a temperature at which the viscosity of glass is 10dPa·s is 670° C. or lower , and , as a glass composition , the content of CeOis from 0.01 to 6% by mass , and the content of SbOis 0.1% by mass or less.2. The lead-free glass for semiconductor encapsulation according to claim 1 , which consists of SiO—BO—RO (R is an alkali metal) based glass claim 1 , and comprises two or more of LiO claim 1 , NaO and KO as the RO.3. The lead-free glass for semiconductor encapsulation according to claim 1 , which comprises claim 1 , as a glass composition claim 1 , from 20 to 65% of SiO claim 1 , from 0 to 10% of AlO claim 1 , from 10 to 40% of BO claim 1 , from 0 to 10% of MgO claim 1 , from 0 to 10% of CaO claim 1 , from 0 to 10% of SrO claim 1 , from 0 to 10% of BaO claim 1 , from 0 to 35% of ZnO claim 1 , from 0.2 to 10% of LiO claim 1 , from 0.5 to 17% of NaO claim 1 , from 0 to 16% of KO claim 1 , from 0 to 10% of TiO claim 1 , from 0 to 5% of ZrO claim 1 , from 0 to 25% of BiOand from 0 to 10% of LaO claim 1 , in terms of % by mass.4. The lead-free glass for semiconductor encapsulation according to claim 1 , wherein the content of BaO is less than 1% by mass.5. An encapsulator for semiconductor encapsulation made of the glass according to . The present invention relates to a lead-free glass for semiconductor encapsulation, particularly a glass for encapsulating semiconductor ...

Typical metal containing polysiloxane composition, process for its production, and its uses

A material suitable for sealing an LED element or for a gas barrier layer for a resin component, and an LED device, an FPD device and a semiconductor device using it. A process for producing a polymer composition, which includes mixing and reacting as component (A), an unsaturated group-containing siloxane compound of the following formula (1): wherein the siloxane structure is a chain or cyclic structure, as component (B), a siloxane compound having a structure of the following formula (2) wherein hydrogen is directly bonded to silicon, wherein the siloxane structure is a chain or cyclic structure, as component (C), at least one member selected from the group consisting of organic metal compounds of Group 1, 2, 12, 13 and 14 metals of the periodic table, and as component (D), a metal catalyst of Group 8, 9 or 10 metal of the periodic table.

Bond pad structure and fabricating method thereof

A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.

Fixing material comprising silane compound polymer and photonic device sealed body

A fixing material includes a silane compound polymer as the main component, the silane compound polymer being produced by condensing a silane compound mixture that includes at least one silane compound (1) shown by the following formula (1): R 1 Si(OR 2 ) p (X 1 ) 3-p (wherein R 1 represents a group including an ester structure or a cyanoalkyl group, R 2 represents an alkyl group having 1 to 6 carbon atoms or the like, X 1 represents a halogen atom, and p is an integer from 0 to 3), and at least one silane compound (2) shown by the following formula (2): Si(OR 3 ) q (X 2 ) 4-q (wherein R 3 represents an alkyl group having 1 to 6 carbon atoms, X 2 represents a halogen atom, and q is an integer from 0 to 4). A sealed optical device includes an optical device that is sealed with a cured product of the fixing material. The fixing material produces a cured product that exhibits high hardness, excellent transparency and heat resistance, and rarely undergoes coloration even when subjected to high-energy light or heat for a long time.

Gan-on-si switch devices

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

WAFER BACKSIDE COATING PROCESS WITH PULSED UV LIGHT SOURCE

A process for coating a semiconductor wafer with a coating composition comprises curing the coating with a pulsed UV light, thereby preventing delamination during reflow operations. In a particular embodiment, the coating composition comprises both epoxy and acrylate resins. The epoxy resin can be cured thermally; the acrylate resin is cured by UV irradiation. 1. A process for coating a semiconductor wafer with a coating composition comprising:(A) providing a coating composition(B) disposing the coating composition onto the semiconductor wafer; and(C) B-stage curing the coating composition by exposing the composition to pulsed UV light in an amount sufficient to cure the coating composition.2. The process according to in which the coating composition is exposed to a total of 0.1 to 10 J/cm.3. The process according to in which the pulsed UV light source is used at a distance of 12 to 38 cm from wafer to bulb for 15 to 300 seconds.4. The process according to in which the semiconductor wafer is 100 μm or less in thickness.5. The process of in which the coating composition comprises a resin that can be cured thermally and a resin that can be cured by free radical polymerization.6. The process of in which the resin that can be cured thermally is an epoxy resin and the resin that can be cured by free radical polymerization is an acrylate resin.8. A semiconductor wafer coated using the process of9. A semiconductor wafer coated using the process of in which the coating composition comprises (i) a solid epoxy resin with a melting point between 80° and 130° C. claim 1 , and (ii) an acrylate resin having a viscosity less than 50 mPas and a boiling point greater than 150° C. This invention relates to a process for coating the inactive side (backside) of a semi-conductor wafer in which the coating is cured using a pulsed UV light source.Recent advancements in semiconductor packaging have led to the downsizing of the package through the use of thinner dies in a stacked ...

RESIN COMPOSITION

A resin composition for obtaining a cured resin material exhibiting improved heat resistance and a higher glass transition temperature is disclosed. The resin composition contains a resin selected from a) a thermosetting resin and a curing agent, or b) a thermoplastic resin, and an inorganic filler with an average particle diameter of 1000 nm or less. 1. A resin composition comprising: a) a thermosetting resin and a curing agent, and', 'b) a thermoplastic resin; and, '(i) a resin selected from'}(ii) an inorganic filler with an average particle diameter of 1000 nm or less.2. The resin composition according to claim 1 , wherein a mixing ratio of the inorganic filler in the resin composition is 0.1 to 10 wt % based on a total mass of the resin composition.3. The resin composition according to claim 1 , wherein the inorganic filler is at least one selected from the group consisting of AlO claim 1 , SiO claim 1 , BN claim 1 , AlN and SiN claim 1 , and has an average particle diameter of 1 to 1000 nm.4. The resin composition according to claim 1 , wherein the resin is a thermosetting resin and a curing agent.5. The resin composition according to claim 4 , wherein the thermosetting resin is an epoxy resin and the curing agent is an acid anhydride curing agent or a curing agent containing a molecule having 1 or more of functional groups —NH claim 4 , —NHand —NH in a molecular structure thereof claim 4 , and the inorganic filler has an average particle diameter of 100 nm or less.6. The resin composition according to claim 5 , wherein the epoxy resin is a trifunctional epoxy resin.7. A cured nanocomposite resin material obtained by thermosetting the resin composition according to .8. The cured nanocomposite resin material according to claim 7 , wherein an average inter-filler distance is 1 to 200 nm.9. The resin composition according to claim 1 , wherein the resin is a thermoplastic resin.10. The resin according to claim 9 , wherein the thermoplastic resin is a nylon claim 9 ...

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

PHOTOSENSITIVE ADHESIVE COMPOSITION, PHOTOSENSITIVE ADHESIVE FILM, AND SEMICONDUCTOR DEVICE USING EACH

Provided is a photosensitive adhesive composition comprising (A) an alkali-soluble polyimide having particular structural unit(s) and having a particular structure at at least one end of the main chain, (B) a glycidylamine type epoxy compound of a particular structure, (C) a photopolymerizable compound, and (D) a photoinitiator, wherein (A) the alkali-soluble polyimide has a glass transition temperature of 160° C. or higher. The photosensitive adhesive composition has the ability to form patterns with an alkaline developer, excellent thermocompressibility at a low temperature to an irregular substrate after exposure, and a high adhesive strength even at a high temperature. 2. The photosensitive adhesive composition according to claim 1 , wherein Rin Formula (6) is glycidyl group.3. The photosensitive adhesive composition according to claim 1 , wherein the alkali-soluble group contained in (A) the alkali-soluble polyimide is phenolic hydroxyl group.4. The photosensitive adhesive composition according to claim 1 , further comprising (E) a liquid epoxy compound that has aromatic group(s) and does not have any glycidyl amino group.6. The photosensitive adhesive film according to claim 5 , wherein Rin Formula (6) is glycidyl group.7. The photosensitive adhesive film according to claim 5 , wherein the alkali-soluble group contained in (A) the alkali-soluble polyimide is phenolic hydroxyl group.8. The photosensitive adhesive film according to claim 5 , further comprising (E) a liquid epoxy compound that has aromatic group and does not have any glycidyl amino group.9. A cured product of the photosensitive adhesive composition according to or of the photosensitive adhesive film according to .10. A semiconductor device having the cured product of the photosensitive adhesive composition according to or of the photosensitive adhesive film according to .11. A semiconductor device having between circuit components the cured product of the photosensitive adhesive composition ...

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Epoxy resin composition

The present invention provides an epoxy resin composition comprising epoxy resin, phenolic resin, a cure accelerator and an inorganic filler; said epoxy resin comprises: (1) 20-50% of Formula I; (2) 10-40% of Formula II; and (3) 0-30% of Formula III and/or 0-40% of Formula IV, wherein Formula III and Formula IV are not 0% simultaneously; and wherein, R 1 and R 2 are independently hydrogen or alkyl of C 1 -C 6 ; n is an integer from 0 to 50 in Formula I; the ratio of the number of phenolic hydroxyls in said phenolic resin to the number of epoxy groups in the epoxy resin mixture is 0.8-1.3; all said percentages are percentages relative to the total mass of the epoxy resin mixture. The present invention provides a green, environmentally friendly epoxy resin composition with high reliability and low warpage properties that can satisfy the requirement of lead-free high temperature reflux process.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

EPOXY RESIN COMPOSITION AND SEMICONDUCTOR DEVICE

An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): 135-. (canceled)38. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 36 ,wherein said butadiene-acrylonitrile copolymer (C-2) is contained in the amount of 0.05 wt % to 0.5 wt % both inclusive in the total epoxy resin composition.40. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 36 , further comprising a curing accelerator (E).4140. A semiconductor device wherein a semiconductor chip is encapsulated with the epoxy resin composition for encapsulating a semiconductor chip as claimed in any one of -.4240. The epoxy resin composition for encapsulating a semiconductor chip as claimed in any one of - used for encapsulating an area mounting type semiconductor device claims 36 ,wherein a semiconductor chip is mounted on one side of the substrate and substantially only the side of the substrate mounting the semiconductor chip is encapsulated.43. An area mounting type semiconductor device claim 42 , wherein a semiconductor chip is encapsulated with the area mounting type epoxy resin composition for encapsulating a semiconductor chip as claimed in . This application is a continuation of U.S. patent application Ser. No. 11/289,265, which is based on Japanese patent application Nos. 2004-347743, 2004-368714, 2005-002381, 2005-039050 and 2005-099390, the contents of which are incorporated hereinto by reference.1. Technical FieldThis invention relates to an epoxy resin composition for encapsulating a semiconductor chip and a semiconductor device. In particular, this invention is suitably used in an area mounting type semiconductor device where a semiconductor chip is mounted on one side of a printed-wiring board or metal lead frame and substantially only the mounted side is encapsulated with a resin.2. Related ...

Functional particle, functional particle group, filler, resin composition for electronic component, electronic component and semiconductor device

A functional particle ( 100 ) contains an inorganic particle ( 101 ), a first layer ( 103 ) coating the inorganic particle ( 101 ), and a second layer ( 105 ) coating the first layer ( 103 ). Any one or two component(s) of a resin, a curing agent and a curing accelerator is (are) contained in the first layer ( 103 ), and the others are (is) contained in the second layer ( 105 ).

EPOXY RESIN COMPOSITION AND SEMICONDUCTOR DEVICE

An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): 135-. (canceled)38. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 37 , wherein the number average molecular weight of said epoxidized polybutadiene compound (C-1) is 500 to 4000 both inclusive.39. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 37 , further comprising a curing accelerator (E).4039. A semiconductor device wherein a semiconductor chip is encapsulated with the epoxy resin composition for encapsulating a semiconductor chip as claimed in any one of -.4139. The epoxy resin composition for encapsulating a semiconductor chip as claimed in - used for encapsulating an area mounting type semiconductor device claims 37 ,wherein a semiconductor chip is mounted on one side of the substrate and substantially only the side of the substrate mounting the semiconductor chip is encapsulated.42. An area mounting type semiconductor device claim 41 , wherein a semiconductor chip is encapsulated with the area mounting type epoxy resin composition for encapsulating a semiconductor chip as claimed in .44. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 43 , wherein said epoxidized polybutadiene compound (C-1) has the number average molecular weight of 500 to 4000 both inclusive.45. The epoxy resin composition for encapsulating a semiconductor chip as claimed in claim 43 , further comprising a curing accelerator (E).4645. A semiconductor device wherein a semiconductor chip is encapsulated with the epoxy resin composition for encapsulating a semiconductor chip as claimed in any one of -.4745. The epoxy resin composition for encapsulating a semiconductor chip as claimed in any one of - used for encapsulating an area mounting type semiconductor device claims 43 ,wherein a ...

Positive Photosensitive Resin Composition, Photosensitive Resin Film Prepared by Using the Same, and Semiconductor Device Including the Photosensitive Resin Film

Disclosed are a positive photosensitive resin composition that includes (A) a polybenzoxazole precursor including a first polybenzoxazole precursor including a repeating unit represented by the following Chemical Formula 1 and a repeating unit represented by the following Chemical Formula 2, and having a thermally polymerizable functional group at at least one of the terminal end; (B) a dissolution controlling agent including a novolac resin including a repeating unit represented by the following Chemical Formula 4; (C) a photosensitive diazoquinone compound; (D) a silane compound; (E) an acid generator; and (F) a solvent, a photosensitive resin film prepared using the same, and a semiconductor device including the photosensitive resin film.

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture. 1. A semiconductor device , comprising:a semiconductor die;an encapsulant deposited over a first surface of the semiconductor die and around a peripheral region of the semiconductor die;a first insulating layer formed over the encapsulant and a second surface of the semiconductor die opposite the first surface of the semiconductor die with multiple dwell curing cycles to enhance adhesion to the semiconductor die and encapsulant;a first conductive layer formed over the first insulating layer; anda second insulating layer formed over the first insulating layer and first conductive layer with multiple dwell curing cycles to enhance adhesion to the first insulating layer and first conductive layer.2. The semiconductor device of claim 1 , wherein the multiple dwell curing cycles include a first dwell step with a first temperature for a first time period claim 1 , second dwell step with a second temperature for a second time period claim 1 , and third dwell step with a third temperature for a third time period.3. The semiconductor device of claim ...

VOID FREE INTERLAYER DIELECTRIC

A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids. 120-. (canceled)21. A memory device comprising:a plurality of memory cells formed on a substrate of the memory device; [ 'the dielectric layer, deposited using the atomic layer deposition process,', 'the dielectric layer being deposited using an atomic layer deposition process,'}, 'the dielectric layer, deposited using the atomic layer deposition process,', 'filling spaces between adjacent memory cells of the plurality of memory cells, and'}, 'having a substantially uniform thickness that prevents re-entrant angles; and, 'a dielectric layer deposited over a control gate of each memory cell, of the plurality of memory cells, and the substrate,'} 'voids, in the interlayer dielectric, being eliminated based on the interlayer dielectric being deposited to fill the spaces between the adjacent memory cells.', 'the interlayer dielectric being deposited to fill, based on the substantially uniform thickness that prevents the re-entrant angles, the spaces between the adjacent memory cells,'}, 'an interlayer dielectric deposited over the dielectric layer,'}22. The device of claim 21 , where the dielectric layer comprises a silicon nitride.23. The device of claim 21 , where the dielectric layer comprises silicon dioxide.24. The device of claim 21 , where the interlayer dielectric is deposited to a thickness ranging from about 2 claim 21 ,000 Å to about 11 claim 21 ,000 Å.25. The device of claim 21 , where the dielectric layer acts as a liner for the interlayer dielectric.26. The device of claim 21 , where the ...

Liquid resin composition and semiconductor device

According to the invention, a liquid resin composition which has favorable wet spreadability after mounting of a chip and exhibits excellent solder cracking resistance even in a high-temperature solder reflow process at about 260° C., i.e., even when being used in lead-free solder, and a semiconductor package using the liquid resin composition are provided. In the liquid resin composition of the invention, an acrylic copolymer having a radical polymerizable functional group contains alkyl(meth)acrylate as a constituent monomer having a linear or branched alkyl group having 6 to 9 carbon atoms in an amount of 10 wt % to 40 wt % of the entire constituent monomers.

Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die

A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. 1. A semiconductor device , comprising:a plurality of semiconductor die;a first insulating layer formed over the semiconductor die;an encapsulant deposited around the semiconductor die;a second insulating layer formed over the encapsulant and semiconductor die;a conductive layer formed over the second insulating layer; anda third insulating layer formed over the second insulating layer and conductive layer.2. The semiconductor device of claim 1 , further including a channel in the second insulating layer around the semiconductor die.3. The semiconductor device of claim 1 , further including a net pattern in the second insulating layer around the semiconductor die.4. The semiconductor device of claim 1 , wherein the second insulating layer covers the encapsulant around the semiconductor die.5. The semiconductor device of claim 1 , further including an interconnect structure formed over the third insulating layer and electrically connected to the conductive layer.6. The semiconductor device of claim 1 , wherein the plurality of semiconductor die is singulated through the ...

PHENYL GROUP-CONTAINING ORGANIC/INORGANIC HYBRID PREPOLYMER, HEAT RESISTANT ORGANIC/INORGANIC HYBRID MATERIAL, AND ELEMENT ENCAPSULATION STRUCTURE

The object of the present invention is to provide an organic-inorganic hybrid material having heat resistance, and said object of the present invention can be attained by providing an organic-inorganic hybrid prepolymer containing a phenyl group which is prepared by the polycondensation reaction accompanying dehydration between a polydimethylsiloxane and a metal and/or semimetal alkoxide, wherein (a) phenyl group(s) is (are) partially or wholly introduced into said polydimethylsiloxane and/or said metal and/or semimetal alkoxide. 1. An organic-inorganic hybrid prepolymer containing a phenyl group which is prepared by the condensation reaction between a polydimethyl-siloxane and a metal and/or semimetal alkoxide , wherein said phenyl group(s) is (are) partially or wholly introduced into said metal and/or semimetal alkoxide.2. An organic-inorganic hybrid prepolymer containing a phenyl group in accordance with claim 1 , wherein a metal and/or semimetal alkoxide oligomer is used as said metal and/or semimetal alkoxide.3. (canceled)6. (canceled)7. A heat-resistant organic-inorganic hybrid material comprising a gelatinized material which is produced by heating and gelatinizing said organic-inorganic hybrid prepolymer containing a phenyl group in accordance with .8. An heat resistant organic-inorganic hybrid material in accordance with claim 7 , wherein said heat resistant organic-inorganic material has a hardness of 80 or less according to its measurement using a Shore E hardness meter claim 7 , after being kept in an environment at 250□C for 1000 hours.9. A sealing structure of an element characterized by sealing a heat-generating element using said heat resistant organic-inorganic hybrid material in accordance with .10. A sealing structure of an element in accordance with claim 9 , wherein SiC and/or GaN is (are) installed as the semiconductor(s) in said heat-generating element.14. A heat-resistant organic-inorganic hybrid material comprising a gelatinized material ...

ANISOTROPIC CONDUCTIVE FILM AND SEMICONDUCTOR DEVICE BONDED BY THE SAME

A semiconductor device bonded by an anisotropic conductive film and an anisotropic conductive film composition, the anisotropic conductive film including a reactive monomer having an epoxy equivalent weight of about 120 to about 180 g/eq; a hydrogenated epoxy resin; and a sulfonium cation curing catalyst. 1. A semiconductor device bonded by an anisotropic conductive film , the anisotropic conductive film comprising:a reactive monomer having an epoxy equivalent weight of about 120 to about 180 g/eq;a hydrogenated epoxy resin; anda sulfonium cation curing catalyst.2. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film includes:about 1 to about 20 parts by weight of the reactive monomer having an epoxy equivalent weight of about 120 to about 180 g/eq;about 5 to about 50 parts by weight of the hydrogenated epoxy resin; andabout 0.1 to about 10 parts by weight of the sulfonium cation curing catalyst, all parts by weight being based on 100 parts by weight of the anisotropic conductive film in terms of solid content.3. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film further includes a binder resin and conductive particles.4. The semiconductor device as claimed in claim 3 , wherein the binder resin includes at least one selected from the group of a polyimide resin claim 3 , a polyamide resin claim 3 , a phenoxy resin claim 3 , an epoxy resin claim 3 , a polymethacrylate resin claim 3 , a polyacrylate resin claim 3 , a polyurethane resin claim 3 , an acrylate modified urethane resin claim 3 , a polyester resin claim 3 , a polyester urethane resin claim 3 , a polyvinyl butyral resin claim 3 , a styrene-butylene-styrene resin and epoxy modifications thereof claim 3 , a styrene-ethylene-butylene-styrene resin and modifications thereof claim 3 , and acrylonitrile butadiene rubber and hydrogenated compounds thereof.5. The semiconductor device as claimed in claim 3 , wherein the anisotropic conductive ...

RESIN COMPOSITION AND SEMICONDUCTOR DEVICE PRODUCED USING RESIN COMPOSITION

A resin composition of the present invention includes a maleimide derivative (A) represented by a general formula (1) and a bis-maleimide compound (B) represented by a general formula (2). In the general formula (1), R1 represents a straight chain or branched alkylene group having 1 or more carbon atoms, R2 represents a straight chain or branched alkyl group having 5 or more carbon atoms, and the sum of carbon atoms of R1 and R2 is 10 or less. In the general formula (2), X1 represents —O—, —COO—, or -—OCOO—R3, represents a straight chain or branched alkylene group having 1 to 5 carbon atoms, R4 represents a straight chain or branched alkylene group having 3 to 6 carbon atoms, and m is an integer of 1 or more and 50 or less. 2. The resin composition according to claim 1 , further comprising an allyl ester group-containing compound (C).3. The resin composition according to claim 2 , wherein the allyl ester group-containing compound (C) has an aliphatic ring.5. The resin composition according to claim 1 , further comprising a filler.6. A semiconductor device which has been produced using the resin composition according to . The present invention relates to a resin composition and a semiconductor device produced using the same.This application claims priority on Japanese Patent Application No. 2010-199889, filed Sep. 7, 2010, the content of which is incorporated herein by reference.In recent years, higher integration and surface mounting of electronic devices are employed from year to year in market trends toward making electronic equipment smaller, lighter, and highly functioning. For example, making semiconductor devices higher in pin count and thinner is approaching a limit in conventional surface-mounting semiconductor devices, represented by Quad Flat Packages (QFPs) and Small Outline Packages (SOPs), while in order to address need for making them further higher in pin count and thinner, area mounting semiconductor devices such as Lead Frame-Chip Scale Packages (LF ...

TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. 1. A process comprising:forming at least one pillar over a semiconductor wafer;forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the at least one pillar; andapplying a solder layer to the at least one pillar.2. The process as recited in claim 1 , wherein forming at least one pillar further comprises:applying a first photoresist layer over the semiconductor wafer;patterning and at least partially etching the first photoresist layer to form a first etched area;depositing conductive material in the first etched area;applying a second photoresist layer over the first photoresist layer;patterning and at least partially etching the second photoresist layer to form a second etched area, the second etched area formed over the first etched area;depositing conductive material in the second etched area to form the at least one pillar; andat least substantially removing the first photoresist layer and the second photoresist layer.3. The process as recited in claim 1 , wherein forming an encapsulation layer further comprises depositing an epoxy material over the semiconductor wafer claim 1 , the encapsulation layer at least partially encapsulating the at least one pillar.4. The process as recited in claim 1 , wherein the at least one pillar comprises a copper pillar.5. The process as recited in claim 1 , wherein an aspect ratio of the at least one pillar ranges from at least approximately ...

Thermally stable compositions containing resin-linear organosiloxane block copolymers

Solid compositions of organosiloxane block copolymers are disclosed having a tensile strength greater than 1.0 MPa and a % elongation at break greater than 40%. The organosiloxane block copolymers comprise: 40 to 90 mole percent disiloxy units of the formula [R 1 2 SiO 2/2 ] 10 to 60 mole percent trisiloxy units of the formula [R 2 SiO 3/2 ] 0.5 to 35 mole percent silanol groups [≡SiOH] where R 1 is independently a C 1 to C 30 hydrocarbyl, R 2 is independently a C 1 to C 20 hydrocarbyl, wherein; the disiloxy units [R 1 2 SiO 2/2 ] are arranged in linear blocks having an average of from 10 to 400 disiloxy units [R 1 2 SiO 2/2 ] per linear block, the trisiloxy units [R 2 SiO 3/2 ] are arranged in non-linear blocks having a molecular weight of at least 500 g/mol, and at least 30% of the non-linear blocks are crosslinked with each other, each linear block is linked to at least one non-linear block, and the organosiloxane block copolymer has a molecular weight (M w ) of at least 20,000 g/mole.

Photosensitive Novolac Resin, Positive Photosensitive Resin Composition Including Same, Photosensitive Resin Film Prepared by Using the Same, and Semiconductor Device Including the Photosensitive Resin Film

Disclosed is a photosensitive novolac resin including a structural unit represented by the following Chemical Formula 1 and structural unit represented by the following Chemical Formula 2, wherein R 11 , R 12 , R 13 , and R 14 in Chemical Formulae 1 and 2 are the same as defined in the detailed description, a positive photosensitive resin composition including the same, a photosensitive resin film fabricated using the same, and a semiconductor device including the photosensitive resin composition.

THERMOSETTING RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND ENCAPSULATED SEMICONDUCTOR DEVICE

A thermosetting resin composition for semiconductor encapsulation contains a both end allyl isocyanurate ring-terminated organopolysiloxane polymer as a sole base polymer and an isocyanurate ring-containing organohydrogenpolysiloxane polymer as a sole curing agent or crosslinker. When a semiconductor element array having semiconductor elements mounted on a substrate with an adhesive is encapsulated with the thermosetting resin composition, warp-free semiconductor devices having improved heat resistance and moisture resistance are obtainable. 2. The composition of wherein the spherical inorganic filler (D) is spherical silica.3. The composition of wherein the spherical inorganic filler (D) has been surface treated with a silane coupling agent.4. The composition of wherein the silane coupling agent is at least one member selected from the group consisting of vinytrimethoxysilane claim 3 , vinyltriethoxysilane claim 3 , 2-(3 claim 3 ,4-epoxycyclohexyl)ethyltrimethoxysilane claim 3 , 3-glycidoxypropylmethyldimethoxysilane claim 3 , 3-glycidoxypropyltrimethoxysilane claim 3 , 3-glycidoxypropylmethyldiethoxysilane claim 3 , 3-glycidoxypropyltriethoxysilane claim 3 , p-styryltrimethoxysilane claim 3 , 3-methacryloxypropylmethyldimethoxysilane claim 3 , 3-methacryloxypropyltrimethoxysilane claim 3 , 3-methacryloxypropylmethyldiethoxysilane claim 3 , 3-methacryloxypropyltriethoxysilane claim 3 , 3-acryloxypropyltriethoxysilane claim 3 , and 3-ureidopropyltriethoxysilane.5. A resin-encapsulated semiconductor device fabricated by coating the thermosetting resin composition of to one surface of a silicon wafer having at least one semiconductor element formed therein in entirety under pressure or under reduced pressure in a vacuum atmosphere claim 1 , heat curing the composition to encapsulate the wafer with a cured resin layer claim 1 , polishing the cured resin layer claim 1 , and dicing the wafer into singulated devices. This non-provisional application claims priority under ...

SILICONE RESIN

A silicone resin is provided. The silicone resin may be effectively used to encapsulate a semiconductor element, for example, a light-emitting element of a light-emitting diode. 1. A silicone resin that is represented by an average composition formula of Formula 1 and comprises a siloxane unit of Formula 2 and a siloxane unit of Formula 3 , wherein a molar ratio of aryl groups bound to the silicon atom with respect to the total silicon atoms is in a range of 0.7 to 1.3:{'br': None, 'sub': 3', '1/2', 'a', '2', '2/2', 'b', '3/2', 'c', '4/2', 'd, '(RSiO)(RSiO)(RSiO)(SiO)\u2003\u2003[Formula 1]'}{'br': None, 'sup': '2', 'sub': '2/2', 'R1RSiO\u2003\u2003[Formula 2]'}{'br': None, 'sup': '3', 'sub': '3/2', 'RSiO\u2003\u2003[Formula 3]'}{'sub': 2', '3, 'sup': 1', '2', '3', '1', '2, 'wherein R, Rand Rare substituents directly bound to a silicon atom, and each independently represents hydrogen, an alkoxy group having 1 to 12 carbon atom(s), a hydroxy group, an epoxy group, a (meth)acryloyl group, an isocyanate group, an alkyl having 1 to 12 carbon atom(s), an alkenyl group having 2 to 12 carbon atoms, an aryl group having 6 to 18 carbon atoms or arylalkyl group having 6 to 19 carbon atoms Rand Reach independently represent an alkyl group having 1 to 12 carbon atom(s) and an aryl group having 6 to 18 carbon atoms, Rrepresents an aryl group having 6 to 18 carbon atoms, a is in a range of 0≦a≦0.5, b is in a range of 0 Подробнее

Semiconductor device and method for manufacturing the same

A method is disclosed for manufacturing a semiconductor device. The method includes providing a substrate and forming a well region in the substrate by an ion implantation. The method also includes forming, by rapid thermal oxidation and on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation. Further, the method includes removing the oxide layer and forming a gate oxide layer on the repaired substrate having the well region. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate;forming a well region in the substrate by an ion implantation;forming, by rapid thermal oxidation, on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation;removing the oxide layer; andforming a gate oxide layer on the repaired substrate having the well region.2. The method according to claim 1 , wherein the oxide layer for repairing the substrate has a thickness of approximately 100 Å.3. The method according to claim 1 , wherein the well region formed in the substrate is a P-well.4. The method according to claim 1 , wherein the well region formed in the substrate is a P-well doped with indium ions.5. The method according to claim 1 , further including:before forming the well region in the substrate, forming a blocking oxide layer on the substrate; andafter forming a well region in the substrate, removing the blocking oxide layer.6. The method according to claim 1 , wherein forming the well region in the substrate includes:forming a photoresist layer with a well region pattern on the substrate;forming the well region in the substrate using the photoresist layer with the well region pattern as a mask; andremoving the photoresist layer with the well region pattern.7. The method according to claim 1 , wherein the oxide layer for repairing the substrate is silicon oxide.8. A semiconductor device claim 1 , comprising:a substrate;a well region in ...

RESIN COMPACT, METHOD FOR PRODUCING RESIN COMPACT, RESIN COMPOSITION, METHOD FOR PRODUCING RESIN COMPOSITION AND ELECTRONIC COMPONENT DEVICE

The present invention is related to a method for producing a resin compact containing an epoxy resin, a curing agent, a curing accelerator and an inorganic filler. The method includes a kneading and crushing process for preparing a first powder material obtained by mixing, heat-melting, kneading and crushing a first component containing the epoxy resin and the curing agent and the inorganic filler, but not containing the curing accelerator; a pulverizing process for preparing a second powder material obtained by pulverizing a second component containing the curing accelerator; a mixing process for preparing a resin composition by dispersing and mixing the first powder material and the second powder material; and a molding process for obtaining the resin compact by compression-molding the resin composition. This makes it possible to obtain a resin compact (particularly, a resin compact for encapsulation) having superior long term storage stability at room temperature, good curable property and fluidity. 1. A method for producing a resin compact containing an epoxy resin , a curing agent , a curing accelerator and an inorganic filler , the method comprising:a kneading and crushing process for preparing a first powder material obtained by mixing, heat-melting, kneading and crushing a first component containing the epoxy resin and the curing agent and the inorganic filler, but not containing the curing accelerator;a pulverizing process for preparing a second powder material obtained by pulverizing a second component containing the curing accelerator;a mixing process for preparing a resin composition by dispersing and mixing the first powder material and the second powder material; anda molding process for obtaining the resin compact by compression-molding the resin composition.2. The method as claimed in claim 1 , wherein temperatures of the first powder material and the second powder material are lower than melting temperatures or softening temperatures of the epoxy ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer. 1. A semiconductor package comprising:a first semiconductor element;a second semiconductor element opposingly spaced apart from the first semiconductor element;a connection structure disposed between the semiconductor elements to electrically connect the first and second semiconductor elements to each other; anda protective structure disposed to protect the connection structures and bond the first and second semiconductor elements to each other,wherein the protective structure comprises:a first material layer disposed to fully cover the connection structures; anda second material layer disposed to surround the first material layer.2. The semiconductor package as set forth in claim 1 , wherein the connection structures are collectively disposed on one region of one surface of the second semiconductor element claim 1 ,3. The semiconductor package as set forth in claim 2 , wherein the first material layer has the substantially same or larger area as the one region of the second semiconductor element.4. The semiconductor package as set forth in claim 3 , wherein the second material layer covers a region of the one surface of the second semiconductor element where the first material layer is not disposed.5. The semiconductor package as set forth in claim 1 , wherein the first material layer fully fills a space between adjacent connection structures claim 1 , when viewed cross-sectionally claim 1 , extends to the outside of the adjacent connection structures claim 1 , and has a sloped mating surface with the second material layer.6. The semiconductor package as set forth in claim 1 , wherein the first material layer includes an adhesive film.7. The semiconductor package as set forth in claim 1 , wherein ...

Liquid epoxy resin composition and semiconductor device

Disclosed is a liquid epoxy resin composition containing: (A) a liquid epoxy resin comprising at least one liquid epoxy resin represented by the following general formula (1) or (2): (B) a phenolic curing agent, (C) an accelerator in an amount of 0.01 to 10 parts by weight based on 100 parts by weight of component (A), and (D) an inorganic filler in an amount of 20 to 900 parts by weight based on 100 parts by weight of component (A).

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

PHOTOSENSITIVE RESIN COMPOSITION, PHOTOSENSITIVE RESIN COMPOSITION FILM, AND SEMICONDUCTOR DEVICE USING THE PHOTOSENSITIVE RESIN COMPOSITION OR PHOTOSENSITIVE RESIN COMPOSITION FILM

A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a). 2. The photosensitive resin composition according to claim 1 , wherein the compound (b) is a compound having two or more epoxy groups.3. The photosensitive resin composition according to or claim 1 , wherein the imidization ratio of the polyimide (a) is not less than 90%.4. The photosensitive resin composition according to claim 1 , wherein the content of the compound (b) is not less than 40 parts by weight per 100 parts by weight of the polyimide (a).5. The photosensitive resin composition according to claim 1 , wherein the content of an acrylic resin contained is less than 10 parts by weight per 100 parts by weight of the polyimide (a).7. The photosensitive resin composition film according to claim 6 , wherein the compound (b) has two or more epoxy groups in each molecule.8. The photosensitive resin composition film according to or claim 6 , wherein the content of the compound (b) is not less than 40 parts by weight per 100 parts by weight of the polyimide (a).9. The photosensitive resin composition film according to claim 6 , wherein the content of an acrylic resin contained is less than 10 parts by weight per 100 parts by weight of the polyimide (a).10. A laminate comprising a support claim 6 , the photosensitive resin composition film according to claim 6 , and a cover film in this order.11. A cured product of the photosensitive resin composition according to or of the photosensitive resin composition film according to .12. A semiconductor device comprising a cured product of the photosensitive resin composition according to or of the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. 1. A semiconductor device comprising;a metal oxide layer in contact with an adhesive over a first plastic substrate with an insulating surface,an element over the metal oxide layer, anda second plastic substrate over the element,wherein the first and second plastic substrate comprise a material selected from the group consisting of polyethylene terephthalate, polyether sulfone, polyethylene naphthalate, polycarbonate, nylon, polyether ether ketone, polysulfone, polyetherimide, polyarylate, polybutylene telephthalate, and polyimide.2. The semiconductor device according to claim 1 , wherein the element is a thin film transistor claim 1 , an organic light-emitting element claim 1 , an element comprising a liquid crystal claim 1 , a memory element claim 1 , a thin film diode claim 1 , a photoelectric conversion element comprising PIN junction of silicon claim 1 , or silicon resistor element.3. The semiconductor device according to claim 1 , wherein the semiconductor device is a video camera claim 1 , a digital camera claim 1 , a goggle type display claim 1 , a car navigation system claim 1 , a personal computer claim 1 , or a personal digital assistant.4. The semiconductor device according to claim 1 , wherein the metal oxide layer ...

Epoxy encapsulating and lamination adhesive and method of making same

An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

STRUCTURE AND MANUFACTURING METHOD OF CHIP SCALE PACKAGE

A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. 1. A chip package comprising:a substrate;a die having a first side coupled to the substrate, in which a first opening through the substrate exposes the first side of the die, and the die comprises a first conductive layer, a second conductive layer and a passivation layer at the first side of the die, in which a second opening in the passivation layer exposes a first contact point of the first conductive layer, and the first contact point is exposed by the second opening, the second conductive layer is coupled to the first contact point through the second opening, and the second conductive layer has a second contact point exposed by the first opening;a second opening adhesive material between the substrate and the first side of the die;a conductive interconnect coupled to the second contact point through the first opening; anda molding material on the substrate.2. The chip package of claim 1 , in which the first conductive layer comprises copper.3. The chip package of claim 1 , in which the first conductive layer comprises aluminum.4. The chip package of claim 1 , in ...

CROSSLINKED POLYIMIDE, COMPOSITION COMPRISING THE SAME AND METHOD FOR PRODUCING THE SAME

A novel polyimide which retains the characteristics of polyimides, that is, excellent heat resistance, electrical insulation and chemical resistance, of which dielectric constant is lower than those of the known polyimides, as well as a composition containing the same and a process for producing the same, is disclosed. The polyimide of the present invention is a cross-linked polyimide having a dielectric constant of not more than 2.7, which was produced by polycondensing (a) tetramine(s), (a) tetracarboxylic dianhydride(s) and (an) aromatic diamine(s) in the presence of a catalyst. 110-. (canceled)11. A process for producing a composition containing a cross-linked polyimide , comprising polycondensing (a) tetramine(s) , (a) tetracarboxylic dianhydride(s) and (an) aromatic diamine(s) in a polar solvent containing toluene or xylene in the presence of a catalyst under heat ,said polycondensation yielding said cross-linked polyimide, said cross-linked polyimide having a dielectric constant of not more than 2.7.12. The process according to claim 11 , wherein said tetramine(s) is(are) (an) aromatic tetramine(s).13. The process according to claim 12 , wherein said aromatic tetramine(s) is(are) at least one selected from the group consisting of bis(3 claim 12 ,5-diaminobenzoyl)-1 claim 12 ,4-piperazine claim 12 , bis(3 claim 12 ,5-diaminobenzoyl)-4 claim 12 ,4′-diaminodiphenylether claim 12 , bis-(3 claim 12 ,5-diaminophenyl)-2 claim 12 ,2′-dioxazol-4 claim 12 ,4′-diphenylsulfone claim 12 , bis(3 claim 12 ,5-diaminophenyl)-2 claim 12 ,2′-dioxazol-4 claim 12 ,4′-biphenyl claim 12 , 2 claim 12 ,7-diamino-9 claim 12 ,9′-(bis-4-aminophenyl)fluorene and bis(3 claim 12 ,5-diaminobenzoyl)-1 claim 12 ,4-diaminobenzene.14. The process according to claim 11 , wherein a diaminosiloxane is contained as a part of diamine component.15. The process according to claim 11 , wherein said catalyst is a binary catalyst comprising (an) acid(s) selected from the group consisting of oxalic acid ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer. 1. A semiconductor device comprising:an element formation layer over a substrate;an antenna over the element formation layer; anda protective layer over the element formation layer and the antenna,wherein the element formation layer comprises a plurality of circuits,wherein an electromagnetic wave supplies a power source voltage to each of the plurality of circuits, andwherein a value in a thickness ratio of the protective layer in a portion not covering the antenna to the antenna is at least 1.2.2. The semiconductor device according to claim 1 , wherein the protective layer comprises epoxy resin.3. The semiconductor device according to claim 1 , wherein the substrate has a thickness of 2 μm to 20 μm.4. The semiconductor device according to claim 1 , wherein an adhesive layer is provided between the substrate and the element formation layer.5. The semiconductor device according to wirelessly transmits signals by electromagnetic coupling method claim 1 , an electromagnetic induction method or a microwave method.6. A semiconductor device comprising:an element formation layer ...

Electronic Device Module Comprising Film of Homogeneous Polyolefin Copolymer and Grafted Silane

An electronic device module comprising: 1. An electronic device module comprising:A. at least one electronic device, and [ [{'sup': '3', 'a. an overall polymer density of not more than 0.905 g/cm;'}, 'b. total unsaturation of not more than 125 per 100,000 carbons;', 'c. up to 3 long chain branches/1000 carbons;', 'd. vinyl-3 content of less than 5 per 100,000 carbons; and', {'sub': 'n', 'e. a total number of vinyl groups/1000 carbons of less than the quantity (8000/M),'}, {'sup': '1', 'wherein the vinyl-3 content and vinyl group measurements are measured by gel permeation chromatography (145° C.) and H-NMR (125° C.),'}], '(1) an ethylene interpolymer having, '(2) grafted silane,', '(3) optionally, free radical initiator or a photoinitiator in an amount of at least about 0.05 wt % based on the weight of the interpolymer, and', '(4) optionally, a co-agent in an amount of at least about 0.05 wt % based upon the weight of the interpolymer., 'B. a polymeric material in intimate contact with at least one surface of the electronic device, the polymeric material comprising2. The module of in which the electronic device is a solar cell.3. The module of in which the free radical initiator is present.4. The module of in which the coagent is present.5. The module of in which the free radical initiator is a peroxide.6. The module of in which the polymeric material is in the form of a monolayer film in intimate contact with at least one face surface of the electronic device.7. The module of in which the polymeric material further comprises a scorch inhibitor in an amount from about 0.01 to about 1.7 wt %.8. The module of further comprising at least one glass cover sheet.9. The module of in which the free radical initiator is a photoinitiator.10. The module of which the grafted vinyl silane is grafted to the ethylene interpolymer.11. The module of in which the grafted vinyl silane is grafted to a separate compatible graft polymer and is added to the ethylene interpolymer of the ...

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate; a stress-relaxation adhesive layer made of resin that covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed; and a semiconductor element affixed, using a bonding material, to the surface of the electrode pattern opposite the insulating substrate, and a first sealing resin member which covers the semiconductor element and the semiconductor element substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than that of the first sealing resin member. 110-. (canceled)11. A semiconductor device , comprising:a semiconductor-element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate;a stress-relaxation adhesive layer made of resin which covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed and a part of portion of a surface of the electrode pattern;a semiconductor element affixed, via a bonding material, to the surface of the electrode pattern opposite the insulating substrate; anda first sealing resin member which covers the semiconductor element and the semiconductor-element substrate,wherein a coefficient of linear thermal expansion of the first sealing resin member is closer to a coefficient of linear thermal expansion of the electrode pattern than a coefficient of linear thermal expansion of the insulating substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than a modulus of elasticity of the first sealing resin member.12. A semiconductor device ...

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

CURABLE EPOXY RESIN COMPOSITION

Disclosed is a liquid curable epoxy resin composition which includes a cycloaliphatic epoxy compound (A) having at least one alicyclic skeleton and two or more epoxy groups per molecule; a silica (B); and a phosphite ester (C). The liquid curable epoxy resin composition preferably includes, for example, 5 to 80 parts by weight of the cycloaliphatic epoxy compound (A) having at least one alicyclic skeleton and two or more epoxy groups per molecule; 20 to 95 parts by weight of the silica (B); and 0.001 to 5.0 parts by weight of the phosphite ester (C), per 100 parts by weight of the total amount of the components (A) and (B). 1. A liquid curable epoxy resin composition comprising a cycloaliphatic epoxy compound (A); a silica (B); and a phosphite ester (C) , the cycloaliphatic epoxy compound (A) having at least one alicyclic skeleton and two or more epoxy groups per molecule.2. The liquid curable epoxy resin composition of claim 1 , comprising:5 to 80 parts by weight of the cycloaliphatic epoxy compound (A) having at least one alicyclic skeleton and two or more epoxy groups per molecule;20 to 95 parts by weight of the silica (B); and0.001 to 5.0 parts by weight of the phosphite ester (C),per 100 parts by weight of the component (A) and the component (B).3. The liquid curable epoxy resin composition of claim 1 , further comprising a curing catalyst (F) claim 1 , or a combination of a curing agent (D) with a curing accelerator (E).4. The liquid curable epoxy resin composition of claim 1 , as a semiconductor-encapsulating liquid curable epoxy resin composition.5. A resin cured product cured from the liquid curable epoxy resin composition of .6. A semiconductor device comprising a semiconductor element encapsulated with the semiconductor-encapsulating liquid curable epoxy resin composition of .7. The liquid curable epoxy resin composition of claim 2 , further comprising a curing catalyst (F) claim 2 , or a combination of a curing agent (D) with a curing accelerator (E).8. ...

SEMICONDUCTOR APPARATUS AND METHOD FOR PRODUCING THE SAME

A method for producing a semiconductor apparatus with a mold including an upper mold half and a lower mold half, includes: an arranging step of arranging on one of the upper mold half and the lower mold half of the mold a substrate on which a semiconductor device is mounted, the mold being kept at a room temperature or heated to a temperature up to 200° C., and arranging on the other of the upper mold half and the lower mold half a substrate on which no semiconductor device is mounted; an integrating step of integrating the substrate on which the semiconductor device is mounted and the substrate on which no semiconductor device is mounted by molding a thermosetting resin with the mold on which the substrates are arranged; and a step of dicing the integrated substrates taken out of the mold to obtain an individualized semiconductor apparatus. 1. A method for producing a semiconductor apparatus with a mold including an upper mold half and a lower mold half , the method comprising:an arranging step of arranging on one of the upper mold half and the lower mold half of the mold a substrate on which a semiconductor device is mounted, the mold being kept at a room temperature or heated to a temperature up to 200° C., and arranging on the other of the upper mold half and the lower mold half a substrate on which no semiconductor device is mounted;an integrating step of integrating the substrate on which the semiconductor device is mounted and the substrate on which no semiconductor device is mounted by molding a thermosetting resin with the mold on which the substrates are arranged; anda step of dicing the integrated substrates taken out of the mold to obtain an individualized semiconductor apparatus.2. The method for producing a semiconductor apparatus according to claim 1 , wherein the integrating step is configured to: place the thermosetting resin onto the substrate arranged on the lower mold half claim 1 , the thermosetting resin being in a liquid state at a room ...

CURABLE SILICONE RESIN COMPOSITION AND OPTOELECTRONIC DEVICE

A curable silicone resin composition is provided comprising (A) a linear organopolysiloxane having at least two aliphatic unsaturated radicals and optionally, an organopolysiloxane of branched or three-dimensional network structure, (B) an organohydrogenpolysiloxane having at least two SiH radicals and free of aliphatic unsaturation, (C) a hydrosilylation catalyst, and (D) silicone powder having an average particle size of 0.5-100 μm. The composition is suitable for LED encapsulation. 2. The composition of wherein in formula (1) claim 1 , Ar is phenyl claim 1 , and n is an integer of 1 to 100.4. The composition of wherein component (D) consists of particles of a polyorganosilsesquioxane resin or silicone particles covered partially or entirely on their surface with a polyorganosilsesquioxane resin.5. The composition of wherein a sub-composition composed essentially of components (A) claim 1 , (B) and (C) claim 1 , when cured claim 1 , has an oxygen permeability of up to 1 claim 1 ,000 cm/m/24 h/atm.6. The composition of which is used for the encapsulation of optoelectronic semiconductor.7. A cured product obtained by curing the curable silicone resin composition of .8. An optoelectronic semiconductor device obtained by encapsulating an optoelectronic semiconductor element with the curable silicone resin composition of and heat curing the composition. This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application Nos. 2012-055872 and 2012-136714 filed in Japan on Mar. 13, 2012 and Jun. 18, 2012, respectively, the entire contents of which are hereby incorporated by reference.This invention relates to a curable silicone resin composition useful as material for optical devices and optical members, insulating material for electronic devices and electronic parts, coating material or the like, and an optoelectronic semiconductor device encapsulated therewith.Epoxy resins are generally used as the encapsulating material for light-emitting ...

Resin-linear organosiloxane block copolymers

Organosiloxane block copolymers, curable compositions, and solid compositions derived from these block copolymers are disclosed. The organosiloxane block copolymers comprise: 40 to 90 mole percent disiloxy units of the formula [R 1 2 —SiO 2/2 ] 10 to 60 mole percent trisiloxy units of the formula [R 2 SiO 3/2 ] 0.5 to 35 mole percent silanol groups [≡SiOH] where R 1 is independently a C 1 to C 30 hydrocarbyl, R 2 is independently a C 1 to C 20 hydrocarbyl, wherein; the disiloxy units [R 1 2 SiO 2/2 ] are arranged in linear blocks having an average of from 10 to 400 disiloxy units [R 1 2 SiO 2/2 ] per linear block, the trisiloxy units [R 2 SiO 3/2 ] are arranged in non-linear blocks having a molecular weight of at least 500 g/mol, and at least 30% of the non-linear blocks are crosslinked with each other, each linear block is linked to at least one non-linear block, and the organosiloxane block copolymer has a molecular weight (M w ) of at least 20,000 g/mole.

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

ELECTRONIC DEVICE

An electronic device is provided wherein the characteristics thereof are prevented from deteriorating. The electronic device () is provided with: a chip component () having an electronic element (); a wiring board () on which the chip component () is mounted with a space therebetween, the space for containing the electronic element (); a resin layer () provided from the surface of the chip component () to the surface of the wiring board () so as to surround the space; and an inorganic insulating layer (), which is provided at the resin layer () and is positioned at the side of the space. Since entry of water vapor into the space can be reduced not only by means of the resin layer () but also by means of the inorganic insulating layer (), the electronic device () having high airtight sealing performance can be provided. 1. An electronic device comprising:a chip component having an electronic element;a wiring board on which the chip component is mounted with a space therebetween, the space for containing the electronic element;a resin layer provided from the surface of the chip component to the surface of the wiring board so as to surround the space; andan inorganic insulating layer which is provided at the resin layer and is positioned at the side of the space.2. The electronic device as set forth in claim 1 , wherein the inorganic insulating layer is provided on the inner surface of the resin layer.3. The electronic device as set forth in claim 1 , wherein the inorganic insulating layer is provided on the outer surface of the resin layer.4. The electronic device as set forth in claim 2 , wherein a relationship of α1>α2>α3 is satisfied where the thermal expansion coefficients of the resin layer claim 2 , inorganic insulating layer claim 2 , and chip component are α1 claim 2 , α2 claim 2 , and α3.5. The electronic device as set forth in claim 1 , wherein the inorganic insulating layer is provided inside the resin layer.6. The electronic device as set forth in claim 1 ...

Laminate

Provided is a laminate including a thermoplastic resin layer and a substrate, which has superior transparency, is resistant to “warping”, and is advantageous for the encapsulation and surface protection of opto-electronic devices. The laminate includes a substrate; a thermoplastic resin layer having a thickness of more than 200 μm and less than or equal to 500 μm; and a pressure-sensitive adhesive layer lying between the substrate and thermoplastic resin layer and bonding them to each other, in which the thermoplastic resin layer has a 180-degree peel strength of 1.0 N/25 mm or more with respect to the pressure-sensitive adhesive layer at 23° C. The laminate preferably has a total luminous transmittance of 80% or more.

Method of Preparing Liquid Chemical for Forming Protective Film

Disclosed herein is a method for preparing a liquid chemical for forming a water-repellent protective film, the liquid chemical being for forming the water-repellent protective film at the time of cleaning a wafer having at its surface an uneven pattern and containing silicon element at least at a part of the uneven pattern at least on surfaces of recessed portions of the uneven pattern, the liquid chemical containing a nonaqueous organic solvent, a silylation agent, and an acid or a base. The method includes (i) adjusting a water content of the nonaqueous organic solvent to 200 mass ppm or less by dehydration; and (ii) mixing the nonaqueous organic solvent, the silylation agent, and the acid or the base after the adjusting step. 1. A method for preparing a liquid chemical for forming a water-repellent protective film , the liquid chemical being for forming the water-repellent protective film at the time of cleaning a wafer having at its surface an uneven pattern and containing a silicon element at least at a part of the uneven pattern at least on surfaces of recessed portions of the uneven pattern , the liquid chemical comprising a nonaqueous organic solvent , a silylation agent , and an acid or a base , the method comprising:adjusting a water content of the nonaqueous organic solvent to 200 mass ppm or less by dehydration; andmixing the nonaqueous organic solvent, the silylation agent, and the acid or the base after the adjusting step.2. A method for preparing the liquid chemical for forming the water-repellent protective film claim 1 , as claimed in claim 1 , wherein the adjusting step is at least one selected from the group consisting ofa step of purifying the nonaqueous organic solvent by distillation,a step of removing water from the nonaqueous organic solvent by adding an insoluble water-absorbing agent to the nonaqueous organic solvent,a step of performing a substitution to the nonaqueous organic solvent by using a dried inert gas under exposure to air, anda ...

EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR DEVICE

A highly reliable semiconductor device with the improved humidity resistance reliability is disclosed. A disclosed epoxy resin composition for semiconductor encapsulation encapsulates, in the manufacture of the semiconductor device, a semiconductor element that is mounted on a lead frame having a die pad unit or a circuit substrate and a wire that connects an electrical junction disposed on the lead frame or circuit substrate and an electrode pad disposed on the semiconductor element. The epoxy resin composition includes an epoxy resin (A), a curing agent (B), and an inorganic filler (C). The epoxy resin (A) has a main peak area of 90% or more with respect to the total area of all peaks as measured by the gel permeation chromatography area method. 1. An epoxy resin composition for semiconductor encapsulation , which is used to produce a semiconductor device by encapsulating a semiconductor element that is mounted on a lead frame having a die pad unit or a circuit substrate , and a metal wire that electrically connects an electrode pad disposed on the semiconductor element and an electrical junction disposed on the lead frame or the circuit substrate; the epoxy resin composition for semiconductor encapsulation comprises an epoxy resin (A) , a curing agent (B) , and an inorganic filler (C) , wherein the epoxy resin (A) has a main peak area of 90% or more with respect to the total area of all peaks as measured by a gel permeation chromatography area method.2. The epoxy resin composition for semiconductor encapsulation according to claim 1 , wherein the epoxy resin (A) has a main peak area of 92% or more with respect to the total area of all peaks as measured by the gel permeation chromatography area method.3. The epoxy resin composition for semiconductor encapsulation according to claim 1 , wherein the epoxy resin (A) has a total chlorine content of 300 ppm or less and a hydrolysable chlorine content of 150 ppm or less.4. The epoxy resin composition for semiconductor ...

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.