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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 17806. Отображено 100.
02-02-2012 дата публикации

Vapor deposition of metal oxides, silicates and phosphates, and silicon dioxide

Номер: US20120028478A1
Принадлежит: Harvard College

Metal silicates or phosphates are deposited on a heated substrate by the reaction of vapors of alkoxysilanols or alkylphosphates along with reactive metal amides, alkyls or alkoxides. For example, vapors of tris(tert-butoxy)silanol react with vapors of tetrakis(ethylmethylamido)hafnium to deposit hafnium silicate on surfaces heated to 300° C. The product film has a very uniform stoichiometry throughout the reactor. Similarly, vapors of diisopropylphosphate react with vapors of lithium bis(ethyldimethylsilyl)amide to deposit lithium phosphate films on substrates heated to 250° C. Supplying the vapors in alternating pulses produces these same compositions with a very uniform distribution of thickness and excellent step coverage.

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09-02-2012 дата публикации

Substrate processing apparatus and producing method of semiconductor device

Номер: US20120034788A1
Принадлежит: Hirohisa Yamazaki, Masanori Sakai, Toru Kagaya

A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O 3 ) are alternately fed into the reaction tubeto generate Al 2 O 3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube where a temperature is lower than a temperature near the wafer, and the ozone and TMA are supplied into the reaction tube through the nozzle.

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19-04-2012 дата публикации

Two silicon-containing precursors for gapfill enhancing dielectric liner

Номер: US20120094468A1
Принадлежит: Applied Materials Inc

Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

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10-05-2012 дата публикации

Method of depositing dielectric films using microwave plasma

Номер: US20120115334A1
Автор: Hiroyuki Takaba
Принадлежит: Tokyo Electron Ltd

Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.

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14-06-2012 дата публикации

Method for forming stair-step structures

Номер: US20120149201A1
Автор: Hyun-Yong Yu, Qian Fu
Принадлежит: Lam Research Corp

A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

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28-06-2012 дата публикации

Semiconductor Device

Номер: US20120161226A1
Автор: Mohamed N. Darwish
Принадлежит: MaxPower Semiconductor Inc

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

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28-06-2012 дата публикации

Thin film forming method, thin film forming apparatus, and program

Номер: US20120164847A1
Принадлежит: Tokyo Electron Ltd

A control unit heats a reaction pipe to a load temperature by controlling a temperature-raising heater 16, and then makes semiconductor wafers received in the reaction pipe. Next, the control unit heats the reaction pipe in which the semiconductor wafers are received to a film formation temperature by controlling the temperature-raising heater, and then forms thin films on the semiconductor wafers by supplying a film forming gas into the reaction pipe from a process gas introducing pipe. Also, the control unit sets the load temperature to a temperature higher than the film formation temperature.

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19-07-2012 дата публикации

Semiconductor Device, An Electronic Device and an Electronic Apparatus

Номер: US20120181633A1
Автор: Masayasu Miyata
Принадлежит: Seiko Epson Corp

A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5 ; and a gate insulating film 3 provided between the base 2 and the gate electrode 5 . The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2 , and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.

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19-07-2012 дата публикации

Methods for manufacturing superjunction semiconductor device having a dielectric termination

Номер: US20120184072A1
Автор: Xu Cheng
Принадлежит: Icemos Technology Ltd

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

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23-08-2012 дата публикации

Method and apparatus of fabricating silicon carbide semiconductor device

Номер: US20120214309A1
Принадлежит: Sumitomo Electric Industries Ltd

A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.

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30-08-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120220130A1
Автор: Chai-O CHUNG
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a trench over a substrate, forming a spin on dielectric (SOD) layer in a first part of the trench, and forming an oxide layer within the trench, where the oxide layer is formed over the SOD layer by using a process for plasma chemical vapor deposition.

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06-09-2012 дата публикации

Reduced pattern loading using silicon oxide multi-layers

Номер: US20120225565A1
Принадлежит: Applied Materials Inc

Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

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06-09-2012 дата публикации

Annealing method and annealing apparatus

Номер: US20120225568A1
Принадлежит: Tokyo Electron Ltd

An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film.

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20-09-2012 дата публикации

Methods for etch of sin films

Номер: US20120238102A1
Принадлежит: Applied Materials Inc

A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

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27-09-2012 дата публикации

Method of manufacturing a base substrate for a semi-conductor on insulator type substrate

Номер: US20120244687A1
Принадлежит: Soitec SA

A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.

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04-10-2012 дата публикации

Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication

Номер: US20120252204A1
Принадлежит: International Business Machines Corp

An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.

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01-11-2012 дата публикации

Hardmask materials

Номер: US20120276752A1
Принадлежит: Individual

Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si x B y C z , Si x B y N z , Si x B y C z N w , B x C y , and B x N y . In some embodiments, a hardmask film includes a germanium-rich GeN x material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

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20-12-2012 дата публикации

Deposition of thin film dielectrics and light emitting nano-layer structures

Номер: US20120322181A1
Автор: Jean-Paul Noel, Ming Li
Принадлежит: Group IV Semiconductor Inc

A method is disclosed for deposition of thin film dielectrics, and in particular for chemical vapour deposition of nano-layer structures comprising multiple layers of dielectrics, such as, silicon dioxide, silicon nitride, silicon oxynitride and/or other silicon compatible dielectrics. The method comprises post-deposition surface treatment of deposited layers with a metal or semiconductor source gas, e.g. a silicon source gas. Deposition of silicon containing dielectrics preferably comprises silane-based chemistry for deposition of doped or undoped dielectric layers, and surface treatment of deposited dielectric layers with silane. Surface treatment provides dielectric layers with improved layer-to-layer uniformity and lateral continuity, and substantially atomically flat dielectric layers suitable for multilayer structures for electroluminescent light emitting structures, e.g. active layers containing rare earth containing luminescent centres. Doped or undoped dielectric thin films or nano-layer dielectric structures may also be provided for other semiconductor devices.

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27-12-2012 дата публикации

Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Номер: US20120326163A1
Принадлежит: Cree Inc

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

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10-01-2013 дата публикации

Silicon oxide film forming method and plasma oxidation apparatus

Номер: US20130012033A1
Принадлежит: Tokyo Electron Ltd

A silicon oxide film forming method includes forming a silicon oxide film by allowing a plasma of a processing gas to react on a silicon exposed on a surface of a target object to be processed in a processing chamber of a plasma processing apparatus. The processing gas includes an ozone-containing gas having a volume ratio of O 3 to a total volume of O 2 and O 3 , ranging 50% or more.

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17-01-2013 дата публикации

Digital oxide deposition of sio2 layers on wafers

Номер: US20130017689A1
Принадлежит: UNIVERSITY OF SOUTH CAROLINA

Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.

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28-02-2013 дата публикации

Semiconductor Laser Device and a Method for Manufacturing a Semiconductor Laser Device

Номер: US20130051421A1
Принадлежит: Individual

A semiconductor laser device formed on a semiconductor substrate, the device comprising: a passivation layer arranged on an upper surface of the device structure for resisting moisture ingress, wherein the passivation layer comprises an inner layer deposited on the upper surface of the device by atomic layer deposition and an outer layer deposited on the inner layer, and comprising a material that is inert in the presence of water.

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07-03-2013 дата публикации

Method of manufacturing semiconductor device and substrate processing apparataus

Номер: US20130059451A1
Принадлежит: HITACHI KOKUSAI ELECTRIC INC

A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen.

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28-03-2013 дата публикации

Halogenated organoaminosilane precursors and methods for depositing films comprising same

Номер: US20130078392A1
Принадлежит: Air Products and Chemicals Inc

Described herein are precursors and methods of forming films. In one aspect, there is provided a precursor having Formula I: X m R 1 n H p Si(NR 2 R 3 ) 4-m-n-p   I wherein X is selected from Cl, Br, I; R 1 is selected from linear or branched C 1 -C 10 alkyl group, a C 2 -C 12 alkenyl group, a C 2 -C 12 alkynyl group, a C 4 -C 10 cyclic alkyl, and a C 6 -C 10 aryl group; R 2 is selected from a linear or branched C 1 -C 10 alkyl, a C 3 -C 12 alkenyl group, a C 3 -C 12 alkynyl group, a C 4 -C 10 cyclic alkyl group, and a C 6 -C 10 aryl group; R 3 is selected from a branched C 3 -C 10 alkyl group, a C 3 -C 12 alkenyl group, a C 3 -C 12 alkynyl group, a C 4 -C 10 cyclic alkyl group, and a C 6 -C 10 aryl group; m is 1 or 2; n is 0, 1, or 2; p is 0, 1 or 2; and m+n+p is less than 4, wherein R 2 and R 3 are linked or not linked to form a ring.

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25-04-2013 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20130099350A1

A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

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02-05-2013 дата публикации

Method of forming silicon oxide film

Номер: US20130109197A1
Принадлежит: Tokyo Electron Ltd

A method of forming a silicon oxide film includes forming a seed layer on a base, forming a silicon film on the seed layer, and forming the silicon oxide film on the base by oxidizing the silicon film and the seed layer.

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16-05-2013 дата публикации

Pattern forming method and manufacturing method of semiconductor device

Номер: US20130122429A1
Принадлежит: Tokyo Electron Ltd

A disclosed manufacturing method of a semiconductor device includes laminating a substrate, an etched film, an anti-reflective coating film, and a resist film; forming a pattern made of the resist film using a photolithographic technique; forming the third mask pattern array by a mask pattern forming method; and a seventh step of forming a fourth mask pattern array by processing the etched film using the third mask pattern array.

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23-05-2013 дата публикации

Film deposition method and film deposition apparatus

Номер: US20130130512A1
Принадлежит: Individual

A film deposition method including: a step of carrying a substrate into a vacuum chamber, and placing the substrate on a turntable; a step of rotating the turntable; and an adsorption-formation-irradiation step of supplying a first reaction gas to the substrate from a first reaction gas supply part to adsorb the first reaction gas on the substrate; supplying a second reaction gas from a second reaction gas supply part so that the first reaction gas adsorbed on the substrate reacts with the second reaction gas so as to form a reaction product on the substrate; and supplying a hydrogen containing gas to a plasma generation part that is separated from the first reaction gas supply part and the second reaction gas supply part in a circumferential direction of the turntable so as to generate plasma above the turntable and to irradiate the plasma to the reaction product.

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11-07-2013 дата публикации

Semiconductor device and fabrication method for the same

Номер: US20130175548A1
Автор: Chiaki Kudou
Принадлежит: Panasonic Corp

A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

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11-07-2013 дата публикации

Interlevel Dielectric Stack for Interconnect Structures

Номер: US20130175697A1
Принадлежит: International Business Machines Corp

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

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15-08-2013 дата публикации

Interconnection structures in a semiconductor device and methods of manufacturing the same

Номер: US20130207267A1
Автор: Il Cheol Rho
Принадлежит: SK hynix Inc

Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

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26-09-2013 дата публикации

Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium

Номер: US20130252439A1
Принадлежит: HITACHI KOKUSAI ELECTRIC INC

A method includes: forming a thin film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas to the substrate in a process chamber; and (b) supplying a reactive gas to the substrate in the process chamber, wherein at least one of (a) and (b) includes: (c) supplying the source gas or the reactive gas at a first flow rate with exhaust of an inside of the process chamber being suspended until an inner pressure of the process chamber reaches a predetermined pressure; and (d) supplying the source gas or the reactive gas at a second flow rate less than the first flow rate with exhaust of the inside of the process chamber being performed while maintaining the inner pressure of the process chamber at the predetermined pressure after the inner pressure of the process chamber reaches the predetermined pressure.

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24-10-2013 дата публикации

Etch Stop Layer Formation In Metal Gate Process

Номер: US20130277764A1
Принадлежит: International Business Machines Corp

A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

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07-11-2013 дата публикации

Method for fabricating semiconductor device and the semiconductor device

Номер: US20130292700A1

A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO 2 film and an Al 2 O 3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.

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07-11-2013 дата публикации

HIGH TEMPERATURE ATOMIC LAYER DEPOSITION OF SILICON OXIDE THIN FILMS

Номер: US20130295779A1
Принадлежит:

Composition(s) and atomic layer deposition (ALD) process(es) for the formation of a silicon oxide containing film at one or more deposition temperature of about 500° C. is disclosed. In one aspect, the composition and process use one or more silicon precursors selected from compounds having the following formulae I, II, described and combinations thereof

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12-12-2013 дата публикации

Hardmask materials

Номер: US20130330932A1
Принадлежит: Novellus Systems Inc

Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si x B y C z , Si x B y N z , Si x B y C z N w , B x C y , and B x N y . In some embodiments, a hardmask film includes a germanium-rich GeN x material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

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02-01-2014 дата публикации

High voltage three-dimensional devices having dielectric liners

Номер: US20140001569A1
Принадлежит: Intel Corp

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

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02-01-2014 дата публикации

SILICON OXIDE FILM FORMING METHOD AND APPARATUS

Номер: US20140004715A1
Принадлежит:

A method of forming a silicone oxide film includes: forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; and modifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere. 1. A method of forming a silicone oxide film , comprising:forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; andmodifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere.2. The method of claim 1 , wherein the chlorine-containing silicon source includes one of tetrachlorosilane claim 1 , trichlorosilane claim 1 , dichlorosilane claim 1 , monochlorosilane and hexachlorodisilane.3. The method of claim 1 , wherein a temperature in the reaction chamber is maintained at 600 to 1000 degrees C. at forming the silicone oxide film and modifying the silicon oxide film.4. The method of claim 1 , wherein a temperature in the reaction chamber at forming the silicone oxide film is equal to a temperature in the reaction chamber at modifying the silicon oxide film.5. The method of claim 1 , wherein modifying the silicon oxide film includes supplying the hydrogen and the oxygen into the reaction chamber at a ratio of a supply amount of the oxygen to a supply amount of the hydrogen ranging from 1.2:1 to 3:1.6. A silicone oxide film forming apparatus claim 1 , comprising:a film forming unit ...

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09-01-2014 дата публикации

SILICON OXIDE FILM FORMING METHOD AND APPARATUS

Номер: US20140011371A1
Принадлежит: TOKYO ELECTRON LIMITED

A silicone oxide film forming method includes forming a silicon oxide film on a plurality of target objects by supplying a chlorine atom-containing silicon source into a reaction chamber accommodating the plurality of target objects. Forming the silicon oxide film includes making an interior of the reaction chamber be under a hydrogen atmosphere by supplying a hydrogen gas into the reaction chamber. 1. A method of forming a silicone oxide film , comprising:forming a silicon oxide film on a plurality of target objects by supplying a chlorine atom-containing silicon source into a reaction chamber accommodating the plurality of target objects,wherein forming the silicon oxide film includes making an interior of the reaction chamber be under a hydrogen atmosphere by supplying a hydrogen gas into the reaction chamber.2. The method of claim 1 , wherein the chlorine atom-containing silicon source includes one of tetrachlorosilane claim 1 , trichlorosilane claim 1 , dichlorosilane claim 1 , monochlorosilane and hexachlorodisilane.3. The method of claim 1 , wherein a temperature in the reaction chamber is maintained at 600 to 1000 degrees C. at forming the silicone oxide film.4. The method of claim 1 , wherein a supply amount of the hydrogen gas supplied into the reaction chamber is 0.5 to 5 times of a supply amount of the chlorine atom-containing silicon source.5. A silicone oxide film forming apparatus claim 1 , comprising:a film forming gas supply unit configured to supply a film forming gas into a reaction chamber accommodating a plurality of target objects, the film forming gas having a chlorine atom-containing silicon source;a hydrogen supply unit configured to supply a hydrogen gas into the reaction chamber; anda control unit configured to control the film forming gas supply unit and the hydrogen supply unit,wherein the control unit controls the hydrogen supply unit such that the hydrogen supply unit supplies the hydrogen gas into the reaction chamber, thus making an ...

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09-01-2014 дата публикации

Film deposition method

Номер: US20140011372A1
Принадлежит: Tokyo Electron Ltd

A film deposition method deposits a silicon oxide film on a substrate in which a concave portion is formed by supplying a silicon-containing gas to the substrate so that the silicon-containing gas is adsorbed on the substrate and by oxidizing the adsorbed silicon-containing gas with an oxidation gas. A gas-phase temperature in an atmosphere above the substrate to which the silicon-containing gas is supplied can be kept lower by an inactive gas supplied from a separation area that separates the silicon gas supply part and the oxidation gas supply part even if the substrate is heated to a temperature higher than a temperature that can decompose the silicon-containing gas. Accordingly, the silicon-containing gas can adsorb on the substrate without decomposing in the gas phase.

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06-02-2014 дата публикации

Carbosilane Precursors For Low Temperature Film Deposition

Номер: US20140038427A1
Принадлежит:

Provided are processes for the low temperature deposition of silicon-containing films using carbosilane precursors containing a carbon atom bridging at least two silicon atoms. Certain methods comprise providing a substrate; in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms; exposing the carbosilane precursor to a low-powered energy sourcedirect plasma to provide a carbosilane at the substrate surface; and densifying the carbosilanestripping away at least some of the hydrogen atoms to provide a film comprising SiC. The SiC film may be exposed to the carbosilane surface to a nitrogen source to provide a film comprising SiCN. 1. A method of forming a layer on a substrate surface , the method comprising:providing a substrate;in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms;exposing the carbosilane precursor to a low-powered energy source to provide a carbosilane at the substrate surface; andstripping away at least some of the hydrogen atoms to provide a film comprising SiC.2. The method of claim 1 , wherein stripping away at least some of the hydrogen atoms comprises exposing the substrate surface to a plasma containing one or more of He claim 1 , Ar and H.3. The method of claim 1 , wherein the film comprising SiC has a ratio of Si:C approximately matching that of the carbosilane precursor.4. The method of claim 3 , wherein the carbosilane precursor is one or more of 1 claim 3 ,3 claim 3 ,5-trisilapentane claim 3 , 1 claim 3 ,3-disilapropane claim 3 , 1 claim 3 ,3-disilabutane claim 3 , 1 claim 3 ,3-disilacyclobutane and 1 claim 3 ,3 claim 3 ,5-trisilacyclohexane.5. The method of claim 4 , wherein the carbosilane precursor comprises 1 claim 4 ,3 claim 4 ,5-trisilapentane.6. The method of claim 4 , wherein the carbosilane precursor comprises 1 claim 4 ,3-disilapropane.7. ...

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27-02-2014 дата публикации

METHOD FOR FORMING SILICON OXIDE FILM OF SEMICONDUCTOR DEVICE

Номер: US20140057458A1
Принадлежит: SK HYNIX INC.

A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved. 1. A method for forming a silicon oxide film of a semiconductor device comprising:depositing a silicon oxide precursor over a semiconductor substrate, a surface of the semiconductor substrate including a step coverage region; andforming a silicon oxide film by curing the silicon oxide precursor,wherein the surface of the semiconductor substrate is treated with an amine-based compound.2. The method according to claim 1 , wherein the step coverage region includes any of a trench claim 1 , a contact hole claim 1 , and two or more conductive patterns.3. The method according to claim 1 , wherein the silicon oxide precursor compound comprises a silicon-containing compound and a solvent.4. The method according to claim 3 , wherein the silicon-containing compound has a weight-average molecular weight of 3000-7000 claim 3 , the silicon-containing compound being any of a polysilazane compound claim 3 , and a trisilylamine compound.5. The method according to claim 3 , wherein the solvent is any of dibutyl ether claim 3 , benzene claim 3 , toluene claim 3 , xylene claim 3 , and diisopropyl ether.6. The method according to claim 1 , wherein the silicon oxide precursor is applied by a coating or a deposition process.7. The method according to claim 6 , wherein the coating or deposition process is carried out under a room temperature condition.8. The method according to claim 1 , wherein the curing process is carried out by any of a steam annealing claim 1 , a thermal annealing claim 1 , an inductively coupled plasma annealing claim 1 , an ultraviolet annealing claim 1 , an e-beam annealing claim 1 , an acid-vapor catalytic decomposition annealing claim 1 , a base-vapor catalytic ...

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06-03-2014 дата публикации

Method of forming a material layer in a semiconductor structure

Номер: US20140065808A1
Принадлежит: Globalfoundries Inc

A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

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13-03-2014 дата публикации

PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS

Номер: US20140073113A1
Автор: NAKAHARA Yoichi
Принадлежит: TOKYO ELECTRON LIMITED

A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited. 1. A plasma etching method , comprising:depositing a silicon-containing deposit by plasma process using Si-containing gas on an object to be processed which includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the plurality of narrow linear portions and the film to be processed which is exposed between the plurality of narrow linear portions; andetching the deposit by plasma of CF-based gas and CHF-based gas after depositing the silicon-containing deposit so as to expose the plurality of narrow linear portions of the organic film and the film to be processed between the plurality of narrow linear portions.2. The plasma etching method of claim 1 , further comprising:ashing the exposed organic film so as to selectively remove the exposed organic film;etching the rigid film remaining after the etching the deposit; andetching the film to be processed using the remaining rigid film as a mask.3. The plasma etching method of claim 1 , wherein bias voltage is applied in the depositing the silicon-containing deposit.4. The plasma etching method of claim 1 , further comprising:performing a surface modifying processing on the silicon-containing deposit using plasma by hydrogen gas ...

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03-04-2014 дата публикации

Transistor

Номер: US20140091395A1
Принадлежит: United Microelectronics Corp

A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.

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03-04-2014 дата публикации

Methods of providing dielectric to conductor adhesion in package structures

Номер: US20140091469A1
Принадлежит: Individual

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

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10-04-2014 дата публикации

Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus

Номер: US20140099797A1
Автор: Masato Terasaki
Принадлежит: HITACHI KOKUSAI ELECTRIC INC

A silicon oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a silicon-containing layer on the substrate by supplying a source gas containing silicon, to the substrate housed in a processing chamber and heated to a first temperature; and oxidizing and changing the silicon-containing layer formed on the substrate, to a silicon oxide layer by supplying reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure atmosphere of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure atmosphere of less than atmospheric pressure and heated to a second temperature equal to the first temperature or higher than the first temperature.

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07-01-2016 дата публикации

GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20160002093A1
Принадлежит:

A glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a glass raw material which contains at least ZnO, SiO, BO, AlOand at least two oxides of alkaline earth metals selected from a group consisting of BaO, CaO and MgO and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing no filler. 1. A glass composition for protecting a semiconductor junction used in forming a glass layer which protects a pn junction in a semiconductor element having a pn junction exposure portion where the pn junction is exposed , wherein{'sub': 2', '2', '3', '2', '3, 'the glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a glass raw material which contains at least ZnO, SiO, BO, AlOand at least two oxides of alkaline earth metals selected from a group consisting of BaO, CaO and MgO with the following contents and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing no filler.'}ZnO: 30 mol % to 60 mol %{'sub': '2', 'SiO: 5 mol % to 45 mol %'}{'sub': 2', '3, 'BO: 5 mol % to 30 mol %'}{'sub': 2', '3, 'AlO: 5 mol % to 13 mol %'}oxide of alkaline earth metal: 1 mol % to 10 mol %2. The glass composition for protecting a semiconductor junction according to claim 1 , wherein the glass raw material substantially contains no Bi.3. The glass composition for protecting a semiconductor junction according to claim 2 , wherein the glass raw material substantially contains no P.4. The glass composition for protecting a semiconductor junction according to claim 1 , wherein the glass raw material further contains nickel oxide.5. The glass composition for protecting a semiconductor junction according to claim 1 , wherein the glass raw material further contains ...

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01-01-2015 дата публикации

METHODS OF FORMING SILICON-CONTAINING DIELECTRIC MATERIALS AND SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

Номер: US20150004805A1
Принадлежит:

A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures. 1. A method of forming a silicon-containing dielectric material , comprising:forming a plasma comprising nitrogen radicals;absorbing the nitrogen radicals onto a substrate; andexposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate.2. The method of claim 1 , wherein forming a plasma comprising nitrogen radicals comprises dissociating a nitrogen radical precursor into the nitrogen radicals.3. The method of claim 2 , wherein dissociating a nitrogen radical precursor into the nitrogen radicals comprises dissociating a nitrogen radical precursor selected from the group consisting of elemental nitrogen claim 2 , nitrous oxide claim 2 , ammonia claim 2 , nitrogen oxide claim 2 , azide claim 2 , an azide derivative claim 2 , dinitrogen pentoxide claim 2 , hydrazine claim 2 , and a hydrazine derivative into the nitrogen radicals.4. The method of claim 1 , wherein forming a plasma comprising nitrogen radicals comprises forming the plasma comprising the nitrogen radicals and helium.5. The method of claim 1 , wherein absorbing the nitrogen radicals onto a substrate and exposing the substrate to a silicon-containing precursor in a non-plasma environment comprises forming monolayers of nitrogen and silicon as the substrate is heated.6. The method of claim 1 , wherein exposing the substrate to a silicon-containing precursor comprises exposing ...

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01-01-2015 дата публикации

LOW-K OXIDE DEPOSITION BY HYDROLYSIS AND CONDENSATION

Номер: US20150004806A1
Принадлежит:

Methods for depositing flowable dielectric films using halogen-free precursors and catalysts on a substrate are provided herein. Halogen-free precursors and catalysts include self-catalyzing aminosilane compounds and halogen-free organic acids. Flowable films may be used to fill pores in existing dielectric films on substrates having exposed metallization layers. The methods involve hydrolysis and condensation reactions. 1. A method of depositing a film on a semiconductor substrate , the method comprising:introducing process gases comprising a silicon-containing precursor, an oxidant, and a halogen-free acid catalyst compound to a reaction chamber; andexposing the substrate to the process gases under conditions such that a condensed flowable film forms on the substrate,{'sub': 'N', 'wherein the chemical reactions that form the flowable film comprise a S1 hydrolysis mechanism and condensation.'}2. The method of claim 1 , wherein the halogen-free catalyst compound is selected from the group consisting of acetic acid claim 1 , and photosensitive organic acid catalysts.3. The method of claim 2 , wherein the photosensitive organic acid catalyst is selected from the group consisting of sulfonic acid claim 2 , picric acid claim 2 , tartaric acid claim 2 , citric acid claim 2 , ethylenediaminetetraacetic acid claim 2 , pyrophosphoric acid claim 2 , substituted derivatives of these acids claim 2 , and combinations thereof.4. The method of claim 2 , wherein the substrate is exposed to the process gases while the substrate is exposed to UV radiation.5. The method of claim 1 , wherein the oxidant is selected from the group consisting of water claim 1 , ozone claim 1 , and peroxide.6. The method of claim 1 , wherein the silicon-containing precursor and the oxidant are introduced to the reaction chamber via separate inlets.7. The method of claim 1 , wherein the halogen-free catalyst compound is introduced to the reaction chamber separate from the silicon-containing precursor and ...

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05-01-2017 дата публикации

Liquid crystal display device and electronic device including the liquid crystal display device

Номер: US20170004788A1
Принадлежит: Semiconductor Energy Laboratory Co Ltd

In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×10 14 /cm 3 .

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05-01-2017 дата публикации

Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device

Номер: US20170004966A1
Автор: Sato Takayuki
Принадлежит:

A substrate processing apparatus includes: a plasma generating unit to excite a process gas into plasma state; a process chamber where a substrate is processed using the process gas excited in plasma state; a loading port installed at a sidewall of the process chamber, wherein the substrate is passed through the loading port when the substrate is loaded into the process chamber; a substrate support supporting the substrate in the process chamber; an electrode unit installed in the substrate support and including a plurality of divided electrodes; an impedance adjusting unit electrically connected to each of the plurality of electrodes to adjust an impedance thereof; and a control unit to control the impedance of the impedance adjusting unit so as to adjust the electrical potentials of the respective electrodes of the electrode unit. The substrate processing apparatus improves the uniformity of a substrate during a substrate processing process using plasma. 1. A substrate processing apparatus comprising:a plasma generating unit configured to excite a process gas into plasma state;a process chamber where a substrate is processed using the process gas excited in plasma state;a loading port installed at a sidewall of the process chamber, wherein the substrate is passed through the loading port when the substrate is loaded into the process chamber;a substrate support supporting the substrate in the process chamber;an electrode unit installed in the substrate support and including a plurality of divided electrodes;an impedance adjusting unit electrically connected to each of the plurality of electrodes and configured to adjust an impedance thereof; anda control unit configured to control the impedance of the impedance adjusting unit so as to adjust the electrical potentials of the respective electrodes of the electrode unit, wherein the control unit controls the impedance adjusting unit such that an impedance of an electrode positioned in a direction facing the loading ...

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05-01-2017 дата публикации

SELECTIVE DEPOSITION OF SILICON OXIDE FILMS

Номер: US20170004974A1
Принадлежит:

Embodiments described herein generally provide a method for filling features formed on a substrate. In one embodiment, a method for selectively forming a silicon oxide layer on a substrate is provided. The method includes selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature. 1. A method for selectively forming a silicon oxide layer on a substrate , comprising:selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by exposing the patterned feature to tetraethyl orthosilicate (TEOS) and ozone.2. The method of claim 1 , further comprising:after the selectively depositing a silicon oxide layer within the patterned feature, annealing the selectively deposited silicon oxide layer.3. The method of claim 2 , further comprising:after the annealing the selectively deposited silicon oxide layer, wet etching the silicon oxide layer.4. The method of claim 1 , wherein the tetraethyl orthosilicate (TEOS) flows into a 300 mm substrate processing chamber at a rate between 400 mg/minute and 2 g/minute.5. The method of claim 4 , wherein the ozone flows into the 300 mm substrate ...

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05-01-2017 дата публикации

SELF-FORMING BARRIER FOR SUBTRACTIVE COPPER

Номер: US20170005039A1
Принадлежит:

A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines. 1. A method of forming electrically conductive structures comprising:forming at least one copper containing line including a barrier forming element;applying a first anneal to the at least one copper containing line, wherein the first anneal increases grain size of copper in said at least one copper containing line;depositing a dielectric fill in a space between adjacent copper containing lines; andapplying a second anneal to the plurality of copper containing lines, wherein during said second anneal said barrier forming element diffuse to an interface between sidewalls of the plurality of the copper containing pillars and the dielectric fill to form a barrier layer.2. The method of claim 1 , wherein the barrier forming element comprises manganese (Mn).3. The method of claim 1 , wherein the forming of the copper containing lines including the barrier forming element comprises:forming a first layer of barrier material on a substrate;forming a seed layer containing the barrier forming element on the first layer of the barrier material;forming a copper layer on the seed layer, wherein the seed layer and the copper layer provide the at least one copper containing layer including the barrier forming element; andetching the ...

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05-01-2017 дата публикации

METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK

Номер: US20170005041A1
Принадлежит:

The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer. 1. A method for forming an interconnect on a substrate , comprising:depositing a barrier layer on the substrate;depositing a transition layer on the barrier layer; anddepositing an etch-stop layer on the transition layer, wherein the transition layer shares a first common element with the barrier layer, and wherein the transition layer shares a second common element with the etch-stop layer.2. The method of claim 1 , wherein the barrier layer is deposited using a silicon-based precursor.3. The method of claim 1 , wherein the etch-stop layer is formed from a metal dielectric material.4. The method of claim 1 , wherein the transition layer is configured to decrease the fringing capacitance between the barrier layer and the etch-stop layer.5. The method of claim 1 , wherein the first common element shared between the transition layer and the barrier layer forms a first covalent bond between the transition layer and the barrier layer and the second common element shared between the transition layer and the etch-stop layer forms a second covalent bond between the transition layer and the etch-stop layer.6. The method of claim 5 , wherein the first covalent bond and the second covalent bond aid in saturating dangling defects between the transition layer and the etch-stop layer and the transition layer and the barrier layer.7. The method of claim 1 , wherein the barrier layer is formed from SiOC claim 1 , the transition layer is formed from SiCN claim 1 , ...

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05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20170005055A1
Автор: Suzuki Shinya
Принадлежит:

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are ...

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05-01-2017 дата публикации

OXIDE FORMATION IN A PLASMA PROCESS

Номер: US20170005108A1
Принадлежит:

A method of making and structural embodiments of a semiconductor structure are provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate, forming a charge storage layer overlying the tunneling layer, and forming a blocking structure on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described. 1. A memory transistor , comprising:a gate electrode;a blocking structure disposed beneath the gate electrode;a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer comprises a trap dense charge storage layer over a substantially trap free charge storage layer;a tunneling layer disposed beneath the multi-layer charge storage layer; anda channel region disposed beneath the tunneling layer, wherein the channel region is positioned laterally between a source region and a drain region.2. The memory transistor of claim 1 , wherein the channel region is formed in a substrate.3. The memory transistor of claim 1 , wherein the channel region is formed overlying a substrate.4. The memory transistor of claim 1 , wherein the channel region is suspended above a substrate.5. The memory transistor of claim 1 , wherein the channel region is formed perpendicular to a substrate. The present application is a continuation of U.S. application Ser. No. 14/969,468 filed Dec. 15, 2015, which is a continuation of U.S. application Ser. No. 14/562,462, filed Dec. 5, 2014, now U.S. Pat. No. 9,406,574 issued Aug. 2, 2016, which is a continuation-in-part of U.S. application no. 14/473,634, filed August 29, 2014, now abandoned, which is a continuation of U. S. application no. 13/401,712, filed February 21, 2012, now U.S. Pat. No. 8,822,349 issued Sep. 2, 2014, which is a continuation ...

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05-01-2017 дата публикации

IMPLEMENTING A HYBRID FINFET DEVICE AND NANOWIRE DEVICE UTILIZING SELECTIVE SGOI

Номер: US20170005112A1
Принадлежит:

A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer. 1. A silicon-on-insulator substrate having selectively formed regions , the silicon-on-insulator substrate comprising:a first region having an epitaxially grown silicon layer formed on a buried oxide layer, without an intervening layer, the first region serving as an active silicon region for a formation of one or more finFET devices; anda second region having an epitaxially grown silicon layer formed on a silicon-germanium layer, wherein the silicon-germanium layer is formed on the buried oxide layer and is formed by thermally annealing a deposited silicon-germanium layer, the second region serving as a designated region for a formation of one or more nanowire devices.2. The silicon-on-insulator substrate of claim 1 , wherein thermally annealing the deposited silicon-germanium layer comprises performing a thermal anneal in an oxidizing environment.3. The silicon-on-insulator substrate of claim 2 , wherein the oxidizing environment comprises one or more of: oxygen claim 2 , nitrous oxide claim 2 , or water vapor.4. The silicon-on-insulator substrate of ...

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05-01-2017 дата публикации

PATTERNING OF SILICON OXIDE LAYERS USING PULSED LASER ABLATION

Номер: US20170005206A1
Принадлежит:

Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. 1. A method of ablating an electrically insulating layer on a semiconductor substrate , said method comprising:providing a semiconductor substrate having n-type doping;depositing a first relatively thin layer of undoped glass or undoped oxide on a surface of said semiconductor substrate;depositing a first relatively thin semiconductor layer comprising a substance chosen from the group consisting of amorphous semiconductor, nanocrystalline semiconductor, microcrystalline semiconductor, and polycrystalline semiconductor on said relatively thin layer of undoped glass or undoped oxide;depositing a layer of borosilicate glass or a borosilicate/undoped glass stack on said relatively thin semiconductor layer; andselectively ablating said layer of borosilicate glass or borosilicate/undoped glass stack with a pulsed laser, said relatively thin semiconductor layer substantially protecting said semiconductor substrate from ...

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13-01-2022 дата публикации

Semiconductor device and method

Номер: US20220013364A1

An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

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07-01-2016 дата публикации

METHOD FOR SELECTIVELY DEPOSITING A LAYER ON A THREE DIMENSIONAL STRUCTURE

Номер: US20160005607A1
Принадлежит:

A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion. 1. A method , comprising:providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane;directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam;directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; andproviding a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness of the layer grown on the second portion.2. The method of claim 1 , further comprising providing the second species as reactive ions to the substrate before the directing the angled ions claim 1 , wherein the reactive ions form a sub- ...

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07-01-2016 дата публикации

ETCHING METHOD, ETCHING APPARATUS AND STORAGE MEDIUM

Номер: US20160005621A1
Принадлежит:

A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times. 1. A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by a pattern layer and stopping the etching before a base layer of the silicon oxide film is etched , the method comprising:heating the target substrate in a vacuum atmosphere;intermittently supplying, as an etching gas, at least one of a first processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a second processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit in multiple cycles.2. The method of claim 1 , wherein a time period of said supplying the etching gas to the target substrate in each cycle is about 0.5 sec to 5 sec.3. The method of claim 1 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.4. The method of claim 2 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.5. The method of claim 1 , wherein the compound of nitrogen claim 1 , hydrogen and fluorine is either NHF or NHFHF.6. The method of claim 2 , wherein the compound of nitrogen claim 2 , hydrogen and fluorine is either NHF or NHFHF.7. The method of claim 3 , wherein the compound of nitrogen claim 3 , hydrogen and fluorine is either NHF or NHFHF.8. The method of claim ...

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04-01-2018 дата публикации

SELECTIVE ATOMIC LAYER DEPOSITION WITH POST-DOSE TREATMENT

Номер: US20180005814A1
Принадлежит:

Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition are provided. Post-dose treatment operations are performed after adsorbing precursors onto the substrate to remove adsorbed precursors at the tops of features prior to converting the adsorbed precursors to a silicon-containing film. Post-dose treatments include exposure to non-oxidizing gas, exposure to non-oxidizing plasma, and exposure to ultraviolet radiation. 1. A method of processing a patterned substrate in a process chamber , the method comprising:(a) providing the patterned substrate having one or more features;(b) exposing the patterned substrate to a silicon-containing precursor under conditions allowing the silicon-containing precursor to adsorb onto surfaces of the one or more features, thereby forming an adsorbed layer of the silicon-containing precursor over the patterned substrate;(c) before exposing the patterned substrate to a reactant to form a silicon-containing film and after exposing the patterned substrate to the silicon-containing precursor, performing a post-dose treatment operation to preferentially remove the adsorbed layer at tops of the one or more features; and(d) exposing the patterned substrate to the reactant and igniting a first plasma to form the silicon-containing film over the patterned substrate.2. The method of claim 1 , wherein performing the post-dose treatment operation comprises exposing the patterned substrate to a gas selected from the group consisting of nitrogen claim 1 , argon claim 1 , hydrogen claim 1 , ammonia claim 1 , helium claim 1 , and CH claim 1 , wherein x is an integer between and including 1-5 and y is an integer between and including 4-16.3. The method of claim 2 , wherein performing the post-dose treatment operation further comprises igniting a second plasma at a plasma power less than about 6 kW.4. The method of claim 3 , wherein performing the post- ...

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04-01-2018 дата публикации

SUBSTRATE PROCESSING METHOD FOR DEPOSITING A BARRIER LAYER TO PREVENT PHOTORESIST POISONING

Номер: US20180005819A1
Принадлежит:

A method for depositing a barrier layer includes a) arranging a substrate including a nitride layer in a processing chamber; b) setting a process temperature in the processing chamber to a predetermined process temperature range; c) setting a process pressure in the processing chamber to a predetermined process pressure range; d) supplying at least one of a gas and a vapor including an organosilane precursor species; and e) depositing a barrier layer on the nitride layer. The barrier layer reduces diffusion of nitrogen-containing groups in the nitride layer into a photoresist layer that is subsequently deposited on the nitride layer. 1. A method for depositing a barrier layer , comprising:a) arranging a substrate including a nitride layer in a processing chamber;b) setting a process temperature in the processing chamber to a predetermined process temperature range;c) setting a process pressure in the processing chamber to a predetermined process pressure range;d) supplying at least one of a gas and a vapor including an organosilane precursor species; ande) depositing a barrier layer on the nitride layer,wherein the barrier layer reduces diffusion of nitrogen-containing groups in the nitride layer into a photoresist layer that is subsequently deposited on the nitride layer.2. The method of claim 1 , wherein the organosilane species includes one or more SiCHfunctional groups.3. The method of claim 1 , wherein the organosilane species has a form RSX claim 1 , wherein R includes one or more organic functional groups and X includes one or more hydrolysable functional groups that react with —OH or —H active sites on a surface of the substrate.4. The method of claim 3 , wherein the one or more hydrolysable functional groups are selected from a group consisting of primary amine groups claim 3 , secondary amine groups claim 3 , tertiary amine groups claim 3 , alcoxy groups (—OR) claim 3 , acyloxy groups (—O(CO)R) claim 3 , and halogen atoms.5. The method of claim 1 , further ...

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04-01-2018 дата публикации

COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER

Номер: US20180005820A1
Принадлежит:

A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon. 1. A method of forming a porous layer , comprising:{'sup': '2', 'coating a substrate with a composition comprising a sol-gel precursor and a mixture of discrete nanospheres in a medium that at least partially prevents assembly of said nanosphreres into supramolecular or colloidal structures, wherein said nanospheres comprising organic substance of biological origin, and wherein a variance in a size of said nanosphreres is less than 2 nm;'}drying said composition; andtreating said dried composition so as to decompose said nanospheres, thereby forming voids in said dried composition.2. The method according to claim 1 , wherein said treatment comprises calcination.3. The method of claim 2 , wherein said calcination is at a temperature of from about 300° C. to about 600° C.4. The method according to claim 1 , wherein said treating comprises applying optical radiation.5. The method according to claim 4 , wherein said optical radiation is ultraviolet radiation.6. The method according to claim 1 , further comprising passivating internal walls of said voids such that said walls are hydrophobic.7. The method according to claim 6 , wherein said passivation is by a hydrophobic primer selected from the group consisting of a hexamethyldisilazane claim 6 , a octadecyltrichlorosilane and a phenyltriethoxysilane.8. The method according to claim 1 , wherein said sol-gel precursor is an orthosilicate sol-gel precursor.9. The method according to claim 1 , wherein said silicate sol-gel precursor comprises tetraethylorthosilicate.10. The method according to claim 1 , wherein said sol-gel precursor comprises a silsesquioxane.11. The method according to claim 10 , wherein said silsesquioxane is selected from the ...

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07-01-2021 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Номер: US20210005448A1
Автор: NAKATANI Kimihiko
Принадлежит: KOKUSAI ELECTRIC CORPORATION

There is provided a technique that includes: forming a silicon oxide film having a non-stoichiometric composition on a substrate by repeating a cycle a plurality of times, the cycle including non-simultaneously performing: (a) adsorbing a pseudo catalyst on a surface of the substrate by supplying the pseudo catalyst to the substrate; (b) adsorbing silicon contained in a silicon hydride on the surface of the substrate by action of the pseudo catalyst adsorbed on the surface of the substrate by supplying the silicon hydride to the substrate; and (c) oxidizing the silicon adsorbed on the surface of the substrate by supplying an oxidizing agent to the substrate under a condition in which atomic oxygen is not generated. 1. A method of manufacturing a semiconductor device , comprising: (a) adsorbing a pseudo catalyst on a surface of the substrate by supplying the pseudo catalyst to the substrate;', '(b) adsorbing silicon contained in a silicon hydride on the surface of the substrate by action of the pseudo catalyst adsorbed on the surface of the substrate by supplying the silicon hydride to the substrate; and', '(c) oxidizing the silicon adsorbed on the surface of the substrate by supplying an oxidizing agent to the substrate under a condition in which atomic oxygen is not generated., 'forming a silicon oxide film having a non-stoichiometric composition on a substrate by repeating a cycle a plurality of times, the cycle including non-simultaneously performing2. The method according to claim 1 , wherein a ratio of the number of silicon atoms to the number of oxygen atoms in the silicon oxide film having the non-stoichiometric composition is larger than a ratio of the number of silicon atoms to the number of oxygen atoms in a silicon oxide film having a stoichiometric composition.3. The method according to claim 1 , wherein the silicon oxide film having the non-stoichiometric composition is made of a substance represented by a chemical formula SiO(where 1.5≤x≤1.9).4. The ...

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07-01-2021 дата публикации

METHOD OF FORMING A STRUCTURE ON A SUBSTRATE

Номер: US20210005449A1
Принадлежит:

The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: 1. A method of providing a structure by depositing a layer on a substrate in a reactor , the method comprising: [{'sub': 2n+2−y−z', 'in', 'y', 'z, '(1) HSXA, wherein the formula (1) compound is a cyclic compound, n=3-10, y=1 or more and up to 2n−z, z=0 or more and up to 2n−y, X is I or Br, and A is a halogen other than X;'}, {'sub': 2n+2−y−z−w', 'n', 'y', 'z', 'w, '(2) HSiXAR, wherein, n=1-10, y=1 or more and up to 2n+2−z−w, z=0 or more and up to 2n+2−y−w, w=0 or more and up to 2n+2−y−z, X is I or Br, A is a halogen other than X, and R is an organic ligand; or'}, {'sub': 2n+2−y−z−w', 'n', 'y', 'z', 'w, 'sup': II', 'II, '(3) HSiXAR, wherein, n=1-10, y=0 or more and up to 2n+2−z−w, z=0 or more and up to 2n+2−y−w, w=1 or more and up to 2n+2−y−z, X is I or Br, A is a halogen other than X, and Ris an organic ligand containing I or Br;'}], 'introducing a silicon halide precursor, wherein the silicon halide precursor has a general formulaand wherein the silicon halide comprises at least one hydrogen;introducing a reactant gas comprising one or more of oxygen, helium, and argon in the reactor;providing an energy source to create a plasma from the reactant gas to form reactive species; andusing the reactive species, forming a layer comprising silicon dioxide.2. The method according to claim 1 , wherein the reactant gas comprises less than 5000 ppm nitrogen.3. The method according to claim 1 , wherein the method comprises a PECVD process.4. The method according to claim 1 , wherein the reactant gas comprises argon.5. The method according to claim 1 , wherein a temperature within a reaction chamber of the reactor is between 25° C. and 700° C.6. The method according to claim 1 , wherein the plasma is remotely generated.7. The method according to claim 1 , wherein at least one of the silicon halide precursor and the reactant gas is pulsed to the ...

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04-01-2018 дата публикации

FORMING FINS UTILIZING ALTERNATING PATTERN OF SPACERS

Номер: US20180005898A1
Автор: Cheng Kangguo, Xu Peng
Принадлежит:

A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material. 1. A semiconductor structure , comprising:a substrate; andtwo or more fins formed in the substrate in a given pattern, each of the two or more fins having a pad layer formed on a top surface thereof and a spacer formed over a top of the pad layer;wherein the given pattern comprises alternating spacers of a first material and a second material with at least a portion of one of the spacers removed via a cut mask.2. The semiconductor structure of claim 1 , wherein a fin pitch between at least two of the fins is less than 30 nanometers.3. The semiconductor structure of claim 1 , wherein the first material comprises a nitride and the second material comprises an oxide.4. The semiconductor structure of claim 1 , wherein the substrate comprises one of bulk semiconductor and a semiconductor-on-insulator.5. The semiconductor structure of claim 1 , wherein the pad layer comprises silicon oxynitride.6. The semiconductor structure of claim 1 , wherein the pad layer comprises at least one of silicon carbide nitride claim 1 , silicon oxy carbide nitride and silicon boron carbide nitride.7. The semiconductor structure of claim 1 , wherein the first material ...

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07-01-2021 дата публикации

SiC FREESTANDING FILM STRUCTURE

Номер: US20210005469A1
Автор: Satoshi Kawamoto
Принадлежит: Admap Inc

A SiC Freestanding Film Structure capable of preventing a functional surface of a SiC Freestanding Film Structure from being affected by a film thickness and improving strength by increasing the film thickness, the SiC Freestanding Film Structure is formed by depositing a SiC layer through a vapor deposition type film formation method. The SiC layer is deposited with respect to a first SiC layer serving as a functional surface in the SiC Freestanding Film Structure. Focusing on the functional surface and a non-functional surface positioned on front and back sides of any particular portion, the functional surface has smoothness higher than that of the non-functional surface.

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07-01-2021 дата публикации

SiC FILM STRUCTURE

Номер: US20210005491A1
Автор: Satoshi Kawamoto
Принадлежит: Admap Inc

A SiC film structure for obtaining a three-dimensional SiC film by forming the SiC film in an outer circumference of a substrate using a vapor deposition type film formation method and removing the substrate, the SiC film structure including: a main body having a three-dimensional shape formed of a SiC film and having an opening for removing the substrate; a lid configured to cover the opening; and a SiC coat layer configured to cover at least a contact portion between the main body and an outer edge portion of the lid and join the main body and the lid.

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07-01-2021 дата публикации

SEMICONDUCTOR PACKAGES INCLUDING THROUGH HOLES AND METHODS OF FABRICATING THE SAME

Номер: US20210005533A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole. 1. A semiconductor package , comprising:a first wiring layer;a first semiconductor substrate on the first wiring layer;a first dielectric layer on the first semiconductor substrate;a landing pad in the first wiring layer;a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer, the through hole exposing the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole; anda mask layer on an upper lateral surface of the through hole.2. The semiconductor package of claim 1 , wherein a minimum diameter of the second hole is less than a width of the landing pad.3. The semiconductor package of claim 1 , wherein a diameter at a top end of the first hole is greater than a width of the landing pad.4. The semiconductor package of claim 1 , wherein claim 1 , when viewed in a plan view claim 1 , a diameter at a top end of the first hole exposed by the mask layer is less than a maximum diameter of the first hole.5. The semiconductor package of claim 1 , further comprising:a die on a bottom surface of the first wiring layer, the die includes a second semiconductor substrate and a second wiring layer that ...

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04-01-2018 дата публикации

FORMATION OF A SEMICONDUCTOR DEVICE WITH RIE-FREE SPACERS

Номер: US20180006030A1
Принадлежит:

A method of forming a fin-type field effect transistor (FinFET) can comprise forming at least one fin having an active region and a non-active region. Thereafter, a nitride is deposited on the fin. A dummy gate and nitride mask are formed on the fin over the nitride. Oxide spacers are formed on sidewalls of the dummy gate. The nitride is removed from the fin. Thereafter, a source region and a drain region are formed in the active region of the at least one fin. The result is a more reliable finFET without any possible pinch-off problems and fin erosion. Other embodiments are also described herein. 1. A method of forming a structure of a semiconductor device , the method comprising:forming at least one fin having an active region and a non-active region;forming a single first nitride on the fin;forming a dummy gate and nitride mask on the fin over the single first nitride, wherein the dummy gate is in contact with the single first nitride on the fin;forming oxide spacers on sidewalls of the dummy gate; andremoving the single first nitride and forming a source region and a drain region.2. The method of further comprising removing the dummy gate and nitride mask to form a trench.3. The method of further comprising forming a gate structure in the trench.4. The method of wherein forming the gate structure comprises:removing nitride covering the fin in the gate trench;depositing a high-K dielectric material in the trench; anddepositing a metal material on the dielectric material.5. The method of wherein the metal material is chosen from aluminum and tungsten.6. The method of further comprising depositing a metal liner between the high-K dielectric material and the gate metal.7. The method of further comprising performing a native oxide clean prior to forming oxide spacers.8. The method of wherein depositing the single first nitride on the fin comprises performing a nitradation in NH.9. The method of wherein the dummy gate comprises either an amorphous silicon or a ...

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04-01-2018 дата публикации

FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE

Номер: US20180006035A1
Принадлежит:

Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET. 1. A Fin Field Effect Transistor (FinFET) complementary metal oxide semiconductor (CMOS) circuit , comprising:a semiconductor substrate;a P-type FinFET comprising a first Fin formed from the semiconductor substrate and corresponding to a P-type semiconductor material (P-type) diffusion region;an N-type FinFET comprising a second Fin formed from the semiconductor substrate and corresponding to an N-type semiconductor material (N-type) diffusion region;a first single diffusion break (SDB) isolation structure formed in the first Fin on a first side of a gate of the P-type FinFET;a second SDB isolation structure formed in the first Fin on a second side of the gate of the P-type FinFET opposite of the first side of the gate of the P-type FinFET;a first double diffusion break (DDB) isolation structure formed in the second Fin on a first side of a gate of the N-type FinFET; anda second DDB isolation structure formed in the second Fin on a second side of the gate of the N-type FinFET opposite of the first side of the gate of the N-type FinFET.2. The FinFET ...

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04-01-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20180006050A1
Принадлежит: Toshiba Memory Corporation

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion. 1. A semiconductor memory device , comprising:a semiconductor pillar extending in a first direction;a first electrode extending in a second direction crossing the first direction;a second electrode provided between the semiconductor pillar and the first electrode;a first insulating film provided between the semiconductor pillar and the second electrode; anda second insulating film provided between the first electrode and the second electrode, a thin sheet portion disposed on the first electrode side, and', 'a thick sheet portion disposed on the semiconductor pillar side, a length in the first direction of the thick sheet portion being longer than a length in the first direction of the thin sheet portion., 'the second electrode including'}2. The device according to claim 1 , wherein a first layer disposed between the thin sheet portion and the first electrode and on two first-direction sides of the thin sheet portion; and', 'a second layer disposed between the first layer and the first electrode and on two first-direction sides of the first electrode., 'the second insulating film includes3. The device according to claim 2 , wherein a portion of the second layer is disposed on two first-direction sides of the first ...

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02-01-2020 дата публикации

Treatment for Adhesion Improvement

Номер: US20200006055A1
Принадлежит:

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer. 1. A method comprising:forming an opening in an insulating layer of a structure;depositing an adhesion layer in the opening;incorporating nitrogen atoms into the adhesion layer; anddepositing metal into the opening, the metal forming an interlayer interposed between a metal plug and the adhesion layer, the interlayer comprising a compound of the metal and nitrogen.2. The method of claim 1 , wherein the adhesion layer comprises non-crystalline TiN.3. The method of claim 1 , wherein the metal of the metal plug comprises Co.4. The method of claim 1 , wherein incorporating nitrogen atoms into the adhesion layer comprises applying an N/Hplasma treatment to the adhesion layer.5. The method of claim 4 , further comprising:prior to depositing the metal, soaking the structure in silane, wherein the compound includes silicon.6. The method of claim 1 , further comprising:prior to depositing the adhesion layer, depositing a metal layer in the opening; andforming a silicide.7. The method of claim 6 , wherein the adhesion layer is a nitride of the metal of the metal layer.8. The method of claim 1 , wherein the metal nitride interlayer comprises a first crystalline structure claim 1 , wherein the metal plug comprises a second crystalline structure claim 1 , and wherein the first crystalline structure and second crystalline structure have a lattice ...

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02-01-2020 дата публикации

Device and Method for High Pressure Anneal

Номер: US20200006063A1

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

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02-01-2020 дата публикации

Forming Nitrogen-Containing Layers as Oxidation Blocking Layers

Номер: US20200006065A1
Автор: Kao Wan-Yi, Ko Chung-Chi
Принадлежит:

A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen. 1. A method comprisingforming a silicon layer on a wafer;forming an oxide layer in contact with the silicon layer; and{'sub': '3', 'after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer, wherein the dielectric barrier layer comprises silicon and nitrogen.'}2. The method of further comprising claim 1 , after the annealing claim 1 , removing a portion of the silicon layer.3. The method of claim 1 , wherein the annealing is performed at a temperature in a range between about 500° C. and about 700° C. claim 1 , with an annealing duration in a range between about 20 minutes and about 40 minutes.4. The method of claim 1 , wherein the annealing is performed at a temperature in a range between about 900° C. and about 1 claim 1 ,100° C. claim 1 , with an annealing duration in a range between about 1 millisecond and about 5 milliseconds.5. The method of claim 1 , wherein the annealing is performed in a plasma-free environment.6. The method of claim 1 , wherein the forming the dielectric barrier layer comprises:conducting nitrogen atoms to penetrate through the oxide layer, wherein the nitrogen atoms are blocked by the silicon layer.7. The method of claim 1 , wherein the forming the silicon layer comprises epitaxially growing a crystalline silicon layer or depositing a polysilicon layer.8. The method of claim 1 , wherein the dielectric barrier layer has a peak nitrogen concentration between the silicon layer and the oxide layer claim 1 , and atomic percentages of ...

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07-01-2021 дата публикации

METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE

Номер: US20210005757A1
Автор: Li Wei, ZHAO ZHENYU
Принадлежит:

A method of manufacturing a thin film transistor (TFT) substrate and a TFT substrate. The method of manufacturing the TFT substrate adopts a first gate and a second gate to form a double gate structure, and uses a silicon nitride layer to form a etch stop layer. When depositing the silicon nitride layer of the etch stop layer, hydrogen atoms in the silicon nitride layer diffuse into the active layer to form a doping in the active layer. The hydrogen atoms provide a large amount of electrons as a donor, which increases an electron mobility of a channel region with low impedance and further reduces the impedance. Thus, a TFT channel series structure is formed in the channel region. A double TFT structure is realized by an ion diffusion doping, which saves costs and effectively saves space and optimizes a spatial layout in practical use. 1. A method of manufacturing a thin film transistor (TFT) substrate , comprising:{'b': '1', 'a step S of providing a substrate, forming a first gate and a second gate spaced apart from each other on the substrate, depositing a gate insulating layer on the first gate, the second gate, and the substrate, and depositing and patterning to form an active layer on the gate insulating layer and corresponding to the first gate and the second gate;'}{'b': '2', 'a step S of depositing an etch stop layer on the active layer and the gate insulating layer, the etch stop layer comprising a silicon nitride layer, when depositing the silicon nitride layer of the etch stop layer, hydrogen atoms in the silicon nitride layer diffuse into the active layer, so as to reduce impedance of the active layer; and'}{'b': '3', 'a step S of depositing and patterning to form a source and a drain on the etch stop layer.'}22. The method according to claim 1 , wherein in the step S claim 1 , the silicon nitride layer of the etch stop layer is deposited by a plasma chemical vapor deposition.31. The method according to claim 1 , wherein in the step S claim 1 , the active ...

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02-01-2020 дата публикации

IN-SITU DEPOSITION AND ETCH PROCESS AND APPARATUS FOR PRECISION PATTERNING OF SEMICONDUCTOR DEVICES

Номер: US20200006080A1
Принадлежит:

A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer. 1. A method of patterning a structure , comprising:forming a first material layer, a second material layer, and a photoresist layer over a substrate;lithographically patterning the photoresist layer;forming a patterned second material layer by transferring a pattern in the photoresist layer through the second material layer using a first anisotropic etch process;depositing a conformal spacer layer over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus;forming spacer films by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus; andanisotropically etching portions of the first material layer located between the substrate and bottom surfaces of the spacer films using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus.2. The method of claim 1 , wherein a combination of the substrate claim 1 , the first material layer claim 1 , and the second material layer remain in the in-situ deposition ...

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02-01-2020 дата публикации

PATTERNING METHOD FOR SEMICONDUCTOR DEVICE AND STRUCTURES RESULTING THEREFROM

Номер: US20200006082A1
Автор: Su Yi-Nien
Принадлежит:

An embodiment method includes patterning a tin oxide layer to define a plurality of mandrels over a target layer; depositing a spacer layer over and along sidewalls of the plurality of mandrels; and patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels. The method further includes after patterning the spacer layer, removing the plurality of mandrels. The method further includes after removing the plurality of mandrels, patterning the target layer using the plurality of spacers. 1. A method comprising:patterning a tin oxide layer to define a plurality of mandrels over a target layer;depositing a spacer layer over and along sidewalls of the plurality of mandrels;patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels;after patterning the spacer layer, removing the plurality of mandrels; andafter removing the plurality of mandrels, patterning the target layer using the plurality of spacers.2. The method of claim 1 , wherein patterning the tin oxide layer comprises a dry etching process using a gaseous etchant claim 1 , wherein hydrogen as a reactive component of the gaseous etchant.3. The method of claim 2 , wherein the gaseous etchant comprises HBr claim 2 , H claim 2 , NH claim 2 , or a combination thereof.4. The method of claim 2 , wherein the dry etching process further comprises using a process gas comprising argon claim 2 , nitrogen claim 2 , or combinations thereof.5. The method of claim 1 , wherein patterning the tin oxide layer comprises a dry etching process using a gaseous etchant claim 1 , wherein chlorine as a reactive component of the gaseous etchant.6. The method of claim 1 , wherein removing the plurality of mandrels comprises reducing a height of the plurality of spacers without removing the plurality of spacers.7. The method of claim 1 , wherein the spacer layer comprises AlO claim 1 , AlN claim 1 , AlON claim 1 , TaN claim 1 , TiN claim 1 , TiO ...

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03-01-2019 дата публикации

Three-dimensional Vertical NOR Flash Thin-Film Transistor Strings

Номер: US20190006009A1
Автор: Harari Eli
Принадлежит: SUNRISE MEMORY CORPORATION

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings. 1. A memory structure , comprising:a storage transistor having a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of data stored therein;a word line connected to the gate terminal to provide a control voltage during a read operation;a bit line connecting the first drain or source terminal to data detection circuitry; anda source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.2. The memory structure of claim 1 , further comprising a pre-charge transistor for charging the capacitance to a predetermined voltage prior to the ...

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02-01-2020 дата публикации

Methods of Sealing Openings, and Methods of Forming Integrated Assemblies

Номер: US20200006113A1
Автор: YANG Guangjun
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening. 132-. (canceled)33. A method of forming an integrated assembly , comprising: 'covering an upper portion of the opening with a sealant material and leaving a lower portion of the opening empty.', 'providing a construction having an opening between a pair of spaced structures; and'}34. The method of wherein the covering comprises providing a mass of material on at least one of the pair of structures and processing the mass of material to form the sealant material.35. The method of further comprising treating the sealant material to fill any pinholes present in the sealant material.36. The method of wherein the covering comprises providing a mass of material adjacent the opening and processing the mass of material to form the sealant material.37. The method of wherein the covering comprises providing a mass of material and sputtering particles from the mass of material to form the sealant material.38. The method of wherein the providing and the sputtering are performed simultaneously.3942322. The method of wherein the providing and the sputtering are conducted within a reaction chamber in the presence of chemical species which include SiCl together with one or more of O claim 38 , O claim 38 , HO.40. The method of wherein the sputtering occurs after the providing.41. The method of wherein the mass of material comprises one or more elements selected from group 14 of the periodic table.42. The method of wherein the mass of material comprises one or more elements selected from group 14 of the periodic ...

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02-01-2020 дата публикации

Methods for Improving Interlayer Dielectric Layer Topography

Номер: US20200006152A1
Принадлежит:

Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region. 1. A method comprising:forming a first contact etch stop layer over a first region of a wafer, wherein a first topography variation exists between the first region and a second region of the wafer and the first contact etch stop layer has a first thickness;forming a second contact etch stop layer over the second region of the wafer, wherein the second contact etch stop layer has a second thickness that is different than the first thickness to reduce the first topography variation to a second topography variation between the first region and the second region; andforming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.2. The method of claim 1 , wherein the second topography variation is a difference in a height of a topmost surface of the first contact etch stop layer in the first region and a height of a topmost surface of the second contact etch stop layer in the second region claim 1 , wherein the difference is less than or equal to about 10%.3. The method of claim 1 , wherein: depositing the first ...

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03-01-2019 дата публикации

GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICE

Номер: US20190006184A1
Принадлежит:

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum. 1. A gallium nitride based semiconductor device , comprising:a gallium nitride based semiconductor layer of a first conductivity type;an insulating layer that is provided on the gallium nitride based semiconductor layer and includes a metal element; anda transition layer that is provided in the vicinity of a boundary between the gallium nitride based semiconductor layer and the insulating layer and is constituted of elements of the gallium nitride based semiconductor layer and of the insulating layer, whereinwhen a thickness of the transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm:(i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to an atomic composition of nitrogen element at a position on the gallium nitride based semiconductor layer side sufficiently away from the transition layer, anda depth position on the gallium nitride based semiconductor layer side at which an atomic composition of the metal element constituting the insulating layer is ½ ...

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03-01-2019 дата публикации

Production of semiconductor regions in an electronic chip

Номер: US20190006229A1
Автор: Franck Julien
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

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03-01-2019 дата публикации

METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS

Номер: US20190006232A1
Принадлежит:

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions. 1. An integrated circuit product , comprising:a first layer of insulating material comprising a first insulating material positioned above a device layer of a semiconductor substrate, the device layer comprising transistors;a metallization blocking structure positioned in an opening in the first layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material;a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure; anda conductive metallization line comprising first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure, wherein the conductive metallization line has a long axis extending along the first and second portions.2. The product of claim 1 , wherein the first insulating material and the second insulating material are selectively etchable relative to one another.3. The product of claim 1 , wherein the first insulating material comprises silicon and oxygen ...

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03-01-2019 дата публикации

POLYSILICON STRUCTURE INCLUDING PROTECTIVE LAYER

Номер: US20190006359A1
Принадлежит:

A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers. 1. A manufacture , comprising:a substrate comprising a first portion and a second portion;a first polysilicon structure over the first portion of the substrate;a second polysilicon structure over the second portion of the substrate;two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion; anda protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.2. The manufacture of claim 1 , wherein the two spacers are L-shaped spacers.3. The manufacture of claim 1 , further comprising:a static random access memory (SRAM) cell comprising the second polysilicon structure and the two spacers.4. The manufacture of claim 1 , further comprising:a one-time-programmable (OTP) device comprising the first polysilicon structure.5. The manufacture of claim 1 , wherein the protective layer comprises silicon oxide.6. The manufacture of claim 1 , further comprising another two spacers on opposite sidewalls of the first ...

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03-01-2019 дата публикации

High-Dielectric Constant Capacitor Structures on III-V Substrates

Номер: US20190006459A1

A semiconductor structure includes a III-V semiconductor structure; a first electrode; a first barrier layer disposed over the first electrode; a first adhesion layer disposed over the first electrode; a first passivation layer disposed over the first adhesion layer; a dielectric layer disposed over the first passivation layer; a second passivation layer disposed over the dielectric layer; a second adhesion layer disposed over the second passivation layer; a second barrier layer disposed over the second adhesion layer; and a second electrode disposed over the second barrier layer.

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03-01-2019 дата публикации

METAL OXIDE SEMICONDUCTOR (MOS) CONTROLLED DEVICES AND METHODS OF MAKING THE SAME

Номер: US20190006505A1
Принадлежит:

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs. 2. The semiconductor device of claim 1 , wherein the second average thickness is greater than the first average thickness.3. The semiconductor device of claim 2 , wherein the source/emitter region comprises:an inner region contiguous with the channel region underlying the central region of the oxide layer and an outer region contiguous with the inner region opposite the channel region and underlying the first or second peripheral region of the oxide layer;wherein the inner region and the outer region have different implant species, different implant levels and/or different levels of implantation induced damage.4. The semiconductor device of claim 1 , wherein the first average thickness is greater than the second average thickness and the oxide layer has a third average thickness in the first and second outer peripheral regions claim 1 , wherein the third average thickness is greater than the second average thickness by at least 25%.5. The semiconductor device of claim 1 , wherein ...

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02-01-2020 дата публикации

Method for manufacturing isolation structure for ldmos

Номер: US20200006529A1
Автор: Guipeng Sun, Shukun QI
Принадлежит: CSMC Technologies Fab2 Co Ltd

Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

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02-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200006530A1
Принадлежит:

In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions. 1. A method comprising:growing a semiconductor layer on a substrate, the substrate comprising silicon, the semiconductor layer comprising silicon germanium;etching trenches in the semiconductor layer and the substrate to form a fin from portions of the semiconductor layer and substrate between the trenches;performing a hydrogen radical treatment process on a top surface and sides of the fin, a silicon concentration of the fin at the top surface and the sides of the fin being decreased after the hydrogen radical treatment process; andforming a metal gate stack along the top surface and the sides of the fin.2. The method of claim 1 , wherein performing the hydrogen radical treatment process comprises:{'sub': '2', 'dispensing a gas source comprising a first gas and a second gas on the top surface and the sides of the fin, the first gas being H, the second gas being an inert gas; and'}generating a hydrogen plasma to convert the first gas into hydrogen radicals.3. The method of claim 2 , wherein performing the hydrogen radical treatment process ...

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03-01-2019 дата публикации

Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures

Номер: US20190006520A1
Автор: Hopkins John D.
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures. 1. A memory device , comprising:a stack of alternating electrically conductive levels and electrically insulative levels over a material comprising tungsten silicide;electrically insulative pillars that extends through the stack and contact an upper surface of the material comprising tungsten silicide;a channel material post between a first adjacent pair of the pillars, the channel material post extending through the material comprising tungsten silicide and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;gate dielectric material and charge-storage material between edges of the electrically conductive levels and the channel material post.2. The memory device of claim 1 , further comprising charge blocking material ...

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02-01-2020 дата публикации

Integrated Circuits with Channel-Strain Liner

Номер: US20200006558A1
Принадлежит:

Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain. 1. An integrated circuit device comprising:a substrate;a fin extending from the substrate;a gate disposed on the fin and having a bottom portion disposed towards the fin and a top portion disposed on the bottom portion; anda liner disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner.2. The integrated circuit device of claim 1 , wherein the liner is configured to produce a channel strain.3. The integrated circuit device of claim 1 , wherein the liner has a height that is between about 1/100 and about ⅘ of a height of the gate.4. The integrated circuit device of claim 1 , wherein a majority of the gate is free of the liner.5. The integrated circuit device of claim 1 , wherein:the substrate includes a first region with a first device having a first channel type and a second region with a second device having a second channel type;the first region includes the liner; andthe second region is free of the liner.6. The integrated circuit device of claim 1 , wherein the fin includes a source/drain feature and the liner is disposed on the source/drain feature.7. The integrated circuit device of further comprising an etch stop layer disposed between the liner and the side surface of the bottom portion of the gate.8. The integrated circuit device of further comprising an inter-level dielectric layer disposed on the liner claim 7 , wherein ...

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08-01-2015 дата публикации

NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR PRODUCING NON-VOLATILE SEMICONDUCTOR MEMORY

Номер: US20150008500A1
Принадлежит:

A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate. 1. A non-volatile semiconductor memory comprising:a silicon substrate;a first silicon oxide film;a second silicon oxide film;a first silicon nitride film; anda second silicon nitride film, whereinthe first silicon oxide film is layered on the silicon substrate,the first silicon nitride film is layered on the first silicon oxide film,the second silicon oxide film is layered on the first silicon nitride film, andthe second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate.2. A non-volatile semiconductor memory comprising:a silicon substrate;a first silicon oxide film;a second silicon oxide film;a third silicon oxide film;a first silicon nitride film; anda second silicon nitride film, whereinthe first silicon oxide film is layered on the silicon substrate,the first silicon nitride film is layered on the first silicon oxide film,the second silicon oxide film is layered on the first silicon nitride film,the third silicon oxide film has a thickness that is smaller than that of the first silicon oxide film, andthe second silicon nitride film has a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon ...

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12-01-2017 дата публикации

Furnace-type semiconductor apparatus, method of cleaning the same, and method of forming thin film using the same

Номер: US20170008042A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Embodiments of the inventive concepts provide a method of cleaning a furnace-type semiconductor apparatus that is equipped in a clean room and includes a process chamber in which a process of forming a thin film is performed on a substrate. The method includes supplying air of the clean room into the process chamber after the process of forming the thin film, and thermally treating an inside of the process chamber using the air of the clean room supplied to the inside of the process chamber. An adhered material containing chlorine is formed on an inner surface of the process chamber by the process of forming the thin film, and the chlorine of the adhered material is removed by the thermal treatment of the inside of the process chamber.

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20-01-2022 дата публикации

DEFECTIVE CHIP PROCESSING METHOD

Номер: US20220020650A1
Автор: Greenlaw David
Принадлежит:

When a chip, or manufactured integrate circuit, is found to have a portion that is defective, “floorsweeping” may be used to salvage the working portion of the chip. Floorsweeping involves downgrading, or turning off, the portion of the chip with the defect and then operating the remaining portion of the chip as a lower quality chip than the larger chip that was originally intended. In use, applications will then only use the active portion of the chip. However, the resulting lower quality chip will still have the same static leakage of the larger, non-defective chip. This leakage results from a voltage still being applied to the entire area of the larger chip, even though a portion of that area has been downgraded. The present disclosure provides a method for processing defective chips to form a smaller chip that avoids the excess static leakage associated with floorsweeping by physically removing the defective portion of the chip. 1. A method , comprising:identifying a defective portion of a chip;physically cutting the defective portion of the chip away from a working portion of the chip;polishing a cut side of the working portion of the chip.2. The method of claim 1 , wherein the chip is a graphics processing unit (GPU).3. The method of claim 1 , wherein the chip includes repeating sub-blocks.4. The method of claim 3 , wherein the defective portion of the chip includes one or more neighboring sub-blocks of the repeating sub-blocks.5. The method of claim 1 , wherein the defective portion of the chip is identified from results of testing of the chip.6. The method of claim 1 , wherein physically cutting the defective portion of the chip away from the working portion of the chip includes making at least one of a vertical laser cut or a horizontal laser cut through the chip.7. The method of claim 6 , wherein the at least one of the vertical laser cut or the horizontal laser cut is made in a lane existing between the defective portion of the chip and the working ...

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08-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20150011049A1
Принадлежит:

An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method. 1. (canceled)2. A method for manufacturing a semiconductor device , comprising the steps of:forming an oxide semiconductor layer comprising indium and zinc over a substrate;heating the oxide semiconductor layer at 200° C. or higher under a nitrogen atmosphere;forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer after the heating step; andforming an insulating film comprising silicon and oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,wherein the insulating film is in contact with part of the oxide semiconductor layer.3. The method according to claim 2 , further comprising a step of forming a gate electrode layer over the substrate.4. The method according to claim 3 , further comprising a step of forming a gate insulating layer over the gate electrode layer.5. The method according to claim 2 , wherein the insulating film is a silicon oxide film.6. The method according to claim 2 , wherein the part of the oxide semiconductor ...

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08-01-2015 дата публикации

BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY

Номер: US20150011050A1
Принадлежит:

Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. 119-. (canceled)20. A method , comprising:forming a sacrificial layer on a surface of a bridge substrate comprising a glass, ceramic, or a semiconductor material;forming an electrically conductive layer on the sacrificial layer, the electrically conductive layer being coupled with the surface of the bridge substrate through the sacrificial layer by an electrically conductive material; andremoving material of the sacrificial layer to provide an air gap between the surface of the bridge substrate and the electrically conductive layer.21. The method of claim 20 , further comprising:prior to forming the sacrificial layer, forming electrical routing features through the bridge substrate and on the surface of the bridge substrate, the electrical routing features including through-hole vias, traces, and pads.22. The method of claim 20 , wherein forming the sacrificial layer comprises depositing silicon oxide (SiO).23. The method of claim 21 , further comprising:prior to forming the electrically conductive layer, forming openings in the sacrificial layer to expose one or more of the electrical routing features; ...

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11-01-2018 дата публикации

SINGLE ALD CYCLE THICKNESS CONTROL IN MULTI-STATION SUBSTRATE DEPOSITION SYSTEMS

Номер: US20180010250A1
Принадлежит:

Disclosed are methods of depositing films of material on multiple semiconductor substrates in a multi-station processing chamber. The methods may include loading a first set of one or more substrates into the processing chamber at a first set of one or more process stations and depositing film material onto the first set of substrates by performing N cycles of film deposition. Thereafter, the methods may further include transferring the first set of substrates from the first set of process stations to a second set of one or more process stations, loading a second set of one or more substrates at the first set of process stations, and depositing film material onto the first and second sets of substrates by performing N′ cycles of film deposition, wherein N′ is not equal to N. Also disclosed are apparatuses and computer-readable media which may be used to perform similar operations. 1. A multi-station substrate processing apparatus for performing atomic layer deposition to deposit films of material on multiple semiconductor substrates , the apparatus comprising:a processing chamber;a first set of one or more process stations contained in the processing chamber, each having a substrate holder;a second set of one or more process stations contained in the processing chamber, each having a substrate holder;one or more valves for controlling flow of film precursor to the process stations;a valve-operated vacuum source for removing film precursor from the volumes surrounding the process stations contained in the processing chamber;a substrate loading device for loading substrates into the processing chamber at one or more of the process stations;a substrate transferring device for transferring one or more substrates from the first set of process stations to the second set of process stations; (a) loading a first set of one or more substrates into the processing chamber at the first set of process stations;', '(b) depositing film material onto the first set of substrates at ...

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09-01-2020 дата публикации

HYDRIDOSILAPYRROLES, HYDRIDOSILAAZAPYRROLES, METHOD FOR PREPARATION THEREOF, AND REACTION PRODUCTS THEREFROM

Номер: US20200010488A1
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Hydridosilapyrroles and hydridosilaazapyrrole are a new class of heterocyclic compounds having a silicon bound to carbon and nitrogen atoms within the ring system and one or two hydrogen atoms on the silicon atom. The compounds have formula (I): 2. The hydridosilapyrrole or hydridosilaazapyrrole according to claim 1 , wherein R is an alkyl claim 1 , aryl claim 1 , ester claim 1 , chiral phenethylamine claim 1 , trimethylsilyl claim 1 , or tertiary amine group.3. The hydridosilapyrrole or hydridosilaazapyrrole according to claim 1 , wherein the hydridosilapyrrole is N-butyl-2-silapyrrole.4. The hydridosilapyrrole or hydridosilaazapyrrole according to claim 1 , wherein the hydridosilapyrrole is N-(3-dimethylaminopropyl)-2-silapyrrole.5. The hydridosilapyrrole or hydridosilaazapyrrole according to claim 1 , wherein the hydridosilapyrrole is (N-trimethylsilyl-2-methyl-silapyrrole). This application is a divisional of co-pending U.S. patent application Ser. No. 15/728,606, filed Oct. 10, 2017, which is a divisional of U.S. patent application Ser. No. 15/176,703, filed Jun. 8, 2016, now U.S. Pat. No. 9,815,858, issued Nov. 14, 2017, which claims priority to U.S. Provisional Application No. 62/180,351, filed Jun. 16, 2015, the disclosures of which are herein incorporated by reference in their entireties.There is currently a great deal of interest in molecular layer deposition for nano-featured devices, including semiconductors and microelectromechanical systems (MEMS). Rapid and preferably quantitative deposition of single molecular layers with a minimum of byproducts is desirable. Silicon carbonitride films are of particular interest for a variety of dielectric, passivation and etch-stop applications.Examples of known systems to produce silicon nitride or silicon carbonitride films include that described in U.S. Pat. No. 4,200,666 using trisilylamine ((SiH)N) and an inert gas with optional ammonia; the system of diethylsilane and ammonia in an LPCVD system at 800° C. as ...

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