СПОСОБ И УСТРОЙСТВО ДЛЯ ПЕРЕДАЧИ И ПРИЕМА РАДИОСИГНАЛОВ ПО ТЕХНОЛОГИИ ВНУТРИПОЛОСНОЙ ПЕРЕДАЧИ ПО ОДНОМУ КАНАЛУ, ВКЛЮЧАЮЩЕЙ В СЕБЯ КОДИРОВАНИЕ НА ОСНОВЕ КОМПЛЕМЕНТАРНОГО РАЗРЕЖЕННОГО КОНТРОЛЯ ПО ЧЕТНОСТИ

Изобретение относится к способам и устройствам передачи и приема радиосигналов. Технический результат заключается в повышении эффективности обработки цифровой информации. В способе принимают множество информационных битов, представляющих аудиоинформацию и/или данные, кодируют информационные биты с использованием кодирования на основе комплементарного разреженного контроля по четности (CLDPC), чтобы формировать составное кодовое слово и множество независимо декодируемых кодовых полуслов, представляющих собой блочный код половинного размера на каждой боковой полосе частот, причем комплементарный разреженный контроль по четности обеспечивает комплементарные свойства пары кодовых полуслов, содержащих составное кодовое CLDPC-слово, модулируют по меньшей мере один несущий сигнал с кодовыми битами кодовых полуслов и передают несущий сигнал(ы). 5 н. и 34 з.п. ф-лы, 17 ил.

ПЕРЕСТАНОВОЧНЫЙ ДЕКОДЕР С ОБРАТНОЙ СВЯЗЬЮ

Изобретение относится к технике связи и может использоваться при проектировании новых и модернизации существующих систем обмена данными. Техническим результатом является сокращение объема памяти для хранения эталонных матриц. Перестановочный декодер с обратной связью содержит: блок приема, блок мягких решений символов, преобразователь мягких решений, блок упорядочения оценок, блок эквивалентного кода, блок сравнения и обратных преобразований, блок исправления стираний, при этом дополнительно введены блок ранжирования перестановок, блок отрицательных перестановок, блок ввода отрицательных перестановок, блок положительных перестановок, блок быстрых матричных преобразований, блок усреднения мягких решений и блок сигналов обратной связи. 3 ил., 2 табл.

НОСИТЕЛЬ ЗАПИСИ, ИМЕЮЩИЙ СТРУКТУРУ ДАННЫХ ДЛЯ УПРАВЛЕНИЯ, ПО КРАЙНЕЙ МЕРЕ, ОБЛАСТЬЮ ДАННЫХ НОСИТЕЛЯ ЗАПИСИ, И СПОСОБЫ И УСТРОЙСТВА ЗАПИСИ И ВОСПРОИЗВЕДЕНИЯ

Структура данных на носителе записи включает временную зону управления дефектами, в которой хранится блок данных. Блок данных включает информацию о записи и временную информацию о состоянии носителя записи. Информация о записи предоставляет информацию о зонах непрерывной записи в области данных носителя записи. Временная информация о состоянии носителя записи предоставляет информацию о состоянии носителя записи и содержит, по крайней мере, один указатель информации во временной зоне управления дефектами. Технический результат: оптимизация управления дефектами при помощи информации о состоянии носителя записи. 5 н. и 26 з.п. ф-лы, 6 ил.

СПОСОБ И УСТРОЙСТВО ДОСТУПА К ДАННЫМ

Изобретение относится к области информационных технологий. Технический результат заключается в уменьшении потери данных и сокращении времени прерывания доступа, когда данные успешно не считываются. В способе при получении запроса на считывание данных для группы первых дисков осуществляют перенос адреса считывания; определение диапазона местоположений первой полосы группы первых дисков согласно адресу считывания; последовательное считывание данных из первых полос в пределах диапазона местоположений первой полосы, задание результата считывания данных для первой полосы, данные которой успешно не считываются, как предварительно установленных дополняющих данных, осуществляют продолжение считывания данных из следующей первой полосы до тех пор, как данные не будут считаны из всех первых полос. Осуществляют возврат результата считывания данных для каждой первой полосы. 2 н. и 12 з.п. ф-лы, 12 ил.

СПОСОБ ЗАПИСИ И ЗАПИСЫВАЮЩИЙ АППАРАТ ДЛЯ ЗАПОМИНАЮЩЕГО УСТРОЙСТВА

Изобретение относится к вычислительной технике. Технический результат заключается в предотвращении ошибки при записи, вызываемой константной неисправностью в импедансном запоминающем устройстве. Способ записи, предназначенный для запоминающего устройства, в котором получают n численных значений, которые должны быть записаны; определяют n битов, соответствующих этим n численным значениям, которые должны быть записаны, и информацию о константных неисправностях, содержащихся в этих n битах; группируют эти n битов в В групп битов способом группирования путем регулирования интервала между двумя смежными битами в одной и той же группе, так, чтобы В групп битов удовлетворяли группировочному условию, и, в случае, когда эти n битов представляют двухмерный массив, состоящий из В строк и А столбцов, любые два бита, которые принадлежат к одной и той же группе, находились в различных строках и столбцах или в одной и той же строке; и соответственно записывают эти n численных значений в соответствии с ...

НОСИТЕЛЬ ЗАПИСИ, ИМЕЮЩИЙ СТРУКТУРУ ДАННЫХ ДЛЯ УПРАВЛЕНИЯ, ПО КРАЙНЕЙ МЕРЕ, ОБЛАСТЬЮ ДАННЫХ НОСИТЕЛЯЗАПИСИ, И СПОСОБЫ И УСТРОЙСТВА ЗАПИСИ И ВОСПРОИЗВЕДЕНИЯ

... 1. Носитель записи, имеющий структуру данных для управления областью данных носителя записи, содержащий временную зону управления дефектами, в которой хранится первый блок данных, причем первый блок данных включает в себя информацию о последовательной записи и временную структуру определения, информация о последовательной записи предоставляет информацию о зонах непрерывной записи в области данных носителя записи, а временная структура определения содержит, как минимум, один указатель информации во временной зоне управления дефектами. 2. Носитель записи по п.1, в котором первый блок данных имеет размер, как минимум, один кластер. 3. Носитель записи по п.2, в котором один сектор первого блока данных отдано временной структуре определения, и не больше чем 31 сектор первого блока данных отданы информации о последовательной записи. 4. Носитель записи по п.3, в котором первый сектор информации о последовательной записи расположен рядом с временной структурой определения. 5. Носитель записи по ...

ПЕРЕСТАНОВОЧНЫЙ ДЕКОДЕР С ПАМЯТЬЮ

FEHLERPRUEFANORDNUNG FUER EINE DATENVERARBEITENDE MASCHINE

Error correction in digital communication or storage system - involves stepwise computation of sets of coeffts. from syndromes of block data multiplication by equality matrix

Four syndromes of n received words are calculated by a syndrome computer (120) for use in prodn. of two sets of coeffts. (130,140) and an error site value (150). Actual error sites are found from the computed site values and applied to an error value computer (180). The number of errors is obtd. from a discriminator (160). The error site value computer (150) uses Exclusive-OR logic to solve a set of eight simultaneous equations related to the coeffts. of the second set (140). ADVANTAGE - Erroneous values can be detected in shorter computation time by simplified circuit.

VERFAHREN UND VORRICHTUNG ZUR KENNZEICHNUNG VON DATENFELDERN

ZENTRALPROZESSOR MIT DUPLIZIERTEN BASISVERARBEITUNGSEINHEITEN

Anwenderschnittstellenprozessor für Rechnernetz.

Fehlertolerantes Datenverarbeitungssystem

PARITÄTS-UND HOCHGESCHWINDIGKEITSNORMIERUNGSKREIS FÜR EIN MASSIVPARALLELES VERARBEITUNGSSYSTEM

Eingang-/Ausgangsteuerungseinrichtung

Netzwerkteilnehmer

PARALLELPROZESSOR MIT BINÄRER BAUMSTRUKTUR.

Schaltungsanordnung zur Korrektur von faelschlich versetzt auftretenden Impulsen in Datenuebertragungseinrichtungen fuer elektronische Rechenanlagen

Paritaetspruefschaltung fuer ein sowohl rein binaer als auch binaer-dezimal arbeitendes Addierwerk

VERFAHREN UND EINRICHTUNG ZUR FEHLERPRUEFUNG FUER EINE GRUPPE VON KONTROLLOGIKEINHEITEN

SCHALTUNGSANORDNUNG ZUR SELBSTPRUEFENDEN PARITAETSPRUEFUNG FUER ZWEI ODER MEHR VONEINANDER UNABHAENGIGE DATENKANAELE

SPEICHEREINHEIT ZUM PROTOKOLLIEREN VON DATEN

Verfahren zur Synchronisation zweier zentraler Verarbeitungseinheiten für Duplex-Lock-Step-Operationen

Detecting key corruption

Disturbed data storage and recovery

VITAL PROCESSOR V

PROCESSING DATA

Parity checking

A parity check circuit comprises a plurality of logic gates IC7-, IC8-, IC9- connected to a plurality of data inputs A0, D6-D7 for monitoring the parity status thereof and including at least one test signal input for receiving a recurring test signal (from IC14d or IC16) to cause a change in the parity check status at IC9c if a gate is inoperative. ...

PROCESSING DATA

Generating databases.

A reference database storage structure is generated from a plurality of data field memory structures. The process involves generation of a general source code module into which text in the desired language is inserted before the source code is subsequently compiled. Insertion of text in the desired language involves retrieving a text code and using it to access a translation database. In parallel with generation of source code modules, the method involves generation of error detection code which automatically generates a breakpoint data file indicating program pointers and memory contents when a non-serious error occurs. A modified reference storage structure may be compared with the previous reference structure and the differences automatically used to update existing databases based on the previous reference structure. ...

Binary data error correction using hint signal

An error detection and correction method and apparatus is described which permits the correction of double errors using a (15, 11) Hamming code and a parity bit. The Hamming code and parity bit allows the detection of double errors. A modulated waveform carrying the binary data is examined for anomalies such as noise pulses. A hint signal is generated based on the anomalies which points to a suspect bit. The state of this bit is changed to correct for double errors. ...

Data processing systems

VITAL PROCESSOR IV

A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if ...

Processing data

Method and apparatus for processing data wherein control dependency on a host computer during data recording/ reproduction is lowered through use of an external controller 10 with the aid of a simple program, and an error correction method wherein the error correction capability for burst errors may be improved. Commands from the host computer are held in a register in the controller and interpreted, 12, as microprograms. An error correction processor 13 handles double-encoded interleaved data.

METHOD FOR PROCESSING DATA

Error detection in data transfer by comparing expected and actual identifiers

A method of data transfer in a data processing system having at least one source buffer and at least one destination buffer. The source buffer includes a plurality of data blocks, each data block having an address and being for storage of data including an identifier uniquely identifying that data block. The destination buffer includes a plurality of data blocks corresponding to the data blocks of the source buffer, each destination block having an address and being for storage of data. Each source block identifier is a function of a corresponding destination block address. Transferring data from the source buffer to the destination buffer includes: (a) obtaining the address of a data block in the destination buffer to transfer data into; (b) obtaining the address of a corresponding data block in the source buffer to transfer data from; and (c) checking the integrity of said addresses before data transfer, including: (i) retrieving the source block identifier in the source block via the ...

A METHOD FOR CHECKING THE RELIABILITY OF A MEMORY FOR A RECEIVING DATA PACKET IN A DATA ARRAY WITHIN A DATA RECEIVING LOGIC CIRCUIT

Data storage and transmission using parity data

A method of storing or transmitting data comprises separating the data, such as a web page, into a plurality of data subsets. Parity data is then generated from the plurality of data subsets (e.g. using XOR) such that any one or more of the plurality of data subsets may be recreated from the remaining data subsets and the parity data. These steps are then repeated on any one or more of the plurality of data subsets and parity data providing further data subsets and further parity data. Each of the further data subsets and further parity data are stored in separate storage locations or transmitted. This system ensures that if data on a particular device is lost, it may be recreated from the data sets stored in separate locations.

Apparatus for checking coded information

... 1,066,038. Parity check bits for digital data. OLYMPIA WERKE A.G. Nov. 26, 1963 [Dec. 12, 1962], No. 46644/63. Heading G4A. Apparatus for producing a parity check bit for a binary word such as fedcba comprises three pairs of AND gates 16-21, gate 16 receiving f and e, gate 17 receiving f and e, the other gates receiving corresponding inputs, each pair of gates being connected to a separate OR gate 29-31 the output of the OR gates A, B, C being connected to an inverter 35-37 the output and the inverted output being applied to further AND and OR gates to produce an appropriate parity bit. As shown, four further AND gates 53 to 56 and one OR gate 57 are provided. Gate 53 has as input A, B, C, gates 54 has input B, C, A, gate 55 has C, A, B and gate 56 has A, B, C. Thus a parity bit output is produced if an even number of bits or no bits are present in the said word. A further circuit (Fig. 3, not shown) is described for use with a sevenbit word, the circuit of Fig. 2 being combined with further ...

Data processing system

An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally 20 to the southernmost element of the neighbouring group, via a respective switch 22 so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction. ...

Method and apparatus for using cache memory in a system that supports a low power state

A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

A dirty memory using redundant entries indicating that blocks of memory associated with the entries have been written to

A dirty memory subsystem includes storage operable to store redundant copies of dirty indicators. Each dirty indicator is associated with a respective block of main memory and is settable to a predetermined state to indicate that the block of main memory associated therewith has been dirtied. By providing redundant storage for the dirty indicators, any difference between the stored copies of the dirty indicators can be considered as indicative of memory corruption, for example as a result of a cosmic ray impact. As the different copies can be stored in different locations, it is unlikely that a cosmic ray impact would affect all copies equally. If a difference between the stored copies is detected, then the dirty indicator can be take as being unreliable and remedial action can be taken. Such a memory finds application in a method of managing reinstatement of an equivalent memory state in the main memory of a plurality of processing sets of a fault tolerant computer following a lock step ...

Storage system comprising a controller which performs a read-after-write check

Fault tolerant parity generation

Monitoring the Transmission of Digital Data

... 1,188,228. Digital transmission systems. SIEMENS A.G. 27 Sept., 1968 [28 Sept., 1967], No. 46158/68. Heading H4P. [Also in Division G4] A process for testing a transmission path comprises transmitting data through the path, the data comprising a word having free bitlocations. A predetermined one of the free bit-locations is supplied with a parity bit. At least one check unit downstream of that supply checks the word on the basis of the parity bit and produces a further parity bit which is entered into a further free bit-location of the word. Devices 1 such as analog/digital converters or pulse counters supply data to an input device 2. The data can be supplied with a parity bit or have one supplied at the input device. A check unit 6 is used to check the word against the parity bit and to insert a further bit to maintain the parity, the further bit being introduced into a predetermined location. The data is then passed, via multiplexors and decoders if required, to a device controlling ...

Distributed data storage and recovery

Method and apparatus for receiving a transmitted data packet with accompanying parity data. Data is split into components of data (subset A, Subset B) with associated parity data P; each component and the associated parity data is split into respective subsets (AA, AB; BA, BB; PA, PB) with associated further parity data (AP, BP, PP) The subsets are received over separate transmission channels C1-C9. The receiver is then able to use the parity data to correct any transmission errors that have occurred, either by using the associated further parity data generated from the missing subset, or by using the relevant subset of the associated parity data generated from the components. The parity function may be XOR, exclusive or. There may be multi-dimensional parity eg. 2 dimensional parity or 3 dimensional parity.

ERROR DETECTION CIRCUIT

DATA COMMUNICATION MODULE FOR THE SUPPLY OF ERROR TOLERANCE AND INCREASED STABILITY

SYSTEM AND PROCEDURE FOR THE INFORMATION CODING IN THE FORM OF GEOMETRICAL SYMBOLS

PROCEDURE FOR THE ERROR CORRECTION IN MBC FLASHSPEICHER

COPY BAKING OPTIMIZATION FOR A MEMORY SYSTEM

SYSTEMS, PROCEDURES AND DEVICES FOR THE TRANSMISSION OF DATA AND DATA MASK BIT IN A CONVENTIONAL FRAME WITH COMMON ERRONEOUS BIT CODE

ERROR RECOGNITION IN ASYMMETRICAL HIGH-SPEED INTERFACES USING DEDICATED INTERFACE LINES

SWITCHING CONFIGURATION FOR THE MONITORING OF THE LOGIC OF GROUPS OF CODE SIGNALS, IN PARTICULAR OF BINARY NUMBERS OF GIVING LENGTH IN PROGRAM CONTROLLED MECHANISMS OF THE DATA PROCESSING

BROADCAST AND EMPFANGSSYSTEM AND CONDITION ENTRANCE SYSTEM FOR IT

PROCEDURE FOR THE SOFTWARE FAULT TREATMENT

PROCEDURE AND DEVICE FOR THE REMOTE CONTROL AND - MONITORING OF THE USE OF COMPUTER PROGRAMS

BCH ERROR CORRECTION CODE DEKODIERUNGSVERFAHREN IN REAL TIME PROCESSING

PROCEDURE AND ARRANGEMENT FOR RECOGNIZING AND ANNOUNCING INCORRECT ONE, DATA MULTIPLEXER STEERING CONTROL SIGNALS IN INTEGRATED CIRCUIT COMPONENTS.

PROCEDURE FOR THE PARITY BIT DETERMINATION AND FOR THE MONITORING OF THE TRANSMISSION DURING THE DATA PUSHING AS WELL AS SWITCHING CONFIGURATION FOR THE EXECUTION OF THE PROCEDURES.

PROCESSING OF DIGITAL TELEVISION SIGNALS.

ON HIGH SYSTEM LEVEL SELF-CHECKING INTELLIGENT I/O CONTROLLER.

ELECTRICAL INTERFACE SYSTEM AND METHOD.

HIGH-SPEED (CARRIAGE RETURN CHARACTER) CHECK SUM GENERATOR AND TEST SYSTEM WITH PROGRAMMABLE ARCHITECTURE

PROCEDURE FOR THE ENTERPRISE OF A SIGNAL-TECHNICALLY SAFE MULTIPROCESSOR SYSTEM.

COMBINATION FROM MEDICINE-TECHNICAL EQUIPMENT WITH REDUNDANTLY DEVELOPED CONTROL UNIT TO THE INFUSION THERAPY OR BLOOD TREATMENT AND A PROGRAMMING DEVICE.

ERRORTOLERANT COMPUTER SYSTEM.

SWITCHING CONFIGURATION FOR PARITY BIT PRODUCTION.

DATENUBERTRAGUNGS ANSCHLUSSGERAT

DATA REMOTE LOAD

ERRORTOLERANT DATA PROCESSING SYSTEM

DIGITAL DATA PROCESSING DEVICE.

ERROR CORRECTION CIRCUIT AND PROCEDURE IN A STORAGE FACILITY

DEVICE FOR THE MONITORING OF ON A VIDEO INDICATOR INDICATED INFORMATION

TELEVISION OR RADIO CONTROL SYSTEM DEVELOPMENT FOR MPEG

Switching configuration for memory

Indexing and recovering encoded blockchain data

... (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property (1) Organization11111111111111111111111I1111111111111i1111liiiii International Bureau (10) International Publication Number (43) International Publication Date W O 2020/011287 A3 16 January 2020 (16.01.2020) W IPO I PCT (51) International Patent Classification: (72) Inventor: ZHUO, Haizhen; No. 556 Xixi Road, 8th Floor, H04L 29/08 (2006.01) Section B, Suite 801-11, West Lake District, Hangzhou, (21) International Application Number: Zhejiang 310000 (CN). PCT/CN2019/111316 (74) Agent: BEIJING BESTIPR INTELLECTUAL PROP (22) International Filing Date• ERTY LAW CORPORATION; Room 409, Tower B, Ka 15 October 2019 (15.10.2019) Wah Building, No. 9 Shangdi 3rd Street, Haidian District, Beijing 100085 (CN). (25) Filing Language: English (81) Designated States (unless otherwise indicated, for every (26) Publication Language: English kind ofnational protection available): AE, AG, AL, ...

Link error correction in memory system

Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.

BYTE WRITE ERROR CODE METHOD AND APPARATUS

CROSS-COUPLED CHECKING CIRCUIT

INTERPROCESSOR SWITCHING NETWORK

ADDRESS TRANSFORMATION METHOD AND APPARATUS

METHOD AND MEANS FOR TOLERATING MULTIPLE DEPENDENT OR ARBITRARY DOUBLE DISK FAILURES IN A DISK ARRAY

Coding method

DATA PROCESSING USING SYMBOL CORRECTING CODE

DIGITAL VIDEO PROCESSOR ERROR CORRECTING/CONCEALING BY FIELD MEMORY

Infrared data communication system

Method and apparatus for preventing fraudulent access in a conditional access system

Change-tolerant method for generating identifier for collection of assets in computing environment using error-correction code scheme

A secure and change-tolerant method for obtaining an identifier for a collection of assets associated with a computing environment. Each asset has an asset parameter and the computing environment has a fingerprint based on an original collection of assets and on a codeword generation algorithm on the original collection of assets. The method comprises: retrieving the asset parameters of the collection of assets and processing the retrieved asset parameters to obtain code symbols. An error- correction algorithm is applied to the code symbols to obtain the identifier. The method can be used in node-locking.

Improved processes for making opioids including 14-hydroxycodeinone and 14-hydroxymorphinone

Improved processes for making opioid products having low impurity levels including making 14-hydroxycodeinone and 14-hydroxymorphinone from thebaine and oripavine, respectively.

GROUND FAULT INTERRUPTER APPARATUS

Method and apparatus for preventing fraudulent access in a conditional access system

Data processing system

Computer memory organization

Error detection scheme for ASQ systems

System and method for multi-dimensional encoding and decoding

A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.

Apparatus for reallocating logical to physical disk devices using a storage controller and method of the same

A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical device; and reallocates the first and second logical devices to the second and the first physical disk device, respectively.

System and method for data recovery in multi-level cell memories

A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.

Rule based aggregation of files and transactions in a switched file system

A switched file system, also termed a file switch, is logically positioned between client computers and file servers in a computer network. The file switch distributes user files among multiple file servers using aggregated file, transaction and directory mechanisms. The file switch distributes and aggregates the client data files in accordance with a predetermined set of aggregation rules. Each rule can be modified independently of the other rules. Different aggregation rules can be used for different types of files, thereby adapting the characteristics of the switched file system to the intended use and to the expected or historical access patterns for different data files.

Coordinated garbage collection for raid array of solid state disks

An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices.

Memory systems and memory modules

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Redundant array of independent clouds

A computing device executing a reliable cloud storage module divides data into a first data block and a second data block. The computing device stores the first data block in a first storage cloud provided by a first storage service, and stores the second data block in a second storage cloud provided by a second storage service. The computing device thereafter receives a command to read the data. In response, the computing device retrieves the first data block from the first storage cloud and the second data block from the second storage cloud. The computing device then reproduces the original data from the first data block and the second data block.

Object File System

An object based file system for storing and accessing objects is disclosed. The file system may be implemented as a method in hardware, firmware, software, or a combination thereof. The method may include receiving from an application program an object write request. A selected storage node on which to store the object may be selected, including identifying a least busy storage node and/or a least full storage node. The object and the object write request may be sent to the selected storage node. A write success message may be received from the selected storage node. The successful writing of the object may be reported to the application program. An object identifier and object data may be stored in a database.

Method and system for placement of data on a storage device

Embodiments of systems and methods for a storage system are disclosed. More particularly, in certain embodiments locations of storage devices may be allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where the different performance characteristics associated with different areas of disks in the data bank may be taken into account when allocating physical segments to corresponding logical segments of a volume by allocating certain physical segments to a particular logical segment based upon a location of the physical segment or criteria associated with the logical segment.

Semiconductor memory device with error correction

This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Decoder based data recovery

Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

Apparatus, system, and method for managing lifetime of a storage device

An apparatus, system, and method are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module monitors write bandwidth of the data storage device relative to the write bandwidth target. A throttle module adjusts execution of one or more write operations on the data storage device in response to the write bandwidth of the data storage device failing to satisfy the write bandwidth target.

Systems and methods for averaging error rates in non-volatile devices and storage systems

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Apparatus and method for programmable read preamble

A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.

Intra-device data protection in a raid array

A system and method for intra-device data protection in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to identify a unit of data stored in the data storage subsystem, wherein said unit of data is stored across at least a first storage device and a second storage device of the plurality of storage devices, each of the first storage device and the second storage device storing intra-device redundancy data corresponding to the unit of data; and change an amount of intra-device redundancy data corresponding to the unit of data on only the first storage device.

Cache with Multiple Access Pipelines

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Opportunistic decoding in memory systems

Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Memory for accessing multiple sectors of information substantially concurrently

A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.

Reconstruct reads in a raid array with dynamic geometries

A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout. The controller is further configured to initiate a reconstruct read corresponding to a given read request directed to a particular storage device of the plurality of storage devices, in response to determining the particular storage device is exhibiting a non-error related relatively slow read response.

Data recovery using outer codewords stored in volatile memory

Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

Semiconductor package

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Data processing method and semiconductor integrated circuit

A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

Method and apparatus for generating an application program for a safety-related control unit

A safety controller designed to control an automated installation having a plurality of sensors and a plurality of actuators. A method for generating a user program for the safety controller comprises the step of generating a source code having a number of control instructions for controlling the actuators and having a number of diagnosis instructions for producing diagnosis reports. Safety-related program variables are processed in failsafe fashion during execution of the control instructions. A machine code is generated on the basis of the source code. At least one checksum is determined for at least some of the machine code. The diagnosis instructions are ignored for the determination of the checksum.

Method for coding and decoding digital data, particularly data processed in a microprocessor unit

The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series.

Hybrid error correction coding to address uncorrectable errors

A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data.

Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information

A system comprising a memory subsystem having at least one memory device, and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem.

Data archiving using data compression of a flash copy

Embodiments of the disclosure relate to archiving data in a storage system. An exemplary embodiment comprises making a flash copy of data in a source volume, compressing data in the flash copy wherein each track of data is compressed into a set of data pages, and storing the compressed data pages in a target volume. Data extents for the target volume may be allocated from a pool of compressed data extents. After each stride worth of data is compressed and stored in the target volume, data may be destaged to avoid destage penalties. Data from the target volume may be decompressed from a flash copy of the target volume in a reverse process to restore each data track, when the archived data is needed. Data may be compressed and uncompressed using a Lempel-Ziv-Welch process.

Memory controller and information processing system

A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

Method and system for protecting against multiple failures in a raid system

Embodiments of methods of protecting RAID systems from multiple failures and such protected RAID systems are disclosed. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks. Furthermore, one or more levels of RAID may be implemented within one or more of the data banks comprising the distributed RAID system.

Memory device

According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

Method and System for Initializing Storage in a Storage System

Embodiments of systems and methods for a high availability storage system are disclosed. More particularly, in certain embodiments desired locations of storage devices may be zeroed out during operation of the storage system and areas that have been zeroed out allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where each data bank in the set of data banks may execute a background process which zeroes areas of the storage devices of the data bank. When a command pertaining to a logical location is received a zeroed area of the physical storage devices on the data bank may be allocated to store data associated with that logical location.

Method and memory controller for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory

An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Validation of access to a shared data record subject to read and write access by multiple requesters

According to a method of access to a shared data record subject to contemporaneous read and write access by multiple requesters, a requester reads a shared data record including a payload and a first checksum. The requester calculates a second checksum of the payload of the data record. If the first and second checksums are not equal, the requester again reads the shared data record, including a third checksum, and calculates a fourth checksum of the payload of the shared data record. If the third and fourth checksums are equal, the requester processes the shared data record as valid, and if the second and fourth checksums are equal, the requester handles the shared data record as corrupt.

Program Disturb Error Logging and Correction for Flash Memory

Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory.

Methods of data handling

Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.

Apparatus and method for indicating a packet error in an audio and video communication system

An apparatus and method are provided for indicating an error of a transport packet in an audio and video communication system. The method includes receiving a frame including a transport packet, attempting Forward Error Correction (FEC) on the frame, and setting a value of an error indicating field in the transport packet according to a result of the FEC. The error indicating field includes at least one of a first flag indicating a presence or absence of an error in the transport packet, a second flag indicating a success or failure of the FEC, and a third flag indicating detection or non-detection of a Cyclic Redundancy Check (CRC).

System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss

Embodiments of the invention are directed to systems and methods for reducing an amount of backup power needed to provide power fail safe preservation of a data redundancy scheme such as RAID that is implemented in solid state storage devices where new write data is accumulated and written along with parity data. Because new write data cannot be guaranteed to arrive in integer multiples of stripe size, a full stripe's worth of new write data may not exist when power is lost. Various embodiments use truncated RAID stripes (fewer storage elements per stripe) to save cached write data when a power failure occurs. This approach allows the system to maintain RAID parity data protection in a power fail cache flush case even though a full stripe of write data may not exist, thereby reducing the amount of backup power needed to maintain parity protection in the event of power loss.

Method and apparatus for correcting errors in memory device

A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.

System and method for handling io to drives in a raid system

A system and method for handling IO to drives in a RAID system is described. In one embodiment, the method includes providing a multiple disk system with a predefined strip size. IO request with a logical block address is received for execution on the multiple disk system. A plurality of sub-IO requests with a sub-strip size is generated, where the sub-strip size is smaller than the strip size. The generated sub-IO commands are executed on the multiple disk system. In one embodiment, a cache line size substantially equal to the sub-strip size is assigned to process the IO request.

Data storage apparatus and apparatus and method for controlling nonvolatile memories

According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller is configured to control data input to, and output from, nonvolatile memories for channels. The encoding module is configured to generate encoded data for which an inter-channel error correction process, using data stored in each of the nonvolatile memories. The data controller is configured to manage the encoded data in units of logic blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to one plane in each logic block.

Parity-based vital product data backup

A method for maintaining vital product data (VPD) of each field replaceable unit (FRUs) in a computer system, the computer system including a first FRU and a second FRU operatively coupled with the first FRU. The method includes calculating a parity for the VPD of the second FRU, and upon detecting a failure of the second FRU, regenerating the VPD for the failed second FRU using the parity.

Determining location of error detection data

Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.

Dram address protection

In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

Soft decoding systems and methods for flash based memory systems

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Configurable pipeline based on error detection mode in a data processing system

A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Method in a Gaming Machine for Providing Data Recovery

Disclosed is a gaming machine capable of data restoration.

Storage device and storage-device control method

A generation-code storage unit stores therein a generation code in association with identification information for identifying the block datum. A generation-code managing unit assigns a new generation code to a detected consecutive data set and any block datum included in writing data other than the consecutive data set and stores the assigned generation code in the generation-code storage unit. A data writing unit adds the new generation code to the block datum or consecutive data set included in the writing data and writes it to a storage unit. A determining unit determines whether the generation code added to a read block datum or consecutive data set is accordant with the generation code of the read block datum or consecutive data set stored in the generation-code storage unit. A data transmitting unit transmits, when the generation codes are accordant, the read block datum or consecutive data set.

System and Method for Fault Tolerant Computing Using Generic Hardware

A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function. The first application instance calls the synchronization function provided by the multitasking real-time operating system before invoking a set events function provided by a multitasking real-time operating system.

Nonvolatile semiconductor memory device

The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.

Bit-replacement technique for dram error correction

The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

Semiconductor memory device and method of controlling the same

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Reliable Data Transmission with Reduced Bit Error Rate

A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

Openstack database replication

Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.

Copyback Optimization for Memory System

In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory.

Methods, devices, and systems for data sensing

The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Appending data to existing data stored in a dispersed storage network

A method begins by a processing module receiving a request to store data in dispersed storage network (DSN) memory and determining whether the data is to be appended to existing data. When the data is to be appended, the method continues with the processing module encoding, using an append dispersed storage error coding function, the data to produce a set of encoded append data slices, generating a set of append commands, wherein an append command of the set of append commands includes an encoded append data slice of the set of encoded append data slices and identity of one of a set of dispersed storage (DS) units, and outputting at least a write threshold number of the set of append commands to at least a write threshold number of the set of DS units.

Method and apparatus for dispersed storage memory device selection

A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.

Disk array apparatus and control method thereof

Proposed are a disk array apparatus and a control method thereof which facilitate data processing such as write processing and read processing even if the block sizes handled by a host computer are different. If a first write command is received from the host computer, the controller of the disk array apparatus divides first write data into a plurality of second write data, and adds a first guarantee code and writes this data to the plurality of first storage devices; if a first read command is received from the host computer, the controller reads a plurality of first read data from the plurality of first storage devices, generates second read data which is obtained by combining [the plurality of first read data], and adds a second guarantee code [to the second read data] and transmits this data to the host computer; if a second write command is received from the host computer, the controller generates fourth write data based on third write data, adds a third guarantee code [to the fourth write data] and writes this data to the plurality of second storage devices and, if the second read command is received from the host computer, the controller reads third read data from the plurality of second storage devices, divides this data into fourth read data, and adds a fourth guarantee code and transmits the data to the host computer

Memory buffer for buffer-on-board applications

Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

Data management in solid state storage systems

Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.

Distributed storage network including memory diversity

A dispersed storage (DS) unit a processing module and a plurality of hard drives. The processing module is operable to maintain states for at least some of the plurality of hard drives. The processing module is further operable to receive a memory access request regarding an encoded data slice and identify a hard drive of the plurality of hard drives based on the memory access request. The processing module is further operable to determine a state of the hard drive. When the hard drive is in a read state and the memory access request is a write request, the processing module is operable to queue the write request, change from the read state to a write state in accordance with a state transition process, and, when in the write state, perform the write request to store the encoded data slice in the hard drive.

Semiconductor memory device

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

Network-coding-based distributed file system

A network-coding-based distributed file system (NCFS) is disclosed. The NCFS may include a file system layer, a disk layer, and a coding layer. The file system layer may be configured to receive a request, for an operation on data within a data block, to specify the data block to be accessed in a storage node of a plurality of storage nodes. The disk layer may provide an interface to the file system to provide access the plurality of storage nodes via a network. The coding layer may be connected between the file system layer and the disk layer, to encode and/or decode functions of fault-tolerant storage schemes based on a class of maximum distance separable (MDS) codes. Additional apparatus, systems, and methods are disclosed.

Storage system that executes performance optimization that maintains redundancy

One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.

Image processing apparatus and control method

An image processing apparatus and a method for controlling an image processing apparatus are disclosed. The method includes: primarily processing a first thread from among a plurality of threads for a preset process; generating and storing a first error correction code for data recorded in a stack area of a random access memory (RAM) corresponding to the first thread when a primary process terminates; processing a second thread which is different from the first thread from among the plurality of threads; determining whether the data of the stack area is valid on the basis of the stored first error correction code at a point of time when the process for the second thread terminates and a secondary process for the first thread begins; and secondarily processing the first thread by restoring the data having an error in the stack area in response to a determination that the data of the stack area is invalid.

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

Memory controller and operating method of memory controller

A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector.

Method and system for data migration in a distributed raid implementation

Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with a volume stored on the associated storage media of the data banks. Migration of this volume, or a portion thereof, from one configuration to another configuration may be accomplished such that the volume, or the portion thereof, and corresponding redundancy data may be stored according to this second configuration.

Memory controller, semiconductor memory apparatus and decoding method

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Advanced memory device having improved performance, reduced power and increased reliability

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Systems and methods for storing parity groups

A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.

Populating strides of tracks to demote from a first cache to a second cache

Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system.

Writing of data of a first block size in a raid array that stores and mirrors data in a second block size

Data that is to be written is received, wherein the data is indicated in one or more blocks of a first block size. Each of the one or more blocks of the first block size is written in consecutive blocks of a second block size that is larger is size than the first block size, wherein each of the consecutive blocks of the second block size stores only one block of the first block size, and wherein each of the consecutive blocks of the second block size has empty space remaining, subsequent to the writing of each of the one or more blocks of the first block size. Filler data is written in the empty space remaining in each of the consecutive blocks of the second block size.

Apparatus for Generating a Checksum

An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

Cache memory, computer system and memory access method

A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

Memory controller and non-volatile storage device

A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.

Method and system for checking the consistency of application jar files

A computer method and system dynamically provide consistency of Java application files. A processor executed routine is configured (e.g., instrumented as an agent) to intercept each class that is loaded into a subject Java application or JVM. The system computes a cyclic redundancy check (CRC) of the respective JAR file surrounding the loaded class. The system compares the computed CRC value to a CRC value of at least one other copy of the respective JAR file. Based on the comparison, the system determines consistency (e.g., same version) of the multiple copies of the respective JAR file used by the subject Java application. If the multiple copies of the respective JAR file are determined to be inconsistent, the system alerts the user and/or enables the application to abort.

System and method for detecting copyback programming problems

Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Configuring a generic computing device utilizing specific computing device operation information

A method begins with the specific computing device token sending a distributed storage network (DSN) access request to DSN memory via the generic computing device. The DSN access request identifies specific computing device operation information that is stored as one or more of-sets of encoded data slices in the DSN memory. The method continues with the specific computing device token receiving the one or more of sets of encoded data slices from the DSN memory via the generic computing device and decoding the one or more of sets of encoded data slices to retrieve the specific computing device operation information. The method continues with enabling the generic computing device to function as a specific computing device in accordance with the specific computing device operation information.

Memory device repair apparatus, systems, and methods

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

Flash storage wear leveling device and method

A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data.

Memory card controller, memory card adaptor and memory card drive

A memory card controller includes a receiver, a flow controller, a continuity determination unit, and a command controller. When size of data transferred from the memory card reaches transfer size specified by first read command, the command controller controls the flow controller to transmit a response representing a transfer busy state, and pauses a transfer operation of the memory card. When the receiver receives a second read command in a state that the transfer operation of the memory card is paused, the command controller controls the flow controller to transmit a response representing transfer ready state to the transfer authorization request from the memory card so as to restart a transfer operation of the memory card.

Refresh architecture and algorithm for non-volatile memories

Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

System and method for improving ecc enabled memory timing

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

Controller Interface Providing Improved Data Reliability

In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Method of processing faults in a microcontroller

Embodiments described in the present disclosure relate to a method of processing faults in a control unit, the method including: upon each request for reading a datum in a first memory, received by a first interface circuit for accessing the first memory, calculating by means of the first interface circuit, a check word based on the datum read, if the check word calculated is different from a check word read in the memory in association with the datum read, activating an error signal by means of the first interface circuit, and sending the error signal to an output circuit of the control unit, without using any circuits of the control unit, likely to send a request to access the first memory.

Efficient and scalable cyclic redundancy check circuit using galois-field arithmetic

Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Data encoding in solid state storage devices

Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=p k , k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are u th and v th powers respectively of a common base r, where u and v are positive integers and k f u, whereby p (k/u)v =s.

Method and apparatus for detecting communication errors on a bus

A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Data processing method, memory controller, and memory storage device

A data processing method is provided. A data is compressed to obtain a compressed data. Compression information corresponding to the compressed data is obtained. Error checking and correcting (ECC) codes are respectively generated for the compression information and the compressed data. The compression information, the compressed data, and the ECC codes are respectively written into a rewritable non-volatile memory module. The compression information, the compressed data, and the ECC codes are respectively read from the rewritable non-volatile memory module. An ECC procedure is preformed on the compression information according to the corresponding ECC code, so as to obtain a storage state when the compression information is written. An ECC procedure is preformed on the compressed data according to the storage state of the compression information and the ECC code corresponding to the compressed data, so as to obtain a storage state when the compressed data is written.

Lifetime mixed level non-volatile memory system

A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Identifying a slice error in a dispersed storage network

A method begins by a dispersed storage (DS) processing module identifying a set of collections of records corresponding to a data segment that is stored in a dispersed storage network (DSN) as a set of encoded data slices, wherein a collection of records includes an event record including information regarding an event, a first record including information regarding a dispersed storage (DS) processing module processing an event request to produce a plurality of sub-event requests, and a plurality of records including information regarding a set of DS units processing the plurality of sub-event requests. The method continues with the DS processing module determining whether an error exists for one of the set of encoded data slices based on at least some of the set of collections of records and when the error exists, flagging the one of the set of encoded data slices for potential rebuilding.

Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats

Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.

System and method for instruction sets with run-time consistency check

A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.

Method for improving performance in raid systems

A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Collecting failure information on error correction code (ecc) protected data

Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

Storage system, storage control device, and storage control method

A control device manages a plurality of storage devices so that data to be recorded is redundantly recorded in different storage devices. An error monitoring unit monitors an occurrence of an error in each of the plurality of storage devices to register information indicative of error occurrence conditions in an error information storage unit for each storage device. When the use of one of the plurality of storage devices is stopped, a rebuild controller determines a timing to perform rebuild processing based on past error occurrence conditions in the storage devices other than the one storage device of the plurality of storage devices by referring to information registered in the error information storage unit.

Error indicator from ecc decoder

The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

Network-capable raid controller for a semiconductor storage device

Embodiments of the present invention provide a network-capable RAID controller for a storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a network-capable RAID controller coupled to one or more (i.e., a set of) semiconductor storage devices (SSDs). Among other components, the network-capable RAID controller comprises an input/output (I/O) controller coupled to a network interface. The network interface allows the network-capable RAID controller to communicate with an external network.