КОНСТРУКЦИЯ БИПОЛЯРНЫХ ТРАНЗИСТОРОВ С ИЗОЛИРОВАННЫМ ЗАТВОРОМ

Конструкции биполярных транзисторов р-п-р(или п-р-п)-типа с изолированным затвором содержит области эмиттера, базы, коллектора и затвора, отделенного от них диэлектрической пленкой, а также диод с управляющим электродом, объединенный с электродами биполярного транзистора, в частности р(или п)-типа коллектор с анодом (или катодом), а n (или p)-типа база с катодом (или анодом) диода с управляющим электродом-затвором служит для задания тока в базу и устранения паразитных тиристорных и транзисторных структур. В другом варианте биполярный транзистор с изолированным затвором состоит из множества транзисторов по основному варианту, изготовленных в единой подложке и соединенных параллельно по одноименным электродам.

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Mfg. self-aligned gallium arsenide MESFET - involves forming T=shaped tungsten gate electrode

Mfr. of a self-aligned MESFET with a T-shaped tungsten gate electrode involves (a) applying a thin Si layer over the entire surface of a semi-insulating GaAs substrate by plasma-enhanced CVD, applying a Si3N4 layer by photo-CVD and ion implanting to produce an n-active layer using a photo-mask; (b) forming a gate electrode pattern by etching the Si3N4 layer using. the photo-mask; (c) selectively depositing tungsten by CVD only on the exposed Si layer and not on the Si3N4 layer; (d) thickening the tungsten in the transverse direction to form a T-shape; (e) forming an n+-layer by ion implantation using the T-shaped tungsten gate such that the gap between the gate electrode and the n+-layer is 1000-2000 Angstroms; (f) activating the n- and n+-layers using the Si layer and the Si3N4 layer as cover film; (g) ion implanting through the Si and Si3N4 layers to provide insulation between the devices; and (h) etching the Si and Si3N4 layers and applying an ohmic metallisation (AuGe/Ni) by a lift-off ...

DÜNNSCHICHTTRANSISTOR UND DIESEN TRANSISTOR GEBRAUCHENDE ANZEIGE.

Dünnfilmtransistor und Anzeigevorrichtung unter Verwendung desselben

FELDEFFEKT-HALBLEITERANORDNUNG MIT EINER NEBENELEKTRODE.

Leistungs-Halbleitervorrichtung

Vorgesehen wird eine Leistungs-Halbleitervorrichtung, die einen Elementbruch verhindert, was somit deren Zuverlässigkeit verbessert. Die Leistungs-Halbleitervorrichtung umfasst eine erste Hauptelektrode. Die erste Hauptelektrode umfasst einen ersten Metallfilm, einen Zwischenfilm und einen zweiten Metallfilm. Die ersten und zweiten Metallfilme bestehen aus einem Metall mit einer AI-Konzentration, die höher als oder gleich 95 Gew.-% ist. Der Zwischenfilm enthält Phasen eines primären Bestandteils, die jeweils aus einer Metallverbindung gebildet sind, und enthält eine Phase eines sekundären Bestandteils, die aus einem Element der Eisengruppe gebildet ist. Die Metallverbindung ist diejenige aus zumindest einer Art eines Elements, das aus einer Gruppe ausgewählt wurde, die aus einem Element der Gruppe 4A, einem Element der Gruppe 5A und einem Element der Gruppe 6A besteht, und zumindest einer Art eines Elements, das aus einer aus C und N bestehenden Gruppe ausgewählt wurde. Der Zwischenfilm ...

Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe

Ein Nanodrahttransistor weist undotierte Source- und Drain-Bereiche auf, die elektrisch mit einem Kanalbereich gekoppelt sind. Ein Source-Stapel, der elektrisch von einem Gate-Leiter isoliert ist, weist eine Grenzflächenschicht und einen Source-Leiter auf und läuft koaxial vollständig um den Source-Bereich, indem er sich entlang mindestens eines Abschnitts des Source-Bereichs erstreckt. Eine Schottky-Barriere zwischen dem Source-Leiter und dem Source-Bereich ist eine negative Schottky-Barriere, und eine Konzentration freier Ladungsträger wird in dem Halbleiter-Source-Bereich induziert.

ELEKTRISCH LEITFÄHIGE STRUKTUR, VERFAHREN ZUM BILDEN DER ELEKTRISCH LEITFÄHIGEN STRUKTUR UND HALBLEITERVORRICHTUNG

... [Problem] Verringern von Kontaktwiderstand beim Abgreifen eines Stroms oder einer Spannung von einer Metallschicht.[Lösung] Eine elektrisch leitfähige Struktur ist mit Folgendem versehen: einer Isolierschicht, einer auf einer Oberfläche der Isolierschicht dahingehend angeordneten Metallschicht, in einer Dickenrichtung der Isolierschicht vorzuragen, und einer zweidimensionalen Materialschicht, die entlang den äußeren Formen der Metallschicht und der Isolierschicht von einer Seitenfläche der Metallschicht zu der einen Oberfläche der Isolierschicht angeordnet ist.

Verfahren zur Herstellung einer Bipolartransistorstruktur für Höchstgeschwindigkeitsschaltung.

Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip

Vertikal isolierter, monolithischer Hochleistungsbipolartransistor mit Topkollektor

Schnellschaltender, lateraler Feldeffekttransistor mit isolierter Steuerelektrode

BIPOLAR TRANSISTOR

HALBLEITERELEMENT UND HALBLEITERBAUTEIL

Ein Halbleiterelement beinhaltet einen Hauptkörper und eine Vorderseitenelektrode. Der Hauptkörper beinhaltet eine Vorderseite, die in eine Dickenrichtung weist. Die Vorderseitenelektrode ist elektrisch mit dem Hauptkörper verbunden. Die Vorderseitenelektrode beinhaltet eine erste Sektion und eine Vielzahl von zweiten Sektionen. Die erste Sektion ist auf der Vorderseite vorgesehen. Die Vielzahl von zweiten Sektionen stehen in Kontakt mit der ersten Sektion und sind voneinander in einer Richtung beabstandet, die senkrecht ist zu der Dickenrichtung. Ein Gesamtflächenbereich der Vielzahl von zweiten Sektionen ist kleiner als ein Flächenbereich der ersten Sektion, einschließlich von Abschnitten, die mit der Vielzahl von zweiten Sektionen überlappen, und zwar in einer Ansicht in der Dickenrichtung.

Halbleiterbauelement und Herstellungsverfahren

Ein ohmscher Widerstand ist zwischen zwei Anteilen einer Leiterschicht vorhanden, so dass die Größe des ohmschen Widerstandes ermittelt werden kann, und/oder in oder auf einer Schicht aus dem Dielektrikum (1) ist ein Halbleiterbereich (2) vorhanden, wobei die Leiterschicht (5) in einen Gate-Kontakt (6), einen Source-Kontakt (7) und einen Drain-Kontakt (70) strukturiert ist, so dass in dem Halbleiterbereich eine Transistor- oder Schaltfunktion möglich ist. Damit kann ein Versuch einer Analyse der in dem Chip integrierten Schaltung detektiert werden.

Leistungshalbleitervorrichtung mit einer Grabengateelektrode und Verfahren zum Herstellen derselben

Halbleiterbauteil mit verbesserter und reduzierter Miller-Kapazität in einer sich wiederholenden zellulären Struktur, wobei die Zellen des Bauteils umfassen: ein Substrat mit einer ersten Schicht, die mit einem Dotierstoff erster Leitfähigkeit dotiert ist und einen Drain bildet, eine zweiten Schicht, die sich über der ersten Schicht befindet und mit einem Dotierstoff erster Leitfähigkeit dotiert ist, eine dritten Schicht, die sich über der zweiten Schicht befindet und mit einem Dotierstoff zweiter Leitfähigkeit dotiert ist, der entgegengesetzt zu der ersten Leitfähigkeitskomponente polarisiert ist, eine vierten Schicht, die sich auf der gegenüberliegenden Fläche des Halbleitersubstrats befindet und mit einem Dotierstoff erster Leitfähigkeit stark dotiert ist, eine Grabenstruktur,...

Druckkontakt-Halbleiterbauelement mit Blindsegment

Jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) wird als Blindsegment verwendet. Eine obere Oberfläche eines vorstehenden Teils (OMPP, IMPP) jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) ist mit einer Isolierschicht (1S + 1P) bedeckt, und zwischen einer oberen Oberfläche der Isolierschicht (1S + 1P) und einer unteren Oberfläche (2BS) einer Katodenentlastungsplatte ist ein Abstand (CL) vorhanden. Alle anderen Segmente (SG), mit Ausnahme der äußersten und der innersten, besitzen einen vorstehenden Teil, auf dem eine Katodenelektrode (1K-AL) ausgebildet ist. Die Dicke (T1) der Katodenelektrode (1K-AL) ist so bemessen, dass eine obere Oberfläche der Katodenelektrode (1K-AL) mit der unteren Oberfläche (2BS) der Katodenentlastungsplatte in Kontakt kommen kann.

Leistungs-MOSFET

Leistungshalbleiterbauelement mit erhöhter Robustheit

Leistungshalbleiterbauelement mit erhöhter Robustheit, umfassend: - einen Halbleiterkörper (1) mit einer ersten Hauptoberfläche (7) auf einer Vorderseite des Halbleiterkörpers (1) und einer zweiten, entgegengesetzt zur ersten Hauptoberfläche (7) gelegenen Hauptoberfläche (11) auf einer Rückseite des Halbleiterkörpers (1), - einer auf der ersten Hauptoberfläche (7) angeordneten ersten Metallisierung (10), und - einer auf der zweiten Hauptoberfläche (11) angeordneten zweiten Metallisierung (12), - wobei der Halbleiterkörper (1) mit der ersten Metallisierung (10) an der ersten Hauptoberfläche (7) und mit der zweiten Metallisierung (12) an der zweiten Hauptoberfläche (11) elektrisch Kontaktiert wird, dadurch gekennzeichnet, dass - beide Metallisierungen (10, 12) als direkt auf der entsprechenden Hauptoberfläche (7, 11) des Halbleiterkörpers (1) aufgebrachte Schicht eine Kontaktschicht (14) aufweisen, die aus Aluminium besteht und eine Schichtdicke zwischen 1 und 5 nm hat.

Halbleiteranordnung mit einem Tunnelkontakt und Verfahren zu deren Herstellung

Bei einer Halbleiteranordnung aus Siliciumcarbid oder dergleichen mit einem Wafer als Substrat ist ein hochleitfähiger Tunnelkontakt vorhanden. Dazu wird ein n-Substrat verwendet, wobei eine Umkehrung der Dotierung beim weiteren epitaktischen Wachstum erfolgt. Bei der Herstellung einer solchen Anordnung durch epitaktische Beschichtung eines n-dotierten Wafers als Substrat mit einem p-dotierten Halbleitermaterial (p-Epitaxie) wird zur Herstellung des Tunnelkontaktes vor der p-Epitaxie eine n-Implantation in den Wafer vorgenommen. Es können so insbesondere IGBT-artige Bauelemente hergestellt werden.

Nitridhalbleitervorrichtung und deren Herstellungsverfahren

Nitridhalbleitervorrichtung, die einen IIIV Nitridhalbleiter umfasst, der aus zumindest einem Element der Gruppe III aus einer Gallium, Aluminium, Bor und Indium enthaltenden Gruppe und zumindest Stickstoff als Element der Gruppe V aus einer Stickstoff, Phosphor und Arsen enthaltenden Gruppe zusammengesetzt ist, die Nitridhalbleitervorrichtung umfasst dabei: eine erste Nitridhalbleiterschicht, die den auf einem Substrat abgeschiedenen IIIV Nitridhalbleiter aufweist, wobei die erste Nitridhalbleiterschicht als Ladungszufuhrschicht eingerichtet ist; eine zweite Nitridhalbleiterschicht, die den IIIV Nitridhalbleiter aufweist, der auf der ersten Nitridhalbleiterschicht abgeschieden ist und kein Aluminium enthält; und eine Steuerelektrode, die einen Schottky-Kontakt mit der zweiten Nitridhalbleiterschicht ausbildet, wobei die erste Nitridhalbleiterschicht eine Epitaxieschicht ist, und die zweite Nitridhalbleiterschicht eine Schicht mit einer Kristallinität mit winzigen Körnern ist, die durch ...

Diode mit einem plattenförmigen Halbleiterelement

Die Erfindung zeigt eine Diode mit einem plattenförmigen Halbeiterelement (3) mit einer ersten Seite und einer zweiten Seite, wobei die erste Seite durch eine erste Verbindungsschicht (5) mit einer ersten metallischen Kontaktierung (6) verbunden ist und die zweite Seite durch eine zweite Verbindungsschicht (4) mit einer zweiten metallischen Kontaktierung (2) verbunden ist, wobei die erste Seite in einem Mittelbereich ein Diodenelement (1613) aufweist und in einem Randbereich der ersten Seite, der Kristallstörungen aufgrund eines Trennprozesses des plattenförmigen Halbleiterelements aufweist, ein weiteres Diodenelement (1413) aufweist, wobei die erste Verbindungsschicht (5) nur einen elektrischen Kontakt zum Diodenelement (1613) und nicht zum weiteren Diodenelement (1413) herstellt und auf der ersten Seite das weitere Diodenelement (1413) einen freiliegenden Kontakt aufweist, der durch die erste Verbindungsschicht (5) elektrisch kontaktierbar ist.

SOURCE-DOWN-LEISTUNGSTRANSISTOR

"PLANARE TRANSISTORSTRUKTUR"

There is disclosed a planar transistor structure comprised of a semiconductor chip with n<-> conductivity forming a collector area and presenting a base area (11) and a transmitter area (12) with n<+> conductivity diffused in its upper surface and a passivation layer (13). The passivation layer (13) covers the portions of the upper surface of the chip (10) which do not act as a contact window. In the collector material with n<-> conductivity an annular area with n<+> conductivity is diffused which completely surrounds the base area (11). The passivation layer extends on this annular area (16). Either the transmitter metalization (14), or the base metallization (15) is prolonged above the passivation layer up to the region of the annular area (16).

Verbindungsstruktur einer Halbleitereinrichtung und ihr Herstellungsverfahren

Verfahren zur Herstellung einer MOS-Transistorstruktur mit einstellbarer Schwellspannung

Verfahren zur Herstellung einer Trench-MOS-Transistorstruktur mit einstellbarer Schwellspannung, mit Sourcegebieten (8), Draingebieten (11) und Gate-Elektroden (9) mit den Schritten: - Bereitstellen einer Substratschicht (1) ersten Leitungstyps, - Bilden von Bodygebieten (2) zweiten Leitungstyps, die an die Substratschicht (1) angrenzen, wobei die Bodygebiete (2) eine Hauptoberfläche (3) der Transistorstruktur definieren, - Bilden von Gateoxid (10) und Gate-Elektroden (9), - Bilden von Sourcegebieten (8) ersten Leitungstyps, die sich von der Hauptoberfläche (3) in die Bodygebiete (2) erstrecken, wobei mindestens eine Kanalregion (7) in den Bodygebieten (2) zwischen den Sourcegebieten (8) und der Substratschicht (1) definiert wird, die an eine Gate-Elektrode (5) angrenzt, wobei - eine Implantation von Dotiermaterial ersten Leitungstyps zumindest in einen Teil der Kanalregion (7) des Bodygebietes (2) erfolgt und dabei die Implantationsdosis so eingestellt wird, dass im Implantationsgebiet ...

HALBLEITERBAUELEMENT

MOS-FELDEFFEKTTRANSISTOR

Hochintegriertes Halbleiterbauelement mit Silicidschicht und zugehöriges Herstellungsverfahren

Hochintegriertes Halbleiterbauelement mit einem Halbleitersubstrat (100), einer Gateelektrode (110), die auf einem vorgegebenen Bereich des Halbleitersubstrats angeordnet ist, einem Offset-Abstandshalter (115) an wenigstens einer Seitenwand der Gateelektrode, einer epitaxialen Schicht (120) auf dem Halbleitersubstrat (100) beidseits neben der Gateelektrode (110) mit dem Offset-Abstandshalter und daran angrenzend, wobei die Gateelektrode um eine vorgegebene Tiefe (d) in der epitaxialen Schicht vertieft ist, einem Sourcebereich und einem Drainbereich (150a, 150b) die beidseits der Gateelektrode in der epitaxialen Schicht und einem vorgegebenen oberen Bereich des Halbleitersubstrats unterhalb der epitaxialen Schicht ausgebildet sind und jeweils einen schwach dotierten Bereich (130a, 130b), der sich im oberen Bereich des Halbleitersubstrats lateral bis zur Seitenwand einer Gateisolationsschicht (105) der Gateelektrode erstreckt, und einen stark dotierten Bereich (140a, 140b) lateral angrenzend ...

VERFAHREN ZUM HERSTELLEN EINES FELDEFFEKTTRANSISTORS MIT ISOLIERTER STEUERELEKTRODE

Monolithische Darlington-Transistorschaltung

Semiconductor arrangement for switching inductive loads such as motor, has Schottky diode that is formed by Schottky contact between source electrode and drift zone of semiconductor surface

The arrangement has a gate electrode (40) arranged in a trench extending in vertical direction of semiconductor surface (100). The gate electrode is insulated from the semiconductor surface and a source electrode (60). A Schottky diode connected in parallel with a drain-source path of the MOS transistor, is formed by the Schottky contact between source electrode and drift zone (12) of semiconductor surface.

Verfahren zum Herstellen eines Trenchtransistors

Verfahren zum Herstellen eines Trenchtransistors mit: – einem Halbleiterkörper (1) des einen Leitungstyps, – einem in einem Oberflächenbereich des Halbleiterkörpers (1) vorgesehenen Halbleitergebiet (9) des anderen, zum einen Leitungstyp entgegengesetzten Leitungstyps, – einem von der freiliegenden Oberfläche des Halbleitergebiets (9) durch das Halbleitergebiet (9) bis zum Halbleiterkörper (1) von oben nach unten ragenden Trench (5), – einer die Wand des Trenches (5) wenigstens teilweise auskleidenden Isolierschicht (4), – einer leitenden Trenchfüllung (7) im unteren Bereich des Trenchs (5), – einer isolierenden Trenchfüllung (8) im oberen Bereich des Trenchs (5) und – einer in dem Halbleitergebiet (9) längs der Isolierschicht (4) vorgesehenen Halbleiterzone (11) des einen Leitungstyps, wobei: – das obere Ende der Isolierschicht (4) und die Oberfläche der isolierenden. Trenchfüllung (8) die Oberfläche des Halbleitergebiets (9) wenigstens teilweise überragen, – der untere Rand der Halbleiterzone ...

FABRICATION OF SEMICONDUCTOR DEVICES INCORPORATING POLYCRYSTALLINE SILICON

... 1384153 Semi-conductor devices RCA CORPORATION 12 Oct 1972 [20 Oct 1971] 47217/72 Heading H1K In the manufacture of a semi-conductor device silicon is vapour deposited on a substrate maintained at a temperature less than 700‹ C. so as to be insulating (10<12> ohm. cm. resistivity) and is then annealed at about 1100‹C. to convert it into semi-conductor form, dopant atoms being incorporated in the layer at some stage. The substrate may be of quartz, ceramic, sapphire, spinel, silicon or germanium with or without a coating of metal, semi-conductor oxide or nitride. As described the silicon is deposited at a rate of 2Á/hour from a mixture of silane, hydrogen and a source of dopant (arsine or borane) on silicon held at 600‹ C. in a tube which has been purged first with nitrogen and then hydrogen and is purged after deposition with hydrogen. It is annealed by heating to 1100‹ C. in hydrogen. Typically the process is used in making an integrated circuit comprising a bipolar transistor and an IGFET ...

Chemical vapour deposition method and apparatus therefor

A chemical vapor deposition method is characterized in that a heating block and a surface to be deposited of a substrate are arranged to face to each other at a given distance in a closed space, a source gas is guided into the closed space and supplied between the heating block and the substrate, thereby depositing a thin film on the surface to be deposited of the substrate. A chemical vapor deposition apparatus includes a heating block arranged in a closed space, a substrate holder for holding a substrate so that a surface to be deposited of the substrate is arranged to face to the heating block at a given distance, and a device for guiding a source gas to the closed space. In this CVD apparatus, the source gas guided by the device is guided to the closed space and supplied between the heating block and the substrate, thereby depositing a thin film on the surface to be deposited of the substrate.

Trench MOSFET structure

A trench MOSFET in which two first trenches (7) and a second trench (12) arranged between the first trenches (7) extend into a semiconductor structure through a first region (9) of a first conductivity type and a second region (10) of a second conductivity type into a third region (11) of the first conductivity type. The second trench (12) is separated from the third region (11) by a fourth regions (13) of the second conductivity type. The first trenches (7) receive gate-forming conductive material (4) insulated by layer (8) from the surrounding structure with material (4) connected to electrode (3), whereas the second trench receives metal (2) defining a source contact (1). The fourth region (13) is more highly doped than the second region (10), and extends to a depth no greater than the depth of the first trenches (7). The drain region (6) is situated below the third region (11) and is connected to electrode (5).

High performance mosfet

Bicmos process utilizing novel planarization technique

A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing ...

Vessel with discharge means

A vessel, 1, has a bottom consisting of a set of doors, 2, capable of at least partial rotation about parallel axes, 3. The doors in a closed position provide a series of peaks and troughs, and partial rotation of one or more of the doors to an open position permits material in the vessel to flow out. ...

Semiconductor structures

In a semiconductor structure a masking layer 12 is formed to cover a portion of a surface of a semiconductor 10, a first doped region 36 is formed by ion implantation in a portion of the semiconductor exposed by the masking layer 12, a chemical etchant is brought into contact with the masking layer 12, reducing the area of the masking layer covering the semiconductor and thereby exposing a second, different portion 47 of the semiconductor contiguous to the first exposed portion 36 of the semiconductor, and particles capable of establishing a doped region in the semiconductor layer are introduced by ion implantation into the second exposed portion 47 of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, the chemically etched masking layer 12 inhibiting the particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self- aligned gate region (second ...

Semiconductor device electrodes

A semiconductor device, especially a gate turn-off thyristor, has interdigitated electrodes (106, 107), e.g. of Al, provided with with contact strips (106a, 107a) of a solderable material, to which a lead (400) may be soldered. The solderable strips may comprise multilayer structures of Al-Mo-Ni-Au or Al-Zn-Ni-Au. ...

Field-effect controlled bi-directional lateral thyristor

A five terminal solid-state relay which represents the merger in a single semiconductive body of a pair of DMOS transistors (13, 14) in a common drain configuration in shunt with a parallel pair of oppositely poled thyristors (16, 17). This relay is combined with special control circuitry to form a normally OFF switch which is bilateral, able to hold off high voltages, can withstand large current of overvoltage surges, and can be switched on either electrically or optically.

THIN FILM TRANSISTOR WITH LAMINATED SOURCE AND DRAIN ELECTRODES AND METHOD OF MANUFACTURE

Phototransistor

MOS transistor

A first insulating layer 22 is formed to cover the gate structure 25. A second insulating layer 26 is formed on the substrate 10 spaced apart from the first insulating layer 22. Lightly doped source/drain regions 28 are formed in the surface of the substrate 10 between the second insulating layer 26 and the gate structure 25. Elevated source/drain extension layers 30 are formed on the source/drain regions 28, and heavily doped source/drain regions 34 are formed on the second insulating layer 26 so as to connect with the source/drain extension layers 30. Alternatively, heavily doped source/drain regions are formed on the second insulating layer 26, and fill the gaps between the gate structure 25 and the second insulating layer 26. A memory cell comprising two gate structures is also disclosed. The invention suppresses the short channel effect and reduces the source/drain junction capacitance.

Improvements in or relating to solid state rectifiers

... 981,270. Semi-conductor devices. GENERAL INSTRUMENT CORPORATION. June 28, 1963 [July 27, 1962], No. 25754/63. Heading H1K. In a controlled power rectifier comprising a semi-conductor body having three successive layers of which the second layer 32 is of opposite conductivity type to the first and third layers 36 and 34, respectively, a first terminal 14, Fig. 1 (not shown), is connected to the first layer 36, a region 38 of opposite conductivity type is provided in the third layer 34 and extends to a portion of the outer surface of the third layer, a second terminal 22 is connected to the region 38, a gate terminal 24 is connected to a part 40 of the outer surface of the third layer 34 not occupied by the region 38, and the outer surface of the third layer 34 is metal plated (at 42 and 46, Fig. 4, or 60 and 62, Fig. 5) with a gap 50, Fig. 4, or 64, 641, Fig. 5, in the metal plating, the gap lying mainly over the junction 52 between the region 38 and the part 40 but departing from ...

MOS TRANSISTOR

Field effect transistor

The gate of a gallium indium arsenide FET grown on an indium phosphide substrate comprises a top layer of GaInAsP (band gap 1.2 eV) a middle layer of GaInAs and a bottom layer of InP. This can be etched to produce an overhanging top layer which allows self-aligned gate contact metallization avoiding the registration problems of a further masking stage.

VDMOS DEVICE

Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Semiconductive pnpn devices

... 909,870. Semi-conductor devices, WESTERN ELECTRIC CO. Inc. May 30, 1961 [June 10, 1960], No. 19470/61. Class 37. The turn-off gain of a PNPN(NPNP) device is made large by arranging that the total is slightly greater than unity, the of one of the included transistors being less than but close to unity and the other greater than but close to zero. In the arrangement shown in Fig. 2, the NPN transistor is made by conventional methods to have a gain of about 0.99 but the PNP transistor is made to have a gain of about 0.05 by making the injection efficiency low. This is achieved in practice by making the sheet resistance of P zone 24 much higher than that of base zone 23. Actual figures are 1000 ohms/ square for the P zone and 50 ohms/square for the N zone. The device may be produced by starting with a N-type silicon base 23, the P and N zones 22, 21 being produced by successive diffusion of boron and phosphorous respectively and P region 24 is produced by phosphorous diffusion. In a further ...

CCD ARRANGEMENTS

Improvements in crystal contacts of which one element is silicon

In the manufacture of silicon crystal contacts as claimed in the parent Specification the purified silicon powder is melted in a container made of or lined with alumina or a mixture of alumina and beryllium oxide. Pieces of the melt may be treated with hydrofluoric acid, heated in an oxidizing atmosphere, and again treated with hydrofluoric acid. The Provisional Specification describes also chromium oxide as a material for making the container. Specification 577,181 is referred to.

BI-DIRECTIONAL LATERAL THYRISTOR

FIELD EFFECT TRANSISTORS

IGFET

Multi-junction semi-conductor elements

... 1,144,402. Semi-conductor device. WESTINGHOUSE BRAKE & SIGNAL CO. Ltd. 17 Nov., 1967 [20 Jan., 1967], No. 3211/67. Heading H1K. In a multi-junction semi-conductor element with two planar faces 1, 2, between which is a peripheral face 3, and where the junction J, adjacent to the anode emerges on this peripheral face and all the other junctions emerge on a planar face 1, a layer 4 of metal such as aluminium is deposited on the anode face 2 and part of the peripheral face 3 to partially shortcircuit the junction J 1 . The metal layer is formed by vapour deposition from a pellet, either in one or a series of sequential stages.

A PRODUCTION METHOD OF A SEMICONDUCTOR DEVICE

Semiconductor device

Liquid crystal display device and a method of manufacturing the same

METHOD OF MAKING DEVICES HAVING CLOSELY SPACED ELECTRODES

... 1456459 Charge coupled devices TEXAS INSTRUMENTS Inc 13 Dec 1974 [26 Dec 1973] 53978/74 Heading H1K In the manufacture of a CCD a plurality of regions defining PN junctions with the semiconductor substrate are formed at its surface and exposed through an overlying layer of insulation to contact a first layer of metallization which after being patterned to define a set of electrodes is anodized by passing a current from an electrode applied to the back of the substrate to an electrolyte contacting the electrodes via the forward biased junctions. Typically, in forming a three-phase structure, the regions, designed as clock lines, and input and output regions are simultaneously formed by diffusion adjacent a P-type charge transfer path defined in the surface of a P + substrate. The first metallization, of aluminium, defines a first set of electrodes and their connections to appropriate clock lines and after anodization a second metallization is deposited to define electrodes interleaved with ...

Improvements in or relating to electrical asymmetrical conducting devices having a crystalline semi-conductor

... 780,260. Semi-conductor devices. TELEFUNKEN GES. June 17, 1954 [June 17, 1953], No. 17767/54. Class 37. A PN junction is produced by plunging a portion of a semi-conductor crystal 7, such as germanium of one conductivity type, into a melted mass 9 of impurity characteristic of the opposite conductivity type. The impurity material, which may be indium, may be melted by passing current through a support electrode 10. The inserted portion of the semi-conductor is pointed. The invention enables the extent of diffusion and the area of the PN junction to be controlled.

Method of manufacturing an insulated gate field-effect transistor and transistor manufactured using such a method

A method of manufacturing an IGFET device in an entirely self-registering manner, in which on the semi-conductor body a narrow silicon nitride strip is formed which covers only the active region of the body and the width of which is substantially equal to that of the transistors to be manufactured and possibly other circuit elements. This nitride strip is used as a mask for providing the channel stopper zone and as an oxidation mask for providing a first oxide layer. The nitride strip is then etched in which the strip is locally removed over its entire width and only parts remain above the channel region and contact regions which form a second oxidation mask and, in cooperation with the first oxide layer, a doping mask. The source and drain zones of the transistors and possibly further zones, for example underpasses, are formed via said doping mask after which by oxidation a sunken oxide pattern is formed over the whole surface with the exception of the channel regions and the contact regions ...

SEMICONDUCTOR STORAGE CELL

FIELD EFFECT DEVICES

... 1453270 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 30 April 1975 [20 May 1974] 17911/75 Heading H1K An IGFET is made in a semi-conducting substrate 10, Fig. 4, by providing an insulating covering 20 on a surface in which source and drain regions 12, 14 have been formed, depositing a layer 22 of a silicon on the insulating covering 20, depositing Si 3 N 4 and SiO 2 layers 24, 26 over the silicon layer 22, removing by photolithographic techniques coincident areas of the nitride and oxide layers 24, 26 leaving coincident areas at least over the gate region, oxidizing the exposed areas 30 of the silicon layer through its entire thickness, removing the remaining areas of the oxide and nitride layers 24, 26, depositing a passivating layer 42, 44, Fig. 7, on the structure, forming contact openings 46, 48 to at least the source and drain regions 12, 14, and forming a conductive interconnecting pattern on the passivating layer 42, 44. The silicon layer 22 which forms the gate electrode ...

SELF-REGISTERED IGFET STRUCTURE

STRUCTURE OF A SEMICONDUCTOR ARRANGEMENT AND A METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT

PROTECTION DIODE TO THE PROTECTION OF SEMICONDUCTOR CIRCUITS AGAINST ELECTROSTATIC UNLOADINGS

PHOTO TRANSISTOR

MANUFACTURING PROCESS FOR SEMICONDUCTOR COMPONENT

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH DITCH GATE

PROCESS FOR SOI MECHANISMS WITH ULTRADÜNNEM BODY, THE EPI SILIZIUMSPITZEN CONTAINING, AND THEREBY MANUFACTURED ARTICLES

VERTICAL POWER SEMICONDUCTOR ARRANGEMENT AND PROCEDURE FOR THEIR PRODUCTION

REDUCTION OF A TRANSISTOR CONNECTING CAPACITY BY RECESS OF ABFLUSSUND SOURCE AREAS

VERTICAL HIGH VOLTAGE TRANSISTOR

MONOLITHIC SEMICONDUCTOR ARRANGEMENT WITH EN SENKTEM ISOLATION SAMPLES AND FIELD-EFFECT TRANSISTOR WITH INSULATING GATE ELECTRODE AND PROCEDURE FOR THE PRODUCTION THE SAME

MANUFACTURING PROCESS OF A TRANSISTOR WITH SOURCE OF METAL AND - DISCHARGE

PROCEDURE FOR THE PRODUCTION OF A VERTICAL ONE, METAL OXIDE SEMICONDUCTOR

MOS FIELD-EFFECT TRANSISTOR WITH AUXILIARY ELECTRODE

TRANSISTOR STRUCTURE.

Transistor switching arrangement

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A BIPOLAR TRANSISTOR

INTEGRATED CIRCUIT DEVICE

LATERAL SHORT-CHANNEL DMOS, METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR DEVICE

Semiconductor component with a bipolar lateral power transistor

METHOD OF MAKING TRANSISTORS

Mmic folded power amplifier

An arrangement in a power mos transistor

Semiconductor structure with improved smaller forward voltage loss and higher blocking capability

MICROWAVE FIELD EFFECT TRANSISTOR STRUCTURE ON SILICON CARBIDE SUBSTRATE

THIN FILM TRANSISTOR, LIQUID CRYSTAL DISPLAY APPARATUS, MANUFACTURING METHOD OF THIN FILM TRANSISTOR, AND MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY APPARATUS

ORGANIC SEMICONDUCTOR AND METHOD

Silicon carbide metal-semiconductor field effect transistors and methods of fabricating silicon carbide metal-semiconductor field effect transistors

A semiconductor device

Collector-up rf power transistor

BIPOLAR TRANSISTOR STABILIZATION STRUCTURE

Liquid crystal display and method for manufacturing the same

Provided is a liquid crystal display including: a first substrate; a thin film transistor disposed on the first substrate; a passivation layer disposed on the thin film transistor and comprising a contact hole exposing an electrode of the thin film transistor; a pixel electrode disposed on the passivation layer and connected to the electrode of the thin film transistor through the contact hole; a lower buffer layer disposed on the pixel electrode; a lower alignment layer disposed on the lower buffer layer; a second substrate facing the first substrate; a common electrode disposed on the second substrate; an upper buffer layer disposed on the common electrode; and an upper alignment layer disposed on the upper buffer layer, in which the lower buffer layer comprises parylene, the upper buffer layer comprises parylene, or both the lower and the upper buffer layers comprise parylene.

Thin film transistor array panel, liquid crystal display, and method to repair the same

The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

DISPLAY PANEL AND ELECTRONIC DEVICE

The present disclosure provides a display panel and an electronic device. The display panel comprises: a substrate, wherein a metal layer and an anti-reflection film are disposed on the substrate, the anti-reflection film is disposed on a light-emitting side of the metal layer, and the anti-reflection film comprises a protective layer and a darkening layer; wherein the protective layer is disposed between the darkening layer and the metal layer, and a material of the darkening layer comprises at least one of MoXO, MoXN, MoXON, MoXW, MoXC, or AlON, wherein a, c, and d are rational numbers greater than 0, b is a rational number greater than or equal to 0, and X is at least one of tantalum, vanadium, nickel, niobium, zirconium, tungsten, titanium, rhenium, or hafnium. The display panel and the electronic device of the present disclosure can improve display effect and display quality. 1. A display panel , comprising:a substrate, wherein a metal layer and an anti-reflection film are disposed on the substrate, the anti-reflection film is disposed on a light-emitting side of the metal layer, and the anti-reflection film comprises a protective layer and a darkening layer;{'sub': a', 'b', 'c', 'a', 'b', 'd', 'a', 'b', 'c', 'd', 'a', 'b', 'c', 'a', 'b', 'c', 'a', 'b', 'c', 'x', 'x, 'wherein the protective layer is disposed between the darkening layer and the metal layer, and a material of the darkening layer comprises at least one of MOXO, MOXN, MOXON, MOXW, MOXC, or AlON, wherein a, c, and d are rational numbers greater than 0, b is a rational number greater than or equal to 0, and X is at least one of tantalum, vanadium, nickel, niobium, zirconium, tungsten, titanium, rhenium, or hafnium, and a material of the protective layer comprises at least one of Mo, Ti, Si, SiO, or SiN,'}the metal layer comprises a first sub-metal layer and a second sub-metal layer disposed on the first sub-metal layer, the first sub-metal layer comprises a gate electrode, and the second sub-metal ...

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL

An array substrate and a manufacturing method thereof and a display panel are provided. The array substrate includes: a base substrate; a first layer, located on the base substrate, including a force electrode configured to detect a touch force; a buffer layer located on the first layer; a thin film transistor including a gate electrode located on the buffer layer; and a second layer including a force electrode wire and the gate electrode; the force electrode wire and the force electrode being electrically connected. 1. An array substrate applied for a force sensing device , comprising:a base substrate;a first layer, located on the base substrate, comprising a force electrode configured to detect a touch force;a buffer layer, located on the first layer;a thin film transistor, comprising a gate electrode located on the buffer layer; anda second layer, comprising a force electrode wire;wherein the force electrode wire and the force electrode are electrically connected; the force electrode wire is in a same layer with the gate electrode.2. The array substrate according to claim 1 , further comprising a via hole claim 1 , wherein the thin film transistor further comprises a gate insulating layer claim 1 , the gate insulating layer is located on the buffer layer claim 1 , the via hole runs through the buffer layer and the gate insulating layer claim 1 , and the force electrode wire and the force electrode are electrically connected through the via hole.3. The array substrate according to claim 2 , wherein the via hole only runs through the gate insulating layer and the buffer layer.4. The array substrate according to claim 2 , wherein a height of the via hole in a direction perpendicular to the base substrate ranges from about 1400 Å to about 3800 Å.5. The array substrate according to claim 2 , wherein a height of the via hole in a direction perpendicular to the base substrate is in a range of about 5200±364 Å.6. The array substrate according to claim 1 , wherein a ...

ARRAY SUBSTRATE AND DISPLAY DEVICE

An array substrate and a display device are disclosed. The array substrate includes a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed. Overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area. 1. An array substrate comprising a peripheral area in which a plurality of gate electrode material lines , a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed ,wherein, overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.2. The array substrate according to claim 1 , wherein the peripheral area comprises a main routing area; in the main routing area claim 1 , the source-drain material lines and the first metal lines do not have any overlapping area claim 1 , and the gate electrode material lines have overlapping areas with the source-drain material lines and the first metal lines.3. The array substrate according to claim 2 , wherein in the main routing area claim 2 , the source-drain ...

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same. 1. A method of manufacturing a display substrate comprising:forming a gate metal pattern including a gate electrode on a base substrate;forming a gate insulation layer that covers the gate metal pattern;forming an active layer on the gate insulation layer;forming a source metal layer on the active layer;forming a photoresist layer on the source metal layer;developing the photoresist layer to form a first photoresist pattern; andforming an active pattern and a source metal pattern by etching the active layer and the source metal layer while using the first photoresist pattern as a mask, depositing a first lower layer comprising molybdenum or molybdenum alloy on the active layer;', 'depositing a third lower layer comprising molybdenum nitride;', 'depositing a second lower layer comprising molybdenum or molybdenum alloy on the first lower layer;', 'depositing a low-resistance metal layer comprising aluminum or aluminum alloy on the second lower layer; and', 'depositing an upper layer comprising molybdenum or molybdenum alloy on the low-resistance metal layer, and, 'wherein forming the source metal layer compriseswherein the source metal layer is etched by a fluorine-containing gas.2. The method of claim 1 , wherein forming the source metal layer includes performing a plasma process on the first lower layer after the first lower layer is deposited.3. The ...

MANUFACTURING METHOD OF LOW TEMPERATURE POLY-SILICON TFT ARRAY SUBSTRATE

A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer. 1. A manufacturing method of a low temperature poly-silicon thin film transistor (LTPS-TFT) array substrate , comprising:sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the base substrate and the source and drain electrodes being provided on the active layer,wherein the method comprises:{'b': '1', 'Step of depositing a gate-metal-layer on the base substrate, and performing a patterning process by using a first mask to form a gate electrode;'}{'b': 2', '1, 'Step of depositing a gate insulating layer on the base substrate after Step , the gate insulating layer covering the base substrate and the gate electrode;'}{'b': 3', '2, 'Step of sequentially forming the poly-silicon layer and the data-line-metal layer on the base substrate after Step , and performing the patterning process by using a third mask to simultaneously form the active layer and the source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode; and'}{'b': 4', '3, 'Step of depositing a transparent conductive layer on the base substrate after Step , and performing a patterning process by using a fourth mask to form a pixel electrode, the pixel electrode being provided on the source and drain electrodes and the gate insulating layer.'}2. The ...

LIQUID-CRYSTAL DISPLAY

A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode. 1. A liquid-crystal display comprising:a gate line extending in a first direction;a gate electrode protruding from the gate line;a gate insulating layer arranged on the gate electrode;an active layer arranged on the gate insulating layer and insulated from the gate electrode, the active layer comprising a semiconductor material;a data line arranged on the active layer and extending in a second direction crossing the first direction;a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and comprising a plurality of source electrode branches that are separate from each other;a drain electrode separate from the source electrode, and comprising a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches;a pixel electrode defining a pixel region having a first width in the first direction and a second width in the second direction, the ...

METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND METHOD FOR FORMING THROUGH HOLE

A method for manufacturing an array substrate and a method for forming a through hole are provided. The method for manufacturing the array substrate comprise: coating photoresist in an insulating layer through-hole region on a substrate; depositing an insulating layer on the substrate provided with the photoresist in the insulating layer through-hole region; and stripping off the photoresist in the insulating layer through-hole region to form an insulating layer through hole. The manufacturing method simplifies the process of forming the insulating layer through hole. 1. A method for forming a through hole , comprising:coating photoresist in an insulating layer through-hole region on a substrate;depositing an insulating layer on the substrate provided with the photoresist in the insulating layer through-hole region; andstripping off the photoresist in the insulating layer through-hole region to form an insulating layer through hole.2. A method for manufacturing an array substrate , comprising:coating photoresist in an insulating layer through-hole region on a substrate;depositing an insulating layer on the substrate provided with the photoresist in the insulating layer through-hole region; andstripping off the photoresist in the insulating layer through-hole region to form an insulating layer through hole.3. The method for manufacturing the array substrate according to claim 2 , comprising:depositing a metal layer on a substrate;coating photoresist on the substrate provided with the metal layer;performing complete exposure and development on the photoresist in a metal layer etch region to remove the photoresist in the metal layer etch region, taking the insulating layer through-hole region as a non-exposed region, and performing half-exposure and development on the photoresist outside of the insulating layer through-hole region to reduce the thickness of the photoresist outside of the insulating layer through-hole region;etching the metal layer in the metal layer ...

THIN FILM TRANSISTOR, FABRICATION METHOD THEREOF, REPAIR METHOD THEREOF AND ARRAY SUBSTRATE

Embodiments of the present disclosure disclose a thin film transistor, a fabrication method thereof, a repair method thereof, and an array substrate. The thin film transistor comprises a gate electrode (), a gate insulating layer (), an active layer (), a source electrode () and a drain electrode (). The source electrode () comprises a first source electrode portion () and a second source electrode portion () independent from each other, the first source electrode portion () and the second source electrode portion () are electrically connected with the active layer (), respectively; and/or, the drain electrode () comprises a first drain electrode portion () and a second drain electrode portion () independent from each other, the first drain electrode portion () and the second drain electrode portion () are electrically connected with the active layer (), respectively. 1. A thin film transistor , comprising: a gate electrode , a gate insulating layer , an active layer , a source electrode and a drain electrode , wherein ,the source electrode comprises a first source electrode portion and a second source electrode portion independent from each other, the first source electrode portion and the second source electrode portion are electrically connected with the active layer, respectively; and/or,the drain electrode comprises a first drain electrode portion and a second drain electrode portion independent from each other, the first drain electrode portion and the second drain electrode portion are electrically connected with the active layer, respectively.2. The thin film transistor according to claim 1 , wherein claim 1 , the first source electrode portion and the second source electrode portion are disposed in a same layer;and the first drain electrode portion and the second drain electrode portion are disposed in a same layer.3. The thin film transistor according to claim 1 , wherein claim 1 , the source electrode and the drain electrode are disposed in a same layer ...

LIQUID CRYSTAL DISPLAY DEVICE

A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs. 1. A liquid crystal display (LCD) device , comprising:a substrate;first through third thin-film transistors (TFTs) disposed on the substrate; andfirst and second sub-pixel electrodes disposed above the first through third TFTs,whereinthe second and third TFTs share a single output terminal as their output terminals,the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, andthe second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.2. The LCD device of claim 1 , wherein the single output terminal of the second and third TFTs has a bar shape extending in a straight line along a first direction.3. The LCD device of claim 2 , wherein each of input terminals of the second and third TFTs has an outer side extending in a straight line along a second direction.4. The LCD device of claim 3 , wherein the first direction is the same as the second direction.5. The LCD device of claim 1 , wherein channels of the second and third TFTs extend in a same direction.6. The LCD device of claim 1 , further comprising:a sustain electrode, a gate line, and a data line disposed between the substrate and a layer including the first and second sub-pixel electrodes,whereincontrol terminals of the first through third TFTs are electrically connected to the gate line,input terminals of the first and second TFTs are connected to the data line, andan input terminal of the third TFT is ...

Thin film transistor, method of manufacturing the same, and electronic apparatus

A thin film transistor includes: a gate electrode and a pair of source and drain electrodes; and a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively, wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface.

THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. Source and drain electrodes of the thin film transistor each include a lower layer and an upper layer. A first passivation layer contacts the lower layer of the source and drain electrodes but does not contact the upper layer of the source and drain electrodes, and a second passivation layer is disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride. 1. A thin film transistor , comprising:a gate electrode;a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer;an insulating layer disposed between the gate electrode and the source and drain electrodes;a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor;a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; anda second passivation layer disposed on the upper layer of the source and drain electrodes.2. The thin film transistor of claim 1 , wherein the first passivation layer is disposed between the source electrode and the drain electrode and also contacts the semiconductor.3. The thin film transistor of claim 2 , wherein the second passivation layer contacts the first passivation layer claim 2 , the lower layer of the source and drain electrodes claim 2 , and the upper layer of the source and drain electrodes.4. The thin film transistor of claim 1 , wherein the first passivation comprises silicon oxide claim 1 , and the second passivation layer comprises silicon nitride. This application is divisional of U.S. ...

FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

A field effect transistor and a manufacturing method thereof are provided. The field effect transistor includes two top gate structures (C and D) and two bottom gate structures (A and B). The top gate structures (C and D) and the bottom gate structures (A and B) are opposite to each other in pair. This increases a quantity of control-voltage-induced carriers in the field effect transistor, and therefore increases an output current of the field effect transistor, improves a power gain limit frequency in high-frequency use, and makes an electric field between the top gate structures (C and D) and the bottom gate structures (A and B) more adequately cover a channel layer () between source structures ( and ) and a drain (), thereby reducing a parasitic effect in a high frequency, and further improving a frequency characteristic of the field effect transistor. 1. A field effect transistor , comprising:a substrate layer having a first gate structure and a second gate structure disposed in a groove in an upper surface of the substrate layer;a bottom gate insulation layer covering the upper surface of the substrate layer;a channel layer covering an upper surface of the bottom gate insulation layer;a top gate insulation layer covering an upper surface of the channel layer;a first source structure and a second source structure disposed on a lower surface of the top gate insulation layer;a drain disposed between the first source structure and the second source structure; anda third gate structure and a fourth gate structure disposed in a groove in an upper surface of the top gate insulation layer, wherein the third gate structure is disposed in a first projection region of the first gate structure on the top gate insulation layer and the first projection region is located between the first source structure and the drain, and wherein the fourth gate structure is disposed in a second projection region of the second gate structure on the top gate insulation layer and the second ...

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer. 1. A thin film transistor , comprising:an active layer located on one side of a substrate;a first interlayer dielectric layer located on one side of the active layer away from the substrate;a source penetrating through the first interlayer dielectric layer, and connected to the active layer;a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; anda drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.2. The thin film transistor according to claim 1 , wherein the drain further comprises:a second portion connected to the first portion and located on one side of the second interlayer dielectric layer away from the first interlayer dielectric layer, wherein the second portion is configured to be connected to a first electrode.3. The thin film transistor according to claim 2 , wherein an orthographic projection of the second portion of the drain on the substrate partially overlaps with an orthographic projection of the source on the substrate.4. The thin film transistor according to ...

DEVICES WITH STAGGERED BODY CONTACTS

The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure. 1. A structure comprising:a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length;a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; andisolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.2. The structure of claim 1 , wherein the plurality of body contacts overlap underneath the gate body along its width.3. The structure of claim 1 , wherein the gate body includes at least one notch or tab portion which extends laterally outward from the at least one side of the gate body along its width claim 1 , and each of which electrically connects to a respective body contact of the plurality of body contacts.4. The structure of claim 1 , further comprising a contact ring body which surrounds the gate structure and which electrically contacts to each of the plurality of body contacts.5. The structure of claim 4 , further comprising contact bridges electrically contacting the channel region under gate body along both of its ends and the contact ring body.6. The structure of claim 1 , wherein the semiconductor substrate material is semiconductor on insulator (SOI) technology.7. The structure of claim 6 , wherein the plurality of body contacts are staggered about ...

Thin-film transistor for electro-static discharge (esd) protection and esd protection structure

A thin-film transistor for electro-static discharge (ESD) protection and an ESD protection structure are provided. The thin-film transistor for ESD protection includes a substrate; an active layer disposed on the substrate; a gate insulating layer disposed on the active layer and on the substrate; a gate electrode disposed on the gate insulating layer and opposite to the active layer; an interlayer insulating layer disposed on the gate electrode and on the gate insulating layer; and a source electrode and a drain electrode disposed on the interlayer insulating layer and spaced apart. The source electrode has first ESD peaks, and the drain electrode has second ESD peaks facing first ESD peaks. The thin-film transistor for ESD protection has a thin-film transistor ESD path and a peak ESD path by disposing opposite ESD peaks on the source and drain electrodes, improving ESD efficiency, preventing circuits from being burnt, and guaranteeing product yield.

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

An array substrate, a manufacturing method thereof, and a display device including the array substrate. The array substrate includes a plurality of gate line groups and a plurality of data lines disposed on a substrate, the plurality of gate line groups intersecting with the plurality of data lines to define a plurality of pixel units arranged in an array, wherein each of the plurality of gate line groups includes a first gate line and a second gate line insulated from each other, and orthographic projections of the first gate line and the second gate line of each of the plurality of gate line groups on the substrate at least partially overlap. 1. An array substrate comprising a plurality of gate line groups and a plurality of data lines disposed on a substrate ,wherein the plurality of gate line groups intersect with the plurality of data lines to define a plurality of pixel units arranged in an array;wherein each of the plurality of gate line groups includes a first gate line and a second gate line and the first gate line and the second gate line are insulated from each other; andwherein orthographic projections of the first gate line and the second gate line of each of the plurality of gate line groups on the substrate at least partially overlap.2. The array substrate according to claim 1 , wherein each of a plurality of rows of pixel units in the array includes a plurality of pixel unit groups claim 1 , each of the plurality of pixel unit groups includes a first pixel unit and a second pixel unit claim 1 , and the first pixel unit and the second pixel unit of each of the plurality of pixel unit groups share one data line.3. The array substrate according to claim 2 , wherein in each of the plurality of pixel unit groups claim 2 , a thin film transistor of the first pixel unit is connected to a first gate line in a corresponding gate line group claim 2 , and a thin film transistor of the second pixel unit is connected to a second gate line in the corresponding ...

VERTICAL THIN FILM TRANSISTOR WITH PERFORATED OR COMB-GATE ELECTRODE CONFIGURATION AND FABRICATION METHODS FOR SAME

The present invention provides a vertical-type thin film transistor (TFT) and methods of fabricating vertical TFTs. The vertical TFT may comprise a source electrode and a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes. A semiconductor layer may be arranged in between the source electrode and the drain electrode. At least one gate electrode may be embedded in the semiconductor layer. At least one of the source electrode and the drain electrode comprise patterned electrodes. One or all of the gate electrodes, the source electrode and the drain electrode may be patterned electrodes. The patterned electrodes may comprise one or more of fingers or combs, micro perforations, a mesh structure, or a lattice structure. Back side exposed fabrication techniques may be used to fabricate various of the vertical TFT embodiments. 1. A vertical TFT , comprising:a source electrode;a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes;a semiconductor layer arranged in between the source electrode and the drain electrode; andat least one gate electrode embedded in the semiconductor layer;wherein at least one of the source electrode and the drain electrode comprise patterned electrodes.2. The vertical TFT in accordance with claim 1 , wherein the source electrode and the drain electrode each comprise patterned electrodes.3. The vertical TFT in accordance with claim 2 , wherein:the source electrode comprises a first comb-like structure comprising one or more electrically connected fingers; andthe drain electrode comprises a second comb-like structure comprising one or more electrically connected fingers.4. The vertical TFT in accordance with claim 3 , wherein the at least one gate electrode also comprises a patterned electrode.5. The vertical TFT in accordance with claim 4 , wherein the at least one gate electrode comprises a third comb-like structure comprising one or ...

PRODUCTION METHOD OF THIN-FILM TRANSISTOR, THIN-FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY PANEL

There are provided a thin-film transistor and a production method thereof, an array substrate, and a display panel. The method comprises forming an active layer, a gate insulating layer, and a gate electrode on a substrate, wherein conductor conversion treatment is performed on both sides of the homogeneous active material layer to obtain an active layer, and the active layer comprises conductor regions located at both sides and a non-conductor region located at the center, wherein a projection of the gate electrode on the substrate is within a projection of the non-conductor region on the substrate, and the distances from the projection of the gate electrode to projections of the two conductor regions on the substrate are each between 0 micrometer and 1 micrometer. 1. A production method of a thin-film transistor , comprising the steps of:a step of forming a homogeneous active material layer on a substrate;a step of performing conductor conversion treatment on both sides of the homogeneous active material layer to obtain an active layer, wherein the active layer comprises two conductor regions located at both sides and a non-conductor region located at the center;a step of forming a gate insulating layer located only on the non-conductor region;a step of forming a gate electrode layer located on the gate insulating layer; anda step of forming a source electrode and a drain electrode electrically connected to the two conductor regions of the active layer, respectively;wherein an orthographic projection of the gate electrode layer on the substrate is within an orthographic projection of the non-conductor region on the substrate, and the distances from the orthographic projection of the gate electrode layer on the substrate to orthographic projections of the two conductor regions on the substrate are each between 0 micrometer and 1 micrometer.2. The production method according to claim 1 , wherein the steps are performed claim 1 , in this order:the step of forming a ...

DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

The present invention provides a display substrate and a manufacturing method thereof. The display substrate of the present invention comprises a first structure and a second structure; wherein, the second structure is provided with a lap portion disposed on the first structure and a main body portion connected with the lap portion and outside the first structure; the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that outside the thinned region; and at least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region. 1. A display substrate , comprising a first structure and a second structure;wherein, the second structure is provided with a lap portion disposed on the first structure, and a main body portion disposed outside the first structure and connected with the lap portion;the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that of the first structure outside the thinned region; andat least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region.2. The display substrate according to claim 1 , wherein claim 1 ,the display substrate is an array substrate, the first structure is a drain of a thin film transistor, and the second structure is a pixel electrode.3. The display substrate according to claim 2 , wherein claim 2 ,the drain is entirely disposed on an active region.4. The display substrate according to claim 1 , wherein claim 1 ,the display substrate further comprises a base, and a distance between the first structure and the base is larger than or equal to that between ...

THIN FILM TRANSISTOR STRUCTURES WITH REGROWN SOURCE & DRAIN

Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility. 1. An integrated circuit (IC) structure , comprising:one or more levels of metallization; and a source material separated from a drain material by a first length of channel material, wherein the channel material has a first composition, and the source material and the drain material have a second composition, different than the first composition;', 'a gate electrode separated from the channel, source and drain materials by one or more gate dielectric materials, wherein the gate electrode has a second length, in a direction parallel to the first length, that is larger than the first length;', 'a source contact metallization coupled to the source material, and a drain contact metallization coupled to the drain material., 'a transistor structure over at least one of the levels of metallization, the transistor structure comprising2. The IC structure of claim 1 , wherein the channel material has a first microstructure and each of the source material and the drain material have a second microstructure claim 1 , and wherein a boundary between the first and second microstructures overlaps the second length.3. The IC structure of claim 1 , wherein the channel material has a first thickness and wherein at least a first portion the source material and at least a first portion of the drain material have a ...

TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

The present invention provides a TFT array substrate and a manufacturing method thereof. The TFT array substrate has a source electrode () and a drain electrode (), which each include, stacked from bottom to top, a first molybdenum layer (), a first aluminum layer (), a second aluminum layer (), and a second molybdenum layer (). The first aluminum layer () and the second aluminum layer () each have a surface including a plurality of spikes () formed and distributed thereon. The spikes () of the second aluminum layer () have a height greater than a height of the spikes () of the first aluminum layer () such that the source electrode () and the drain electrode () each have an upper surface exhibiting a rough surface having irregularity comprising raised and recessed portion. Compared to a flat smooth surface that is involved in the prior art, the rough surface having irregularity comprising raised and recessed portions helps expand contact area between the drain electrode () and the pixel electrode () so as to reduce contact impedance between a TFT and the pixel electrode and improve performance of a liquid crystal display panel. 1. A thin-film transistor (TFT) array substrate , comprising: a backing plate , a light-shielding layer arranged on the backing plate , a buffer layer set on and covering the light-shielding layer and the backing plate , a poly-silicon semiconductor layer arranged on the buffer layer and corresponding to the light-shielding layer , a gate insulation layer set on and covering the poly-silicon semiconductor layer and the buffer layer , a gate electrode arranged on the gate insulation layer and corresponding to the poly-silicon semiconductor layer , an interlayer insulation layer set on and covering the gate electrode and the gate insulation layer , a source electrode and a drain electrode arranged on the interlayer insulation layer , a planarization layer set on and covering the source electrode , the drain electrode , and the interlayer ...

THIN FILM TRANSISTOR, DISPLAY APPARATUS COMPRISING THE SAME, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING DISPLAY APPARATUS

A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer. 1. A thin film transistor (TFT) , comprising:a substrate including a first area, a second area adjacent to one side of the first area, and a third area adjacent to another side of the first area;a polysilicon layer on the substrate; anda source electrode and a drain electrode on the polysilicon layer in the first and third areas, each of the source electrode and the drain electrode including a metal silicide layer adjacent the polysilicon layer.2. The TFT as claimed in claim 1 , wherein each of the source and drain electrodes includes an additional metal layer that contacts an upper surface of the metal silicide layer.3. The TFT as claimed in claim 2 , wherein the metal silicide layer includes a silicide of a material included in the additional metal layer.4. The TFT as claimed in claim 2 , wherein the additional metal layer includes a first layer on the metal silicide layer and a second layer on the first layer.5. The TFT as claimed in claim 1 , wherein the metal silicide layer includes metal catalysts to induce crystallization of the polysilicon layer.6. The TFT as claimed in claim 5 , wherein the metal silicide layer includes a silicide of a material to getter the metal catalysts.7. The TFT as claimed in claim 5 , wherein the metal silicide layer includes a titanium silicide.8. A display apparatus claim 5 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the thin film transistor (TFT) as claimed in ; and'}a display that is electrically connected to at least one of source or drain electrodes of the TFT.9. A method of manufacturing a thin film transistor ...

Selective Polysilicon Doping for Gate Induced Drain Leakage Improvement

Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed. 1. A transistor , comprising:a source region and a drain region, which are separated by a channel region; and a first gate region having a first dopant concentration, which is adjacent the source region; and', 'a second gate region having a second dopant concentration, which is adjacent the drain region, wherein the second dopant concentration is less than the first dopant concentration., 'a gate separated from the channel region by a gate dielectric, the gate comprising2. The transistor of claim 1 ,wherein a first length of the first gate region is greater than a second length of the second gate region; andwherein the first and second lengths are measured along a channel length direction of the transistor.3. The transistor of claim 1 , wherein the second dopant is at least an order of magnitude less than the first dopant concentration.4. The transistor of claim 1 , further comprising a silicide layer arranged on the first gate region.5. The transistor of claim 4 , wherein a portion of the first gate region extends laterally past the silicide layer.6. ...

MANUFACTURING METHOD FOR ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL

The present discloses a manufacturing method for an array substrate, an array substrate and a display panel. The manufacturing method includes sequentially forming a first metal layer, an insulation layer, a first thin-film layer, a second metal layer and an inorganic layer on a substrate; forming a color resist layer on the inorganic layer; forming an organic layer on the inorganic layer and the color resist layer; digging a hole on the organic and the inorganic layer to form a first through hole so as to uncover a portion of the second metal layer; forming a second thin-film layer on the organic layer and the uncovered second metal layer. The present invention can reduce the damage of the metal layer and the number of the masks in the manufacturing process, and increase the yield 1. A manufacturing method for an array substrate , comprising:sequentially forming a first metal layer, an insulation layer, a first thin-film layer, an etching stop layer, a second metal layer and an inorganic layer on a substrate;forming a color resist layer on the inorganic layer;forming an organic layer on the inorganic layer and the color resist layer;digging a hole on the organic layer and the inorganic layer in order to form a first through hole to make a portion of the second metal layer to be uncovered; andforming a second thin-film layer on the organic layer and the portion of the second metal layer which is uncovered.2. The manufacturing method according to claim 1 , wherein claim 1 , the step of sequentially forming a first metal layer claim 1 , an insulation layer claim 1 , a first thin-film layer claim 1 , an etching stop layer claim 1 , a second metal layer and an inorganic layer on a substrate specifically includes:forming the first metal layer and patterning the first metal layer in order to form a first metal electrode and a second metal electrode;forming the insulation layer on the first metal layer and substrate, and patterning the insulation layer in order to uncover ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure relates to the field of manufacturing technologies for semiconductor devices and provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor includes: an active layer located on a plane; a source electrode, which is located on the active layer and is in contact with the active layer; a first insulation layer located on the source electrode and including a first via hole; and a drain electrode located on the first insulation layer, where the drain electrode is in contact with the active layer via the first via hole. 1. A thin film transistor , comprising:an active layer located on a plane;a source electrode, which is located on the active layer and is in contact with the active layer;a first insulation layer located on the source electrode and comprising a first via hole; anda drain electrode located on the first insulation layer, wherein the drain electrode is in contact with the active layer via the first via hole.2. The thin film transistor according to claim 1 , further comprising:a second insulation layer covering the drain electrode; anda gate electrode comprising a first portion, wherein the first portion is located on the second insulation layer and comprises a part corresponding to a region between the source electrode and the drain electrode.3. The thin film transistor according to claim 2 , wherein the gate electrode further comprises a second portion electrically connected with the first portion of the gate electrode claim 2 ,the drain electrode and the second portion of the gate electrode are at a same layer, andthe second insulation layer covers the second portion of the gate electrode and the drain electrode.4. The thin film transistor according to claim 3 , wherein the second portion of the gate electrode is located at a side of the source electrode far away from the drain electrode.5. The thin film transistor according to claim 3 , wherein the second ...

Array Substrate and Method of Forming the Same

An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns. A first through hole and a second through hole are arranged on the array substrate. One of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole. The other one of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole and is insulated from the first shielding pattern. The present invention where the array substrate and the method of forming the array substrate are proposed is related to a top-gate design. The driving ability of the TFT driving circuit still improves without increasing the original processes and production costs. 1. An array substrate , applied to a gate driver on array (GOA) circuit , the array substrate comprising a substrate , a buffer layer , a first shielding pattern , a passivation layer , a first semiconductor pattern , a gate insulating layer , a first gate pattern , an interlayer insulating layer , and two first source/drain electrode patterns formed successively on the substrate;a first through hole and a second through hole being arranged on the array substrate, one of the first source/drain electrode patterns being electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole;the other one of the first source/drain electrode patterns being electrically connected to the first semiconductor pattern through the second through hole and being insulated from the first shielding pattern;the width of the first shielding pattern being smaller than the distance of the first through hole and the second through hole so that a projection of the ...

TFT Substrate, Display Device And Manufacturing Method

A TFT substrate, a display device and a manufacturing method are disclosed. The TFT substrate includes a substrate and a first TFT structure and a second TFT structure formed on the substrate. The first TFT structure includes a first gate pattern and a first semiconductor pattern. The first semiconductor pattern is divided into a first channel region, and a first doping region and a second doping region located at two sides of the first channel region. The first channel region is disposed corresponding to the first gate pattern to form a first conductive channel under the function of first gate pattern. The first doping region is extended inside the second TFT structure as a second gate pattern of the second TFT structure. The present invention uses doping drain of a switching TFT as gate of a driving TFT to save layout space, and beneficial for realization of higher PPI. 1. A TFT substrate , comprising:a substrate; anda first TFT structure and a second TFT structure formed on the substrate;wherein, the first TFT structure includes a first gate pattern and a first semiconductor pattern, the first semiconductor pattern is divided into a first channel region, and a first doping region and a second doping region located at two sides of the first channel region, wherein, the first channel region is disposed corresponding to the first gate pattern so as to form a first conductive channel under the function of the first gate pattern, and the first doping region is extended to and inside the second TFT structure and functions as a second gate pattern of the second TFT structure.2. The TFT substrate according to claim 1 , wherein claim 1 , the second TFT structure includes a second semiconductor pattern claim 1 , the second semiconductor pattern is divided into a second channel region claim 1 , and a third doping region and a fourth doping region which are located at two sides of the second channel region claim 1 , the second channel region is disposed corresponding to a ...

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND LIQUID CRYSTAL DISPLAY PANEL

The present application discloses a thin film transistor, a method for manufacturing a thin film transistor and a liquid crystal display panel, and relates to a display technology field. The thin film transistor includes a substrate, a gate electrode layer and an insulating layer, the gate electrode layer is formed on the substrate, the insulating layer is covered on the gate layer; a semiconductor layer is formed on the insulating layer; a conductor layer is formed on the semiconductor layer; an insulating spacer layer is formed on the insulating layer; a source-drain electrode layer is formed on the conductor layer and the insulating spacer layer; a passivation layer formed on the source-drain electrode layer and the semiconductor layer; wherein the insulating spacer layer is located between the source-drain electrode layer and the semiconductor layer to solve the leakage current too large problem of the thin film transistor. 1. A liquid crystal display panel comprising a thin film transistor , wherein the thin film transistor comprises:a substrate, a gate electrode layer and an insulating layer, the gate electrode layer is disposed on the substrate, the insulating layer is covered the gate electrode layer;a semiconductor layer is disposed on the insulating layer;a conductor layer is disposed on the semiconductor layer;the semiconductor layer comprises a channel region, the channel region divides the semiconductor layer into left and right portions, the conductor layer is disposed on the left and right portions of the semiconductor layer to form two island structures;an insulating spacer layer is disposed on the insulating layer;a source-drain electrode layer is disposed on the conductor layer and the insulating spacer layer;a passivation layer is disposed on the source-drain electrode layer and the semiconductor layer;wherein the insulating spacer layer is disposed between the source-drain electrode layer and the semiconductor layer;the gate electrode layer and ...

ARRAY SUBSTRATE AND MANUFACTURING METHOD FOR ARRAY SUBSTRATE

An array substrate and a manufacturing method. The array substrate includes a substrate, multiple gate and data lines, and multiple common electrode lines parallel with the gate lines. The substrate includes a first surface. Among two adjacent gate lines and data lines, one pixel region is defined. The array substrate further includes a thin-film transistor, a common electrode, a pixel electrode and a storage capacitor disposed in the pixel region. The transistor includes a gate electrode, the first insulation layer, a channel layer, a source and drain electrode. The storage capacitor includes a first and a second conductive portion. The gate electrode, the common electrode line, the common electrode and the first conductive portion are disposed on the first surface. The channel layer, the source and drain electrode, the second conductive portion and the pixel electrode are disposed on the first insulation layer. The pixel electrode is a metal layer. 1. An array substrate , comprising:a substrate,multiple gate lines and multiple data lines which are disposed at a same side of the substrate;wherein, the substrate includes a first surface; the multiple gate lines are disposed on the first surface; the multiple gate lines are extended along a first direction and separately arranged along a second direction; the multiple data lines and the multiple gate lines are insulated by a first insulation layer; the multiple data lines are extended along the second direction and separately arranged along the first direction;the array substrate further includes multiple common electrode lines; the common electrode lines and the multiple gate lines are parallel; one common electrode line is disposed between two adjacent gate lines, and the common electrode lines and the data lines are insulated by the first insulation layer;among two adjacent gate lines and two adjacent data lines, one pixel region is defined; the array substrate further includes a thin-film transistor, a common ...

ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

An array substrate includes a plurality of pixel regions, each of which includes: a pixel electrode and a drain electrode arranged on a same layer and independent from each other. The pixel electrode and the drain electrode are connected by a conductive part that is arranged on a different layer from the layer which the pixel electrode and the drain electrode are arranged on. The pixel electrode, the drain electrode and the conductive part are separated from each other by an insulation layer. A first via hole and a second via hole penetrating through the insulation layer are formed in the insulation layer at a position corresponding to the drain electrode and at a position corresponding to the pixel electrode, respectively. The drain electrode is connected to the conductive part through the first via hole, and the pixel electrode is connected to the conductive part through the second via hole. 1. An array substrate comprising a plurality of pixel regions , wherein each of the pixel regions comprises:a pixel electrode and a drain electrode arranged on a same layer and independent from each other, wherein the pixel electrode and the drain electrode are connected by a conductive part that is arranged on a different layer from the layer which the pixel electrode and the drain electrode are arranged on,wherein the pixel electrode, the drain electrode and the conductive part are separated from each other by an insulation layer, a first via hole penetrating through the insulation layer is formed in the insulation layer at a position corresponding to the drain electrode, a second via hole penetrating through the insulation layer is formed in the insulation layer at a position corresponding to the pixel electrode, the drain electrode is connected to the conductive part through the first via hole, and the pixel electrode is connected to the conductive part through the second via hole.2. The array substrate according to claim 1 , wherein the insulation layer is a passivation ...

SEMICONDUCTOR DEVICE

There is provided a semiconductor device. An n-type transistor is formed on a (551) surface of a silicon substrate. A silicide layer region in contact with a diffusion region (heavily doped region) of the n-type transistor has a thickness not more than 5 nm. A metal layer region in contact with the silicide layer has a thickness of 25 nm (inclusive) to 400 nm (inclusive). A barrier height between the silicide layer region and the diffusion region has a minimum value in this thickness relationship. 1. A semiconductor device comprising:an n-type transistor formed on a (551) surface of a silicon substrate, wherein a silicide layer region in contact with a diffusion region (heavily doped region) of the n-type transistor has a thickness not more than 8.5 nm, a metal layer region in contact with the silicide layer has a thickness of 25 nm (inclusive) to 400 nm (inclusive), and a barrier height between the silicide layer region and the diffusion region has a minimum value in this thickness relationship.2. The semiconductor device according to claim 1 , wherein the silicide layer has a thickness of 2 nm (inclusive) to 8.5 nm (inclusive).3. The semiconductor device according to claim 1 , wherein the silicide layer in contact with the diffusion region of the n-type transistor is made essentially of one of erbium silicide and holmium silicide. This application is a continuation of International Patent Application No. PCT/JP2012/002447 filed on Apr. 6, 2012, the entire content of which is incorporated herein by reference.1. Field of the InventionThe present invention relates generally to a semiconductor device, and particular to a semiconductor device having a transistor formed on the (551) surface of a silicon semiconductor substrate.2. Description of the Related ArtConventionally, transistors have enhanced the performance mainly by shortening a channel length L and thinning the gate insulating film. However, along with the decrease in the channel length L, the problem of ...

SEMICONDUCTOR DEVICE

A decrease in on-state current in a semiconductor device including an oxide semiconductor film is suppressed. A transistor including an oxide semiconductor film, an insulating film which includes oxygen and silicon, a gate electrode adjacent to the oxide semiconductor film, the oxide semiconductor film provided to be in contact with the insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the interface with the insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. 1. (canceled)2. A semiconductor device comprising:a gate electrode;an insulating layer over the gate electrode, the insulating layer including silicon;an oxide semiconductor layer over the insulating layer, the oxide semiconductor layer including a channel formation region; a first region in direct contact with the insulating layer; and', 'a second region over the first region,, 'wherein the oxide semiconductor layer includeswherein a concentration of silicon in the first region is lower than or equal to 1.0 at. %, andwherein a concentration of silicon in the second region is lower than the concentration of silicon in the first region.3. The semiconductor device according to claim 2 , wherein the concentration of silicon included in the first region is lower than or equal to 0.1 at. %.4. The semiconductor device according to claim 2 ,wherein the insulating layer includes carbon, and{'sup': 20', '3, 'wherein a concentration of carbon in the first region is lower than or equal to 1.0×10atoms/cm.'}5. The semiconductor device according to claim 2 , wherein the oxide semiconductor layer has crystallinity.6. The ...

VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS

A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin. 1. A method of forming a semiconductor structure , comprising:forming at least one fin disposed over a top surface of a substrate, the at least one fin providing a vertical transport channel for a vertical transport field-effect transistor;forming a top source/drain region disposed over a top surface of the at least one fin;forming a first contact trench at a first end of the at least one fin and a second contact trench at a second end of the at least one fin, the first and second contact trenches being self-aligned to the top source/drain region;forming inner spacers on sidewalls of the first contact trench and the second contact trench; andforming contact material in the first contact trench and the second contact trench between the inner spacers;wherein the contact material comprises a stressor material that induces vertical strain in the at least one fin.2. The method of claim 1 , wherein:the first contact trench provides an opening that reveals a portion of a top surface of a bottom source/drain region at the first end of the at least one fin;the second contact trench provides an opening that reveals a portion of a gate ...

THIN FILM TRANSISTOR AND METHOD OF DRIVING SAME

A thin film transistor (TFT) and a method of driving the same are disclosed. The TFT includes: an active layer; a bottom gate electrode disposed below the active layer to drive a first region of the active layer; and a top gate electrode disposed on the active layer to drive a second region of the active layer. The TFT controls the conductivity of the active layer by using the bottom gate electrode and the top gate electrode. 1. A thin film transistor (TFT) comprising:an active layer;a bottom gate electrode below the active layer to drive a first region of the active layer; anda top gate electrode on the active layer to drive a second region of the active layer, the bottom and top gate electrodes configured to control the conductivity of the active layer.2. The TFT of claim 1 , wherein at least one partial region of the bottom gate electrode and the top gate electrode vertically overlap with each other.3. The TFT of claim 2 , wherein the bottom gate electrode and the top gate electrode are single gate electrodes claim 2 , respectively claim 2 , are disposed to extend in opposite directions claim 2 , and vertically overlap with each other at the at least one partial region.4. The TFT of claim 2 , wherein the bottom gate electrode includes first and second bottom gate electrodes separated from each other and the at least one partial region includes the first and second partial regions claim 2 , andthe top gate electrode is between the first and second bottom gate electrodes and vertically overlaps with the first and second bottom gate electrodes at the first and second partial regions, respectively.5. The TFT of claim 2 , wherein the top gate electrode includes first and second top gate electrodes separated from each other and the at least one partial region includes the first and second partial regions claim 2 , andthe bottom gate electrode is between the first and second top gate electrodes and vertically overlaps with the first and second top gate electrodes at the ...

PIXEL UNIT, FABRICATION METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY DEVICE

A pixel unit includes a thin film transistor, a first insulating layer, a pixel electrode, a second insulating layer, a meltable conductive component, and a common electrode. The thin film transistor includes a drain electrode. The first insulating layer is arranged over the drain electrode. The pixel electrode is arranged over the first insulating layer and electrically coupled to the drain electrode. The second insulating layer is arranged over the pixel electrode. The meltable conductive component is arranged over the second insulating layer. The common electrode is arranged over the meltable conductive component and electrically coupled to the meltable conductive component. 1. A pixel unit , comprising:a thin film transistor including a drain electrode,a first insulating layer over the drain electrode;a pixel electrode over the first insulating layer and electrically coupled to the drain electrode;a second insulating layer over the pixel electrode;a meltable conductive component over the second insulating layer; anda common electrode over the meltable conductive component and electrically coupled to the meltable conductive component.2. The pixel unit according to claim 1 , wherein:the meltable conductive component includes a common electrode line.3. The pixel unit according to claim 2 , wherein:a portion of the pixel electrode is in a via hole penetrating the first insulating layer and electrically coupled to the drain electrode; anda portion of the second insulating layer and a portion of the common electrode line are over the via hole.4. The pixel unit according to claim 3 , further comprising:a conductive connector penetrating the portion of the common electrode line over the via hole, the portion of the second insulating layer over the via hole, and the portion of the pixel electrode in the via hole to electrically couple the common electrode line to the drain electrode.5. The pixel unit according to claim 2 , wherein the common electrode overlaps with the ...

ARRAY SUBSTRATE AND DISPLAY DEVICE

An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate; wherein the base substrate is provided with at least one TFT, each of the at least one TFT includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; and wherein, at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode. 1. An array substrate comprising:a base substrate; anda first electrically conductive layer and a second electrically conductive layer on the base substrate;wherein the base substrate is provided with at least one TFT, each of the at least one TFT comprises a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; andwherein, at least one of the drain electrode and the source electrode comprises an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode.2. The array substrate according to claim 1 , wherein the first electrically conductive layer further comprises a gate line connected to the gate electrode; andthe extending portion overlaps with the gate line.3. The array substrate according to claim 2 , wherein a length of an overlapping portion of the extending portion and the gate line in a widthwise direction of the gate line is not greater than one third of a width of the gate line at the overlapping portion.4. ...

GATE DRIVER CIRCUIT, DISPLAY DEVICE USING GATE DRIVER CIRCUIT, AND METHOD OF DRIVING DISPLAY DEVICE

A gate driver circuit, a display device, and a method of driving the display device are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node. 1. A gate driver circuit , comprising:a first transistor supplying a start signal to a Q node in response to a clock;a second transistor adjusting a gate voltage of the first transistor in response to the clock;a third transistor adjusting a gate voltage of the second transistor in response to the start signal;a fourth transistor turned on depending on a voltage of the Q node and changing a voltage of a QB node;a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal;a sixth transistor turned on depending on the voltage of the Q node and supplying a gate-off voltage to an output node;a seventh transistor turned on depending on the voltage of the QB node and supplying a gate-on voltage to the output node;an eighth transistor supplying a second line control signal to the QB node in response to a line designation signal indicating a location of a n-th line, where n is a positive integer; anda ninth transistor supplying a third line control signal to the Q node in response to the line designation signal,wherein the first to third line control signals are generated independently of the start signal and ...

DISPLAY APPARATUS

Provided is a display apparatus, including a substrate including: a pixel electrode; an organic insulating film; a common electrode laminated on the organic insulating film so as to be opposed to the pixel electrode via an insulating layer; a common signal line connected to the common electrode; and a transistor configured to apply, to the pixel electrode, a voltage signal input to a signal line. The pixel electrode is connected to a source electrode of the transistor via a through hole formed through the organic insulating film. The through hole includes, in at least one extending portion formed by retreating the organic insulating film toward an outer side of the through hole, a stepped portion formed by laminating a part of the common signal line. 114-. (canceled)15. A display apparatus , comprising a substrate comprising:a thin film transistor including a semiconductor layer;a common electrode laminated on the semiconductor layer through an insulating film;a pixel electrode disposed so as to be opposed to the common electrode via an insulating layer,the pixel electrode being connected to a source electrode of the thin film transistor via a through hole formed through the insulating film,the through hole including at least one extending portion protruding from other part of the through hole,wherein a portion of the insulating layer in the extending portion of the through hole is provided with a stepped portion.16. The display apparatus according to further comprising a common signal line connected to the common electrode and disposed between the insulating film and the insulating layer claim 15 ,the stepped portion formed by laminating a part of the common signal line.17. The display apparatus according to claim 15 , wherein the insulating film is an organic insulating film.18. The display apparatus according to further comprising an another insulating layer laminated between the organic insulating film and the semiconductor layer.19. The display apparatus ...

SEMICONDUCTOR DEVICE

An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×10/cmis used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths. 1. (canceled)2. A semiconductor device comprising:a gate electrode layer;a gate insulating layer adjacent to the gate electrode layer; andan oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less,wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,wherein the oxide semiconductor layer comprises indium and zinc, andwherein an off current per micrometer in a channel width is 100 aA/μm or less when a drain voltage of 1 V to 10 V is applied.3. The semiconductor device according to claim 2 , wherein a carrier concentration of the oxide semiconductor layer is less than 1×10/cm claim 2 ,4. The semiconductor device according to claim 2 , wherein the length of the channel formed in the oxide semiconductor layer is 0.2 μm or more.5. The semiconductor device according to claim 2 , wherein a thickness of the gate insulating layer is 20 nm to 50 nm.6. The semiconductor device according to claim 2 , wherein the gate electrode layer comprises a film containing a metal element selected from aluminum claim 2 , copper ...

Organic Light Emitting Display Device

Disclosed is an organic light emitting display device that may include first and second pads on a pad area of a substrate, wherein the first pad includes a first bonding region and a first link region, and the second pad includes a second bonding region, a contact region, and a second link region. A first bonding electrode in the first bonding region is electrically connected to one or more signal lines in the active area of the device through contact holes in the first bonding region. A second bonding electrode is electrically connected to one or more signal lines of the device through contact holes in the contact region. The contact region is closer to the active area than the first bonding region. 1. A display device comprising:a substrate with an active area and a pad area;a first signal line and a second signal line in the active area; and a link region electrically connected to the first signal line; and', 'a first bonding region having a first bonding electrode for bonding to an external circuit, the first bonding region including one or more first contact holes through which the first bonding electrode is electrically connected to the link region; and, 'a first pad in the pad area and connected to the first signal line, wherein the first pad comprises a second bonding region having a second bonding electrode for bonding to the external circuit; and', 'a contact region electrically connected with the second bonding region, the contact region having one or more second contact holes through which the second bonding electrode is electrically connected to the second signal line, the contact region being closer to the active area than the first bonding region., 'a second pad in the pad area and connected to the second signal line, wherein the second pad comprises2. The display device of claim 1 , wherein a width of the first bonding region of the first pad is greater than a width of the contact region of the second pad.3. The display device of claim 1 , wherein a ...

PIXEL STRUCTURE

A pixel structure including scan lines, data lines, and sub-pixels is provided. The scan and data lines are disposed on the substrate. The sub-pixels include switch devices, contact pattern layer, color filter pattern layers, and pixel electrodes. The switch devices are electrically connected to one scan line and one data line respectively. 1. A pixel structure disposed on a substrate , the pixel structure comprising:a plurality of scan lines and a plurality of data lines disposed on the substrate, the scan lines being intersected with the data lines a plurality of switch devices, each of the switch devices being electrically connected to one of the scan lines and one of the data lines respectively;', 'a contact pattern layer;', 'a plurality of color filter pattern layers, the contact pattern layer and the color filter pattern layers being disposed on the substrate and the switch devices, wherein the contact pattern layer covers at least part of two adjacent switch devices, at least two of the color filter pattern layers each includes a patterned opening respectively, and the contact pattern layer is disposed in the patterned opening; and', 'a plurality of pixel electrodes disposed on the color filter pattern layers, the contact pattern layer, and the switch devices, at least one pixel electrode being partially disposed between the color filter pattern layer and the corresponding switch devices while electrically connected to the switch devices., 'a plurality of sub-pixels, comprising2. The pixel structure according to claim 1 , wherein each of the switch devices comprises a gate electrode electrically connected to the scan line claim 1 , a source electrode electrically connected to one of the data line correspondingly claim 1 , and a drain electrode electrically connected to one of the pixel electrode correspondingly.3. The pixel structure according to claim 1 , wherein each of the switch devices comprises a poly-silicon transistor claim 1 , and a source electrode ...

Thin Film Transistor Substrate and Display Device Including the Same

Disclosed is a thin film transistor substrate capable of preventing a circuit from being damaged by static electricity, and a display device including the same, wherein the thin film transistor substrate includes a substrate having a display area for displaying an image, and a non-display area. The circuit is disposed in the non-display area. The circuit includes a first electrode, an insulating film on the first electrode, and a second electrode on the insulating film. An edge of the first electrode facing the display area extends beyond an edge of the second electrode facing the display area. 1. A thin film transistor substrate comprising;a substrate having a display area for displaying an image, and a non-display area adjacent to the display area; anda circuit part in the non-display area, the circuit part including a first electrode, an insulating film on the first electrode, and a second electrode on the insulating film, the first electrode and the second electrode partially overlapping with each other,wherein an edge of the first electrode facing the display area extends beyond an edge of the second electrode facing the display area.2. The thin film transistor substrate according to claim 1 ,wherein the circuit part includes a transistor,wherein the first electrode is a gate electrode of the transistor, andwherein the second electrode is a drain electrode or a source electrode of the transistor.3. The thin film transistor substrate according to claim 1 , wherein the circuit part further includes a bridge pattern coupled to the second electrode claim 1 , the bridge pattern protruding towards the display area.4. The thin film transistor substrate according to claim 3 , further comprising a gate connection pattern provided with an interval from the first electrode claim 3 , wherein the gate connection pattern is electrically connected to the bridge pattern.5. The thin film transistor substrate according to claim 4 , wherein the interval between the first ...

Contacts for Highly Scaled Transistors

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium. 1. A semiconductor device , comprising:a substrate;first and second source/drain(S/D) regions;a channel between the first and second S/D regions;a gate engaging the channel; anda contact feature connecting to the first S/D region, wherein the contact feature includes a first contact layer and a second contact layer over the first contact layer, the first contact layer in physical contact with the first S/D region on at least two sides of the first S/D region.2. The semiconductor device of claim 1 , wherein the first contact layer includes one of III-V semiconductors.3. The semiconductor device of claim 1 , wherein the first contact layer includes one of InAs claim 1 , InGaAs claim 1 , InP claim 1 , and Ge.4. The semiconductor device of claim 1 , wherein the first contact layer includes a semiconductor-metal alloy.5. The semiconductor device of claim 1 , wherein:the first S/D region includes an epitaxial feature having four sides; andthe first contact layer is in direct contact with the four sides of the epitaxial feature.6. The semiconductor device of claim 1 , wherein:a bottom surface of the first contact layer is below a top surface of the first S/D region by a depth that ranges from about 5 nanometers to about 60 ...

TEST CIRCUIT, ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE

An array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area surrounding the display area. The array substrate further includes a plurality of signal lines located in the display area, a plurality of test signal lines and a plurality of test control transistors located in the non-display area and respectively corresponding to the plurality of signal lines. Each of the signal lines is connected to a respective one of the test signal lines by a respective one of the test control transistors. The plurality of test control transistors each have a channel width-to-length ratio between 10 and 200. 1. A test circuit , comprising:a plurality of test signal lines; anda plurality of test control transistors,wherein the plurality of test control transistors are configured to connect respective ones of the plurality of test signal lines to respective ones of a plurality of signal lines to be tested, andwherein each of the test control transistors has a channel width-to-length ratio between 10 and 200.2. The test circuit of claim 1 , wherein each of the test control transistors comprises an interdigital source claim 1 , an interdigital drain claim 1 , and a semiconductor film that is between the interdigital source and the interdigital drain and forms a channel.3. The test circuit of claim 2 ,wherein the interdigital source of each of the test control transistors comprises at least two first finger electrodes, a pitch between adjacent ones of the first finger electrodes is between 2 and 20 microns, and each of the first finger electrodes has a width between 2 and 20 microns and a length between 10 and 200 microns; andwherein the interdigital drain of each of the test control transistors comprises at least two second finger electrodes, a pitch between adjacent ones of the second finger electrodes is between 2 and 20 microns, and each of the second finger electrodes has a width between 2 and 20 microns and a length ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

A thin film transistor includes: a bottom gate electrode; a bottom gate electrode insulating layer, a semiconducting active layer and a first insulating layer which are disposed on the bottom gate electrode in sequence; a source electrode and a drain electrode which are disposed at a side of the first insulating layer away from the bottom gate electrode; vias disposed in the first insulating layer at positions which correspond to the source electrode and the drain electrode respectively; and ohmic contact layers disposed on and covering the semiconducting active layer at positions corresponding to the vias respectively. Each of the source electrode and the drain electrode is in contact with a corresponding one of the ohmic contact layers through a corresponding one of the vias. 1. A thin film transistor , comprisinga bottom gate electrode;a bottom gate electrode insulating layer, a semiconducting active layer and a first insulating layer which are disposed on the bottom gate electrode in sequence;a source electrode and a drain electrode which are disposed at a side of the first insulating layer away from the bottom gate electrode;vias disposed in the first insulating layer at positions which correspond to the source electrode and the drain electrode respectively; andohmic contact layers disposed on and covering the semiconducting active layer at positions corresponding to the vias respectively, wherein each of the source electrode and the drain electrode is in contact with a corresponding one of the ohmic contact layers through a corresponding one of the vias.2. The thin film transistor according to claim 1 , wherein the thin film transistor further comprises a top gate electrode located on a side of the first insulating layer away from the bottom gate electrode claim 1 , and the first insulating layer is a top gate electrode insulating layer.3. The thin film transistor according to claim 2 , wherein the top gate electrode is in a same layer and of same material as ...

FIN-TYPE GRAPHENE DEVICE

Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer. 1. A graphene device comprising:a substrate;a graphene channel layer substantially vertical to the substrate;a gate insulating layer substantially covering one side surface of the graphene channel layer;a gate electrode on the gate insulating layer; anda source electrode and a separate drain electrode on an other side surface of the graphene channel layer.2. The graphene device of claim 1 , wherein the graphene channel layer comprises a horizontal unit on a top part thereof claim 1 , the horizontal unit extending substantially parallel to the substrate in a direction of the other side surface of the graphene channel layer claim 1 , andwherein the gate insulating layer and the gate electrode overlap the horizontal unit.3. The graphene device of claim 2 , wherein the source electrode and the drain electrode each comprise a catalyst metal for growing graphene.4. The graphene device of claim 1 , wherein at least one of the source electrode and the drain electrode comprises Cu claim 1 , Fe claim 1 , Ni claim 1 , Co claim 1 , Pt claim 1 , Ir claim 1 , Pd claim 1 , or Ru.5. The graphene device of claim 1 , wherein the graphene channel layer has a height less than about 10 nm claim 1 , and the graphene device is a graphene field effect transistor.6. The graphene device of claim 1 , wherein the gate insulating layer comprises an extension unit extending on the substrate from a bottom part of the gate insulating layer in a direction of the one side surface of the graphene channel layer.7. The graphene device of claim 1 , wherein the ...

THIN FILM TRANSISTOR ARRAY PANEL

A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions. 1. A thin film transistor array panel comprising:a substrate;a gate line elongated in a first direction and comprising a first gate electrode and a second gate electrode and disposed on the substrate;a gate insulating layer on the first gate electrode and the second gate electrode;a semiconductor on the gate insulating layer; anda source electrode and a first drain electrode and a second drain electrode connected to each other disposed on the semiconductor,whereinthe first drain electrode faces the source electrode with respect to the first gate electrode, and the second drain electrode is disposed adjacent to the second gate electrode,the drain electrode comprises a plurality of first regions each having a predetermined width in the first direction, and the second drain electrode comprises a plurality of second regions each having a predetermined width in the first direction,at least one of the plurality of second regions comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, anda planar area of at least one of the plurality of second regions is different ...

ARRAY SUBSTRATE, METHOD FOR FABRICATING ARRAY SUBSTRATE, AND DISPLAY

An array substrate includes a substrate, a gate electrode, a gate insulating layer, an active layer, a source-drain electrode, and a passivation layer. A buffer layer is disposed between the source-drain electrode and the passivation layer for improving the adhesion between the source-drain electrode and the passivation layer, and the buffer layer is coated on the surface of the source-drain electrode. 1. An array substrate , comprising:a substrate;a gate electrode formed on the substrate;a gate insulating layer, formed on the substrate and covering the gate electrode;an active layer formed on the gate insulating layer;a source-drain electrode formed on the active layer; anda passivation layer covering the source-drain electrode;wherein a buffer layer is disposed between the source-drain electrode and the passivation layer for improving the adhesion between the source-drain electrode and the passivation layer, and the buffer layer is coated on the surface of the source-drain electrode.2. The array substrate according to claim 1 , wherein the buffer layer is made of a conductive material claim 1 , and the conductive material is ITO claim 1 , molybdenum alloy or titanium-contained alloy.3. The array substrate according to claim 1 , wherein the buffer layer is made of a semiconductor material claim 1 , and the semiconductor material is a metal oxide semiconductor material.4. The array substrate according to claim 1 , wherein the buffer layer is made of an insulating material claim 1 , and the insulating material is an organic insulating material or an inorganic insulating material.5. The array substrate according to claim 4 , wherein the organic insulating material is resin.6. The array substrate according to claim 4 , wherein the inorganic insulating material comprises at least one of silicon nitride claim 4 , silicon oxynitride and aluminium oxide.7. The array substrate according to claim 1 , wherein the buffer layer has a thickness of 10-200 nm.8. A method for ...

THIN FILM TRANSISTOR ASSEMBLY, ARRAY SUBSTRATE AND DISPLAY PANEL

Embodiments of the present disclosure provide a thin film transistor assembly, an array substrate and a display panel. The thin film transistor assembly includes a first thin film transistor and a second thin film transistor disposed on a substrate. The first thin film transistor includes a first source electrode, a first drain electrode, and a first active layer. The second thin film transistor includes a second source electrode. The first source electrode is disposed on a side of the first active layer facing towards the substrate. The first drain electrode is disposed on a side of the first active layer facing away from the substrate. An orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate. 1. A thin film transistor assembly comprising:a first thin film transistor and a second thin film transistor disposed on a substrate, the first thin film transistor comprises a first source electrode, a first drain electrode, and a first active layer, and the second thin film transistor comprises a second source electrode,', 'the first source electrode is disposed on a side of the first active layer facing towards the substrate,', 'the first drain electrode is disposed on a side of the first active layer facing away from the substrate, and', 'an orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate., 'wherein2. The thin film transistor assembly of claim 1 , wherein:the orthogonal projection of the second source electrode on the substrate covers the orthogonal projection of the first source electrode on the substrate.3. The thin film transistor assembly of claim 1 , wherein:the second thin film transistor further comprises a second drain electrode, and the second source electrode and the second drain electrode are disposed in a same layer as the first drain electrode.4. The thin film ...

DISPLAY DEVICE, ARRAY SUBSTRATE, AND MANUFACTURING METHOD

A display device, an array substrate, and a manufacturing method for the array substrate are disclosed. The array substrate includes a substrate base, and two gates, a source, a drain, an active layer, and a pixel electrode on the substrate base. The drain and the pixel electrode are connected together. The source and the drain contact the active layer, respectively. The two gates control the conduction and cut off of the active layer, which in turn controls the conduction and cut off between the source and the drain. Through the present disclosure, the variation of threshold voltage is effectively prevented. 1. An array substrate , comprising a substrate base , and two gates , a source , a drain , an active layer , and a pixel electrode on the substrate base , wherein the drain and the pixel electrode are connected together; the source and the drain contact the active layer , respectively; and the two gates control the conduction and cut off of the active layer , which in turn controls the conduction and cut off between the source and the drain.2. The array substrate as claimed in claim 1 , wherein the source claim 1 , the two gates claim 1 , the active layer claim 1 , the drain claim 1 , and the pixel electrode are sequentially stacked on the substrate base; and the drain and the pixel electrode are at a same level.3. The array substrate as claimed in claim 2 , further comprising a buffer layer on the substrate base claim 2 , wherein a buffer via is configured in the buffer layer claim 2 , exposing the substrate base; the source is disposed in the buffer via; and the source has a top surface level with that of the buffer layer.4. The array substrate as claimed in claim 3 , further comprising a passivation layer on the buffer layer and the source claim 3 , wherein a passivation via is configured in the passivation layer claim 3 , exposing the source; the two gates are disposed on the passivation layer oppositely across the passivation via; a gate metal claim 3 , ...

THIN FILM TRANSISTOR ARRAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME

A display device includes: a substrate including a display area at which an image is displayed with light; and a switching element on the substrate in the display area thereof. The switching element includes: a semiconductor layer; a first gate electrode; a second gate electrode connected to the first gate electrode; a fluorine-doped first insulating layer between the first gate electrode and semiconductor layer; and a fluorine-doped second insulating layer between the second gate electrode and the semiconductor layer. 1. A thin film transistor array panel comprising:a substrate including a display area at which an image is displayed with light; and a semiconductor layer;', 'a first gate electrode;', 'a second gate electrode connected to the first gate electrode;', 'a fluorine-doped first insulating layer between the first gate electrode and semiconductor layer; and', 'a fluorine-doped second insulating layer between the second gate electrode and the semiconductor layer., 'a switching element on the substrate in the display area thereof, the switching element comprising2. The thin film transistor array panel of claim 1 , whereinthe fluorine-doped first insulating layer and the fluorine-doped second insulating layer include a gate contact hole commonly defined therein, andthe second gate electrode is connected to the first gate electrode at the gate contact hole commonly defined in the fluorine-doped first and second insulating layers.3. The thin film transistor array panel of claim 1 , whereinan upper region of the fluorine-doped first insulating layer which is adjacent to the semiconductor layer includes fluorine.4. The thin film transistor array panel of claim 3 , whereina maximum thickness of the upper region of the fluorine-doped first insulating layer which includes the fluorine is about 20% or more of an entire thickness of the fluorine-doped first insulating layer.5. The thin film transistor array panel of claim 1 , whereina lower region of the fluorine-doped ...

ARRAY SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE

An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially. 112-. (canceled)13. A method for manufacturing an array substrate including a step of forming data lines , scan lines , and a light shielding metal layer on a substrate and a step of forming thin film transistors on the substrate , forming the thin film transistor includes a step of forming a gate electrode , a source electrode , a drain electrode , and an active region , both the thin film transistors and the light shielding metal layer are formed in a plurality of pixel regions defined by the scan lines and the data lines , wherein the light shielding metal layer and the data lines are formed along a direction parallel to a surface of the substrate in a same layer on the substrate in a single step , and are arranged with an interval therebetween on the substrate , the data lines being arranged under the active region , the light shielding metal layer is formed under the active region and at least partially overlaps with the active region in a projection direction , the data line is close to the source electrode and does not overlap with the active region at least partially in the projection ...

Array Substrate And Method of Manufacturing the Same, and Display Panel

The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel comprising the array substrate, for reducing a drop or height difference between surfaces of portions of a passivation layer located on either side of a source/drain electrode lead wire and a surface of a portion of passivation layer located on an upper surface of the source/drain electrode lead wire so as to increase an aperture ratio of the display panel. The method comprises: forming a source/drain electrode lead wire and a passivation layer successively on a base substrate, the passivation layer at least covering the source/drain electrode lead wire; and thinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein. 1. A method of manufacturing an array substrate , the method comprising steps of:forming a source/drain electrode lead wire and a passivation layer in turn on a base substrate, the passivation layer covering at least the source/drain electrode lead wire; andthinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.2. The method according to claim 1 , wherein the step of thinning the portion of the passivation layer located on the source/drain electrode lead wire comprises:forming a photoresist layer on the passivation layer;exposing and developing the photoresist layer with a mask so as to form a photoresist partially-remained region, a photoresist fully-removed region and a photoresist fully-remained region, the photoresist partially-remained region corresponding to the source/drain electrode lead wire and the photoresist fully- ...

BIOSENSOR

Disclosed herein is a biosensor. The biosensor includes: a mount; a bio-sensing chip disposed on the mount and including at least one thin film transistor; a reaction layer disposed on the bio-sensing chip and including at least one of a biological sample and a biochemical reaction reagent; an upper electrode disposed on an upper surface of the reaction layer and supplying electric signal to the reaction layer; and at least one pad disposed on the bio-sensing chip and electrically connected to the bio-sensing chip. The biosensor can measure voltage-current characteristics in a linear region and a saturation region through examination with respect to a target substance using the thin film transistor. 1. A biosensor comprising:a mount;a bio-sensing chip disposed on the mount and comprising at least one thin film transistor;a reaction layer disposed on the bio-sensing chip and comprising at least one of a biological sample and a biochemical reaction reagent;an upper electrode disposed on the reaction layer and supplying electric signal to the reaction layer; andat least one pad disposed on the bio-sensing chip and electrically connected to the bio-sensing chip,wherein the at least one pad comprises at least one of a readout pad, a gate driving pad, and a Vdd pad.2. The biosensor according to claim 1 , further comprising;a wall disposed on the bio-sensing chip to surround the reaction layer.3. (canceled)4. A biosensor comprising:a mount;a bio-sensing chip disposed on the mount and comprising at least one thin film transistor;a reaction layer disposed on the bio-sensing chip and comprising at least one of a biological sample and a biochemical reaction reagent;an upper electrode disposed on the reaction layer and supplying electric signal to the reaction layer; andat least one pad disposed on the bio-sensing chip and electrically connected to the bio-sensing chip,wherein the bio-sensing chip comprises a plurality of sub-cells regularly arranged and electrically connected ...

THIN FILM TRANSISTOR ARRAY PANEL

A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain electrode by reducing an area of a thin film transistor. The thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer on the gate line; a semiconductive island on the gate insulating layer; a circular drain electrode on the semiconductive island; and a source electrode disposed on the semiconductive island and shaped like a circular band bent in a direction from which the drain electrode is disposed. The gate electrode may include a circular portion that is overlapped by the drain electrode and a circular sector portion that is overlapped by the source electrode. 1. A thin film transistor array panel comprising:a substrate;a gate line on the substrate, the gate line comprising a gate electrode;a gate insulating layer on the gate line;a semiconductive island on the gate insulating layer;a circular drain electrode on the semiconductive island;a source electrode on the semiconductive island, the source electrode being shaped like a circular band bent in a direction from which the drain electrode is disposed;a protective layer on the drain and source electrodes, the protective layer having a contact hole through which the drain electrode is partially exposed; anda pixel electrode electrically coupled to the drain electrode through the contact hole,wherein the gate electrode comprises a circular portion that is overlapped by the drain electrode and a circular sector portion that is overlapped by the source electrode, andwherein the contact hole is defined in a region of the protective layer that overlaps the circular portion so as to expose the drain electrode.2. The thin film transistor array panel of claim 1 , wherein the source and drain electrodes overlap the gate electrode.3. The thin film transistor array panel of claim 1 , ...

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISLAY DEVICE

The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain. 1. An array substrate , comprising: a base substrate , and a first transistor and a second transistor on a side of the base substrate; whereinan orthographic projection of the first transistor on the base substrate and an orthographic projection of the second transistor on the base substrate are non-overlapped;the first transistor comprises: a first active layer, a first gate, a first source and a first drain, wherein the first source and the first drain are in a same layer and are both in contact with the first active layer;the second transistor comprises: a second active layer, a second gate, a second source and a second drain, wherein the second source and the second drain are on a side, close to the base substrate, of the second active layer and are both in contact with the second active layer, and the second source and the second drain are in different layers, an orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap, and the second gate is on a side, away from the base substrate, of the second active layer; andstructures in the first transistor ...

TFT SUBSTRATE AND LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME

A thin film transistor (TFT) substrate comprises a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, and wherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view. 1. A thin film transistor (TFT) substrate , comprising:a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer,wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, andwherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view.2. The TFT substrate of claim 1 , wherein the first channel portion includes a first channel part extending in a first direction claim 1 , and a second channel part extending in a second direction different from the first direction claim 1 ,wherein the second channel portion includes a third channel part extending in the first direction and overlapping the first channel part, and a fourth channel part extending in a direction different from the second direction, andwherein the first and third channel parts have a same channel length.3. The TFT substrate of claim 2 , wherein the fourth channel part further extends in a third direction different from the first and second directions.4. The TFT substrate of claim 2 , wherein the fourth ...

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL

The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via. 1. An array substrate , comprising a substrate and an insulation layer provided on the substrate , the insulation layer comprising a via therein formed by etching , wherein ,the insulation layer comprises a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.2. The array substrate according to claim 1 , wherein claim 1 ,the insulation layer consists of a first insulation sub-layer and a second insulation sub-layer provided on a side of the first insulation sub-layer far away from the substrate.3. The array substrate according to claim 2 , wherein claim 2 ,under the etching condition for forming the via, the first insulation sub-layer has an etching rate ranging from 6000 Å/min to 7000 Å/min, and the second insulation sub-layer has an etching rate ranging from 8000 Å/min to 12000 Å/min.4. The array substrate according to claim 2 , wherein claim 2 ,a ratio of a thickness of the first insulation sub-layer to that of the second insulation sub-layer is equal to or greater than 4:1.5. The array substrate according to claim 4 , wherein claim 4 ,the thickness of the first insulation sub-layer ranges from 800 Å to 1700 Å, and the thickness of the second insulation sub-layer ranges from 200 Å to 300 Å.6. The array substrate according to claim 1 , ...

SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT

A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage. 1. A semiconductor device , comprising:a substrate;a main circuit disposed over a front surface of the substrate; anda backside power delivery circuit disposed over a back surface of the substrate, wherein: a first back side insulating layer disposed over the back surface of the substrate;', 'a first main power supply wiring for supplying a first voltage;', 'a second main power supply wiring for supplying a second voltage;', 'a first local power supply wiring; and', 'a first switch coupled to the first main power supply wiring and the first local power supply wiring,, 'the backside power delivery circuit includesthe first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in the first back side insulating layer, andthe first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.2. The semiconductor device of claim 1 , wherein the switch is a thin film transistor (TFT) including:a semiconductor film having a channel region, a ...

Thin-film transistor and manufacturing method for the same

A thin-film transistor and a manufacturing method for the same are disclosed. The method includes steps of: depositing a first metal layer on a substrate; depositing a semiconductor material layer on the first metal layer, and using a first photolithography process to perform a patterning process to the semiconductor material layer in order to form a semiconductor active layer depositing a second metal layer on the first metal layer and the semiconductor active layer, and using a second photolithography process to perform a patterning process to the first metal layer and the second metal layer in order to obtain a first electrode, a second electrode, and a third electrode, wherein the first electrode and the second electrode are disposed at an interval, the first electrode is disposed on the substrate, the second electrode is disposed between the substrate and the semiconductor active layer, and the third electrode is disposed on the semiconductor active layer, projections of the second electrode and the third electrode on a horizontal plane are overlapped; the first electrode is formed by the first metal layer and the second metal layer. The fabrication of the first electrode, the second electrode, the third electrode, and the active layer can be completed by only two photolithography processes, which reduce process steps and reduce cost.

CHEMICALLY-SENSITIVE FIELD EFFECT TRANSISTORS, SYSTEMS, AND METHODS FOR MANUFACTURING AND USING THE SAME

This invention concerns chemically-sensitive field effect transistors (FETs) are preferably fabricated using semiconductor fabrication methods on a semiconductor wafer, and in preferred embodiments, on top of an integrated circuit structure made using semiconductor fabrication methods. The instant chemically-sensitive FETs typically comprise a conductive source, a conductive drain, and a channel composed of a one-dimensional (1D) or two-dimensional (2D) transistor material, which channel extends from the source to the drain and is fabricated using semiconductor fabrication techniques on top of a wafer. Such chemically-sensitive FETs, preferably configured in independently addressable arrays, may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological samples, including nucleic acid hybridization and/or sequencing reactions. 1. A chemically-sensitive field effect transistor having a multi-layered structure , comprising:a substrate layer having an extended body;a first insulating layer positioned above the extended body of the substrate layer;a second insulating layer positioned above the first insulating layer;a source electrode and a drain electrode each having a top surface and a bottom surface, the top surface separated from the bottom surface by opposing outer and inner side portions, each of the opposed side portions and each of the bottom surfaces of the source and drain electrodes being disposed within the first insulating layer, the source electrode being separated from the drain electrode by a distance;a graphene layer positioned between the first and second insulating layers and extending between the outer side portion of the source electrode and the outer side portion of the drain electrode thereby forming a channel between the source and drain electrodes, the graphene layer contacting the top surface of the source and drain electrodes; anda well structure provided in the second insulating layer, ...

DISPLAY DEVICE AND ELECTRONIC DEVICE

The number of lithography processes is reduced and a high-definition display device is provided. The display device includes a pixel portion and a driver circuit for driving the pixel portion. The pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor. The driver circuit includes a second transistor and a connection portion. The second transistor includes a metal oxide film, first and second gate electrodes that face each other with the metal oxide film positioned therebetween, source and drain electrodes over and in contact with the metal oxide film, and a first wiring connecting the first and second gate electrodes. The connection portion includes a second wiring on the same surface as the first gate electrode, a third wiring on the same surface as the source electrode and the drain electrode, and a fourth wiring connecting the second wiring and the third wiring. The pixel electrode, the first wiring, and the fourth wiring are formed using the same layer. 1. A display device comprising:a pixel portion; anda driver circuit for driving the pixel portion, a first transistor; and', 'a pixel electrode electrically connected to the first transistor,, 'wherein the pixel portion comprises a second transistor; and', 'a connection portion,, 'wherein the driver circuit comprises a metal oxide film;', 'a first gate electrode and a second gate electrode that face each other with the metal oxide film positioned therebetween;', 'a source electrode and a drain electrode over and in contact with the metal oxide film; and', 'a first wiring connecting the first gate electrode and the second gate electrode,, 'wherein the second transistor comprises a second wiring on the same surface as the first gate electrode;', 'a third wiring on the same surface as the source electrode and the drain electrode; and', 'a fourth wiring connecting the second wiring and the third wiring, and, 'wherein the connection portion compriseswherein the ...

3D Directed Self-Assembly for Nanostructures

A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels. 1. A method of forming a device , the method comprising:receiving a substrate having nano-channels positioned over the substrate and extending in a direction parallel to a working surface of the substrate, the nano-channels arranged so that first nano-channels are positioned vertically above second nano-channels in a vertical stack, the nano-channels having a gate formed all around a cross section of the nano-channels;depositing a polymer mixture on the substrate that fills open spaces around the nano-channels;causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels; andmetalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels.2. The method of claim 1 , wherein causing self-assembly of the polymer mixture comprises forming first cylinders and second cylinders claim 1 , the first cylinders formed of a first material while the second cylinders are formed of a second material claim 1 , the first and second material being different.3. The method of claim 1 , wherein metalizing the polymer cylinders ...

SEMICONDUCTOR DEVICE

A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions. 1. (canceled)2. A light-emitting device comprising:a first transistor, in a pixel;a second transistor in the pixel;a light-emitting element in the pixel; anda first to fourth conductive film,wherein the first transistor is configured to control an input of an image signal to the pixel,wherein the second transistor is configured to control a current to the light-emitting element according to the image signal,wherein the first conductive film is configured to be a gate electrode of the second transistor,wherein the second conductive film is electrically connected to one of a source region and a drain region of the second transistor,wherein the first conductive film overlaps with the second conductive film,wherein the second conductive film overlaps with a channel formation region of the second transistor,wherein the third conductive film is electrically connected to the second conductive film,wherein the third conductive film overlaps with the fourth conductive film,wherein the fourth conductive film is electrically connected to one of a source region and a drain region of the first transistor,wherein the fourth conductive film is configured to supply the image signal to the pixel,wherein a semiconductor film which comprises the channel formation region of the second transistor has a bent-shape in the channel formation region of the second transistor,wherein ...

Semiconductor device and fabrication method thereof

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

THIN FILM TRANSISTOR SUBSTRATES, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICES INCLUDING THE SAME

A thin film transistor substrate includes a data line, a gate line, a gate electrode, a source electrode, a first drain electrode, a semiconductor layer and a second drain electrode. The data line and the gate line cross each other on a base substrate. The gate electrode is electrically connected to the gate line. The source electrode is electrically connected to the data line. The first drain electrode and the source electrode face each other. The semiconductor layer serves as a channel between the source electrode and the first drain electrode. The second drain electrode is disposed on the first drain electrode. The second drain electrode is electrically connected to the first drain electrode. 1. A thin film transistor substrate , comprising:a data line and a gate line which cross each other on a base substrate;a gate electrode of a thin film transistor, electrically connected to the gate line;a source electrode of the thin film transistor, electrically connected to the data line;a first drain electrode of the thin film transistor, which faces the source electrode;a semiconductor layer which serves as a channel of the thin film transistor, between the source electrode and the first drain electrode; anda second drain electrode of the thin film transistor, on the first drain electrode, wherein the second drain electrode is electrically connected to the first drain electrode.2. The thin film transistor substrate of claim 1 , wherein the second drain electrode comprises a land portion which is connected to a pixel electrode contact of a display device.3. The thin film transistor substrate of claim 1 , wherein the second drain electrode is in a different layer from that of the first drain electrode.4. The thin film transistor substrate of claim 1 , further comprising a first contact which electrically connects the first drain electrode and the second drain electrode to each other.5. The thin film transistor substrate of claim 1 , wherein the channel extends in a ...

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

An array substrate, a liquid crystal display panel and a liquid crystal display device are disclosed. The present invention designs that a width of the gate electrode is less than a width of an active layer of a thin-film transistor, and is greater than a width of a channel. Through shortening the width of the gate electrode, decreasing an overlapping region between the source electrode and the gate electrode and between the drain electrode and the gate electrode, a parasitic capacitance between the source electrode, the drain electrode and the gate electrode is reduced in order to increase the display quality. 1. An array substrate , comprising:an underlying substrate;a gate electrode formed on the underlying substrate;a gate insulation layer formed on the underlying substrate and covering the gate electrode;an active layer formed on the gate insulation layer and located above the gate electrode, wherein, the active layer includes a polysilicon semiconductor layer and an ohmic contact layer which are sequentially formed above the gate insulation layer; a side of the polysilicon semiconductor layer back to the gate electrode is provided with a channel; the ohmic contact layer is located above the channel, and provided with a slit communicated with the channel; an orthographic projection of the active layer on the underlying substrate covers the gate electrode and a portion of the underlying substrate located at two terminals of the gate electrode; an orthographic projection of the channel on the underlying substrate is located inside a region where the gate electrode is located;a protection layer formed on the channel; anda source electrode and a drain electrode formed on the active layer and respectively located at two terminals of the active layer.2. The array substrate according to claim 1 , wherein claim 1 , an orthographic projection of the source electrode on the underlying substrate is partially overlapped with the gate electrode claim 1 , and an orthographic ...

METHOD OF FORMING PATTERNED METAL FILM LAYER AND PREPARATION METHOD OF TRANSISTOR AND ARRAY SUBSTRATE

A method of forming a patterned metal film layer and preparation methods of a transistor and an array substrate are disclosed, in the technical field of displays. The method of forming a patterned metal film layer of the invention comprises: sequentially depositing a sacrificial layer and a photoresist layer on a substrate, and forming a patterned sacrificial layer and a patterned photoresist layer overlying on the patterned sacrificial layer by exposure, development, and etching, wherein a side wall of the patterned sacrificial layer adjacent to a patterned metal film layer to be formed forms a chamfer; depositing a metal film layer on the substrate after finishing the above step, and removing the patterned photoresist layer and the sacrificial layer to form a patterned metal film layer. 1. A method of forming a patterned metal film layer , comprising:sequentially depositing a sacrificial layer and a photoresist layer on a substrate, and forming a patterned sacrificial layer and a patterned photoresist layer overlying on the patterned sacrificial layer by exposure, development, and etching, wherein a side wall of the patterned sacrificial layer adjacent to a patterned metal film layer to be formed forms a chamfer;depositing a metal film layer on the substrate after finishing sequentially depositing the sacrificial layer and a photoresist layer on the substrate and forming the patterned sacrificial layer and the patterned photoresist layer overlying on the patterned sacrificial layer, wherein an upper surface of the sacrificial layer is higher than an upper surface of the patterned metal film layer to be formed; andremoving the patterned photoresist layer and the sacrificial layer to form the patterned metal film layer.2. The method of forming a patterned metal film layer according to claim 1 , wherein before depositing the metal film layer claim 1 , the method further comprises:depositing an adhesion layer.3. The method of forming a patterned metal film layer ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A thin film transistor includes a substrate, a gate electrode disposed on the substrate, a channel layer located on the gate electrode, a gate insulation layer disposed between the gate electrode and the channel layer, an etching stop layer disposed on the channel layer, and a source electrode and a drain electrode disposed on the etching stop layer. The gate electrode has multiple through holes, the etching stop layer has multiple contact holes overlapped with the through holes in a direction perpendicular to the substrate, and the source and drain electrodes are respectively electrically connected to the channel layer through the contact holes. A method of manufacturing the thin film transistor, where the contact holes in the etching stop layer are formed by backside exposure using the gate electrode as a mask. A conductivity of a region of the channel layer exposed by the contact holes has a great conductivity. 1. A thin film transistor , comprising:a substrate;a gate electrode, disposed on the substrate, and having a plurality of through holes;a channel layer, located on the gate electrode;a gate insulation layer, disposed between the gate electrode and the channel layer;an etching stop layer, disposed on the channel layer, and having a plurality of contact holes overlapped with the through holes in a direction perpendicular to the substrate; anda source electrode and a drain electrode, disposed on the etching stop layer and respectively electrically connected to the channel layer through the contact holes.2. The thin film transistor according to claim 1 , wherein edges of the through holes are substantially aligned to edges of the contact holes.3. The thin film transistor according to claim 1 , wherein the channel layer further comprises a first channel region and a second channel region claim 1 , the first channel region is electrically connected to the source electrode and the drain electrode respectively through the contact holes claim 1 , and the second ...

THIN FILM TRANSISTOR, DISPLAY PANEL AND DISPLAY APPARATUS

Disclosed is a thin film transistor, including a gate electrode, a source electrode and a drain electrode. The source electrode includes a loop structure with an opening, and a width of the opening is less than a maximum width of an inner ring of the loop structure of the source electrode in a direction identical to a direction of the width of the opening. The drain electrode is surrounded by the loop structure, and is not in contact with the source electrode. The drain electrode is distant from the inner ring of the loop structure of the source electrode at a same interval. 1. A thin film transistor (TFT) , comprising a gate electrode , a source electrode and a drain electrode ,wherein the source electrode comprises a loop structure with an opening, a width of the opening is less than a maximum width of an inner ring of the loop structure of the source electrode in a direction identical to a direction of the width of the opening;the drain electrode is surrounded by the loop structure, and is not in contact with the source electrode; andthe drain electrode is distant from the inner ring of the loop structure of the source electrode at a same interval.2. The TFT according to claim 1 , wherein the loop structure is a rectangular or round loop structure with an opening.3. The TFT according to claim 2 , wherein when the loop structure is the round loop structure claim 2 , the source electrode further comprises a projecting portion arranged inside the round loop structure and connected to the round loop structure.4. The TFT according to claim 1 , wherein the drain electrode is of a shape scaled down from that of the inner ring of the loop structure of the source electrode.5. The TFT according to claim 2 , wherein the drain electrode is of a shape scaled down from that of the inner side of the loop structure of the source electrode.6. The TFT according to claim 3 , wherein the drain electrode is of a shape scaled down from that of the inner side of the loop structure of ...

THIN FILM TRANSISTOR AND DISPLAY SUBSTRATE HAVING THE SAME

A display substrate includes a base substrate, a semiconductor active layer disposed on the base substrate, a gate insulating layer disposed on the semiconductor active layer, a first conductive pattern group disposed on the gate insulating layer and including at least a gate electrode, a second conductive pattern group insulated from the first conductive pattern group and including at least a source electrode, a drain electrode, and a data pad. The second conductive pattern group includes a first conductive layer and a second conductive layer disposed on the first conductive layer to prevent the first conductive layer from being corroded and oxidized. 1. A thin film transistor , comprising:a semiconductor active layer including a source region and a drain region;a gate electrode insulated from the semiconductor active layer;a source electrode contacted with the source region; and a first conductive layer including one of copper, a copper alloy, aluminum, and an aluminum alloy; and', 'a second conductive layer disposed on the first conductive layer and including a molybdenum-nickel alloy., 'each of the source and drain electrodes comprising, 'a drain electrode contacted with the drain region,'}2. The thin film transistor of claim 1 , wherein the molybdenum-nickel alloy contains nickel of about 10 at % to about 50 at % with respect to an aggregate of the molybdenum-nickel alloy.3. The thin film transistor of claim 1 , wherein each of the source electrode and the drain electrode further comprises a third conductive layer disposed under the first conductive layer and including a same material as the second conductive layer.4. The thin film transistor of claim 3 , wherein the second conductive layer and the third conductive layer comprise a molybdenum-nickel-titanium alloy.5. The display apparatus of claim 4 , wherein the molybdenum-nickel-titanium alloy contains nickel of about 15 at % to about 30 at % with respect to an aggregate of the molybdenum-nickel-titanium ...

THIN FILM TRANSISTOR AND DISPLAY DEVICE HAVING THE SAME

A thin film transistor includes a semiconductor pattern on a base substrate, the semiconductor pattern including an input area, an output area, and a channel area between the input area and the output area, a first insulating layer covering the semiconductor pattern, a control electrode on the first insulating layer, the control electrode overlapping the channel area, a second insulating layer covering the control electrode, an input electrode connected to the input area, an output electrode connected to the output area, and a heat discharge electrode on the second insulating layer, the heat discharge electrode being connected to the control electrode. 1. A thin film transistor , comprising:a semiconductor pattern on a base substrate, the semiconductor pattern including an input area, an output area, and a channel area between the input area and the output area;a first insulating layer covering the semiconductor pattern;a control electrode on the first insulating layer, the control electrode overlapping the channel area;a second insulating layer covering the control electrode;an input electrode connected to the input area;an output electrode connected to the output area; anda heat discharge electrode on the second insulating layer, the heat discharge electrode being connected to the control electrode.2. The thin film transistor as claimed in claim 1 , wherein the heat discharge electrode is connected to the control electrode through a contact hole in the second insulating layer.3. The thin film transistor as claimed in claim 2 , wherein the input electrode and the output electrode are disposed on the second insulating layer.4. The thin film transistor as claimed in claim 3 , wherein the input electrode and the output electrode are respectively connected to the input area and the output area through contact holes in the first insulating layer and the second insulating layer.5. The thin film transistor as claimed in claim 4 , wherein the heat discharge electrode is ...

DOUBLE CROSS-COUPLE FOR TWO-ROW FLIP-FLOP USING CFET

A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks. 1. A semiconductor device , comprising:a cell array including tracks and rows formed on a substrate, the tracks extending perpendicularly to the rows;a logic cell formed across two adjacent rows within the cell array, the logic cell including a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows, wherein each XC includes two cross-coupled complementary field-effect-transistors (CFETs) and each poly track is configured to function as an inter-row gate for the XCs; anda pair of signal tracks positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.2. The semiconductor device of claim 1 , wherein the plurality of poly tracks comprises:a first poly track and a second poly track that is positioned above the first poly track; anda third poly track and a fourth poly track that is positioned above the third poly track.3. The semiconductor device of claim 2 , wherein:the adjacent two rows include a first row and a second row,the CFETs include a first CFET and a second CFET in the first row and a third CFET and a fourth CFET in the second row, andthe pair of signal tracks includes a first signal track and a second signal track.4. The semiconductor device of claim 3 , wherein:the first poly track is configured to function as a lower inter-row gate for the first and third CFETs,the ...

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE

There is provided an array substrate, a manufacturing method therefor, a display panel, and a display device. The array substrate includes: a base substrate, and a gate metal pattern, a gate insulating layer and a source-drain metal pattern which are sequentially disposed on the base substrate. The gate metal pattern includes a signal line and a gate electrode, the signal line is in the peripheral area, the gate insulating layer is provided with a first via hole penetrating the gate insulating layer, the orthogonal projection of the first via hole on the base substrate and the orthogonal projection of the signal line on the base substrate have an overlapping area, the source-drain metal pattern includes a source-drain electrode wire, and the source-drain electrode wire is electrically connected to the signal line through the first via hole. The present disclosure achieves the function of protecting the signal line. 1. An array substrate , comprising a display area and a peripheral area which is around the display area , wherein the array substrate comprises:a base substrate, and a gate metal pattern, a gate insulating layer and a source-drain metal pattern which are sequentially disposed on the base substrate;wherein the gate metal pattern comprises a signal line and a gate electrode, the signal line is in the peripheral area, the gate insulating layer is provided with a first via hole penetrating the gate insulating layer, an orthogonal projection of the first via hole on the base substrate and an orthogonal projection of the signal line on the base substrate have an overlapping area, the source-drain metal pattern comprises a source-drain electrode wire, the source-drain electrode wire is electrically connected to the signal line through the first via hole, and one surface of a portion of the source-drain electrode wire in the peripheral area near the base substrate is in contact with the gate insulating layer.2. The array substrate according to claim 1 , wherein ...

Electrode Structure of a Transistor, and Pixel Structure and Display Apparatus Comprising the Same

An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width. 1. An electrode structure of a transistor , comprising: at least two first portions substantially parallel with each other and each of the first portions having a first width; and', 'at least one second portion, having a second width, and connecting the first portions to define a space having an opening; and, 'a first electrode, havinga second electrode having a body and an end portion, and the end portion via the opening disposed in part of the space;wherein the end portion has a width substantially greater than a width of the body.2. The electrode structure of claim 1 , wherein a ratio of the width of the end portion and the width of the body ranges from about 0.7 to about 2.3. The electrode structure of claim 1 , wherein the width of the body ranges from about 4 um to about 6 um.4. The electrode structure of claim 1 , wherein the width of the end portion ranges from about 4.2 um to about 8 um.5. The electrode structure of claim 1 , wherein the first width is substantially greater than the second width.6. The electrode structure of claim 1 , wherein a ratio of the first width and the second width ranges from about 1.05 to about 2.7. The electrode structure of claim 1 , wherein the first width is substantially 4 um.8. The electrode structure of claim 1 , wherein the second width ranges from about 2 um to about 3.8 um.9. The electrode structure of claim 1 , ...

SEMICONDUCTOR DEVICES INCLUDING METAL GATE PROTECTION AND METHODS OF FABRICATION THEREOF

Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer. 1. A semiconductor device structure , comprising:a gate dielectric layer;a gate electrode layer in contact with the gate dielectric layer;a first self-aligned contact (SAC) layer disposed over the gate electrode layer;an isolation layer disposed between the gate electrode layer and the first SAC layer; anda first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.2. The semiconductor device structure of claim 1 , wherein the isolation layer is formed of a dielectric material free of oxygen atoms.3. The semiconductor device structure of claim 1 , wherein the isolation layer is in contact with the first SAC layer.4. The semiconductor device structure of claim 1 , further comprising:a metal layer disposed between and in contact with the gate electrode layer and the isolation layer.5. The semiconductor device structure of claim 4 , wherein the metal layer is further in contact with the gate dielectric layer.6. The semiconductor device structure of claim 4 , wherein the first sidewall spacer is in contact with the metal layer.7. The semiconductor device structure of claim 6 , further comprising:a second sidewall spacer in contact with the first sidewall spacer.8. The semiconductor device structure of claim 7 , further comprising:a contact etch stop layer (CESL) in contact with the second sidewall spacer and the first SAC layer.9. The semiconductor device structure of claim 8 , further comprising:a source/drain ...

THIN FILM TRANSISTOR AND METHOD OF FABRICATING SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present application provides a thin film transistor, an array substrate, a display device and a method of fabricating a thin film transistor. According to embodiments of the present application, the thin film transistor includes: a substrate; a first source/drain electrode on the substrate; an active layer at a side of the first source/drain electrode facing away from the substrate; and a second source/drain electrode at a side of the active layer facing away from the first source/drain electrode. The first source/drain electrode and the second source/drain electrode are electrically connected to the active layer independently. 1. A thin film transistor , comprising:a substrate;a first source/drain electrode on the substrate;an active layer at a side of the first source/drain electrode facing away from the substrate; anda second source/drain electrode at a side of the active layer facing away from the first source/drain electrode,wherein the first source/drain electrode and the second source/drain electrode are electrically connected to the active layer independently.2. The thin film transistor of claim 1 , wherein an orthographic projection of the first source/drain electrode on the substrate at least partially overlaps with an orthographic projection of the second source/drain electrode on the substrate.3. The thin film transistor of claim 1 , wherein an orthographic projection of the active layer on the substrate has a rectangular shape.4. The thin film transistor of claim 1 , wherein an orthographic projection of the first source/drain electrode on the substrate covers an orthographic projection of the active layer on the substrate.5. The thin film transistor of claim 1 , wherein an orthographic projection of the second source/drain electrode on the substrate partially overlaps with an orthographic projection of the first source/drain electrode on the substrate.6. The thin film transistor of claim 1 , further comprising at least one of:a buffer layer between ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first oxide semiconductor layer is amorphous. The second and the third oxide semiconductor layers each have a crystalline structure. 1. (canceled)2. A semiconductor device comprising:a transistor including a channel formation region, the channel formation region comprising silicon,a first insulating layer over the transistor;a first gate electrode over the first insulating layer;a second insulating layer over the first gate electrode;a first oxide semiconductor layer over the second insulating layer, the first oxide semiconductor layer overlapping with the first gate electrode;a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer overlapping with the first gate electrode;a third oxide semiconductor layer over the second oxide semiconductor layer, the third oxide semiconductor layer overlapping with the first gate electrode;a source electrode and a drain electrode over the first oxide semiconductor layer and the second oxide semiconductor layer, the source electrode and the drain electrode electrically connected to the first oxide semiconductor layer, ...

Electrode Structure of a Transistor, and Pixel Structure and Display Apparatus Comprising the Same

An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width. 1. An electrode structure of a transistor , comprising: at least one end portion, having a first width,', 'a first portion connecting the end portion having a second width; and', 'wherein the first width is substantially greater than the second width; and, 'a first electrode having a curved shape structure defining a space having an opening, includinga second electrode having an end portion, and the end portion of the second electrode disposed in part of the space via the opening and directed to the first portion of the first electrode.2. The electrode structure of claim 1 , wherein width of at least parts of the second electrode is substantially greater than the second width.3. The electrode structure of claim 1 , further comprising a connecting section connected to one of the end portion of the first electrode or the first portion of the first electrode.4. The electrode structure of claim 1 , wherein a ratio of the first width and the second width ranges from about 1.05 to about 2.5. The electrode structure of claim 1 , wherein a ratio of width of the second electrode and the second width ranges from about 1.05 to about 2.6. A pixel structure incorporating the electrode structure of the transistor of .7. A display apparatus incorporating the electrode structure of the transistor of .8. An electrode structure of a transistor claim 1 , comprising:a first ...

Thin film transistor array panel, liquid crystal display, and method to repair the same

A method to repair a data line in a thin film transistor array panel includes, if the data line is disconnected at a disconnection portion, irradiating a laser on at least one side of the disconnected portion of the data line to short the data line and a storage electrode, and irradiating the laser to separate a portion shorted to the data line among the storage electrode to be disconnected. The storage electrode includes a first portion overlapping the data line between two adjacent gate lines and a second portion connected to the first portion and enclosing an edge of a pixel area except for a region where the first portion is formed. Two adjacent pixel areas are defined by the two adjacent gate lines and two adjacent data lines, and the storage electrode is branched between pixel electrodes.

VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS

Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs. 1. A transistor structure comprising:a source material;a channel material on a first portion of the source material;a drain material on a first portion of the channel material;a gate dielectric on a second portion of the channel material, the second portion of the channel material laterally adjacent to the first portion of the channel material, and the gate dielectric laterally adjacent to the drain material; anda gate electrode on the gate dielectric, wherein a sidewall of the gate electrode is laterally adjacent to a sidewall of the drain material.2. The transistor structure of claim 1 , further comprising a buffer material in contact with a substrate material claim 1 , wherein:the source material is on the buffer material; andthe substrate material comprises a group IV material and the buffer material comprises a Group III-V material.3. The transistor structure of claim 2 , further comprising: the buffer material is within a trench through the isolation material; and', 'the trench has a depth of at least 50 nm and a width less than 20 nm., 'an isolation material on the substrate; and wherein4. The transistor structure of claim 1 , wherein:the source material has a first conductivity type; andthe drain material has a second ...

ACTIVE DEVICE ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block. 1. An active device array substrate , comprising:a substrate;a first active device, disposed on the substrate and comprising a first gate electrode, a first semiconductor block, a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode contact the first semiconductor block and are separate from each other;a second active device, disposed on the substrate and comprising a second gate electrode, a second semiconductor block, a second source electrode and a second drain electrode, wherein the second source electrode and the second drain electrode contact the second semiconductor block and are separate from each other, and a film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode;a gate insulation layer, disposed on the substrate, wherein the first gate electrode and the second gate electrode are located between the gate insulation layer and the substrate, and the gate ...

THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF, AND ARRAY SUBSTRATE

The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer. 1. A thin film transistor , comprising a gate , a first active layer , a second active layer , a first source , a first drain , a second source and a second drain which are provided above a base substrate , whereinthe first active layer is located at a side of the gate facing the base substrate;the second active layer is located at a side of the gate facing away from the first active layer;the first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer;the second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer;each of the first drain and the second drain has a ring-like shape, the first drain surrounds the first source, and the second drain surrounds the second source; andthe first source is electrically connected with the second source, and the first drain is electrically connected with the second drain.2. The thin film transistor of claim 1 , further comprising a first conductive pattern claim 1 , a second conductive pattern claim 1 , a first insulation layer and a second insulation ...

Contacts For Highly Scaled Transistors

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium. 1. A semiconductor device , comprising:a substrate;first and second source/drain (S/D) regions;a channel between the first and second S/D regions;a gate engaging the channel; anda contact feature connecting to the first S/D region, wherein:the contact feature includes a first contact layer and a second contact layer over the first contact layer;the first contact layer has a conformal cross-sectional profile; andthe first contact layer is in contact with the first S/D region on at least two sides of the first S/D region or wraps around the first S/D region.2. The semiconductor device of claim 1 , wherein the first contact layer includes one of III-V semiconductors.3. The semiconductor device of claim 1 , wherein the first contact layer includes one of InAs claim 1 , InGaAs claim 1 , InP claim 1 , and Ge.4. The semiconductor device of claim 1 , wherein the first contact layer includes a semiconductor-metal alloy.5. The semiconductor device of claim 1 , wherein:the first S/D region includes an epitaxial feature having four sides; andthe first contact layer is in direct contact with the four sides of the epitaxial feature.6. The semiconductor device of claim 1 , wherein:a bottom surface of the first contact layer is below a top ...

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL HAVING THE THIN FILM TRANSISTOR SUBSTRATE

A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed. 1. A thin film transistor (TFT) substrate , comprising:a substrate; anda TFT, disposed on the substrate and having a gate, a gate dielectric layer, a film layer, a source and a drain, wherein the gate is disposed on the substrate, the gate dielectric layer is disposed on the gate, the film layer is disposed on the gate dielectric layer, the source and the drain are disposed on the film layer, and the source and the drain contact with the film layer respectively,wherein there is an interval between the source and the drain, and the film layer corresponding to the interval has an arc concave portion.2. The TFT substrate of claim 1 , wherein the film layer acts an etching stop layer of the TFT claim 1 , the TFT further comprises a channel layer claim 1 , the material of the channel layer is MOS disposed on the gate dielectric layer claim 1 , and the etching stop layer is disposed on the channel layer.3. The TFT substrate of claim 2 , wherein the drain and the source contact with the channel layer respectively through an opening of the etching stop layer.4. The TFT substrate of claim 3 , wherein a first thickness represents a thickness of peripheral region of the etching stop layer corresponding to the interval claim 3 , a second thickness represents a thickness of a middle region of the etching stop layer corresponding to the interval claim 3 , and the ...

SEMICONDUCTOR DEVICE HAVING A MULTI-TERMINAL TRANSISTOR LAYOUT

A semiconductor device includes a gate region, a source/drain region and an insulating layer between the gate region and the source/drain region. The source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg. 1. A semiconductor device , comprising:a gate region;a source/drain region; andan insulating layer between the gate region and the source/drain region;wherein the source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg.2. The semiconductor device according to claim 1 , wherein the third leg extends in a second direction different from the first direction.3. The semiconductor device according to claim 2 , wherein the second direction is orthogonal to the first direction.4. The semiconductor device according to claim 1 , wherein the source/drain region includes a first source/drain terminal claim 1 , a second source/drain terminal and a third source/drain terminal claim 1 , which are not overlapped with the gate region.5. The semiconductor device according to claim 4 , wherein the first source/drain terminal and the gate region define a first transistor claim 4 , the second source/drain terminal and the gate region define a second transistor claim 4 , and the third source/drain terminal and the gate region define a third transistor.6. The semiconductor device according to claim 4 , wherein one end of the third leg is connected to one end of the second leg.7. The semiconductor device according to claim 4 , further comprising a fourth source/drain region.8. The semiconductor device according to claim 7 , wherein the fourth source/drain terminal and the gate region define a fourth transistor.9. The semiconductor device according to claim 1 , wherein the third leg is disposed proximate to source/ ...

AN APPARATUS AND METHOD COMPRISING TWO DIMENSIONAL MATERIAL

An apparatus and method, the apparatus comprising: at least one electrode configured to provide an electrical connection to a channel of two dimensional material wherein the electrode comprises a conductive layer and plurality of nanostructures wherein at least some of the nanostructures comprise a conductive core and a coating of two dimensional material. 1. An apparatus comprising:at least one electrode configured to provide an electrical connection to a channel of two dimensional material, wherein the electrode comprises a conductive layer and a plurality of nanostructures, and wherein at least some of the nanostructures comprise a conductive core and a coating of two dimensional material, and wherein the coating of two dimensional material is configured to enable electron tunnelling between the conductive layer of the electrode and the conductive core of at least some of the nanostructures.2. The apparatus of wherein the conductive layer comprises metal.3. The apparatus of wherein the conductive core of at least some of the nanostructures comprises metal.4. The apparatus of wherein the nanostructures comprise at least one of: nanoparticles claim 1 , nanowires.5. The apparatus of wherein the coating of two dimensional material is formed on the conductive core of at least some of the nanostructures.6. The apparatus of y wherein the channel of two dimensional material and the coating of two dimensional material both comprise graphene.7. The apparatus of wherein the nanostructures are provided overlaying the conductive layer.8. The apparatus of wherein the channel of two dimensional material is provided overlaying the nanostructures.9. The apparatus of wherein the conductive layer is provided overlaying the nanostructures.10. The apparatus of wherein the nanostructures are provided overlaying the channel of two dimensional material.11. The apparatus of further comprising a first electrode and a second electrode and the channel of two dimensional material extends ...

REFLECTIVE LIQUID CRYSTAL DISPLAY PANEL

A reflective LCD panel includes a plurality of pixel units, each of which includes: first and second substrates, first and second scan lines, first and second data lines, a liquid crystal layer, and first, second, third, and fourth pixel structures. The first and second scan lines and the first and second data lines are disposed on the first substrate. Each of the first, second, third, and fourth pixel structures is electrically connected to one of the first and second scan lines and one of the first and second data lines, respectively. The first, second, third, and fourth pixel structures respectively include: an active component and a reflective pixel electrode electrically connected to the active component, and a reflective area ratio of the first, second, third, and fourth pixel structures is 1:2:4:8 or 2:1:4:8. Here, 16 gray scales may be displayed for achieving better visual effects. 1. A reflective liquid crystal display (LCD) panel comprising a plurality of pixel units , each pixel unit comprising:a first substrate;a first scan line, a second scan line, a first data line, and a second data line, disposed on the first substrate;a first pixel structure, a second pixel structure, a third pixel structure, and a fourth pixel structure, respectively electrically connected to one of the first scan line and the second scan line and one of the first data line and the second data line, wherein the first pixel structure, the second pixel structure, the third pixel structure, and the fourth pixel structure respectively comprise:an active component; anda reflective pixel electrode electrically connected to the active component,wherein a reflective area ratio of the first pixel structure, the second pixel structure, the third pixel structure, and the fourth pixel structure being 1:2:4:8 or 2:1:4:8;a second substrate disposed opposite to the first substrate; anda liquid crystal layer disposed between the first substrate and the second substrate.2. The reflective LCD panel ...

THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF

The present application discloses a thin film transistor comprising active layer on a base substrate; an insulating layer over fee active layer, the insulating layer comprising a source via and a drain via, each of which extending through the insulating layer; a source electrode within the source via in contact with the active layer; and a drain electrode within the drain via in contact with the active layer. 1. A thin film transistor , comprising:an active layer on a base substrate;an insulating layer over the active layer, the insulating layer comprising a source via and a drain via, each of which extending through the insulating layer;a source electrode within the source via in contact with the active layer; anda drain electrode within the drain via in contact with the active layer.2. The thin film transistor of claim 1 , wherein the source via and the drain via are completely within the insulating layer.3. The thin film transistor of claim 1 , wherein the source electrode and the drain electrode are completely within the insulating layer.4. The thin film transistor of claim 1 , wherein the active layer is made of a material comprising a polycrystalline silicon.5. The thin film transistor of claim 1 , wherein the insulating layer is on a side of the active layer distal to the base substrate.6. The thin film transistor of claim 1 , wherein the source via comprising a first source sub-via distal to the active layer and a second source sub-via proximal to the active layer claim 1 , the drain via comprising a first drain sub-via distal to the active layer and a second drain sub-via proximal to the active layer; the first source sub-via has a diameter larger than that of the second source sub-via claim 1 , and the first drain sub-via has a diameter larger than that of the second drain sub-via.7. The thin film transistor of claim 1 , further comprising a gate electrode insulated from the active layer by the insulating layer; wherein the insulating layer comprises a ...

MANUFACTURING METHOD OF THIN FILM TRANSISTOR OF DISPLAY DEVICE

A manufacturing method of a thin film transistor of a display device, the method including forming a gate insulating layer on a semiconductor layer; attaching a halftone mask onto the gate insulating layer; forming a channel region including a plurality of bridged grain lines formed; exposing the gate insulating layer of the channel region; forming a gate electrode layer on the halftone mask and the gate insulating layer; forming a gate electrode on the channel region by etching a portion corresponding to a boundary of the channel region of the gate electrode layer; removing the halftone mask; forming source/drain regions; forming an interlayer insulating layer on the gate electrode and the gate insulating layer; forming contact holes by etching the gate insulating layer and the interlayer insulating layer to expose the source/drain regions; and forming source/drain electrodes connected with the source/drain regions through the contact holes. 1. A manufacturing method of a thin film transistor of a display device , the method comprising:forming a gate insulating layer on a semiconductor layer including a polysilicon layer;attaching a halftone mask formed using a photoresist onto the gate insulating layer;forming a channel region including a plurality of bridged grain lines formed by doping impurities on the semiconductor layer;exposing the gate insulating layer of the channel region by etching a part of the halftone mask;forming a gate electrode layer on the halftone mask and the gate insulating layer;forming a gate electrode on the channel region by etching a portion corresponding to a boundary of the channel region of the gate electrode layer;removing the halftone mask;forming source/drain regions by doping impurities on both sides of the channel region of the semiconductor layer;forming an interlayer insulating layer on the gate electrode and the gate insulating layer;forming contact holes by etching the gate insulating layer and the interlayer insulating layer ...

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Provided is a thin film transistor. The thin film transistor includes a substrate, a channel part extending on the substrate in a first direction parallel to an upper surface of the substrate, source/drain electrodes connected to both ends of the channel part in the first direction, and a gate electrode spaced apart from the channel part in a second direction intersecting the first direction and parallel to the upper surface of the substrate. Each of the channel part, the source/drain electrodes, and the gate electrode is provided as a single layer. 1. A thin film transistor comprising:a substrate;a channel part extending on the substrate in a first direction parallel to an upper surface of the substrate;source/drain electrodes connected to both ends of the channel part in the first direction; anda gate electrode spaced apart from the channel part in a second direction intersecting the first direction and parallel to the upper surface of the substrate;wherein each of the channel part, the source/drain electrodes, and the gate electrode is provided as a single layer.2. The thin film transistor of claim 1 , wherein the channel part claim 1 , the source/drain electrodes claim 1 , and the gate electrode are composed of the same material.3. The thin film transistor of claim 2 , wherein the channel part and the source/drain electrodes are composed of a single body.4. The thin film transistor of claim 2 , wherein the channel part claim 2 , the source/drain electrodes and the gate electrode comprise a conductive metal oxide or a semiconductor material doped with an impurity.5. The thin film transistor of claim 1 , wherein upper surface of the channel part is located at a lower level than upper surface of the gate electrode.6. The thin film transistor of claim 1 , wherein the substrate has a recess provided between the channel part and the gate electrode claim 1 ,wherein the recess is toward the inside of the substrate from the upper surface of the substrate.7. The thin film ...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT STRUCTURES FOR SUB-FIN ELECTRICAL CONTACT

Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires. 1. An integrated circuit structure , comprising:a semiconductor island on a semiconductor substrate;a vertical arrangement of horizontal nanowires above a fin protruding from the semiconductor substrate, a channel region of the vertical arrangement of horizontal nanowires electrically isolated from the fin, wherein the fin is electrically coupled to the semiconductor island; anda gate stack over the vertical arrangement of horizontal nanowires.2. The integrated circuit structure of claim 1 , wherein the semiconductor island and the vertical arrangement of horizontal nanowires comprise a same semiconductor material.3. The integrated circuit structure of claim 2 , wherein the same semiconductor material is silicon.4. The integrated circuit structure of claim 2 , wherein the same semiconductor material is silicon germanium.5. The integrated circuit structure of claim 1 , further comprising:a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.6. The integrated circuit structure of claim 5 , further comprising:a pair of conductive contacts on the pair of epitaxial source or drain structures; anda conductive contact on the semiconductor island.7. The integrated circuit structure of claim 6 , wherein one of the pair of conductive contacts is electrically connected to the conductive contact on the semiconductor island.8. The integrated ...

THIN-FILM TRANSISTOR AND DISPLAY PANEL

The present invention provides a thin-film transistor and a display panel. The thin-film transistor includes a substrate, an active layer, an insulating layer, a metal layer, a dielectric layer, a source electrode, a drain electrode, a first through hole, a second through hole, a third through hole, and a fourth through hole. A first contact portion in a first metal layer is connected to the active layer via the first through hole, and a second contact portion is connected to the active layer via a second through hole. The source electrode is connected to the first contact portion via the third through hole, and the drain electrode is connected to the second contact portion via the fourth through hole. 1. A thin-film transistor , comprising:a substrate;an active layer disposed on the substrate;an insulating layer disposed on the active layer, and comprising a first through hole and a second through hole;a metal layer disposed on the insulating layer, and comprising a first contact portion and a second contact portion both disposed on a same layer and spaced apart from each other, the first contact portion connected to the active layer via the first through hole, the second contact portion connected to the active layer via the second through hole;a dielectric layer disposed on the metal layer, and comprising a third through hole corresponding to the first contact portion, and a fourth through hole corresponding to the second contact portion; anda source electrode and a drain electrode both disposed on a same layer on the dielectric layer, the source electrode connected to the first contact portion via the third through hole, and the drain electrode connected to the second contact portion via the fourth through hole.2. The thin-film transistor of claim 1 , wherein the metal layer further comprises a first metal sub-layer claim 1 , an insulating sub-layer claim 1 , and a second metal sub-layer claim 1 , whereinthe first metal sub-layer is disposed on the insulating ...

PIXEL STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE

Provided are a pixel structure, an array substrate and a display device. The pixel structure includes a first group of TFTs, a second group of TFTs and a pixel electrode. First group of TFTs and second group of TFTs each include at least two TFTs. Source electrodes of all TFTs in first group of TFTs are connected to a same data line, drain electrodes of all TFTs in first group of TFTs are connected to sources electrodes of all TFTs in second group of TFTs, drain electrodes of all TFTs in second group of TFTs are connected to pixel electrode, and gate electrodes of all TFTs in first group of TFTs and gate electrodes of all TFTs in second group of TFTs are connected to a same gate line. A problem that whole pixel cannot work normally caused by the breakage of area where the channel is formed is avoided. 1. A pixel structure , comprising a first group of thin film transistors , a second group of thin film transistors and a pixel electrode , the first group of thin film transistors and the second group of thin film transistors each comprising at least two thin film transistors , source electrodes of all the thin film transistors in the first group of thin film transistors being connected to a same data line , drain electrodes of all the thin film transistors in the first group of thin film transistors being connected to sources electrodes of all the thin film transistors in the second group of thin film transistors , drain electrodes of all the thin film transistors in the second group of thin film transistors being connected to the pixel electrode , and gate electrodes of all the thin film transistors in the first group of thin film transistors and gate electrodes of all the thin film transistors in the second group of thin film transistors being connected a same gate line.2. The pixel structure according to claim 1 , wherein the first group of thin film transistors comprises 2-4 thin film transistors claim 1 , and the second group of thin film transistors comprises 2- ...

STACKED NANOSHEETS BY ASPECT RATIO TRAPPING

A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material. 1. A semiconductor structure comprising:a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material, wherein each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, said sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheet of semiconductor channel material has a chevron shape.2. The semiconductor structure of claim 1 , wherein each pillar of said sacrificial III-V compound semiconductor material is located on a topmost surface of a semiconductor fin portion that extends upwards from a semiconductor substrate portion.3. The semiconductor structure of claim 2 , wherein each pillar of said sacrificial III-V compound semiconductor material and each semiconductor fin portion is surrounded by a trench dielectric material structure.4. The semiconductor structure of claim 3 , wherein a sidewall surface of a topmost portion of said trench dielectric material structure extends above a topmost surface of each pillar of said sacrificial III-V compound semiconductor material.5. The semiconductor structure of claim 3 , wherein a bottommost surface of said semiconductor channel material is laterally offset from a topmost surface of said trench dielectric ...

ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY PANEL

An array substrate, a method of manufacturing the same, and a display panel are provided, the array substrate includes a base substrate, and a pixel unit on the base substrate; and a reflective layer disposed on the base substrate and located in a portion of a region of the pixel unit, a surface of the reflective layer facing away from the base substrate includes a rugged structure. 1. An array substrate comprising:a base substrate, anda pixel unit on the base substrate; anda reflective layer disposed on the base substrate and located in a portion of a region of the pixel unit,wherein, a surface of the reflective layer facing away from the base substrate comprises a rugged structure.2. The array substrate according to claim 1 , wherein the reflective layer is made of a metal material.3. The array substrate according to claim 2 , wherein the reflective layer is made of silver.4. The array substrate according to claim 1 , further comprising:a pixel electrode disposed on the base substrate and located in the pixel unit,wherein the reflective layer is disposed between the pixel electrode and the base substrate.5. The array substrate according to claim 4 , further comprising:a thin film transistor on the base substrate,wherein the thin film transistor comprises a gate electrode, an active layer, and a source/drain electrode,wherein the reflective layer is disposed in a same layer as any one of the gate electrode, the active layer, and the source/drain electrode.6. The array substrate according to claim 5 , wherein the reflective layer is disposed in the same layer as the active layer.7. The array substrate according to claim 5 , wherein the thin film transistor is a top-gate thin film transistor claim 5 , and the array substrate further comprises:a light shielding layer between the thin film transistor and the base substrate;wherein an orthogonal projection of the gate electrode on the base substrate is located within an orthogonal projection of the light shielding layer ...

THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREFOR, ARRAY SUBSTRATE AND DISPLAY DEVICE

Provided are a thin film transistor and manufacturing method therefor, and an array substrate, and a display device. The method includes: forming a source electrode and a drain electrode on a substrate; forming a photoresist layer at the side of the source electrode and the drain electrode away from the substrate; performing exposure and developing treatment on the photoresist layer so as to obtain a photoresist pattern; successively forming a semiconductor layer, a first insulation layer and a conducting layer in sequence on at the side of the photoresist pattern away from the substrate; and removing the photoresist pattern so as to obtain an active layer a gate insulation layer and a gate electrode. 1. A method for manufacturing a thin film transistor , comprising:forming a source electrode and a drain electrode on a base substrate;forming a photoresist layer on a side of the source electrode and the drain electrode away from the base substrate;exposing and developing the photoresist layer to form a photoresist pattern;forming a semiconductor layer, a first insulation layer and a conductive layer successively on a side of the photoresist pattern away from the base substrate; andremoving the photoresist pattern to form an active layer, a gate insulation layer and a gate electrode.2. The method for manufacturing the thin film transistor according to claim 1 , wherein the source electrode and the drain electrode each contains a metal and serves as a mask for exposing the photoresist layer.3. The method for manufacturing the thin film transistor according to claim 1 , wherein a buffer layer is formed between the base substrate and the source electrode and between the base substrate and the drain electrode claim 1 , the buffer layer is configured to transmit an exposure light beam in an exposure process.4. The method for manufacturing the thin film transistor according to claim 3 , wherein the exposure light beam passes through the base substrate and the buffer layer ...

FLEXIBLE DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, FLEXIBLE DISPLAY PANEL, AND FLEXIBLE DISPLAY DEVICE

A flexible display substrate, a method for manufacturing the same, a flexible display panel, and a flexible display device. The flexible display substrate includes: a flexible base substrate including a bendable region and an unbendable region, the bendable region including a bendable edge and an unbendable edge, the unbendable edge extending in a first direction; and at least one transistor in the bendable region of the flexible base substrate, including a gate electrode, a source region, a drain region, and an active layer, wherein the active layer extends in a direction substantially parallel to the first direction. 1. A flexible display substrate , comprising:a flexible base substrate comprising a bendable region and an unbendable region, the bendable region comprising a bendable edge and an unbendable edge, the unbendable edge extending in a first direction; andat least one transistor in the bendable region of the flexible base substrate, comprising a gate electrode, a source region, a drain region, and an active layer, wherein the active layer extends in a direction substantially parallel to the first direction.2. The flexible display substrate according to claim 1 , wherein a gate insulation layer is provided between the active layer and the gate electrode claim 1 , and at least one groove is provided at at least one side of the transistor in the gate insulation layer.3. The flexible display substrate according to claim 2 , wherein the at least one groove is filled with an organic material.4. The flexible display substrate according to claim 2 , wherein at least two grooves are provided respectively at both sides of a reference axis which is an axis passing through the transistor and extending in the first direction.5. The flexible display substrate according to claim 2 , wherein the at least one groove extends through the gate insulation layer.6. The flexible display substrate according to claim 2 , further comprising a sub-interlayer insulation layer above ...