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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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31-07-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US0008232161B2

Автор: Hitoshi Matsuura, Yoshito Nakazawa, MATSUURA HITOSHI, NAKAZAWA YOSHITO

Принадлежит: Renesas Electronics Corporation, MATSUURA HITOSHI, NAKAZAWA YOSHITO, RENESAS ELECTRONICS CORP, RENESAS ELECTRONICS CORPORATION

A trench is formed so as to reach a p-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

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Номер записи: 1

12-01-2012 дата публикации

Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Номер: US20120007151A1

Автор: Hiromasa YOSHIMORI, Toshiaki Iwamatsu

Принадлежит: Renesas Electronics Corp

A high breakdown voltage circuit containing a high breakdown voltage MOSFET in LSI, unlike a quintessential internal circuit, has an operating voltage fixed in a high state due to the relation with the outside and, therefore, miniaturization by the voltage lowering can not be applied, differing from ordinary cases. Consequently, the voltage lowering of an internal circuit part results in a furthermore enlargement of occupying area in the chip. The present inventors evaluated various measures for the problem, and made it clear that such problems as compatibility with the CMOSFET circuit configuration and device configuration, etc. constitute obstacles. The present invention is a semiconductor integrated circuit device having MISFETs of an N-channel type and a P-channel type, each provided with a wave undulation on a channel surface, wherein the wave undulation provided on the channel surface of the N-channel type MISFET has a narrower pitch than that of the wave undulation provided on the channel surface of the P-channel type MISFET.

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Номер записи: 2

19-01-2012 дата публикации

interconnection structure for n/p metal gates

Номер: US20120012937A1

Автор: Han-Guan Chew, Harry-Hak-Lay Chuang, Lee-Wee Teo, Ming Zhu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

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Номер записи: 3

19-01-2012 дата публикации

Methods of manufacturing semiconductor devices

Номер: US20120015489A1

Автор: Ki-Hong Kim, Kwan-Heum Lee, Sang-Bom Kang, Soon-Wook Jung, Wook-Je Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

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Номер записи: 4

26-01-2012 дата публикации

Self-aligned silicidation for replacement gate process

Номер: US20120018816A1

Автор: Akif Sultan, Andreas Knorr, Indradeep SEN, Thorsten Kammler

Принадлежит: Globalfoundries Inc

A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

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Номер записи: 5

02-02-2012 дата публикации

Temperature monitoring in a semiconductor device by using a pn junction based on silicon/germanium materials

Номер: US20120025276A1

Автор: Anthony Mowry, Gert Burbach, Markus Forsberg, Rolf Stephan

Принадлежит: Advanced Micro Devices Inc

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

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Номер записи: 6

09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1

Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy

Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

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Номер записи: 7

16-02-2012 дата публикации

Differential stoichiometries by infusion thru gcib for multiple work function metal gate cmos

Номер: US20120037999A1

Автор: Hemanth Jagannathan, Sivananda K. Kanakasabapathy

Принадлежит: International Business Machines Corp

A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices.

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Номер записи: 8

23-02-2012 дата публикации

Method for manufacturing a semiconductor device

Номер: US20120045876A1

Автор: Hiroshi Umeda, Masaru Kadoshima, Shinsuke Sakashita, Takaaki Kawahara

Принадлежит: Renesas Electronics Corp

There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.

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Номер записи: 9

01-03-2012 дата публикации

Semiconductor device production method

Номер: US20120052645A1

Автор: Masaki HANEDA

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a tantalum-nitrogen-containing film that contains tantalum and nitrogen on the first aluminum oxide film; forming an electrically conductive film on the tantalum-nitrogen-containing film; patterning the electrically conductive film to form a gate electrode; injecting n-type impurities into the p-type region using the gate electrode as a mask; and carrying out heat treatment after the formation of the tantalum-nitrogen-containing film.

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Номер записи: 10

15-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120063212A1

Автор: Koji Miyamoto, Masahiko Kanda

Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities.

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Номер записи: 11

15-03-2012 дата публикации

Lateral Uniformity in Silicon Recess Etch

Номер: US20120064686A1

Автор: David Gerald Farber, Tom Lii

Принадлежит: Texas Instruments Inc

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

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Номер записи: 12

12-04-2012 дата публикации

Methods of Fabricating Devices Including Source/Drain Region with Abrupt Junction Profile

Номер: US20120088342A1

Автор: Changwoo Oh, Dongil Bae, Kang-ill Seo, Li Ming, Sangpil Sim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.

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Номер записи: 13

19-04-2012 дата публикации

Method for fabricating mos transistors

Номер: US20120094460A1

Автор: Pin-Chien Chu, Po-Lun Cheng

Принадлежит: Individual

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.

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Номер записи: 14

26-04-2012 дата публикации

Semiconductor device and a method for manufacturing a semiconductor device

Номер: US20120097977A1

Автор: Tadashi Yamaguchi

Принадлежит: Renesas Electronics Corp

A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.

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Номер записи: 15

03-05-2012 дата публикации

Method for growing strain-inducing materials in cmos circuits in a gate first flow

Номер: US20120104507A1

Автор: Abhishek Dube, Bo Bai, Judson R. Holt, Kathryn T. Schonenberg, Keith H. Tabakman, Linda Black, Matthew W. Stoker, Viorel C. Ontalus

Принадлежит: International Business Machines Corp

A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

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Номер записи: 16

03-05-2012 дата публикации

Method for forming a semiconductor device with stressed trench isolation

Номер: US20120108032A1

Автор: Haizhou Yin, Huilong Zhu, Zhijiong Luo

Принадлежит: Institute of Microelectronics of CAS

A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S 11 ); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S 12 ); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S 13 ); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S 14 ). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

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Номер записи: 17

31-05-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120135574A1

Автор: Naoyoshi Tamura

Принадлежит: Fujitsu Semiconductor Ltd

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

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Номер записи: 18

07-06-2012 дата публикации

Device Having Adjustable Channel Stress and Method Thereof

Номер: US20120139054A1

Автор: Dapeng Chen, Huaxiang Yin, Qiuxia Xu

Принадлежит: Institute of Microelectronics of CAS

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

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Номер записи: 19

07-06-2012 дата публикации

Semiconductor device having insulated gate field effect transistors and method of manufacturing the same

Номер: US20120142151A1

Автор: Toshiyuki Sasaki

Принадлежит: Toshiba Corp

N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.

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Номер записи: 20

14-06-2012 дата публикации

Structure and method for mobility enhanced mosfets with unalloyed silicide

Номер: US20120146092A1

Автор: Dureseti Chidambarrao, Judson R. Holt, Kern Rim, Oleg Gluschenkov, Renee T. Mo, Yaocheng Liu

Принадлежит: International Business Machines Corp

While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

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Номер записи: 21

21-06-2012 дата публикации

Low-Diffusion Drain and Source Regions in CMOS Transistors for Low Power/High Performance Applications

Номер: US20120153399A1

Автор: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper

Принадлежит: Globalfoundries Inc

The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.

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Номер записи: 22

28-06-2012 дата публикации

Transistor Comprising an Embedded Sigma-Shaped Semiconductor Alloy Having Superior Uniformity

Номер: US20120161240A1

Автор: Juergen Amon, Manfred Horstmann, Stephan Kronholz

Принадлежит: Globalfoundries Inc

When incorporating a strain-inducing semiconductor alloy in one type of sophisticated transistors, the removal of sacrificial cap materials, such as a spacer layer, sacrificial spacer elements and dielectric cap materials, may be accomplished by using, at least in a first phase of the removal process, an efficient etch stop liner material, which may thus reduce the material loss in the drain and source extension regions that are formed prior to the deposition of the strain-inducing semiconductor material. Moreover, the drain and source extension regions of the other type of transistor may be formed with superior process uniformity due to a reduced material erosion of the corresponding spacer elements.

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Номер записи: 23

12-07-2012 дата публикации

Semiconductor structures and methods of manufacturing the same

Номер: US20120175713A1

Автор: Viorel C. Ontalus, Xi Li

Принадлежит: International Business Machines Corp

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

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Номер записи: 24

19-07-2012 дата публикации

Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance

Номер: US20120181614A1

Автор: Chih Sieh Teng, Chin-Miin Shyu, Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala

Принадлежит: Individual

An IGFET ( 40 or 42 ) has a channel zone ( 64 or 84 ) situated in body material ( 50 ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( 60 and 62 or 80 and 82 ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones ( 140 and 142 or 160 and 162 ) of a p-channel IGFET ( 120 or 122 ) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

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Номер записи: 25

19-07-2012 дата публикации

Fabrication of Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications

Номер: US20120181626A1

Автор: Constantin Bulucea

Принадлежит: National Semiconductor Corp

An insulated-gate field-effect transistor ( 220 U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones ( 262 and 264 ), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line ( 136 U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion ( 262 M or 264 M) and a more lightly doped lateral extension ( 262 E or 264 E). Alternatively or additionally, a more heavily doped pocket portion ( 280 ) of the body material extends along one of the source/drain zones.

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Номер записи: 26

19-07-2012 дата публикации

Replacement gate with reduced gate leakage current

Номер: US20120181630A1

Автор: Keith Kwong Hon Wong, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Takashi Ando, Unoh Kwon

Принадлежит: International Business Machines Corp

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

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Номер записи: 27

19-07-2012 дата публикации

High-k/metal gate stack using capping layer methods, ic and related transistors

Номер: US20120184093A1

Автор: Dae-Gyu Park, Michael P. Chudzik, Naim Moumen, Vamsi K. Paruchuri, Vijay Narayanan

Принадлежит: International Business Machines Corp

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

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Номер записи: 28

16-08-2012 дата публикации

Silicon germanium film formation method and structure

Номер: US20120205749A1

Автор: Abhishek Dube, Ashima B. Chakravarti, Dominic J. Schepis

Принадлежит: International Business Machines Corp

Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

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Номер записи: 29

27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241869A1

Автор: Akihiro Usujima, Shigeo Satoh

Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

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Номер записи: 30

27-09-2012 дата публикации

Methods of fabricating semiconductor devices

Номер: US20120244670A1

Автор: Hajin LIM, Jinho Do, Kyungil Hong, Moonkyun Song, Weonhong Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

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Номер записи: 31

04-10-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120248545A1

Автор: Jiro Yugami

Принадлежит: Renesas Electronics Corp

A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z 1 and a first high-dielectric film hk 1 , and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z 1 and a second high-dielectric film hk 2. The first high-dielectric film hk 1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk 2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

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Номер записи: 32

11-10-2012 дата публикации

Semiconductor device and fabrication method

Номер: US20120256264A1

Автор: Masaki HANEDA, Masanori Terahara, Takayuki Aoyama, Yuka Kase

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

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Номер записи: 33

18-10-2012 дата публикации

Minimizing leakage current and junction capacitance in cmos transistors by utilizing dielectric spacers

Номер: US20120261672A1

Автор: Dureseti Chidambarrao, Philip J. Oldiges, Ramachandran Muralidhar, Viorel Ontalus

Принадлежит: International Business Machines Corp

A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

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Номер записи: 34

18-10-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120261759A1

Автор: Haizhou Yin, Huilong Zhu, Qingqing Liang, Zhijiong Luo

Принадлежит: Institute of Microelectronics of CAS

A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.

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Номер записи: 35

18-10-2012 дата публикации

Semiconductor Structure and Method for Manufacturing the Same

Номер: US20120261763A1

Автор: Dapeng Chen, Huaxiang Yin, Qiuxia Xu

Принадлежит: Institute of Microelectronics of CAS

The present invention relates to a semiconductor and a method for manufacturing the same. The semiconductor structure comprises an NMOS device comprising a first gate structure and a PMOS device comprising a second gate structure; a first stress liner, at least formed on both sides of the first gate structure of said NMOS device; a second stress liner, at least formed on both sides of the second gate structure of said PMOS device; wherein said first stress liner is a spin-on glass (SOG) film with tensile stress, said second stress liner is formed of a material that can introduce compressive stress into the channel of the PMOS device. The present invention can reduce the difficulty of the process of manufacturing dual stress liner using the same material, e.g. nitride, and can reduce influence of nitride having a high dielectric constant upon the device interconnect delay while still maintaining the tensile strain advantage.

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Номер записи: 36

18-10-2012 дата публикации

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Номер: US20120261765A1

Автор: Klaus Hempel, Stefanie Steiner, Sven Beyer, Thilo Scheiper

Принадлежит: Globalfoundries Inc

In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

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Номер записи: 37

01-11-2012 дата публикации

Integrated circuit device with well controlled surface proximity and method of manufacturing same

Номер: US20120273847A1

Автор: Chun-Fai Cheng, HUI Ouyang, Ming-Huan Tsai, Wei-Han Fan

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

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Номер записи: 38

01-11-2012 дата публикации

Control of threshold voltages in high-k metal gate stack and structures for cmos devices

Номер: US20120276720A1

Автор: Hemanth Jagannathan, Takashi Ando, Vijay Narayanan

Принадлежит: International Business Machines Corp

A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

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Номер записи: 39

08-11-2012 дата публикации

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

Номер: US20120280251A1

Автор: Abhishek Dube, Viorel Ontalus

Принадлежит: International Business Machines Corp

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

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Номер записи: 40

08-11-2012 дата публикации

Process Flow to Reduce Hole Defects in P-Active Regions and to Reduce Across-Wafer Threshold Voltage Scatter

Номер: US20120282763A1

Автор: Andreas Ott, Stephan Kronholz

Принадлежит: Globalfoundries Inc

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.

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Номер записи: 41

15-11-2012 дата публикации

Fin field-effect transistor and method for manufacturing the same

Номер: US20120286337A1

Автор: Huicai Zhong, Huilong Zhu, Qingqing Liang

Принадлежит: Institute of Microelectronics of CAS

Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

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Номер записи: 42

29-11-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120299058A1

Автор: Guang-Yaw Hwang, Hsiang-Ying Wang, I-Chang Wang, Shin-Chuan Huang, Yu-Hsiang Hung

Принадлежит: United Microelectronics Corp

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

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Номер записи: 43

29-11-2012 дата публикации

PMOS Threshold Voltage Control by Germanium Implantation

Номер: US20120302023A1

Автор: Peter Javorka, Stephan Kronholz

Принадлежит: Globalfoundries Inc

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region.

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Номер записи: 44

29-11-2012 дата публикации

Method of Protecting STI Structures From Erosion During Processing Operations

Номер: US20120302037A1

Автор: Hans-Juergen Thees, Joerg Radecker, Stephan Kronholz

Принадлежит: Globalfoundries Inc

Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.

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Номер записи: 45

06-12-2012 дата публикации

Method of fabricating semiconductor devices

Номер: US20120309150A1

Автор: QIYANG He, YIYING Zhang

Принадлежит: Semiconductor Manufacturing International Beijing Corp

A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

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Номер записи: 46

13-12-2012 дата публикации

Semiconductor device and method of manufacturing the semiconductor device

Номер: US20120315736A1

Автор: Gen Tsutsui, Toshiyuki Iwamoto

Принадлежит: Renesas Electronics Corp

A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.

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Номер записи: 47

10-01-2013 дата публикации

Method for Efficiently Fabricating Memory Cells with Logic FETs and Related Structure

Номер: US20130009231A1

Автор: WEI Xia, Xiangdong Chen

Принадлежит: Broadcom Corp

According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

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Номер записи: 48

24-01-2013 дата публикации

Integrated circuit having a stressor and method of forming the same

Номер: US20130020717A1

Автор: Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang, Mei-Hsuan LIN

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

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Номер записи: 49

31-01-2013 дата публикации

Methods of Forming a PMOS Device with In Situ Doped Epitaxial Source/Drain Regions

Номер: US20130029463A1

Автор: Ina Ostermay, Ralf Illgen, Stefan Flachowsky

Принадлежит: Globalfoundries Inc

Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.

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Номер записи: 50

07-02-2013 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20130032887A1

Автор: HaiBiao YAO, Jingang Wu, Yonggen He

Принадлежит: Semiconductor Manufacturing International Beijing Corp

A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.

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Номер записи: 51

21-02-2013 дата публикации

Structure having three independent finfet transistors

Номер: US20130043544A1

Автор: David P. Paulsen, Gregory J. Uhlmann, II John E. Sheets, Karl R. Erickson, Kelly L. Williams, Phil C. Paone

Принадлежит: International Business Machines Corp

A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates.

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Номер записи: 52

28-02-2013 дата публикации

Semiconductor device

Номер: US20130049091A1

Автор: Kanta Saino

Принадлежит: Elpida Memory Inc

A semiconductor device comprises an MIS field effect transistor including a channel region made of p-conductive silicon, a gate insulating film including a first insulating film having dielectric constant higher than dielectric constant of silicon dioxide, and a gate electrode. The gate electrode includes a first metal film formed on the gate insulating film and having a work function greater than a work function of intrinsic semiconductor silicon, and a p-conductive silicon film formed on the first metal film and in contact with the first metal film.

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Номер записи: 53

28-02-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130049138A1

Автор: Haizhou Yin, Huilong Zhu, Zhijiong Luo

Принадлежит: Institute of Microelectronics of CAS

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

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Номер записи: 54

14-03-2013 дата публикации

Semiconductor device with high-voltage breakdown protection

Номер: US20130062694A1

Автор: Hideyuki Akanuma, Hiroaki Nitta, Tomoyuki Furuhata

Принадлежит: Seiko Epson Corp

A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

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Номер записи: 55

28-03-2013 дата публикации

Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals

Номер: US20130075820A1

Автор: Peter Baars, Thilo Scheiper

Принадлежит: Globalfoundries Inc

When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.

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Номер записи: 56

28-03-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20130075825A1

Автор: Nishibori Masakazu, Ochiai Toshihiko, SHIMIZU Hiroharu

Принадлежит: RENESAS ELECTRONICS CORPORATION

To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. 116-. (canceled)17. A semiconductor integrated circuit device comprising:an element isolation region; anda first active region defined by the element isolation region in a semiconductor substrate,wherein the first active region is formed in the semiconductor substrate and includes a first well of a first conductivity type;wherein the first active region further includes a first region which extends in a first direction and in which a plurality of MISFETs is formed, and a second region which extends in the first direction and which feeds power to the plurality of MISFETs;wherein the first region and the second region are separated by an element isolation in planar view, and are connected with each other by the first well;wherein each gate electrode of each of the plurality of MISFETs is formed over at least the first region and extends in a second direction intersecting the first direction;wherein a plurality of first plugs are formed over each of the gate electrodes of the MISFETs, respectively;wherein a plurality of second plugs are formed over the second region and are placed along the first direction;wherein each the gate electrodes of the MISFETs includes a metal film;wherein each gate insulating film of each of the plurality of MISFETs has a dielectric constant higher than that of the silicon nitride film; andwherein when a distance between a center of the first plug and a center of the second plug is less than 2.5 times a diameter of the second plug, the second plug is not formed on the second region.18. A semiconductor integrated circuit device according to the claim 17 ,wherein a shortest distance between an edge of the first plug and an edge of the second plug is set to be larger than at least 1.5 times the diameter of the second plug.19. A semiconductor integrated circuit device according to the claim 17 ,wherein a ...

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Номер записи: 57

04-04-2013 дата публикации

Zener Diode Structure and Process

Номер: US20130082330A1

Автор: WEI Xia, Xiangdong Chen

Принадлежит: Broadcom Corp

A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

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Номер записи: 58

04-04-2013 дата публикации

LIQUID CRYSTAL DISPLAY DEVICE WITH SHIELD LINES ON DATA LINES AND THIN FILM TRANSISTOR COMPONENTS

Номер: US20130084683A1

Автор: LEE Seok Woo, Park Yung In

Принадлежит: LG DISPLAY CO., LTD.

A liquid crystal display device includes a p-type driving thin film transistor and an n-type driving thin film transistor in a non-display region, and a pixel thin film transistor connected to a gate line and a data line in a display region. The liquid crystal display device further includes a pixel electrode that covers and directly contacts a third drain electrode of the pixel thin film transistor, a shield pattern that covers and directly contacts each of the first source electrode and the first drain electrode of the p-type driving thin film transistor and the second source electrode and the second drain electrode of the n-type driving thin film transistor, and a shield line that covers and directly contacts the data line and a third source electrode of the pixel thin film transistor. 1. A method of fabricating a liquid crystal display device , comprising:forming first and second polycrystalline semiconductor patterns in p-type and n-type regions of a non-display region of a substrate, respectively, third and fourth polycrystalline semiconductor patterns in switching and storage regions of a display region of the substrate, respectively, and a storage pattern on the fourth polycrystalline semiconductor pattern, wherein the fourth polycrystalline semiconductor pattern is extended from the third polycrystalline pattern;forming a gate insulating layer on the first to fourth polycrystalline semiconductor patterns;forming a first gate electrode in the p-type region, a first metal pattern in the n-type region, a second metal pattern in the switching and storage regions, a gate line connected to the second metal pattern, on the gate insulating layer;doping first source and drain portions of the first polycrystalline semiconductor pattern with p+ ions after forming the first gate electrode and the first and second metal patterns;forming a second gate electrode from the first metal pattern in the n-type region, and a third gate electrode and a first storage electrode ...

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Номер записи: 59

11-04-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130087836A1

Автор: MATSUI Osamu, OOOKA Masato, TSUJINO Shuji

Принадлежит: Panasonic Corporation

A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction. 1. A semiconductor device comprising:a channel region disposed in a surface portion of a semiconductor substrate and having a first conductivity type;a first semiconductor region disposed under the channel region in the semiconductor substrate and having a second conductivity type;a gate region disposed in a surface portion of the channel region and having the second conductivity type; andsource/drain regions disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction and having the first conductivity type, whereinsecond semiconductor regions having a higher impurity concentration than the first semiconductor region and having the second conductivity type are further disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction, andthe second semiconductor regions each have a shallower depth than the first semiconductor region.2. The semiconductor device of claim 1 , whereinthe second semiconductor regions have a greater depth than the channel region.3. The semiconductor device of claim 1 , whereinthe gate region is spaced apart from the source/drain regions.4. The semiconductor device of claim 1 , whereinthe second semiconductor ...

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Номер записи: 60

11-04-2013 дата публикации

Method for fabricating semiconductor device

Номер: US20130087837A1

Автор: Chiu-Te Lee, Chu-Chun Chang, Chun-Mao Chiou

Принадлежит: United Microelectronics Corp

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

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Номер записи: 61

11-04-2013 дата публикации

Nitrogen passivation of source and drain recesses

Номер: US20130087857A1

Автор: Ching-Chien HUANG, Jia-Yang Ko, Ling-Sung Wang, Ying-Han CHIOU

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.

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Номер записи: 62

11-04-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130087858A1

Автор: MORITA TATSUO, NAKAZAWA Kazushi, Uemoto Yasuhiro, Yanagihara Manabu

Принадлежит: Panasonic Corporation

A bidirectional switch includes a plurality of unit cells including a first ohmic electrode , a first gate electrode , a second gate electrode , and a second ohmic electrode . The first gate electrodes are electrically connected via a first interconnection to a first gate electrode pad . The second gate electrodes are electrically connected via a second interconnection to a second gate electrode pad . A unit cell including a first gate electrode having the shortest interconnect distance from the first gate electrode pad includes a second gate electrode having the shortest interconnect distance from the second gate electrode pad 111-. (canceled)12. A semiconductor device comprising:a plurality of unit cells including a semiconductor layer formed on a substrate, and a first ohmic electrode, a first gate electrode, and a second ohmic electrode formed on the semiconductor layer, the first gate electrode being between the first ohmic electrode and the second ohmic electrode;a first gate electrode pad electrically connected to the first gate electrode;a first ohmic electrode pad electrically connected to the first ohmic electrode; anda second ohmic electrode pad electrically connected to the second ohmic electrode, whereina portion of the first ohmic electrode and a portion of the second ohmic electrode are overlapped by the first ohmic electrode pad in plan view, anda portion of the first ohmic electrode and a portion of the second ohmic electrode are overlapped by the second ohmic electrode pad in plan view.13. The semiconductor device of claim 12 , further comprising:a second gate electrode being between the first ohmic electrode and the second ohmic electrode; anda second gate electrode pad electrically connected to the second gate electrode.14. The semiconductor device of claim 13 , wherein claim 13 ,a portion of the first gate electrode and a portion of the second gate electrode are overlapped by the first ohmic electrode pad in plan view, anda portion of the first ...

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Номер записи: 63

18-04-2013 дата публикации

LAYOUT DATA CREATION DEVICE FOR CREATING LAYOUT DATA OF PILLAR-TYPE TRANSISTOR

Номер: US20130093027A1

Автор: Endo Kiyotaka, Ishizuka Kazuteru, KATO Shinji, Koda Mitsuki

Принадлежит: ELPIDA MEMORY, INC.

A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area. 1. A layout data creation device comprising a transistor adjustment unit that divides a pillar-type transistor into a plurality of sub-pillar-type transistors each of which includes one or more unit pillar-type transistors having the same configuration as one another , the transistor adjustment unit arranging the sub-pillar-type transistors in a predetermined area defined in an integrated circuit.2. The layout data creation device as claimed in claim 1 , whereinthe transistor adjustment unit divides a number of the unit pillar-type transistors constituting the pillar-type transistor by an allocatable number with rounding up to calculate a division number, where the allocatable number represents a number of the unit pillar transistors that can be arranged in a first direction of the predetermined area, andthe transistor adjustment unit divides the pillar-type transistor into the sub-pillar-type transistors in the division number.32. The layout data creation device as claimed in claim claim 1 , whereinthe transistor adjustment unit multiplies the allocatable number by the division number to calculate a total allocatable number, where the total allocatable number represents a number of the unit pillar-type transistors that can be arranged in a predetermined area, andthe transistor adjustment unit subtracts the number of the unit pillar-type transistors constituting the pillar-type transistor from the total allocatable number to calculate a pillar missing number, where the pillar missing number ...

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Номер записи: 64

18-04-2013 дата публикации

INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME

Номер: US20130093028A1

Автор: CHERN Chan-Hong, HUANG MEI-HUI

Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An integrated circuit includes at least one first gate electrode of at least one active transistor. The integrated circuit further includes at least one first dummy gate electrode and at least one second dummy gate electrode. The integrated circuit further includes at least one guard ring disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode or the at least one second dummy gate electrode. 1. An integrated circuit comprising:at least one first gate electrode of at least one active transistor;at least one first dummy gate electrode;at least one second dummy gate electrode; andat least one guard ring disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode, wherein an ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode or the at least one second dummy gate electrode.2. The integrated circuit of claim 1 , further comprising an isolation structure disposed around the at least one guard ring.3. The integrated circuit of claim 1 , wherein the at least one guard ring comprises a diffusion ring spaced from the at least one first dummy gate electrode and the at least one second dummy gate electrode.4. The integrated circuit of claim 3 , wherein a space between the diffusion ring and the at least one first dummy gate electrode and the at least one second dummy gate electrode has a dopant type opposite a dopant type of the ion implantation layer.5. The integrated circuit of claim 3 , wherein a space between the diffusion ring and the at least one first dummy gate electrode and the at least one second dummy gate electrode has a dopant concentration different from a dopant ...

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Номер записи: 65

25-04-2013 дата публикации

ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20130099241A1

Автор: CHUN Ki-Chul, JUNG Deuk-Soo, Kim Hwan

Принадлежит: LG DISPLAY CO., LTD.

An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode. 1. An array substrate for a liquid crystal display device , comprising:first and second lines on a substrate and spaced apart from each other, the first and second lines formed of a first metallic material;a gate electrode connected to the first line;a gate insulating layer on the first and second lines and the gate electrode and including a groove, the groove exposing the substrate and positioned between the first and second lines;a semiconductor layer on the gate insulating layer and corresponding to the gate electrode;a data line crossing the first and second lines and on the gate insulating layer;a source electrode on the semiconductor layer and connected to the data line;a drain electrode on the semiconductor layer and spaced apart from the source electrode;a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing a portion of the gate insulating layer and an end of the drain electrode; anda pixel electrode positioned on the gate insulating layer and in the opening, the pixel electrode contacting the end of ...

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Номер записи: 66

25-04-2013 дата публикации

POWER SEMICONDUCTOR DEVICE

Номер: US20130099279A1

Автор: Kopta Arnost, Rahimo Munaf, Storasta Liutauras

Принадлежит: ABB TECHNOLOGY AG

An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer. 1. A reverse conducting power semiconductor device having a wafer that includes layers of different conductivity types , which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side , which is arranged opposite of the emitter side , the device comprising:a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side;a first layer having a first region of the first conductivity type and higher doping concentration than the drift layer and a second region of a second conductivity type, the second region is arranged adjacent to the first region, and the first layer is arranged between the drift layer and the collector electrode;a plurality of base layers of a second conductivity type, arranged between the drift layer and the emitter electrode, wherein the base layers are in direct electrical contact to the emitter electrode;a plurality of source regions of the first conductivity type, arranged at the emitter side embedded in one of the base layers and contact the emitter electrode, wherein the source regions have a higher ...

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Номер записи: 67

25-04-2013 дата публикации

SELECTIVE FLOATING BODY SRAM CELL

Номер: US20130099316A1

Автор: Chang Josephine B., Chang Leland, Koester Steven J., Sleight Jeffrey W.

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. 1. A memory cell comprising:N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six;wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor;wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; andwherein each of said pull-up transistors comprises a floating body device.2. The memory cell of claim 1 , wherein each of the said access transistors and each of the said pull-down transistors is an n-type transistor claim 1 , and each of the said pull-up transistors is a p-type transistor.34.-. (canceled)5. The memory cell of claim 1 , wherein the memory cell comprises a static random access memory cell in which each of the pull-up and pull-down transistors comprise a gate coupled to a channel of at least one of the access transistors.69.-. (canceled)10. The memory cell of claim 1 , wherein each of the ...

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Номер записи: 68

25-04-2013 дата публикации

METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRATED CIRCUIT DIE USING THERMAL PROXIMITY CORRECTION

Номер: US20130099321A1

Автор: Benistant Francis, Colombeau Benjamin, HSIA Liang Choo, Poon Debora Chyiu Hyia, See Alex KH, TAN Yun Ling, Zhou Mei Sheng

Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal. 110.-. (canceled)11. An integrated circuit die comprising:a device structure formed at a pre-determined location on the die; andone or more dummy structures formed within a pre-defined effective thermal area surrounding the transistor structure and operable for purposely affecting temperature at the pre-determined location during a thermal anneal process.12. The integrated circuit die in accordance with wherein the device structure comprises a transistor including source/drain regions claim 11 , a gate electrode and a channel region.13. The integrated circuit die in accordance with wherein the one or more dummy structures has a structure that resembles another structure proximate a second transistor at the time of performance of the thermal anneal process.14. The integrated circuit die in accordance with wherein the one or more dummy structures has a structure that assists in achieving a temperature at the transistor that meets a desired temperature during the thermal anneal process ...

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Номер записи: 69

02-05-2013 дата публикации

Current Control Semiconductor Element and Control Device Using the Same

Номер: US20130105913A1

Автор: HIROTSU Teppei, Kanekawa Nobuyasu, TANABE Itaru

Принадлежит: HITACHI AUTOMOTIVE SYSTEMS, LTD

This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element includes a main MOSFET that drives a current and a sense MOSFET that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET and a channel located farthest from the center of the multi-finger MOSFET is indicated by L, a channel that is located closest to a position distant by a distance of (L/(√3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 1. A current control semiconductor element comprising:a main MOSFET that drives a current; anda sense MOSFET that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET, the main MOSFET and the sense MOSFET being arranged on the same semiconductor chip,wherein the main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row,wherein a part of the channels of the multi-finger MOSFET is used as a channel for the sense MOSFET, andwherein when a distance between the center of the multi-finger MOSFET and a channel located farthest from the center of the multi-finger MOSFET is indicated by L, a channel that is located closest to a position distant by a distance of (L/√3)) from the center of the multi-finger MOSFET is used as the channel for the sense MOSFET.2. The current control semiconductor element according to claim 1 ,wherein the MOSFETs that form the multi-finger MOSFET have the same pattern.3. The current control semiconductor ...

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Номер записи: 70

09-05-2013 дата публикации

Method for manufacturing semiconductor device and semiconductor device

Номер: US20130113037A1

Автор: Fujio Masuoka, Hiroki Nakamura

Принадлежит: Unisantis Electronics Singapore Pte Ltd

A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

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Номер записи: 71

09-05-2013 дата публикации

CIRCUITS, DEVICES AND SENSORS FOR FLUID DETECTION

Номер: US20130115136A1

Автор: Breysse Patrick N., Dhar Mukund Bal, Katz Howard Edan, Tremblay Jonathan Noah

Принадлежит: THE JOHNS HOPKINS UNIVERSITY

An electronic device includes a first field effect transistor that includes a first gate electrode, a first drain electrode, and a first source electrode; a second field effect transistor that includes a second gate electrode, a second drain electrode, and a second source electrode, the first and second gate electrodes being at least one of electrically connected or integral, and the first and second source electrodes being at least one of electrically connected or integral; an input electrode electrically connected to the first and second gate electrodes; and an output electrode electrically connected to the first and second source electrodes. The first field effect transistor also includes a first semiconductor material. The second field effect transistor further also incudes a second semiconductor material. At least one of the first semiconductor material and second semiconductor material has a surface that can be exposed to a fluid and changes an electrical property thereof while being exposed to the fluid. 1. An electronic device , comprising:a first field effect transistor comprising a first gate electrode, a first drain electrode, and a first source electrode;a second field effect transistor comprising a second gate electrode, a second drain electrode, and a second source electrode, said first and second gate electrodes being at least one of electrically connected or integral, and said first and second source electrodes being at least one of electrically connected or integral;an input electrode electrically connected to said first and second gate electrodes; andan output electrode electrically connected to said first and second source electrodes,wherein said first field effect transistor further comprises a first semiconductor material,wherein said second field effect transistor further comprises a second semiconductor material,wherein at least one of said first semiconductor material and second semiconductor material has a surface that can be exposed to a ...

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Номер записи: 72

16-05-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME

Номер: US20130119452A1

Автор: Endoh Tetsuo, Moon-Sik Seo

Принадлежит: TOHOKU UNIVERSITY

Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell in the semiconductor integrated circuit is provided with: a semiconductor pillar that serves as a channel; a floating gate that circumferentially covers the semiconductor pillar via a tunnel insulation layer on the outer circumference of the semiconductor pillar ; and a control gate that circumferentially covers the semiconductor pillar via an insulating layer on the outer circumference of the semiconductor pillar , and that circumferentially covers the floating gate via an insulating layer on the outer circumference of the floating gate. 1. A semiconductor integrated circuit in which a plurality of memory cells are serially-connected in an axial direction , comprising:a semiconductor pillar provided in the axial direction that serves as a channel;a floating gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar;a control gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar and that circumferentially covers the side face of the floating gate or covers a part of the floating gate to have an interval from the outer circumference of the floating gate;a first insulating layer provided between the semiconductor pillar and the floating gate;a second insulating layer provided between the floating gate and the control gate; anda third insulating layer provided between the semiconductor pillar and the control gate, ...

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Номер записи: 73

16-05-2013 дата публикации

NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY

Номер: US20130119453A1

Автор: Chen Hsin-Ming, Ching Wen-Hao, Lai Yen-Hsin, Lu Hau-Yan, Wang Shih-Chen, Yang Ching-Sung

Принадлежит: eMemory Technology Inc.

A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction. 1. An only-one-polysilicon layer non-volatile memory unit cell comprising:a transistor pair having a first transistor and a second transistor that are connected in parallel and of opposite types, the first transistor and the second transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated;a first control gate coupled to the first floating polysilicon gate through a first capacitively coupling junction;a second control gate coupled to the second floating polysilicon gate through a second capacitively coupling junction;a third control gate coupled to the first floating polysilicon gate through a first tunneling junction; anda fourth control gate coupled to the second floating polysilicon gate through a second tunneling junction.2. The only-one-polysilicon layer non-volatile memory unit cell ...

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Номер записи: 74

16-05-2013 дата публикации

METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE INCLUDING STRESS FILMS

Номер: US20130119475A1

Автор: Torii Yasunobu

Принадлежит:

A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region. 1. A semiconductor device comprising:first active regions provided in a semiconductor substrate;second active regions provided in the semiconductor substrate;gate wires which intersect the first active regions and the second active regions;first transistors which are provided on the first active regions and which include first gate electrodes, each of which is a part of each gate wire;second transistors which are provided on the second active regions and which include second gate electrodes, each of which is a part of each gate wire;at least one compressive stress film which is provided on a region including the first active regions and which covers the first transistors; anda tensile stress film which is provided on a region including the second active regions adjacent to the compressive stress film and which covers the second transistors,wherein the distances in a longitudinal direction of the gate wires from end portions of first regions in which the first active regions and the gate wires are overlapped with each other to end portions of the at least one compressive stress film are set to a first value.2. The semiconductor device according to ...

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Номер записи: 75

16-05-2013 дата публикации

Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends

Номер: US20130119476A1

Автор: Becker Scott T., Lambert Carole, Mali Jim

Принадлежит:

A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. 1. An integrated circuit , comprising:a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second ...

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Номер записи: 76

16-05-2013 дата публикации

Transistor Performance Improving Method with Metal Gate

Номер: US20130119485A1

Автор: Huan-Tsung Huang, Yuri Masuoka

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

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Номер записи: 77

23-05-2013 дата публикации

IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS

Номер: US20130126881A1

Автор: Erickson Karl R., II John E., Paone Phil C., Paulsen David P., Sheets, Uhlmann Gregory J., Williams Kelly L.

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. 1. A back-end-of-line (BEOL) structure for implementing stacked vertical transistors comprising:a pair of stacked vertical field effect transistors (FETs) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire;a channel length of each of said pair of stacked vertical FETs being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; anda wire via being formed defining a gate node of each of said pair of stacked vertical FETs.2. The back-end-of-line (BEOL) structure as recited in wherein each of said pair of stacked vertical field effect transistors (FETs) is a high performance transistor.3. The back-end-of-line (BEOL) structure as recited in wherein said pair of stacked vertical field effect transistors (FETs) includes a stacked N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).4. The back-end-of-line (BEOL) structure as recited in includes an output via defining an output connection to each of the pair of stacked vertical FETs.5. The back-end-of-line (BEOL) structure as recited in wherein said pair of stacked vertical field effect transistors (FETs) includes a series connected N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).6. The back-end-of- ...

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Номер записи: 78

23-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20130126963A1

Автор: Kakehashi Elichirou, Nishi Hiro

Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device. 1. A semiconductor device comprising:a semiconductor substrate having first and second regions;a first pillar transistor; anda second pillar transistor,wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar,wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar,wherein the first gate electrode is different in height from the second gate electrode, andthe first and second pillar transistors form a CMOS device.2. The semiconductor device according to claim 1 , wherein the first gate electrode is lower in height from the second gate electrode.3. The semiconductor device according to claim 2 , wherein the first pillar transistor is an n-channel MOS transistor claim 2 , and the second pillar transistor is a p-channel MOS transistor.4. The semiconductor device according to claim 3 , wherein the first semiconductor pillar comprises a p-type semiconductor claim 3 , and the second semiconductor pillar comprises an n-type semiconductor.5. The semiconductor device according to claim 3 , wherein the first gate electrode comprises an ...

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Номер записи: 79

23-05-2013 дата публикации

CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS

Номер: US20130126970A1

Автор: Archer Donald, Bahl Sandeep, Bulucea Constantin, Chaparala Prasad, French William, Parker David Courtney, Yang Jeng-Jiun

Принадлежит: National Semiconductor Corporation

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and ) utilize empty wells (, and ) in achieving desired transistor characteristics. Other IGFETs (, and ) utilize filled wells (, and ) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications. 1. A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET , the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type , each FET comprising: a channel zone of a region of the body material; first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface , laterally separated by the channel zone , and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface , (b) the body-material region extends laterally under both S/D zones , and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum ...

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Номер записи: 80

23-05-2013 дата публикации

SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME

Номер: US20130126971A1

Автор: ARTHUR STEPHEN DALEY, Losee Peter Almren, Matocha Kevin Sean, MCMAHON James Jay, Sandvik Peter Micah, Stum Zachary Matthew

Принадлежит: GENERAL ELECTRIC COMPANY

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process. 1. A semiconductor device comprising:at least a first and a second semiconductor cell each comprising material regions extending in a Z direction, the regions spaced apart in an X direction; a substrate;', 'a drain contact on a first surface of the substrate;', 'an epitaxial layer on a second surface of the substrate, the second surface opposite the first surface, the epitaxial layer doped a first dopant type;', 'a first doped region extending in a Y direction from an upper surface of the epitaxial layer and doped a second dopant type;', 'a first and a second source spaced apart in the X direction, disposed within the first doped region, and doped the first dopant type, the first and second sources formed in a self-aligned manner relative to the first doped region;', 'source rungs in the first doped region, each source rung connecting the first and second sources at a different location along the first and second sources, the source rungs alternating with first doped regions and formed in a self-aligned manner relative to the first and second sources, the source rungs comprising dopants of the first dopant type; and', 'wherein an area of the ...

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Номер записи: 81

23-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130126973A1

Автор: ARAO Tatsuya

Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress. 1. A semiconductor device comprising: a first semiconductor; and', 'a first conductive film over the first semiconductor; and, 'an n-channel transistor comprising a second semiconductor; and', 'a second conductive film over the second semiconductor,, 'a p-channel transistor comprisingwherein the first semiconductor receives a tensile stress,wherein the second semiconductor receives a compressive stress, andwherein a first impurity element is introduced into at least one of the first conductive film and the second conductive film.2. The semiconductor device according to claim 1 , wherein the first impurity element is one or a plurality of elements selected from impurity elements imparting n-type conductivity claim 1 , impurity elements imparting p-type conductivity and rare gas elements.3. The semiconductor device according to claim 1 , wherein a peak concentration of the first impurity element in the first conductive film or the second conductive film is in a range of 1×10to 1×10/cm.4. The semiconductor device according to claim 1 ,wherein the first impurity element is introduced into the first ...

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Номер записи: 82

23-05-2013 дата публикации

SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEEN

Номер: US20130126980A1

Автор: Baars Peter, Carter Richard, Wei Andy

Принадлежит: GLOBALFOUNDRIES INC.

Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures. 116.-. (canceled)17. A device , comprising:a plurality of gate structures positioned above a semiconducting substrate;at least one sidewall spacer positioned proximate respective sidewalls of each of said plurality of gate structures;a metal silicide region in a source/drain region formed in said semiconducting substrate, said metal silicide region extending laterally so as to contact said at least one sidewall spacer positioned proximate each of said plurality of gate structures; anda conductive contact positioned between said plurality of gate structures, said conductive contact comprising a lower portion that conductively contacts said metal silicide region and an upper portion positioned above said lower portion, wherein said lower portion is laterally wider than said upper portion and extends laterally so as to contact said at least one sidewall spacer positioned proximate each of said plurality of gate structures.18. The device of ...

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Номер записи: 83

23-05-2013 дата публикации

STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE

Номер: US20130130449A1

Автор: Kronholz Stephan, Lenski Markus, Papageorgiou Vassilios

Принадлежит: GLOBALFOUNDRIES INC.

Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region. 121.-. (canceled)22. A method , comprising:forming a gate layer stack above a first semiconductor region and a second semiconductor region;patterning said gate layer stack to form a first gate electrode structure above said first semiconductor region and a second gate electrode structure above said second semiconductor region, an upper portion of said first gate electrode structure having a first target gate length, a lower portion of said first gate electrode structure adjacent to said first semiconductor region having a first effective gate length that is less than said first target gate length, and a lower portion of said second gate electrode structure having a second effective gate length adjacent to said second semiconductor region that is greater than said first effective gate length;forming a spacer layer above said first and second gate electrode structures, said spacer layer having a thickness of approximately 10 nm or less;forming a spacer element on sidewalls of said first gate electrode structure from said spacer layer; andforming a strain-inducing semiconductor alloy in said first semiconductor region by using said spacer element as a mask.23. The method of claim 22 , wherein forming said gate layer stack comprises forming a high-k dielectric material above said first and second semiconductor regions and forming a metal-containing cap layer above said high-k dielectric material.24. The method of claim ...

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Номер записи: 84

23-05-2013 дата публикации

MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS

Номер: US20130130452A1

Автор: Ramaswamy Durai Vishak Nirmal, Sandhu Gurtej S.

Принадлежит: MICRON TECHNOLOGY, INC.

Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described. 1. A method comprising:forming a pillar of epitaxially grown semiconductor material;forming a charge storage node around the pillar; andforming a control gate around the charge storage node.2. The method of claim 1 , wherein forming a pillar of epitaxially grown semiconductor material further comprises selectively growing epitaxial silicon to form a pillar of selective epitaxial grown (SEG) silicon.3. The method of claim 1 , wherein forming a charge storage node includes forming a floating gate.4. The method of claim 1 , further comprising growing a tunnel dielectric on the pillar claim 1 , wherein the tunnel dielectric separates the pillar from the charge storage node.5. The method of claim 1 , wherein:forming a pillar of epitaxially grown semiconductor material further comprises extending the pillar of epitaxially grown semiconductor material;forming a charge storage node further comprises forming a plurality of charge storage nodes around the pillar; andforming a control gate further comprises forming a plurality of control gates, each control gate being formed around one of the charge storage nodes to form a plurality of transistors.6. The method of claim 1 , wherein: oxidizing the pillar to grow a tunnel oxide on the pillar; and', 'forming a polysilicon floating gate around the tunnel oxide; and, 'forming a charge storage node comprises'} forming a dielectric around the polysilicon floating gate; and', 'forming a control gate around the dielectric., 'forming a control gate comprises'}7. The method of claim 6 , wherein:forming a polysilicon ...

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Номер записи: 85

23-05-2013 дата публикации

Semiconductor device and fabrication method thereof

Номер: US20130130460A1

Автор: Ching-Hwa Tey, Duan-Quan LIAO, Shih-Chieh Hsu, Yi-Kun Chen

Принадлежит: United Microelectronics Corp

A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.

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Номер записи: 86

30-05-2013 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER

Номер: US20130134507A1

Автор: Takaishi Yoshihiro

Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared. 1. A semiconductor device comprising:a high-breakdown voltage transistor including at least first and second vertical transistors which are connected in series,wherein the first vertical transistor comprises a first unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,wherein the second vertical transistor comprises a second unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,wherein the plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.2. The semiconductor device as claimed in claim 1 , wherein the first and the second vertical transistors are disposed in an active region.3. The semiconductor device as claimed in claim 2 ,wherein the plurality of unit transistors constituting the first unit transistor group comprise first pillar upper diffusion layers which are connected in parallel to each other,wherein the plurality of unit transistors constituting the second unit transistor group comprise second pillar upper diffusion layers which are connected in parallel to each other.4. The semiconductor device as claimed in claim 3 ,wherein the plurality of unit transistors constituting the first unit transistor group comprise:a first semiconductor pillar group comprising a ...

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Номер записи: 87

30-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130134521A1

Автор: MISUMI Tadashi

Принадлежит:

A semiconductor device is equipped with an element region, an electrode, a thermal conduction portion, and a protective membrane. The element region is equipped with a plurality of gate electrodes. The electrode is formed on a surface of the element region. The thermal conduction portion is located on a surface side of a central portion of the electrode, and is higher in thermal conductivity than the element region. The protective membrane is formed on a peripheral portion that is located on the surface side of the electrode and surrounds a periphery of the central portion. In the element region, an emitter central region that is formed on a back side of the central portion of the electrode remains on for a longer time than an emitter peripheral region that is formed on a back side of the peripheral portion of the electrode. 1. A semiconductor device comprising:a semiconductor element region that is equipped with a plurality of insulated gates;an electrode that is formed on a surface of the semiconductor element region;a thermal conduction member that is located on a surface side of a central portion of the electrode; anda protective membrane that is formed on a surface of the electrode on a peripheral portion surrounding the central portion, whereinthe thermal conduction member is higher in thermal conductivity than the protective membrane, andout of regions included in the semiconductor element region, a central region that is formed on a back side of the central portion of the electrode remains on for a longer time than a peripheral region that is formed on a back side of the peripheral portion of the electrode.2. The semiconductor device according to claim 1 , whereinthe plurality of the insulated gates include a plurality of first insulated gates that are formed in the central region, and a plurality of second insulated gates that are formed in the peripheral region, and an average of threshold voltages of the first insulated gates at a time when the central ...

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Номер записи: 88

30-05-2013 дата публикации

Multi-Transistor Exposed Conductive Clip for Semiconductor Packages

Номер: US20130134524A1

Автор: Cho Eung San

Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. 120-. (canceled)21. A semiconductor package comprising:at least two transistors including a control transistor having a control source on a top surface thereof and a sync transistor having a sync drain on a top surface thereof;a driver integrated circuit (IC) coupled to said at least two transistors;an exposed conductive clip coupled to said control source and said sync drain.22. The semiconductor package of further comprising a mold compound enclosing said at least two transistors without covering a top surface of said exposed conductive clip.23. The semiconductor package of claim 21 , wherein said driver IC is coupled to a sync gate of said syn transistor by at least one wirebond.24. The semiconductor package of claim 21 , wherein said driver IC is coupled to a control gate of said control transistor by at least one wirebond.25. The semiconductor package of claim 21 , wherein said driver IC is coupled to a sync gate of said syn transistor and to a control gate of said control transistor through respective wirebonds.26. The semiconductor package of claim 21 , wherein said control transistor is a field effect transistor (FET).27. The semiconductor package of claim 21 , wherein said sync transistor is a field effect transistor (FET).28. The semiconductor package of claim 21 , wherein said driver IC is a flip chip.29. The semiconductor package ...

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Номер записи: 89

06-06-2013 дата публикации

THIN FILM TRANSISTOR AND ARRAY SUBSTRATE INCLUDING THE SAME

Номер: US20130140556A1

Автор: LIM Dong-Hun, PARK Heon-Kwang

Принадлежит: LG DISPLAY CO., LTD.

An array substrate includes a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode. 1. An array substrate comprising:a gate line on a substrate including a pixel region, the gate line extending in one direction;a gate electrode in the pixel region and extending from the gate line;a gate insulating layer on the gate line and the gate electrode;a data line on the gate insulating layer and crossing the gate line to define the pixel region;an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode;an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer;a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; anda drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode.2. The array substrate according to claim 1 , wherein the source electrode has a U shape claim 1 , and the drain electrode has a bar shape.3. The array substrate according to claim 2 , wherein the drain electrode is inserted into an opening of the source ...

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Номер записи: 90

06-06-2013 дата публикации

HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT

Номер: US20130140638A1

Автор: Dixit Abhisek

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout. 1. An integrated circuit logic element or component including FinFETS comprisingtwo pairs of parallel fins which are oriented in orthogonal directions to each other wherein each fin of said two pairs of parallel fins has impurities implanted therein of the same or different conductivity types such that said two pairs of parallel fins can function as two, three or four transistors,a gate structure common to each pair of fins, andconnections between said two, three or four transistors.2. The integrated circuit logic element or component as recited in claim 1 , wherein said connections between said two claim 1 , three or four transistors are formed in a single common layer.3. The integrated circuit logic element or component as recited in wherein at least one pair of transistors formed from a pair of parallel fins have a common node.4. The integrated circuit logic element or component as recited in claim 3 , wherein said transistors having a common node are of opposite conductivity types.5. The integrated circuit logic element or component as recited in claim 1 , wherein said parallel fins are formed from an active semiconductor layer of an SOI substrate.6. The integrated circuit logic element or component as recited in claim 1 , wherein said gate structure extends between a said pair of fins.7. An SRAM bit-cell layout ...

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Номер записи: 91

06-06-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130140644A1

Автор: KAJIMOTO Minori, NITTA Hiroyuki, Noguchi Mitsuhiro

Принадлежит: KABUSHIKI KAISHA TOSHIBA

A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed. 1. A semiconductor device comprising:a semiconductor substrate;a first transistor including a first gate insulating film, a first gate electrode on the first gate insulating film, a first diffusion layer in the semiconductor substrate adjacent to the first gate electrode, and a first insulating film above the first diffusion layer; anda second transistor including a second gate insulating film, a second gate electrode on the second gate insulating film, and a second diffusion layer in the semiconductor substrate adjacent to the second gate electrode;wherein the second gate insulating film directly under the second gate electrode has a second thickness less than a first thickness of the first gate insulating film directly under the first gate electrode, and an upper surface of the second diffusion layer is lower than a lower surface of the second gate insulating film directly under the second gate electrode.2. The device according to claim 1 , wherein the second transistor further includes a second insulating film having a third thickness greater than the second thickness above the second diffusion layer.3. The device according to claim 2 , wherein the second insulating film is in direct contact with the second diffusion layer.4. The device according to claim 1 , wherein an upper surface of the first diffusion layer is flat.5. The device according to claim 1 , wherein the first insulating film is in direct contact with the first diffusion layer.6. The device according to claim 1 , wherein the upper surface of the second diffusion layer ...

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Номер записи: 92

13-06-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES

Номер: US20130146972A1

Автор: Culshaw Ian, Peake Steven Thomas, Rutter Phil

Принадлежит: NXP B. V.

A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes. 1. A semiconductor device comprising:a plurality of transistors formed at an active area of semiconductor substrate, the transistors each comprising a source layer, a drain layer and a gate;at least one isolation trench formed around the active area and having an insulator liner; andat least one further trench processed with the isolation trench and filled with the insulator liner and an electrode material, wherein a transistor gate is electrically connected to the top of the further trench, and the transistor drain is capacitively connected to the bottom of the further trench.2. A device as claimed in claim 1 , wherein the isolation trench and the at least one further trench is filled with the insulating liner and an electrode material.3. A device as claimed in claim 2 , wherein the electrode material comprises a doped semiconductor material.4. A device as claimed in wherein the plurality of transistors are connected in parallel.5. A device as claimed in claim 4 , comprising between 1 claim 4 ,000 claim 4 ,000 and 10 claim 4 ,000 claim 4 ,000 MOS transistors connected in parallel.6. A device as claimed in claim 1 , wherein the further trench is outside the active area where the transistors are formed.7. A device as claimed claim 1 , wherein the plurality of transistors have their gates connected to a gate pad via a gate bus bar with gate lines extending from the gate bus bar into the active area claim 1 , wherein a series impedance is provided between the gate pad and the gate bus bar claim 1 , and wherein the series ...

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Номер записи: 93

20-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Номер: US20130153887A1

Автор: Hayashi Yoshihiro, INOUE Naoya, KANEKO Kishou

Принадлежит: RENESAS ELECTRONICS CORPORATION

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer. 1. A semiconductor device comprising:a multilayer interconnect layer having a first interconnect layer and a second interconnect layer positioned over the first interconnect layer; anda first transistor and a second transistor formed by using the first interconnect layer,wherein the first transistor includes:a first gate electrode buried in the first interconnect layer;a first gate insulating film positioned over the first gate electrode;a first semiconductor layer positioned over the first gate insulating film; andan insulating cover film positioned below the second interconnect layer and covering the upper surface and the lateral side of the first semiconductor layer, andwherein the second transistor includes:a second gate electrode buried in the first interconnect layer;a second gate insulating film positioned over the second gate electrode; anda second semiconductor layer positioned over the second gate insulating film, positioned at least partially above the insulating cover film and formed of a material different from that of the first semiconductor layer.2. The semiconductor device according to claim 1 ,wherein the multilayer interconnect layer has an anti-diffusion film positioned ...

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Номер записи: 94

20-06-2013 дата публикации

PIXEL STRUCTURE OF ORGANIC LIGHT EMITTING DEVICE

Номер: US20130153908A1

Автор: Liu Chun-Yen

Принадлежит: AU OPTRONICS CORPORATION

A pixel structure including a first scan line, a second scan line, a data line and a power line substantially perpendicular to the first scan line and the second scan line, a reference signal line and an emission signal line substantially parallel with the first scan line and the second scan line, a common thin film transistor (C-TFT), a first pixel unit, and a second pixel unit is provided. The common thin film transistor has a common gate electrode, a common source electrode and a common drain electrode. The common gate electrode is electrically connected to the first scan line, the common drain electrode is electrically connected to the reference signal line. The first and the second pixel units respectively have a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a capacitor, and an emission device. 1. A pixel structure of an organic light emitting device , comprising:a first scan line and a second scan line;a data line, crossed to the first scan line and the second scan line;a reference signal line;an emission signal line;a common contact window, being connected to the reference signal line; a first thin film transistor, having a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode being electrically connected to the first scan line, the first drain electrode of the first thin film transistor being electrically connected to the reference signal line through the common contact window;', 'a second thin film transistor, having a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the emission signal line;', 'a capacitor, having a first capacitive electrode and a second capacitive electrode, the first capacitive electrode being electrically connected to the first source electrode of the first thin film transistor, and the second capacitive electrode being electrically connected to the second drain ...

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Номер записи: 95

20-06-2013 дата публикации

Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor

Номер: US20130153913A1

Автор: Liang Qingqing, Zhong Huicai, Zhu Huilong

Принадлежит:

A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. 1. A method for fabricating a transistor , comprising:providing a substrate and forming a first insulating layer on the substrate;defining a first device area on the first insulating layer;forming a spacer surrounding the first device area on the first insulating layer;defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; andforming transistor structures in the first and second device area, respectively.2. The method according to claim 1 , wherein the step of defining a first device area on the first insulating layer comprises:sequentially depositing a first semiconductor layer and a first mask layer on the first insulating layer; andpatterning the first semiconductor layer and the first mask layer to define the first device area.3. The method according to claim 2 , wherein the step of patterning the first semiconductor layer and the first mask layer comprises:applying a photoresist layer onto the first mask layer;forming a patterned photoresist layer by photolithography; andetching away a portion of the first mask layer and a portion of the ...

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Номер записи: 96

20-06-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130153980A1

Автор: HONDA Masashi

Принадлежит:

A nonvolatile semiconductor storage device manufacturing method including forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate; embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors; detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; exposing an upper portion of the second silicon film by etching the inter-gate insulating film between the gate electrodes of two adjacent ones of the selector gate transistors down to a first depth while leaving a contact region of a first width between the gate electrodes; performing silicidation of the upper portion of the second silicon film of each of the gate electrodes; and forming an inter-layer insulating film after the silicidation. 1. A nonvolatile semiconductor storage device manufacturing method comprising:forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate;etching the processing insulating film, the second silicon film, the inter-electrode insulating film, and the first silicon film to form gate electrodes of memory cell transistors and selector gate transistors;embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors;detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; ...

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Номер записи: 97

20-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Номер: US20130154000A1

Автор: NAKAZAWA Yoshito, SHINBORI Atsushi

Принадлежит: RENESAS ELECTRONICS CORPORATION

The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. 1. A semiconductor device comprising:an active cell which causes a load current to flow therethrough;a sense cell which detects a magnitude of the load current flowing through the active cell; andan inactive cell which separates the active cell and the sense cell from each other,wherein each of the active cell, the sense cell and the inactive cell includes:a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;a dummy gate electrode formed inside the trench via the first insulating film;a second insulating film formed so as to cover an upper ...

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Номер записи: 98

20-06-2013 дата публикации

Self-Aligned Gate Structure for Field Effect Transistor

Номер: US20130154017A1

Автор: Dix Gregory, Grimm Daniel J., Kline Harold, Schroeder Rodney

Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region. 1. A method for manufacturing a field effect transistor comprising:providing a stack comprising a substrate and epitaxial layer deposited on said substrate, a multilayer insulating layer on top of the epitaxial layer, and a first gate-layer on top of the insulating layer;patterning the stack to provide openings up to a lowest layer of the multi-layer insulating layer;implanting base regions;depositing a second gate layer covering the openings and the first gate layer;performing an etching up to the lowest layer of the multi-layer insulating layer such that spacers on sides of the openings remain and form respective gate structures of the field effect transistor.2. The method according to claim 1 , wherein the multi-layer insulating layer comprises a first oxide layer on top of the substrate claim 1 , a nitride layer on top of the first oxide layer; a second oxide layer on top of the nitride layer.3. The method according to claim 2 , wherein the first layer is a Gate oxide.4. The method according to claim 1 , wherein each layer of the multi-layer insulating layer has a different thickness.5. The method according to claim 2 , wherein the Gate oxide layer has a thickness of approximately 250 Å claim 2 , the nitride layer of approximately 400 Å claim 2 , the thick oxide layer of approximately 2500 Å claim 2 , and the first polysilicon layer of approximately 1500 Å.6. The method according to claim 1 , wherein the second polysilicon layer has a thickness of approximately 2500 Å.7. The method according to claim 1 , wherein the ...

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Номер записи: 99

20-06-2013 дата публикации

SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS

Номер: US20130154018A1

Автор: Baars Peter, Feustel Frank, Werner Thomas

Принадлежит: GLOBALFOUNDRIES INC.

Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material. 120.-. (canceled)21. A semiconductor device , comprising:a transistor comprising drain and source regions and a gate electrode structure;a contact bar formed in a first dielectric material and connecting to one of said drain region and said source region, said contact bar comprising a first conductive material, a length of said contact bar extending along a width direction of said transistor; anda conductive line formed in a second dielectric material, said conductive line comprising an upper portion having a top width extending along a length direction of said transistor and a lower portion having a bottom width extending along said length direction that is less than said top width of said upper portion, said conductive line connecting to said contact bar and comprising a second conductive material that differs from said first conductive material.22. The semiconductor device of claim 21 , wherein said first conductive material comprises a first type of metal and said second conductive material comprises a second type of metal that differs ...

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Номер записи: 100

20-06-2013 дата публикации

System, method and apparatus for seedless electroplated structure on a semiconductor substrate

Номер: US20130154020A1

Автор: Christian Rene Bonhote, Georges Gibran Siddiqi, Jeffrey S. Lille, Ricardo Ruiz

Принадлежит: Hitachi Global Storage Technologies Netherlands BV

An integrated circuit has a doped silicon semiconductor with regions of insulators and bare silicon. The bare silicon regions are isolated from other bare silicon regions. A semiconductor device on the doped silicon semiconductor has at least two electrical connections to form regions of patterned metal. A metal is electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer. A self-aligned silicide is located under each plated connection, formed by annealing, for the regions of plated metal on bare silicon.

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Номер записи: 101