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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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10-11-2016 дата публикации

Система хранения данных с модулем хеширования

Номер: RU0000165821U1
Автор: Максим Андреевич Сибиряков
Принадлежит: Максим Андреевич Сибиряков

Полезная модель относится к вычислительной технике, в частности к системам хранения данных. Полезная модель может быть применена для уменьшения времени поиска адресов блоков данных, хранимых в дисковой кэш-памяти системы хранения данных. Это достигается тем, что система хранения данных с модулем хеширования содержит дисковые устройства, дисковую кэш-память, управляющий процессор, системную шину, интерфейсы хост-узлов, интерфейсы дисковых устройств, системную память, хранящую управляющие таблицы в виде хеш-таблиц с цепочками коллизий и модуль хеширования, выполняющий поиск адреса блока данных, хранимого в дисковой кэш-памяти системы хранения данных, в одной из цепочек коллизий хеш-таблиц. Техническим результатом, обеспечиваемым приведенной совокупностью признаков, является ускоренный поиск адресов блоков данных, хранимых в дисковой кэш-памяти системы хранения данных, реализуемый модулем хеширования. Более быстрый поиск адресов блоков данных в цепочке коллизий хеш-таблицы в сравнении со списками и таблицами обусловлен тем, что количество адресов блоков данных в цепочке коллизий хеш-таблицы меньше, чем количество адресов блоков данных, хранимых в таблице или двусвязном кольцевом списке. Полезная модель может быть осуществлена на основе системы хранения данных прототипа. Система хранения данных должна иметь модуль хеширования. Управляющие таблицы, хранимые в системной памяти системы хранения данных, должны быть в виде хеш-таблиц с цепочками коллизий. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 165 821 U1 (51) МПК G06F 12/0893 (2016.01) G06F 12/0864 (2016.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ТИТУЛЬНЫЙ (21)(22) Заявка: ЛИСТ ОПИСАНИЯ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ 2016122968/08, 09.06.2016 (24) Дата начала отсчета срока действия патента: 09.06.2016 (72) Автор(ы): Сибиряков Максим Андреевич (RU) (73) Патентообладатель(и): Сибиряков Максим Андреевич (RU) R U Приоритет(ы): (22) Дата подачи заявки: 09.06.2016 (45) Опубликовано: 10.11.2016 Бюл. № 31 R U 1 6 5 8 2 ...

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Номер записи: 1
05-01-2012 дата публикации

Pre-Emptive Garbage Collection of Memory Blocks

Номер: US20120005405A1
Автор: Jianmin Huang, Neil David Hutchison, Shai Traister, Steven Sprouse, William Wu
Принадлежит: SanDisk Technologies LLC

A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system.

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Номер записи: 2
05-01-2012 дата публикации

Garbage Collection of Memory Blocks Using Volatile Memory

Номер: US20120005406A1
Автор: Neil David Hutchison, Steven Sprouse
Принадлежит: SanDisk Technologies LLC

A method and system for performing garbage collection operations on update blocks in a memory device using volatile memory is disclosed. When performing a garbage collection operation, a first part of the data related to the garbage collection operation is written to a volatile memory in the memory device, and a second part of the data related to the garbage collection operation is written to a non-volatile memory in the memory device. The first part of the data that is written to the volatile memory (such as a random access memory) may comprise control information (such as mapping information of the logical addressable unit to a physical metablock). The second part of the data related to the garbage collection that is written to the non-volatile memory (such as a flash memory) may comprise the consolidated data in the update block.

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Номер записи: 3
15-03-2022 дата публикации

Высокоплотный вычислительный узел

Номер: RU0000209333U1
Автор: Владимир Геннадиевич Басалов, Эдуард Геннадьевич Байков, Юрий Алексеевич Малых
Принадлежит: Российская Федерация, от имени которой выступает Государственная корпорация по атомной энергии "Росатом" (Госкорпорация "Росатом"), Федеральное государственное унитарное предприятие "Российский Федеральный ядерный центр - Всероссийский научно-исследовательский институт экспериментальной физики" (ФГУП "РФЯЦ-ВНИИЭФ")

Полезная модель относится к области вычислительной техники и может быть использована при создании высокопроизводительных вычислительных систем (ВВС). Высокоплотный вычислительный узел содержит корпус высотой 4U, блейд-сервера, коммуникационные устройства и блоки питания. Корпус разделен на переднюю и заднюю секции информационной и электрической объединительными платами, блейд-сервера, устанавливаются в передней части корпуса, а коммуникационные устройства и блоки питания устанавливаются в задней части корпуса. Блейд-сервера и коммуникационные устройства с разных сторон подключаются к объединительным платам. Каждое коммуникационное устройство имеет три группы портов. Первыми группами портов коммуникационные устройства объединяются между собой по полносвязной топологии. Вторые группы портов коммуникационных устройств являются внешними выводами высокоплотного вычислительного узла, которые предназначены для объединения высокоплотных вычислительных узлов в единую высокопроизводительную вычислительную систему неограниченной производительности. К третьей группе портов каждого коммуникационного устройства подключены до двух соответствующих блейд-серверов. Блейд-сервера и коммуникационные устройства оборудованы контактной системой жидкостного охлаждения. Технический результат заключается в увеличении эффективности высокоплотного вычислительного узла. 5 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 209 333 U1 (51) МПК G06F 12/0813 (2016.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G06F 12/0813 (2021.08) (21)(22) Заявка: 2021128505, 27.09.2021 (24) Дата начала отсчета срока действия патента: Дата регистрации: 15.03.2022 (45) Опубликовано: 15.03.2022 Бюл. № 8 2 0 9 3 3 3 R U (56) Список документов, цитированных в отчете о поиске: Tiffany Trader "Sugon VP on Global Market Strategy, the VMware Venture and Robotic Immersive Cooling", опубл. 18.11.2015 на 2 страницах [прототип], размещено в Интернет по адресу URL:https://www ...

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Номер записи: 4
19-01-2012 дата публикации

Information Handling System with Processing System, Low-power Processing System and Shared Resources

Номер: US20120013795A1
Автор: Andrew T. Sultenfuss, Steven L. Belt
Принадлежит: Dell Products LP

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

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Номер записи: 5
19-01-2012 дата публикации

Managing extended raid caches using counting bloom filters

Номер: US20120017041A1
Автор: Ross E. Zwisler
Принадлежит: LSI Corp

Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

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Номер записи: 6
19-01-2012 дата публикации

Multi-resolution cache monitoring

Номер: US20120017045A1
Автор: Edwin Scott Olds, Jonathan Williams Haines, Steven S. Williams, Timothy Richard Feldman, Wayne Howard Vinson
Принадлежит: SEAGATE TECHNOLOGY LLC

Multi-resolution cache monitoring devices and methods are provided. Multi-resolution cache devices illustratively have a cache memory, an interface, an information unit, and a processing unit. The interface receives a request for data that may be included in the cache memory. The information unit has state information for the cache memory. The state information is organized in a hierarchical structure. The process unit searches the hierarchical structure for the requested data.

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Номер записи: 7
19-01-2012 дата публикации

Information Handling System Universal Memory Wear Leveling System and Method

Номер: US20120017052A1
Автор: William F. Sauber
Принадлежит: Individual

An information handling system universal memory architecture assigns memory blocks to information handling system functions, such as a persistent storage function and a working storage function, that have different relative rates of writes of information. The blocks are periodically analyzed for remaining memory life to reassign blocks to functions that result in wear leveling across the blocks. For example, blocks having relatively low life remaining that are assigned to functions having a relatively high number of writes have their function switched with blocks that have a relatively high life remaining that are assigned to functions having a relatively low number of writes. In addition, wear leveling performed within a block ensures even wear of the memory cells within the block.

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Номер записи: 8
02-02-2012 дата публикации

Method, Mobile Terminal and Computer Program Product for Sharing Storage Device

Номер: US20120030433A1
Автор: Chunhui Sun, Fuliang Zhang, Jinmei Yang, Wenying Shan
Принадлежит: Lenovo Beijing Ltd

The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile storage device. A processing capacity of the first processor is different from that of the second processor. A state in which the first processor is operating and using the storage device is a second state. A state in which the second processor is operating and using the storage device is a third state. The method comprising: the first processor receiving a switch instruction; the first processor controlling the storage device to enter the second state or the third state according to the switch instruction. As compared with the prior art, by controlling the sharing of the storage device by the first processor, the invention reduces the elements in the mobile terminal and saves the hardware cost of the mobile terminal; moreover, the physical connection between the components in the mobile terminal is simple and easily controlled.

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Номер записи: 9
02-02-2012 дата публикации

Electrical apparatus and power supply control method

Номер: US20120030491A1
Автор: Shigeharu Itou
Принадлежит: Kyocera Mita Corp

An electrical apparatus has a controller for switching between a normal power mode and power saving modes. A receiver receives instructions for a manipulation on the apparatus. A switch controller switches to a first power saving mode when no instruction for manipulation is received within a first standby time in the normal power mode, switches to a second and lower power saving mode when no instruction for manipulation is received and the time reaches a preset second standby time in the first power saving mode, switches to the normal power mode when an instruction for manipulation is received when the apparatus is in the first or second power saving mode, and switches to the second or a third power saving mode for supplying less power than the first power saving mode but more than the second when the time reaches the first standby time if a predetermined condition is satisfied.

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Номер записи: 10
09-02-2012 дата публикации

Semiconductor storage device with volatile and nonvolatile memories

Номер: US20120033496A1
Автор: Hidenori Matsuzaki, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
Принадлежит: Individual

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

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Номер записи: 11
09-02-2012 дата публикации

Coordinated garbage collection for raid array of solid state disks

Номер: US20120036309A1
Автор: David A. Dillow, Feiyi Wang, Galen M. Shipman, Hakki S. Oral, Youngjae Kim
Принадлежит: UT Battelle LLC

An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices.

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Номер записи: 12
09-02-2012 дата публикации

Wear Leveling Technique for Storage Devices

Номер: US20120036312A1
Автор: Jonathan Haines, Timothy Feldman
Принадлежит: SEAGATE TECHNOLOGY LLC

A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks.

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Номер записи: 13
09-02-2012 дата публикации

Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

Номер: US20120036509A1
Автор: Chien-Chun Chou, Drew E. Wingard, Harutyun Aslanyan, Krishnan Srinivasan, Ruben Khazhakyan
Принадлежит: Sonics Inc

A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

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Номер записи: 14
16-02-2012 дата публикации

Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems

Номер: US20120042121A1
Автор: Christopher J. Hughes, Daehyun Kim, Partha Kundu, Yen-Kuang Chen
Принадлежит: Individual

A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

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Номер записи: 15
16-02-2012 дата публикации

Intelligent cache management

Номер: US20120042123A1
Автор: Curt Kolovson
Принадлежит: Curt Kolovson

An exemplary storage network, storage controller, and methods of operation are disclosed. In one embodiment, a method of managing cache memory in a storage controller comprises receiving, at the storage controller, a cache hint generated by an application executing on a remote processor, wherein the cache hint identifies a memory block managed by the storage controller, and managing a cache memory operation for data associated with the memory block in response to the cache hint received by the storage controller.

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Номер записи: 16
23-02-2012 дата публикации

Computer system, control apparatus, storage system and computer device

Номер: US20120047502A1
Автор: Akiyoshi Hashimoto
Принадлежит: HITACHI LTD

The computer system includes a server being configured to manage a first virtual machine to which a first part of a server resource included in the server is allocated and a second virtual machine to which a second part of the server resource is allocated. The computer system also includes a storage apparatus including a storage controller and a plurality of storage devices and being configured to manage a first virtual storage apparatus to which a first storage area on the plurality of storage devices is allocated and a second virtual storage apparatus to which a second storage area on the plurality of storage devices is allocated. The first virtual machine can access to the first virtual storage apparatus but not the second virtual storage apparatus and the second virtual machine can access to the second virtual storage apparatus but not the first virtual storage apparatus.

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Номер записи: 17
01-03-2012 дата публикации

Memory device and operating method thereof

Номер: US20120054419A1
Автор: CHEN Xiu, LIANG Chen
Принадлежит: Via Technologies Inc

The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a first specific requirement, and when the data access fulfills the conditions of the first requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

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Номер записи: 18
01-03-2012 дата публикации

Load Balancing Scheme In Multiple Channel DRAM Systems

Номер: US20120054423A1
Автор: Feng Wang, Jonghae Kim, Matthew Michael Nowak, Shiqun Gu
Принадлежит: Qualcomm Inc

A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

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Номер записи: 19
01-03-2012 дата публикации

Method and apparatus for fuzzy stride prefetch

Номер: US20120054449A1
Автор: Shiliang Hu, Youfeng Wu
Принадлежит: Intel Corp

In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

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Номер записи: 20
08-03-2012 дата публикации

Method and apparatus for handling critical blocking of store-to-load forwarding

Номер: US20120059971A1
Автор: Bradley Burgess, Christopher D. Bryant, David Kaplan, Tarun Nakra
Принадлежит: Advanced Micro Devices Inc

The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.

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Номер записи: 21
08-03-2012 дата публикации

Hybrid memory management

Номер: US20120059992A1
Автор: John Geldman, Martin Ragnar Furuhjelm, Michael Murray, William H. Radke
Принадлежит: Micron Technology Inc

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

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Номер записи: 22
08-03-2012 дата публикации

Method for using bad blocks of flash memory

Номер: US20120060054A1
Автор: Junhong Weng, Yingtong Sun
Принадлежит: Nationz Technologies Inc

A method is provided for using bad blocks in flash memory. The method includes placing in a replacement area of the flash memory a special bad block that meets a “still usable” condition from the bad blocks of the flash memory. The method also includes receiving a use request for using the special bad block in the replacement area to store user data, writing the user data into the special bad block, and determining whether the user data is successfully written into the special bad block. Further, the method includes placing the special bad block back into the replacement area for a next use request when it is determined that the user data is not successfully written into the special bad block.

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Номер записи: 23
15-03-2012 дата публикации

Scheduling of i/o writes in a storage environment

Номер: US20120066435A1
Автор: Bo Hong, Craig Harmer, Ethan MILLER, Feng Wang, John Colgrove, John Hayes
Принадлежит: Pure Storage Inc

A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

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Номер записи: 24
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 25
15-03-2012 дата публикации

Apparatus for detecting presence or absence of oscillation of clock signal

Номер: US20120066557A1
Автор: Kimiharu Eto
Принадлежит: Renesas Electronics Corp

A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

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Номер записи: 26
22-03-2012 дата публикации

Selection of Units for Garbage Collection in Flash Memory

Номер: US20120072639A1
Автор: Mark Allen Gaertner, Ryan James Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest.

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Номер записи: 27
29-03-2012 дата публикации

Hierarchical Memory Addressing

Номер: US20120075319A1
Автор: William James Dally
Принадлежит: Nvidia Corp

One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

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Номер записи: 28
29-03-2012 дата публикации

Nonvolatile semiconductor memory device with advanced multi-page program operation

Номер: US20120079173A1
Автор: Dong-Hyuk Chae, Young-Ho Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

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Номер записи: 29
29-03-2012 дата публикации

Method and apparatus for reducing processor cache pollution caused by aggressive prefetching

Номер: US20120079205A1
Автор: Patrick Conway
Принадлежит: Advanced Micro Devices Inc

A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.

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Номер записи: 30
05-04-2012 дата публикации

Tracking written addresses of a shared memory of a multi-core processor

Номер: US20120084498A1
Автор: Charles Edwards Peet, JR., Chris Randall Stone, David Sonnier
Принадлежит: LSI Corp

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

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Номер записи: 31
05-04-2012 дата публикации

Disk control apparatus, disk control method, and storage medium storing disk control program

Номер: US20120084503A1
Автор: Yuichi Hagiwara
Принадлежит: Canon Inc

A disk control apparatus that is capable of performing a reliable mirroring control for both of an SSD and an HDD. The disk control apparatus that performs a mirroring control to the SSD and the HDD. An acquisition unit acquires the data rewriting number in the SSD. A derivation unit derives a data retention period of the SSD from the data rewriting number acquired. A comparison unit compares a predetermined threshold value with an increment between the data rewriting number acquired at a predetermined timing and the data rewriting number acquired after a retention period, which is derived from the data rewriting number at the predetermined timing, elapses. A setting unit sets so as to read data from the SSD by default and to read data from the HDD when the comparison unit determines that the increment is less than the threshold value.

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Номер записи: 32
05-04-2012 дата публикации

Circuit and method for determining memory access, cache controller, and electronic device

Номер: US20120084513A1
Автор: Kazuhiko Okada
Принадлежит: Fujitsu Semiconductor Ltd

A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.

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Номер записи: 33
12-04-2012 дата публикации

Method for managing and tuning data movement between caches in a multi-level storage controller cache

Номер: US20120089782A1
Автор: Brian D. McKean, Donald R. Humlicek, Timothy R. Snider
Принадлежит: LSI Corp

A method for managing data movement in a multi-level cache system having a primary cache and a secondary cache. The method includes determining whether an unallocated space of the primary cache has reached a minimum threshold; selecting at least one outgoing data block from the primary cache when the primary cache reached the minimum threshold; initiating a de-stage process for de-staging the outgoing data block from the primary cache; and terminating the de-stage process when the unallocated space of the primary cache has reached an upper threshold. The de-stage process further includes determining whether a cache hit has occurred in the secondary cache before; storing the outgoing data block in the secondary cache when the cache hit has occurred in the secondary cache before; generating and storing metadata regarding the outgoing data block; and deleting the outgoing data block from the primary cache.

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Номер записи: 34
12-04-2012 дата публикации

Memory storage device, memory controller thereof, and method for automatically creating fill-file thereof

Номер: US20120089805A1
Автор: Sing-Chang Liu
Принадлежит: Phison Electronics Corp

A memory storage device, a memory controller thereof, and a method for automatically creating a fill-file thereof are provided. In the present method, a plurality of logical addresses is configured and grouped into a plurality of logical blocks to be mapped to physical blocks of a memory chip in the memory storage device. When a host system is powered on, whether the logical addresses have been formatted into a partition is determined. If the logical addresses have been formatted into a partition, whether a fill-file of a predetermined file capacity exists is determined. If the fill-file does not exist, data related to the fill-file is respectively filled into a file allocation table (FAT) and a root directory of the formatted partition when the host system reads the FAT and the root directory, so as to automatically create the fill-file.

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Номер записи: 35
12-04-2012 дата публикации

Query sampling information instruction

Номер: US20120089816A1
Автор: Damian L. Osisek, Donald W. Schmidt, Jane H. Bartik, Lisa Cranton Heller, Patrick M. West, Jr., Phil C. Yeh
Принадлежит: International Business Machines Corp

A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

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Номер записи: 36
19-04-2012 дата публикации

Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems

Номер: US20120095607A1
Автор: Avinash N. Ananthakrishnan, Eric C. Samson, Inder Sodhi, Joydeep Ray, Ryan D. Wells
Принадлежит: Ananthakrishnan Avinash N, Inder Sodhi, Joydeep Ray, Samson Eric C, Wells Ryan D

According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.

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Номер записи: 37
19-04-2012 дата публикации

Cache memory device, cache memory control method, program and integrated circuit

Номер: US20120096213A1
Автор: Kazuomi Kato
Принадлежит: Panasonic Corp

To aim to provide a cache memory device that performs a line size determination process for determining a refill size, in advance of a refill process that is performed at cache miss time. According to the line size determination process, the number of reads/writes of a management target line that belongs to a set is acquired (S 51 ), and in the case where the numbers of reads completely match one another and the numbers of writes completely match one another (S 52 : Yes), the refill size is determined to be large (S 54 ). Otherwise (S 52 : No), the refill size is determined to be small (S 55 ).

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Номер записи: 38
19-04-2012 дата публикации

System and Method for the Synchronization of a File in a Cache

Номер: US20120096228A1
Автор: David Thomas, Scott Wells
Принадлежит: Individual

The present invention provides a system and method for bi-directional synchronization of a cache. One embodiment of the system of this invention includes a software program stored on a computer readable medium. The software program can be executed by a computer processor to receive a database asset from a database; store the database asset as a cached file in a cache; determine if the cached file has been modified; and if the cached file has been modified, communicate the cached file directly to the database. The software program can poll a cached file to determine if the cached file has changed. Thus, bi-directional synchronization can occur.

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Номер записи: 39
19-04-2012 дата публикации

Power-cap settings

Номер: US20120096248A1
Автор: Clifford A. McCarthy
Принадлежит: Hewlett Packard Development Co LP

When the maximum power consumption of a computer exceeds a currently selected power-consumption cap, a cap setting corresponding to the currently selected power-consumption cap is reduced in addition, power-cap settings corresponding to power-consumption caps between said currently selected power-consumption cap and said maximum power consumption are reduced.

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Номер записи: 40
19-04-2012 дата публикации

Data processing method and semiconductor integrated circuit

Номер: US20120096335A1
Автор: Nobuhiro Tsuboi, Tomohisa Sezaki, Tsukasa Takahashi, Yoshiteru Mino
Принадлежит: Panasonic Corp

A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

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Номер записи: 41
26-04-2012 дата публикации

Transitioning from mimo to siso to save power

Номер: US20120099497A1
Автор: Harish Vaidya, Manoj Raveendranath Kamath, Rakesh Raman
Принадлежит: Broadcom Corp

Various example embodiments are disclosed. According to an example embodiment, an apparatus may include at least one processor and at least one memory. The at least one memory may include computer-executable code that, when executed by the processor, is configured to cause the apparatus to send a message to a node in wireless communication with the apparatus, the message indicating a transition by the apparatus from multiple-input multiple-output (MIMO) to single-input single-output (SISO), and transition from wireless MIMO communication with the node to wireless SISO communication with the node after sending the message to the node.

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Номер записи: 42
26-04-2012 дата публикации

Multiplexing Users and Enabling Virtualization on a Hybrid System

Номер: US20120102138A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, support multiple users in an out-of-core processing environment. At least one accelerator system in a plurality of accelerator systems is partitioned into a plurality of virtualized accelerator systems. A private client cache is configured on each virtualized accelerator system in the plurality of virtualized accelerator systems. The private client cache of each virtualized accelerator system stores data that is one of accessible by only the private client cache and accessible by other private client caches associated with a common data set. Each user in a plurality of users is assigned to a virtualized accelerator system from the plurality of virtualized accelerator systems.

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Номер записи: 43
03-05-2012 дата публикации

Storage device cache

Номер: US20120110258A1
Автор: Jack Lakey, Ron WATTS
Принадлежит: SEAGATE TECHNOLOGY LLC

Implementations described and claimed herein provide a method and system for comparing a storage location related to a new write command on a storage device with storage locations of a predetermined number of write commands stored in a first table to determine frequency of write commands to the storage location. If the frequency is determined to be higher than a first threshold, the data related to the write command is stored in a write cache.

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Номер записи: 44
10-05-2012 дата публикации

Low power dual processor architecture for multi mode devices

Номер: US20120115456A1
Автор: Albert S. Ludwin, Ranganathan Krishnan, William R. Gardner
Принадлежит: Qualcomm Inc

A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

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Номер записи: 45
10-05-2012 дата публикации

Hybrid Server with Heterogeneous Memory

Номер: US20120117312A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

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Номер записи: 46
10-05-2012 дата публикации

Apparatus and method for accessing cache memory

Номер: US20120117326A1
Автор: Jui-Yuan Lin, Yen-Ju Lu
Принадлежит: Realtek Semiconductor Corp

The present invention relates to an apparatus and a method for accessing a cache memory. The cache memory comprises a level-one memory and a level-two memory. The apparatus for accessing the cache memory according to the present invention comprises a register unit and a control unit. The control unit receives a first read command and a reject datum of the level-one memory and stores the reject datum of the level-one memory to the register unit. Then the control unit reads and stores a stored datum of the level-two memory to the level-one memory according to the first read command.

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Номер записи: 47
17-05-2012 дата публикации

Secondary Cache Memory With A Counter For Determining Whether to Replace Cached Data

Номер: US20120124291A1
Автор: Anil Krishna, Heather D. Achilles, Nicholas David Lindberg, Shaul Yifrach, Steven Paul Vanderwiel, Timothy Hume Heil
Принадлежит: International Business Machines Corp

A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.

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Номер записи: 48
24-05-2012 дата публикации

Signal processing system, integrated circuit comprising buffer control logic and method therefor

Номер: US20120131241A1
Автор: Alistair Robertson, Joseph Circello, Mark Maiolani
Принадлежит: FREESCALE SEMICONDUCTOR INC

A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

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Номер записи: 49
24-05-2012 дата публикации

Correlation-based instruction prefetching

Номер: US20120131311A1
Автор: Yuan C. Chou
Принадлежит: Oracle International Corp

The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, the system determines whether the current instruction cache access is discontinuous with a preceding instruction cache access. If so, the system completes the current instruction cache access by performing a cache access to service the cache miss or the first demand fetch, and also prefetching a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access.

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Номер записи: 50
31-05-2012 дата публикации

Method and apparatus for selectively performing explicit and implicit data line reads

Номер: US20120136857A1
Автор: Greggory D. Donley
Принадлежит: Advanced Micro Devices Inc

A method and apparatus are described for selectively performing explicit and implicit data line reads. When a data line request is received, a determination is made as to whether there are currently sufficient data resources to perform an implicit data line read. If there are not currently sufficient data resources to perform an implicit data line read, a time period (number of clock cycles) before sufficient data resources will become available to perform an implicit data line read is estimated. A determination is then made as to whether the estimated time period exceeds a threshold. An explicit tag request is generated if the estimated time period exceeds the threshold. If the estimated time period does not exceed the threshold, the generation of a tag request is delayed until sufficient data resources become available. An implicit tag request is then generated.

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Номер записи: 51
07-06-2012 дата публикации

Method and apparatus of route guidance

Номер: US20120143504A1
Автор: Andrew Tesch Miller, Andrey Yuryevich Ulanov, Iljya Kalai, Keith Ito, Michael Siliski
Принадлежит: Google LLC

Systems and methods of route guidance on a user device are provided. In one aspect, a system and method transmit partitions of map data to a client device. Each map partition may contain road geometries, road names, road network topology, or any other information needed to provide turn-by-turn navigation or driving directions within the partition. Each map partition may be encoded with enough data to allow them to be stitched together to form a larger map. Map partitions may be fetched along each route to be used in the event of a network outage or other loss of network connectivity. For example, if a user deviates from the original route and a network outage occurs, the map data may be assembled and a routing algorithm may be applied to the map data in order to direct the user back to the original route.

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Номер записи: 52
07-06-2012 дата публикации

Monitoring processes in a computer

Номер: US20120144028A1
Автор: Andrew Hawkins, Geoff Collins, Mark Blackburn
Принадлежит: 1E Ltd

A monitoring program is run on a computer to identify a process running on the computer, and, for the identified process, determine whether or not one or more predetermined characteristics of the process complies with respective reference characteristics. This allows the program to automatically distinguish whether the process is likely to be a productive process or a non-productive process. For each characteristic a certainty value is incremented or decremented depending on whether the characteristic complies with the reference characteristic. Examples of characteristics are the time pattern of running of a process and the use of hardware resources by the process. Other characteristics include receiving input from a user and connections to known IP addresses. The monitoring process may be used to control power consumption to detect and run non-productive processes in a low power state.

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Номер записи: 53
07-06-2012 дата публикации

Dynamic adjustment of read/write ratio of a disk cache

Номер: US20120144109A1
Автор: Brian M. Rogers, Ganesh Balakrishnan, Gordon B. Bell, MVV Anil Krishna, Timothy H. Heil
Принадлежит: International Business Machines Corp

Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.

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Номер записи: 54
07-06-2012 дата публикации

Recommendation based caching of content items

Номер: US20120144117A1
Автор: Christopher B. Weare, Eric N. Lockard
Принадлежит: Microsoft Corp

Content item recommendations are generated for users based on metadata associated with the content items and a history of content item usage associated with the users. Each content item recommendation identifies a user and a content item and includes a score that indicates how likely the user is to view the content item. Based on the content item recommendations, and constraints of one or more caches, the content items are selected for storage in one or more caches. The constraints may include users that are associated with each cache, the geographical location of each cache, the size of each cache, and/or costs associated with each cache such as bandwidth costs. The content items stored in a cache are recommended to users associated with the cache.

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Номер записи: 55
07-06-2012 дата публикации

Read-ahead processing in networked client-server architecture

Номер: US20120144123A1
Автор: Konstantin Mushkin, Lior Aronovich, Oded SONIN
Принадлежит: International Business Machines Corp

Various embodiments for read-ahead processing in a networked client-server architecture by a processor device are provided. Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache.

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Номер записи: 56
07-06-2012 дата публикации

Apparatus, method, and system for instantaneous cache state recovery from speculative abort/commit

Номер: US20120144126A1
Автор: Hamid-Reza S. Bonakdar, Prashanth Nimmala
Принадлежит: Intel Corp

An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.

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Номер записи: 57
07-06-2012 дата публикации

Custom atomics using an off-chip special purpose processor

Номер: US20120144128A1
Автор: Benjamin C. Serebrin, Stephen D. Glaser
Принадлежит: Advanced Micro Devices Inc

An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

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Номер записи: 58
07-06-2012 дата публикации

Fast computer startup

Номер: US20120144177A1
Автор: Brian E. King, Emily N. Wilson, Kirsten V. Stark, Mehmet Iyigun, Neel Jain, Patrick L. Stemen, Sushu Zhang, Vasilios Karagounis, Yevgeniy Bak
Принадлежит: Microsoft Corp

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

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Номер записи: 59
14-06-2012 дата публикации

Method for operating flash memories on a bus

Номер: US20120151122A1
Автор: Ming-Hung Hsieh
Принадлежит: Individual

Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash.

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Номер записи: 60
14-06-2012 дата публикации

Systems and methods for background destaging storage tracks

Номер: US20120151148A1
Автор: Binny S. Gill, Brent C. Beardsley, Lokesh M. Gupta, Michael T. Benhase, Sonny E. WILLIAMS
Принадлежит: International Business Machines Corp

Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.

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Номер записи: 61
14-06-2012 дата публикации

Cache Line Fetching and Fetch Ahead Control Using Post Modification Information

Номер: US20120151150A1
Автор: Alexander Rabinovitch, Leonid Dubrovin
Принадлежит: LSI Corp

A method is provided for performing cache line fetching and/or cache fetch ahead in a processing system including at least one processor core and at least one data cache operatively coupled with the processor. The method includes the steps of: retrieving post modification information from the processor core and a memory address corresponding thereto; and the processing system performing, as a function of the post modification information and the memory address retrieved from the processor core, cache line fetching and/or cache fetch ahead control in the processing system.

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Номер записи: 62
14-06-2012 дата публикации

Systems and methods for managing cache destage scan times

Номер: US20120151151A1
Автор: Brent C. Beardsley, Lokesh M. Gupta, Michael T. Benhase, Sonny E. WILLIAMS
Принадлежит: International Business Machines Corp

Systems and methods for managing destage scan times in a cache are provided. One system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. Physical computer storage mediums including a computer program product for performing the above method are also provided.

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Номер записи: 63
14-06-2012 дата публикации

Reading core data in a ring bus type multicore system

Номер: US20120151152A1
Автор: Aya Minami, Yohichi Miwa
Принадлежит: International Business Machines Corp

The present invention provides a ring bus type multicore system including one memory, a main memory controller for connecting the memory to a ring bus; and multiple cores connected in the shape of the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling or managing the interface, and the cache controller of each of the cores connected in the shape of the ring bus executes a step of snooping data on the request through the cache interface; and when the cache of the core holds the data, a step of controlling the core to receive the request and return the data to the requester core, or, when the cache of the core does not hold the data, the main memory controller executes a step of reading the data from the memory and sending the data to the requester core.

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Номер записи: 64
14-06-2012 дата публикации

Virtual storage system and control method thereof

Номер: US20120151160A1
Автор: Ai Satoyama, Yoshiaki Eguchi
Принадлежит: Individual

A virtual storage system is equipped with a plurality of storage systems and a virtualization device for virtualizing the plurality of storage systems logically into a single storage resource provided to a host computer. When one of the storage systems receives a command from the host computer, in the event that the storage system itself is not in possession of a function corresponding to the command, the storage system retrieves a storage system in possession of a function corresponding to the command and transfers this command to the storage system in possession of the function corresponding to the command.

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Номер записи: 65
14-06-2012 дата публикации

Management of multiple software images with shared memory blocks

Номер: US20120151202A1
Автор: Claudio Marinelli, David Clerc, Jacques Fontignie, John G. Rooney, Luis Garcés-Eric, Marc V. Stückelberg
Принадлежит: International Business Machines Corp

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.

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Номер записи: 66
14-06-2012 дата публикации

Power-Saving Device for Universal Serial Bus Modem Apparatus and Method Thereof

Номер: US20120151239A1
Автор: Wei Wang
Принадлежит: ZTE Corp

A power-saving apparatus for universal serial bus (USB) modem equipment is disclosed in the present invention, which includes: a personal computer and USB Modem equipment. Accordingly, a power-saving method for USB Modem equipment is provided in the present invention, which includes: regularly detecting whether selective suspending is allowed, if not allowed, processing a received request from an application program, and if allowed, transmitting an instruction for entering the selective suspending state to the USB Modem equipment; after receiving the instruction for entering the selective suspending state, the USB Modem equipment entering the selective suspending state. Thus, the present invention can realize that the USB Modem equipment enters the power-saving state in the idle period and resumes the work state when receiving a service request.

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Номер записи: 67
14-06-2012 дата публикации

System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss

Номер: US20120151253A1
Автор: Robert L. Horn
Принадлежит: Western Digital Technologies Inc

Embodiments of the invention are directed to systems and methods for reducing an amount of backup power needed to provide power fail safe preservation of a data redundancy scheme such as RAID that is implemented in solid state storage devices where new write data is accumulated and written along with parity data. Because new write data cannot be guaranteed to arrive in integer multiples of stripe size, a full stripe's worth of new write data may not exist when power is lost. Various embodiments use truncated RAID stripes (fewer storage elements per stripe) to save cached write data when a power failure occurs. This approach allows the system to maintain RAID parity data protection in a power fail cache flush case even though a full stripe of write data may not exist, thereby reducing the amount of backup power needed to maintain parity protection in the event of power loss.

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Номер записи: 68
21-06-2012 дата публикации

System and method for handling io to drives in a raid system

Номер: US20120159067A1
Автор: Allen Kelton, Michael Richmond
Принадлежит: LSI Corp

A system and method for handling IO to drives in a RAID system is described. In one embodiment, the method includes providing a multiple disk system with a predefined strip size. IO request with a logical block address is received for execution on the multiple disk system. A plurality of sub-IO requests with a sub-strip size is generated, where the sub-strip size is smaller than the strip size. The generated sub-IO commands are executed on the multiple disk system. In one embodiment, a cache line size substantially equal to the sub-strip size is assigned to process the IO request.

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Номер записи: 69
21-06-2012 дата публикации

Protecting Data During Different Connectivity States

Номер: US20120159078A1
Автор: Apurva Ashwin Doshi, Bohdan W. Raciborski, Grigory Borisovich Lyakhovitskiy
Принадлежит: Microsoft Corp

Aspects of the subject matter described herein relate to data protection. In aspects, during a backup cycle, backup copies may be created for files that are new or that have changed since the last backup. If external backup storage is not available, the backup copies may be stored in a cache located on the primary storage. If backup storage is available, the backup copies may be stored in the backup storage device and backup copies that were previously stored in the primary storage may be copied to the backup storage. The availability of the backup storage may be detected and used to seamlessly switch between backing up files locally and remotely as availability of the backup storage changes.

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Номер записи: 70
21-06-2012 дата публикации

Direct Access To Cache Memory

Номер: US20120159082A1
Автор: Eric F. Robinson, Jason A. Cox, Kevin C. Lin, Nadav Levison, Omer Heymann
Принадлежит: International Business Machines Corp

Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

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Номер записи: 71
21-06-2012 дата публикации

Computer system management apparatus and management method

Номер: US20120159112A1
Автор: Takato Kusama, Yoshitaka Tokusho, Yuuki Miyamoto
Принадлежит: HITACHI LTD

The present invention makes it possible for different types of application programs to efficiently use a virtual volume created on a basis of a hierarchized pool. A configuration management part P 30 determines, based on access information, to which of storage tiers 211 actual areas 212 allocated to virtual volumes 220 should be allocated. The configuration management part comprises a determination part P 3020 for determining a type of an application program that uses an actual area, and reallocation destination instruction parts P 3021 and P 3022 for determining reallocation destinations of the actual areas in accordance with the determination result, and instructing the storage apparatus as to these determinations.

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Номер записи: 72
28-06-2012 дата публикации

Data management in solid-state storage devices and tiered storage systems

Номер: US20120166749A1
Автор: Evangelos S. Eleftheriou, Robert Haas, Xiao-yu HU
Принадлежит: International Business Machines Corp

A method for managing data in a data storage system having a solid-state storage device and alternative storage includes identifying data to be moved in the solid-state storage device for internal management of the solid-state storage; moving at least some of the identified data to the alternative storage instead of the solid-state storage; and maintaining metadata indicating the location of data in the solid-state storage device and the alternative storage.

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Номер записи: 73
28-06-2012 дата публикации

Weather adaptive environmentally hardened appliances

Номер: US20120167093A1
Автор: Aaron K. Shook, Andrew Ivory, Erik J. Burckart, Gennaro A. Cuomo, Victor S. Moore
Принадлежит: International Business Machines Corp

Embodiments of the present invention provide a method, system and computer program product for weather adaptive environmentally hardened appliances. In an embodiment of the invention, a method for weather adaptation of an environmentally hardened computing appliance includes determining a location of an environmentally hardened computing appliance. Thereafter, a weather forecast including a temperature forecast can be retrieved for a block of time at the location. As a result, a cache policy for a cache of the environmentally hardened computing appliance can be adjusted to account for the weather forecast.

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Номер записи: 74
05-07-2012 дата публикации

Solid state drive with low write amplification

Номер: US20120173795A1
Автор: Anthony Leach, Franz Michael Schuette
Принадлежит: OCZ Technology Group Inc

A solid state drive having a non-volatile memory device and methods of operating the solid state drive to compare existing data stored on the memory device to subsequent data in an incoming data stream received by the solid state drive from a host system. If matching data are found, the solid state drive uses the existing data instead of writing the subsequent data to the memory device. Common data patterns can be shared among different files stored on the memory device.

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Номер записи: 75
05-07-2012 дата публикации

Flash memory storage system

Номер: US20120173802A1
Автор: Kazuhisa Fujimoto, Shunji Kawamura, Takashige Iwamura, Yoshiaki Eguchi
Принадлежит: Individual

A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration.

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Номер записи: 76
05-07-2012 дата публикации

Methods of operating a memory system

Номер: US20120173804A1
Автор: Sergey Anatolievich Gorobets
Принадлежит: Micron Technology Inc

Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without having to store and/or retrieve, respectively, all portions of the data.

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Номер записи: 77
05-07-2012 дата публикации

Cache Result Register for Quick Cache Information Lookup

Номер: US20120173825A1
Автор: Kevin C. Heuer, Robert A. McGowan, Robert Ehrlich
Принадлежит: FREESCALE SEMICONDUCTOR INC

Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache's CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus.

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Номер записи: 78
05-07-2012 дата публикации

Apparatus and method for determining a cache line in an n-way set associative cache

Номер: US20120173844A1
Автор: Deepak Lala, Maghawan Punde
Принадлежит: LSI Corp

A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.

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Номер записи: 79
12-07-2012 дата публикации

Mobile information apparatus and display control method

Номер: US20120176353A1
Автор: Junichi Ishii
Принадлежит: NEC Corp

Multiple displays are arranged such that their display surfaces are arrayed side by side. A measurement section measures orientation information about apparatus orientation. A control section determines the display surface a user is viewing from among multiple displays, based on the orientation information measured by the measurement section. The control section causes the display surface of displays, other than the display surface determined as being viewed by the user, to become darker than the display surface of the display determined as being viewed by the user.

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Номер записи: 80
12-07-2012 дата публикации

Method and system for dynamic templatized query language in software

Номер: US20120179720A1
Автор: Christopher J. Kasten, Greg Seitz
Принадлежит: eBay Inc

A system to automatically generate query language in software is described. The system receives a request for data that is persistently stored in a database. The system selects a predefined query template from a number of query templates based on the request. The system utilizes the query template to receive content from at least one different source, the first source being a prototype data object. The system generates a query statement based on the query template that includes the content. Finally the system queries the database using the query statement to retrieve the requested data.

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Номер записи: 81
12-07-2012 дата публикации

Global instructions for spiral cache management

Номер: US20120179872A1
Автор: Volker Strumpen
Принадлежит: International Business Machines Corp

A method of operation of a pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and a spiral push-back network for pushing out modified values to the backing-store. The cache controller manages application of global commands by propagating individual commands to the tiles. The global commands may provide zeroing, flushing and reconciling of the given tiles. Commands for interrupting and resuming interrupted global commands may be implemented, to reduce halting or slowing of processing while other global operations are in process. A line detector within each tile supports reconcile and flush operations, and a line patcher in the controller provides for initializing address ranges with no processor intervention.

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Номер записи: 82
12-07-2012 дата публикации

Using ephemeral stores for fine-grained conflict detection in a hardware accelerated stm

Номер: US20120179875A1
Автор: Ali-Reza Adl-Tabatabai, Bratin Saha, Gad Sheaffer, Quinn Jacobson
Принадлежит: Individual

A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.

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Номер записи: 83
12-07-2012 дата публикации

Mechanism to support flexible decoupled transactional memory

Номер: US20120179877A1
Автор: Arrvindh Shriraman, Michael Scott, Sandhya Dwarkadas
Принадлежит: UNIVERSITY OF ROCHESTER

The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.

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Номер записи: 84
12-07-2012 дата публикации

Adaptively preventing out of memory conditions

Номер: US20120179889A1
Автор: Kirk J. Krauss
Принадлежит: International Business Machines Corp

A computer-implemented method of preventing an out-of-memory condition can include evaluating usage of virtual memory of a process executing within a computer, detecting a low memory condition in the virtual memory for the process, and selecting at least one functional program component of the process according to a component selection technique. The method also can include sending a notification to each selected functional program component and, responsive to receiving the notification, each selected functional program component releasing at least a portion of a range of virtual memory reserved on behalf of the selected functional program component.

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Номер записи: 85
19-07-2012 дата публикации

Method and system for cache endurance management

Номер: US20120185638A1
Автор: Daniel Schreiber, Judah Gamliel Hahn, Robert K. KHEDOURI
Принадлежит: Sandisk IL Ltd

A system and method for cache endurance management is disclosed. The method may include the steps of querying a storage device with a host to acquire information relevant to a predicted remaining lifetime of the storage device, determining a download policy modification for the host in view of the predicted remaining lifetime of the storage device and updating the download policy database of a download manager in accordance with the determined download policy modification.

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Номер записи: 86
19-07-2012 дата публикации

Distributed Storage Service Systems and Architecture

Номер: US20120185641A1
Автор: Alain Nochimowski, Itzhak Pomerantz, Micha Rave
Принадлежит: Sandisk IL Ltd

Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer.

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Номер записи: 87
19-07-2012 дата публикации

Computer architectures using shared storage

Номер: US20120185725A1
Автор: David D. Bettger, Dennis L. Kuehn, Kevin A. Stone, Marc A. Peters
Принадлежит: Boeing Co

A method includes providing a persistent common view of a virtual shared storage system. The virtual shared storage system includes a first shared storage system and a second shared storage system, and the persistent common view includes information associated with data and instructions stored at the first shared storage system and the second shared storage system. The method includes automatically updating the persistent common view to include third information associated with other data and other instructions stored at a third shared storage system in response to adding the third shared storage system to the virtual shared storage system.

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Номер записи: 88
26-07-2012 дата публикации

Blow molding apparatus

Номер: US20120189727A1
Автор: Daisaburo Takehana, Hiroshi Horigome, Kazuyuki Yokobayashi
Принадлежит: Nissei ASB Machine Co Ltd

A blow molding apparatus includes an injection molding station ( 12 ) that injection-molds preforms ( 1 A) held by N (N is an integer equal to or larger than 2) rows of holding plates ( 30 ), a temperature control station ( 14 ) that performs a temperature control operation on the preforms ( 1 A), a blow molding station ( 16 ) that blow-molds the preforms into containers, and a row pitch change section ( 130 ) that changes the row pitch of the N rows of holding plates so that P1<P3<P2 is satisfied, P1 being the row pitch of the N rows of holding plates when they hold the performs, P2 being the row pitch of the N rows of holding plates when they hold the containers, and P3 being the row pitch of the N rows of holding plates when they hold the preforms that are transferred to N rows of blow molds that are opened.

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Номер записи: 89
26-07-2012 дата публикации

Storage apparatus and method of managing data storage area

Номер: US20120191903A1
Автор: Akihiko Araki, Sadahiro Sugimoto, Yoshiki Kano, Yusuke Nonaka
Принадлежит: Individual

To extend endurance and reduce bit cost, a storage apparatus includes a controller and a first storage device and a second storage device having a smaller erase count upper limit than the first storage device. Area conversion information includes correspondence of a first address of a data storage destination and a second address of a data storage area The controller selects an area corresponding to the first address, determines whether a rewrite frequency of the selected area is equal to or larger than a first threshold and, when the rewrite frequency is equal to or larger than the threshold, selects an area of the first storage device, and, when the rewrite frequency is smaller than the threshold, selects an area of the second storage device and maps the address of the selected area to the first address.

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Номер записи: 90
26-07-2012 дата публикации

Managing Access to a Cache Memory

Номер: US20120191917A1
Автор: Subhendu Das, Xiao Jun Dai, ZHANG Yue, Zhi Gan
Принадлежит: International Business Machines Corp

Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

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Номер записи: 91
26-07-2012 дата публикации

Just in time garbage collection

Номер: US20120191936A1
Автор: David S. Ebsen, Ryan J. Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory is disclosed that includes multiple garbage collection units. The memory also includes a controller that determines whether to select a garbage collection unit of the multiple garbage collection units for garbage collection based on a variable threshold number of the multiple garbage collection units to garbage collect.

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Номер записи: 92
26-07-2012 дата публикации

Garbage collection management in memories

Номер: US20120191937A1
Автор: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson
Принадлежит: SEAGATE TECHNOLOGY LLC

The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect.

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Номер записи: 93
02-08-2012 дата публикации

Guest to native block address mappings and management of native code storage

Номер: US20120198122A1
Автор: Mohammad Abdallah
Принадлежит: Soft Machines Inc

A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

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Номер записи: 94
02-08-2012 дата публикации

Binary Rewriting in Software Instruction Cache

Номер: US20120198169A1
Автор: Brad W. Michael, Brian Flachs, John K.P. O&#39;Brien, Kathryn M. O&#39;Brien, Mark R. Nutter, Tao Zhang, Tong Chen
Принадлежит: International Business Machines Corp

Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

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Номер записи: 95
02-08-2012 дата публикации

Address-based hazard resolution for managing read/write operations in a memory cache

Номер: US20120198178A1
Автор: Eric F. Robinson, Jason A. Cox, Kevin CK Lin, Robert J. Dorsey
Принадлежит: International Business Machines Corp

One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

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Номер записи: 96
02-08-2012 дата публикации

Controlling power sequence in a blade center environment

Номер: US20120198261A1
Автор: Deanna Lynn Quigg Brown, II Ronald Ivan Olguin, Jason James Graves, Kevan D. Holdaway, Nhu Thanh Nguyen
Принадлежит: International Business Machines Corp

For controlling power sequence in a blade center environment, a relationship component module creates a topology of interdependent relationships of devices in the blade center environment. The devices include server blades, storage blades, and switch modules. A sequence module defines a sequence of the devices in the blade center environment to power off and on based on the topology of interdependent relationships. The sequence includes an order of a first independent blade server, each dependent storage blade of the first independent blade server, and a second independent blade server. A monitor component module monitors a command from an Advanced Management Module (AMM) to regulate power for the devices in the blade center environment. The AMM regulates power within the blade center. A validation module validates that the command does not violate the interdependent relationships and the sequence of devices or else blocks the command if the command is not validated.

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Номер записи: 97
09-08-2012 дата публикации

Storage control system with change logging mechanism and method of operation thereof

Номер: US20120203958A1
Автор: Joseph Taylor, Robert W. Ellis, Ryan Jones
Принадлежит: Smart Storage Systems Inc

A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory for persisting changes in the volatile memory table; and restoring a logical-to-physical table in the volatile memory table, after a power cycle, by restoring a random access memory with a logical-to-physical partition from a most recently used list.

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Номер записи: 98
09-08-2012 дата публикации

Selecting a virtual tape server in a storage system to provide data copy while minimizing system job load

Номер: US20120203964A1
Автор: Eiji Tosaka, Katsuyoshi Katori, Kohei Taguchi, Norie Iwasaki, Takeshi Nohta
Принадлежит: International Business Machines Corp

In a storage system including plural source storage devices, a target storage device selects which source storage device to accept a copy request from the target storage device so as to minimize the load on the entire system. The system calculates first and second load values for job loads being processed. System load values for the system are derived from job load value of a specific data, and respective load values for first and second source storage devices. The system compares the system load values to select a storage device to provide the data copy so as to minimize the load on the entire system.

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Номер записи: 99
09-08-2012 дата публикации

Coordinated writeback of dirty cachelines

Номер: US20120203968A1
Автор: Benjiman L. Goodman, David M. Daly, Hillery C. Hunter, Jeffrey A. Stuecheli, William J. Starke
Принадлежит: International Business Machines Corp

A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

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Номер записи: 100