METAL-INSULATOR-METAL CAPACITORS WITH ENLARGED CONTACT AREAS

Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

Verfahren, Vorrichtung und System zum Reduzieren einer Gate-Schnitt-Aushöhlung und/oder eines Gate-Höhenverlusts in Halbleitervorrichtungen

Verfahren, umfassend ein Bereitstellen eines Halbleitersubstrats; einer auf dem Halbleitersubstrat angeordneten Finne; eines Dummy-Gates, das über der Finne angeordnet ist, wobei das Dummy-Gate eine Oberseite auf einer ersten Höhe über dem Substrat aufweist; und eines Zwischenschichtdielektrikums (ILD), das über der Finne und neben dem Dummy-Gate angeordnet ist, wobei die ILD eine Oberseite auf einer zweiten Höhe über dem Substrat aufweist, wobei die zweite Höhe unter der ersten Höhe liegt; und ein Abdecken der ILD mit einer dielektrischen Kappe, wobei die dielektrische Kappe eine Oberseite auf der ersten Höhe aufweist. Systeme, die zur Implementierung der Methoden konfiguriert sind. Halbleitervorrichtungen, die durch die Verfahren hergestellt werden.

Sewage treatment piece -rate system with outer lining reinforcing complex film

The utility model provides a sewage treatment piece -rate system with outer lining reinforcing complex film, sewage treatment piece -rate system with outer lining reinforcing complex film, including aeration pipe, gas flowmeter, air -blower, pressure sensor, suction pump, fluidflowmeter, product water pipe, inlet tube, membrane cisterna, outer lining reinforcing hollow fiber membrane membrane module and automatic control cabinet, the aeration pipe is placed in the outer lining reinforcing hollow fiber membrane membrane module below of membrane cisterna bottom, and aeration union coupling gas flowmeter, gas flowmeter pass through the pipe connection air -blower, and outer lining reinforcing hollow fiber membrane membrane module passes through pipeline connection pressure sensor, and the inlet tube is placed in the top of membrane cisterna and water injection in to the membrane cisterna, outer lining reinforcing hollow fiber membrane membrane module combines hollow fiber membrane and the ...

Semiconductor structure having logic region and analog region

A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Hardmask for a halo/extension implant of a static random access memory (SRAM) layout

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

Automatic management method of simulation test process of overall performance of gliding flying machine

The invention relates to an automatic management method of the simulation test process of overall performance of a gliding flying machine. The method includes the steps of grid information pre-processing, grid search algorithm performing, mapping relation algorithm selection, information mapping, post-processing and the like. According to the method, input grid information is decomposed into a plurality of sub problems through analysis, proper solving methods are sequentially searched for from all modules according to characteristics of the grid information, and all the methods are organically combined. By using the method, information mapping can be performed in various heterogeneous grids, limitations of the grid division method and information content needing to be mapped are avoided, and significant stimulation effect is played for communication among various professional fields.

T-shaped contacts for semiconductor device

A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Non-planar semiconductor device with multiple-head epitaxial structure on fin

A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor. 1. A device , comprising:a pull-down (PD) transistor formed over a substrate;a pass-gate (PG) transistor formed over the substrate; anda hardmask formed over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor.2. The device according to claim 1 , wherein the distance between the first section and the PD transistor prevents a halo/extension implant from impacting a first side of the PD transistor.3. The device according to claim 2 , wherein the halo/extension implant comprises a first implant at a first angle and a second implant at a second angle.4. The device according to claim 3 , wherein the second section of the hardmask is configured to allow the first implant to impact the following: the first side of the PD transistor claim 3 , a second side of the PD transistor claim 3 , a first side of the PG transistor claim 3 , and a second side of the PG ...

A METHOD OF MANUFACTURING FINFET DEVICES USING NARROW AND WIDE GATE CUT OPENINGS IN CONJUCTION WITH A REPLACEMENT METAL GATE PROCESS

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

EPITAXIAL REGION FOR EMBEDDED SOURCE/DRAIN REGION HAVING UNIFORM THICKNESS

A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask. 19-. (canceled)10. A method of forming an embedded source/drain region in a substrate , the method comprising:forming a trench in the substrate adjacent to a gate structure positioned thereon, the trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottommost surface extending between the first sidewall and the second sidewall;forming a first epitaxial region at least partially in the trench;forming a first spacer layer on the gate structure and on a portion of an uppermost surface of the first epitaxial region adjacent to the gate structure;removing a first portion of the first epitaxial region using the first spacer layer as a mask, wherein after the removing the first portion of the epitaxial region a thickness of a remaining portion of the epitaxial region has a substantially uniform sidewall thickness; andforming a second epitaxial region in the trench abutting the remaining portion of the first epitaxial region to form the embedded source/drain region.11. The method of claim 10 , wherein removing the first ...

FABRICATING FIN STRUCTURES WITH DOPED MIDDLE PORTIONS

Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

Copper-coated chromium composite powder and preparation method and application thereof

The invention discloses copper-coated chromium composite powder which comprises an inner core and an outer coating layer. The inner core is mainly irregular particles formed by chromium powder, the diameter of each particle is smaller than 75 microns, and the outer coating layer is mainly a continuous Cu metal layer. A preparation method of the copper-coated chromium composite powder comprises the steps that chromium powder is pretreated; electroless copper plating is conducted on the outer surface of the chromium powder, an electroless plating solution is composed of soluble copper salt, a complexing agent, strong base, a reducing agent, potassium ferrocyanide and an addition agent, the power of hydrogen and the steam pocket of the electroless plating solution are monitored in real time in the electroless copper plating process, and main components in the electroless plating solution are continuously supplemented according to changes; surface passivating treatment is conducted on the composite ...

Methods for forming FinFETs with reduced series resistance

A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

Epi facet height uniformity improvement for fdsoi technologies

Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Fin structure in sublitho dimension for high performance CMOS application

A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.

Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits

A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.

Self-aligned junction structures

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.

Fin-type field effect transistors with single-diffusion breaks and method

Device for improving performance through gate cut last process

Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

Semiconductor Device with Air Gaps Between Metal Gates and Method of Forming the Same

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure. 1. A semiconductor device comprising:a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; anda separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.2. The semiconductor device of claim 1 , further comprising a sealing layer disposed over the first dielectric layer and the second dielectric layer and covering an opening of the air gap.3. The semiconductor device of claim 1 , wherein a material of the first dielectric layer is silicon nitride (SiN).4. The semiconductor device of claim 1 , wherein the air gap is formed between a top portion of the first dielectric layer and a top portion of the second dielectric layer claim 1 , and a supporting layer is formed between a bottom portion of the ...

Stress-Inducing Silicon Liner in Semiconductor Devices

A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner. 1. A method , comprising:providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;forming a silicon liner over the semiconductor device, wherein the silicon liner includes elemental silicon;forming an interlayer dielectric (ILD) layer over the silicon liner;introducing a dopant species to the ILD layer;subsequent to introducing the dopant species, removing the dummy gate structure to form a gate trench;performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner; andforming a metal gate stack in the gate trench and over the oxidized silicon liner.2. The method of claim 1 , wherein the thermal treatment is a first thermal treatment claim 1 , the method further comprising performing a second thermal treatment to the ILD layer before introducing the dopant species claim 1 , wherein performing the second thermal treatment partially oxidizes the silicon liner.3. The method of claim 2 , wherein the first thermal treatment is performed at a first temperature claim 2 , and wherein the second thermal treatment is performed at a second temperature lower than the first ...

Fin structures and multi-Vt scheme based on tapered fin and method to form

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Forming self-aligned NiSi placement with improved performance and yield

Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

Hybrid-Gate-Schnitt

In Verbindung mit einem Austausch-Metall-Gate (RMG) -Prozess zur Bildung eines Finnen-Feldeffekttransistors (FinFET) nutzen Gate-Isolationsverfahren und zugehörige Strukturen die Bildung von unterschiedlichen schmalen und breiten Gateschnittbereichen in einem Opfergate. Die Bildung eines schmalen Gateschnitts zwischen eng beabstandeten Finnen kann das Ausmaß des Ätzschadens an dielektrischen Zwischenschichtschichten benachbart zu dem schmalen Gateschnitt verringern, indem die Abscheidung solcher dielektrischen Schichten bis nach der Bildung der schmalen Gateschnittöffnung verzögert wird. Die Verfahren und resultierenden Strukturen verringern auch die Neigung zu Kurzschlüssen zwischen später gebildeten benachbarten Gates.

Nanosheet-Transistor mit verbessertem inneren Abstandshalter

Ein Verfahren zum Bilden von Nanosheet- und Nanodraht-Transistoren umfasst die Bildung von alternierenden epitaktischen Schichten aus Silizium-Germanium (SiGe) und Silizium (Si), wobei der Germaniumgehalt innerhalb entsprechender Schichten aus Silizium-Germanium systematisch variiert wird, um das selektive Ätzen dieser Schichten herbeizuführen. Der Germaniumgehalt kann gesteuert werden, so dass ausgesparte Bereiche, die durch ein teilweises Entfernen der Silizium-Germanium-Schichten erzeugt werden, gleichförmige seitliche Dimensionen aufweisen, und das Hinterfüllen von jedem dieser ausgesparten Bereiche mit einem selektiv ätzbaren Material in der Bildung einer robusten Ätzbarriere resultiert.

METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES

One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity. 1. A method , comprising:forming a sacrificial gate structure above a semiconductor substrate, said sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure;forming a gate cap layer above said multi-layer sacrificial gate electrode structure of said sacrificial gate structure;removing said sacrificial gate structure to form a replacement gate cavity; andforming a replacement gate structure in said replacement gate cavity.2. (canceled)3. The method of claim 1 , wherein said sacrificial gate structure is formed for one of a FinFET device claim 1 , a planar transistor device or a vertical transistor device.4. The method of claim 1 , wherein said multi-layer sacrificial gate electrode structure comprises first and second layers of sacrificial gate electrode material.5. The method of claim 4 , wherein said first and second layers of sacrificial gate electrode material are made of first and second materials claim 4 , respectively claim 4 , wherein said first and second materials may be selectively etched relative to one another.6. The method of claim 1 , wherein said replacement gate structure comprises a high-k replacement gate insulation layer and a replacement gate electrode that comprises at least one metal-containing layer of material.7. The method of claim 4 , wherein said sacrificial gate insulation layer is formed by performing a first conformal deposition process claim 4 , said first layer of sacrificial gate electrode material is formed by performing a second conformal ...

Preventing bridge formation between replacement gate and source/drain region through STI structure

A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

FINFET FABRICATION METHOD

Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins. 1. A method of forming a semiconductor structure , comprising:forming a nitride liner on a semiconductor substrate;forming a plurality of sacrificial material regions on the nitride liner;forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;removing the plurality of sacrificial material regions;removing the second set of spacers while preserving the first set of spacers; andforming fins on the semiconductor substrate.2. The method of claim 1 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of amorphous silicon regions.3. The method of claim 1 , wherein forming a first set of spacers and a second set of spacers comprises depositing silicon nitride.4. The method of claim 1 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of silicon oxide regions.5. The method of claim 1 , further comprising:forming a plurality of shallow trench isolation regions in the semiconductor substrate; andwherein forming a plurality of sacrificial material regions on the nitride liner comprises forming each sacrificial material region in an off-center alignment with a corresponding shallow trench isolation region.6. ...

Integrated Circuits with Channel-Strain Liner

Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain. 1. An integrated circuit device comprising:a substrate;a fin extending from the substrate;a gate disposed on the fin and having a bottom portion disposed towards the fin and a top portion disposed on the bottom portion; anda liner disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner.2. The integrated circuit device of claim 1 , wherein the liner is configured to produce a channel strain.3. The integrated circuit device of claim 1 , wherein the liner has a height that is between about 1/100 and about ⅘ of a height of the gate.4. The integrated circuit device of claim 1 , wherein a majority of the gate is free of the liner.5. The integrated circuit device of claim 1 , wherein:the substrate includes a first region with a first device having a first channel type and a second region with a second device having a second channel type;the first region includes the liner; andthe second region is free of the liner.6. The integrated circuit device of claim 1 , wherein the fin includes a source/drain feature and the liner is disposed on the source/drain feature.7. The integrated circuit device of further comprising an etch stop layer disposed between the liner and the side surface of the bottom portion of the gate.8. The integrated circuit device of further comprising an inter-level dielectric layer disposed on the liner claim 7 , wherein ...

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Nanowire transistors having multiple threshold voltages

Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.

Integrated circuit fabrication with boron etch-stop layer

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.

Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device

Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Dehumidification device with low power consumption

The invention relates to a dehumidification device with low power consumption, mainly comprising a body, a dehumidification component and a heat conduction component, wherein the dehumidification component has a dehumidification area and a regeneration area; the heat conduction component comprises a refrigeration end and a heating end, and a high-temperature condensing effect and a high-temperature heating effect can be simultaneously generated by the refrigeration end and the heating end, therefore, high waste heat generated by the dehumidification device is effectively recycled, and the electric energy loss of the dehumidification device can be further reduced.

Contact structures

MULTIPLE FIN HEIGHTS WITH DIELECTRIC ISOLATION

Fin-type field effect transistors with single-diffusion breaks and method

Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF

Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch

Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack.

Integrated circuit fabrication with boron etch-stop layer

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain. 1. A vertical FinFET device comprising:a fin disposed on a semiconductor substrate, the fin having a lower end in contact with a well region disposed within the substrate;a main gate stack comprising a main gate dielectric and main gate conductor disposed over at least one sidewall of the fin and extending laterally over a portion of the well region on at least one side of the fin;a channel region between the main gate conductor and the fin and between the main gate conductor and the well region on the at least one side of the fin; anda bottom source/drain region laterally adjacent to the well region on the at least one side of the fin, wherein the portion of the well region underlying the main gate stack is disposed between the bottom source/drain region and the well region in contact with the lower end of the fin.2. The vertical FinFET device of claim 1 , wherein a length of the channel region on the at least one side of the fin is greater than a height (H) of the fin.3. The vertical FinFET device of claim 1 , wherein the main gate dielectric disposed over the fin and extending laterally over the well region comprises a ...

Preparation method of tunneling field effect transistor

The invention provides a preparation method of a tunneling field effect transistor, and belongs to the technical field of micro-nano electronics. On the basis of a basic tunneling field effect transistor structure, a medium-concentration silicon material with the same doping type as a drain region or a source region is prepared between the surface of a substrate and a gate stack by adopting an epitaxial method to serve as a channel region, so that the gate voltage of the tunneling field effect transistor for channel inversion is reduced or increased; therefore, the turn-on voltage of the tunneling field effect transistor is reduced or increased. Meanwhile, the thickness of the channel region is relatively small, and a substrate region main body of the device is still lightly doped high-resistance silicon, so that the advantage of low off-state current of the tunneling field effect transistor is maintained. The method can be compatible with the CMOS technology and can be used for integration ...

Integrated Circuits with Channel-Strain Liner

Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain. 1. A method comprising:forming a fin structure over a substrate;forming a first gate stack over the fin structure;forming a source/drain feature in the fin structure;forming an etch stop layer on the first gate stack and the source/drain feature;forming a semiconductor liner layer on the etch stop layer disposed on the first gate stack and the source/drain feature;removing a first portion of the semiconductor liner layer from over the first gate stack such that a second portion of the semiconductor liner layer extends along a bottom portion of the first gate stack without extending to a top portion of the first gate stack after the removing of the first portion of the semiconductor liner layer; andoxidizing the second portion of the semiconductor liner layer to form an oxidized liner layer disposed on the bottom portion of the first gate stack.2. The method of claim 1 , further comprising forming an interlayer dielectric layer over the second portion of the semiconductor liner layer after the removing of the first portion of the semiconductor liner layer from over the first gate stack.3. The method of claim 1 , further comprising:removing a portion of the first gate stack to form a trench; andforming a gate electrode layer within the trench.4. The method of claim 3 , wherein a portion of the fin structure is exposed within the trench after the removing of the portion of the first gate stack to ...

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain. 1. A vertical FinFET device comprising:a fin disposed on a semiconductor substrate, the fin having a lower end in contact with a well region disposed within the substrate;a main gate stack comprising a main gate dielectric and main gate conductor disposed over at least one sidewall of the fin and extending laterally over a portion of the well region on at least one side of the fin;a channel region between the main gate conductor and the fin and between the main gate conductor and the well region on the at least one side of the fin; anda bottom source/drain region laterally adjacent to the well region on the at least one side of the fin, wherein the portion of the well region underlying the main gate stack is disposed between the bottom source/drain region and the well region in contact with the lower end of the fin.2. The vertical FinFET device of claim 1 , wherein a length of the channel region on the at least one side of the fin is greater than a height (H) of the fin.3. The vertical FinFET device of claim 1 , wherein the main gate dielectric disposed over the fin and extending laterally over the well region comprises a ...

NANOSHEET FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE/DRAIN ISOLATION

Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A seed layer is epitaxially grown on a substrate, and a layer stack is epitaxially grown on the seed layer. The layer stack includes a first plurality of semiconductor layers and a second plurality of semiconductor layers alternatingly arranged with the first plurality of semiconductor layers. The layer stack is patterned to form a body feature located on the seed layer. The body feature includes a plurality of nanosheet channel layers patterned from the first plurality of semiconductor layers and a plurality of sacrificial layers patterned from the second plurality of semiconductor layers. Semiconductor material for a source/drain region is epitaxially grown laterally from the nanosheet channel layers and vertically from the seed layer. 1. A method for forming a field-effect transistor , the method comprising:epitaxially growing a seed layer on a substrate;epitaxially growing a layer stack on the seed layer, the layer stack including a first plurality of semiconductor layers and a second plurality of semiconductor layers alternatingly arranged with the first plurality of semiconductor layers;patterning the layer stack to form a body feature on the seed layer and to expose a portion of the seed layer adjacent to the body feature, the body feature including a plurality of nanosheet channel layers patterned from the first plurality of semiconductor layers and a plurality of sacrificial layers patterned from the second plurality of semiconductor layers; andepitaxially growing a semiconductor material for a source/drain region laterally from a side surface of the plurality of nanosheet channel layers and vertically from the seed layer.2. The method of wherein the seed layer is composed of a rare-earth metal oxide.3. The method of wherein the rare-earth metal oxide includes one or more rare-earth metal elements selected from the group consisting ...

Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices

One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices

Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices are disclosed. Embodiments include providing a polysilicon dummy gate electrode between spacers and extending over a BP, an active area of a transistor, and a shallow-trench-isolation (STI) region therebetween; providing an interlayer dielectric surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work-function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate electrode; and planarizing the metal down to an upper surface of the spacers.

Methods, apparatus and system for gate cut process using a stress material in a finFET device

At least one method, apparatus and system disclosed herein involves a gate cut process using a stress material for a finFET device. A set of fins are formed on a semiconductor substrate. A gate region is formed above a portion of the set of fins. A gate cut trench is formed within the gate region. A dielectric material comprising an intrinsic stress is deposited into the gate cut region. A replacement metal gate process is performed in the gate region. Residue metal features are removed about the gate cut region.

Electric field type wireless power transmission compensation system and design method, device and design method

The invention discloses an electric field type wireless power transmission bilateral MC compensation system, a design method, a device and a design method.The system comprises an inverter, a coupler, a rectifier and an MC compensation network, the MC compensation network comprises a primary side compensation network and a secondary side compensation network, the inverter is connected with the coupler through the primary side compensation network, and the secondary side compensation network is connected with the coupler through the secondary side compensation network; the coupler is connected with the rectifier through a secondary side compensation network; wherein the primary side compensation network comprises a primary winding and a first capacitor, the primary winding comprises a first winding and a second winding, a winding coil of the first winding and a winding coil of the second winding are connected end to end to form the primary winding, the input end of the primary winding is ...

New fin structures and multi-vt scheme based on tapered fin and method to form

Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits

A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.

DEHUMIDIFYING APPARATUS OF LOW POWER CONSUMPTION

PROBLEM TO BE SOLVED: To provide a dehumidifying apparatus of the dehumidifying rotor type with low power consumption. SOLUTION: The dehumidifying apparatus is provided with a body (200), a dehumidifying member (20) and heat conduction members (22, 24). The dehumidifying member (20) has a dehumidifying area (20A) and regeneration area (20B) and the heat conduction members (22, 24) have a cooling side (221) and a heating side (241). High waste heat by the dehumidifying apparatus (20) can be recovered by simultaneously producing the elevated temperature condensation effect and the high temperature heating effect by the cooling side (221) and heating side (241), and further the power consumption due to the dehumidifying apparatus can be reduced. COPYRIGHT: (C)2010,JPO&INPIT ...

Fin-FET replacement metal gate structure and method of manufacturing the same

A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.

Vertical field effect transistor formation with critical dimension control

Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

Membrane bio -reactor (MBR) membrane module structure

The utility model relates to a membrane bio -reactor (MBR) membrane module structure goes up membrane shell, lower membrane shell and filter screen pocket, have thousands of filtration membrane silk up to a hundred between the upper and lower membrane shell, the upper and lower both ends of filtration membrane silk are sealed respectively and are moulded in upper and lower membrane shell, and filtration membrane silk, last membrane shell and lower membrane shell set up in the filter screen pocket, form the rivers passageway between the outer wall of two adjacent filter screen pockets, set up a filter screen pocket through the outside at the filtration membrane silk, during the operation, the even interval arrangement of membrane module of a plurality of area filter screen is laid on the ware fixed bolster is organized to the membrane, sewage gets into membrane group ware during the aeration, upwards flow along the rivers passageway between two filter screen pocket outer walls, rivers must ...

Semiconductor structure, preparation method thereof and electronic equipment

The embodiment of the invention discloses a semiconductor structure, a preparation method thereof and electronic equipment. The electronic device includes: a substrate; a hard mask plate, wherein the hard mask plate is formed on the substrate; the through hole penetrates through the hard mask plate and extends to the substrate, the through hole is filled with a first conductor material, the first conductor material is etched back by a set depth through corrosion so as to form an opening of the through hole, an isolation layer is formed at the opening of the through hole, the isolation layer covers the edge of the first conductor material, and the isolation layer covers the edge of the first conductor material. The first conductor material is exposed in the middle of the isolating layer; and the middle part of the isolation layer is filled with the second conductor material, and a blocking adhesion layer is arranged between the first conductor material and the second conductor material.

Source/drain contact spacers and methods of forming same

Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlevel dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature ...

Flat surface contacted voltage regulator with big capacity

A high-capacity plane-contact type voltage regulator has winding and bruch groups. Each brushing group has to brushes arranged staggered for ensuring the good contact between winding and brush at anytime to output current continuously. Its advantages are low contact temp. and low-grade spark.

Method of forming mandrel and non-mandrel metal lines having variable widths

A method includes providing a semiconductor structure having a silicon mandrel layer, a hardmask stack and a dielectric layer. A 1st portion and a 2nd portion of the mandrel layer are doped with a 1st concentration and a 2nd greater concentration of dopant respectively. 1st and 2nd mandrels are patterned into the 1st and 2nd portions of the mandrel layer respectively. The 1st and 2nd mandrels are oxidized in the same thermal oxidation process to form 1st oxidation spacers on sidewalls of the 1st mandrels and 2nd oxidation spacers on sidewalls of the 2nd mandrels. The 2nd oxidation spacers have a thickness that is greater than a thickness of the 1st oxidation spacers. The 1st and 2nd oxidation spacers are utilized to form 1st and 2nd metal lines respectively in the dielectric layer. The 1st and 2nd metal lines have a different thickness.

Fault analysis method and system applied to nucleic acid detector

The embodiment of the invention provides a fault analysis method and system applied to a nucleic acid detector, and the method comprises the steps: determining a representation feature vector of candidate fault log data under a plurality of fault linkage evaluation indexes based on the obtained fault triggering data of the candidate fault log data under the plurality of fault linkage evaluation indexes; therefore, fault linkage confidence values among the candidate fault log data are determined, and target fault linkage characteristics of the candidate fault log data are determined according to the fault linkage confidence values among the candidate fault log data, so that the target fault linkage characteristics of the candidate fault log data are determined according to a plurality of fault linkage evaluation indexes. The fault linkage confidence value between the candidate fault log data is determined more perfectly, so that the evaluation of the fault linkage confidence value between ...

Vertical field effect transistor

The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.

CONTACT STRUCTURES

The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material. 1. A structure comprising:an active gate structure composed of conductive material located between sidewall material;an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; anda contact structure in electrical contact with the conductive material of the active gate structure, the contact structure being located between the sidewall material and between the upper sidewall material, wherein:the sidewall material is a low-k dielectric material and the upper sidewall material has an etch selectivity different than the low-k dielectric material;the upper sidewall material separates the contact structure for the active gate structure from a contact structure of a source/drain region of the active gate structure; anda lower portion of the contact structure of the source/drain region is located between the sidewall material and an upper portion of the contact structure of the source/drain region is located between the upper sidewall material.2. (canceled)3. The structure of claim 1 , wherein the upper sidewall material is a high-k dielectric material.4. The structure of claim 1 , wherein the upper sidewall material is a metal oxide material.5. (canceled)6. (canceled)7. The structure of claim 1 , wherein the contact structure of the source/drain region is separated from the conductive ...

Cervical vertebra traction therapeutic equipment

The invention relates to a cervical traction therapy apparatus comprising a footstock, a neck ring, a hauling rope unit and a retractor. The hauling rope unit is arranged between the footstock and the neck ring for connection. The hauling rope unit is used for connecting the footstock with the hauling rope unit and leads the neck ring to the particular position where the neck ring is arranged under the footstock. One end of the hauling rope unit is connected with the neck ring and the stressed included angle of the hauling rope unit corresponding to the footstock can be changed, thus achieving the purpose of changing the direction and the angle of the neck ring by coordinating with the hauling rope unit. Therefore, the cervical traction therapy apparatus is designed to provide function ofadjusting the hauling direction and the angle of traction.

Cervical vertebra traction therapeutic equipment

The invention relates to a cervical traction therapy apparatus comprising a footstock, a neck ring, a hauling rope unit and a retractor. The hauling rope unit is arranged between the footstock and the neck ring for connection. The hauling rope unit is used for connecting the footstock with the hauling rope unit and leads the neck ring to the particular position where the neck ring is arranged under the footstock. One end of the hauling rope unit is connected with the neck ring and the stressed included angle of the hauling rope unit corresponding to the footstock can be changed, thus achieving the purpose of changing the direction and the angle of the neck ring by coordinating with the hauling rope unit. Therefore, the cervical traction therapy apparatus is designed to provide function of adjusting the hauling direction and the angle of traction.

Dielectric preservation in a replacement gate process

Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.

Methods of cutting gate structures on transistor devices

One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

Rear-loading compression type garbage truck floating type canister overturning device

The invention discloses a floating type tube turning device of a back feeding compression garbage truck which includes a stent, an upper pressure plate, a support plate, cylinder, a groove guiding plate, a movable guide plate and a cylinder support plate. The groove guiding plate which is arranged on the truck body of the compression garbage truck is equipped with an arc guide groove. The lower part of the cylinder is equipped with an open slot which is arranged on the truck body and under the groove guiding plate. The lower end of the movable guide plate is equipped with an arc guide groove,the upper end of which is equipped with a pin. The pin is arranged in a pin seat on the truck body. The pin seat is arranged above the cylinder support plate. The upper end of the stent is equipped with a pin which is arranged in the arc guide groove of the groove guiding plate. The lower end of the stent is equipped with a pin which is arranged in the arc guide groove of the movable guide plate.The ...

Parameter compensation method for IPT system under variable coupling working condition

The invention relates to the technical field of wireless charging, in particular to a parameter compensation method for an IPT system under a variable coupling working condition, and the method comprises the steps: obtaining a primary side resonance compensation capacitor based on the working frequency of an S-S type wireless power supply system and the self-inductance calculation of a primary side coil; obtaining secondary side resonance compensation capacitance based on the working frequency of the S-S type wireless power supply system and secondary side coil self-inductance; calculating primary side and secondary side equivalent compensation capacitance based on the Kirchhoff circuit law and equivalent impedance angle conversion; and carrying out series equivalence on the equivalent compensation capacitor and the resonance compensation capacitor to respectively obtain the primary side compensation capacitor and the secondary side compensation capacitor of the system. According to the ...

Doctor Ai portrait auxiliary diagnosis and treatment system

The invention provides a doctor Ai portrait auxiliary diagnosis and treatment system. The system comprises the following steps: inputting medical record information of a patient into inquiry equipment; carrying out auxiliary inquiry on the medical record information of the patient under an Ai portrait auxiliary plug-in; the Ai portrait auxiliary plug-in outputs suspected illness conditions and diagnosis evaluation; obtaining a data report according to the suspected illness state and the diagnosis evaluation; combining the data report with doctor diagnosis to obtain an examination result; recommending a treatment scheme according to the examination result; the treatment scheme is sent back to the Ai portrait auxiliary plug-in to collect data; the diagnosis prompt information is optimized and simplified, the recommendation that doctors are familiar with disease categories is reduced, and the information utilization rate of the doctors is improved; invalid calling is reduced, and the system ...

Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures

The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

Gate Cut Dielectric Feature and Method of Forming the Same

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

Kontaktstrukturen

Die vorliegende Erfindung betrifft Halbleiterstrukturen und insbesondere einen Kontakt über einer Aktivgate-Struktur und Verfahren zur Herstellung. Die Struktur umfasst: eine Aktivgate-Struktur gebildet aus einem leitfähigen Material, das zwischen einem Seitenwandmaterial angeordnet ist; ein oberes Seitenwandmaterial über dem Seitenwandmaterial, wobei das obere Seitenwandmaterial von dem Material des Seitenwandmaterials verschieden ist; und eine Kontaktstruktur in einem elektrischen Kontakt mit dem leitfähigen Material der Aktivgate-Struktur. Die Kontaktstruktur ist zwischen dem Seitenwandmaterial und zwischen dem oberen Seitenwandmaterial angeordnet.

Fins with single diffusion break facet improvement using epitaxial insulator

The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

Fin-type field effect transistors with single-diffusion breaks and method

Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

NITRIDE LAYER PROTECTION BETWEEN PFET SOURCE/DRAIN REGIONS AND DUMMY GATE DURING SOURCE/DRAIN ETCH

Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack. 1. A method comprising:forming an oxide layer on a substrate;forming a nitride protection layer on the oxide layer;forming a dummy gate layer on the nitride protection layer;patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate;forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively;forming first and second low-k dielectric spacers at opposite sides of the first and second dummy gate stacks, respectively;growing first and second embedded silicon germanium (eSiGe) source/drain regions in the first and second source/drain cavities, respectively;removing the first dummy gate and the second dummy gate stack;removing the nitride protection layer from the first ...

FORMING SELF-ALIGNED NiSi PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD

Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions 1. A method comprising:forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate;forming embedded silicon germanium (eSiGe) source/drain regions at opposite sides of the first dummy gate;forming raised source/drain regions at opposite sides of the second dummy gate;forming a silicon cap on each of the eSiGe and raised source/drain regions;forming an interlayer dielectric (ILD) over and between the first and second dummy gates;replacing the first and second dummy gates with first and second high-k/metal gates (HKMG), respectively;forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; andforming a silicide over the eSiGe and raised source/drain regions.2. The method according to claim 1 , further comprising forming second spacers at opposite sides of each of the first and second dummy gates prior to forming the silicon cap.3. The method according to claim 2 , comprising forming the second spacers to a width of 1 to 20 nanometers (nm).4. The method according to claim 1 , comprising forming the silicon caps by epitaxially growing silicon on the eSiGe and raised ...

Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product

One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES

A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers. 1. A device comprising:a gate structure formed on a silicon-on-insulator (SOI) layer;a first pair of spacers formed on the SOI layer and on opposite sides of the gate structure;a second pair of spacers formed adjacent to and on the opposite sides of the gate structure, the second pair of spacers being more selective to epitaxial growth than the first pair of spacers; anda pair of faceted raised source/drain structures formed on the SOI, each of the source/drain structures faceted at the upper surface of the first pair of spacers.2. The device according to claim 1 , wherein each of the first pair of spacers has a greater width than each of the second pair of spacers.3. The device according to claim 2 , wherein each of the first pair of spacers has a width of 5 nm to 10 nm and a height of 5 nm to 15 nm.4. The device according to claim 3 , wherein each of the second pair of spacers has a width of 3 nm to 4 nm.5. The device according to claim 1 , wherein the second pair of spacers is formed either on the SOI layer or on an upper surface of the first pair of spacers.6. The device according to claim 1 , wherein the first pair of spacers are formed of furnace nitride by molecular layer deposition (MLD) or of deposited nitride by plasma enhanced ...

DESIGN STRUCTURES AND METHODS FOR EXTRACTION OF DEVICE CHANNEL WIDTH

Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths. 1. A method comprising:determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors; anddetermining a target channel width for a target transistor based on the effective channel widths.2. The method according to claim 1 , further comprising:determining respective total capacitances of the plurality of integrated circuits between gate nodes and shorted source, drain, and/or substrate nodes of the transistors; anddetermining the effective channel widths based, at least in part, on the respective total capacitances.3. The method according to claim 2 , wherein transistors for each integrated circuit have a single drawn channel width claim 2 , and the single drawn channel width varies between the plurality of integrated circuits.4. The method according to claim 2 , wherein each transistor includes a gate dielectric layer claim 2 , with the gate dielectric layer varying between groups of the plurality of integrated circuits.5. The method according to claim 2 , further comprising:determining overlap capacitance between the gate node and the source node and/or the drain corresponding to the plurality of integrated circuits; anddetermining the effective channel widths based, at least in part, on the overlap capacitance.6. The method according to claim 1 , further comprising:determining respective metal line capacitances between metal lines and substrates, without gate, source, and drain contacts for the transistors, of the plurality of integrated circuits; anddetermining the effective channel widths based, at least in part, on the ...

IC PRODUCT COMPRISING A NOVEL INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES

One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.

Composite contact etch stop layer

Composite contact etch stop layer

A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

COMPOSITE SPACERS FOR TAILORING THE SHAPE OF THE SOURCE AND DRAIN REGIONS OF A FIELD-EFFECT TRANSISTOR

Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer. 1. A structure comprising:a gate structure having a sidewall;a sidewall spacer arranged adjacent to the sidewall of the gate structure, the sidewall spacer including a first section and a second section arranged over the first section, the first section of the sidewall spacer comprised of a first dielectric material, and the second section of the sidewall spacer comprised of a second dielectric material different from the first dielectric material; anda source/drain region including a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer, the second section of the source/drain region spaced by a gap from the second section of the sidewall spacer.2. The structure of wherein the first section of the sidewall spacer has a first thickness claim 1 , and the second section of the sidewall spacer has a second thickness that is substantially equal to the first thickness.3. The structure of wherein the first section of the sidewall spacer has a first height and the first thickness is substantially constant over the first height claim 2 , and the second section of the sidewall spacer has a second ...

Fabricating fin structures with doped middle portions

Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

Outdoor maintenance power supply box of transformer substation

The utility model discloses an outdoor maintenance power supply box of transformer substation, the power distribution box comprises a box body, inside bottom one side of box is equipped with the fixed battery that is equipped with, electric connection has pressure measurement resistance on the positive negative pole of battery one side, one side of pressure measurement resistance is equipped with the transformer, one side of transformer is equipped with the terminal box, the inside both sides top of box all is equipped with the fan, the top of box articulates there is the case lid, the fixed TI chip that is equipped with in bottom of case lid, the top of box is inlayed and is had the touch -sensitive screen, the top both sides of box are through the fixed braces that all is connected with, pressure measurement resistance, transformer, fan and touch -sensitive screen all with TI chip electric connection. The device simple structure, reasonable in design, convenient operation, portable, the ...

METHODS OF FORMING FIELD EFFECT TRANSISTOR (FET) AND NON-FET CIRCUIT ELEMENTS ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region. 1. A method of forming an integrated circuit product on an SOI substrate , said SOI substrate comprising an active semiconductor layer , a bulk semiconductor layer and an insulating material layer positioned between said active semiconductor layer and said bulk semiconductor layer , the method comprising:forming an isolation structure that extends into said bulk semiconductor layer so as to define first and second active regions on said SOI substrate;forming a field effect transistor above said first active region, said transistor comprising a source region and a drain region;forming an opening in said second active region that removes a portion of said active layer and a portion of said insulating material layer in said second active region, wherein said opening exposes an upper surface of said bulk semiconductor layer in said second active region; andperforming a common epitaxial growth process so as to form an epi semiconductor material region above each of said source region and said drain region of said transistor and to form a unitary epi semiconductor structure above said second active region, ...

Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

Method for creating metal gate resistor in FDSOL and resulting device

Fabricating FEOL metal gate resistor structures and the resulting device are disclosed. Embodiments include providing a Si layer-insulator layer-Si substrate stack; forming STI regions at first through fourth sides of a rectangular active-area of the Si layer, the first side opposing the third, the STI extending into the substrate; recessing the STI below the insulator upper surface; undercutting the active-area, forming channels in the insulator along and under perimeter edges of the active-area; conformally forming a high-k dielectric on all exposed surfaces; forming metal on the high-k dielectric and filling the channels; removing the metal except for the filled channels and a portion over each of the STI at the first and third sides and overlapping the active-area; and forming low-k spacers on exposed opposing sidewalls of the metal portions and exposed vertical surfaces of the high-k dielectric on edges of the active-area and the filled channels.

Methods of forming doped transition regions of transistor structures

Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region.

Source/Drain Contact Spacers and Methods of Forming Same

Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlevel dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature before forming the source/drain contact.

Low nickel austenitic stainless steel power and use thereof

The invention relates to low nickel austenitic stainless steel powder and an application thereof. The alloy composition relation in the powder is as follows: Cr:13-22%,Ni:0-6%,Mn:9-2.5%,Cu<2%,Nb,Ti,V<1%, with the rest being Fe and impurities brought in the melting process, wherein the total content of Ni and Mn in the alloy must be within the range of 7-12%. The powder is made into pre-powdered alloy by water atomization or gas atomization and in the irregular shape, the triangle shape, the branch shape, the near spherical shape and the spherical shape. The finished product is produced by general powder metallurgy forming methods, such as pressing, injection molding, loose sintering, etc. The invention provides the austenitic stainless steel powder materials with low cost and no magnetism for stainless steel sintered metal products.

Heating plate heating control method and system applied to nucleic acid detector

According to the heating plate heating control method and system applied to the nucleic acid detector, the first-stage processing thought identifies the first heating control element and selects the heating plate control task request by using the identified first heating control element; and only the selected initial heating plate control task request is input to the second-stage processing thought to identify the second heating control element, so that the overhead of pairing the heating plate control task request by using the second heating control element in the second-stage processing thought is remarkably saved, and the timeliness of the analysis of the heating plate control task request is ensured; after the heating plate control task requests are selected by using the first heating control element, the heating plate control task requests are paired by using the second heating control element, so that a heating control execution list for the to-be-processed heating plate control task ...

Epi facet height uniformity improvement for FDSOI technologies

A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD

Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts. 1. A semiconductor structure comprising:a semiconductor fin having a first top surface and first opposing sides;an isolation region in the semiconductor fin, the isolation region having a second top surface that is substantially co-planar with the first top surface of the semiconductor fin and further having second opposing sides;an isolation bump on the second top surface of the isolation region and having a third top surface;a bump sidewall spacer positioned laterally adjacent to the isolation bump and having at least an outer portion above and immediately adjacent to the first top surface of the semiconductor fin;a non-functional gate structure above and immediately adjacent to the third top surface of the isolation bump; a channel region within the semiconductor fin;', 'a functional gate structure adjacent to the first top surface and the first opposing sides of the semiconductor fin at the channel region; and', 'a source/drain region in the semiconductor fin between the channel region and the isolation region, the source/drain region having ...

Abnormity alarm method and system applied to nucleic acid detector

The embodiment of the invention provides an abnormity alarm method and system applied to a nucleic acid detector, and the method comprises the steps: obtaining an operation stability test log of a target nucleic acid detector, loading the operation stability test log into an abnormity decision model, obtaining classification probability values of the operation stability test log under a plurality of abnormity reason labels, and determining the abnormity of the target nucleic acid detector according to the classification probability values. And determining abnormal alarm output information corresponding to the operation stability test log based on the classification probability values of the operation stability test log under a plurality of abnormal reason labels and an alarm evaluation coefficient corresponding to each abnormal reason label, therefore, the abnormal alarm output information of the nucleic acid detector can be determined by combining the alarm evaluation coefficients of the ...

Field effect transistor structure with recessed interlayer dielectric and method

Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES

The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region. 1. A method comprising:forming first and second fins parallel to each other;forming at least one fin portion, connecting the first and second fins;forming a gate perpendicular to the first and second fins, over the at least one fin portion;forming a first source and a first drain over the first fin at opposite sides of the gate;forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate; and{'b': 1', '1', '2', '2, 'determining a resistance of the first and second source and first and second drain extension regions (Rex) utilizing two test modes, a first mode in which the on resistance (Ron) satisfies Ron=2 (Rex+Rch), and the second mode in which the on resistance (Ron) satisfies Ron=2 (Rex+Rch)+Rint, wherein Rch is the gate channel resistance, and Rint is the internal resistance along the fin portion,'}wherein each of the first and second sources and first and second drains includes an extension region, andwherein forming the at least one fin portion comprises forming a single fin portion perpendicular to the first and second fins.2. (canceled)3. (canceled)41122122. The method according to claim 1 , wherein for each of the test modes claim 1 , the gate voltage (Vg) equals the power ...

PREVENTING BRIDGE FORMATION BETWEEN REPLACEMENT GATE AND SOURCE/DRAIN REGION THROUGH STI STRUCTURE

A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure. 1. A method , comprising:forming at least one fin above a semiconductor substrate;forming an isolation structure adjacent said fin;forming a liner layer above said at least one fin and said isolation structure;forming a dielectric layer above said liner layer;recessing said dielectric layer to expose portions of said liner layer disposed on sidewalls of said at least one fin;removing said exposed portions of said liner layer disposed on said sidewalls of said at least one fin;removing remaining portions of said dielectric layer after removing said exposed portions of said liner layer, wherein a portion of said liner layer remains on an upper surface of said isolation structure adjacent an interface where said fin contacts said isolation structure after forming said isolation structure, said liner layer comprising a material different than said isolation structure;forming a sacrificial gate structure including a sacrificial gate insulation layer and a sacrificial gate structure above a portion of said fin;removing said sacrificial gate structure;removing said sacrificial gate insulation layer selectively to said liner layer; andforming a replacement gate structure in a cavity defined by removing said sacrificial gate structure.23.. (canceled)4. The ...

PRODUCT COMPRISED OF FINFET DEVICES WITH SINGLE DIFFUSION BREAK ISOLATION STRUCTURES

An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure. 1. An integrated circuit product , comprising:a plurality of trenches in a semiconducting substrate that define first, second and third fins in said substrate, wherein said first, second and third fins are positioned side-by-side, and wherein said second fin is positioned between said first and third fins;a layer of insulating material positioned in said plurality of trenches such that a desired height of said first, second and third fins is positioned above an upper surface of said layer of insulating material;a recess defined in said second fin structure that at least partially defines a cavity in said layer of insulating material;an SDB isolation structure positioned in said cavity on said recessed portion of said second fin, wherein said SDB isolation structure has an upper surface that is positioned at a level that is above a level of said upper surface of said layer of insulating material; anda gate structure for a transistor positioned above said SDB isolation structure.2. The product of claim 1 , wherein said SDB isolation structure and said layer of insulating material are both made of silicon dioxide.3. ...

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

COMPOSITE CONTACT ETCH STOP LAYER

A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer. 1. A method of fabricating a device , comprising:forming a sacrificial gate structure over a semiconductor substrate, wherein the sacrificial gate structure includes a sacrificial gate and a sacrificial gate cap formed over a top surface of the sacrificial gate;forming a sidewall spacer layer over sidewalls of the sacrificial gate structure;forming a first etch stop layer over the sidewall spacer layer laterally adjacent to the sacrificial gate; andforming a second etch stop layer over the first etch stop layer and the sacrificial gate cap, wherein the second etch stop layer is formed directly on the sacrificial gate cap without intervening layers.2. The method of claim 1 , wherein the first and second etch stop layers are formed by atomic layer deposition.3. The method of claim 1 , wherein the first etch stop layer comprises silicon dioxide and the second etch stop layer comprises silicon nitride.4. The method of claim 1 , wherein a top surface of the first etch stop layer is coplanar with the top surface of the sacrificial gate.5. The method of claim 1 , wherein the second etch stop layer is formed directly over the sidewall spacer layer laterally adjacent to the sacrificial gate cap.6. The method of claim 1 , wherein the second etch stop layer is formed directly over the first etch stop layer laterally adjacent to the sacrificial gate and directly over the sidewall spacer layer ...

Integrated circuit fabrication with boron etch-stop layer

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

Multi-Layer Fin Structure

The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin. 1. A semiconductor structure comprising:a semiconductor substrate;a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; anda gate stack disposed over the fin.2. The semiconductor structure of claim 1 , wherein the fin has a total height and wherein the first layer is 30-60% of the total height.3. The semiconductor structure of claim 2 , wherein the second layer is 40-70% of the total height.4. The semiconductor structure of claim 1 , wherein the second concentration is 10-30% germanium and wherein the first concentration is 3-5% greater than the second concentration.5. The semiconductor structure of claim 1 , further comprising a third layer over the second layer claim 1 , wherein the third layer includes silicon germanium having a third concentration of germanium greater than the second concentration of germanium.6. The semiconductor structure of claim 5 , wherein the fin has a total height and wherein the first layer is 25-35% of the total height.7. The semiconductor structure of claim 6 , wherein the second layer is 40-60% of the total height.8. The ...

Transistor Structure and Method With Strain Effect

The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack. 1. A method , comprising:forming a gate stack on a semiconductor substrate;forming an etch stop layer on the gate stack and the semiconductor substrate;depositing a dielectric liner layer on the etch stop layer;performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate;depositing a silicon layer selectively on exposed surfaces of the etch stop layer;depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; andperforming an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.2. The method of claim 1 , prior to the forming a gate stack claim 1 , further comprising forming a fin active region surrounded by isolation features.3. The method of claim 1 , after the performing an anneal claim 1 , further comprising replacing the gate stack with a metal gate that includes a gate dielectric layer of a high-k dielectric material and a gate electrode of a metal.4. The method of claim 1 , wherein the forming a gate stack includes depositing gate materials and patterning the ...

NANOSHEET TRANSISTOR WITH IMPROVED INNER SPACER

A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier. 1. A method of fabricating a device , comprising:forming a stack of alternating layers of epitaxial silicon germanium and epitaxial silicon over a semiconductor substrate, wherein a germanium content within lower and upper regions of each said layer of epitaxial silicon germanium is greater than a germanium content within an intermediate region between said lower and upper regions;forming a sacrificial gate structure over the stack, wherein the sacrificial gate structure has a length and a width less than the length;forming sidewall spacers over sidewalls of the sacrificial gate structure; andetching exposed portions of the stack using the sacrificial gate structure and the sidewall spacers as an etch mask to form a fin structure.2. The method of claim 1 , further comprising removing the epitaxial silicon germanium layers from under the sidewall spacers to form recessed regions.3. The method of claim 2 , further comprising forming dielectric inner spacers within the recessed regions.4. The method of claim 1 , further comprising removing portions of the epitaxial silicon germanium layers from under the sidewall spacers claim 1 , wherein a distribution of the germanium content within each of the silicon germanium layers causes remaining portions of the silicon germanium layers to have a substantially constant width.5. The method of claim 1 , wherein sidewalls of the stack after ...

METHODS, APPARATUS AND SYSTEM FOR FORMING SIGMA SHAPED SOURCE/DRAIN LATTICE

At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed. 1. A method , comprising:forming a fin on a semiconductor substrate;forming, over said fin, a gate region;forming, in a source region and a drain region adjacent bottom portions of said fin, a first recess cavity in said source region and a second recess cavity in said drain region, said first and second recess cavities comprising sidewalls formed in an angle relative to a vertical axis, wherein portions of said first and second recess cavities extend below said fin; andforming, in said first recess cavity, a first rare earth oxide layer and in said second recess cavity, a second rare earth oxide layer.2. The method of claim 1 , further comprising:forming a first epitaxial (EPI) feature above said first rare earth oxide layer and a second EPI feature above said second rare earth oxide layer;removing a portion of a substrate material in said source region for forming said first recess cavity; andremoving a portion of a substrate material in said drain region for forming said second recess cavity.3. The method of claim 2 , wherein:forming said first EPI feature comprises growing said an EPI structure from at least one of the surface of said first rare earth oxide layer, and a portion of the fin adjacent said source region; andforming said second EPI feature comprises growing ...

FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin. 1. A method comprising:forming a silicon (Si) fin;forming a hard mask on a top surface of the Si fin;forming an oxide layer on opposite sides of the Si fin;implanting a dopant into the Si fin;recessing the oxide layer to reveal an active Si fin; andmodifying sidewalls of the active Si fin by etching.2. The method according to claim 1 , comprising forming the Si fin by etching.3. The method according to claim 1 , comprising implanting a dopant into the Si fin with a vertical channel implant or a punch-through stop (PTS) vertical implant.4. The method according to claim 1 , comprising recessing the oxide layer 20 nanometer (nm) to 60 nm to reveal the active Si fin.5. The method according to claim 1 , comprising etching the sidewalls by plasma Si etching to increase a verticality of the sidewalls.6. The method according to claim 5 , comprising etching the sidewalls selectively to form multiple levels of sidewall verticality.7. The method according to claim 1 , comprising etching the sidewalls by plasma Si etching to taper each sidewall.8. The method according to claim 7 , comprising etching the sidewalls selectively with masking steps to form multiple levels of tapered sidewalls.9. The ...

Devices with Strained Isolation Features

A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer. 1. A device comprising:a first fin and a second fin disposed on a substrate;a first source/drain feature disposed on the first fin and extending to a first height over the substrate;a second source/drain feature disposed on the second fin;a first isolation layer disposed between the first source/drain feature and the second source/drain feature; anda second isolation layer disposed over the first isolation layer, andwherein a portion of the second isolation layer extends into a recess defined by the first isolation layer between the first and second source/drain features, wherein the portion of the second isolation layer further extends between the first and second source/drain features to a second height that is greater than the first height of the first source/drain feature.2. The device of claim 1 , wherein the second source/drain feature extends to the first height over the substrate.3. The device of claim 1 , wherein the first isolation layer includes:a first portion interfacing with a sidewall of the first fin;a second portion interfacing with a sidewall of the second fin; anda third portion disposed between the first and second portions and interfacing with the substrate, the third portion being at a lower level within the ...

SEMICONDUCTOR DEVICE WITH AIR SPACER AND STRESS LINER

Aspects of the disclosure provide a method for fabricating a semiconductor device. A pre-stress liner is formed over a structure. The structure includes a gate structure having sidewalls. A protection layer is formed. The protection layer covers a first portion of the pre-stress liner that extends along the sidewalls of the gate structure, and exposes a second portion of the pre-stress liner that is away from the sidewalls of the gate structure. An oxygen-containing layer is formed. The oxygen-containing layer covers the pre-stress liner and the protection layer. The oxygen-containing layer is separated from the first portion of the pre-stress liner by the protection layer. The structure is annealed such that the second portion of the pre-stress liner oxidizes by receiving oxygen from the oxygen-containing layer, while the first portion of the pre-stress liner remains unoxidized due to the protection layer. 1. A method for fabricating a semiconductor device , comprising:forming a pre-stress liner over a structure that includes a gate structure having sidewalls;forming a protection layer that selectively covers a first portion of the pre-stress liner that extends along the sidewalls of the gate structure, and exposes a second portion of the pre-stress liner that is away from the sidewalls;forming an oxygen-containing layer that covers the pre-stress liner and the protection layer, the oxygen-containing layer being separated from the first portion of the pre-stress liner by the protection layer; andannealing the structure such that the second portion of the pre-stress liner oxidizes by receiving oxygen from the oxygen-containing layer while the first portion of the pre-stress liner remains unoxidized due to the protection layer.2. The method of claim 1 , further comprising:forming an air gap between the protection layer and the sidewalls of the gate structure by removing the first portion of the pre-stress liner on the sidewalls of the gate structure.4. The method of ...

FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin. 1. A method comprising:forming a silicon (Si) fin, the Si fin having an active top portion and an active bottom portion;forming a hard mask on a top surface of the Si fin;forming an oxide layer on opposite sides of the Si fin;implanting a dopant into the Si fin;recessing the oxide layer to reveal the active top portion of the Si fin;etching the active top portion of the Si fin to form vertical sidewalls;forming a nitride spacer covering each vertical sidewall;recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; andtapering the active bottom portion of the Si fin.2. The method according to claim 1 , comprising forming the Si fin by etching.3. The method according to claim 1 , comprising implanting a dopant into the Si fin using a vertical channel implant or a punch-through stop (PTS) vertical implant.4. The method according to claim 1 , comprising forming the active top portion of the Si fin to a width of 7 nanometer (nm) to 15 nm.5. The method according to claim 1 , comprising recessing the oxide layer 25 nm to 60 nm to reveal the active top portion of the Si fin.6. The method according to claim 1 , comprising recessing the recessed oxide layer 10 nm ...

SPACER INTEGRATION SCHEME FOR NFET AND PFET DEVICES

The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension. 1. A structure , comprising:a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers; anda plurality epitaxial grown fin structures for PFET devices having sidewall spacers of a same dimension as the sidewall spacers for the NFET devices.2. The structure of claim 1 , wherein the plurality of epitaxial grown fin structures for the NFET devices and PFET devices are SiGe fin structures.3. The structure of claim 1 , wherein the sidewall spacers of the epitaxial grown fin structures for the NFET devices and PFET devices are SiN.4. The structure of claim 1 , further comprising an a-Si oxidated sidewall separating the epitaxial grown fin structures for the NFET devices and the epitaxial grown fin structures for the PFET devices5. The structure of claim 1 , wherein the dimension is about 1 nm to about 40 nm in thickness.620.-. (canceled) The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture.FinFETs provide superior levels of scalability and increased levels of integration within integrated circuits. The FinFET, for example, also provides improved electrical control over the channel conduction and reduced leakage current levels. Moreover, the FinFET can overcome some other short-channel effects. In addition, FinFETs can provide lower power consumption which allows high integration levels, operation at lower voltage as a result of their lower threshold voltage and, often, increase operating speeds compared to planar ...

FINS WITH SINGLE DIFFUSION BREAK FACET IMPROVEMENT USING EPITAXIAL INSULATOR

The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material. 1. A structure comprising:a plurality of fin structures;an insulator material filling a cut between adjacent fin structures of the plurality of fin structures, and filling a recess of the adjacent fin structures above the cut;a metal material at least partially lining vertical sidewalls of the cut below the recess, with the metal material embedded between the material of the adjacent fin structures and the insulator material within the cut and above the metal material within the recess; andan epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.2. The structure of claim 1 , wherein the metal material is a rare earth oxide claim 1 , embedded between material of the epitaxial source region or epitaxial drain region and the insulator material.3. The structure of claim 2 , wherein the insulator material is an oxide material and the material of the epitaxial source region or epitaxial drain region is semiconductor material that is grown in a cavity formed in the at least one of the plurality of fin structures.4. The structure of claim 3 , wherein the semiconductor material is SiGe claim 3 , which grows on the rare earth material.5. The structure of claim 1 , wherein the metal material is a rare earth material or SrTiO.6. The structure of claim 1 , wherein the metal material lines an upper portion of the cut. ...

TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF

Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure. 1. A method comprising: providing a cavity within the substrate; and', 'forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, wherein the first portion inhibits diffusion of material from the second portion into the substrate., 'fabricating a transistor structure at least partially within a substrate, the fabricating comprising2. The method of claim 1 , wherein the forming comprises using a single epitaxial growth step in forming the first portion and the second portion of the transistor structure.3. The method of claim 1 , wherein the forming comprises:providing the first portion with first impurities and the second portion with second impurities, wherein the first impurities of the first portion inhibit diffusion of the second impurities of the second portion into the substrate.4. The method of claim 3 , wherein the first impurities comprise one or more of carbon atoms or fluorine atoms.5. The method of claim 3 , wherein the second impurities comprise p- ...

METHOD OF IMPROVED CA/CB CONTACT AND DEVICE THEREOF

Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal. 1. A method comprising:providing a replacement metal gate (RMG) between first and second sidewall spacers, the RMG and the first and second sidewall spacers surrounded by an insulator on a substrate, wherein the RMG comprises a dielectric layer having an inner side and an outer side, and a metal layer and the outer side of the dielectric layer directly abuts the first and second sidewall spacers and the metal layer directly contacts the inner side of the dielectric layer;providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG;forming a source/drain contact hole through the oxide layer and the insulator, adjacent to, but not contacting, the first sidewall spacer, leaving a sliver portion of the insulator between the source/drain contact hole and the first sidewall spacer;forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal layer at an upper surface of the RMG, while concurrently removing the sliver portion of the insulator;enlarging the source/drain contact hole to the metal layer of the RMG by removing the first sidewall spacer and a ...

MEMORY CELL WITH ASYMMETRICAL TRANSISTOR, ASYMMETRICAL TRANSISTOR AND METHOD OF FORMING

An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell. 1. A memory cell , comprising:a capacitor; andan asymmetric transistor for controlling access to the capacitor, the asymmetric transistor including a device channel located between a source and a drain, the source operatively coupled to the capacitor, andwherein the source has a higher threshold voltage than the drain.2. The memory cell of claim 1 , wherein the asymmetric transistor includes: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop an entirety of the device channel,', 'a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and', 'a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer., 'at least one gate stack located atop the device channel and within an opening space of a surrounding spacer, the at least one gate stack including, from bottom to top3. The memory cell of claim 2 , wherein the ...

SELECTIVELY FORMING A PROTECTIVE CONDUCTIVE CAP ON A METAL GATE ELECTRODE

A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap. 1. A method , comprising:forming a replacement gate structure comprising an HK/MG material layer stack and a conductive metal gate electrode in a gate cavity, wherein said gate cavity is formed in a dielectric material formed above an active region of a semiconductor device, and wherein said HK/MG material layer stack is formed between said conductive metal gate electrode and sidewall and bottom surfaces of said gate cavity, said HK/MG material layer stack comprising a high-k dielectric material and a work function metal material formed above said high-k dielectric material;planarizing an upper surface of said conductive metal gate electrode, an upper surface of said HK/MG material layer stack, and an upper surface of said dielectric material during a common planarization process;selectively forming a protective conductive cap on and in direct physical contact with said planarized upper surface of said conductive metal gate electrode, wherein said protective conductive cap is substantially confined to said planarized upper surface of said conductive metal gate electrode and is not formed on and in direct physical contact with planarized upper surface portions of said high-k dielectric material or said work function metal material of said HK/MG material layer ...

SELECTIVE SHALLOW TRENCH ISOLATION (STI) FILL FOR STRESS ENGINEERING IN SEMICONDUCTOR STRUCTURES

The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region. 1. A structure comprising a single diffusion break (SDB) region comprising at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region , the stress fill material imparting a stress on a gate structure adjacent to the at least one STI region.2. The structure of claim 1 , wherein the stress fill material comprises a liner and a fill material within the recess of the at least one STI region.3. The structure of claim 1 , wherein the stress fill material comprises a single material within the recess of the at least one STI region.4. The structure of claim 1 , wherein the recess is approximately 20% to 60% of a depth of the at least one STI region.5. The structure of claim 1 , wherein the stress fill material exhibits one of a tensile stress on the gate structure and a compressive stress on the gate structure.6. The structure of claim 1 , wherein the stress fill material is an insulator material.7. The structure of claim 1 , wherein:the at least one STI region is two STI regions;a first of the STI regions is filled with a first stress material imparting a tensile stress; anda second of the STI regions is filled with a second stress material imparting a compressive stress.8. The structure of claim 1 , further comprising a double diffusion break (DDB) region comprising at least one STI region with a non-stress fill material.9. The structure of claim 1 , wherein the substrate is a fin structure and the ...

Increased surface area of epitaxial structures in a mixed n/p type fin semiconductor structure with multiple epitaxial heads

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

INTEGRATED CIRCUITS INCLUDING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure. 1. A method for fabricating an integrated circuit , the method comprising:forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate;forming additional sidewall spacer structures laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures; andreplacing the dummy gate structure with a replacement gate structure.2. The method of claim 1 , wherein the sidewall spacer structures each have an inner sidewall surface that is formed facing the dummy gate structure and an outer sidewall surface that is formed facing away from the dummy gate structure claim 1 , and wherein replacing the dummy gate structure comprises removing the dummy gate structure to form a recess that exposes the inner sidewall surfaces claim 1 , wherein forming the additional sidewall spacer structures comprises forming the additional sidewall spacer structures along and under the inner sidewall surfaces after forming the recess claim 1 , and wherein replacing the replacement gate structure further comprises forming the replacement gate structure in a remaining space of the recess adjacent to the additional sidewall spacer structures.3. The method of claim 2 , wherein the dummy gate structure is disposed between the sidewall spacer structures and an interlayer dielectric (ILD) layer overlying the semiconductor substrate claim 2 , and wherein removing the dummy gate structure comprises removing ...

GATE STRUCTURES WITH LOW RESISTANCE

The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nFET device formed in a first cavity having a first volume which is filled with conductive material; and a pFET device forming in a second cavity having a second volume greater than the first volume. The second volume being filled with the conductive material. 1. A structure , comprising:an nFET device formed in a first cavity having a first volume which is filled with conductive material; anda pFET device forming in a second cavity having a second volume greater than the first volume, the second volume being filled with the conductive material.2. The structure of claim 1 , wherein the conductive material is tungsten material for both the nFET device and the pFET device.3. The structure of claim 2 , wherein the conductive material of the pFET device has a lowered gate resistance compared to the nFET device.4. The structure of claim 3 , further comprising a dielectric layer lining the first cavity and the second cavity claim 3 , under the conductive material.5. The structure of claim 4 , further comprising an n-type workfunction material lining the first cavity claim 4 , underneath the conductive material in the first cavity.6. The structure of claim 5 , further comprising an n-type diffusion barrier layer located between the dielectric layer and the n-type workfunction material.7. The structure of claim 4 , further comprising a p-type workfunction material in the second cavity below the conductive material.8. The structure of claim 7 , wherein the p-type workfunction material is between the dielectric layer and the conductive material.9. The structure of claim 8 , wherein the dielectric layer is a high-k dielectric material.10. A structure claim 8 , comprising:an nFET device in a first cavity having an n-type diffusion barrier material, an n-type workfunction metal and a first volume of ...

EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES

A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers. 1. A method comprising:providing a gate structure on a silicon-on-insulator (SOI) layer;forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure, wherein the first pair of spacers have upper surfaces parallel to the SOI layer and side surfaces inclined from the upper surfaces, such that the side surfaces form an acute angle with the SOI layer and an obtuse angle with the upper surfaces of the first pair of spacers;forming a second pair of spacers on the upper surface of the first pair of spacers, but not on the side surface of the first pair of spacers, adjacent to and on the opposite sides of the gate structure, wherein upper surfaces and lower surfaces of the second pair of spacers are parallel to the upper surfaces of the first pair of spacers and the lower surfaces of the second pair of spacers coincide with the upper surfaces of the first pair of spacers; andforming a pair of faceted raised source/drain structures on the SOI layer, each of the pair of faceted raised source/drain structures faceted at the upper surface of the first pair of spacers, wherein portions of the pair of faceted raised source/drain structures coincide with the inclined side surfaces of the first pair of spacers,wherein ...

Semiconductor Device with Corner Isolation Protection and Methods of Forming the Same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure. 1. A method for fabricating an integrated circuit comprising:providing a semiconductor substrate including a shallow trench isolation structure disposed therein and a gate electrode structure overlying semiconductor material of the semiconductor substrate;forming a first sidewall spacer adjacent to the gate electrode structure, wherein a first surface of the shallow trench isolation structure is exposed and spaced from the first sidewall spacer by a region of the semiconductor material;masking the first surface of the shallow trench isolation structure with an isolation structure mask, wherein the region of the semiconductor material disposed between the first sidewall spacer and the shallow trench isolation structure is free from the isolation structure mask;etching a recess in the region of the semiconductor material disposed between the first sidewall spacer and the shallow trench isolation structure with the isolation structure mask in place; andepitaxially growing a semiconductor material within the recess after ...

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE

Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes. 1. A device comprising:a semiconductor layout comprising:parallel segments of adjacent metal and via layers; anda via connected to each of the metal segments in a layout area, wherein first and second level metal segments include a portion parallel to the corresponding metal segment but adjacent an edge remote from the other metal segment, and the corresponding via connects to the portion.2. The device according to claim 1 , wherein the portion for each of the adjacent metal segments comprises a widening of the corresponding metal segment in a direction remote from the other metal segment.3. The device according to claim 1 , wherein the portion for each of the adjacent metal segments comprises a staircase-like extension of the corresponding metal segment in a direction remote from the other metal segment.4. The device according to claim 1 , wherein the portion for each of the adjacent metal segments comprises a combination of a widening of the corresponding metal segment in a direction remote from the other metal segment and a staircase-like extension of the corresponding metal segment in a direction remote from the other metal segment.5. The device according to claim 1 , wherein the staircase-like extension comprises:diffused metal segments in a ...

METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED DEVICE

A method for eliminating line voids during RMG processing and the resulting device are provided. Embodiments include forming dummy gates over PFET and NFET regions of a substrate, each dummy gate having spacers at opposite sides, and an ILD filling spaces between spacers; removing dummy gate material from the gates, forming a cavity between each pair of spacers; forming a high-k dielectric layer over the ILD and spacers and in the cavities; forming a metal capping layer over the high-k dielectric layer; forming a first work function metal layer over the metal capping layer; removing the first work function metal layer from the PFET region; forming a second work function metal layer over the metal capping layer in the PFET region and over the first work function metal layer in the NFET region; and forming a metal layer over the second work function metal layer, filling the cavities. 1. A method comprising:forming dummy gates over p-channel field-effect transistor (PFET) and n-channel field-effect transistor (NFET) regions of a substrate, each dummy gate having spacers formed on opposite sides of the dummy gate, and an interlayer dielectric (ILD) over source/drain (S/D) regions formed in the substrate, filling spaces between the spacers;removing dummy gate material from the gates, forming a cavity between each pair of spacers;forming a high-k dielectric layer over the ILD and spacers and in the cavities;forming a metal capping layer over the high-k dielectric layer;forming a first work function metal layer over the metal capping layer, the first work function metal layer comprising aluminum-doped titanium carbide (TiAlC) for a n-type device;removing the first work function metal layer from the PFET region;forming a second work function metal layer over the metal capping layer in the PFET region and over the first work function metal layer in the NFET region; andforming a metal layer over the second work function metal layer, filling the cavities and forming ...

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain. 1. A method of making a vertical FinFET device comprising:forming a fin having a height (H) on a semiconductor substrate;forming a well region in the substrate, where a lower end of the fin is in contact with the well region;forming a bottom source/drain region in the substrate laterally adjacent to the well region and spaced away from the fin,forming a main gate stack over at least one sidewall of the fin, the main gate stack extending laterally over the well region and the bottom source/drain region on at least one side of the fin, wherein the main gate stack comprises a main gate dielectric and a main gate conductor formed over the main gate dielectric; andetching a portion of the main gate conductor over the bottom source/drain region to define a channel region between the main gate conductor and the fin and between the main gate conductor and the well region.2. The method of claim 1 , wherein the channel region comprises a horizontal component over the well region on the at least one side of the fin claim 1 , and a vertical component over the sidewall of the fin on the at least one side of the fin claim 1 , and a ...

SEMICONDUCTOR DEVICE HAVING CONTACT FEATURE AND METHOD OF FABRICATING THE SAME

A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide. 1. A method , comprising:providing a device including a gate structure and a source/drain feature adjacent to the gate structure;forming an insulating layer over the source/drain feature;etching a trench in the insulating layer to expose a surface of the source/drain feature;forming a semiconductor material in the etched trench on the surface of the source/drain feature; andconverting the semiconductor material to a silicide.2. The method of claim 1 , further comprising:forming a contact metal layer over the silicide filling the etched trench.3. The method of claim 1 , wherein the forming the semiconductor material includes forming silicon on the surface of the source/drain feature.4. The method of claim 3 , further comprising:epitaxially growing the source/drain feature prior to forming the dielectric layer.5. The method of claim 4 , wherein the epitaxially growing the source/drain feature includes epitaxially growing silicon germanium.6. The method of claim 1 , further comprising:forming a liner layer on sidewalls of the etched trench after forming the semiconductor material.7. The method of claim 6 , wherein the forming the liner layer is performed before converting the semiconductor material to the silicide.8. The method of claim 6 , further comprising:etching the formed liner layer, wherein the etching the formed liner layer removes a portion of the formed liner layer and removes a portion of the semiconductor material.9. The method of claim 1 , wherein the etching the trench in the insulating layer includes ...

SELF-ALIGNED JUNCTION STRUCTURES

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners. 1. A structure , comprising:a plurality of epitaxial grown fin structures for first type devices, the first type devices comprising a gate with associated source and drain regions;a plurality epitaxial grown fin structures for second type devices, the second type devices comprising a gate having sidewall liners and associated source and drain regions; anda liner material deposited on the plurality of epitaxial grown fin structures for first type devices and between oxide material over the plurality of epitaxial grown fin structures for the first type devices and second type devices, the liner material separating the epitaxial grown fin structures for nFET devices and the epitaxial grown fin structures for pFET devices.2. The structure of claim 1 , wherein the first type devices are nFET devices and the second type devices are pFET devices.3. The structure of claim 2 , wherein the plurality of epitaxial grown fin structures for the pFET devices are eSiGe fin structures.4. The structure of claim 2 , wherein the sidewall liners of the epitaxial grown fin structures for the pFET devices is low-k material.5. (canceled)6. The structure of claim 1 , wherein the epitaxial grown fin structures for the other of the nFET devices or pFET devices claim 1 , respectively claim 1 , are devoid of a liner or spacer material.7. A method claim 1 , comprising:forming a plurality of epitaxial grown fin structures on a first side of a substrate, while protecting fin structures on a second side of the substrate with amorphous material lined with a sidewall liner;removing portions of the fin structures on the second side of the substrate, while protecting the ...

FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD

Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions. 1. A method comprising:removing a sacrificial gate, the removing of the sacrificial gate creating a gate opening that extends vertically through an interlayer dielectric layer and is physically separated from the interlayer dielectric layer by a sidewall spacer;forming a replacement metal gate in the gate opening adjacent to a channel region;performing a polishing process so that top surfaces of the interlayer dielectric layer, the sidewall spacer and the replacement metal gate are approximately level;recessing the interlayer dielectric layer relative to the sidewall spacer and the replacement metal gate;conformally depositing a dielectric cap layer so as to cover exposed surfaces of the interlayer dielectric layer, the sidewall spacer and the replacement metal gate, the dielectric cap layer being conformally deposited so as to have an essentially uniform thickness and so that a top surface of a portion of the dielectric cap layer on the interlayer dielectric layer is below a level of a top surface of the replacement metal gate;forming an additional interlayer dielectric layer on the dielectric cap layer; andforming an ...

METHOD OF MULTI-WF FOR MULTI-VT AND THIN SIDEWALL DEPOSITION BY IMPLANTATION FOR GATE-LAST PLANAR CMOS AND FINFET TECHNOLOGY

A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting Nin the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the Nimplanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W. 1. A method comprising:forming a silicon (Si) fin;forming a n-type field effect transistor (nFET) replacement metal gate (RMG) trench and a p-type FET (pFET) RMG trench, each over and perpendicular to the Si fin, the nFET and pFET RMG trenches being laterally separated;forming a first titanium (Ti) layer in the nFET and pFET RMG trenches;{'sub': '2', 'implanting nitrogen gas (N) in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench selectively;'}{'sub': '2', 'annealing the Nimplanted first Ti layer to form a titanium nitride (TiN) layer at a bottom of the pFET RMG trench;'}stripping un-reacted Ti of the first Ti layer;forming a second Ti layer in the nFET and pFET RMG trenches;implanting aluminum (Al) or carbon (C) in the second Ti layer vertically at a 0° implant angle;annealing the Al or C implanted second Ti layer to form titanium aluminide (TiAl) or titanium carbide (TiC) at a bottom of the nFET and pFET RMG trenches, respectively; andfilling the nFET and pFET RMG trenches with Al or tungsten (W).2. The method according to claim 1 , wherein the Si fin has an active top portion claim 1 , the method further comprising etching a profile of the active top portion to modify the ...

METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET

A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided. 1. A method of making a semiconductor structure comprising:providing a plurality of fins on a semiconductor substrate;depositing a layer comprising silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate;depositing a photoresist layer on one or more but less than all of the plurality of fins;etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited;stripping the photoresist layer;depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; anddepositing a silicon nitride liner step on the plurality of fins.2. The method of wherein depositing a layer of pure boron comprises performing chemical-vapor deposition.3. The method of wherein the silicon dioxide comprises phosphocilicate glass.4. The method of wherein a thickness of the layer of pure boron is less than 1 nm.5. The method of further comprising:depositing a layer of sacrificial oxide on the silicon nitride liner;recessing a portion of the layer of sacrificial oxide to expose a tip of the plurality of fins wherein the portion is less than all;removing the silicon nitride liner from the tip ...

FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD

Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions. 1. A field effect transistor comprising:source/drain regions and a channel region positioned laterally between the source/drain regions;a gate adjacent to the channel region;a sidewall spacer positioned laterally adjacent to a sidewall of the gate;an interlayer dielectric layer positioned laterally adjacent to the sidewall spacer, the interlayer dielectric layer having a top surface that is at a lower level than top surfaces of the gate and the sidewall spacer; anda dielectric cap layer on the interlayer dielectric layer, the sidewall spacer and gate, the dielectric cap layer having a portion above the top surface of the interlayer dielectric layer and positioned laterally immediately adjacent to a vertical surface of the sidewall spacer.2. The field effect transistor of claim 1 , the gate comprising a replacement metal gate and the field effect transistor further comprising:an additional interlayer dielectric layer on the dielectric cap layer; andcontacts that extend vertically through the additional interlayer dielectric layer, the dielectric cap layer and the interlayer dielectric layer to source/drain regions.3. ...

Middle of the line (mol) contact formation method and structure

Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

METHODS OF FORMING UPPER SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure. 1. A method of forming a vertical transistor device , the method comprising:forming a plurality of vertically oriented channel semiconductor structures above a substrate;forming a bottom source/drain (S/D) region proximate a lower portion of said vertically oriented channel semiconductor structure;forming a first dielectric layer above said vertically oriented channel semiconductor structure;reducing a thickness of said first dielectric layer to expose an upper portion of said vertically oriented channel semiconductor structure;forming a first semiconductor material region on said exposed upper portion;further reducing said thickness of said first dielectric layer after forming said first semiconductor material region to expose a channel portion of said vertically oriented channel semiconductor structure and to define a bottom spacer adjacent said bottom S/D region;forming a gate structure comprising a gate insulation layer around said channel portion of said vertically oriented ...

METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET

A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided. 1. A partial semiconductor structure comprising:a first plurality of fins comprising a first plurality of sidewalls;a layer of pure boron on one or more sidewalls of the first plurality of sidewalls;a silicon nitride liner on the layer of pure boron; anda layer of oxide between two or more fins of first plurality of fins.2. The partial semiconductor structure of wherein a thickness of the layer of pure boron is less than 1 nm.3. The partial semiconductor structure of wherein a tip of one or more fin of the first plurality of fins is exposed above a top of the layer of oxide.4. The partial semiconductor structure of wherein the tip of one or more fin of the first plurality of fins is not covered by the layer of pure boron.5. The partial semiconductor structure of wherein a thickness of the layer of pure boron is less than 1 nm.6. The partial semiconductor substrate of further comprising:a second plurality of fins comprising a second plurality of sidewalls;a layer of phosphosilicate glass on one or more sidewalls of the second plurality of sidewalls;a silicon nitride liner on the layer of phosphosilicate glass; anda layer of oxide between two or more fins of the second plurality of fins.7. The partial ...

INTRODUCING MATERIAL WITH A LOWER ETCH RATE TO FORM A T-SHAPED SDB STI STRUCTURE

A method of introducing SDB material with a lower etch rate during a formation of a t-shape SDB STI structure are provided. Embodiments include providing an STI region in a Si substrate; forming a hardmask over the STI region and the Si substrate; forming a cavity through the hardmask over the STI region, the cavity having a width greater than a width of the STI region; depositing a SDB material in the cavity with an etch rate lower than HDP oxide to form a t-shaped SDB STI structure; and removing the hardmask. 1. The method comprising:providing a shallow trench isolation (STI) region in a silicon (Si) substrate;forming a hardmask over the STI region and the Si substrate;forming a cavity through the hardmask over the STI region, the cavity having a width greater than a width of the STI region;depositing a single diffusion break (SDB) oxide material in the cavity with an etch rate lower than HDP oxide to form a t-shape SDB STI structure; andremoving the hardmask.2. The method according to claim 1 , comprising forming the SDB material of silicon dioxide (SiO) modified with nitrogen (N).3. The method according to claim 2 , wherein the SDB material has an etch rate ratio between etch rates of pure oxide and silicon nitride (SiN).4. The method according to claim 2 , comprising modifying the SiOis with 10 to 40% of N.5. The method according to claim 1 , comprising forming the SDB material of silicon dioxide (SiO) modified with carbon (C).6. The method according to claim 5 , wherein the SDB material has an etch rate ratio between etch rates of pure oxide and silicon carbide (SiC).7. The method according to claim 5 , comprising modifying the SiOwith 1 to 15% of C.8. The method according to claim 1 , comprising forming the SDB material of pure nitride.9. The method according to claim 1 , further comprising:providing trenches filled with STI material in the Si substrate perpendicular to the STI region;recessing the STI material to form Si FINs subsequent to removing the ...

Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

DIFFERENT HEIGHT OF FINS IN SEMICONDUCTOR STRUCTURE

There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height. 2. The semiconductor structure of claim 1 , wherein the first fin height is defined as a spacing between a top of the fins of the first region and a top of the oxide layer of the first region.3. The semiconductor structure of claim 1 , wherein the first region and the second region have an opposite polarity.4. The semiconductor structure of claim 1 , wherein the first region and the second region have an opposite polarity claim 1 , wherein the first region is a pFET region and wherein the first fin height is taller than the second fin height so that a device variability between the first region and the second region has a closer correspondence than a device variability in the case the first region and the second region have common fin heights.5. The semiconductor structure of claim 1 , wherein fins of the first region and fins of the second region have common top elevations.6. The semiconductor structure of claim 1 , wherein the oxide layer within the first region and the oxide layer within the second region have common top elevations.7. The semiconductor structure of claim 1 , wherein the first region and the second region have a common polarity claim 1 , wherein the first fin height is taller than the second fin height so that the first region has a smaller threshold voltage than the second region.8. A method for fabrication of a semiconductor structure comprising:providing fins of a first region to include a first fin height;providing fins of a second region to include a second fin height different than the first fin height; andwherein the first region and the second region have an opposite polarity.9. The method of claim 8 , wherein the first fin height is defined as a spacing between a top of the fins of the first region and a top of ...

FINFET DEVICES HAVING ASYMMETRICAL EPITAXIALLY-GROWN SOURCE AND DRAIN REGIONS AND METHODS OF FORMING THE SAME

Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins. 1. A fin field-effect transistor device comprising:a semiconductor substrate having a plurality of fins disposed in parallel relationship;a first insulator layer overlying the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions;a gate electrode structure overlying the exposed fin portions and electrically insulated from the fins by a gate insulating layer; andepitaxially-grown source regions and drain regions disposed adjacent to the gate electrode structure;wherein the epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.2. The fin field-effect transistor device of claim 1 , wherein the epitaxially-grown source regions and drain regions protrude less on a first side of the fins than on a second side of the fins along the lateral direction perpendicular to the length of the fins.3. The fin field-effect transistor device of claim 1 , wherein a first sidewall spacer is disposed adjacent to a first side of the fins and directly over the first insulator layer.4. The fin field-effect transistor device of claim 3 , wherein a ...

MIXED N/P TYPE NON-PLANAR SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS AND METHOD OF MAKING SAME

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape. 1. A method , comprising:providing a semiconductor structure, the structure comprising a semiconductor substrate, at least one first raised semiconductor structure of a first type coupled to the substrate, and at least one second raised semiconductor structure of a second type coupled to the substrate;growing at least one first epitaxial structure on a first top surface of one or more of the at least one first raised structure, wherein the at least one first epitaxial structure comprises at least one first epitaxial material;growing at least one second epitaxial structure on a second top surface of one or more of the at least one second raised structure, wherein the at least one second epitaxial structure comprises at least one second epitaxial material;increasing a first surface area of the at least one first epitaxial structure without growing additional at least one first epitaxial material; andincreasing a second surface area of the at least one second epitaxial structure without growing additional at least one second epitaxial material.2. The method of claim 1 , wherein increasing the first surface area and the second surface area comprises:modifying the at least one first epitaxial structure to create at least two first epitaxial head structures; andmodifying the at least one second epitaxial structure to create at least two second epitaxial head structures.3. The method ...

MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME

A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. 1. A method , comprising:providing a starting non-planar semiconductor structure, the structure comprising a semiconductor substrate and at least one raised semiconductor structure coupled to the substrate;growing at least one epitaxial structure on a top surface of one or more of the at least one raised semiconductor structure, wherein the at least one epitaxial structure has a surface area; andincreasing the surface area of the at least one epitaxial structure without growing additional epitaxy.2. The method of claim 1 , wherein the semiconductor structure further comprises a filler layer of at least one filler material conformally surrounding the at least one raised semiconductor structure while exposing the top surface claim 1 , and wherein the growing comprises: recessing the exposed top surface below a top surface of the filler layer; and growing the at least one epitaxial structure on the recessed top surface of the at least one raised semiconductor structure.3. The method of claim 2 , wherein the at least one raised structure comprises at least one first raised structure and at least one second raised structure claim 2 , wherein the growing and the increasing are performed only on the at least one first raised ...

Method to make gate-to-body contact to release plasma induced charging

Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area.

SEMICONDUCTOR STRUCTURE HAVING LOGIC REGION AND ANALOG REGION

A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces. 1. A method of fabricating a semiconductor structure , the method comprising:growing epitaxial growth material to form an epitaxial growth formation that defines an active logic device within a logic region of a semiconductor structure;performing, simultaneously with the growing, epitaxial growth to form an epitaxial growth formation that defines an analog device within an analog region of the semiconductor structure.2. The method of claim 1 , wherein the active logic device is provided by a MOSFET.3. The method of claim 1 , wherein the analog device is provided by a bipolar device selected from the group consisting of a pn junction claim 1 , an np junction of a bipolar junction transistor (BJT).4. The method of claim 1 , wherein the logic device is a transistor that has a channel defined by a thin silicon layer of a silicon on insulator (SOI) structure.5. The method of claim 1 , wherein the analog device is a bipolar device that has an electrode defined by a substrate of a silicon on insulator (SOI) structure.6. The method of claim 1 , wherein the performing is provided using opposing surfaces as seed surfaces.7. The method of claim 1 , wherein the epitaxial growth formation within a logic region defines a source-drain of an active MOSFET claim 1 , and wherein the epitaxial growth formation within an analog region defines an electrode of an analog device.8. The method of claim 1 , wherein the performing is provided using a top and bottom ...

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE

Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes. 1. A method comprising:comparing design data of an integrated circuit (IC) device against criteria of manufacturing processes to manufacture the IC device;identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area;performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is extended; andintegrating the partial re-routing into the design data for use in the manufacturing processes.2. The method according to claim 1 , wherein the partial re-routing comprises:forming a staircase-like extension on a portion of each of the metal segments in the layout area.3. The method according to claim 1 , wherein the partial re-routing comprises:a widening of a portion of each of the metal segments in the layout area.4. The method according to claim 1 , wherein the partial re-routing comprises:a combination of forming a staircase-like extension on a portion of each of the metal segments in the critical area and a widening of a portion of each of the metal segments in the layout area.5. The method according to claim 2 , wherein the staircase-like extension comprises:diffusing the metal ...

T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE

A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES

A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

Finfet fabrication method

Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE

Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. 1. A method comprising:forming an independent-gate fin field-effect transistor (FinFET) above a substrate; andforming stress within the fin between two independent gates of the independent-gate FinFET.2. The method according to claim 1 , wherein the fin includes a fin channel between the two independent gates claim 1 , and the stress is formed within the fin channel.3. The method according to claim 2 , wherein forming the stress comprises:implanting a dopant at an oblique angle to the fin channel;forming a strain memorization technique (SMT) capping layer over the independent-gate FinFET;annealing the SMT capping layer and the independent-gate FinFET; andremoving the SMT capping layer.4. The method according to claim 3 , comprising:implanting the dopant at the oblique angle to the fin channel to implant the dopant at a greater concentration on one side of the fin channel than another side of the fin channel.5. The method according to claim 4 , wherein the two independent gates comprise a main nFET gate and a body voltage control nFET gate claim 4 , and the one side of the fin channel corresponds to the nFET main gate and the another side of the fin channel corresponds to the body control voltage nFET gate.6. The method according to claim 5 , wherein the stress relative to the main nFET gate is tensile stress.7. The method according to claim 4 , wherein the two independent gates comprise a main pFET gate and a body voltage control pFET gate claim 4 , and the one side of the fin channel corresponds to the body control voltage pFET gate and the another side of the fin channel corresponds to the pFET main gate.8. The method according to claim 7 , ...

INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer. 1. A method of forming an integrated circuit (IC) structure , the method comprising:growing a conductive epitaxial layer on an upper surface of a semiconductor element;forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer;forming an insulator on the boron etch-stop layer;forming an opening within the insulator to expose an upper surface of the boron etch-stop layer;annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer and semiconductor materials from the conductive epitaxial layer into the boron etch-stop layer, such that the boron etch-stop layer and a portion of the conductive epitaxial layer become a boron-rich region; andforming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.2. The method of claim 1 , further comprising forming a silicide region within the boron-rich region after the annealing.3. The method of claim 1 , wherein the semiconductor ...

METHODS FOR PERFORMING A GATE CUT LAST SCHEME FOR FINFET SEMICONDUCTOR DEVICES

A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity. 1. A method , comprising:forming a placeholder gate structure embedded in a dielectric layer, said placeholder gate structure including a sacrificial material;forming a first hard mask layer above said dielectric layer, said first hard mask layer and said sacrificial material comprising a same material;forming a second hard mask layer above said first hard mask layer;patterning said second hard mask layer to define an opening therein exposing a portion of said first hard mask layer and being disposed above a portion of said placeholder gate structure;removing said exposed portion of said first hard mask layer and a portion of said sacrificial material of said placeholder gate structure disposed below said opening to define a gate cut cavity and divide said placeholder gate structure into first and second segments; andforming a dielectric material in said gate cut cavity.2. The method of claim 1 , further comprising:removing said second hard mask layer;removing remaining portions of said first hard mask layer and remaining portions of said sacrificial material of said placeholder gate structure to define a gate ...

INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via. 1. A method for fabricating an integrated circuit , the method comprising:depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer;forming a patterned hard mask overlying the OILD layer to form a first target metal line trench pattern and a second target metal line trench pattern;forming a patterned mask overlying the hard mask and the second target metal line trench pattern to form a target via-hole pattern in the first target metal line trench pattern;forming a via-hole extending through the target via-hole pattern and in the OILD layer;removing the patterned mask overlying the second target metal line trench pattern;forming a metal line trench extending through the second target metal line trench pattern and in the OILD layer;depositing a conductive metal fill in the via-hole for forming a via and in the metal line trench for forming a metal line; andplanarizing the conductive metal fill to expose an upper surface portion of the OILD layer.2. The method of claim 1 , wherein depositing the organic dielectric material comprises forming the OILD layer having a dielectric constant of from about 1.9 to about 4.3. The method of claim 1 , wherein depositing the organic dielectric material comprises depositing the organic dielectric material selected from the group consisting of polyimides claim 1 , polyamides claim 1 , polyesters claim 1 , aromatic polymers claim 1 , polyarylene-ether claim 1 , fluorine doped polyarylene-ether claim 1 , fluorine doped amorphous carbon claim 1 ...

A METHOD OF MANUFACTURING FINFET DEVICES USING NARROW AND WIDE GATE CUT OPENINGS IN CONJUCTION WITH A REPLACEMENT METAL GATE PROCESS

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates. 1. A method of forming a semiconductor structure , comprising:forming a plurality of semiconductor fins over a semiconductor substrate;forming a sacrificial gate layer over the fins;etching the sacrificial gate layer to form a sacrificial gate and a narrow gate cut opening extending through a portion of the sacrificial gate between adjacent fins;forming a first spacer layer over sidewalls of the sacrificial gate;forming a second spacer layer over sidewalls of the first spacer layer;etching the sacrificial gate to form a wide gate opening extending through the sacrificial gate between adjacent fins; andforming a dielectric fill layer within the wide gate cut opening.2. The method of claim 1 , wherein the sacrificial gate and the narrow gate cut opening are formed simultaneously.3. The method of claim 1 , wherein the first spacer layer partially fills the narrow gate cut opening.4. The method of claim 1 , wherein the first spacer layer and the second spacer layer entirely fill the narrow gate cut opening.5. The method of claim 1 , wherein the first spacer layer comprises silicon nitride and the second spacer layer comprises a low-k dielectric.6. The method of claim 1 , wherein the dielectric fill layer comprises silicon nitride.7. The method of claim 1 , wherein the first spacer layer defines a pair of opposing sidewalls of ...

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK

A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming spacer elements over sidewalls of the dummy gate stack and partially removing the dummy gate electrode to form a recess. The method further includes partially removing the spacer elements to enlarge the recess and removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer elements after the remaining portion of the dummy gate electrode is removed and removing the dummy gate dielectric layer. The method further includes forming a metal gate stack in the recess. 1. A method for forming a semiconductor device structure , comprising:forming a dummy gate stack over a semiconductor substrate, wherein the dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer;forming spacer elements over sidewalls of the dummy gate stack;partially removing the dummy gate electrode to form a recess;partially removing the spacer elements to enlarge the recess;removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer;doping the spacer elements after the remaining portion of the dummy gate electrode is removed;removing the dummy gate dielectric layer; andforming a metal gate stack in the recess.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein doping the spacer elements comprises ion-implanting the spacer elements with a halide-containing dopant.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the spacer elements are doped with fluorine.4. The method for forming a semiconductor device structure as claimed in claim 1 , wherein an upper portion of the spacer elements is partially removed while ...

DEVICE FOR IMPROVING PERFORMANCE THROUGH GATE CUT LAST PROCESS

Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method. 1. A device comprising:an intermediate semiconductor interconnect device having a substrate including a plurality of fins, and an STI layer;a high k material on a top surface of the STI layer, surrounding the fins;a gate stack over the high k material;a gate contact metal over the gate stack; andan inter-layer dielectric in a portion of the device, wherein the inter-layer dielectric directly contacts the gate contact metal.2. The device of claim 1 , wherein the gate stack comprises a metal gate stack.3. The device of claim 2 , wherein the metal gate stack comprises TiN.4. The device of claim 1 , wherein the high k material comprises TiAl.5. The device of claim 1 , wherein the inter-layer dielectric directly contacts the metal gate stack claim 1 , the high k material claim 1 , and the STI layer.6. The device of claim 5 , wherein a bottom surface of the inter-layer dielectric is bonded to the STI layer claim 5 , a first portion of a side of the inter-layer dielectric directly above the bottom surface interfaces with the high k material claim 5 , a second portion of the side of the inter-layer dielectric claim 5 , directly above the first portion ...

MULTI-PHASE SOURCE/DRAIN/GATE SPACER-EPI FORMATION

Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer. 1. A method for forming a device , the method comprising:forming a first portion of an epitaxial source/drain in a source/drain region on a fin in a finned substrate;forming, subsequent to the forming of the first portion of the source/drain, a secondary spacer in the source/drain region; andforming a remainder portion of the source/drain in the source/drain region, wherein the secondary spacer separates the source/drain from a gate stack region on the fin.2. The method according to claim 1 , further comprising forming a set of fins from the substrate to form the finned substrate.3. The method according to claim 1 , further comprising:forming, prior to the forming of the first portion of the source/drain, a first gate stack region and a second gate stack region on the finned substrate.4. The method according to claim 3 , the forming of the first and second gate stack regions further comprising:forming a dummy gate on the finned substrate in each of the first gate stack region and the second gate stack region; andforming a primary spacer on a vertical surface of each dummy gate,wherein the source/drain region is between the first gate stack region and the second gate stack region, andwherein the secondary spacer is formed over the primary spacer on the vertical surface of each dummy gate.5. The method according to claim 4 , wherein the secondary spacer restricts a growth of the source/drain in a direction of an adjacent source/drain.6. The method ...

METHODS FOR CROSSED-FINS FINFET DEVICE FOR SENSING AND MEASURING MAGNETIC FIELDS

Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity. 1. A method comprising:forming first-fins, parallel to and spaced from each other, in a first direction on a substrate;forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first-fins and in a second direction perpendicular to and crossing the first-fins;forming a dummy gate with a spacer on each side over channel areas of the first and second fins;forming source/drain (S/D) regions at opposite ends of each first and second fin;forming an interlayer dielectric (ILD) over the fins and the dummy gate and planarizing to reveal the dummy gate;removing the dummy gate, forming a cavity;forming a high-k/metal gate in the cavity;forming contacts through the ILD over the S/D regions; andbiasing the high-k/metal gate to an inversion state,wherein the S/D regions of the second and first-fins are in an electrical floating state.2. The method according to claim 1 , comprising forming the first and second fins by:forming first-fin-spacers, parallel to and spaced from each other, on the substrate;forming second-fin-spacers, parallel to and spaced from each other on the substrate, perpendicular to and crossing the first-fin-spacers; ...

METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING NOTCH WITHIN FIN FILLED WITH RARE EARTH OXIDE AND RELATED STRUCTURE

The disclosure is directed to methods of forming an integrated circuit structure and a related structure. One method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin. 1. A method of forming an integrated circuit structure , the method comprising:forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin;forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region;forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; andforming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.2. The method of claim 1 , further comprising:after the forming of the gate structure and prior to the forming of the notch, vertically etching the fin to remove a portion of the fin adjacent to the channel region such that the channel region remains disposed beneath the gate structure.3. The method of claim 2 , further comprising:after the vertically etching of the fin and prior to the forming of the notch, forming a sacrificial spacer over the fin and adjacent to the gate structure,wherein the forming of the notch includes laterally etching the fin on the opposing sides of the channel region and beneath the sacrificial spacer.4. The method of ...

IC PRODUCT COMPRISING A NOVEL INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES

One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction. 1. An integrated circuit product , comprising:a first final gate structure having a first end surface;a second final gate structure having a second end surface; andan insulating gate separation structure positioned between said first and second final gate structures, said insulating gate separation structure comprising first and second side surfaces that are opposite one another, wherein said first end surface contacts said first side surface of said insulating gate separation structure and said second end surface contacts said second side surface of said insulating gate separation structure, and wherein said insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.2. The integrated circuit product of claim 1 , wherein said insulating gate separation structure comprises silicon nitride and said first final gate structure comprises a high-k replacement gate insulation layer and a gate electrode that comprises at least one metal-containing layer of material.3. The integrated circuit product of claim 1 , wherein a bottom portion of said insulating gate separation structure is outwardly flared.4. The integrated circuit product of claim 1 , wherein a bottom portion of said insulating gate separation structure has a ...

Devices with Strained Isolation Features

A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer. 1. A semiconductor device , comprising:a first fin including a first source/drain region;a second fin including a second source/drain region;a first isolation layer disposed between the first source/drain region and the second source/drain region;a second isolation layer disposed over the first isolation layer; andan etch stop layer disposed between and interfacing with the first isolation layer and the second isolation layer such that the first isolation layer is prevented from interfacing with second isolation by the etch stop layer,wherein a first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region,wherein a portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.2. (canceled)3. The semiconductor device of claim 1 , further comprising a spacer claim 1 ,wherein a first portion of the spacer is disposed over the first portion of the first isolation layer and a second portion of the spacer is disposed over the second portion of the first isolation layer.4. The semiconductor device of claim 3 , wherein the etch stop ...

Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof

Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide. 1. A device comprising: a metal contact,', 'a contact isolation layer surrounding sidewalls of the metal contact,', 'an air gap surrounding sidewalls of the metal contact, wherein the air gap is disposed between the contact isolation layer and the insulating layer, and', 'an air gap seal having a first portion disposed over a second portion, wherein the first portion is disposed over a top surface of the contact isolation layer and is not disposed on a top surface of the insulating layer, the second portion surrounds a top portion of sidewalls of the metal contact, and the second portion is disposed between the contact isolation layer and the insulating layer., 'an interconnect disposed in an insulating layer, the interconnect having2. The device of claim 1 , wherein the air gap seal includes amorphous silicon.3. The device of claim 2 , wherein the contact isolation layer includes silicon and nitrogen and the insulating layer includes silicon and oxygen.4. The device of claim 2 , wherein the air gap seal includes amorphous silicon portions and silicon ...

STRESS-INDUCING SILICON LINER IN SEMICONDUCTOR DEVICES

A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

Devices with strained isolation features

A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Methods of forming upper source/drain regions on a vertical transistor device

A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

Low-K dielectric spacer for a gate cut

Structures including one or more field-effect transistors and methods for forming a structure that includes one or more field-effect transistors. A first semiconductor fin and a second semiconductor fin are formed in which the second semiconductor fin is spaced from the first semiconductor fin. A semiconductor layer is formed that covers the first semiconductor fin and the second semiconductor fin. An opening is formed in the semiconductor layer that exposes the first semiconductor fin. A dielectric spacer is formed on at least one sidewall of the semiconductor layer bordering the opening.

Method and structure to provide integrated long channel vertical FinFET device

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

Epitaxial region for embedded source/drain region having uniform thickness

A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Method and structure to provide integrated long channel vertical FinFet device

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

Transistor structure and method with strain effect

The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.

Semiconductor device having contact feature and method of fabricating the same

A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Method of forming super steep retrograde wells on FinFET

A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

Method for increasing a surface area of epitaxial structures in a mixed N/P type fin semiconductor structure by forming multiple epitaxial heads

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.