Memory access device including multiple processors

Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device.

MEMORY ACCESS DEVICE INCLUDING MULTIPLE PROCESSORS

Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device. Accordingly, the memory access device enables multiple processors, which are to simultaneously access a specific memory, to perform other operations during the standby time taken to access the specific memory.

OBSTACLE DETECTING SYSTEM AND METHOD

The obstacle detecting system includes a first image acquiring unit which acquires first image information by selectively receiving a laser beam emitted from at least one laser source toward a road surface at a target distance; a second image acquiring unit which acquires an image of actual surroundings as second image information; an image recognizing unit which recognizes an image of an obstacle by performing 3-D image recognition signal processing on line information of the laser beam using the first image information, and recognizes a pattern of the obstacle by performing pattern recognition signal processing on the second image information; and a risk determining unit which determines a possibility of collision due to presence of the obstacle within the target distance by classifying the recognized obstacles according to whether or not the image-recognized obstacle is matched with the pattern-recognized obstacle.

IMAGE MATCHING DEVICES AND IMAGE MATCHING METHODS THEREOF

Provided is an image matching method of matching at least two images. The image matching method extracts feature points of a reference image and feature points of a target image, changes a feature point, selected from among the feature points of the reference image, to a reference point in the target image, sets a matching candidate region on the basis of the reference point, in the target image, and performs a similarity operation between the selected feature point in the reference image and a plurality of feature points included in the matching candidate region among the feature points of the target image. The image matching method decreases the number of similarity operations performed in the image matching operation, thereby guaranteeing a high-speed operation.

FEATURE VECTOR CLASSIFICATION DEVICE AND METHOD THEREOF

Disclosed is a feature vector classification device which includes an initial condition setting unit; a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit; a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; and a hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit. 1. A feature vector classification device comprising:an initial condition setting unit;a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit;a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; anda hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit.2. The feature vector classification device of claim 1 , wherein an error calculated by the variable calculating unit is a normalized mean square error.3. The feature vector classification device of claim 1 , wherein the variable calculating unit expands and calculates the training vector.4. A feature vector classification method comprising:setting an initial condition;receiving a training vector;selecting features of the training vector one by one to calculate an error and a weight;determining an error, satisfying a specific condition, from among the calculated errors; andcomparing the specific error value with an error threshold to judge whether or not to generate a hyperplane.5. The feature vector classification method of claim 4 , wherein the initial condition includes the error threshold and a minimum feature number of the training vector.6. The feature vector classification ...

Multi-gate MOS transistor and method of manufacturing the same

Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.

SIMD parallel processor with SIMD/SISD/row/column operation modes

Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.

Structures of high voltage device and low voltage device, and method of manufacturing the same

The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

High voltage mosfet having Si/SiGe heterojunction structure and method of manufacturing the same

Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

IMAGE RECOGNIZING METHOD AND IMAGE RECOGNIZING DEVICE

Provided is an image recognizing method. The image recognizing method includes selecting a partial data from a standard image data, recognizing image based on the selected data, reduction-converting the selected data, and recognizing image based on the reduction-converted data. 1. A method for recognizing an image , comprising:selecting a partial data from a standard image data;recognizing image based on the selected data;reduction-converting the selected data; andrecognizing image based on the reduction-converted data.2. The method of claim 2 , further comprising:reselecting a partial data from the selected data and unselected data from the standard image data;recognizing image based on the reselected data;reduction-converting the reselected data; andrecognizing image based on the reduction-converted data of the reselected data.3. An image recognizing device claim 2 , comprising:an image acquirer;a standard image memory configured to store a partial data of a standard image data acquired by the image acquirer;a first reducer configured to reduction-convert the data stored in the standard image memory;a reduced image memory configured to store an output data of the first reducer;a search window setter configured to set a search window based on the data stored in the standard image memory and the data stored in the reduced image memory; andan image recognition processor configured to recognize image based on the search window set by the search window setter.4. The image recognizing device of claim 3 , wherein the search window setter is configured to set the search window based on the data stored in the reduced image memory after the recognizing image based on the data stored in the standard image memory is finished.5. The image recognizing device of claim 3 , wherein the standard image memory comprises a storage capacity corresponding to a horizontal resolution of the search window and a vertical resolution of the image acquirer.6. The image recognizing device of ...

Arithmetic method and device of reconfigurable processor

Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

Sources driver circuit for active matrix electroluminescent display and driving method thereof

Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.

Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation

Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

Multiple-gate MOS transistor and a method of manufacturing the same

Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability ...

Hall sensor signal generating device

Disclosed is a hall sensor signal generating device which includes a rotor which has a magnetic property and rotates on the basis of a rotary axis; a hall sensor unit which is disposed to be spaced apart from a stator disposed outside the rotor; and a clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal.

VEHICLE SAFETY SENSOR CONTROL DEVICE

A vehicle safety sensor control device is provided. The vehicle safety sensor control device may include a slope sensor portion sensing a slope of vehicle; a safety sensor portion sensing running safety information for a vehicle safety running; a sensing control angle generation portion sensing a sensing control angle from the sensed slope; and a safety sensor control portion controlling up and down direction angles of the safety sensor on the basis of a horizontal plane of vehicle depending on the sensing control angle.

EDMOS device having a lattice type drift region

The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Device and method for predicting state of battery

An apparatus and a method for predicting a state of a battery are provided. The apparatus includes a data measuring unit that measures information about the battery and outputs first data, a data producing unit that reflects a change in available capacity of the battery based on at least a portion of the first data to calculate a corrected state of charge and processes the first data based on the corrected state of charge to generate second data, and outputs the second data, and a battery state estimating unit that estimates state information of the battery based on the second data.

Object detection device and system

Provided are an object detection device and system. The object detection device includes an outline image extraction unit, a feature vector calculation unit, and an object judgment unit. The outline image extraction unit extracts an outline image from an input image. The feature vector calculation unit calculates a feature vector from the outline image by using histogram of oriented gradients (HOG) representing a frequency distribution of gradient vectors with respect to pixels of the outline image, and pixel coordinate information varying according to a spatial distribution of the gradient vectors. The object judgment unit judges a target object corresponding to the feature vector with reference to pre-learned data.

TRAINING FUNCTION GENERATING DEVICE, TRAINING FUNCTION GENERATING METHOD, AND FEATURE VECTOR CLASSIFYING METHOD USING THE SAME

Provided is a training function generating method. The method includes: receiving training vectors; calculating a training function from the training vectors; comparing a classification performance of the calculated training function with a predetermined classification performance and recalculating a training function on the basis of a comparison result, wherein the recalculating of the training function includes: changing a priority between a false alarm probability and a miss detection probability of the calculated training function; and recalculating a training function according to the changed priority. 1. A training function generating method comprising:receiving training vectors;calculating a training function from the training vectors;comparing a classification performance of the calculated training function with a predetermined classification performance and recalculating a training function on the basis of a comparison result,wherein the recalculating of the training function comprises:changing a priority between a false alarm probability and a miss detection probability of the calculated training function; andrecalculating a training function according to the changed priority.2. The method of claim 1 , wherein the classification performance of the calculated training function is determined by the false alarm probability and the miss detection probability of the calculated training function.3. The method of claim 2 , wherein the classification performance of the calculated training function is a miss detection probability when the calculated training function has a predetermined false alarm probability.4. The method of claim 1 , wherein the calculated training function is a linear function.5. The method of claim 1 , wherein the calculating of the training function uses a mean square error corresponding to the training vectors.6. The method of claim 5 , wherein the calculated function has a minimum value of the mean square error.7. The method of claim 1 , ...

DIRECT MEMORY ACCESS CONTROLLER AND OPERATING METHOD THEREOF

Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels. 1. An operating method of a direct memory access (DMA) controller having first and second DMA channels , comprising:(a) iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel;(b) iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel;(c) reconfiguring the transfer and loop information of the first and second DMA channels; and(d) again performing the steps (a) and (b) based upon the reconfigured transfer and loop information of the first and second DMA channels.2. The operating method of claim 1 , wherein each of the steps (a) and (b) comprises:(e) performing a DMA transfer operation according to a source address and a destination address included in the transfer information;(f) increasing the source address by a source address offset value included in the loop information and the destination address by a destination address offset value included in the loop information; and(g) iterating a DMA transfer operation according to the increased source address and the increased ...

Apparatus for calculating absolute difference

Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.

System on chip (SOC) system for a multimedia system enabling high-speed transfer of multimedia data and fast control of peripheral devices

Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.

OBJECT DETECTION DEVICE AND SYSTEM

Provided are an object detection device and system. The object detection device includes an outline image extraction unit, a feature vector calculation unit, and an object judgment unit. The outline image extraction unit extracts an outline image from an input image. The feature vector calculation unit calculates a feature vector from the outline image by using histogram of oriented gradients (HOG) representing a frequency distribution of gradient vectors with respect to pixels of the outline image, and pixel coordinate information varying according to a spatial distribution of the gradient vectors. The object judgment unit judges a target object corresponding to the feature vector with reference to pre-learned data.

Method for fabricating high density trench gate type power device

A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

Memory system and integrated management method for plurality of DMA channels

Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

Ferroelectric memory cell array and method of storing data using the same

The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.

MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS

Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

Semiconductor device having heat release structure using SOI substrate and fabrication method thereof

Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the ...

Sensing circuit for recognizing movement and movement recognizing method thereof

Provided is a sensing circuit for recognizing a movement including: at least one light emitting device outputting light; at least one light receiving device receiving the light reflected by an object on the light emitting device and generating a plurality of current signals proportional to an amount of incident light; a signal conversion unit converting the plurality of current signals into a plurality of digital signals; a recognition unit measuring a synthetic digital signal to determine whether an object moves by receiving the plurality of current signals; and a control unit controlling the recognition unit, wherein the recognition unit generates a clock signal for the synthetic digital signal greater than a critical value and measures a count generated by the clock signal; and the control unit determines whether the object moves through a comparison of the count and a reference value.

Analog-digital converter and converting method using clock delay

The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.

Method of manufacturing multiple-gate MOS transistor having an improved channel structure

Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability ...

High voltage MOSFET having Si/SiGe heterojunction structure and method of manufacturing the same

Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced ...

METHOD AND SYSTEM FOR DETECTING OBJECT

Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data. 1. A method of detecting an object , comprising:selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected;dividing an input image into one or more regions according to the selected scan mode;merging adjacent regions having similar characteristics among the divided regions;extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions;extracting feature data including a feature vector for detecting the object in the search region; anddetecting the object in the search region using the extracted feature data.2. The method of claim 1 , wherein dividing the input image into one or more regions includes continuously dividing a region until the region has a uniform characteristic.3. The method of claim 1 , wherein merging the adjacent regions having similar characteristics includes merging the adjacent regions having a difference in feature of a threshold or less among the divided regions.4. ...

Latch circuit and flip-flop

A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a high threshold backward clock inverter forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.

Reconfigurable arithmetic unit and high-efficiency processor having the same

Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit ...

Apparatus and method for preventing collision of vehicle

The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.

Arithmetic method and device of reconfigurable processor

Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

Multiple-gate MOS transistor using Si substrate and method of manufacturing the same

Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type

Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.

Method for fabricating a high-voltage high-power integrated circuit device

The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to ...

APPARATUS FOR CALCULATING ABSOLUTE DIFFERENCE

Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.

PROCESS INDEPENDENT TEMPERATURE SENSOR BASED ON OSCILLATOR

The inventive concept discloses a new temperature sensor structure based on oscillator which is insensitive to a process change and improves an error rate of temperature output. The temperature sensor based on oscillator compares an oscillator circuit structure insensitive to a temperature change with an oscillator circuit structure having a frequency change in proportion to a temperature change to output a relative difference between the two oscillator circuit structures and thereby it is compensated itself. In the temperature sensor based on oscillator, a problem of performance reduction due to an external environment and a process deviation of temperature sensor is improved and an output distortion and temperature nonlinearity are effectively improved. Thus, since the temperature sensor based on oscillator has a structure of high performance, low power and low cost, it can be variously used in a detection equipment of temperature environment.

Feature vector classification device and method thereof

Disclosed is a feature vector classification device which includes an initial condition setting unit; a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit; a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; and a hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit.

Monolithic metal-insulator transition device and method for manufacturing the same

Provided is a monolithic metal-insulator transition device. The monolithic metal-insulator transition device includes a substrate including a driving region and a switching region, first and second source/drain regions on the driving region, a gate electrode between the first and second source/drain regions, an inlet well region formed adjacent to an upper surface of the substrate on the switching region, a control well region having a different conductivity type from the inlet well region between the inlet well region and a lower surface of the substrate, a first wiring electrically connecting the first source/drain region and the control well region, and a second wiring electrically connecting the second source/drain region and the inlet well region.

APPARATUS AND METHOD FOR RECOGNIZING IMAGE

Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.

Method of fabricating TDMOS device using self-align technique

A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

IMAGE REGISTRATION DEVICE AND METHOD THEREOF

Disclosed is an image registration device which includes an image input unit which receives an image; an image information generating unit which generates a homography matrix from the input image; and a warping unit which registers an image based on the homography matrix. The registration information generating unit comprises a distance information generator which generates distance information on subjects of the input image; a distance information modeler which approximates the generated distance information; an overlap information generator which generates overlap information from the approximated distance information; a matching pair determiner which determines a matching pair from the overlap information; and a homography matrix generator which generates a homography matrix from the matching pair.

Multiple-gate MOS transistor using Si substrate and method of manufacturing the same

Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

Apparatus and method for calculating sum of absolute differences for motion estimation of variable block

An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

Successive approximation register analog-to-digital converter

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

METHOD OF PERFORMING 3D GRAPHICS GEOMETRIC TRANSFORMATION USING PARALLEL PROCESSOR

Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.

IMAGE RECOGNITION DEVICE AND METHOD OF RECOGNIZING IMAGE THEREOF

An image recognition device in accordance with the inventive concept may include an input vector extraction part extracting an input vector from an input image; a compression vector conversion part converting the input vector into a compression vector using a projection vector; a training parameter generation part receiving a training vector to generate a training parameter using a projection vector obtained through a folding operation of the training vector; and an image classification part classifying the compression vector using the training vector to output image recognition data.

EDMOS device having a lattice type drift region and method of manufacturing the same

The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Method and system for detecting object

Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data.

VEHICLE CRASH PREVENTION APPARATUS AND METHOD

The present invention relates to a vehicle accident prevention apparatus comprising a camera unit which photographs an image of a front view, an image recognition unit which processes the image of the front view to detect the registration number of a vehicle driving in front of the vehicle from a license plate of the vehicle driving in front of the vehicle, a wireless communication unit which receives accident prevention information containing an identifier and speed of the vehicle driving in front of the vehicle, a speed sensing unit which senses the speed of the vehicle equipped with the apparatus of the present invention, and a determining and control unit which identifies the vehicle driving in front of the vehicle by matching the registration number and the identifier of the vehicle driving in front of the vehicle, and generates a control signal for preventing vehicle accident by performing a speed comparison. 1. A vehicle accident prevention apparatus , comprising:a camera unit to photograph a front image of a vehicle;an image recognition unit to recognize a leading vehicle registration number from a license plate of a leading vehicle located at a front of the vehicle, through image processing of the front image;a wireless communication unit to receive accident prevention information including a leading vehicle identifier and a speed of the leading vehicle, through communicating with the leading vehicle;a speed detection unit to detect a speed of the vehicle; anda determining and control unit to identify the leading vehicle, through matching the leading vehicle registration number and the leading vehicle identifier, and generate a control signal for preventing an accident with the leading vehicle through comparing the speed of the vehicle to the speed of the leading vehicle.2. The vehicle accident prevention apparatus of claim 1 , further comprising:a global position system (GPS) module unit to measure a time of the vehicle.3. The vehicle accident prevention ...

Image registration device and method thereof

Disclosed is an image registration device which includes an image input unit which receives an image; an image information generating unit which generates a homography matrix from the input image; and a warping unit which registers an image based on the homography matrix. The registration information generating unit comprises a distance information generator which generates distance information on subjects of the input image; a distance information modeler which approximates the generated distance information; an overlap information generator which generates overlap information from the approximated distance information; a matching pair determiner which determines a matching pair from the overlap information; and a homography matrix generator which generates a homography matrix from the matching pair.

DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR

Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.

Process independent temperature sensor based on oscillator

The inventive concept discloses a new temperature sensor structure based on oscillator which is insensitive to a process change and improves an error rate of temperature output. The temperature sensor based on oscillator compares an oscillator circuit structure insensitive to a temperature change with an oscillator circuit structure having a frequency change in proportion to a temperature change to output a relative difference between the two oscillator circuit structures and thereby it is compensated itself. In the temperature sensor based on oscillator, a problem of performance reduction due to an external environment and a process deviation of temperature sensor is improved and an output distortion and temperature nonlinearity are effectively improved. Thus, since the temperature sensor based on oscillator has a structure of high performance, low power and low cost, it can be variously used in a detection equipment of temperature environment.

Input and output port circuit

The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously ...

Direct memory access controller and operating method thereof

Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.

High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same

Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced ...

HALL SENSOR SIGNAL GENERATING DEVICE

Disclosed is a hall sensor signal generating device which includes a rotor which has a magnetic property and rotates on the basis of a rotary axis; a hall sensor unit which is disposed to be spaced apart from a stator disposed outside the rotor; and a clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal. 1. A hall sensor signal generating device comprising:a rotor which has a magnetic property and rotates on the basis of a rotary axis;a hall sensor unit which is disposed on stator disposed outside the rotor; anda clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal.2. The hall sensor signal generating device of claim 1 , wherein the hall sensor signal generating device is included in a Brushless Direct Current (BLDC) motor.3. The hall sensor signal generating device of claim 1 , wherein the hall sensor signal generating device is included in a Synchronous Reluctance Motor (SynRM).4. The hall sensor signal generating device of claim 1 , wherein the hall sensor unit includes a plurality of hall sensors that are disposed with the same interval.5. The hall sensor signal generating device of claim 4 , wherein the plurality of hall sensors includes three hall sensors that are disposed with an interval of 120 degrees.6. The hall sensor signal generating device of claim 1 , further comprising:a clock generating unit which generates an internal driving clock; anda clock controlling unit which receives an external driving clock and a control signal from an external device, selects one of the external driving clock and the internal driving clock according to the control signal, and ...

PIPELINED DECODING APPARATUS AND METHOD BASED ON PARALLEL PROCESSING

An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs).

Dual structure FinFET and method of manufacturing the same

Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field ...

Image matching devices and image matching methods thereof

Provided is an image matching method of matching at least two images. The image matching method extracts feature points of a reference image and feature points of a target image, changes a feature point, selected from among the feature points of the reference image, to a reference point in the target image, sets a matching candidate region on the basis of the reference point, in the target image, and performs a similarity operation between the selected feature point in the reference image and a plurality of feature points included in the matching candidate region among the feature points of the target image. The image matching method decreases the number of similarity operations performed in the image matching operation, thereby guaranteeing a high-speed operation.

Image registration device and operation method of the same

Provided is an image registration device including a first feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one first feature point among feature points of a reference image to create a first magnitude value, a second feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one second feature point among feature points of a target image to create a second magnitude value, a magnitude difference calculating unit receiving the first and second magnitude values and calculating a difference between the received first and second magnitude values to create a third magnitude value, a first threshold value creating unit creating a first threshold value on the basis of the first magnitude value and a magnitude ratio, and a magnitude difference determining unit receiving the third magnitude value and the first threshold value, and determining a magnitude difference.

Wheel speed sensor interface, operation method thereof, and electronic control system including the same

Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.

Apparatus for controlling driving of lighting-emitting diode and method of providing control signal thereof

The control apparatus of the present invention determines a motion state of an object and provides an IRLED switching control signal suitable for the motion state in an apparatus for sensing/recognizing a motion of the object by using an infrared light-emitting diode (IRLED) and a photodiode (PD). Such a control apparatus is an LED driving control apparatus, and includes a motion velocity generating unit, a previous section average value generating unit, a state value generating unit, a control unit, and an LED switching control signal generating unit.

MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS

Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. 1. A memory system , comprising:a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other; anda direct memory access (DMA) controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.2. The memory system of claim 1 , further comprising a contact module connecting the channels of the memory controller with the DMA channels.3. The memory system of claim 2 , wherein the contact module includes a plurality of buses or a matrix switch for connecting the channels of the memory controller with the DMA channels.4. The memory system of claim 1 , wherein the DMA controller comprises:a register module having a set of registers storing information on the exchanged data; anda multi-channel management module dividing and setting set values for the plurality of DMA channels with reference to the set of registers.5. The memory system of claim 4 , wherein the set of registers includes at least one selected from the group consisting of a source address claim 4 , a destination address claim 4 , a transmission size claim 4 , a source address offset and a destination address offset claim 4 , andthe multi-channel management module sets values of source and destination addresses for the plurality of DMA channels by ...

DEVICE AND METHOD FOR PREDICTING STATE OF BATTERY

Disclosed is a battery state prediction device including a data measurement unit that measures information about a battery and to output first data and a battery state estimation unit that calculates a state of charge (SOC) value of the battery based on the first data, generates second data by pre-processing the first data based on the SOC value, and estimates a state of health (SOH) of the battery based on the second data. The battery state estimation unit calculates the SOC value based on an extended Kalman filter and adjusts a parameter of the extended Kalman filter based on the estimated SOH.

MEMS microphone using noise filter

An MEMS microphone is provided which includes a reference voltage/current generator configured to generate a DC reference voltage and a reference current; a first noise filter configured to remove a noise of the DC reference voltage; a voltage booster configured to generate a sensor bias voltage using the DC reference voltage the noise of which is removed; a microphone sensor configured to receive the sensor bias voltage and to generate an output value based on a variation in a sound pressure; a bias circuit configured to receive the reference current to generate a bias voltage; and a signal amplification unit configured to receive the bias voltage and the output value of the microphone sensor to amplify the output value. The first noise filter comprises an impedance circuit; a capacitor circuit connected to a output node of the impedance circuit; and a switch connected to both ends of the impedance circuit.

Image recognition device and method of recognizing image thereof

An image recognition device in accordance with the inventive concept may include an input vector extraction part extracting an input vector from an input image; a compression vector conversion part converting the input vector into a compression vector using a projection vector; a training parameter generation part receiving a training vector to generate a training parameter using a projection vector obtained through a folding operation of the training vector; and an image classification part classifying the compression vector using the training vector to output image recognition data.

VECTOR CLASSIFIER AND VECTOR CLASSIFICATION METHOD THEREOF

Provided is a vector classifier and a vector classification method. The vector classifier includes a vector compressor configured to compress an input vector; a support vector storage unit configured to store a compressed support vector; and a support vector machine operation unit configured to receive the compressed input vector and the compressed support vector and perform an arithmetic operation according to a classification determining equation.

Sound detecting circuit and amplifier circuit thereof

Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

Low-power clock gating circuit

Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

ANALOG-DIGITAL CONVERTER AND CONVERTING METHOD USING CLOCK DELAY

The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal. 1. An analog-digital converter which converts an analog signal into an N-bit digital signal (N being a positive integer) , comprising:a clock generating unit generating a clock signal;a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal (K being a positive integer of more than 1 and less than N) according to a control signal, the first clock signal being delayed by a first delay time from the clock signal and the Kth clock signal being delayed by a Kth delay time from the clock signal;a capacitive digital-analog converting unit receiving the analog signal and a reference signal and outputting a difference between the analog signal and the reference signal;a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; andan SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output ...

Sound detecting circuit and amplifier circuit thereof

Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD

Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics. 1. A voltage supply circuit comprising:a voltage regulator configured to receive an external power supply voltage to generate a charge pump power supply voltage based on comparison between a reference voltage and a feedback voltage; anda charge pump configured to perform charge pumping on the charge pump power supply voltage according to a clock to generate a charge pump output voltage,wherein the charge pump feeds back the charge pump output voltage to the voltage regulator through a feedback line connected to the voltage regulator.2. The voltage supply circuit as set forth in claim 1 , wherein when the charge pump output voltage fluctuates depending on load variation claim 1 , the feedback voltage fluctuates to compensate fluctuation of the charge pump output voltage.3. The voltage supply circuit as set forth in claim 1 , wherein the reference voltage is generated from a bandgap reference circuit.4. The voltage supply circuit as set forth in claim 1 , wherein the voltage regulator further comprises a voltage-controlled current source circuit to obtain the feedback voltage depending on an output of the voltage-controlled current source circuit.5. The voltage supply circuit as set forth in claim 4 , wherein the feedback voltage is obtained at the junction between an output terminal of the voltage-controlled current source circuit ...

FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME

Provided are a feature vector extractor and a recognition device using the same. The feature vector classifier includes a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; and a feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image. Thus, during extraction and classification of a feature vector, time required for the extraction and classification and the size of hardware required are significantly reduced. 1. A recognition device comprising:a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; anda feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image.2. The recognition device as set forth in claim 1 , wherein the feature vector extractor comprises:a feature extractor configured to extract a feature value from a search window of the input image; anda feature vector generator configured to generate a feature vector having the feature value as an element, compute the normalized value based on the feature value, and output the generated feature vector and the computed normalized value.3. The recognition device as set forth in claim 1 , wherein the feature vector classifier classifies the feature vector using a linear support vector machine (LSVM) algorithm.4. The recognition device as set forth in claim 3 , wherein the feature vector classifier comprises:a dot-product unit configured to perform dot product of the feature vector and a predetermined weighted vector; andan index classifier configured to classify an index of the feature vector based on a value of the dot product to classify the feature vector.5. The ...

BUS BRIDGE APPARATUS

Disclosed is a bus bridge apparatus may prevent a transfer performance from being lowered due to bus protocol performance mismatch between interconnections. The bus bridge apparatus is used to transfer data to a slave device of a network-based interconnection from a master device of a bus-based interconnection, data of the master device may be buffered by an internal buffer, and may then be transferred to the slave device. At this time, lowering of a transfer efficiency may be prevented by converting a transfer timing of addresses and data to be optimized to a transfer protocol of the network-based interconnection through a protocol converter. 1. A bus bridge apparatus comprising:a slave port which interfaces with a master device of a bus-based interconnection, receives read and write transfer command, address data, and write data from the master device, and transfers read data to the master device;a command controller which receives the transfer command;an address buffer which stores the address data;a write data buffer which stores the write data;a read data buffer which stores the read data;a protocol converter which interfaces with a slave device of a network-based interconnection, outputs write data of the master device to the slave device using the address data and the write data at the write transfer command, and receives read data from the slave device at the read transfer command; anda transfer mode controller which operates at read and write modes according to the transfer command under a control of the command controller and controls outputs of the address, read, and write buffers to transfer the read and write data.2. The bus bridge apparatus of claim 1 , wherein the slave port provides the command controller with command information associated with read and write transfer commands claim 1 , a burst type claim 1 , and a data transfer size received from the master device.3. The bus bridge apparatus of claim 2 , wherein the command controller provides the ...

MEMS MICROPHONE USING NOISE FILTER

An MEMS microphone is provided which includes a reference voltage/current generator configured to generate a DC reference voltage and a reference current; a first noise filter configured to remove a noise of the DC reference voltage; a voltage booster configured to generate a sensor bias voltage using the DC reference voltage the noise of which is removed; a microphone sensor configured to receive the sensor bias voltage and to generate an output value based on a variation in a sound pressure; a bias circuit configured to receive the reference current to generate a bias voltage; and a signal amplification unit configured to receive the bias voltage and the output value of the microphone sensor to amplify the output value. The first noise filter comprises an impedance circuit; a capacitor circuit connected to a output node of the impedance circuit; and a switch connected to both ends of the impedance circuit. 1. An MEMS microphone , comprising:a reference voltage/current generator configured to generate a DC reference voltage and a reference current;a first noise filter configured to remove a noise of the DC reference voltage;a voltage booster configured to generate a sensor bias voltage using the DC reference voltage the noise of which is removed;a microphone sensor configured to receive the sensor bias voltage and to generate an output value based on a variation in a sound pressure;a bias circuit configured to receive the reference current to generate a bias voltage; anda signal amplification unit configured to receive the bias voltage and the output value of the microphone sensor to amplify the output value,wherein the first noise filter comprises:an impedance circuit;a capacitor circuit connected to an output node of the impedance circuit; anda switch connected to both ends of the impedance circuit.2. The MEMS microphone of claim 1 , wherein the impedance circuit comprises:a first diode having a cathode connected to an input of the impedance circuit and an anode ...

Successive approximation register analog-to-digital converter

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

PULSE NOISE SUPPRESSION CIRCUIT AND PULSE NOISE SUPPRESSION METHOD THEREOF

Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level. 1. A pulse noise suppression circuit , comprising:a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal;a level reset circuit resetting the filter signal in response to the input signal and an output signal; andan output circuit converting the filter signal into the output signal of a pulse type,wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level.2. The circuit of claim 1 , wherein the level reset circuit does not reset the filter signal when the input signal and the output signal have different levels.3. The circuit of claim 1 , wherein the filter circuit comprises a driver circuit adjusting a current amount flowing through the filter circuit.4. The circuit of claim 3 , wherein the driver circuit comprises an inverter lowering a rate of voltage rise of the filter signal.5. The circuit of claim 3 , wherein the driver circuit comprises:a P-channel metal-oxide-semiconductor (PMOS) switch lowering a rate of voltage rise of the filter signal;an N-channel metal-oxide-semiconductor (NMOS) switch lowering the rate of voltage rise of the filter signal;a current source connected ...

APPARATUS FOR CONTROLLING DRIVING OF LIGHTING-EMITTING DIODE AND METHOD OF PROVIDING CONTROL SIGNAL THEREOF

The control apparatus of the present invention determines a motion state of an object and provides an IRLED switching control signal suitable for the motion state in an apparatus for sensing/recognizing a motion of the object by using an infrared light-emitting diode (IRLED) and a photodiode (PD). Such a control apparatus is an LED driving control apparatus, and includes a motion velocity generating unit, a previous section average value generating unit, a state value generating unit, a control unit, and an LED switching control signal generating unit. 1. An apparatus for controlling the driving of a light-emitting diode (LED) , the apparatus comprising:a motion velocity generating unit receiving an input signal to generate a motion velocity signal;a previous section average value generating unit comparing input signals received in previous sections to generate a previous section average value;a state value generating unit generating a motion state value for the input signal based on the previous section average value and settings for determination of a motion state of the object;a control unit applying the settings to the state value generating unit, wherein the control unit receives the motion velocity signal and the motion state value and generates a frequency value of a switching control signal; andan LED switching control signal generating unit generating an LED switching control signal in response to the frequency value of the switching control signal, wherein the LED switching control signal generating unit applies a generated signal to a driving unit driving an LED.2. The apparatus of claim 1 , wherein the input signal is one or more photodiode (PD) signals.3. The apparatus of claim 1 , wherein the control unit comprises:a setting register unit storing frequency information, velocity information, and time information as settings for determination of the motion state of the object;a variable state frequency generator generating a variable state frequency for ...

WHEEL SPEED SENSOR INTERFACE, OPERATION METHOD THEREOF, AND ELECTRONIC CONTROL SYSTEM INCLUDING THE SAME

Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device. 1. A wheel speed sensor interface comprising:a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; anda comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.2. The wheel speed sensor interface of claim 1 , wherein the comparison speed detection circuit comprises:a plurality of counters configured to generate a plurality of counting values by counting each of the plurality of the detected speed pulses; anda time division multiplexer configured to receive the plurality of the generated counting values and transmit the comparison speed information to the external device by multiplexing the plurality of the received counting values through the time division method.3. The wheel speed sensor ...

CAPACITOR-TYPE SENSOR READ-OUT CIRCUIT

Provided is a capacitor-type sensor read-out circuit. The capacitor-type sensor read-out circuit includes: a signal conversion unit outputting a sensor signal inputted from a sensor; a voltage booster generating a bias voltage; and a capacitor-type signal coupling circuit receiving the sensor signal as a feedback, mixing the received sensor signal with the bias voltage, and outputting the mixed signal. 1. A capacitor-type sensor read-out circuit comprising:a signal conversion unit outputting a sensor signal inputted from a sensor;a voltage booster generating a bias voltage; anda capacitor-type signal coupling circuit receiving the sensor signal as a feedback, mixing the received sensor signal with the bias voltage, and outputting the mixed signal.2. The capacitor-type sensor read-out circuit of claim 1 , wherein the sensor signal mixed with the bias voltage is an alternating current (AC) signal.3. The capacitor-type sensor read-out circuit of claim 1 , wherein the signal conversion unit comprises:a high impedance circuit converting the sensor signal into a voltage signal;a first amplifier outputting the sensor signal converted into the voltage signal; anda second amplifier outputting the sensor signal outputted from the first amplifier.4. The capacitor-type sensor read-out circuit of claim 3 , wherein the capacitor-type signal coupling circuit comprises a first capacitor feeding back the sensor signal outputted from the first amplifier and mixing the sensor signal with the bias voltage.5. The capacitor-type sensor read-out circuit of claim 4 , wherein the capacitor-type signal coupling circuit comprises a second capacitor adjusting and outputting a gain of the bias voltage mixed with the sensor signal.6. The capacitor-type sensor read-out circuit of claim 1 , wherein the signal conversion unit comprises:a high impedance circuit converting the sensor signal into a voltage signal;a source follower outputting the sensor signal converted into the voltage signal; andan ...

OPERATING METHOD OF ROAD GUIDE SYSTEM AND ROAD GUIDE METHOD OF PORTABLE DEVICE

Provided is an operating method of a road guide system including collecting traffic information around a portable device through the portable device; delivering, to a server, the traffic information collected from the portable device and travel path information; updating the delivered travel path information based on the delivered traffic information; and feeding back the updated travel path information from the server to the portable device. 1. An operating method of a road guide system , the operating method comprising:collecting traffic information around a portable device through the portable device;delivering, to a server, the traffic information collected from the portable device and travel path information;updating the delivered travel path information based on the delivered traffic information; andfeeding back the updated travel path information from the server to the portable device.2. The operating method of claim 1 , wherein the collecting of the traffic information comprises:sensing positional information on the portable device through a global positioning system (GPS); andimaging, through an imaging device, traffic conditions around the portable device.3. The operating method of claim 1 , further comprising storing the delivered traffic information in the server.4. The operating method of claim 1 , wherein the updating of the travel path information comprises updating the travel path information based on traffic information received from two or more portable devices.5. The operating method of claim 1 , wherein the server comprises map information that is required for updating the travel path information.6. A road guide method of a portable device claim 1 , the road guide method comprising:searching for travel path information based on map information;determining traffic conditions according to image information obtained by an imaging device;transmitting the determined traffic situations and positional information to the server;receiving, from the server ...

Image registration device and operation method of the same

Provided is an image registration device including a first feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one first feature point among feature points of a reference image to create a first magnitude value, a second feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one second feature point among feature points of a target image to create a second magnitude value, a magnitude difference calculating unit receiving the first and second magnitude values and calculating a difference between the received first and second magnitude values to create a third magnitude value, a first threshold value creating unit creating a first threshold value on the basis of the first magnitude value and a magnitude ratio, and a magnitude difference determining unit receiving the third magnitude value and the first threshold value, and determining a magnitude difference.

SENSING CIRCUIT FOR RECOGNIZING MOVEMENT AND MOVEMENT RECOGNIZING METHOD THEREOF

Provided is a sensing circuit for recognizing a movement including: at least one light emitting device outputting light; at least one light receiving device receiving the light reflected by an object on the light emitting device and generating a plurality of current signals proportional to an amount of incident light; a signal conversion unit converting the plurality of current signals into a plurality of digital signals; a recognition unit measuring a synthetic digital signal to determine whether an object moves by receiving the plurality of current signals; and a control unit controlling the recognition unit, wherein the recognition unit generates a clock signal for the synthetic digital signal greater than a critical value and measures a count generated by the clock signal; and the control unit determines whether the object moves through a comparison of the count and a reference value. 1. A sensing circuit for recognizing a movement , the circuit comprising:at least one light emitting device outputting light;at least one light receiving device receiving the light reflected by an object on the light emitting device and generating a plurality of current signals proportional to an amount of incident light;a signal conversion unit converting the plurality of current signals into a plurality of digital signals;a recognition unit measuring a synthetic digital signal to determine whether an object moves by receiving the plurality of current signals; anda control unit controlling the recognition unit,wherein the recognition unit generates a clock signal for the synthetic digital signal greater than a critical value and measures a count generated by the clock signal; andthe control unit determines whether the object moves through a comparison of the count and a reference value.2. The circuit of claim 1 , wherein the recognition unit comprises:a signal detection unit measuring the magnitudes of the plurality of digital signals at a predetermined time interval;a synthetic ...

DC-DC BOOST CONVERTER FOR POWER GENERATION ELEMENT

A DC-DC boost converter for a power generation element includes a power generation element configured to generate a both end voltage and a power supply current, an inductor charged by the power supply current, a first and second switch units comprising a plurality of first and second transistors, an MPPT control unit configured to detect the both end voltage and output a control signal to the first and second switch units so that an input voltage output from the power generation element is maintained as a predetermined proportion of the both end voltage, a current detection unit configured to output a signal for controlling the number of enabled first transistors and second transistors according to an intensity of the power supply current, and a switch selection unit configured to connect the first transistors and the second transistors through the signal. 1. A DC-DC boost converter for a power generation element , comprising:a power generation element configured to generate a both end voltage and a power supply current;an inductor connected between a first node and a second node and charged by the power supply current;a first switch unit comprising a plurality of first transistors connected between the second node and a third node;a second switch unit comprising a plurality of second transistors connected to the second node and a ground terminal;a maximum power point tracking control unit configured to detect the both end voltage and output a control signal to the first and second switch units so that an input voltage output from the power generation element is maintained as a predetermined proportion of the both end voltage;a current detection unit connected between the power generation element and the inductor and configured to output a signal for controlling the number of enabled first transistors of the first switch unit and the number of enabled second transistors of the second switch unit according to an intensity of the power supply current; anda switch ...

SEMICONDUCTOR AND METHOD OF MANUFACTURING THE SAME

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate including monocrystalline silicon or polycrystalline silicon, a first insulating layer on the semiconductor substrate, the first insulating layer including a local region in which a portion of an upper surface of the first insulating layer is recessed, a channel layer provided in the local region of the first insulating layer, a silicide provided on one side surface of the channel layer, a control gate provided on the channel layer, a gate insulating film provided between the channel layer and the control gate, and a polarity control gate arranged so as to overlap an interface between the channel layer and the silicide, wherein the polarity control gate is spaced apart from the control gate, and the channel layer includes monocrystalline silicon. 1. A semiconductor device comprising:a semiconductor substrate including monocrystalline silicon or polycrystalline silicon;a first insulating layer on the semiconductor substrate, the first insulating layer including a local region in which a portion of an upper surface of the first insulating layer is recessed;a channel layer provided in the local region of the first insulating layer;a silicide provided on one side surface of the channel layer;a control gate provided on the channel layer;a gate insulating film provided between the channel layer and the control gate; anda polarity control gate arranged so as to overlap an interface between the channel layer and the silicide,wherein the polarity control gate is spaced apart from the control gate, and the channel layer includes monocrystalline silicon.2. The semiconductor device of claim 1 ,wherein the first insulating layer further includes a hole,wherein the hole is arranged spaced apart from the local region.3. The semiconductor device of claim 1 ,wherein the first insulating layer further includes a hole,wherein the hole is contiguous to the local region.4. The semiconductor ...

Apparatus and method for recognizing image based on position information

According to the present invention, the amount of computation required for image recognition processing can be reduced by extracting only image recognition learning information for an object that may appear in a region having the geographical property of a current position and comparing the image recognition learning information with ambient-image information.

Data bus system for micro controller

Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Multi channel data transfer device

Provided is a multi channel data transfer device. The multi channel data transfer device includes: a plurality of channel control unit connected to a plurality of peripheral devices, respectively; a plurality of control registers storing setting data for controlling an operation of each of the plurality of channel controllers; and a common register controller delivering common setting data to all or part of the plurality of control registers, the common setting data being applied in common to all or part of the plurality of channel controllers.

Low-power clock gating circuit

Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

Apparatus and method for calculating sum of absolute differences for motion estimation of variable block

Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

Breaker of discontinuous jump current induced by insulator-metal transition in ac power system

Disclosed is a discontinuous jump current breaker, in an AC power system having an insulating material that exhibits nonlinear electrical characteristics between two electrodes, which blocks an AC power by observing a discontinuous jump current in which an insulator-metal transition occurs. The discontinuous jump current breaker includes a setting unit that sets the magnitude of a discontinuous jump current, a sensor unit including a metallic wire (Republic of Korea Patent Registration No. 10-1981640) parallel to an AC power wire, located at a separation distance d≥0, and that measures electromagnetic waves of an AC power, an amplifier unit that amplifies an analog signal of the metal wire, an analog-to-digital converter that converts the amplified analog signal to digital, a microcontroller unit including a memory unit for storing a program that drives the system, and a power blocking unit that blocks the discontinuous jump current.

Linear power amplifier using predistortion with feedback circuit

Semiconductor and method of manufacturing the same

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate including monocrystalline silicon or polycrystalline silicon, a first insulating layer on the semiconductor substrate, the first insulating layer including a local region in which a portion of an upper surface of the first insulating layer is recessed, a channel layer provided in the local region of the first insulating layer, a silicide provided on one side surface of the channel layer, a control gate provided on the channel layer, a gate insulating film provided between the channel layer and the control gate, and a polarity control gate arranged so as to overlap an interface between the channel layer and the silicide, wherein the polarity control gate is spaced apart from the control gate, and the channel layer includes monocrystalline silicon.