Semiconductor package with single sided substrate design and manufacturing methods thereof

A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Test method for memory

A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.

Embedded component package structure

The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

TEST METHOD FOR MEMORY

A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once. 1. A test method for testing a memory device including a memory array , the memory array including a plurality of symmetric memory cells , a plurality of word lines and a plurality of bit lines , the test method including: charging a first bit line of the bit lines to test a single bit of a first half of a first symmetric memory cell adjacent to the first bit line; and', 'charging a second bit line of the bit lines to test a single bit of a second half of a second symmetric memory cell adjacent to the second bit line; and, 'in testing a first word line of the word lines,'} charging the first bit line of the bit lines to test a single bit of the second half of a third symmetric memory cell adjacent to the first bit line; and', 'charging the second bit line of the bit lines to test a single bit of the first half of a fourth symmetric memory cell adjacent to the second bit line;, 'in testing a second word line of the word lines,'}wherein in testing each of the word lines, each of the bit lines is charged once.2. The test method according to claim 1 , wherein in testing the first word line claim 1 , either one of the first half and the second half of each of the symmetric memory cells on the first word line is read and tested.3. ...

Semiconductor package and process for fabricating same

A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the ...

Memory control device, control method of flash memory, and method for generating security feature of flash memory

A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages.

SUBSTRATE HAVING EMBEDDED SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SAME, AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE

A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly.

Random number generator, encryption/decryption secret key generator and method based on characteristics of memory cells

A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number.

Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package

A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.

MEMORY CONTROL DEVICE, CONTROL METHOD OF FLASH MEMORY, AND METHOD FOR GENERATING SECURITY FEATURE OF FLASH MEMORY

A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages. 1. A method for generating a security feature of a flash memory , comprising:determining a memory block from a plurality of memory blocks in the flash memory;erasing data of the determined memory block of the flash memory;providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; andestablishing a security feature based on the plurality of corresponding threshold voltages of the cells.2. The method according to claim 1 , wherein the step of erasing data of the determined memory block comprises:erasing data in the determined memory block of the flash memory;writing a predetermined data to the determined memory block; anderasing the predetermined data in the written memory block.31. The method according to claim 1 , wherein the predetermined data is zero.41. The method according to claim 1 , wherein the step of providing the predetermined voltage to the memory block is different from a step of writing data to the memory block.51. The method according to claim 1 , wherein the security feature is produced according to at least one of at least part of the plurality of corresponding threshold voltages of the ...

Electronic device, related controller circuit and method

An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

Package carrier, semiconductor package, and process for fabricating same

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. 1. A semiconductor package , comprising:a substrate including:a first patterned conductive layer having an upper surface;a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a portion of the first patterned conductive layer to form a plurality of first contact pads;a second patterned conductive layer below the first patterned conductive layer and having a lower surface; the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and', 'the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and, 'a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, whereina plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to the second patterned conductive layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;a die electrically ...

NAND FLASH MEMORY CONTROLLER AND STORAGE APPARATUS APPLYING THE SAME

A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.

Embedded component substrate and manufacturing methods thereof

An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

RANDOM NUMBER GENERATOR, ENCRYPTION/DECRYPTION SECRET KEY GENERATOR AND METHOD BASED ON CHARACTERISTICS OF MEMORY CELLS

A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number. 1. A method for generating a random number , applied in a random number generator coupled to a flash memory , the method comprising:selecting a plurality of cells from the flash memory;initializing the selecting cells of the flash memory;programming the selecting cells to obtain a plurality of first potential values of the selecting cells;re-initializing the selecting cells of the flash memory;re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; andprocessing the first potential values and the second potential values according to a predetermined algorithm to generating the random number;wherein at least one of the first and the second potential values is different, and each of the first and the second potential values corresponds to a characteristic of each selected cell in the flash memory.2. The method of claim 1 , wherein a complexity of the random number is enhanced by the predetermined algorithm.3. The method of claim 1 , further comprising:obtaining an encryption/decryption key according to the random number.4. The method of claim 1 , wherein the step of processing the first potential values and the second potential values according to the predetermined algorithm comprises:subtracting the first potential values from the second potential values to obtain a ...

SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME

A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Embedded Component Substrate and Manufacturing Methods Thereof

An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second ...

SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF

A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.

Memory controller having temperature dependent data program scheme and related method

A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal.

Circuit board, and chip package structure

A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.

METHOD OF FABRICATING EMBEDDED COMPONENT PACKAGE STRUCTURE AND THE PACKAGE STRUCTURE THEREOF

The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time. 1. A method of fabricating an embedded component package structure , comprising:providing a first laminate structure having a first double-layered sheet and a first metal layer disposed on the first double-layered sheet, wherein the first double-layer sheet consists of a first dielectric layer and a second metal layer, the first and second metal layers are separated by the first dielectric layer and the first dielectric layer is sandwiched between the first and second metal layers;providing a second laminate structure having at least a hollow space therein, wherein the second laminate structure consists of a third metal layer and a second dielectric layer disposed on the third metal layer,providing an interlayer having a first surface and a second surface opposite to the first surface;joining the first laminate structure and the second laminate structure respectively to the first and second surfaces of the interlayer, wherein the second dielectric layer of the second laminate structure is joined to the second surface of the interlayer, and the at least hollow space covered by the interlayer turns into at least a cavity exposing a part of the interlayer, and wherein the first dielectric layer and the second metal layer of the first double-layer sheet is joined to the first surface of the interlayer;performing a drilling process to the form a plurality of through holes in the first laminate structure, the interlayer and the second laminate structure joined together;forming a plurality of plated-through hole structures covering the plurality of the through holes and in the first laminate structure, the ...

Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof

A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.

Operation method for memory device

Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.

SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

NAND flash memory controller and storage apparatus applying the same

A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.

Lighting module

The lighting module includes a light emitter, a hood and a cover. The light emitter is mounted on an end of the hood. The cover is disposed in the hood and has a conic reflecting surface. When the light emitter is lit up, the lights are emitted into the hood and reflected by the conic reflecting surface and then further reflected by the hood to be projected outward.

Embedded component device and manufacturing methods thereof

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

Semiconductor package

A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Semiconductor package with substrate having single metal layer and manufacturing methods thereof

A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof

A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

EMBEDDED COMPONENT DEVICE AND MANUFACTURING METHODS THEREOF

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening. 1. An embedded component device , comprising:an electronic component including an electrical contact;an upper patterned conductive layer;a dielectric layer between the upper patterned conductive layer and the electronic component, the dielectric layer having a first opening exposing the electrical contact;a first electrical interconnect extending from the electrical contact to the upper patterned conductive layer, wherein the first electrical interconnect fills the first opening;a lower patterned conductive layer, the dielectric layer having a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer, the second opening having an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer;a conductive via located at the lower portion of the second opening; anda second electrical interconnect filling the upper portion of the second opening.2. The embedded component device of claim 1 , ...

Single Layer Coreless Substrate

An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages. 1. An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer , wherein the via post layer comprises via posts embedded in a dielectric material comprising glass fibers in a polymer resin , and the chip and routing layer are embedded in a second layer of dielectric material encapsulating the chip and the routing layers.2. The electronic chip package of further comprising a metallic sacrificial base on an opposite side of the via post layer from the routing layer.3. The electronic chip package of wherein at least one via post in the via post layer has a non-cylindrical shape characterized by having a long dimension in the X-Y plane that is at least 3 times as long as the short dimension in the X-Y plane.4. The electronic chip package of wherein an underside of the interposer comprises copper ends of via posts surrounded with the dielectric material such that the copper ends of the via posts are flush with the dielectric material.5. The electronic chip package of wherein an underside of the interposer comprises copper ends of via posts surrounded with the dielectric material such that the copper ends of the via posts are recessed by up to 5 microns with respect to the dielectric material.6. The electronic chip package of wherein said via layer comprises copper vias and a barrier metal layer covering ends distanced from the routing layer such that an underside of the interposer comprises ends of via posts comprising barrier metal ...

CIRCUIT BOARD AND METHOD OF MAKING CIRCUIT BOARD

A circuit board includes a first conductive circuit layer, a cover layer, and a second conductive circuit layer. The cover layer includes an adhesive layer and a base film. The first conductive circuit layer is embedded within the adhesive layer. One side of the first conductive circuit layer is revealed from the adhesive layer. The second conductive circuit layer is located on a side of the base film facing away from the adhesive layer. The cover layer defines a first through hole and a second through hole passing through the cover layer. A diameter of the first through hole is greater than a diameter of the second through hole. The first through hole is filled with a copper post adjacent to the first conductive circuit layer and an electroplating layer adjacent to the second conductive circuit layer. The second through hole is filled with the electroplating layer. 1. A circuit board manufacturing method comprises:providing a carrier plate, the carrier plate comprising a seed layer, and electroplating a surface of the seed layer to form a first conductive circuit layer;forming at least one copper post on a surface of the first conductive circuit layer, the at least one copper post being located at a predetermined first conductive hole;providing a cover layer and attaching the cover layer to the first conductive circuit layer and the at least one copper post;defining at least one first through hole and at least one second through hole in the cover layer, wherein the at least one first through hole is aligned with the at least one copper post, the at least one second through hole is aligned with the first conductive circuit layer, a diameter of the first through hole is greater than a diameter of the second through hole, and a depth of the first through hole is less than a depth of the second through hole;electroplating a surface of the cover layer to form a second conductive circuit layer and electroplating the first through hole and the second through hole to form ...

PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments. 1. A semiconductor fabrication process , comprising:(a) forming a first conductive pattern adjacent to a carrier;(b) forming a plurality of first conductive post segments on the first conductive pattern; and(c) applying a dielectric layer to the first conductive pattern and exposing the first conductive post segments.2. The process as claimed in claim 1 , wherein (a) claim 1 , the carrier includes a first conductive layer claim 1 , and the first conductive pattern is formed on the first conductive layer.3. The process as claimed in claim 2 , wherein the first conductive pattern is formed by a semi-additive process claim 2 , and the first conductive layer provides a current pathway for electroplating.4. The process as claimed in claim 2 , wherein the first conductive post segments are formed by a semi-additive process claim 2 , and the first conductive layer and the first conductive pattern provide a current pathway for electroplating.5. The process as claimed in claim 2 , further comprising:(d ...

Single Layer Coreless Substrate

An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages. 1. A method of fabricating an electronic chip package comprising the steps of:(a) selecting a sacrificial substrate;(b) depositing an etchant resistant barrier layer onto said sacrificial substrate;(c) plating a layer of via posts;(d) laminating the layer of via posts with a dielectric material;(e) thinning and planarizing the dielectric layer;(f) plating a layer of routing features over the via layer;(g) attaching at least one chip, and(h) encapsulating the at least one chip and routing features with a second dielectric material.(i) removing the sacrificial substrate, and(j) removing barrier layer.2. The method of wherein step (g) comprises wire bonding the at least one chip to the routing features and step (h) comprises encapsulating with a molding material.3. The method of wherein step (g) comprises flip chip bonding the at least one chip to the routing features with an array of bumps.4. The method of claim 3 , wherein step (h) comprises encapsulating with a glass fiber in polymer pre-preg.5. The method of claim 1 , wherein the sacrificial substrate comprises a peelable copper substrate claim 1 , a release layer and an ultra-fine copper foil claim 1 , and step (i) of removal of the sacrificial substrate comprises peeling away the peelable copper substrate and etching away the remaining copper foil.6. The method of further comprising the step (k) of terminating the substrate by removing the etchant resistant barrier layer to expose ends of vias on outer surfaces of the stack and applying terminations to said ends ...

Electronic device, related controller circuit and method

An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

MEMORY CONTROLLER AND RELATED METHOD

A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal. 1120. A memory controller () , comprising:{'b': '140', 'an interface (), configured to operably communicate with a host device;'}{'b': 121', '121, 'a temperature detecting circuit (), configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit () generates a control signal (Sc); and'}{'b': 122', '140', '121', '130, 'a processing circuit (), coupled to the interface () and the temperature detecting circuit (), for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory () according to the control signal (Sc).'}2120130. The memory controller () of claim 1 , wherein when the ambient temperature falls within the predetermined temperature range claim 1 , the processing circuit is further arranged to use a predetermined data program scheme to program the data into a second storage block of the flash memory () claim 1 , wherein a first storage unit of the first storage block is a first bit number claim 1 , a second storage unit of the second storage block is a second bit number claim 1 , and the second bit number is greater than the first bit number.3120. The memory controller () of claim 2 , wherein the second storage unit is a form of a quad-level cell (QLC) claim 2 , and the first storage unit is a form of one of a single-level cell (SLC) claim 2 , ...

Package carrier, semiconductor package, and process for fabricating same

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package

Single layer coreless substrate

An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.

Substrate having single patterned metal foil, and package applied with the same, and methods of manufacturing the substrate and package

Package carrier, package structure and process of fabricating package carrier

Fabrication method of circuit board, circuit board, and chip package structure

A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.

Chip package

具有全厚度同軸結構的多層電子結構

一種多層電子結構，其包括在X-Y平面中延伸的多個介電層，並且包括在基本垂直於X-Y平面的Z方向上延伸穿過至少一個介電層的至少一個堆疊柱同軸對，其中所述堆疊通孔柱同軸對包括被環形通孔柱包圍的中心柱，所述中心柱與所述環形通孔柱被介電材料隔離管所分隔開。

Fabrication method of circuit board, circuit board, and chip package structure

Semiconductor package, substrate, and manufacturing method of substrate