Memristive Negative Differential Resistance Device

A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material. 1. A memristive Negative Differential Resistance (NDR) device comprising:a first electrode adjacent to a memristive matrix, said memristive matrix comprising an intrinsic semiconducting region and a highly doped secondary region;a Metal-Insulator-Transition (MIT) material in series with said memristive matrix; anda second electrode adjacent to said MIT material.2. The device of claim 1 , in which said MIT material comprises at least one of: a vanadium oxide material claim 1 , a niobium oxide material claim 1 , an iron oxide material claim 1 , a manganese oxide material claim 1 , and a titanium oxide material.3. The device of claim 1 , in which one of: said first electrode and said second electrode is connected to:a capacitance in parallel with said memristive NDR device; anda bias voltage supply to apply a bias voltage to said memristive NDR device such that an oscillating signal is produced.4. The device of claim 3 , in which one of said first electrode and said second electrode is connected to a programming voltage supply to change a resistive state of said memristive NDR device by applying a programming voltage to move an interface between said semiconducting region and said highly doped semiconducting region.5. The device of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to stop oscillating.6. The device of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to start oscillating.7. The device of claim 4 , in which a programming voltage from said programming ...

MEMORY ARRAY WITH WRITE FEEDBACK

A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance. 1. A memory array with write feedback , the memory array comprising:a number of row lines intersecting a number of column lines;a memory element connected between one of said row lines and one of said column lines; andan electrical condition supply to be selectively applied to one of said row lines; anda feedback control loop to control an electrical condition supplied by said electrical condition supply.2. The memory array of claim 1 , in which said electrical condition is controlled to cause said memory element to exhibit a target resistance.3. The memory array of claim 2 , in which said target resistance is one of a discrete set of values used to represent digital data.4. The memory array of claim 1 , in which said feedback control loop comprises:a sensor connected to one of said column lines connected to said memory element; anda comparator with a first input to receive an output signal from said sensor and a second input to receive a reference signal, an output of said comparator connected to said pulse driver.5. The memory array of claim 1 , in which said feedback control loop includes a filter mechanism between said sensor and said comparator.6. The memory array of claim 1 , in which said feedback control loop comprises at least one of: a latch ...

SEMICONDUCTOR DEVICE FOR PROVIDING HEAT MANAGEMENT

A semiconductor device for providing heat management may include a first electrode with low metal thermal conductivity and a second electrode with low metal thermal conductivity. A metal oxide structure which includes a transition metal oxide (TMO) may be electrically coupled to the first electrode and second electrode and the metal oxide structure may be disposed between the first electrode and second electrode. An electrically insulating sheath with low thermal conductivity may surround the metal oxide structure. 1. A semiconductor device for providing heat management , comprising:a first electrode with low metal thermal conductivity;a second electrode with low metal thermal conductivity;a metal oxide structure including a transition metal oxide (TMO) electrically coupled to the first electrode and second electrode, and the metal oxide structure being disposed between the first electrode and second electrode; andan electrically insulating sheath with low thermal conductivity surrounding the metal oxide structure.2. The semiconductor device of claim 1 , wherein the metal oxide structure exhibits first order metal-insulator phase transition (MIT) characteristics in a pre-defined temperature range.3. The semiconductor device of claim 1 , wherein the metal oxide structure exhibits a current controlled (CC) negative differential resistance (NDR) current-voltage (I-V) characteristics in a pre-defined temperature range.4. The semiconductor device of claim 1 , wherein a transition metal in the transition metal oxide (TMO) is selected from the group consisting of elements from the third group claim 1 , fourth group claim 1 , fifth group claim 1 , sixth group claim 1 , seventh group on the periodic table claim 1 , and combination thereof.5. The semiconductor device of claim 1 , wherein a transition metal in the transition metal oxide (TMO) is selected from the group consisting of Vanadium (V) claim 1 , Titanium (Ti) claim 1 , Niobium (Nb) claim 1 , Tantalum (Ta) claim 1 , ...

Memristive programmable frequency source and method

A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Memory resistor adjustment using feedback control

Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

ELECTRICAL CIRCUIT COMPONENT

An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material. 1. An electrical circuit component comprising:a first electrode;a plurality of second electrodes; anda negative differential resistance (NDR) material, wherein the first electrode and the plurality of second electrodes are connected to the NDR material, and wherein the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material.2. The electrical circuit component according to claim 1 , further comprising:a substrate upon which the first electrode, the plurality of second electrodes, and the NDR material are positioned.3. The electrical circuit component according to claim 2 , wherein the substrate comprises a material selected from the group consisting of plastic claim 2 , glass claim 2 , paper claim 2 , silicon (Si) claim 2 , gallium arsenide (GaAs) claim 2 , indium phosphide (InP) claim 2 , paper claim 2 , and other type III-V materials.4. The electrical circuit component according to claim 1 , wherein the NDR material comprises a material selected from the group consisting of vanadium oxide claim 1 , titanium oxide claim 1 , manganese oxide claim 1 , niobium oxide claim 1 , tungsten oxide claim 1 , and aluminum oxide.5. The electrical circuit component according to claim 1 , wherein the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a ...

Oscillator circuitry having negative differential resistance

Circuitry is provided that closely emulates biological neural responses. Two astable multivibrator circuits (AMCs), each including a negative differential resistance device, are coupled in series-circuit relationship. Each AMC is characterized by a distinct voltage-dependant time constant. The circuitry exhibits oscillations in electrical current when subjected to a voltage equal to or greater than a threshold value. Various oscillating waveforms can be produced in accordance with voltages applied to the circuitry.

DEVICE HAVING MEMRISTIVE MEMORY

A device () may include a semiconductor layer section () and a memory layer section () disposed above the semiconductor layer section (). The semiconductor layer section () may include a processor () and input/output block (), and the memory layer section () may include memristive memory (). A method of forming such device (), and an apparatus () including such device () are also disclosed. Other embodiments are described and claimed. 110. A device () comprising:{'b': 25', '12', '412', '16', '416, 'a semiconductor layer section () including a processor (; ) and input/output block (; ); and'}{'b': 45', '25', '14', '300, 'a memory layer section () disposed above said semiconductor layer section () and including memristive memory (; ).'}218418124121641645. The device of claim 1 , further comprising a bus (; ) for communicating among the processor (; ) claim 1 , input/output block (; ) claim 1 , and memory layer section ().3252242218418. The device of claim 2 , wherein the semiconductor layer section () further includes a volatile memory block (; ) in communication with the bus (; ).4352545. The device of claim 1 , further comprising a via array section () disposed between the semiconductor layer section () and the memory layer section ().5184181241216416451841835. The device of claim 4 , further comprising a bus (; ) for communicating among the processor (; ) claim 4 , input/output block (; ) claim 4 , and memory layer section () claim 4 , wherein the bus (; ) comprises at least part of said via array section ().616416. The device of claim 1 , wherein said input/output block (; ) communicates with external apparatuses.7. A method comprising:{'b': 25', '12', '412', '16', '416, 'forming a semiconductor layer section () to include a processor (; ) and input/output block (; ); and'}{'b': 45', '25', '45', '14', '300, 'forming a memory layer section () above said semiconductor layer section (), said memory layer section () including memristive memory (; ).'}8352545. The ...

MEMRISTOR WITH CONTROLLED ELECTRODE GRAIN SIZE

A memristor with a controlled electrode grain size includes an adhesion layer, a first electrode having a first surface contacting the adhesion layer and a second surface opposite the first surface, in which the first electrode is formed of an alloy of a base material and at least one second material, and in which the alloy has a relatively smaller grain size than a grain size of the base material. The memristor also includes a switching layer positioned adjacent to the second surface of the first electrode and a second electrode positioned adjacent to the switching layer. 1. A memristor with a controlled electrode grain size , said memristor comprising:an adhesion layer;a first electrode having a first surface contacting the adhesion layer and a second surface opposite the first surface, wherein the first electrode is formed of an alloy of a base material and at least one second material, wherein the alloy has a relatively smaller grain size than a grain size of they base material;a switching layer positioned adjacent to the second surface of the first electrode; anda second electrode positioned adjacent to the switching layer.2. The memristor of claim 1 , wherein at least a portion of the second electrode overlaps at least a portion of the first electrode and wherein the switching layer is positioned within an area of the overlapped region.3. The memristor of claim 1 , wherein the area of the overlapped region is smaller than about 50 nm×50 nm.4. The memristor of claim 1 , wherein the area of the overlapped region is smaller than about 30 nm×30 nm.5. The memristor of claim 1 , wherein the at least one second material comprises a material that is relatively nonreactive with a material forming the adhesion layer.6. The memristor of claim 1 , wherein the base material and the at least one second material are selected from the group consisting of platinum claim 1 , palladium claim 1 , gold claim 1 , tantalum claim 1 , cobalt claim 1 , osmium claim 1 , iridium claim 1 ...

MULTILAYER STRUCTURE BASED ON A NEGATIVE DIFFERENTIAL RESISTANCE MATERIAL

A multilayer structure is disclosed that includes a conductive layer, a layer of a negative differential resistance (NDR) material disposed above the conductive layer, a layer M disposed above the NDR material, a second layer of NDR material disposed above layer M, and a conductive layer disposed above the second NDR layer. Layer M can include a conductive material interspersed with regions of a dielectric material or a layer of the dielectric material and regions of the conductive material disposed above and below the dielectric material. 1. A multilayer structure comprising:{'b': '1', 'a conductive layer M;'}{'b': 1', '1', '1, 'a layer NDR disposed above the conductive layer M in a z-direction of the multilayer structure, wherein layer NDR comprises a first negative differential resistance material;'}{'b': 2', '1, 'a layer M disposed above layer NDR in the z-direction;'}{'b': 2', '2', '2, 'a layer NDR disposed above layer M in the z-direction, wherein layer NDR comprises a second negative differential resistance material; and'}{'b': 3', '2, 'a conductive layer M disposed above layer NDR in the z-direction;'}{'b': '2', 'claim-text': a conductive material interspersed with regions of a dielectric material; or', 'a layer of the dielectric material and regions of the conductive material disposed above and below the dielectric material., 'wherein layer M comprises22. The multilayer structure of claim 1 , wherein layer M comprises the conductive material interspersed with at least two regions of the dielectric material claim 1 , wherein the at least two regions are separated by the conductive material in an x-direction of the multilayer structure claim 1 , and wherein each region of the dielectric material has a same length as the conductive material in a y-direction of the multilayer structure.32. The multilayer structure of claim 1 , wherein layer M comprises the conductive material interspersed with multiple separated regions of the dielectric material in a periodic ...

CHAOTIC OSCILLATOR-BASED RANDOM NUMBER GENERATION

Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance. 1. A circuit , comprising:a negative differential resistance (NDR) device to receive an alternating current (AC) bias;a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period; anda random number generator to generate random numbers using samples of the voltage across the capacitance.2. The circuit of claim 1 , further comprising:a resistance in series with the NDR device and the capacitance.3. The circuit of claim 1 , wherein the circuit is formed on a semiconductor device claim 1 , and wherein the NDR device comprises a metal-oxide-metal device formed on the semiconductor device.4. The circuit of claim 1 , wherein claim 1 , in response to the DC bias and noise claim 1 , the capacitance repeatedly charges when the NDR device exhibits a high resistance state claim 1 , and discharges when NDR device exhibits a low resistance state claim 1 , to produce oscillations in the voltage across the capacitance having the chaotic period.5. The circuit of claim 1 , wherein the capacitance is a capacitor or an adjustable capacitor.6. A circuit claim 1 , comprising:a relaxation oscillator to receive a direct current (DC) input voltage as input, and having a capacitance in parallel with a negative differential ...

METAL-INSULATOR TRANSITION LATCH

A metal-insulator transition (MIT) latch includes a first electrode spaced apart from a second electrode and an MIT material disposed between said first and second electrodes. The MIT material comprises a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current. Either the first or second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of the MIT material. 1. A metal-insulator transition (MIT) latch , comprising:a first electrode spaced apart from a second electrode;an MIT material disposed between said first and second electrodes;said MIT material comprising a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current; andat least said first or said second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of said MIT material.2. The latch of claim 1 , wherein said electrical bias source comprises a current regulator.3. The latch of claim 1 , wherein said electrical bias source comprises a voltage regulator.4. The latch of claim 1 , wherein said first and second electrodes are part of a two terminal device.5. The latch of claim 1 , wherein said MIT material is incorporated into a shift-register claim 1 , Goto pairs claim 1 , delay circuit claim 1 , or combinations thereof.6. The latch of claim 1 , wherein said MIT material is incorporated into volatile memory storage.7. The latch of claim 1 , wherein said MIT material also comprises a thermal characteristic exhibited by said MIT material transitioning phases when said bias source applies a signal outside of an NDR range.8. A method for controlling a latch comprising:setting a metal-insulator transition (MIT) material in a first or second resistance phase through joule heating by applying an electrical bias to said MIT material outside of a ...

PRINTHEAD ASSEMBLY INCLUDING MEMORY ELEMENTS

A printhead assembly for a printing device is provided that includes a printhead comprising non-volatile memory elements. The memory elements include memristive elements. Each memristive element includes an active region disposed between two electrodes. The active region includes a switching layer formed of a switching material capable of carrying a species of dopants and a conductive layer in electrical contact with the switching layer, the conductive layer being formed of a dopant source material that includes the species of dopants that are capable of drifting into the switching layer under an applied potential. 1. A printhead assembly for a printing device , comprising: 'an active region disposed between and in electrical contact with first and second electrical contacts, the active region having a switching layer formed of a switching material capable of carrying a species of dopants and transporting the dopants under an applied potential and a conductive layer in electrical contact with the switching layer, the conductive layer being formed of a dopant source material that includes the species of dopants that are capable of drifting into the switching layer under the applied potential.', 'a printhead comprising non-volatile memory elements, wherein the memory elements comprise memristive elements, and wherein each memristive element comprises2. The printhead assembly of claim 1 , wherein the switching material comprises an insulating material claim 1 , wherein the insulating material comprises an oxide of aluminum claim 1 , an oxide of silicon claim 1 , a carbonate of silicon claim 1 , an oxide of gallium claim 1 , an oxide of germanium claim 1 , or an oxide of a transition metal claim 1 , wherein the transition metal is Sc claim 1 , Ti claim 1 , V claim 1 , Cr claim 1 , Mn claim 1 , Fe claim 1 , Co claim 1 , Ni claim 1 , Cu claim 1 , Zn claim 1 , Y claim 1 , Zr claim 1 , Nb claim 1 , Mo claim 1 , Hf claim 1 , Ta claim 1 , W claim 1 , or Re claim 1 , wherein ...

STATEFUL NEGATIVE DIFFERENTIAL RESISTANCE DEVICES

A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state. 1. A stateful NDR device comprising:a first conductive electrode;a second conductive electrode;a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy; anda second material comprising a differential resistance that is negative in a locally active region,in which the first material and second material are sandwiched between the first conductive electrode and second conductive electrode.2. The device of claim 1 , in which the first material is a bipolar memristive element.3. The device of claim 1 , in which a bipolar memristive element comprises one of: tantalum oxide (TaO) claim 1 , hafnium oxide (HfO) claim 1 , titanium oxide (TiO) and zirconium oxide (ZrO).4. The device of claim 1 , in which the first material is a unipolar memristive element for exhibiting a metal-insulator transition induced by Joule-heating.5. The device of claim 1 , in which the first material is a thin film of unipolar memristive material interposed between the first electrode and the second material.6. The device of claim 1 , in which the first material exhibits a nonlinear resistance change based on a magnitude and ...

Metal-insulator transition switching devices

A metal-insulator transition switching device includes a first electrode and a second electrode. A channel region which includes a bulk metal-insulator transition material separates the first electrode and the second electrode. A method for forming a metal-insulator transition switching device includes depositing a layer of bulk metal-insulator transition material in between a first electrode and a second electrode to form a channel region and forming a gate electrode operatively connected to the channel region.

METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE

A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed. 1. A method of switching a memristive device , comprising:applying a first current ramp of a first polarity to the memristive device;monitoring a resistance of the memristive device during the first current ramp; andremoving the first current ramp when the resistance of the memristive device reaches a first target value.2. A method as in claim 1 , wherein the step of monitoring includes:applying the first current ramp simultaneously and in parallel to a reference resistor of the target value;comparing a voltage across the memristive device with a voltage across the reference resistor.3. A method as in claim 2 , wherein the step of comparing includes feeding the voltage across the memristive device and the voltage across the reference resistor to a latched comparator.4. A method as in claim 2 , wherein the steps of applying the current ramp to the memristive device and the reference resistor include driving a current mirror with the current ramp and feeding output currents of the current mirror to the memristive device and the reference resistor.5. A method as in claim 1 , further including:applying a second current ramp to the memristive device;monitoring the resistance of the memristive device during the second current ramp;removing the second current ramp from the memristive device when the resistance of the memristive device reaches a second resistance value.6. A method as in claim 1 , wherein the second current ramp is of the first polarity.7. A method as in claim 5 , wherein the second current ramp is of a second polarity opposite to the first polarity.8. A switching circuit for switching a memristive device claim 5 , comprising:a current driver component for passing a current ramp ...

Display Matrix with Resistance Switches

A display matrix may have a resistance switch and a display element formed on a common display substrate. The resistance switch may have a metal insulator transition (MIT) material that has a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance.

MEMORY DEVICES WITH IN-BIT CURRENT LIMITERS

A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided. 1. A memory device comprising:a first conductive layer;a second conductive layer;an in-bit current limiter comprising a voltage controlled negative differential resistance (VC-NDR) element in electrical contact with the first conductive layer; anda memristor element in electrical contact with the VC-NDR element and the second conductive layer.2. The device of claim 1 , in which the memristive element comprises a memristive matrix and mobile dopants within the memristive matrix.3. The device of claim 1 , in which the VC-NDR element comprises one of: at least one metal oxide layer; a semiconductor junction; and a combination of a metal oxide layer and a semiconductor layer.4. The device of claim 1 , in which the first conductive layer and second conductive layer are intersecting crossbars in a crossbar array.5. The device of claim 1 , further comprising a programming voltage applied across the first conductor layer and second conductor layer claim 1 , in which the VC-NDR element limits current through the memory device during application of the programming voltage.6. The device of claim 1 , further comprising a current-controlled negative differential resistance (CC-NDR) element in electrical series with the VC-NDR element and memristor element.7. The device of claim 1 , in which the VC-NDR element comprises a voltage current curve with a current limiting region that corresponds to programming voltages applied to the memristor element.8. A crossbar memory array comprising:a first crossbar;a second crossbar intersecting the first crossbar;a memory ...

MEMRISTOR WITH EMBEDDED SWITCHING LAYER

A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column. 1. A method of making a memristor with an embedded switching layer , the method comprising:exposing a surface portion of a first electrode material within a via to a reactive species to form a switching layer embedded within and at a surface of the via, the via being in contact with a first conductor trace;depositing a layer of second electrode material adjacent to the via surface and patterning the second electrode layer into a column aligned with the via;depositing an interlayer dielectric material to surround the column; andproviding a second conductor trace in electrical contact with the second electrode material of the column.2. The method of making a memristor with an embedded switching layer of claim 1 , further comprising:forming the via in a dielectric layer that covers the first conductor trace, the first conductor trace being supported by a substrate;filling the via with the first electrode material; andrendering the first electrode material in the via substantially planar with a surface of the dielectric layer before exposing a surface portion of the first electrode material to a reactive species.3. The method of making a memristor with an embedded switching layer of claim 1 , wherein the first electrode material comprises a diffusion barrier material that coats internal walls and a floor of the via; and ...

Storing Data in a Non-volatile Latch

Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair. 1. A non-volatile memory circuit , comprising:a memristor pair in electrical communication with a logic gate;a bias voltage source in communication with said memristor pair; anda transmission gate positioned to permit an input signal to pass to said logic gate.2. The circuit of claim 1 , wherein said circuit is a latch claim 1 , a flip flop claim 1 , a shift register claim 1 , or combinations thereof.3. The circuit of claim 1 , wherein said logic gate comprises at least one inverter.4. The circuit of claim 1 , wherein a memristor of said memristor pair is electrically connected to ground reference.5. A method of storing data in a non-volatile latch claim 1 , comprising:applying a bias voltage to a memristor pair in electrical communication with a at least one logic gate; andapplying a gate voltage to a transmission gate to allow an input voltage to be applied to said at least one logic gate where said input voltage is greater than said bias voltage and said input voltage determines resistance states in said memristor pair.6. The method of claim 5 , wherein said memristor pair is positioned between said transmission gate and said at least one logic gate.7. The method of claim 5 , wherein said at least one logic gate comprises at least one inverter.8. The method of claim 5 , wherein a first memristor of said memristor pair is arranged to have an opposite resistance state of a second memristor in said memristor pair.9. The method of claim 8 , wherein said bias voltage causes a resulting voltage to be applied to said at least one logic gate in an absence of said input ...

Logic circuits using neuristors

Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.

Shiftable memory

A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

SHIELDING A MEMORY DEVICE

A method of shielding a memory device () from high write rates comprising receiving instructions to write data at a memory container (), the memory controller () composing a cache () comprising a number of cache lines defining stored data, with the memory controller (), updating a cache line in response to a write hit in the cache (), and with the memory controller (), executing the instruction to write data in response to a cache miss to a cache line within the cache () in which the memory controller () prioritizes for writing to the cache () over writing to the memory device (). 1110. A method of shielding a memory device () from high write rates comprising;{'b': 105', '105', '120, 'receiving instructions to write data at a memory controller (), the memory controller () comprising a cache () comprising a number of cache lines defining stored data;'}{'b': 105', '120, 'with the memory controller (), updating a cache line in response to a write hit in the cache (); and'}{'b': 105', '120, 'with the memory controller (), executing the instruction to write data in response to a cache miss to a cache line within the cache ();'}{'b': 100', '120', '110, 'in which the memory controller () prioritizes for writing to the cache () over writing to the memory device ().'}2120110. The method of claim 1 , in which executing the instruction to write data in response to a cache miss to a cache line within the cache () further comprises writing an evicted cache line to the memory device ().3. The method of claim 2 , in which the evicted cache line is a least recently used cache line.4110. The method of claim 1 , in which the memory device () is a memristive device.5120. The method of claim 1 , in which the cache () implements a write-back policy.6110. The method of claim 1 , in which the memory device () comprises a number of data lines separated into spare lines and initial lines and in which the method further comprises;{'b': '110', 'receiving instructions to write data to an ...

Locally active memristive device

A method to operate an integrated circuit includes operating a locally active memristive device in a locally reactive region of an operating domain where the device exhibits inductor-like behavior, such as a phase shift where a voltage across the device leads a current through the device.

NEURISTOR-BASED RESERVOIR COMPUTING DEVICES

A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided. 1. A neuristor-based reservoir computing device comprising:support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer;input nodes connected to the support circuitry;output nodes connected to the support circuitry;thin film neuristor nodes disposed over the CMOS layer, a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes; andinterconnections between the neuristor nodes to form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes.2. The computing device of claim 1 , in which the interconnections between the neuristor nodes are parametrically random.3. The computing device of claim 1 , in which the interconnections between the neuristor nodes have parametrically random electrical resistances.4. The computing device of claim 1 , in which the neuristor nodes comprise negative differential resistance elements.5. The computing device of claim 4 , in which the neuristor nodes comprise current-controlled negative differential resistance materials.6. The computing device of claim 1 , further comprising a memristor interposed between a neuristor node and an interconnection claim 1 , the electrical resistance of the memristor determining a degree of ...

CROSSBAR MEMORY TO PROVIDE CONTENT ADDRESSABLE FUNCTIONALITY

Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar. 1. A crossbar memory to provide content-addressable functionality , the crossbar memory comprising:a first crossbar to write data values corresponding to a word;a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar;an output line, that interconnects with the crossbars at junctions, to read the data values at the junctions; anda logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.2. The crossbar memory of wherein the junctions that interconnect the output line and the crossbars are memristors to store the data values across the first and the second crossbar.3. The crossbar memory of wherein the first crossbar contains binary data values that are a bitwise inverse of the data values that represent the word.4. The crossbar memory of wherein the logic module includes circuitry to read a current corresponding to the data values.5. The crossbar memory of wherein the crossbar memory includes m number of crossbars and activates data values sequentially through m−1 number of crossbars to determine whether each of the m−1 number of crossbars correspond to the data values across the first crossbar claim 1 , the data values across the first crossbar corresponding to the word.6. A method of providing content ...

DECODER CIRCUITS HAVING METAL-INSULATOR-METAL THRESHOLD SWITCHES

Decoder circuits having negative differential resistance (NDR) devices are described. In an example, a decoder circuit includes a plurality of input lines to receive select signals, a bias logic to provide a voltage bias, a plurality of output lines to provide output signals, and a plurality of metal-insulator-metal (MIM) threshold switches coupled to the plurality of input lines, the bias logic, and the plurality of output lines. Each of the plurality of MIM threshold switches operating as either a current-controlled positive or negative resistance to map an input logic state of the select signals to an output logic state of the output signals. 1. A decoder circuit , comprising:a plurality of input lines to receive select signals;a bias logic to provide a voltage bias;a plurality of output lines to provide output signals;a plurality of metal-insulator-metal (MIM) threshold switches coupled to the plurality of input lines, the bias logic, and the plurality of output lines, each of the plurality of MIM threshold switches operating as either a current-controlled positive or negative resistance to map an input logic state of the select signals to an output logic state of the output signals.2. The decoder circuit of claim 1 , wherein the plurality of MIM threshold switches comprise:a first stage having a first plurality of MIM threshold switches coupled to the bias logic and the plurality of input lines to provide logically inverted select signals with respect to the select signals; anda second stage having a second plurality of MIM threshold switches, the second plurality of MIM threshold switches coupled to the bias logic in parallel to the first stage, and coupled to the plurality of input lines, the plurality of output lines and the first stage to receive the inverted select signals.3. The decoder circuit of claim 2 , wherein the second plurality of MIM threshold switches logically provide a plurality of AND gates coupled to the bias logic in parallel to each other ...

Storing memory with negative differential resistance material

A memory cell includes a transistor with a first source/drain terminal spaced apart from a second source/drain terminal with a semiconductor material; a gate terminal located proximate the semiconductor material such that an increase in a gate terminal voltage increases a conductivity of the semiconductor material; and the first source/drain terminal being connected in series to a negative differential resistance material.

METAL-INSULATOR PHASE TRANSITION FLIP-FLOP

A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device. 1. A metal-insulator phase transition (MIT) flip-flop comprising:a metal-insulator phase transition (MIT) device having current-controlled negative differential resistance (CC-NDR) to provide a pair of bi-stable operating states, the bi-stable operating states being separated from one another on a current-voltage (I-V) characteristic of the MIT device by a CC-NDR region of the I-V characteristic,wherein a bi-stable operating state of the pair is capable of being selected by a programing voltage, and wherein once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device, the selected bi-stable operating state representing a logic state of the MIT flip-flop.2. The metal-insulator phase transition (MIT) flip-flop of claim 1 , further comprising a multiplexer to select between a data input of the MIT flip-flop and a bias voltage source claim 1 , the data input providing a voltage comprising the programing voltage.3. The metal-insulator phase transition (MIT) flip-flop of claim 2 , wherein the multiplexer comprises a switch and a bias resistor claim 2 , the switch to connect the MIT device to the data input when the switch is ON claim 2 , the bias resistor to provide the bias voltage to the MIT device when the switch is OFF.4. The metal-insulator phase transition (MIT) flip-flop of claim 1 , wherein the MIT device is ...

Method and circuit for switching a memristive device

A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Shiftable memory employing ring registers

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

METAL-INSULATOR PHASE TRANSITION FLIP-FLOP

A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device. 1. A metal-insulator phase transition (MIT) flip-flop comprising:a metal-insulator phase transition (MIT) device having current-controlled negative differential resistance (CC-NDR) to provide a pair of bi-stable operating states, the bi-stable operating states being separated from one another on a current-voltage (I-V) characteristic of the MIT device by a CC-NDR region of the I-V characteristic,wherein a bi-stable operating state of the pair is capable of being selected by a programing voltage, and wherein once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device, the selected bi-stable operating state representing a logic state of the MIT flip-flop.2. The metal-insulator phase transition (MIT) flip-flop of claim 1 , further comprising a multiplexer to select between a data input of the MIT flip-flop and a bias voltage source claim 1 , the data input providing a voltage comprising the programing voltage.3. The metal-insulator phase transition (MIT) flip-flop of claim 2 , wherein the multiplexer comprises a switch and a bias resistor claim 2 , the switch to connect the MIT device to the data input when the switch is ON claim 2 , the bias resistor to provide the bias voltage to the MIT device when the switch is OFF.4. The metal-insulator phase transition (MIT) flip-flop of claim 1 , wherein the MIT device is ...

WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM)

Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell. 1. A word shift static random access memory (WS-SRAM) cell comprising:a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data;a dynamic/static (S/S) mode selector to selectably switch the WS-SRAM cell between a dynamic storage mode and a static storage mode, the D/S mode selector comprising a switch to selectably couple and decouple the pair of cross-coupled elements of the SRAM cell; anda column selector to selectably determine whether or not the WS-SRAM cell accepts data shifted from an adjacent memory cell during the dynamic storage mode,wherein the dynamic storage mode corresponds to decoupled cross-coupled elements and the static storage mode corresponds to coupled cross-coupled elements.2. The WS-SRAM cell of claim 1 , wherein the cross-coupled elements comprise a first inverter cross-coupled to a second inverter claim 1 , and wherein the switch comprised a first transistor switch connected between an output of the first inverter and an input of the second inverter claim 1 , and a second transistor switch connected between an output of the second inverter and an input of the first inverter claim 1 , and ...

Demodulating a signal from intermittently illuminated region

A system may intermittently illuminate a region, detect light from the intermittently illuminated region to form a detected signal, and process the detected signal with a demodulator. The demodulator may include a capacitor having an input to receive the detected signal, a resistor having an input connected to an output of the capacitor at a connection point, and a switch that connects the connection point to ground during times when the region is not illuminated. An output of the resistor may produce an output signal that is a high-pass filtered version of the detected signal during times when the region is illuminated, and a time-invariant ground signal during times when the region is not illuminated. Such a demodulator may reduce the effects of low-frequency noise sources, such as background light, op-amp offsets related to input bias, photodiode 1/f noise and dark current.

Neuristor-based reservoir computing devices

A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.

MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME

Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes. 120-. (canceled)21. A memristor forming a rectifier , comprising:a first electrode;a second electrode; anda junction disposed between the first and second electrodes, wherein the junction includes a layer, the layer having a gradient in dopant distribution from the first electrode to the second electrode to form the rectifier.22. The memristor of claim 21 , wherein a region having a relatively high dopant concentration forms an Ohmic-like barrier in contact with an electrode and wherein a region having a relatively low dopant concentration forms a Schottky-like barrier in contact with an electrode.23. The memristor of claim 22 , wherein the region of relatively low dopant concentration in contact with the first electrode and the region of relatively high dopant concentration in contact with the second electrode form a forward rectifier.24. The memristor of claim 22 , wherein the region of relatively high dopant concentration in contact with the first electrode and the region of relatively low dopant concentration in contact with the second electrode form a reverse rectifier.25. The memristor of claim 22 , wherein a first region of relatively high dopant concentration in contact with the first electrode claim 22 , a second region of relatively high dopant concentration in contact with the second electrode claim 22 , and a region of relatively low dopant concentration between the two regions of relatively high dopant concentration form a shunted rectifier.26. The memristor of claim 22 , wherein a first region of ...

FREQUENCY DOMAIN ADAPTIVE MOTION CANCELLATION FILTER

Various systems and methods for implementing frequency domain adaptive motion cancellation filters. An example method includes receiving an optical signal representative of a physiological function. The example method further includes receiving a motion signal from an accelerometer. From the motion signal, a known motion spectrum is expressed as a sum of a product of coefficients for each component of the motion spectrum, wherein the coefficients are representative of the strength of the coupling between the motion signal and the optical signal. The example method may further include determining the coefficients of the motion spectrum using gradient descent and generating a decontaminated optical signal based on the optical signal and the motion model spectrum. Other systems, apparatuses, and methods are described. 125-. (canceled)26. An apparatus comprising:an accelerometer configured to provide a motion signal representative of motion by a user wearing the apparatus;an optical sensor; and receive an optical signal representative of a physiological function from the optical sensor;', 'receive a motion signal from the accelerometer;', 'evaluate a motion spectrum, based on the motion signal, expressed as a sum of a product of coefficients for axial components of the motion spectrum to generate an expression of a motion model;', 'solve an objective function to determine values for the coefficients, wherein the coefficients are representative of the strength of motion signal coupling to the optical signal, to generate the motion model; and', 'generate a decontaminated signal based on the motion model and the optical signal., 'one or more processors to'}27. The apparatus of claim 26 , wherein the one or more processors are further configured to:provide the decontaminated signal for processing to detect a parameter of the physiological function.28. The apparatus of claim 26 , wherein solving the objective function includes implementing gradient descent.30. The apparatus ...

Memristive programmable frequency source and method

A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Storing memory with negative differential resistance material

A memory cell includes a transistor with a first source/drain terminal spaced apart from a second source/drain terminal with a semiconductor material; a gate terminal located proximate the semiconductor material such that an increase in a gate terminal voltage increases a conductivity of the semiconductor material; and the first source/drain terminal being connected in series to a negative differential resistance material.

Memristor having a triangular shaped electrode

A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode.

Storing memory with negative differential resistance material

A memory cell includes a transistor with a first source/drain terminal spaced apart from a second source/drain terminal with a semiconductor material; a gate terminal located proximate the semiconductor material such that an increase in a gate terminal voltage increases a conductivity of the semiconductor material; and the first source/drain terminal being connected in series to a negative differential resistance material.

Method and circuit for switching a memristive device

A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Memory devices with in-bit current limiters

A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided.

Memristive switch device

A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.

Shiftable memory employing ring registers

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Decoder circuits having metal-insulator-metal threshold switches

Decoder circuits having negative differential resistance (NDR) devices are described. In an example, a decoder circuit includes a plurality of input lines to receive select signals, a bias logic to provide a voltage bias, a plurality of output lines to provide output signals, and a plurality of metal-insulator-metal (MIM) threshold switches coupled to the plurality of input lines, the bias logic, and the plurality of output lines. Each of the plurality of MIM threshold switches operating as either a current-controlled positive or negative resistance to map an input logic state of the select signals to an output logic state of the output signals.

Memristive junction with intrinsic rectifier

A memristive junction (400) can comprise a first electrode (102) and second electrode (104), with a memristive region (106) situated between them. The memristive region is configured to switch between two activation states via a switching voltage (118) applied between the electrodes. The activation state can be ascertained by application of a reading voltage between the first electrode and second electrode. The junction further comprises a rectifier region situated at an interface (420) between the first electrode and the memristive region, and comprising a layer (402) of temperature-responsive transition material that is substantially conductive at the switching voltage and substantially resistive at the reading voltage.

Memristor Having a Triangular Shaped Electrode

A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode.

Testing a nonvolatile circuit element having multiple intermediate states

A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

Memristive junction with intrinsic rectifier

Metal-insulator transition switching devices

Memory array with metal-insulator transition switching devices

A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series with an MIT material. A method of accessing a target memory element within a memory array includes applying half of an access voltage to a row line connected to the target memory element, the target memory element comprising a switching layer in series with an MIT material, and applying an inverted half of the access voltage to a column line connected to the target memory element.

Shiftable memory

A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

Internal gettering by metal alloy clusters

The present invention relates to the internal gettering of impurities in semiconductors by metal alloy clusters. In particular, intermetallic clusters are formed within silicon, such clusters containing two or more transition metal species. Such clusters have melting temperatures below that of the host material and are shown to be particularly effective in gettering impurities within the silicon and collecting them into isolated, less harmful locations . Novel compositions for some of the metal alloy clusters are also described.

Internal gettering by metal alloy clusters

The present invention relates to the internal gettering of impurities in semiconductors by metal alloy clusters. In particular, intermetallic clusters are formed within silicon, such clusters containing two or more transition metal species. Such clusters have melting temperatures below that of the host material and are shown to be particularly effective in gettering impurities within the silicon and collecting them into isolated, less harmful locations . Novel compositions for some of the metal alloy clusters are also described.

Two terminal memcapacitor device

Device having memristive memory

A device ( 10 ) may include a semiconductor layer section ( 25 ) and a memory layer section ( 45 ) disposed above the semiconductor layer section ( 25 ). The semiconductor layer section ( 25 ) may include a processor ( 12; 412 ) and input/output block ( 16; 416 ), and the memory layer section ( 45 ) may include memristive memory ( 14; 300 ). A method of forming such device ( 10 ), and an apparatus ( 600 ) including such device ( 10 ) are also disclosed. Other embodiments are described and claimed.

Shiftable memory supporting atomic operation

A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Shiftable memory employing ring registers

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Shiftable memory supporting atomic operation

Word shift static random access memory (WS-SRAM)

Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.

Shiftable memory supporting atomic operation

A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Cache line eviction based on write count

A method of shielding a memory device ( 110 ) from high write rates comprising receiving instructions to write data at a memory container ( 105 ), the memory controller ( 105 ) composing a cache ( 120 ) comprising a number of cache lines defining stored data, with the memory controller ( 105 ), updating a cache line in response to a write hit in the cache ( 120 ), and with the memory controller ( 105 ), executing the instruction to write data in response to a cache miss to a cache line within the cache ( 120 ) in which the memory controller ( 105 ) prioritizes for writing to the cache ( 120 ) over writing to the memory device ( 110 ).

Shiftable memory

A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.