Design method of metal grid structure horn antenna

A design method for a horn antenna with a metallic grid structure is characterized in that the following steps are comprised: (1) the operating wavelength of the designed horn antenna is determined; (2) a horn antenna with an ordinary rectangular cross section is selected; (3) a flange structure is designed by adopting a CST software; (4) the designed flange is welded on a port of the horn; (5) the metallic grid structure is designed by using the CST software; (6) the designed metallic grid structure is embedded into a foamed material to constitute a metallic foamed material with the metallic grid located in the center of the foamed material; (7) the two layers of designed metallic foamed material are combined together; (8) the acquired metallic foamed material is arranged on the top of the flange, thus finishing the design of the horn antenna with the metallic grid structure. By adding the metallic grid structure at the horn opening, the antenna designed by the invention greatly improves ...

Plastic copied sub-wavelength grating guided mode sympathetic vibration false proof mark and making method thereof

The sub-wavelength grating guided mode resonance anti-fake mark for plastic notebook consists of plastic notebook base, visible pattern, and anti-fake mark area with text and graph and covering layer. It features that the anti-fake mark area has anti-fake text and/or graph visible in certain direction and constituted with sub-wavelength waveguide gratings of different length and distributed densely. Owing to the guided mode resonance of the sub-wavelength waveguide gratings to some wavelength of incident light, bright monochromic anti-fake text and graph may be seed in the front side of the plastic notebook. The guided mode resonance is related to the refractive indexes of plastic notebook material and covering layer material, grating period, grating height and other factors, so that the anti-fake mark has complicated design and high anti-fake effect.

Three-dimensional sub wave length metallic structure lens

Wavelength or long wavelength optical contact approach nanometer photoetching optical apparatus

A device which is composed of light source, lens sets and reflector is characterized as the follows, laser is normal wavelength of long wavelength laser, lens sets are uniform lightening lens of focused spread beam in collimation, mask is metal mask which is placed at uniform lightening position and has distance of 0.005-1000 micron m to high resolution ratio resist layer below it. The present invention uses laser in wavelength of 193-1000 nm to shine metal mask for exciting plasma at surface of metal mask to outshoot small diverging angle light used for photoetching through plasma wave propagation.

Apparatus for implementing non-mask surface plasma interference photolithography by using Lloyd lens

The invention relates to a device of realizing the interference photolithography of a maskless surface plasma body through a laue mirror. The device comprises a precision turntable capable of adjusting the incident light angle, a rectangular dove prism capable of coupling and exciting the surface plasma body interference, a compressing device capable of compressing a substrate and the rectangular dove prism, and a support capable of fixing the compressing device. One side face of the rectangular dove prism is fixed on the precision turntable; a P polarized laser beam reaches the inclined plane in a mode of vertical incidence; and the precision turntable is adjusted finely to determine the real resonance angle for exciting the surface plasma body. The substrate coated with photoresist is arranged on the bottom surface of the prism; and the compressing device is adjusted so as to compress the prism and the substrate. A wide beam reaches the prism in a mode of incidence with the real resonance ...

Simulation algorithm for synthetic aperture imaging process

The invention provides a simulation algorithm for a synthetic aperture imaging process, which comprises the following steps: a preprocessing step, a supersampling step, a pupil dithering step, a low-resolution image generation step, an image dithering step and a downsampling step, and is characterized in that simulation for pupil dithering and image dithering is added under the condition that the simulation efficiency is not obviously reduced; relative jitter of a lens and an imaging target in a real environment is simulated, and the influence of specific jitter on the Fourier lamination imaging quality can be more completely simulated and surveyed.

DYNAMIC P2L ASYNCHRONOUS POWER LOSS MITIGATION

Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.

Two-dimensional groove directed microstrip paster antenna

Disclosed is a two-dimensional trench-oriented micro-strip patch antenna, which is characterized in that: firstly, the operating frequency f of the patch antenna is established; secondly, the metal plate material is selected and the thickness of the metal plate is h; thirdly, a micro-strip patch antenna is arranged in the central region of the metal plate and is fed with electricity by making use of the coaxial line; fourthly, N1 ring-shaped trenches are cyclically arrayed and distributed on the exit surface of the metal plate with a cycle of P1, a depth of d1 and a width of w1; finally, N2 traditional ring-shaped trenches are cyclically arrayed and distributed outside the trenches with a cycle of P2, a depth of d2 and a width of w2, and the manufacturing is finished; and the invention adopts a theory that the trench structure modulates the surface wave in order to improve the antenna radiation performance and a theory that the ...

Multilayer film trap type SERS (Surface Enhanced Raman Scattering) biosensor and preparation method and application thereof

The invention discloses a multilayer film trap type SERS (Surface Enhanced Raman Scattering) biosensor as well as a preparation method and application thereof. The biosensor comprises a substrate; the trap structures are formed on the surface of the substrate and provided with central columns and annular traps located on the peripheries of the central columns; the multilayer film comprises a first metal layer, a dielectric layer and a second metal layer, is formed on the surface of the substrate and at least covers the surface of the central column and the surface of the annular trap of the trap structure; the multilayer film trap type SERS biosensor is configured to be capable of generating a Raman spectrum corresponding to a virus to be detected under the excitation of incident light of the Raman spectrometer. The preparation method comprises the following steps: providing a substrate, and forming a plurality of trap structures on the substrate; and forming a multi-layer film on the surface ...

Dual-function regulation and control device and rotation regulation and control method

The invention provides a dual-function regulation and control device and a rotation regulation and control method, and relates to the technical field of micro-nano optics, and the device comprises a first metasurface element and a second metasurface element which are cascaded and are arranged on the same optical axis. The surfaces of the first metasurface element and the second metasurface element both comprise a plurality of metasurface unit column structures. And the phase distribution of the first metasurface element and the second metasurface element is related to the size and deflection angle value of the plurality of metasurface unit column structures. Wherein the first metasurface element and the second metasurface element are configured to perform phase joint regulation and control and output an image with a focal length when receiving the left-hand circular polarization incident light. The first metasurface element and the second metasurface element are configured to perform phase ...

Metal membrane lens including nano seam

Light sail construction method and light sail

The invention provides a light sail construction method and a light sail, and relates to the technical field of light sails, the surface of the light sail is provided with a super-structure surface structure, and the method comprises the following steps: on the basis of a coordinate system taking the geometric center point of the super-structure surface structure as the origin of coordinates, constructing a light sail; determining phase distribution of each position of the characterization metasurface structure after regulation and control of incident polarized light in the x direction and phase distribution of each position of the characterization metasurface structure after regulation and control of incident polarized light in the y direction, and obtaining target phase distribution; obtaining phase values of the plurality of alternative metasurface units with different geometric parameters after the alternative metasurface units regulate and control the incident x-direction polarized ...

Read retry with targeted auto read calibrate

Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation ...

MULTI-PAGE PARITY PROTECTION WITH POWER LOSS HANDLING

A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group. 1. A memory system comprising: a metadata region for data written to the data page; and', 'a flag region allocated in the metadata region to identify one or more other data pages with the one or more other data pages impacted by an asynchronous power loss event, the one or more other data pages preceding the data page in an order of writing data to the data pages of the parity group., 'multiple parity groups arranged for data protection of the memory system, the multiple parity groups including a parity group having multiple data pages in which to write data and having a parity page in which to write parity data generated from the data written in the multiple data pages, each data page of the multiple data pages of the parity group including2. The memory system of claim 1 , wherein asynchronous power loss status of the one or more data pages includes an asynchronous power loss impacted status in which completion of a write operation of the data to a preceding data page in the order is prevented.3. The memory system of claim 1 , comprising:a memory controller including processing circuitry having one or more processors, the memory ...

Method for preparing multilayer raised compound film

The invention relates to a method for preparing a multilayer raised compound film and is characterized in that slits for passing deposited particles are manufactured on a mask; the slits of the mask are moved in the process of film material deposition to enable deposition areas to move on a substrate; the thickness of the film deposited in each area is controlled through controlling the time of deposition in each area of the substrate to condition the distribution of the thickness of the film; and the multilayer film with different film material and thickness distributions is continuously deposited in the same area of the substrate to obtain the multilayer raised compound film. The invention has the advantage of wide application prospect in the preparation of micro/nano raised structures.

RECOVERY OF MEMORY FROM ASYNCHRONOUS POWER LOSS

Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page. 1. A storage system comprising:at least one non-volatile memory device comprising multiple memory cells organized in physical pages; and in response to a detected asynchronous power loss (APL) at the storage system, determine a number of zeros stored in a first physical page of memory cells; and', 'determine whether to write dummy data to the first physical page using the determined number of zeros in the first physical page., 'a controller coupled to the at least one non-volatile memory device, wherein instructions are stored in the storage system, wherein the instructions, when executed by the controller, cause the controller to perform operations, comprising2. The storage system of claim 1 ,wherein, in response to the detected APL, the controller is configured to detect one or more fake programmed pages, wherein the first physical page is a detected fake programmed page.3. The storage system of claim 1 ,wherein the controller is configured to detect, upon resuming operation from a low-power state, if such low-power state was an APL.4. The storage system of claim 1 ,wherein each memory cell of the first physical page of memory cells comprises a lower page (LP), an upper page (UP), and an extra page (XP),wherein, to determine the number of zeros stored in the first physical page of memory cells, the controller is configured to determine the number of zeroes stored in the XPs of the memory cells of the first physical page of memory cells, andwherein, to determine whether to write dummy data to the first physical page, the controller is configured to determine whether to write dummy data to the XPs of memory cells of the first physical page of memory cells.5. The storage ...

Method for improving super-diffraction lithographic resolution and lithographic quality by utilizing island-type structure mask

The invention relates to a method for improving super-diffraction lithographic resolution and lithographic quality by utilizing an island-type structure mask. The method is characterized by comprising the following steps: firstly preparing an island-type raised structure on a mask base; then sputtering a shading film layer; and utilizing a direct-writing means to process nano patterns on the shading film layer. By utilizing the method, the resolution and lithographic pattern quality of the lithographic material pattern structure obtained by super-diffraction lithography are improved when the characteristic size of the pattern structure of the mask is less than lambda/2.

Deep ultraviolet projection photoetching object lens

The invention relates to a deep ultraviolet projection photoetching object lens, which comprises a constant-temperature sealing coat on an outer layer, an intermediate layer and an inner layer structure, wherein the intermediate layer is a lens barrel formed by connecting a first lens barrel and a second lens barrel through a connecting piece; the inner layer is a lens frame assembly comprising ten optical lens elements and ten separately fixed optical lens elements; an optical system consisting of the ten optical lens elements is a dual telecentric system; resolution reinforcing components are arranged among the ten optical lens elements of the inner layer and divide the ten optical lens elements into a front group of object lenses and a rear group of object lenses; the front group of the object lenses consist of the first to the fourth lenses, and the rear group of the object lenses consist of the fifth to the tenth lenses; and diaphragm surfaces of the resolution reinforcing components ...

Method for detecting staphylococcus aureus enterotoxin by nanostructured composite metal

The invention discloses a method that detects Staphylococcus aureus enterotoxin by a composite nano metal structure, which comprises the following steps: (1) a substrate is chosen and cleaned, and a polystyrene nano-sphere layer is self-assembled on the substrate; (2) the produced self-assembled polystyrene nano-sphere layer is taken as a die, and a silver film and a gold film are vapor-depositedon the self-assembled layer through a vapor deposition method; (3) the self-assembled polystyrene nano-sphere layer is removed through a Lift-off technique, and the nano metal array structure is obtained after array transformation; (4) the nano metal layer is activated by adopting a non-directional covalent connection method, and a biological molecular film layer that resists SE sheep monoclonal antibodies IgG is formed on the surface of the nano metal structure; (5) extinction spectrum of the nano metal structure is extracted by a spectrograph, and an extinction spectrum peak before the biological ...

Multi-page parity protection with power loss handling

A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

MULTIPLE MEMORY DEVICES HAVING PARITY PROTECTION

A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed. 1. A system comprising:a processing device;multiple memory devices, each memory device including an array of memory cells organized into one or more planes, the multiple memory devices organized into multiple blocks, each block having multiple pages with each page having a different portion of the page in a portion of each plane of the one or more planes of the multiple memory devices;a buffer; and program a page in a block of the multiple blocks by programming data in each portion of each plane of the one or more planes of the multiple memory devices mapped to the page;', 'generate a parity for the data programmed in the page;', 'store the parity in the buffer, the buffer configured to hold parity data;', 'transfer the parity data from the buffer to a temporary block in response to a determination that a transfer criterion is satisfied, the temporary block being a block of the multiple blocks; and', 'conduct, after a closing of the block, a verification of the block with respect to data errors., 'firmware having stored instructions, executable by the processing device, to perform operations, the ...

Label-free biochemical detection method reinforced by utilizing local surface plasma

A label-free biochemical detection method reinforced by utilizing local surface plasma is characterized in that the label-free biochemical detection method comprises the steps as follows: (1) preparing an LSPR detection chip according to a detected object; (2) selecting a specific biological molecule to activate the chip according to the detected object, and testing the spectrum reference value of the chip by a spectrum test system; (3) leading in a to-be-detected sample for detection, and obtaining a spectrum curve by test; and (4) judging whether the to-be-detected sample contains the detected object by analysing the spectral peak movement state of the spectrum, so as to quickly detect the detected object with high sensitivity and without a label, meanwhile, the array chip is used for realising high-efficiency and multi-channel detection. The method of the invention does not need complex equipment and does not use radioactive isotope, enzyme or fluorescence as a label, has the remarkable ...

Sub-wavelength continuous surface micro-structure preparation method based on negative refractive rate lens

The invention is a sub-wavelength continuous surface micro-structure manufacturing method based on lens of negative refraction index. (1) making quantitative decomposition of the object structure and manufacture a half-tone photoengraved mask of graphic size in nanometer; (2) painting photoresist on the surface of a substrate, a spacing layer on the substrate surface of photoresist solvent and coat a metal layer of 10nm to120nm thickness on the surface of the spacing layer; (3) painting a gap layer on the surface of the metal layer and tightly press the half-tone photoengraved mask to be manufacture to the surface of the gap layer; (4) irradiating the incoming light vertically to the surface of the half-tone mask and achieve the exposure of photoresist; (5) after exposure, eliminating thegap layer and the metal layer and conduct developing of photoresist so as to get the required continuous surface structure. The invention achieves the sub-wavelength continuous surface micro-structure manufacturing ...

High resolution micro-three-dimensional image forming apparatus

The invention relates to a high resolution micrographic three-dimensional imaging device and the characters comprise the following steps: people firstly confirm a irradiating inlet light, then choosea proper hemisphere prism, choose a glass slide the surface of which is vapor deposited with a layer of metal on the hemisphere plane of the hemisphere prism, the objects are put on the metal layer soas to lead the irradiating inlet light to irradiate on a certain point on a prism hemisphere curved surface along the prism radius direction, the included angle of between the irradiating inlet lightand the glass slide plane is Theta; a beam of light generates complete reflection on the surface of the glass slide; a TM wave generates a surface plasma wave on the metal surface through the complete reflection; the TE wave is reflected; people put a Lambada/4 wave and a reflector on the reflecting path out of the hemisphere prism; people put the detector on the upper part of the objects so as to proceed ...

Method for preparing super-resolution imaging lens with planar zooming magnification

The invention provides a method for preparing a super-resolution imaging lens with planar zooming magnification, comprising the following steps: preparing a circular or square or rectangular flat-bottom groove on a substrate; depositing a silver film layer on the substrate, then coating a cured sol layer on the silver film layer, wherein the sol layer can form an arc surface at the position of the groove under the action of surface tension, and the sol layer is cured after being heated or ultraviolet-irradiated; and so forth, depositing the silver film layers alternatively on the substrate, coating and curing the sol layers, obtaining a plurality of arc-surface film layers formed by a plurality of silver film layers and the sol layers in an alternative manner at the groove position till the groove is filled, and then obtaining the super-resolution imaging lens with planar zooming magnification, wherein an object plane and an image plane of the lens are planes respectively. The super-resolution ...

Method for manufacturing diamond-type metal nanometer particle array structure

A preparation method for a rhombus metal nanometer particle array structure is as follows: (1) a fine polishing silicate glass is selected as a substrate and a layer of chromium with the thickness of a few nanometers is deposited on the glass surface; (2) two monodisperse polystyrene nanometer spheres with a diameter ratio of 1:2.5 is mixed by proportion; (3) the chromium plating glass plate is treated with hydrophilization by a chemical method; (4) the chromium plating glass plate is self-organized with a layer of mixing polystyrene nanometer spheres after the hydrophilization treatment; (5)an active ion etching (RIE) is applied to etch the manufactured polystyrene nanometer sphere self-organization layer, and the small diameter polystyrene nanometer spheres are completely etched; (6) the etched polystyrene nanometer sphere self-organization layer is used as a mould and the metal is filled into the clearance among the spheres; (7)the polystyrene nanometer sphere self-organization layer ...

Method for fabricating smei-cylindrical groove by shadow evaporation and wet etching

The invention relates to a method for fabricating a smei-cylindrical groove by shadow evaporation coating and wet etching, comprising the following steps: using the conventional technology to deposit a mask membrane layer on a substrate, coating photoresist on the mask membrane layer; preparing line structures on the photoresist by the photoetching technology; carrying out oblique evaporation at a certain angle; forming a bar of shadow region which is of a certain width and free from deposit evaporation material outside the edge of each photoresist line; then using evaporation material as a protection layer to carry out dry etching on the mask membrane layer, wherein the mask membrane layer at the shadow region is corroded in the absence of the protection of the evaporation material, so that a mask membrane layer slit corresponding to the shadow region is obtained; carrying out isotropic etching on the substrate by dilute hydrofluoric acid solution through the mask membrane layer slitand ...

Manufacture method of metal micro-nano structure for improving Raman scattering of molecule

The invention relates to a metal micro-nano structure for improving Raman scattering of molecule, which comprises the following steps: (1) estimating limitation of internal memory capacity of a computer; (2) determining parameters such as mesh partition, peripheral medium environment conditions and exciting light condition, and primarily determining initial parameters of the metal micro-nano structure; (3) calculating scattering property Qsca of the metal micro-nano structure; (4) calculating plasma resonant frequency gamma LSPR for simulating the metal micro-nano structure and comparing the plasma resonant frequency gamma LSPR with the system exciting light frequency gamma ex, if the plasma resonant frequency is basically equal to the system exciting light frequency, the next step is entered, and if the plasma resonant frequency is not equal to the system exciting light frequency, the parameters of the peripheral medium environment condition of the metal micro-nano structure is changed ...

Calibration method and system and computer readable storage medium

The invention belongs to the technical field of three-dimensional reconstruction, and particularly discloses a calibration method and system and a computer readable storage medium. The calibration method comprises the following steps: calibrating a camera; determining N calibration positions along the Z axis of the world coordinate system; at each calibration position, obtaining a laser dot matrix image of a laser dot matrix projected to the diffuse reflection plate at the calibration position by the dot matrix light source and a checkerboard image arranged at the calibration position, and calculating a transformation matrix from an XY plane to a pixel coordinate system of the camera by using the checkerboard image and an internal reference matrix and a distortion coefficient of the camera; converting the laser dot matrix image from a pixel coordinate system to a camera coordinate system by using the laser dot matrix image and the internal reference matrix, the distortion parameter and ...

Polarization adjusting assembly, polarization imaging device and polarization imaging method

The invention belongs to the technical field of polarization imaging, and particularly relates to a polarization adjusting assembly, a polarization imaging device and a polarization imaging method. From an object side to an image side, the polarization imaging device sequentially comprises an imaging lens group which is located in front of a focal plane of an imaging detector and used for focusing light rays on the focal plane of the imaging detector, and a polarization adjusting assembly which is used for adjusting the polarization direction of the light rays emitted from the imaging assembly and comprises a first polarization grating, a second polarization grating and a linear polarizer, the polarization adjusting assembly is used for carrying out polarization filtering on light emitted from the polarization adjusting assembly, the imaging detector is used for obtaining image information of a to-be-imaged object, and the controller is used for controlling the imaging detector to obtain ...

Method for preparing semicylindrical superfine slot by combining twice membranous layer deposition, dry etching and wet etching

The invention provides a method for preparing a semicylindrical superfine slot by combining twice membranous layer deposition, dry etching and wet etching. The method comprises the following principal steps of: preparing a sheltering membranous layer having a nano slit on a quartz substrate; and through the slit, performing isotropic etching on the quartz substrate by using hydrofluoric acid buffer solution so as to obtain the semicylindrical superfine slot. By the method, the slit with the width of 100 to 500 nanometers can be formed without expensive equipment such as electronic beams, ion beams and the like, and the semicylindrical superfine slot with the with of 500 nanometers to 2.5 microns and the depth of 250 nanometers to 1.25 microns can be prepared by controlling the conditions of wet etching.

Deep ultraviolet projection lithographic objective

The invention relates to a deep ultraviolet projection lithographic objective, which comprises a constant temperature sealing jacket of an outer layer, an intermediate layer and an inner layer; the intermediate layer is a lens barrel which consists of a first lens barrel and a second lens barrel connected by a connecting piece; the inner layer is ten optical lens elements and ten lens frame components for separating and fixing the optical lens elements; an optical system consisting of the ten optical lens elements is a double-telecentric system; a resolution enhancement component is arranged between the ten optical lens elements of the inner layer, and divides the ten optical lens elements into two groups of objectives forward and back; the front group of objectives consist of a first lens, a second lens, a third lens and a fourth lens, and the back group of objectives consist of a fifth lens, a sixth lens, a seventh lens, an eighth lens, a ninth lens and a tenth lens; and the diaphragm ...

RECOVERY OF MEMORY FROM ASYNCHRONOUS POWER LOSS

Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page. 1. A storage system comprising:at least one non-volatile memory device comprising multiple memory cells organized in physical pages, each memory cell comprising multiple pages, including a lower page (LP), an upper page (UP), and an extra page (XP); and in response to a detected asynchronous power loss (APL) at the storage system, determine a number of zeros stored in the XPs of a first physical page of memory cells; and', 'determine whether to write dummy data to the first physical page using the determined number of zeros in the XPs of the first physical page., 'a controller coupled to the at least one non-volatile memory device, wherein instructions are stored in the storage system, wherein the instructions, when executed by the controller, cause the controller to perform operations, comprising2. The storage system of claim 1 ,wherein, in response to the detected APL, the controller is configured to detect one or more fake programmed pages, wherein the first physical page is a detected fake programmed page.3. The storage system of claim 1 ,wherein the controller is configured to detect, upon resuming operation from a low-power state, if such low-power state was an APL.4. The storage system of claim 1 ,wherein, to determine the number of zeros stored in the XPs of the memory cells of the first physical page of memory cells, the controller is configured to read the values stored in the XPs of the first physical page of memory cells.5. The storage system of claim 1 ,wherein, to determine whether to write dummy data to the first physical page, the controller is configured to compare the determined number of zeros stored in the XPs of the first physical page to a threshold, ...

Methods and apparatuses for coating photoresist

The present disclosure proposes an apparatus for coating photoresist and a method for coating photoresist. The apparatus for coating photoresist comprises a gas supply unit (10) configured to supply gas to a photoresist application unit (20); wherein the photoresist application unit (20) comprises: a device cavity (202) enclosed by sidewalls, a bottom plate and a cover plate (206), a rotation platform (204) configured to carry a substrate (205) and bring the substrate to rotate; a guide unit conformal with the substrate, and configured to uniformly blow the gas supplied by the gas supply unit over a surface of the substrate on which the photoresist is coated; and a gas extraction unit (203) configured to extract gas from the device cavity (202). The present disclosure realizes uniformly and rapidly coating the photoresist on a large substrate.

Laser beam scanning system debugging method

The invention belongs to the technical field of optical systems, and particularly relates to a laser beam scanning system debugging method which comprises the following steps: controlling a laser light source to generate incident laser, and enabling the incident laser to sequentially pass through a first lens and a second lens included in a laser beam scanning system and then be projected to a target surface to form a pattern; adjusting the size of the clear aperture of the first lens to form a zero-order pattern on the target surface; adjusting the size of the clear aperture of the first lens to form a non-zero-order pattern on the target surface; according to the zero-order pattern and the non-zero-order pattern, the position of the second lens is adjusted until the preset condition that the laser beam scanning system completes debugging is met; wherein the preset condition comprises that the central point of the zero-order pattern coincides with the central point of the non-zero-order ...

Surface plasmon imaging lithography method for processing nano graphic with high aspect ratio

The invention relates to a surface plasmon imaging lithography method for processing a nano graphic with a high aspect ratio, which comprises the following steps: using a composite mask of surface plasmon imaging lithography and a substrate with a three-layer photoresist structure for contact exposure, realizing imaging lithography of a pattern with a nano-scale linewidth on a very thin surface photoresist film through developing, and further transmitting the pattern to bottom photoresist through two-step etching, wherein the photoresist pattern can reach 100-500nm. The method overcomes the technical defects of shallow pattern depth and low contrast of the surface plasmon imaging lithography in the traditional technical report, realizes the lithography of the nano-linewidth pattern with a high aspect ratio, can be applied in processing of nano photoresist patterns with the linewidth being 20-500nm, and can also be widely applied in various fields such as processing of electronic integrated ...

Multilayer material and preparation method

The invention provides a multi-layer material and a preparation method, the multi-layer material comprises a flexible support layer, the flexible support layer is provided with gaps, and water vapor can penetrate through the flexible support layer; a first porous layer and a second porous layer are oppositely arranged on the two sides of the flexible supporting layer; the first porous layer and the second porous layer are of non-compact structures and have graded pore structures, and the graded pore structures comprise nano-pore structures and micron-pore structures; the first porous layer and the second porous layer have infrared emissivity and sunlight reflectivity, the infrared emissivity is larger than or equal to 95%, the sunlight reflectivity is larger than or equal to 95%, the corresponding preparation method is provided, the material has high infrared emissivity and high sunlight reflectivity, good radiation refrigeration performance is provided for the material through combination ...

Image acquisition device

The invention belongs to the technical field of imaging, and particularly discloses an image acquisition device which comprises an image acquisition unit used for acquiring an image of a to-be-imaged target; the movement mechanism is used for installing the image acquisition unit and driving the image acquisition unit to move; the control unit is in communication connection with the image acquisition unit and the movement mechanism and is used for controlling the movement mechanism to drive the image acquisition unit to move according to a preset path so as to acquire images of the to-be-imaged target at a plurality of shooting points; the preset path meets the following conditions: the image acquisition unit moves to each shooting point in the same direction to acquire an image of the to-be-imaged target; when the image acquisition units are located at the adjacent shooting points, the areas where the pupils are located are partially overlapped. According to the image acquisition device ...

Lithography mask and optical lithography method using surface plasmon

A periodic structure for producing surface plasmon resonance as a result of coupling surface plasmon with light is formed on a side to which the light is to be input, while a fine structure having a periodically or aperiodically arbitrary shape is formed opposite to the periodic structure in order that a pattern a dimension of which is a half or less than a wavelength of light can be transferred to a resist without requiring closely contact of the resist with a mask, or an exposure for a long period of time unlike near field lithography. An electric field transmission layer may be formed between the periodic structure and the fine structure, and the fine structure may be formed on the electric field transmission layer.

Warm-up flash two-purpose nano impression device

The stamping apparatus is composed of CCD alignment system in two way, corrector in Z direction, illumination system in purple light, left and right side plates, oil pressure lifting jack system, heating desk for loaded piece, slant correcting mechanism and control system. Large base plate of host is on equipment cabinet. The large base plate, left and right side plates, backboard and upper transverse plate constitute frame. Corrector in Z direction and slant correcting mechanism with press mold are hung underside of the transverse plate. Oil lifting jack system faced to the press mold is installed at middle. XYtheta micromotion work desk, the heating desk, substrate is lifted by jack system to impact the mold to stamp out Nano graph structure. Illumination system in purple light illumines polymer in stamping layer to solidify it. Heating up and cooling down heating desk solidifies and demoulds the polymer. The invention possesses advantages of two stamping methods.

MEMORY DEVICE WITH CONFIGURABLE PERFORMANCE AND DEFECTIVITY MANAGEMENT

A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the PIE cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

Contact hole defect database establishment method and contact hole defect detection method and system

The invention belongs to the technical field of integrated circuits, and particularly discloses a contact hole defect database establishment method and a contact hole defect detection method and system. The contact hole defect database establishment method comprises the following steps: S1, providing a sample with a contact hole; s2, performing defect detection on the contact holes of the sample to obtain first detection information of each contact hole, and identifying the contact holes with defects through the first detection information; s3, defect category parameters are calculated through the first detection information of the contact holes with the defects; s4, performing slice sampling on the contact holes with defects, and identifying defect categories of the contact holes; and S5, establishing a contact hole defect category database according to the corresponding relationship between the defect category parameters and the defect categories. According to the method, the defect category ...

High-gain plough groove waveguide gap array microwave antenna

Gap detection system and method and focal plane correction method

The present disclosure provides a gap detection system for detecting global gap data between a template and a substrate, comprising: a support frame; the template frame comprises a focus detection module and is used for monitoring gap data between the template and the substrate in real time; the workpiece table module comprises a wafer bearing table and is used for adjusting the position and the posture of the substrate; the front facade shape detection module is used for detecting the substrate to obtain first surface shape data; the turning surface shape detection module can be switched between a detection position and an avoiding position and is used for detecting the template to obtain second surface shape data; and the control system is used for obtaining position data of the template and the substrate and calibration data of the facade shape detection module and the turning surface shape detection module, and after obtaining the inclination angle between the template and the substrate ...

Dual beam polymerization initiation and inhibition-based high resolution imaging lithography method

The invention provides a dual beam polymerization initiation and inhibition-based high resolution imaging lithography method. The method mainly comprises the following steps: 1, selecting or preparing a photoresist containing a polymerization initiator responding to laser of different wavelengths and a polymerization inhibitor; 2, selecting a corresponding polymerization initiation laser and a corresponding polymerization inhibition laser; 3, making two masks with the mask graphs having same or similar shapes and dimensions; 4, carrying out beam combination imaging on a mask 1 and a mask 2 in a same plane through a dichroic mirror and a lens under the action of polymerization inhibition and polymerization initiation laser, and allowing the obtained image to partially overlap in a space; and 5, placing a photoresist sample containing the polymerization initiator and the polymerization inhibitor on the imaging plane, and exposing and developing to obtain a high resolution imaging lithography ...

A ultrasonic device for cleaning denitration catalyst

The utility model relates to an ultrasonic device for cleaning denitration catalyst. It includes supersonic generator, supersound stick and porous ring flange. Supersonic generator connects the supersound stick, and the supersound stick is more than one or one, is parallel arrangement between the many supersound sticks, and the supersound stick inserts the downthehole of out of stock catalyst, and the supersound stick can be followed the one end or the both ends of denitration catalyst and inserted the downthehole of out of stock catalyst, and the one end of supersound stick is connected with porous ring flange. The utility model discloses clean effectual, the supersound stick gos deep into catalyst hole inside and cleans, ultrasonic wave energy distribution is even, does not have structural damage to the catalyst, the ultrasonic wave is given first place to with radial mode emitted energy, and thoroughly clean to the micropore, catalyst regeneration is of high quality, and is reliable ...

LITHOGRAPHY MASK AND OPTICAL LITHOGRAPHY METHOD USING SURFACE PLASMON

PROBLEM TO BE SOLVED: To transfer a pattern with a dimension half or less than a wavelength of light to a resist without requiring closely contact of the resist to a mask, or an exposure for a long period of time unlike near field lithography. SOLUTION: A periodic structure for producing surface plasmon resonance as a result of coupling surface plasmon with light is formed on a side to which the light is made incident, while a fine structure having a periodically or aperiodically arbitrary shape is formed opposite to the periodic structure. An electric field transmission layer may be formed between the periodic structure and the fine structure, and the fine structure may be formed on the electric field transmission layer. COPYRIGHT: (C)2006,JPO&NCIPI ...

Kyropoulos -method sapphire crystal growth furnace

The utility model discloses a kyropoulos -method sapphire crystal growth furnace, including furnace body, crucible, bell and seed rod, the furnace body is bottom confined barrel, be equipped with cylindric side heat screen in the furnace body, heat preservation and support bottom the bottom is provided with in the furnace body, the bottom reflecting screen has been placed at the top of bottom heat preservation, place on the support the crucible, the crucible is located bottom reflecting screen top, the bell bottom surface is provided with first top heat screen, center on the side heater is installed to the crucible, still be provided with the base heating ware in the furnace body. The utility model discloses an arrange to heater struvture design, heat screen that improvement and surface treatment not only can regulate and control the heater power in a flexible way and for crystal growth provides good thermal field environment, improve crystal quality, but also can show the intensive thermal ...

Surface groove structure based on surface excimer radiation mode

The invention relates to a surface groove structure based on a surface excimer radiation mode. The surface groove structure is manufactured by adopting the steps of: firstly confirming a working frequency f for realizing a beaming effect of the surface groove structure; and then selecting a metal plate material; opening a sub-wavelength aperture with a semidiameter r or a long and narrow gap with a width w at the central region of the metal plate; and then, arranging a plurality of periodic groove structures on the exit surface (or simultaneously on the incident surface and the exit surface) of the metal plate, wherein the grooves have the period gp, the depth gd and the width gw; the distance from the first groove to the center of the metal gap is gp1; in addition, medium with a permittivity epsilon and a thickness t is loaded between the adjacent metal grooves. Compared with a traditional sub-wavelength periodic groove structure, the surface groove structure provided by the invention ...

Medium loading type groove slot array antenna

The invention relates to a medium loading type groove slot array antenna, which consists of an earth plate with n*m slot array elements (the spacing of the array elements exceeds resonant wavelength on an E surface), grooves loaded on the upper surface of the earth plate, and a medium loaded on the upper surface between adjacent grooves on the earth plate; and n and m are natural numbers more than or equal to 1 (n and m cannot be 1 simultaneously). The basic principle of the antenna is that: a pair of surface groove structures is loaded symmetrically on two sides of adjacent array units on the E surface; and a groove area between the loaded adjacent array elements can be taken as an artificial radiation source to radiate surface electromagnetic energy to a free space, so that the equivalent range between the array elements is indirectly reduced. In the designed antenna, the side lobe level is compressed greatly compared with that of the traditional array antenna, and the radiation performance ...

Dynamic objective table and surface shape adjusting method

The invention provides a dynamic objective table and a surface shape adjusting method, and the dynamic objective table comprises a supporting plate which is provided with a wire channel and a vacuum channel; the surface shape control module is installed on the surface of the supporting plate and comprises a piezoelectric ceramic array and an airtight wall, and the airtight wall surrounds the piezoelectric ceramic array; wherein the piezoelectric ceramic array is composed of piezoelectric ceramic units arranged in an array mode, each piezoelectric ceramic unit is independently connected with an external circuit through an electrode wire penetrating through a wire channel, and the external circuit independently applies potential difference to the two ends of each piezoelectric ceramic unit so that the piezoelectric ceramic units can independently generate longitudinal deformation; the piezoelectric ceramic array is used for supporting a to-be-adjusted workpiece, and the vacuum channel is ...

Prioritization of error control operations at a memory sub-system

A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.

Design method for composing singular artificial composite material using period metal lines

The invention discloses a designing method by using a periodical metal wire to form a peculiar manual compound material which comprises the following steps: (1) selecting the frequency f0 of the plasma of a compound structure material; (2) selecting a proper metal wire arranging period a according to the detail design requirements; (3) proposing the following model formula (like the graph)after confirming the frequency f0 of the plasma and the metal wire arranging period a, and calculating the perimeter 1 of the cross section of the metal wire; (4) confirming the detail shape and parameters of the cross section of the metal wire according to the metal wire arranging period a and the perimeter 1 of the cross section; (5) simulating the structure parameters obtained in step (4) and authenticating whether the group of parameters is practical or not, selecting the group of parameters as the structure parameters of the metal wire if the group of parameters is practical, or returning to the step ...

Surface plasma resonance image-forming nanostructure array chip preparation method

The invention relates to a preparation method of nanostructured array chip with surface plasma for resonance imaging. The preparation method is characterized by comprising the following steps: (1) selecting and cleaning a substrate; (2) using a vacuum evaporated coating to coat a first metal film on the substrate; (3) self-assembling a layer of polystyrene nanoparticles on the metal film; (4) coating a second metal film in a way of evaporation on the self-assembled layer so as to fill the gas between balls; (5) eliminating the nanoparticles with the Lift off technology; (6) using laser direct writing machine to manufacture a lattice mask plate of the level of micron; (7) adopting the photolithography to transmit the mask figure to the substrate; (8) acquiring the lattice figure through developing and stripping of photoresist; (9) using a chemical method to eliminate the excessive metal and photoresist; thus the metal lattice chip of the cyclical nanostructure can be formed. The method adopts ...

Metasurface array structure

The invention provides a metasurface array structure, the metasurface array structure is formed by arranging a plurality of metasurface units, the metasurface units are connected in parallel and can be independently controlled, a PIN tube voltage bias line in the metasurface array structure is electrically connected with a PIN tube, and the PIN tube voltage bias line is combined into a path of PIN tube voltage total bias line to be output. Compared with an existing intelligent metasurface, the intelligent metasurface is provided with the PIN tube and the variable capacitance diode which can be regulated and controlled respectively, the variable capacitance diode changes capacitance through different applied voltages, and the effect of modulating the reflection phase of the unit can be achieved; on-off of the PIN tube can play a role in reconstructing a working frequency band, dynamic adjustability of the metasurface unit in different frequency bands under the same aperture plane can be ...

Temperature sensitive NAND programming

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

Phase-shifting filter for projecting etching imaging

The present invention relates to a projection photo-etching image phase-shifting filter equipment, consisting of light source, condenser group, imaging objective and silicon wafer, which is characterized by that on the pupil surface position of projection photo-etching objective a complete transparent phase-shifting filter plate capable of phase-shifting and filtering image light, so that it can ensure that the image light can not be blocked, and can raise image contrast, and can further raise the photo-etching resolution power of short wavelength large-aperture projection iming system, and can greately raise projection image photo-etching resolution power and increase depth of focus.

Design method of multi-layer metal dielectric film capable of implementing imaging function

A design method for multi-layer metal dielectric film capable of realizing the imaging function is characterized by selecting incident wave; selecting two sets of metallic material and dielectric material with a certain thickness, alternatively arranging the metal and medium in two sets to form two kinds of multi-layer metal dielectric film structures, respectively computing the equivalent dielectric constant of the two kinds of multi-layer metal dielectric film structures based on equivalent dielectric constant of each material and the thickness of each film layer; realizing the variation of the value and plusminus of the dielectric constant in respective direction by designing the thickness of each film layer so as to make the optical wave diverge through the first set of multi-layer metal dielectric film structure and converge through the second set of multi-layer metal dielectric film structure; binding the divergent structure multilayer film and the convergent structure multilayer ...

Temperature sensitive NAND programming

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

Standard consistency testing system and testing method thereof

The invention provides a standard consistency testing system and a testing method thereof. The system comprises a preprocessor and a postprocessor, wherein the preprocess is in charge of recording a standard and preparing for a consistency test, the postprocessor is in charge of carrying out system automatic testing, judging a result and generating a testing report on an executable testing suite generated in the preprocessor and managing a testing log and the standard; and the preprocessor and the postprocessor carry out data access through a database. The invention can test whether a tested standard meets the requirements and the specifications specified in the standard consistent with the tested standard, can conveniently and flexibly test the consistency of the traditional standards of different levels, and can store and manage the standard by the connection of the database.

Precision rotating, positioning and focusing system of nano-photon straight write head

The invention provides a precision rotating, positioning and focusing system of a nano-photon straight write head, belonging to the field of straight writing and photoetching equipment. (1) A straight write head adjusting device can move by means of nanometer level along the Z direction; (2) the straight write head adjusting device can rotate by 0-90 degrees; (3) a substrate table can rotate at a high speed; (4) a cantilever of the straight write head has a certain elastic distortion; and (5) the straight write head adopts a design structure of an aerodynamic principle to be capable of floating above the surface of a substrate under the action of an air current generated by rotating the substrate table. The straight write head can float above the surface of the substrate within the range of dozens of nanometers due to the air current generated by rotating the substrate table at a high speed, so that the distance between the straight write head and the surface of the substrate is kept to ...

Method for realizing surface plasma structure formation

The invention discloses a method to form surface plasma structure that includes the following steps: using wet method corrosion to decrease the typical line width of microstructure under mask, and forming a shadow region, taking metal coating on the surface of the structure after corroded and removing the microstructure that the line width and period are both decreased; transferring the microstructure to another film surface; repeating the above steps to gain the nanometer grade structure. The invention supplies a method to actually use nanometer structure.

Method for realizing improvement of surface plasma photoetching quality by utilizing metallic reflecting film structure

The invention relates to a method for realizing the improvement of near-field photoetching quality by utilizing a metallic reflecting film structure, which is characterized by comprising the following steps of: 1. firstly selecting a substrate material; 2. depositing a deposition layer A beneficial to metal attachment on the surface of a substrate, wherein the thickness of the deposition layer is Da; 3. depositing a metal film on the deposition layer A to form a metal layer B for exciting a surface plasma, wherein the thickness of the metal layer B is Db; 4. depositing a protecting film C on the metal layer B and using the protecting film C as a protecting layer for isolating the metal layer B and a protecting layer from contacting a corrosion resisting agent, a developing solution and the like, wherein the layer thickness of the protecting film C is Dc; 5. spin-coating the corrosion resisting agent D on the surface of the structure obtained in the previous step; 6. placing a designed periodic ...

Super-diffraction imaging device for improving resolution based on phase shifting principle and manufacturing method thereof

The invention discloses a super-diffraction imaging device for improving resolution based on a phase shifting principle and a manufacturing method thereof. Adjacent light transmission areas of the super-diffraction imaging device realize phase delay and phase advance respectively by alternately filling two materials with a positive dielectric coefficient and a negative dielectric coefficient and the phase difference modulation of the material thicknesses is enhanced greatly, so that the device is easier to realize a pi phase difference; therefore, the imaging resolution of the device is further improved. The scheme solves the technical difficult problem that a conventional super-diffraction imaging device is difficult to realize the resolution below the line width of 40 nm and has a broad application prospect in super-diffraction imaging and nano-lithography technologies.

Staphylococcal enterotoxin detection method

A staphylococcal enterotoxin detection method is characterized in that the detection method comprises the steps as follows: (1) preparing an LSPR detection chip of staphylococcal enterotoxin; (2) activating the surface of the metal structure of the chip to form a specific biological molecular membrane; (3) testing the extinction spectrum of the chip to obtain a reference value before combination; and (4) dripping a to-be-detected sample, putting the sample in an LSPR sensor for detection after the full reaction of the sample, observing spectral shift condition by using the specific reaction among antigen-antibody molecules, and judging whether the to-be-detected sample contains staphylococcal enterotoxin, so as to realize fast detection with high sensitivity and without a label. The method does not need complex equipment and does not use radioactive isotope, enzyme or fluorescence and the like as a label, and has the remarkable characteristics of quickness, high sensitivity, wide application ...

Optical system

The invention belongs to the technical field of optics, and particularly relates to an optical system, which comprises a first optical subsystem with a first imaging surface, and light from an object side can be imaged on the first imaging surface after passing through the first optical subsystem; the second optical subsystem is provided with a second imaging surface, and the light from the object side can be imaged on the second imaging surface after passing through the first optical subsystem and the second optical subsystem; the mode switching module comprises a light flux adjusting unit and a micro-nano structure unit, the light flux adjusting unit is located at the first imaging surface and used for adjusting the light flux, the micro-nano structure unit is associated with the second optical subsystem, and the optical system can be in an imaging mode or a spectrum detection mode by adjusting the micro-nano structure unit. The light flux adjusting unit has different light flux in the ...

SECONDARY IMAGING OPTICAL LITHOGRAPHY METHOD AND APPARATUS

The present disclosure provides a secondary imaging optical lithography method and apparatus. The method includes: contacting a lithography mask plate with a flexible transparent transfer substrate closely, the flexible transparent transfer substrate comprising a first near-field imaging structure having a photosensitive layer; irradiating the photosensitive layer through the lithography mask plate with a first light source, so as to transfer a pattern of the lithography mask plate to the photosensitive layer; coating a device substrate for fabricating devices with a photoresist; contacting the flexible transparent transfer substrate with the photoresist-coated device substrate closely; irradiating the device substrate through the flexible transparent transfer substrate with a second light source, so as to transfer a pattern of the photosensitive layer to the photoresist of the device substrate; and developing the device substrate comprising an exposed photoresist, so as to obtain a device pattern conforming to the pattern of the lithography mask plate. 1. A secondary imaging optical lithography method comprising:contacting a lithography mask plate with a flexible transparent transfer substrate closely, the flexible transparent transfer substrate comprising a first near-field imaging structure having a photosensitive layer;irradiating the photosensitive layer of the flexible transparent transfer substrate through the lithography mask plate with a first light source, so as to transfer a pattern of the lithography mask plate to the photosensitive layer of the flexible transparent transfer substrate;coating a device substrate for fabricating devices with a photoresist;contacting the flexible transparent transfer substrate with the photoresist-coated device substrate closely;irradiating the device substrate through the flexible transparent transfer substrate with a second light source, so as to transfer a pattern of the photosensitive layer of the flexible transparent ...

Single-feed source periodically arranged groove slot panel antenna

The invention provides a single-feed source periodically arranged groove slot panel antenna, which consists of a grounding plate and a plurality of periodically arranged groove structures loaded on two sides of a slot source, and a distance between a slot and a neighbouring groove is less than a groove period. Different from the radiation mechanism of a traditional periodically arranged groove structure, the grooves of the invention cannot be taken as a secondary radiation source any more, because the phase of an electric field at the grooves is opposite to the phase of the electric field at the slot. Another novel electromagnetic oscillation mode that two neighbouring grooves are integrally taken as the secondary radiation source which radiates energy to the space is generated on the surface of the antenna. The novel antenna has the characteristics of more compact structure and more flexible design, and is smaller in the compression angle of an H surface and antenna gain is improved to ...

Nano photoetching optical apparatus based on plasma ion wave

Projection photoetching objective lens with ultraresolution

The invention is a sort of filter projective photoetching objective lens with a super resolution ratio, it is made up of outer hermetic thermostat wrap, interface-layer's drawtube, inner lens frame module which isolating fixed optical lens components, and filter module. It has filter axial overlap function, augments focal depth, overcomes deficiency that the photoetching resolution ratio of current projective photoetching objective lens and can't draw graph with high resolution ratio, it has characters of super-high photoetching resolution ratio, big focal depth, large minification of opticalsystem, simple structure and that it reduces manufacturing difficulty and cost of super micro-masking greatly.

Photoresist coating method

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a photoresist coating method. The photoresist coating method comprises the following steps: dripping a first liquid on a first surface of a wafer, driving the wafer to rotate so as to enable the first liquid to move from a dripping point to the edge of the wafer, and taking away particulate matters on the first surface of the wafer; after the binder is sprayed on the first surface of the wafer, dripping first liquid on the first surface of the wafer again, driving the wafer to rotate to enable the first liquid to move from a dripping point to the edge of the wafer, and enabling the vapor-phase mist binder adsorbed on the surface of the silicon wafer to be uniformly laid on the first surface of the wafer through the movement of the first liquid; and finally, dripping photoresist to the center of the wafer, and driving the wafer to rotate so that the photoresist is uniformly coated ...

PRIORITIZATION OF ERROR CONTROL OPERATIONS AT A MEMORY SUB-SYSTEM

A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.

Multiple wavelength porous lens design method

Atomic beam generator

Negative refraction artificial material based on iron-clad

The invention relates to a negative refraction artificial material based on a metal covering layer, which comprises the following steps that (1) a quartz basal piece is selected, the surface of the quartz basal piece is polished, and then, a high-purity SiO2 film is evaporated and plated on the surface of the quartz basal piece; (2) the surface of a high-purity SiO2 film is evaporated and plated with a chrome film, and a layer of photoresist is evenly coated on the high-purity SiO2 film; (3) an electron beam photoetching method is adopted, and a medium grating structure is prepared on the photoresist; (4) a wet etching technology is adopted, the photoresist is used as a mask, and the exposed chrome film is etched; (5) a dry etching technology is adopted, the chrome film is used as the mask, the medium grating structure is etched on the high-purity SiO2 film, and the chrome film is removed; (6) a vacuum evaporation technology is adopted, a metal layer is evaporated and plated on the SiO2 ...

Self-cleaning adjustable heat management film

The invention provides a preparation technology and method of a self-cleaning adjustable heat management film for buildings based on a spectrum regulation and control technology, and the technical scheme of the invention is as follows: the self-cleaning adjustable heat management film comprises a macromolecular base film, the interior of the macromolecular base film is provided with a microporous structure, and the surface of the macromolecular base film is provided with a convex structure; the thickness of the macromolecular base film is 0.5 to 2 mm; and the thermochromic particles are distributed in the macromolecular base membrane. The system aims to absorb sunlight for heating in a cold environment and radiate for refrigeration and cooling in a hot environment, so that a proper indoor temperature is kept, the power consumption of an environment temperature control system such as a heater and an air conditioner is reduced, energy conservation and emission reduction are achieved, and ...

VARIABLE READ ERROR CODE CORRECTION

Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum. 1. A controller for variable read error code correction (ECC) , the controller comprising:an interface to receive bits from a read, the read of a type, the type being one of several types assigned to reads; and set a low-density parity-check (LDPC) iteration maximum based on the type;', 'perform LDPC iterations up to the LDPC iteration maximum; and', 'signal a read failure in response to the LDPC iterations reaching the LDPC iteration maximum., 'an ECC component to2. The controller of claim 1 , wherein the interface is configured to receive the bits from a second read claim 1 , the second read of a second type from the several types; and wherein the ECC component is configured to:set a second LDPC iteration maximum based on the second type;perform second LDPC iterations up to the second LDPC iteration maximum; andsignal a read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum.3. The controller of claim 2 , wherein the second type is a read-error type.4. The controller of claim 2 , wherein the second LDPC iteration maximum is a multiple of the LDPC iteration maximum.5. The controller of claim 2 , wherein the second read is a result of a read error handling operation following the read failure in response to the LDPC iterations reaching the LDPC iteration maximum.6. The controller of claim 2 , wherein claim 2 , to signal the read failure in response to the second LDPC iterations reaching the second LDPC iteration maximum claim 2 , the ECC component is configured to provoke a read trial operation.7. ...

Large area micro nano structure soft impression method

A soft pressing method of large-scale micro-nanostructure includes processing out required micronanopattern structure on surface of hard substrate by photo-etching means, coating organic material PDMS on surface of finished hard template, dripping and spiral-coating organic slushing compound on surface of substrate, contacting structure surface of said template closely with polished surface of substrate, picking said template up from said substrate to leave micronanostructure of organic slushing compound on surface of said substrate and using dry means of etching process to remove off base resin or to transfer micronanopattern to surface of said substrate.

Super resolution lithography method based on PDMS template and silver board material

The utility model relates to a super-resolution photolithography method based on the PDMS template and the silver plate material, which comprises the following steps: a metallic film layer which has week adhering capability on a base is vapor-plated on the surface of the base; a micro-nano target structure is produced on the metallic film surface; after mixed with the curing agent, the PDMS is cast on the surface of the metallic film layer; the mixture is solidified in the environment with temperature of 25 to 95 DEG C to generate an elastic film; the PDMS film is lifted and the metallic film layer adhered on the surface of the PDMS film is removed, and then the micro-nano target structure is embedded in the PDMS film; a protective layer with the thickness of 10 to 100nm is spin-coated on the PDMS surface to form a super-resolution photoetching mask; the photoresist is spread on the surface of another substrate, on which a silver layer with the thickness of 10 to 100nm is vapor-plated; ...

Optical band artificial composite structure material made by AAO template

A method for preparing optical band artificial composite structural materials by using an AAO template comprises the steps of selecting a polishing optical silicon chip, and depositing a layer of micrometer-grade aluminum film on the surface of the polishing optical silicon chip; preparing a porous alumina template with thickness less than 1 micrometer on the surface of the aluminum film by using an electrochemistry two-step anodic oxidation method; generating a single-channel nano-pore array AAO template; depositing a metal film layer on the single-channel nano-pore array AAO template by using a lateral vacuum deposition method; selecting an optical material substrate, and connecting one surface of the nano-pore array AAO template having the metal film layer with the substrate; removing the silicon chip; eroding the metallic aluminum film layer and the alumina barrier layer at the back side to form a two-channel pore array AAO template; and depositing a metal film layer on the other surface ...

DYNAMIC SIZE OF STATIC SLC CACHE

Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples. 1. A method comprising:at a memory controller of a memory device having a lifespan:during operation of the memory device, tracking a maximum logical saturation over the lifespan of the memory device, where logical saturation is a percentage of capacity of the memory device written with data; andreallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage in inverse relation to an increase in logical saturation of the memory device, the reallocating including writing at least one electrical state to a register.2. The method of claim 1 , wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes using the logical saturation of the memory device as an input to a table stored in a memory of the memory device.3. The method of claim 1 , wherein tracking and reallocating are responsive to receiving a write request from a host.4. The method of claim 1 , wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes providing SLC static cache size inversely proportional to the maximum logical saturation5. The method of claim 1 , wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic ...

Metal groove joint applicable to light beam shaping

The invention discloses a metal groove joint structure applicable to light beam shaping, comprising the following steps of: (1) selecting a silicon substrate and polishing the surface of the silicon substrate; and then sputtering and depositing a layer of metal film, the thickness of which is in a required wavelength magnitude, on the surface of the metal film; (2) starting etching a groove at one end of the metal film by using a focus ion beam photoetching technology, periodically moving the focus position of the focus ion beams to one end after etching the groove and repeatedly etching a plurality of grooves; (3) moving the focus position of the focus ion beams for a period along the same direction after the grooves reach a certain quantity and etching through a metal layer to form a clearance; and (4) periodically moving the focus position of the focus ion beams along the same direction, repeatedly the step (2) and etching grooves with the same quantity as that of the grooves in the ...

Laser etching image filter

A pattern etching filet consists of a light source, a focus lens set, an image object glass and silicon chip. Also, a composite filltering plate for phase and amplitude filtration is arranged before the image object glass in order to change the focus function of the image etching system and its transfer function as well with less attenuation of imaging light. The said filter has dual spectrum modulation with improved spectrum transfer characteristics and image etching resolution.

Atomic beam generator

This invention relates to an atom beam generator containing mainly a high temperature oven composed of an over cover, oven atomic material container and a baseplate, a vacuum cavity, a big baseseat and a vacuum interface, by exchanging and heating the atomic material container to generate multi-different substantlal materials of atom beams. By vacuum-pumping, expelling useless atoms and gas in operation, a high purity of atom beam can be guaranteed. This invention includes designs of special vacuum working room for atom cooling and control process superfine graphs and a superfine three-dimensional graph in this working room.

Method for fabricating smei-cylindrical groove by shadow evaporation and wet etching

The invention relates to a method for fabricating a smei-cylindrical groove by shadow evaporation coating and wet etching, comprising the following steps: using the conventional technology to deposit a mask membrane layer on a substrate, coating photoresist on the mask membrane layer; preparing line structures on the photoresist by the photoetching technology; carrying out oblique evaporation at a certain angle; forming a bar of shadow region which is of a certain width and free from deposit evaporation material outside the edge of each photoresist line; then using evaporation material as a protection layer to carry out dry etching on the mask membrane layer, wherein the mask membrane layer at the shadow region is corroded in the absence of the protection of the evaporation material, so that a mask membrane layer slit corresponding to the shadow region is obtained; carrying out isotropic etching on the substrate by dilute hydrofluoric acid solution through the mask membrane layer slit and ...

Double-frequency tunable magnetic resonance artificial compound material based on asymmetric metal grating structure

The invention provides a double-frequency adjustable magnetic resonance artificial composite material based on a non-symmetric metal grating structure, which is characterized in that the material is produced through the following steps: selecting a quartz substrate and polishing the surface of the quartz substrate; evaporating a SiO2 film on the surface of the quartz substrate; evaporating a chromium film on the surface of the SiO2 film; coating a photoresist layer on the chromium film; preparing a medium grating structure on the photoresist by electron beam lithography method; eroding and exposing the chromium film by using the photoresist as a mask by wet etching technology; etching the medium grating structure on the SiO2 film by using the chromium film as a mask by dry etching technology, and removing the chromium film; laterally depositing a metal layer with the thickness of h on one side of the SiO2 grating structure by lateral vacuum deposition technology, similarly, depositing a ...

Method for designing high coupling efficiency composite type two-dimensional photon crystal

360-degree panoramic stereoscopic camera

The invention provides a 360-degree panoramic stereoscopic camera. The 360-degree panoramic stereoscopic camera at least comprises a bracket and a shell, wherein the center of the shell is fixed at the top of the bracket; a GPS (Global Positioning System) module is arranged in the center of the shell; a USB (Universal Serial Bus) data interface and an external power interface are formed in the side wall of the shell; a power switch, a shooting speed regulator and a sound collection module are mounted on a lower bottom plate of the shell; a central control and graphic processor, a battery and an audio processor are further arranged inside the shell; the center of the shell is divided into at least four unit modules with the same size; two lenses are mounted on the side surface of each unit module; each lens is provided with an area array CCD (Charge Coupled Device) imaging unit; the area array CCD imaging units are independent of one another. According to the panoramic stereoscopic camera ...

Optical lens switching mechanism

The invention provides an optical lens switching mechanism which comprises an installation frame, and a plurality of through holes penetrating through the installation frame are formed in the side face of the installation frame. The lens is positioned at the through hole; the first transmission assembly is in transmission connection with the mounting frame and can drive the mounting frame to rotate horizontally and circumferentially; and the second transmission assembly is in transmission connection with the lens, and the second transmission assembly can drive the lens to rotate/rotate around the central axis of the lens. Through the ingenious structural design, high-precision switching, increasing and decreasing of the lenses under the space import condition can be achieved, meanwhile, rotation of the lenses can be achieved, a feasible thought is provided for achieving special functions of an optical system, and the optical system is suitable for application scenes of compact spaces such ...

Real-time system control method

The invention provides a control method of a real-time system, which processes data of an input end through a data processing program and then issues the data to a real-time control system in real time to realize hardware real-time output, and comprises a signal input step, a calculation step and an analysis output step. The input signal value is subjected to data processing through the data processing software, the system clock mode can be changed in real time, the issued data instruction and the hardware scanning period can be effectively reduced, and the signal output period range which can be set by a user is greatly increased.

Sudden-onset geological disaster emergency plan digitization system

The invention discloses a geological disaster emergency plan digitization system which comprises a data acquisition transmission layer, a database management layer, a data driving layer and an application layer. The data acquisition transmission layer is positioned at the lowermost part of the digitization system and used for acquiring and transmitting data relating to a geological disaster; the database management layer is positioned on the data acquisition transmission layer and used for storing and processing various data information used in the system; the data driving layer is connected with the database management layer and used for taking charge of managing and supporting various data; the application layer comprises an emergency plan visualization subsystem and a plan dynamic deduction subsystem and is used for managing various functions provided by the system. The geological disaster emergency plan digitization system adopts technical means of a modern computer, a network, IOT ...

Localized surface plasma biochemical sensor production method

Method for accomplishing sub-wavelength interference photolithography utilizing multiple layer metal dielectric-coating structure

A method for utilizing multilayer metal dielectric film structure to realize the sub-wavelength interference lithography is characterized by the following steps of selecting a substrate material; coating an anticorrosion agent on the surface of the substrate; carrying out the alternate vapor deposition of a metal material film and a dielectric material film on the surface of the anticorrosion agent to form a metal layer and a dielectric layer which are arranged alternately; designing and arranging a periodic structure pattern mask on the surface of the structure which is obtained by the abovestep; carrying out the exposure of the obtained structure; removing the mask structure after the finish of the exposure; further removing the material of the metal layer and the material of the dielectric layer; arranging the obtained structure in a developing liquid which is matched with the anticorrosion agent for carrying out the development; carrying out the dry etching of the structure afterthe ...

Method for manufacturing diamond-type metal nanometer particle array structure

Method for preparing composite membrane layer with multilayer embossment structure based on mobile coding mask theory

The invention discloses a method for preparing a composite membrane layer with a multilayer embossment structure based on a mobile coding mask theory. The method is characterized by comprising the following steps of: obtaining a corresponding mask opening function by a thickness distribution function of a prepared membrane layer, and confirming the shape and the geometric dimensioning of the mask opening; preparing the openings periodically on the mask along a mask moving direction; moving the mask during membrane precipitation, and controlling membrane thickness distribution of each precipitation area of the membrane by the shape and the geometric dimensioning of the mask; and repeating the previous steps, therefore, a multilayer embossment structure membrane layer with different materials and thicknesses can be continuously precipitated through changing the mask and the membrane. By combining the mobile mask technology and the oriented precipitation technology, one layer or multilayer ...

Metal mask plate

High sensitivity nano biosensor production method

The present invention provides a producing method of the nanometer biosensor with high sensitivity. The procedures are as follows: firstly, selecting the fundus material and completing the producing of the metal nanometer array; secondly, soaking the fundus in the prepared biology activated chemical reagent solution to ensure the metal surface possess an activated group corresponding to the biology molecule, and to ensure the combination of the antigen and the silver granules array to be more easy, the biology activated chemical reagent is the octane mercaptan 1-OT and the eleven alcoholic acid 11-MUA with the hydrogen thiocyanato, the solvent is ethanol; thirdly, taking out the soaked substrate, cleaning off the leftover on the surface of the substrate and blow the substrate dry; fourthly, selecting the antigen corresponding to the detected molecule and the zero-distance coupling reagent; fifthly, mixing the antigen solution and the zero-distance coupling reagent solution, and then drip ...

Photoresist coating method

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a photoresist coating method. The photoresist coating method comprises the following steps: spraying a binder for improving the adhesive force of photoresist on a first surface of a wafer, dripping a first predetermined amount of first liquid on the first surface of the wafer, and driving the wafer to rotate at a first acceleration so as to enable the first liquid to move from a dripping point to the edge direction of the wafer, the adhesive is uniformly laid on the first surface of the wafer through the movement of the first liquid, a second preset amount of photoresist is dripped to the center of the wafer, and the wafer is driven to rotate at a second acceleration within a first time period after glue dripping is completed so that the second preset amount of photoresist can be spread on the first surface, the wafer is driven to rotate at a preset rotating speed in a second time ...

Laser modulation method and system

The invention belongs to the technical field of adaptive optics, and particularly discloses a laser modulation method, which comprises the following steps of: determining a block division rule; performing block division on the modulation module according to a block division rule; selecting a plurality of blocks meeting specific conditions from the divided blocks; performing the following operations on the plurality of blocks meeting the specific conditions one by one: applying a modulation parameter to the current block to modulate the laser; acquiring a light intensity distribution image of the laser which is modulated and influenced by atmospheric turbulence; calculating an evaluation value; if the difference between the currently calculated evaluation value and the previously calculated evaluation value is greater than an evaluation threshold value, calculating a modulation parameter according to the currently calculated evaluation value and the previously calculated evaluation value ...

Dynamic P2L asynchronous power loss mitigation

Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.

VISIBLE LIGHT-TRANSPARENT AND RADIATIVE-COOLING MULTILAYER FILM

The present disclosure provides a visible light-transparent and radiative-cooling multilayer film, including N layers of films which have different thicknesses and are arranged alternately. The visible light-transparent and radiative-cooling multilayer film adopts a new film layer arrangement, so that the multilayer film has an extremely high visible light transmittance while achieving radiative cooling. Among others, the multilayer film is composed of two materials having high visible light-transmittance. Since there is a difference between dielectric constants of the two materials, a resonant cavity or resonant cavities may be formed among material layers. The resonant cavity may enhance the electric field therein, thereby increasing the radiance of the structure greatly. The present disclosure has the advantages of simple structure, easy to process, good cooling effect, high visible light transmittance and low cost. 1. A visible light-transparent and radiative-cooling multilayer film comprising N layers of films , wherein the N layers of films comprise layers of first films and layers of second films arranged alternately;wherein the layers of first films and the layers of second films are made of different visible light-transparent materials, and the visible light-transparent materials have different dielectric constants in infrared band, and a resonant cavity or resonant cavities are formed between the layers of first films and the layers of second films.2. The visible light-transparent and radiative-cooling multilayer film of claim 1 , wherein the N layers of films have layers of materials with different thicknesses.3. The visible light-transparent and radiative-cooling multilayer film of claim 2 , wherein the layers of first films are made of indium tin oxide claim 2 , and the layers of second films are made of photoresist.4. The visible light-transparent and radiative-cooling multilayer film of claim 3 , wherein N≥3.5. The visible light-transparent and ...

REACTIVE READ BASED ON METRICS TO SCREEN DEFECT PRONE MEMORY BLOCKS

A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed. 1. A system comprising:one or more memory devices having multiple blocks of memory cells; and track multiple metrics associated with memory operations on a block of the multiple blocks;', 'generate a Z-score for each of the multiple metrics;', 'compare the Z-scores of the multiple metrics to Z-score thresholds for the multiple metrics, providing multiple comparisons; and', 'control retirement of the block of memory based on at least one of the multiple comparisons., 'a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations to2. The system of claim 1 , wherein the operations to track the multiple metrics include operations to measure times to perform the memory operations on the block of memory claim 1 , the Z-score for each metric is a Z-score for the measured time corresponding to the metric claim 1 , and the Z-score threshold for each metric is a threshold for Z-scores of time to perform the memory operation corresponding to the metric.3. The system of claim 2 , wherein the times to perform the memory operations include a time to program a page of the block of memory as a first metric of the multiple metrics with a Z-score of the first metric and a threshold for Z-scores being a ...

Uncorrectable ecc

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

PRIORITIZATION OF ERROR CONTROL OPERATIONS AT A MEMORY SUB-SYSTEM

A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation. 1. A method comprising:responsive to detecting that a first memory access operation has failed at a memory device, performing a first error control operation and a second error control operation; andresponsive to determining that the second error control operation has remedied the failed first memory access operation, associating, with the second error control operation, a second priority which is higher than a first priority associated with the first error control operation.2. The method of claim 1 , further comprising:responsive to detecting that a second memory access operation has failed, performing the second error control operation.3. The method of claim 1 , wherein the first error control operation is associated with a first success metric and the second error control operation is associated with a second success metric claim 1 , and wherein the second priority is associated with the second error control operation responsive to determining that the second success metric is higher than the first success metric in view of the second error control operation remedying the failed first memory access operation.4. The method of claim 1 , wherein the first error control operation and the second error control operation are included in a set of error control operations associated with a higher success rate than other error control operations.5. The method of claim 1 , wherein associating the second priority with the second error control operation further comprises:determining that a latency associated ...

MEMORY STRIPE CODING MANAGEMENT

A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane. 1. A method , comprising:writing, to a first sub-set of memory blocks of a first memory plane associated with a memory device, first data corresponding to recovery of an uncorrectable error; 'a relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane', 'writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error, wherein'}2. The method of claim 1 , further comprising writing redundant array of independent NAND (RAIN) data as part of writing the data corresponding to recovery of the uncorrectable error.3. The method of claim 1 , further comprising writing a first portion of redundant array of independent NAND (RAIN) parity data as part of writing the first data or writing a second portion of RAIN parity data as part of writing the second data claim 1 , or both.4. The method of claim 1 , wherein the first memory plane and the second memory plane are configured to store a portion of a first redundant array of independent NAND (RAIN) stripe and wherein the method further comprises:writing, to a ...

LOGICAL-TO-PHYSICAL MAPPING

A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both. 1. An apparatus , comprising: determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both; and', 'cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both., 'a logical to physical (L2P) mapping component to2. The apparatus of claim 1 , wherein the indication corresponds to a determination that a first portion of the data is consecutive with respective to a preceding L2P address written to the first level of the L2P data structure or the second level of the L2P data structure claim 1 , and wherein a second portion of the data is consecutive with respect to a subsequent L2P address written to the first level of the L2P data structure or the second level of the L2P data structure.3. The apparatus of claim 1 , wherein the indication corresponds to a determination that the first level of the L2P data structure and the second level of the L2P data structure contain consecutively written data.4. The apparatus of claim ...

TEMPERATURE SENSITIVE NAND PROGRAMMING

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level. 1. A memory device for temperature sensitive programming , the memory device comprising:an array of memory components; and obtaining a temperature for a memory component in the array of memory components during a write to the memory component;', 'calculating a verification read voltage for a write verification from the temperature; and', 'controlling repeated application of a program pulse to the memory component to perform the write until the memory component can be read using the verification read voltage., 'a controller configured to perform operations comprising2. The memory device of comprising a machine readable medium that includes instructions that claim 1 , when executed by the controller claim 1 , configure the controller to perform the operations.3. The memory device of claim 1 , wherein obtaining the temperature includes obtaining the temperature from a thermometer in response to receiving the command.4. The memory device of claim 1 , wherein calculating the read voltage from the temperature includes performing a quantification of the temperature into one range of a set of temperature ranges.5. The memory device of claim 4 , wherein calculating the read voltage from the temperature includes selecting a temperature compensation value using the one range; andwherein controlling repeated application of the program pulse includes modifying the program pulse to use the temperature compensation value.6. The memory device of claim 5 , wherein selecting the temperature compensation value includes:identifying an intermediate temperature compensation value ...

MEMORY SUB-SYSTEM MEDIA MANAGEMENT OPERATION THRESHOLD

An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.

ULTRA-LARGE AREA SCANNING REACTIVE ION ETCHING MACHINE AND ETCHING METHOD THEREOF

The present disclosure relates to a field of dry etching technology. The present disclosure provides an ultra-large area scanning reactive ion etching machine and an etching method thereof. The ultra-large area scanning reactive ion etching machine includes: an injection chamber (), an etching reaction chamber (), a transition chamber (), and an etching ion generation chamber (). By moving a sample holder () among the injection chamber (), the etching reaction chamber () and the transition chamber () in a scanning direction, a scanning etching is performed on a sample () placed on the sample holder (), which may realize a large-area, uniform and efficient etching.

SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE

A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned. 1. A system comprising:a memory device comprising a plurality of dice; and receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice;', 'identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion;', 'partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages;', 'programming the set of partitions to the plurality of dice; and', 'storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned., 'a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising2. The system of claim 1 , wherein the identifying further comprises determining that the plurality of the sets of pages takes more than a threshold time period to completely program claim 1 , wherein the operations further comprise:partitioning, into a further set of partitions, each set of pages of the plurality of the sets of pages in addition to the set of pages; andprogramming each further set of partitions to the plurality of dice.3. The system of claim 1 , wherein claim 1 , for each set of pages of the plurality of the sets of pages claim 1 , the operations further comprise: ...

MANAGING WORKLOAD OF PROGRAMMING SETS OF PAGES TO MEMORY DEVICE

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned. 1. A system comprising:a memory device comprising a plurality of dice; and{'claim-text': ['receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice;', 'partitioning the set of pages into a set of partitions;', 'programming the set of partitions to the plurality of dice; and', 'storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.'], '#text': 'a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising:'}2. The system of claim 1 , wherein the operations further comprise:associating a first partition of the set of partitions with a first block family; andassigning the first block family to a first threshold voltage offset bin.3. The system of claim 2 , wherein the operations further comprise:associating a subsequent partition of the set of partitions with a second block family; andassigning the second block family to a second threshold voltage offset bin.4. The system of claim 1 , wherein the operations further comprise claim 1 , in response to determining that at least a specified period of time elapses before a partition of the set of partitions has been fully programmed:writing a randomized pattern data to fully program the partition; andassociating the partition with a block family.5. The system of claim 1 , wherein each partition of the set of partitions is of a fixed length ...

MULTI-TIER THESHOLD VOLTAGE OFFSET BIN CALIBRATION

A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan. 1. A system comprising:a memory device comprising a plurality of dice; and performing, at a first frequency, a first scan of a page of a block family from a specified die of the plurality of dice, the first scan to measure a first data state metric within memory cells of the page and identify a specific threshold voltage offset bin corresponding to a measured value for the first data state metric;', 'updating a threshold voltage offset bin, to which the page is assigned for the specified die, to match the specific threshold voltage offset bin;', 'performing, at a second frequency that is higher than the first frequency, a second scan of the page of the block family from the specified die of the plurality of dice, the second scan to measure a second data state metric for read operations performed using a threshold voltage offset value from each of a plurality of threshold voltage offset bins; and', 'updating the threshold voltage offset bin, to which the page is assigned for the specified die, to match a second threshold voltage offset bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan ...

L2p translation techniques in limited ram systems

Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

MEDIA MANAGEMENT ON POWER-UP

A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value. 1. A method , comprising:detecting an occurrence of a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of virtual memory cells associated therewith;responsive to detection of the occurrence of the power-up event and prior to a host utilizing an interface associated with the memory sub-system, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells;determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value; andselectively performing a media management operation on the respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block associated with the open virtual block of memory cells exhibits greater than the threshold health characteristic value.2. The method of claim 1 , further comprising performing a block refresh of data stored in the ...

MULTI-PAGE PARITY PROTECTION WITH POWER LOSS HANDLING

A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group. 1. A method of handling asynchronous power loss to a memory system , the method comprising:writing data to multiple data pages of a parity group, the parity group including a parity page in which to write parity data generated from the data written in the multiple data pages; andmaintaining a flag in metadata of each data page of the multiple data pages to identify asynchronous power loss status of previous data pages of the parity group.2. The method of claim 1 , wherein the method includes generating the parity data using an ordering of the data pages in the parity group.3. The method of claim 1 , wherein the method includes claim 1 , following an uncorrectable error correction code error in writing the data claim 1 , re-constructing data to a data page of the parity group using an ordering of the data pages in the parity group.4. The method of claim 3 , wherein the method includes:starting recovery to re-construct the data to the data page by reading from a last data page in the parity group; andexcluding, from the recovery, previous data pages tagged, using the flag, as impacted by asynchronous power loss.5. The method of claim ...

MOBILE NAND PARITY INFORMATION TECHNIQUES

Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed. 1. A NAND memory device comprising:a random-access memory (RAM) buffer;an array of NAND memory cells organized into pages, data stripes of user data, and a parity information area, wherein the parity information area includes parity information associated with the data stripes of user information; and program first user data to a first portion of a first plurality of data stripes of the array of NAND memory cells;', 'copying current parity information associated with a second plurality of data stripes from the RAM buffer to the parity information area;', 'copying stored parity information of the first plurality of data stripes from the parity information area to the RAM buffer to replace the current parity information associated with the second plurality of data stripes; and', 'determining new parity information for the first plurality of data stripes using the stored parity information and the first user data., 'a controller configured to2. The NAND memory device of claim 1 , wherein each data stripe of the plurality of first data stripes span multiple pages of the array of NAND memory cells.3. The NAND memory device of claim 2 , wherein each page of the multiple pages of the NAND memory of each data stripe is associated with a word line of the NAND memory device; andwherein, within a plane of the array of NAND memory, a page of a first data stripe is separated by each other page of the first data stripe by at ...

Reactive read based on metrics to screen defect prone memory blocks

A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Grown bad block management in a memory sub-system

A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.

Broadband electromagnetic wave phase modulating method and meta surface sub-wavelength structure

A method for regulating the phase of a wide-band electromagnetic wave uses a meta-surface sub-wavelength structure and the meta-surface sub-wavelength structure. The sub-wavelength structure is used as a basic unit of the meta-surface, and the basic unit is arranged in an array according to a regular order determined by the predetermined phase to generate a geometrical phase distribution with the spatial continuity and the spectral achromaticity between 0 and 2π, so that the phase is controlled and modulated in a two dimensional plane. The operating bandwidth may cover the entire electromagnetic spectrum, and a variety of optical devices such as reflective focusing/imaging elements, transmission focusing/imaging elements, prisms, orbital angular momentum generator may be realized. As an extension of the phase regulation, the method may also realize other novel electromagnetic wave functions such as wideband absorption and radar cross section reduction.

TEMPERATURE SENSITIVE NAND PROGRAMMING

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level. 1. A controller comprising:an interface to memory components; and determine a read voltage to verify a write to a memory component of the memory components based on a temperature of the memory component; and', 'perform the write, through the interface, with a variable number of programming pulses based on the determined read voltage to verify the write., 'processing circuitry configured to2. The controller of claim 1 , comprising a second interface to a host claim 1 , and wherein the write was received from the host.3. The controller of claim 1 , wherein claim 1 , to perform the write with a variable number of programming pulses based on the determined read voltage to verify the write includes repeatedly:execute a pulse to program the memory component; andexecute a read at the determined read voltage, the write being verified when the read at the determined read voltage is successful.4. The controller of claim 3 , wherein the read at the determined read voltage is successful when a target charge distribution in the memory component is reached.5. The controller of claim 3 , wherein the write is complete when the write is verified.6. The controller of claim 1 , wherein the memory components are NAND flash memory devices.7. The controller of claim 1 , wherein the controller is included in a package that includes the memory components.8. The controller of claim 7 , wherein the package is a device that conforms to an Universal Flash Storage (UFS) family standards.9. The controller of claim 7 , wherein the package is a device that conforms to an embedded ...

VARIABLE READ ERROR CODE CORRECTION

Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum. 1. A device for variable read error code correction (ECC) , the controller comprising:a hardware interface to receive bits from a memory in response to a read that is one type of several types of read; and performing a number of LDPC decodes that is less than a total number of possible LDPC decodes; and', 'signaling a failure for the read based on reaching the number of LDPC decodes., 'processing circuitry configured to perform a low-density parity check (LDPC) on the bits based on the type by2. The device of claim 1 , wherein the hardware interface is configured to receive bits from a second read claim 1 , the second read of the one type; and wherein the processing circuitry is configured to:address errors in the bits from the third read in fewer LDPC decodes than the number of LDPC decodes; andsignal a read success in response to addressing the errors in the bits from the third read in fewer LDPC decodes than the number of LDPC decodes.3. The device of claim 1 , wherein the interface is configured to receive the bits from a second read claim 1 , the second read of a second type from the several types; and wherein the processing circuitry is configured to:perform second LDPC iterations up to a second number of LDPC decodes, the second number greater that the number of LDPC decodes and less than the total number of possible LDPC decodes; andsignal a second read failure in response to the second LDPC iterations reaching the second number of LDPC decodes.4. The device of claim 3 , wherein the second type is a read-error type.5. The device of ...

SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE

Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition. 1. A system comprising:a memory device comprising a plurality of dice; and identifying, while programming sets of pages of data to at least a subset of a plurality of dice, a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion;', 'partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages;', 'storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned; and', merging the set of partitions into a merged set of pages;', 'selecting a block family for the merged set of pages; and', 'consolidating, within the metadata table, a single entry for the merged set of pages, wherein the single entry is associated with the block family., 'in response to detecting the set of pages exit a queue of a threshold number of the plurality of the sets of pages that are to remain partitioned], 'a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising2. The system of claim 1 , wherein the identifying ...

VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD

A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped. 1. A system comprising:a memory device; and initiating a voltage calibration scan;', 'receiving a first value of a data state metric measured for a sample block of a memory device based a first set of read voltage offsets with a first bin of blocks designed as a current bin, wherein the first value is designated as a minimum value of the data state metric;', 'measuring a second value of the data state metric for the sample block based on a second set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin;', 'determining that the second value exceeds the first value; and', 'in response to determining that the second value exceeds the first value, maintaining the first bin as the current bin and stopping the voltage calibration scan., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein receiving the first value comprises measuring the first value.3. The system of claim 1 , wherein the operations further comprise storing the current bin in non-volatile memory prior to initiating the voltage calibration scan.4. The system of claim 3 , wherein the operations further comprise claim 3 , after stopping the voltage calibration scan:initiating a second voltage calibration scan; andmeasuring a third value of the data state ...

MEMORY SUB-SYSTEM MEDIA MANAGEMENT OPERATION THRESHOLD

An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device. 120-. (canceled)21. An apparatus , comprising: determine a threshold quantity of blocks for a memory mode in the memory device;', 'determine a logical saturation of the memory device; and', 'cause performance of a media management operation based on the determined threshold quantity and a percentage of the determined logical saturation to a total logical saturation of the memory device., 'a media management threshold component to22. The apparatus of claim 21 , wherein the media management threshold component is to further cause the performance of the media management operation in response to a quantity of free blocks being less than a threshold quantity of free blocks.23. The apparatus of claim 22 , wherein the threshold quantity of free blocks is less than a summation of the threshold quantity of blocks and an additional threshold quantity of blocks by a particular portion.24. The apparatus of claim 22 , wherein the threshold quantity of free blocks is based on the determined logical saturation percentage being less than a threshold logical saturation percentage.25. The apparatus claim 21 , wherein the media management threshold component is to further cause the performance of the media management operation in response to the determined logical ...

VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE

A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset. 1. A method comprising:measuring a current memory access voltage distribution for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device, wherein the first voltage bin is associated with a first voltage offset;determining a current value for a reference voltage based on the current memory access voltage distribution measured for the memory page;determining an amount of voltage shift for the memory page based on the current value for the reference voltage and a prior value for the reference voltage, wherein the prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page; andresponsive to determining that the amount of voltage shift satisfies a voltage shift criterion, associating the block family with a second voltage bin of the plurality of voltage bins, wherein the second voltage bin is associated with a second voltage offset.2. The method of claim 1 , wherein the prior memory access voltage distribution for the memory page corresponds to ...

Redundant array management techniques

Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table. 1. A system comprising:a memory device; and detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;', 'determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block; and', 'performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table., 'a processing device, operatively coupled to the memory device, to perform operations comprising2. The system of claim 1 , wherein the processing device is to perform further operations comprising:adjusting the order of the plurality of error-handling operations.3. The system of claim 1 , wherein the processing device is to perform further operations comprising:maintaining a record of read error rates for the voltage offset bin; andresponsive to detecting the read error rates satisfying a threshold criterion, adjusting a read voltage offset associated with at least one ...

PARITY PROTECTION

A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed. 1. A storage device comprising:a storage array, including non-volatile memory cells accessible through access lines;an additional memory array; programing data into the storage array using multiple groups of access lines such that the programming of data using a first group of access lines is completed before programming of data using a second group of access lines;', 'storing parity data, in the additional memory array, while programming using the first group of access lines;', 'discarding the parity data from the additional memory array upon determination that a criterion has been net in the programming using the first group of access lines; and', 'accumulating other parity data in the storage device, after discarding the parity data stored from programming using the first group of access lines, while programming using the second group of access lines of the groups of access lines, the second group of access lines being different from the first group of access lines., 'a controller, including a processor configured to execute instructions stored within the storage device, wherein execution of the instructions by the processor cause the ...

READ RETRY WITH TARGETED AUTO READ CALIBRATE

Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage. 1. A system , comprising:a memory component comprising a plurality of physical addresses including a physical address; and receiving an indication that a read operation at the physical address of the memory component failed;', 'executing a plurality of read retry operations at the physical address;', 'accessing a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations;', 'accessing a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations;', 'selecting a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight; and', 'executing a first auto read calibrate operation at the physical address, the first auto read calibrate ...

NEGATIVE REFRACTION IMAGING LITHOGRAPHIC METHOD AND EQUIPMENT

The embodiments of the present disclosure propose a negative refraction imaging lithographic method and equipment. The lithographic method includes: coating photoresist on a device substrate; fabricating a negative refraction imaging structure, wherein the negative refraction imaging structure exhibits optical negative refraction in response to beam emitted by exposure source; pressing a mask to be close to the negative refraction imaging structure; disposing the mask and the negative refraction imaging structure above the device substrate at a projection distance; and light emitted by the exposure source passes through the mask, the negative refraction imaging structure, the projection gap and is sequentially projected onto the photoresist for exposure. 135.-. (canceled)36. A negative refraction imaging lithographic method , comprising:coating photoresist on a device substrate;fabricating a negative refraction imaging structure on a mask, wherein the negative refraction imaging structure exhibits a negative refraction in response to beam emitted by an exposure source, that is, a refraction beam and an incidence beam are on the same side of the normal of imaging structure plane;wherein the negative refraction imaging structure comprises a multilayered negative refraction imaging structure and a complex negative refraction imaging structure, and different negative refraction imaging structures are configured to achieve different effective refraction indexes and have different optical transfer functions,wherein the negative refraction imaging structure comprises planar and curved imaging structures in a geometric form, wherein the planar negative refraction imaging structure is configured to achieve 1:1 imaging lithography, and the curved one is configured to achieve demagnification imaging lithography of 2 to 10 times, the negative refraction imaging structure has a pattern input layer and an imaging output layer on opposite sides, respectively, wherein the pattern ...

Managing storage of multiple plane parity data in a memory sub-system

Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

MULTI-PAGE PARITY PROTECTION WITH POWER LOSS HANDLING

A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group. 1. A system comprising: metadata of data written to the given data page; and', 'a flag allocated in the metadata to identify a count of one or more data pages impacted by an asynchronous power loss event, the one or more data pages preceding the given data page in an order of writing data to the data pages of the parity group., 'a given data page including, 'a first parity group having multiple data pages in which to write data and at least one parity page in which to write parity data generated from the data written in the multiple data pages, and the multiple data pages including, 'multiple parity groups arranged for data protection of a memory system, the multiple parity groups including2. A system comprising: metadata of data written to the given data page; and', 'a flag allocated in the metadata to identify an asynchronous power loss status of one or more data pages that precede the given data page in an order of writing data to the data pages of the parity group, wherein the asynchronous power loss status of one or more data pages includes an asynchronous power loss impacted status in which completion of a write operation of ...

Methods and apparatuses for coating photoresist

The present disclosure proposes an apparatus for coating photoresist and a method for coating photoresist. The apparatus for coating photoresist comprises a gas supply unit (10) configured to supply gas to a photoresist application unit (20); wherein the photoresist application unit (20) comprises: a device cavity (202) enclosed by sidewalls, a bottom plate and a cover plate (206), a rotation platform (204) configured to carry a substrate (205) and bring the substrate to rotate; a guide unit conformal with the substrate, and configured to uniformly blow the gas supplied by the gas supply unit over a surface of the substrate on which the photoresist is coated; and a gas extraction unit (203) configured to extract gas from the device cavity (202). The present disclosure realizes uniformly and rapidly coating the photoresist on a large substrate.

SUPER-RESOLUTION IMAGING PHOTOLITHOGRAPHY

Provided are apparatuses and methods for super resolution imaging photolithography. An exemplary apparatus may include an illumination light generation device configured to generate illumination light for imaging a pattern included in a mask through the mask. The illumination light may include a high-frequency spatial spectrum such that a high-frequency evanescent wave component of spatial spectrum information for the light is converted to a low-frequency evanescent wave component after being transmitted through the mask pattern. For example, the illumination light generation device may be configured to form the illumination in accordance with a high numerical aperture (NA) illumination mode and/or a surface plasmon (SP) wave illumination mode. 1. An apparatus for super resolution imaging photolithography , comprising:an illumination light generation device configured to generate illumination light which can pass through a mask and then image a pattern included in the mask,wherein the illumination light comprises a high-frequency spatial spectrum such that a high-frequency evanescent wave component of spatial spectrum information for the light is converted to a low-frequency evanescent wave component after being transmitted through the mask pattern.2. The imaging photolithography apparatus according to claim 1 , wherein the illumination light generation device is configured to form the illumination light in accordance with a Surface Plasmon (SP) wave illumination mode and/or a high Numerical Aperture (NA) illumination mode.3. The imaging photolithography apparatus according to claim 2 , wherein the illumination light generation device comprises:a light source configured to emit illumination light;a light homogenizer configured to homogenize uniform the illumination light; anda high NA illumination light shaper configured to shape the homogenized illumination light into the illumination light containing the high-frequency spatial spectrum.4. The imaging ...

Nand parity information techniques for systems with limited ram

Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

SUB-WAVELENGTH STRUCTURAL MATERIAL HAVING COMPATIBILITY OF LOW DETECTABILITY FOR INFRARED, LASER, AND MICROWAVE

The present disclosure provides a sub-wavelength structural material having compatibility of low detectability for infrared, laser, and microwave, which includes, from top to bottom, a metal type frequency selective surface layer I, a dielectric layer I, a metal type frequency selective surface layer II, a dielectric layer II, a resistive film, a dielectric layer III. Each of the metal type frequency selective surface layers is a sub-wavelength patch type array, and metal used by the metal type frequency selective surface layers has a characteristic of low infrared emissivity. The present disclosure modulates a phase by using a phase difference generated by patches with different sizes on the metal type frequency selective surface layer I, so as to control backscattering of incident electromagnetic waves to achieve compatibility of low detectability for laser and infrared, while the bottom three layers achieve absorption of microwave. 1. A sub-wavelength structural material having compatibility of low detectability for infrared , laser , and microwave , comprising:a metal type frequency selective surface layer I, the metal type frequency selective surface layer I being a sub-wavelength patch type array;a dielectric layer I disposed below the metal type frequency selective surface layer I;a metal type frequency selective surface layer II disposed below the dielectric layer I, the metal type frequency selective surface layer II being also a sub-wavelength patch type array;a dielectric layer II disposed below the metal type frequency selective surface layer II;a resistive film layer disposed below the dielectric layer II; anda dielectric layer III disposed below the resistive film layer,wherein the metal type frequency selective surface layer I, the dielectric layer I and the metal type frequency selective surface layer II are used to realize low detectability for laser and infrared, and the dielectric layer II, the resistive film layer, the dielectric layer III, and a ...

DYNAMIC SIZE OF STATIC SLC CACHE

Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples. 1. (canceled)2. A storage system comprising:a memory device including single level cell (SLC) static cache memory cells and SLC dynamic cache memory cells; and tracking a maximum logical saturation over a lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data;', 'using the tracked logical saturation as an input to a table stored in the memory device; and', 'determining a portion of a pool of memory cells of the memory device to be reallocated from single level cell (SLC) static cache memory cells to SLC dynamic cache memory cells using the table and based on a current value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register., 'a memory controller configured to perform operations comprising3. The storage system of claim 2 , wherein the SLC dynamic storage is configured to be used for an SLC storage mode or a multi-level cell (MLC) storage mode.4. The storage system of claim 3 , wherein claim 3 , in MLC storage mode claim 3 , a memory cell stores three or more bits of data per memory cell.5. The storage system of claim 2 , wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes providing SLC static cache size inversely proportional to the maximum logical saturation.6. The storage system of ...

Grown bad block management in a memory sub-system

A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.

DYNAMIC P2L ASYNCHRONOUS POWER LOSS MITIGATION

Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure. 1. A system comprising:a storage system comprising control circuitry and a memory array having multiple groups of memory cells,wherein the control circuitry, when resuming operation from a low-power state, is configured to store a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, and store a second P2L data structure for the second physical area of the first group of memory cells; and', 'store an address of the first P2L data structure in the second P2L data structure., 'wherein the control circuitry is configured to2. The system of claim 1 , wherein to store the first P2L data structure for the first physical area of the first group of memory cells in the second physical area claim 1 , the control circuitry is configured to store the first P2L data structure for the first physical area of the first group of memory cells in a block of user data in the second physical area of the first group of memory cells.3. The system of claim 1 , wherein to store the second P2L data structure for the second physical area claim 1 , the control circuitry is configured to store the second P2L data structure for the ...

ASYNCHRONOUS POWER LOSS IMPACTED DATA STRUCTURE

Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). 1. A system comprising:a storage system comprising control circuitry and a memory array having multiple groups of memory cells,wherein the control circuitry is configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) data structure, to maintain a status of the groups of memory cells in a group data structure, determine if a group of memory cells has an error rate above a stable threshold; and', assign the determined group of memory cells as a marginal group of memory cells;', 'relocate the assigned marginal group of memory cells; and', 'rebuild the L2P data structure subsequent to relocating the assigned marginal group of memory cells., 'in response to determining that the group of memory cells has an error rate above the stable threshold], 'wherein the control circuitry, when resuming operation from a low-power state, is configured to2. The system of claim 1 , wherein resuming operation from the low-power state comprises resuming operation from an asynchronous power loss (APL) claim 1 , andwherein, to rebuild the L2P data structure comprises to rebuild the L2P data structure in response to the APL.3. The system of claim 1 , wherein the control circuitry is configured to:determine the last written group of memory cells in the group data structure; and assign the last written group of memory cells as a marginal group of memory cells;', 'relocate the assigned marginal group of memory cells; and', 'rebuild the L2P data structure subsequent to relocating the assigned marginal group of memory cells., 'in response to determining that the last ...

MULTIPLE MEMORY DEVICES HAVING PARITY PROTECTION

A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed. 1. A system comprising:a processing device;a plurality of memory devices, each memory device comprising an array of memory cells organized into a plurality of blocks, and each block comprising a plurality of pages;a buffer; and programming non-parity data in a page in a first block of the plurality of blocks;', 'generating a parity for the non-parity data programmed in the page;', 'storing the parity in the buffer, the buffer being configured to hold parity data;', 'transferring the parity data from the buffer to a temporary block in response to a determination that a transfer criterion is satisfied, the temporary block comprising a second block of the plurality of blocks, and the temporary block operating as temporary storage for the parity data; and', 'conducting, after a closing of the first block, a verification of the first block with respect to data errors., 'firmware comprising stored instructions, executable by the processing device, to perform operations comprising2. The system of claim 1 , wherein the operations further comprise:releasing of the temporary block from operating as temporary ...

Multi-tier threshold voltage offset bin calibration

A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

OVER PROVISIONING COMPONENT FOR MEMORY MANAGEMENT

A method includes designating, by an over provisioning component, a first set of memory cells of a memory array for use in write burst mode operations, designating a second set of memory cells of the memory array for use in non-write burst mode operations, identifying that a request to perform a particular non-write burst operation exceeds a quantity of memory cells available to the second set of memory cells for use in the non-write burst mode writing operations, designating, by the over provisioning component, a portion of the first set of memory cells as a static single level cell (SLC) block for use in the non-burst mode writing operations in response to the request, and writing data associated with the particular non-write burst writing operation to the static SLC block. 1. A method , comprising:designating, by an over provisioning component, a first set of memory cells of a memory array for use in write burst mode operations;designating a second set of memory cells of the memory array for use in non-write burst mode operations;identifying that a request to perform a particular non-write burst operation exceeds a quantity of memory cells available to the second set of memory cells for use in the non-write burst mode writing operations;designating, by the over provisioning component, a portion of the first set of memory cells as a static single level cell (SLC) block for use in the non-write burst mode writing operations in response to the request; andwriting data associated with the particular non-write burst writing operation to the static SLC block.2. The method of claim 1 , further comprising:performing a media management operation involving data written to the memory array; anddesignating the static SLC block back to the first set of memory cells for the write burst mode operation when the data associated with the particular non-write burst writing operation is erased during performance of the media management operation.3. The method of claim 1 , further ...

Multiple memory devices having parity protection

A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

Memory device virtual blocks using half good blocks

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Uncorrectable ecc

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Memory stripe coding management

A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.

Reactive read based on metrics to screen defect prone memory blocks

A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Determining offsets for memory read operations

Methods, systems, and devices for determining offsets for memory read operations are described. A method comprising: performing a first plurality of read operations on a block of a memory array using a reference voltage (705); determining, as part of performing the first plurality of read operations, one or more offset values to use with the reference voltage to perform the first plurality of read operations (710); determining a fixed offset value to use as a baseline offset for a second plurality of read operations based at least in part on determining the one or more offset values (715); and performing the second plurality of read operations on the block of the memory array using the reference voltage and the fixed offset value (720).

Super-resolution image photoetching

Provided are apparatuses and methods for super resolution imaging photolithography. An exemplary apparatus may includean illumination light generation device configured to generate illumination light for imaging a pattern included in a mask through the mask. The illumination light may include a high-frequency spatial spectrum such that a high-frequency evanescent wave component of spatial spectrum information for the light is converted to a low-frequency evanescent wave component after being transmitted through the mask pattern. For example, the illumination light generation device may be configured to form the illumination in accordance with a high numerical aperture (NA) illumination mode and/or a surface plasmon (SP)wave illumination mode.

Uncorrectable ECC

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Read error recovery

Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

Intelligent correction device control system for super-resolution lithography precision mask

Provided is an intelligent correction device control system for a super-resolution lithography precision mask, including: a sixteen-way pneumatic fine-tuning mask deformation control subsystem configured to deform a mask, detect a force value of a mask deformation, compare the force value of the mask deformation with an output force set value, and generate a first control feedback quantity to adjust a force deforming the mask, so as to control a deformation quantity of the mask; and an alignment subsystem configured to acquire images of the mask and a substrate, and adjust a position between the mask and the substrate according to the images, so as to align the mask with the substrate.

Memory sub-system using partial superblocks

An apparatus can include a media management superblock component. The media management superblock component can determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component can compare the quantity of bad blocks to a bad block criteria. The media management superblock component can write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

Temperature sensitive nand programming

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

Memory device virtual blocks using half good blocks

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Method for etching curved substrate

A method for etching a curved substrate is provided, including: forming a conductive thin film layer with an etched pattern on the curved substrate; supplying power to the conductive thin film layer such that the conductive thin film layer has an equal potential at each position of the conductive thin film layer; etching each position of the curved substrate to an etching depth corresponding to the potential at each position of the conductive thin film layer based on the etched pattern of the conductive thin film layer, so as to obtain the curved substrate having a consistent etching depth at each position of the curved substrate. With the etching method, it is possible to etch an arbitrary curved surface to obtain a microstructure with a uniform processing depth.

Managing storage of multiple plane parity data in a memory sub-system

A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

Multifunctional lithography device

Provided is a multifunctional lithography device, including: a vacuum substrate-carrying stage configured to place a substrate and adsorb the substrate on the vacuum substrate-carrying stage by controlling an airflow, so as to control a gap between the substrate and the mask plate; a mask frame arranged above the vacuum substrate-carrying stage and configured to fix the mask plate; a substrate-carrying stage motion system arranged below the vacuum substrate-carrying stage and configured to adjust a position of the vacuum substrate-carrying stage, so that a distance between the substrate and the mask plate satisfies a preset condition; an ultraviolet light source system arranged above the mask plate and configured to generate an ultraviolet light for lithography; and a three-axis alignment optical path system configured to align the ultraviolet light with the mask plate.

Multilayer radiation cooling film transparent to visible light

Memory sub-system using partial superblocks

An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

Source address memory managment

Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

Reactive read based on metrics to screen defect prone memory blocks

A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Virtual indexing in memory device

A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches

Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Dynamic superblock construction

A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

Method for preparing micro-nano structure

Secondary imaging optical lithography method and apparatus

The present disclosure provides a secondary imaging optical lithography method and apparatus. The method includes: contacting a lithography mask plate with a flexible transparent transfer substrate closely, the flexible transparent transfer substrate comprising a first near-field imaging structure having a photosensitive layer; irradiating the photosensitive layer through the lithography mask plate with a first light source, so as to transfer a pattern of the lithography mask plate to the photosensitive layer; coating a device substrate for fabricating devices with a photoresist; contacting the flexible transparent transfer substrate with the photoresist-coated device substrate closely; irradiating the device substrate through the flexible transparent transfer substrate with a second light source, so as to transfer a pattern of the photosensitive layer to the photoresist of the device substrate; and developing the device substrate comprising an exposed photoresist, so as to obtain a device pattern conforming to the pattern of the lithography mask plate.

Memory sub-system data migration

A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

Recovery of memory from asynchronous power loss

Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.

L2p translation techniques in limited ram systems to increase random write performance using multiple l2p caches

Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

L2P-Übersetzungstechniken in begrenzten RAM-Systemen

Hierin werden Vorrichtungen und Techniken zum effizienteren Ausführen einer Zufalls-Schreiboperation für eine Speichervorrichtung offenbart. In einem Beispiel kann ein Verfahren zum Betreiben einer Flash-Speichervorrichtung das Empfangen einer Schreibanforderung an einer Flash-Speichervorrichtung von einem Host einschließen, wobei die Schreibanforderung eine erste logische Blockadresse und Schreibdaten einschließt, das Speichern der Schreibdaten an einem Ort der Flash-Speichervorrichtung, der eine erste physikalische Adresse hat, das Betreiben der Flash-Speichervorrichtung in einem ersten Modus, wenn eine Menge von Schreibdaten, die mit der Schreibanforderung verbunden sind, über einem Schwellenwert liegt, das Betreiben der Flash-Speichervorrichtung in einem zweiten Modus, wenn eine Schreibdatenmenge unter dem Schwellenwert liegt, und das Vergleichen der Menge der Schreibdaten mit dem Schwellenwert.

Logical-to-physical translation techniques in limited ram systems

Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Memory device with configurable performance and defectivity management

A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

Memory device with configurable performance and defectivity management

A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

Curved substrate etching method

Managing error-handling flows in memory devices

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.

Managing error-handling flows in memory devices

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Voltage bin calibration based on a temporary voltage shift offset

A difference between a current temperature and a prior temperature of a memory device is determined. In response to a determination that the difference between the current temperature and the prior temperature of the memory device satisfies a temperature criterion, an amount of voltage shift is measured for a set of memory cells of a block family associated with a first voltage bin of a set of voltage bins at the memory device. The first voltage bin is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the set of memory cells based on the determined amount of voltage shift and a temporary voltage shift offset associated with the difference between the current temperature and the prior temperature for the memory device. In response to a determination that the adjusted amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the set of voltage bins. The second voltage bin is associated with a second voltage offset.

Adaptive block mapping

Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Managing workload of programming sets of pages to memory device

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Voltage bin calibration based on a temporary voltage shift offset

A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

Memory sub-system media management operation threshold

An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.

Media management on power-up

A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value.

Super block management for efficient utilization

A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Multi-tier threshold voltage offset bin calibration

A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

Adaptive block mapping

Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Memory device virtual blocks using half good blocks

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).