Thin film transistor array panel

A thin film transistor array panel includes a second conductive layer. The second conductive layer has a multi-layer structure which includes: a first sub-layer, the first sub-layer including a conductive metal oxide material containing indium and zinc; a second sub-layer on the first sub-layer, the second sub-layer including a metal material; a third sub-layer on the second sub-layer, the third sub-layer including a conductive metal oxide material containing indium and zinc. A gap is defined in the second conductive layer. The ratio of the indium atoms and zinc atoms in the first sub-layer is larger than that of the third sub-layer, which affects forming of a lateral etch profile of the gap. Thus, the gap has a width in the third sub-layer is larger than that in the first sub-layer.

SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME

A method for forming a TFT includes providing a substrate, a gate electrode on the substrate, an electrically insulating layer on the substrate to totally cover the gate electrode, a channel layer on the electrically insulating layer, a first photoresist pattern on the channel layer, a metal layer on the electrically insulating layer, the channel layer and the first photoresist layer, and a second photoresist pattern on the metal layer. A middle portion of the metal layer is then removed to form a source electrode and a drain electrode and to expose the first photoresist pattern and a portion of the channel layer between the first and second photoresist patterns. The exposed portion of the channel layer is then processed to have its electrical conductivity be lowered to thereby reduce a hot-carrier effect of the channel layer. 1. A thin film transistor comprising:a substrate;a gate electrode formed on the substrate;an electrically insulating layer formed on the substrate and covering the gate electrode;a channel layer made of semiconductor material and formed on the electrically insulating layer;a source electrode formed on a first lateral side of the electrically insulating layer, the source electrode having an inner end covering a first outer end of the channel layer and electrically connecting therewith; anda drain electrode formed on an opposite second lateral side of the electrically insulating layer, the drain electrode having an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith;wherein an area of the channel layer adjacent to one of the source electrode and the drain electrode and not covered thereby has an electrical conductivity lower than other area of the channel layer.2. The thin film transistor of claim 1 , wherein the area of the channel layer which has a lower electrical conductivity is formed by implanting ions therein.3. The thin film transistor of claim 1 , wherein the area of the channel ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

METHOD FOR FABRICATING CONDUCTING STRUCTURE AND THIN FILM TRANSISTOR ARRAY PANEL

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile. 1. A method of providing a conducting structure over a substrate , comprising:disposing a lower sub-layer over the substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio;performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein;disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material;disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; andpatterning the multi-layered conductive structure to generate a composite lateral etch profile.2 ...

Method for manufacturing pixel electrode

一種畫素電極的製造方法，包括以下步驟：提供基板，並在該基板上形成柵極、源極、漏極和鈍化層，鈍化層上形成有接觸孔以將漏極從接觸孔中裸露出來；塗覆奈米金屬材料以形成導電層覆蓋鈍化層以及從接觸孔中露出的漏極；以及圖案化導電層形成畫素電極。

TFT array substrate, display device and method for making the TFT array substrate

A TFT array substrate includes a substrate, pixel arrays and driving circuit on the substrate. The pixel arrays include a plurality of pixel units, each pixel unit includes a light emitting diode, a driving TFT, and a switch TFT electrically coupled between the driving circuit and the driving TFT. Both the driving TFT and the switch TFT have a semiconductor layer made of metal oxide. The driving TFT has a first gate insulate layer, the switch TFT has a second gate insulate layer. The fist gate insulate layer is thicker than the second gate insulate layer. A display device using the TFT array substrate and method for making the TFT array substrate are also provided. A luminance of the light emitting diodes can be effectively controlled.

ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE USING SAME

An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode. 1. An array substrate comprising: a first common electrode;', 'a first protection layer on the first common electrode;', 'a pixel electrode on the first protection layer;', 'a second protection layer on the pixel electrode; and', 'a second common electrode arranged on the second protection layer and electrically coupled to the first common electrode, the second common electrode having a plurality of slits., 'a storage capacitor including2. The array substrate of claim 1 , further comprising a substrate claim 1 , a thin film transistor (TFT) arranged on the substrate claim 1 , a passivation layer covering the TFT claim 1 , and a planar layer covering the passivation layer claim 1 , wherein the storage capacitor is located in the planar layer.3. The array substrate of claim 1 , further comprising a substrate claim 1 , a thin film transistor (TFT) arranged on the substrate claim 1 , a passivation layer covering the TFT claim 1 , and a planar layer covering the passivation layer claim 1 , wherein a first opening hole is defined passing through the passivation layer to expose one portion of the TFT; a second opening hole is defined in the first common electrode and communicates with the first opening hole claim 1 , a diameter of the second opening hole is greater than a diameter of the first opening hole; and a third opening hole is defined in the first protection layer to expose the one part of a drain the TFT.4. The array substrate of claim 3 , wherein the pixel electrode is electrically coupled to the TFT via the third opening hole.5. The array substrate of claim 3 , wherein a fourth opening hole is defined in the second common electrode claim ...

Display array substrate and manufacturing method thereof

本發明提供一種顯示陣列基板的製造方法，該製造方法包括：於一基板上沉積第一金屬層，並定義畫素區域與周邊區域；在周邊區域的第一金屬層上塗佈圖案化光阻層；利用圖案化光阻層為遮罩陽極化處理該第一金屬層形成第一金屬氧化物層；圖案化該畫素區域的第一金屬氧化物層形成閘極絕緣層，並移除圖案化光阻層曝露出該第一金屬層；於閘極絕緣層上形成溝道層；及沉積第二金屬層，並圖案化畫素區域的第二金屬層形成源極與汲極。

TFT SUBSTRATE AND METHOD FOR MAKING SAME

A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.

In-cell touch lcd display panel

Manufacturing method of thin film transistor and display array substrate using same

A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.

DISPLAY ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.

Method for manufacturing thin film transistor substrate

A method for manufacturing a thin film transistor substrate includes: providing a substrate and forming a gate electrode on the substrate; forming a gate insulation layer, a metal oxide layer and a first photo resist layer on the substrate to cover the gate electrode; patterning the first photo resist layer to form a first photo resist pattern; etching the metal oxide layer to form a channel; removing portions of both sides of the first photo resist pattern to expose a part of the channel; forming a metal layer to cover the gate insulation layer and the channel and forming a second photo resist layer on the metal layer; patterning the second photo resist layer to form a second photo resist pattern; etching the metal layer to form a source electrode and a drain electrode; and removing the first photo resist pattern and the second photo resist pattern.

THIN FILM TRANSISTOR AND DISPLAY ARRAY SUBSTRATE USING SAME

A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole. 1. A thin film transistor , comprising:a gate electrode;a gate insulating layer covering the gate electrode;a channel layer arranged on the gate insulating layer corresponding to the gate electrode;an etching stop layer covering the channel layer and comprising an organic stop layer and a hard mask layer, the hard mask layer located on a surface of the organic stop layer opposite to the channel layer;a plurality of contact holes passing through the etching stop layer;a source connecting to the channel layer via one of the plurality of contact holes; anda drain connecting to the channel layer via the another of the plurality of contact holes.2. The thin film transistor of claim 1 , wherein a photosensivity of a photoresistor material is better than a photosensitivity of the etching stop layer.3. The thin film transistor of claim 1 , wherein a thickness of the hard mask layer is less than a thickness of the organic stop layer.4. The thin film transistor of claim 1 , wherein the hard mask layer is made of a material selected from a group of silicon nitride (SiNx) claim 1 , Silicon oxide (SiOx) claim 1 , silicon fluorion (SiFx) claim 1 , and silicon nitride oxide (SiNxOy).5. The thin film transistor of claim 1 , wherein a distance between ...

Display array substrate and manufacturing method thereof

A manufacturing method of display array substrate is provided. The method includes depositing a first metal layer on a substrate and defining a peripheral area and a display area, coating a photo-resist layer on the first metal layer located in the peripheral area, anodizing the first metal layer to a first metal oxide layer with the photo-resist layer as a mask, patterning the first metal oxide layer located in the display area to a gate insulator, removing the photo-resist layer to expose the first metal layer in the peripheral area, forming a channel layer on the gate insulator, and depositing a second metal layer and patterning the second metal layer located in the display area to form a source electrode and a drain electrode.

Array substrate of liquid crystal display

The invention discloses an array substrate of a liquid crystal display. The array substrate includes a storage capacitor which comprising the first common electrode, the first insulating layer disposed on the first common electrode, a pixel electrode disposed on the first insulating layer, the second insulating layer disposed on the pixel electrode and the second common electrode disposed on the second insulating layer. The second common electrode includes a plurality of slits, and electorally connected to the first common electrode. The array substrate of this invention could increase the storage capacitor per unit area, and is suitable for high-resolution liquid crystal display.

Display array substrate and manufacturing method thereof

A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.

Thin film transistor, method of manufacturing the thin film transistor and array substrate

A method of manufacturing a thin film transistor includes: forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor layer, a blocking layer and a photoresist layer orderly above the gate insulating layer; patterning the photoresist layer to form a photoresist pattern with a first part and a second part in staircase structure, wherein the height of the first part is higher than the height of the second part, and the second part includes at least two opposite parts disposed on two side of the first part; removing the semiconductor layer and the blocking layer exposed from the photoresist pattern to form a channel; removing the second part to expose part of the blocking layer; removing the blocking layer corresponding to the second part to form a etching stop layer; removing the rest of the photoresist pattern; then forming a drain electrode and a source electrode disposed on opposite sides of the etching stop layer, respectively ...

Thin film transistor substrate and manufacturing method thereof

THIN FILM TRANSISTOR OF ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a thin film transistor (TFT), the TFT includes a gate, a first insulation layer, a channel layer, a source, a drain, a second insulation, and a flat layer. The gate is formed on a base. The first insulation layer is formed on the base to cover the gate and the base. The channel layer is formed on the first insulation layer corresponding to the gate. The second insulation layer is formed on the base to cover the first insulation layer, the channel layer, the source, and the drain. The flat layer includes a first region and a second region and is formed on the second insulation layer. The first region and the second region respectively have different light transmittance. 1. A method for manufacturing a thin film transistor comprising:forming a gate on a base;forming a first insulation layer on the base to cover the gate;forming a channel layer on the first insulation layer corresponding to the gate;forming a source and a drain respectively coupled with opposite sides of the channel layer;forming second insulation layer on the base to cover the first insulation layer, the channel layer, the source, and the drain; andforming a flat layer having a first region and a second region on the second insulation layer, wherein the first region and the second region respectively have different light transmittance.2. The method according to claim 1 , wherein forming a flat layer having a first region and a second region on the second insulation comprises:forming a layer of organic materials on the second insulation layer; andexposing the organic materials by ultraviolet light using a photomask from a side of the flat layer away from the base to form the flat layer having the first region and the second region.3. The method according to claim 2 , wherein the photomask is located corresponding to prevent the channel layer from being exposed by the UV light.4. The method according to claim 3 , wherein the first region is corresponding to the channel layer ...

Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same

一種薄膜電晶體及其製作方法，以及包括該薄膜電晶體之液晶顯示面板。薄膜電晶體包括金屬材料的閘極及覆蓋該閘極之閘極絕緣層。該閘極絕緣層為包含有矽元素、氧元素及氮元素的混合物，該混合物中的氧原子的濃度與氮原子的濃度比值小於3。

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide. 1. An array substrate comprising:a substrate;a first TFT formed on the substrate, the first TFT comprising a first channel layer formed on the substrate, a first gate insulator layer formed on the substrate and covering the first channel layer, a first gate electrode formed on the first gate insulator layer, a first dielectric layer formed on the first gate insulator layer and covering the first gate electrode, a second dielectric layer formed on the first dielectric layer; and a first source electrode and a first drain electrode formed on the second dielectric layer to electrically couple to the first channel layer;a second TFT formed on the substrate, the second TFT comprising a second gate insulator layer formed on the substrate, a second gate electrode formed on the second gate insulator layer, a third dielectric layer formed on the second gate insulator layer and covering the second gate electrode, a second channel layer formed on the third dielectric layer, and a second source electrode and a second drain electrode formed on the third dielectric layer to electrically couple to the second channel layer; anda third TFT formed on the substrate, the third TFT comprising a third gate insulator layer formed on the ...

Tft array substrate, display panel, display device and method for making the tft array substrate

Thin film transistor and thin film transistor substrate

Thin film transistor substrate, method of manufacturing same and a liquid crystal display with same

The present invention provides a thin film transistor substrate, a method for manufacturing the thin film transistor substrate, and a liquid crystal display with the thin film transistor substrate. The manufacturing method for the thin film transistor substrate includes following steps: forming a thin film transistor on a substrate, and putting the substrate having the thin film transistor into a high pressure environment which has a pressure higher than a standard atmospheric pressure to increase the oxygen ions of thin film transistor substrate. The stable conductivity of the thin film transistor is thus improved by the increase of the oxygen ions of the thin film transistor.

Thin film transistor array panel and conducting structure

A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

Thin film transistor and display array substrate using same

A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Array substrate and display device and method for making the array substrate

An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.

Thin film transistor substrate and manufacturing method thereof

The present invention provides a thin film transistor substrate includes a substrate; and a plurality of TFT on the substrate. Each of the plurality of TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer; and an ohmic contact layer between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc, the channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%. The present invention also provides a method for manufacturing the thin film transistor substrate. The thin film transistor substrate of the present invention can reduce the resistance between the channel layer and the source, and the resistance between the channel layer and the drain, so that the electrical connection between the channel layer and the source, and between ...

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE

A thin film transistor array panel includes a first conductive layer () including a gate electrode; a channel layer () disposed over the gate; and a second conductive layer () disposed over the channel layer (). The second conductive layer () includes a multi-layered portion defining a source electrode () and a drain electrode (), which includes a first sub-layer (-), a second sub-layer (-), and a third sub-layer (-) sequentially disposed one over another. Both the third and the first sub-layers (--) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (-) is greater than that in the third sub-layer (-). The content ratio differentiation between the first and the third sub-layers (--) affects a lateral etch profile associated with a gap () generated in the second conductive layer () between the source and the drain electrodes (), where the associated gap () width in the third sub-layer (-) is wider than that in the first sub-layer (-). 122-. (canceled)24. The thin film transistor array panel of claim 23 , wherein the first metal is indium; and the second metal is zinc.25. The thin film transistor array panel of claim 24 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%.26. The thin film transistor array panel of claim 25 , wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 25% to about 80%.27. The thin film transistor array panel of claim 26 , wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 45% to about 70%.28. The thin film transistor array panel of claim 25 , wherein the indium-to-zinc content ratio in the third sub-layer is in a range from about 5% to about 40%.29. The thin film transistor array panel of claim 28 , wherein the indium-to-zinc content ratio in the third sub-layer is a in range from about 10% to about 35%.30. The thin film transistor array panel of claim ...

Method for making thin film transistor array panel

A method for making a thin film transistor array panel, which includes: forming a first sub-layer over a channel layer, the first sub-layer including a conductive metal oxide material containing indium and zinc; forming a second sub-layer on the first sub-layer, the second sub-layer including a metal material; forming an third sub-layer on the second sub-layer, the third sub-layer including a conductive metal oxide material containing indium and zinc; the first sub-layer, the second sub-layer and the third sub-layer cooperatively form a second conductive layer, and patterning the second conductive layer to form a gap passing through the first sub-layer, the second sub-layer and the third sub-layer. A source and a drain are formed by opposite sides of the gap. The gap gradually decreases along a direction from the third sub-layer to the first sub-layer.

Thin film transistor and method for manufacturing same

THIN FILM TRANSISTOR UTILIZED IN ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY

Method for manufacturing a thin film transistor liquid crystal display is provided. A substrate is provided. A gate electrode, a source electrode, a drain electrode, and a passivation film are formed on the substrate in sequence. The passivation film has a contact hole to expose a part of the drain electrode. A conductive layer is formed by coating nano metal material on the passivation film and in the contract hole from which the drain electrode is exposed. A pixel electrode is formed by patterning the conductive layer. 1. A method for fabricating a thin film transistor (TFT) liquid crystal display , the method comprising:providing a substrate;forming a gate electrode, a source electrode, a drain electrode, and a passivation film on the substrate in sequence, the passivation film having a contact hole to expose a part of the drain electrode;forming a conductive layer by coating nano metal material on the passivation film and the part of the drain electrode exposed from the contract hole; andforming a pixel electrode by patterning the conductive layer.2. The method of claim 1 , wherein the nano metal materiel is nano particles or nano wires.3. The method of claim 2 , wherein the nano metal materiel is made of silver or copper.4. The method of claim 2 , wherein the nano particles or nano wires each have a dimension between 1 nanometer to 50 nanometers.5. The method of claim 1 , wherein the gate electrode claim 1 , the source electrode claim 1 , the drain electrode claim 1 , and the passivation film on the substrate are performed via independent photo-mask processes claim 1 , respectively.6. The method of claim 1 , wherein the step of forming a pixel electrode is performed by a photo-mask process claim 1 , in which a fifth mask and a fifth photo-resist layer are provided for covering the conductive layer.7. The method of claim 6 , wherein a predetermined pattern according to the fifth mask is formed on the fifth photo-resist layer after an exposure and development ...

THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer. 1. A thin film transistor array panel , comprising:a first conductive layer including a gate electrode;a channel layer disposed over the gate electrode and insulated from; and a first sub-layer arranged in electrical contact with the channel layer,', 'a second sub-layer disposed over the first sub-layer, and', 'a third sub-layer disposed over the second sub-layer;, 'a second conductive layer disposed over the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein the multi-layered portion of the second conductive layer comprises at leastwherein each of the third and the first sub-layers comprises a metal oxide material containing indium and zinc,wherein an indium to zinc content ratio in the first sub-layer is greater than an indium to zinc content ratio in the third sub-layer,wherein the indium to zinc content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between ...

Thin film transistor substrate, method of manufacturing thin film transistor substrate, display panel, and thin film transistor structure

The present invention provides a thin film transistor substrate. The thin film transistor substrate includes a number of gate lines and a number of source lines interleaving with the gate lines. The gate lines include a number of first gate lines. The source lines include a number of first source lines and a number of second source lines. The first source lines are insulated and overlapped from the second source lines. A first transistor and a second transistor are formed on a junction of a first gate line, a first source line and a second source line. The first transistor is coupled to the first gate line and the first source line. The second transistor is coupled to the first gate line and the second source line.

Tft array substrate, display panel, display device and method for making the tft array substrate

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING SAME

A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided. 1. A method for manufacturing a thin film transistor comprising:providing a substrate;forming, successively, a first metal layer, a second metal layer and a first photoresist layer on the substrate;patterning the first photoresist layer to form a first photoresist pattern comprising a first margin photoresist pattern and first middle photoresist pattern spaced apart from the first margin photoresist pattern;etching the first metal layer and the second metal layer to form a first margin metal layer corresponding to the first margin photoresist pattern, a second margin metal layer corresponding to the first margin photoresist pattern, a first middle metal layer corresponding to the first middle photoresist pattern, and a second middle metal layer corresponding to the first middle photoresist pattern;removing the first middle photoresist pattern;removing the second middle metal layer;removing the first margin photoresist pattern;forming a semiconductor layer covering the substrate, the second margin metal layer, and the first middle metal layer;removing a part of the semiconductor layer which covers the substrate to form a margin semiconductor layer on the second margin metal layer and a middle semiconductor layer on the first middle metal layer;forming a third metal layer covering the substrate, the margin semiconductor layer and the middle semiconductor layer;forming a second photoresist pattern on the third metal layer and ...

Thin film transistor display array substrate using same

The present invention provides a thin film transistor. The thin film transistor includes a gate electrode and a gate insulation layer covers the gate electrode. A channel layer is arranged on the gate insulation layer corresponding to the gate electrode. An etching stop layer covers the channel layer. The etching stop layer includes an organic stop layer and a hard mask arranged on the organic stop layer. The organic stop layer is a solidified layer which is formed with transparent organic material. The hard mask is arranged on a side of the organic stop layer opposite to the channel layer to increase a hardness of the etching stop layer. Two contact holes penetrate the etching stop layer. A source electrode and a drain electrode contact with the channel layer via the two contact holes. The present invention also provides a display array substrate using the thin film transistor.

Method for manufacturing array substrate and array substrate manufactured by the method

Thin film transistor and method of manufacturing same

A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.

METHOD FOR FABRICATING CONDUCTING STRUCTURE AND THIN FILM TRANSISTOR ARRAY PANEL

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile. 121-. (canceled)22. A thin film transistor array panel , comprising:a substrate;a first conductive layer on the substrate and comprising a gate electrode;a channel layer on the gate electrode and insulated there-from; and a first sub-layer on the channel layer and in electrical contact with the channel layer,', 'a second sub-layer on the first sub-layer, and', wherein each of the third sub-layer and the first sub-layer comprises a metal oxide material containing hydrogen;', 'wherein a gap is in the second conductive layer and between the source electrode and the drain electrode; the gap extends through the first sub-layer, the second sub-layer, and the third sub-layer; and', 'wherein a gap width in the third sub-layer is wider than a gap width in the first sub-layer., 'a third sub-layer on the second sub-layer;'}], 'a second conductive layer on the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein ...

In-cell touch LCD display panel

The present disclosure relates to an in-cell touch liquid crystal display panel. The in-cell touch liquid crystal display panel includes a color filter substrate, a thin film transistor substrate, a liquid crystal layer and a touch electrode layer. The liquid crystal layer and the touch electrode layer are sandwiched between the color filter substrate and the thin film transistor substrate. The in-cell touch liquid crystal display panel further includes an electrostatic protective layer. The touch electrode layer is formed on the thin film transistor substrate. The electrostatic protective layer is formed on the color filter substrate. The in-cell touch liquid crystal display panel has a good touch-sensing performance.

THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING SAME AND A LIQUID CRYSTAL DISPLAY WITH SAME

Thin film transistor array substrate and the liquid crystal display panel

Thin film transistor array panel

A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).

Thin film transistor array panel

A thin film transistor array panel includes a second conductive layer. The second conductive layer defines a source electrode and a drain electrode, and includes: a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The first sub-layer including a conductive metal oxide material containing indium and zinc; the second sub-layer formed on the first sub-layer; the third sub-layer formed on the second sub-layer, the third sub-layer including a conductive metal oxide material containing indium and zinc. The additional sub-layer is formed between the first sub-layer and the second sub-layer. A gap is defined in the second conductive layer and passes through the first sub-layer, the second sub-layer, the third sub-layer, and the additional sub-layer. A source and a drain are formed by opposite sides of the gap.

Thin film transistor with two gates protruding from scan line under a double-layer channel

A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.

TFT array substrate, display panel, display device and method for making the TFT array substrate

A TFT array substrate includes a substrate, a first TFT on the substrate, and a second TFT on the substrate. The first TFT has a first channel layer on the substrate, and the first channel layer is made of doped polysilicon. The second TFT has a second channel layer made of metal oxide. The TFT array substrate includes a third insulator layer and defines a source hole and a drain hole through the third insulator layer, and the third insulator layer between the source hole and drain hole forms a protection area. A display panel and a display device using the TFT array substrate and method for making the TFT array substrate are also provided. The protection are can effectively protect the second channel layer.

Thin film transistor substrate and method for making same

A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.

SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME

A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer. 1. A thin film transistor comprising:a substrate;a gate electrode formed on the substrate;an electrically insulating layer formed on the substrate and covering the gate electrode;a channel layer made of a semiconductor material and formed on the electrically insulating layer;a source electrode formed on a first lateral side of the electrically insulating layer, the source electrode having an inner end covering a first outer end of the channel layer and electrically connecting therewith; anda drain electrode formed on an opposite second lateral side of the electrically insulating layer, the drain electrode having an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith;wherein an area of the channel layer adjacent to one of the source electrode and the drain electrode and not covered thereby has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.2. The thin film transistor of claim 1 , wherein the area of the channel layer which has a lower electrical conductivity is ...

In-cell touch display apparatus

An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.

Tft array substrate, display device and method for making the tft array substrate

Method for manufacturing array substrate and array substrate manufactured by the method

The present invention provides a method for manufacturing an array substrate. The method includes the following steps: providing a thin film transistor (TFT) is provided, wherein the thin film transistor includes a channel layer; forming a insulation layer to cover the TFT; and exposing the insulation layer by UV light and using a shelter to shield the channel layer, so that a portion of the insulation layer which is not shielded by the shelter has been changed from translucence to transparency.

Thin film transistor array panel and method for making same

A method of making a thin film transistor array panel includes: forming a first sub-layer on a channel layer, the first sub-layer including a conductive metal oxide material containing indium and zinc; forming a second sub-layer on the first sub-layer, the second sub-layer including a metal material; forming an third sub-layer on the second sub-layer, the third sub-layer including a conductive metal oxide material containing indium and zinc, the first sub-layer, the second sub-layer and the third sub-layer form a second conductive layer and patterning the second conductive layer to generate a groove composite lateral etch profile, forming a passivation layer on the exposed region of the second conductive layer and the channel layer. A lateral byproduct layer is formed on the side wall of the groove during the forming of the passivation layer. The lateral byproduct layer includes substantially oxide of the metal material in the second sub-layer.

TFT array substrate, display panel, display device and method for making the TFT array substrate

A TFT array substrate includes a substrate, a first TFT on the substrate, and a second TFT on the substrate. The first TFT is a metal oxide TFT, the second TFT is a polysilicon TFT. The first TFT has a buffer layer, a gate, and a gate insulator layer formed on the substrate orderly. The first TFT further includes a source and a drain formed on the gate insulator layer, and a metal oxide semiconductor layer formed on the gate insulator layer and opposite to the gate. The metal oxide semiconductor layer partially covers the source and the drain. A display panel and a display device using the TFT array substrate and method for making the TFT array substrate are also provided. The metal oxide semiconductor layer formed after the forming of the source and the drain, which can effectively protect the metal oxide semiconductor layer.

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MAKING SAME

ARRAY SUBSTRATE AND METHOD FOR MAKING SAME

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole. 1. An array substrate comprising:a substrate;a first insulator layer formed on the substrate;a second insulator layer formed on the first insulator layer;a third insulator layer formed on the second insulator layer;a first TFT formed on the substrate, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer and electrically coupled to the first channel layer;a storage capacitance layer formed on the substrate; anda second TFT formed on the substrate, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer and electrically coupled to the second channel layer;the first insulator layer covering the first channel layer and the storage capacitance layer; the second insulator layer covering the first gate electrode and the second gate electrode;wherein the first channel layer and the storage capacitance layer are made of a semiconducting material containing polycrystalline silicon; the second channel layer is made of a semiconducting material containing metal oxide; the third ...

Array substrate and display device and method for making the array substrate

A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.

Vertical transistor and method for manufacturing same

Thin film transistor array panel and method for making same

Array substrate and liquid crystal display device using same

An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.

Thin film transistor and display array substrate utilizing the thin film transistor

Disclosed is a thin film transistor (TFT) which includes a gate, a source, a drain, and a channel layer. The TFT further includes a shielding layer located at a same layer with the source and drain. The shielding layer is located between the source and the drain and separated from the source and the drain to prevent lights from passing through the channel layer, so as to improve the stability of the TFT.

Thin film transistor and method for manufacturing same

The present invention provides a thin film transistor. The thin film transistor includes a gate electrode, a gate insulation layer, a channel layer, a source electrode, and a drain electrode. The gate insulation layer covers the gate electrode. The channel layer is formed on the gate insulation layer corresponding to the gate electrode. The source electrode and the drain electrode are formed on the gate insulation layer and the channel layer, and cover two opposite sides of the channel layer respectively. The channel layer includes a second electric conductivity portion and two first electric conductivity portions. An electric conductivity of each of the first electric conductivity portions is lower than an electric conductivity of the second electric conductivity portion.

Thin film transistor array substrate and method for making same

A thin film transistor array substrate includes an insulating substrate, a semiconducting layer formed on the insulating substrate, and a second conductive layer on the semiconducting layer. The second conductive layer defines a source and a drain apart from the source. The second conductive layer includes a first layer formed on the semiconducting layer and a second layer formed on the first layer. The first layer is made of metal oxide, and the second layer is made of aluminum or aluminum alloy. A method for making the thin film transistor array substrate is also provided. The first layer is used as an ohmic contact layer between the semiconducting layer and the second layer.

Thin film transistor and method of making same

A method for forming a TFT includes providing a substrate, and forming a gate electrode, an electrically insulating layer, a semiconductor layer, an etch stop layer and a photoresist layer successively on the substrate. A photolithographic process is performed to the photoresist layer by using a half-tone mask to thereby configure the photoresist layer to have two recesses in a top thereof. Two lateral ends of the etch stop layer are etched away to form an etch stop pattern. The photoresist layer is heated to flow downwardly. Two lateral ends of the semiconductor channel are etched away to become a channel layer. An ashing is performed to the photoresist layer to have the recesses thereof communicate atmosphere with the etch stop pattern. The etch stop pattern is etched to define first and second through holes. Source and drain electrodes are formed to electrically connect with the channel layer.

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

Thin film transistor array panel

Thin film transistor substrate, method of manufacturing thin film transistor substrate, display panel, and thin film transistor structure

Thin film transistor and manufacturing method thereof

The present invention relates to a thin film transistor. The thin film transistor includes a substrate, a gate electrode arranged on the substrate, a gate insulating layer covering the gate electrode, a channel layer arranged on the gate insulating layer, an etching stop layer arranged on the channel layer. The etching stop layer defines a first through hole and a second through hole. A source electrode is arranged on the etching stop layer to connect the channel layer via the first through hole. The source electrode extends to an outside of the gate insulating layer along the etching stop layer. A drain electrode is arranged on the etching stop layer to connect the channel layer via the second through hole. The drain electrode extends to other outside of the gate insulating layer.

Self-aligned metal oxide thin film transistor and method of making same

A method for forming a TFT includes providing a substrate, a gate electrode on the substrate, an electrically insulating layer on the substrate to totally cover the gate electrode, a channel layer on the electrically insulating layer, a first photoresist pattern on the channel layer, a metal layer on the electrically insulating layer, the channel layer and the first photoresist layer, and a second photoresist pattern on the metal layer. A middle portion of the metal layer is then removed to form a source electrode and a drain electrode and to expose the first photoresist pattern and a portion of the channel layer between the first and second photoresist patterns. The exposed portion of the channel layer is then processed to have its electrical conductivity be lowered to thereby reduce a hot-carrier effect of the channel layer.

Semiconductor substrate, array substrate, inverter circuit, and switch circuit

The present disclosure provides a semiconductor substrate including a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate. The first thin film transistor is a metal oxide thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor; the first thin film transistor includes a first source and a first drain, and the second thin film transistor includes a second source and a second drain. One of the first source or the first drain is electrically connected to one of the second source or the second drain. The semiconductor substrate of the present disclosure includes a metal oxide thin film transistor, and the metal oxide thin film transistor share a same source/drain with the low temperature polycrystalline silicon thin film transistor, which can reduce the volume and leakage current of the electronic component using the semiconductor substrate.

Method of manufacturing thin film transistor

A method of manufacturing a thin film transistor substrate is provided, including a first photoresist pattern covers a channel during a process of etching a second photoresist pattern and protects the channel. Thus, an etching stop layer is not required.

Thin film transistor, method of manufacturing the thin film transistor and aaray substrate

Thin film transistor array substrate and the liquid crystal display panel

The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate includes a base substrate, a gate electrode formed on the base substrate, a insulating layer of the gate electrode covering the base substrate and the gate electrode, an active layer formed on the insulating layer of the gate electrode corresponding to the gate electrode, an etch stop layer covering the active layer and the insulating layer of the gate electrode, a source electrode, a drain electrode and a passivation layer. The source electrode and the drain electrode are formed on the etch stop layer and the active layer away from each other. The passivation layer is formed on the etch stop layer, the source electrode and the drain electrode. The etch stop layer is a color resist.

Tft array substrate, display device and method for making the tft array substrate

TFT array substrate, display device and method for making the TFT array substrate

A TFT array substrate includes a substrate, a plurality of first TFTs, a plurality of second TFTs, and a third TFTs on the substrate. Each first TFT is a polysilicon TFT and has a first dielectric layer formed on the substrate and a second dielectric layer formed on the first dielectric layer. Both of the second TFT and the third TFT are metal oxide TFTs. Each second TFT has a third dielectric layer formed on the substrate. Each third TFT has a fourth dielectric layer formed on the substrate. The first dielectric layer is made of silicon nitride; the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are silicon dioxide. A display device using the TFT array substrate and method for making the TFT array substrate are also provided. The second TFTs and the third TFTs avoid using silicon nitride.

Thin film transistor array substrate and liquid crystal display panel using same

A thin film transistor (TFT) array substrate of a liquid crystal display (LCD) panel includes a first substrate, a gate located on the first substrate, a gate insulation layer located on the first substrate and covers the gate and the first substrate, a source layer located on the gate insulation layer to correspond to the gate, an etching stopping layer located on the source layer, and a source and a drain located on the etching stopping layer. The etching stopping layer is made of color photoresist.

Thin film transistor and display array substrate utilizing the thin film transistor

Thin film transistor and method of making same

A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. 1. An array substrate comprising:a substrate;a driving circuit formed on the substrate;a pixel array formed on the substrate having a plurality of pixel units, each of the plurality of pixel units comprising a light emitting diode, a switch TFT, and a driving TFT, the switch TFT being electrically connected between the driving circuit and the driving TFT; andwherein the driving TFT comprises a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and both a source electrode and a drain electrode coupled to the metal oxide semiconductor layer of the driving TFT; andwherein the switch TFT comprises a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode both coupled to the metal oxide semiconductor layer of the switch TFT.2. The array substrate of claim 1 , further comprising at least one poly-silicon TFT claim 1 , each poly-silicon TFT comprises a poly-silicon semiconductor layer claim 1 , a buffer layer claim 1 , a gate electrode claim 1 , a first gate insulator layer claim 1 , a second gate insulator layer stacked on the substrate in that order claim 1 , and a source electrode and a drain electrode passing through the ...

Thin film transistor array panel and conducting structure

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

Array substrate and display device and method for making the array substrate

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

Thin film transistor array panel

THIN FILM TRANSISTOR SUBSTRATE, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY PANEL USING SAME

A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure. 1. A method for manufacturing a thin film transistor (TFT) substrate comprising:forming a TFT on a substrate, the TFT comprising a gate, a source, a drain, and a channel layer, wherein the source and the drain respectively are located at opposite sides of the channel layer;forming a passivation layer on the TFT; andperforming an oxygen implanting process to implant oxygen ions into the channel layer in an environment having an air pressure greater than a standard atmospheric pressure.2. The method according to claim 1 , wherein the environment is an annealing chamber.3. The method according to claim 2 , wherein the air pressure in the annealing chamber is between two times the standard atmospheric pressure and seven times the standard atmospheric pressure.4. The method according to claim 2 , wherein the air pressure in the annealing chamber is between three times the standard atmospheric pressure and five times the standard atmospheric pressure.5. The method according to claim 2 , wherein a temperature in the annealing chamber is between 200 degrees centigrade and 500 degrees centigrade.6. The method according to claim 5 , wherein the temperature in the annealing chamber is 350 degrees centigrade.7. The method according to claim 2 , wherein an oxygen ion concentration in the annealing chamber is between 20% and 50%.8. A thin film transistor (TFT) substrate comprising:a substrate;a TFT formed on the substrate, the TFT comprising a gate, a source, a drain, and a channel layer, wherein ...

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING SAME

A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided. 1. A method of manufacturing a thin film transistor , the method comprising:providing a substrate;successively forming a gate electrode and an electrically insulating layer on the substrate;forming an electric conducting layer on the electrically insulating layer;forming a first photoresist layer on the electric conducting layer;photolithographing the first photoresist layer from a top face and a bottom face by using a photo mask as a top face photo mask and the gate electrode as a bottom face photo mask to form a first photoresist pattern layer;etching a portion, which is not covered by the first photoresist pattern layer, of the electric conducting layer to form an electric conduction layer;forming a semiconductor layer on the electric conduction layer;forming a second photoresist layer on the semiconductor layer;photolithographing the second photoresist layer from a top face and a bottom face using the photo mask as a top face photo mask and the gate electrode as a bottom face photo mask to form a second photoresist pattern layer;etching a portion, ...

Array substrate and display device and method for making the array substrate

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

Semiconductor substrate, array substrate, inverter circuit, and switch circuit

Vertical transistor and method for manufacturing same

The present invention provides a method for manufacturing a vertical transistor. The vertical transistor includes a transparent substrate, two gate electrodes, a source electrode, a channel, and a drain electrode. The two gate electrodes and the source electrode are formed on the transparent substrate. The source electrode is between the two gate electrodes. The channel is formed on the source electrode. The drain electrode is formed on the channel. The method can manufacture the vertical transistor with just two masks.

Thin film transistor and manufacturing method thereof

A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.

Touch panel and manufacturing method thereof

Method of manufacturing thin film transistor

A method of manufacturing a thin film transistor includes the following steps: forming a gate electrode and a gate insulating layer orderly above the substrate; forming a conductive layer above the gate insulating layer; forming a first photoresist layer above the conductive layer; using a photomask as front side mask while the gate electrode as the back side mask to expose the first photoresist layer to light simultaneously to form a first photoresist pattern; removing the conductive layer exposed from the first photoresist pattern to form conductive channel layer; forming a semi-conductive layer and a second photoresist layer orderly above the conductive channel layer; using the said photo photomask as front side mask while the gate electrode as the back side mask to expose the second photoresist layer to light simultaneously to form a second photoresist pattern; removing the semi-conductive layer exposed from the second photoresist pattern to form semi-conductive channel layer; then ...

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode. 1. An array substrate comprising:a substrate;a first TFT on the substrate, the first TFT being a metal oxide TFT; anda second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT; the metal oxide semiconductor layer partially covers the source electrode and the drain electrode of the first TFT.2. The array substrate of claim 1 , wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed; the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.3. The array substrate of claim 2 , wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the ...

Manufacturing method of thin film transistor, and display array substrate using same

The present invention provides a manufacturing method of thin-film transistor. The method includes forming a gate electrode on a substrate and a gate insulation layer on the gate electrode. Forming a channel layer on the gate insulation layer corresponding to the gate electrode and coating a etching stop layer on the channel layer. Hard-baking the etching stop layer. Coating photoresistor layer on the etching stop layer. Patterning the photoresistor layer to develop two through holes. Forming two contact holes by etching the etching stop layer to the channel to the channel layer. Removing the photoresistor remained and forming a source electrode and a drain electrode on the two contact holes.

THIN FILM TRANSISTOR AND ARRAY SUBSTRATE HAVING SAME

A thin film transistor includes a gate, a source, a drain, a channel layer, and a shielding layer. The shielding layer, the source, and the drain are located on a same layer. The shielding layer is located on the channel layer and is between the source and the drain to prevent light from being transmitted to the channel layer. 1. A thin film transistor , comprising a gate , a source , a drain , a channel layer , and a shielding layer , wherein the shielding layer , the source , and the drain are located on the channel layer , and the shielding layer is located between the source and the drain and is separated from the source and the drain.2. The thin film transistor according to claim 1 , wherein the shielding layer is made of the same materials with the source and the drain.3. The thin film transistor according to claim 2 , wherein the shielding layer claim 2 , the source claim 2 , and the drain are formed in a same photo etching process.4. The thin film transistor according to claim 1 , wherein the a total distance of a first distance between the source and the shielding layer and a second distance between the drain and the shielding layer is less than a half of a distance between the source and the drain.5. The thin film transistor according to claim 4 , wherein the first distance between the source and the shielding layer is identical to the second distance between the drain and the shielding layer.6. The thin film transistor according to claim 1 , wherein the channel layer is made of materials having light sensitivity performance.7. The thin film transistor according to claim 6 , wherein the channel layer is made of metal oxide materials.8. The thin film transistor according to claim 1 , further comprising an etching stopping layer located on a surface of the channel layer to separate the source from drain.9. The thin film transistor according to claim 8 , wherein the etching stopping layer defines two contact holes to expose a portion of the channel layer ...

THIN FILM TRANSISTOR ARRAY PANEL

A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.

ARRAY SUBSTRATE AND METHOD FOR MAKING SAME

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole. 1. A method for making an array substrate comprising:forming a polycrystalline silicon layer on a substrate;doping the polycrystalline silicon with N-type ion or P-type ion;patterning the doped polycrystalline silicon to form a first channel layer and a storage capacitance layer and doping the first channel layer and the storage capacitance layer;forming a first insulator layer on the substrate, the first insulator layer covering the first channel layer and the storage capacitance layer;forming a first gate electrode and a second gate electrode on the first insulator layer, the first gate electrode corresponding to the first channel layer;doping the first channel layer;forming a second insulator layer on the first insulator layer, the second insulator layer covering the first gate electrode and the second gate electrode;forming a second channel layer on the second insulator layer, the second channel layer overlapping the second gate electrode and being made of a semiconducting material containing metal oxide;forming a third insulator layer on the second insulator layer and defining a first source hole, a first drain hole, a second source hole, and a second drain hole in the third insulator layer; the first source hole and the first drain hole overlapping the first channel layer and extending through the third insulator layer, the second insulator layer, and the first insulator layer; the second ...

METHOD OF MANUFACTURING THIN FILM TRANSISTOR

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT. 1. A method for making an array substrate comprising:forming a poly-silicon semiconductor layer on a substrate;forming a buffer layer on the substrate and covering the poly-silicon semiconductor layer;depositing a first metal layer and patterning the first metal layer to form a first gate electrode for a driving TFT, a second gate electrode for a switch TFT, and a third gate electrode for a poly-silicon TFT, the third gate electrode overlapping with the poly-silicon semiconductor layer;forming a first gate insulator layer covering the third gate electrode and the first gate electrode;forming a second gate insulator layer covering the first gate insulator layer and the second gate electrode;defining a first through hole and a second through hole in the second gate insulator layer, the first through hole and the second through hole passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer;depositing a metal oxide layer on the second gate insulator layer and patterning the metal oxide layer to form a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, the first metal ...

THIN FILM TRANSISTOR ARRAY PANEL

A semiconductor device comprises a multi-layered structure disposed over a substrate () and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (-) disposed over the substrate () and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (-) substantially defining a first indium to zinc content ratio; a middle sub-layer (-) disposed over the lower sub-layer (-) and comprising a metal material; an upper sub-layer (-) disposed over the middle sub-layer (-) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (-) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (-). 128-. (canceled)30. The thin film transistor array panel of claim 29 , wherein the lateral byproduct layer is substantially free from reaching a lower layer boundary defined by the first sub-layer.31. The thin film transistor array panel of claim 29 , wherein a gap width in the third sub-layer is wider than a gap width in the first sub-layer.32. The thin film transistor array panel of claim 29 , wherein each of the first sub-layer and the third sub-layer comprises a metal oxide material containing indium and zinc; wherein an indium-to-zinc content ratio in the first sub-layer is greater than an indium-to-zinc content ratio in the third sub-layer.33. The thin film transistor array panel of claim 32 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%.34. The thin film transistor array panel of claim 33 , wherein the indium-to-zinc content ratio differentiation between the first sub-layer and the third sub-layer affects a generation of a ...

THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE

A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer. 128-. (canceled)29. A thin film transistor array panel , comprising:a substrate;a first conductive layer on the substrate and comprising a gate electrode;a channel layer on the gate electrode and insulated there-from; and a first sub-layer on the channel layer and in electrical contact with the channel layer,', 'a second sub-layer on the first sub-layer,', 'a third sub-layer on the second sub-layer, and', 'at least one additional sub-layer between the first sub-layer and the second sub-layer,', 'wherein each of the first sub-layer, the third sub-layer, and the additional sub-layer comprises a metal oxide material containing indium and zinc;', 'wherein an indium-to-zinc content ratio in the first sub-layer is greater than an indium-to-zinc content ratio in the third sub-layer;', 'wherein an indium content in the first sub-layer is greater than an indium content in the at least one additional sub-layer;', 'wherein a gap is in the second conductive layer and between the source electrode and the drain electrode; the gap extends through the first sub-layer, the second sub-layer, and the third sub- ...

SENSING DEVICE

A sensing device includes a light-emitting panel and a sensing pixel array structure. The light-emitting panel is adapted to emit an initial light with a first waveform. The sensing pixel array structure includes a plurality of first sensing pixel structures and at least one second sensing pixel structure. The first sensing pixel structures provide the initial light with the first waveform as a first sensing light to a first sensing element for sensing. The first sensing pixel structures occupy 90% or more but less than 100% of a configuration area of the overall sensing pixel array structure. The second sensing pixel structure includes a second sensing element and a light conversion layer. The second sensing pixel structure is adapted to adjust the initial light with the first waveform to a second sensing light with a second waveform to be sensed by the second sensing element. 1. A sensing device , comprising:a light-emitting panel adapted to emit an initial light with a first waveform; anda sensing pixel array structure located on a back side of the light-emitting panel, wherein{'claim-text': ['a plurality of first sensing pixel structures, wherein each of the first sensing pixel structures comprises a first sensing element, and each of the first sensing pixel structures provides the initial light with the first waveform as a first sensing light to the first sensing element for sensing, wherein a ratio of the plurality of first sensing pixel structures in a configuration area of an overall sensing pixel array structure is 90% or more but less than 100%; and', 'at least one second sensing pixel structure, wherein the at least one second sensing pixel structure comprises a second sensing element and a light conversion layer, the light conversion layer is located between the second sensing element and the light-emitting panel, the at least one second sensing pixel structure is adapted to adjust the initial light with the first waveform to a second sensing light to be ...

IN-CELL TOUCH DISPLAY APPARATUS

An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus. 1. An in-cell touch display apparatus comprising:a thin film transistor (TFT) array structure with a touch electrode layer and a grounded portion;a color filter structure oppositely facing the TFT array structure;a liquid crystal layer between the color filter structure and the TFT array structure;a sealant between the color filter structure and the TFT array structure, and sealing the liquid crystal layer;wherein the color filter structure comprises an anti-ESD protection layer; the anti-ESD protection layer directly contacts the sealant; the anti-ESD protection layer, the sealant, and the ground portion form an electro statics discharge (ESD) path to discharge electrostatic charges in the in-cell touch display apparatus; the anti-ESD protection layer discharges the electrostatic charges in the in-cell touch display apparatus to the ground portion.2. The in-cell touch display apparatus of claim 1 , wherein the color filter structure comprises a first substrate and a color filter layer located between the first substrate and the liquid crystal layer; wherein the anti-ESD protection layer is between the first substrate and the color filter layer.3. The in-cell touch display apparatus of claim 2 , wherein the anti-ESD protection layer comprises an extending portion; the extending portion extends out of an ...

THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MAKING SAME

A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%. 1. A thin film transistor (TFT) substrate comprising:a substrate; anda plurality of TFT on the substrate,each of the plurality of TFT comprising:a channel layer;a source electrode and a drain electrode on opposite sides of the channel layer; andan ohmic contact layer between the channel layer and the source electrode, and between the channel layer and the drain electrode;wherein both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc, the channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.2. The TFT substrate of claim 1 , wherein the channel layer is made of indium-gallium-zinc oxide (IGZO) claim 1 , and the ohmic contact layer is made of indium-zinc oxide (IZO).3. The TFT substrate of claim 2 , wherein a ratio of the number of indium atoms to zinc atoms in the channel layer is in a range from about 1:1 to about 2:1; and a ratio of the number of indium atoms to zinc atoms in the ohmic contact layer is in a range from about 9:20 to about 7:10.4. The TFT substrate of claim 1 , wherein the source electrode and the drain electrode are spaced apart from each other by a groove claim 1 , the groove extends through the ohmic contact layer to expose the channel layer.5. The TFT substrate of claim 4 , wherein the groove tapers along a direction facing towards the channel layer.6. The TFT substrate ...

Manufacturing method of thin film transistor and display array substrate using same

A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING SAME

A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided. 1. A thin film transistor comprising:a substrate;a gate electrode, the gate electrode formed on the substrate and comprising a first margin metal layer formed on the substrate and a second metal layer located on the first margin metal layer;a first electrode, the first electrode located on the substrate and surrounded by the gate electrode;a second electrode, the second electrode located on the first electrode and surrounded by the gate electrode; anda channel layer, the channel layer located between the first electrode and the second electrode and surrounded by the gate electrode.2. The thin film transistor of claim 1 , wherein the gate electrode is spaced apart from the first electrode claim 1 , the second electrode claim 1 , and the channel layer.3. The thin film transistor of further comprising an electrically insulating layer formed on the substrate and covering the gate electrode and the second electrode claim 2 , wherein the electrically insulating layer makes the gate electrode electrically insulated from the first electrode claim 2 , the second electrode and the channel layer.4. The thin film transistor of claim 3 , wherein the electrically insulating layer is filled in a gap between the gate electrode and a combination of the first electrode claim 3 , the second electrode claim 3 , and the channel layer.5. The thin film transistor of claim 1 , wherein the first electrode is a source electrode of the thin film transistor ...

Array substrate and display device and method for making the array substrate

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

TFT ARRAY SUBSTRATE, DISPLAY PANEL, AND TFT STRUCTURE

A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line. 1. A thin film transistor (TFT) array substrate comprising:a plurality of scan lines comprising a first scan line having a first side and a second side opposite the first side;a plurality of date lines insulated with the plurality of scan lines and comprising a first date line and a second date line, the first date line insulated with and at least partly covering the second date line;a plurality of pixels defined by two adjacent scan lines and two adjacent date lines;a first TFT configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line; anda second TFT configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.2. The TFT array substrate of claim 1 , wherein the first TFT covers the second TFT.3. The TFT array substrate of claim 2 , wherein the first TFT and the second TFT shares a same gate electrode.4. The TFT array substrate of claim 3 , wherein the first TFT further comprises a first channel layer claim 3 , a source electrode claim 3 , and a drain electrode; the second TFT further comprises a second channel layer claim 3 , a second ...

Method of manufacturing thin film transistor

A method of manufacturing a thin film transistor substrate is provided, including a first photoresist pattern covers a channel during a process of etching a second photoresist pattern and protects the channel. Thus, an etching stop layer is not required.

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL USING SAME

A thin film transistor (TFT) array substrate of a liquid crystal display (LCD) panel includes a first substrate, a gate located on the first substrate, a gate insulation layer located on the first substrate and covers the gate and the first substrate, a source layer located on the gate insulation layer to correspond to the gate, an etching stopping layer located on the source layer, and a source and a drain located on the etching stopping layer. The etching stopping layer is made of color photoresist. 1. A thin film transistor (TFT) array substrate comprising:a first substrate;a gate located on the first substrate;a gate insulation layer located on the first substrate and covering the gate and the first substrate;a source layer located on the gate insulation layer and corresponding with the gate;an etching stopping layer located on the source layer and composed, at least in part, of color-photo-resistive material;a source and a drain located on the etching stopping layer; anda passivation layer covering the source and the drain.2. The TFT array substrate according to claim 1 , further comprising a color photoresist layer claim 1 , the color photoresist layer and the etching stopping layer being located at a same structure layer.3. The TFT array substrate according to claim 2 , wherein the etching stopping layer is a portion of the color photoresist layer.4. The TFT array substrate according to claim 2 , wherein the color photoresist layer comprises a plurality of color photoresist units composed of at least one red photoresist unit claim 2 , at least one green photoresist unit claim 2 , and at least one blue photoresist unit.5. The TFT array substrate according to claim 4 , wherein the plurality of color photoresist units are arranged in a matrix having a plurality of rows and columns.6. The TFT array substrate according to claim 2 , wherein the color photoresist layer comprises a first through hole and a second through hole claim 2 , the source and the drain are ...

ARRAY SUBSTRATE AND METHOD FOR MAKING SAME

A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy. 1. A TFT substrate comprising:a substrate;a semiconductor layer formed on the substrate, the semiconductor layer having a top surface and a bottom surface opposite to and facing away from the top surface;a first conductive layer formed on the bottom surface of the semiconductor layer, the first conductive layer defining a gate electrode; anda second conductive layer formed on the top surface of the semiconductor layer opposite to the first conductive layer, the second conductive layer defining a source electrode and a drain electrode separated from the source electrode;wherein the second conductive layer comprises a first layer positioned on the semiconductor layer and a second layer positioned on the first layer; the first layer is made of metal oxide; and the second layer is made of aluminum or aluminum alloy.2. The TFT substrate of claim 1 , wherein a groove is defined between the source electrode and the drain electrode; the groove passes through the first layer and the second layer; and wherein the size of the groove gradually decreases along a direction from the second layer to the first layer.3. The TFT substrate of claim 1 , wherein the second conductive layer further comprises a third layer positioned on the second layer claim 1 , the third layer is made of metal oxide.4. The TFT substrate of claim 3 , wherein a ...

Thin film transistor and thin film transistor substrate

A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.

Display array substrate and manufacturing method thereof

A manufacturing method of display array substrate is provided. The method includes depositing a first metal layer on a substrate and defining a peripheral area and a display area, coating a photo-resist layer on the first metal layer located in the peripheral area, anodizing the first metal layer to a first metal oxide layer with the photo-resist layer as a mask, patterning the first metal oxide layer located in the display area to a gate insulator, removing the photo-resist layer to expose the first metal layer in the peripheral area, forming a channel layer on the gate insulator, and depositing a second metal layer and patterning the second metal layer located in the display area to form a source electrode and a drain electrode.

THIN FILM TRANSISTOR AND METHOD OF MAKING SAME

A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer. 1. A thin film transistor comprising:a substrate;a gate electrode formed on the substrate;an electrically insulating layer formed on the substrate and covering the gate electrode;a channel layer made of semiconductor material and formed on the electrically insulating layer;an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole;a source electrode formed on the etch stop pattern and extending into the first through hole to electrically couple to the channel layer; anda drain electrode formed on the etch stop pattern and extending into the second through hole to electrically couple to the channel layer;wherein both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.2. The thin film transistor of claim 1 , wherein both the first through hole and the second through hole gradually diminish along a direction from the etch stop pattern to the substrate.3. The thin film transistor of claim 1 , wherein the channel layer is symmetrical to a central line of the substrate of the thin film transistor.4. The thin film transistor of claim 1 , wherein the etch stop pattern is formed by forming an etch stop ...

Thin film transistor substrate, manufacturing method thereof, and liquid crystal display panel using same

A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.

Array substrate and method for making same

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

Manufacturing method of thin film transistor, and display array substrate using same

垂直型薄膜トランジスタ及びその製造方法

【課題】本発明は、プロセスが簡単であり、大量模生産に有利な垂直型薄膜トランジスタの製造方法及びその製造方法により製造された垂直型トランジスタを提供することを目的とする。【解決手段】本発明に係る垂直型薄膜トランジスタ２００は、基板２１０、該基板２１０上に形成されたエッジ第一金属層２６１１及びエッジ第一金属層２６１１上に形成されたエッジ第二金属層２６２１を含む２つのゲート電極２２０、２つのゲート電極の間に設置された第一電極２３０、第二電極２４０及び第一電極２３０及び第二電極２４０の間に設置されたチャンネル層２５０を備える。【選択図】図１

Array substrate and method for making same

A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.

Thin film transistor utilized in array substrate and manufacturing method thereof

A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

Thin film transistor and method of manufacturing same

A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

Method for fabricating conducting structure and thin film transistor array panel

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

TFT array substrate, display panel, and TFT structure

A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.

Thin film transistor array panel

A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.