Method for reducing chip set power consumption and apparatus thereof

It is a method to decrease chip set power consumption when storing or taking storage module and its relevant apparatus. The chip set has multiple driving units and each unit is connected with an address terminal of each storage module to send one-bit address data. The invention judges the storage module address terminals according to the real group of the each storage module and needn't driving address terminal to receive the power of the driving unit when searching for addresses.

Memory updating method and memory updating system

A method for updating storage includes timing idle time of idle storage column when storage column is on idle state, making idle storage enter into a self-updating mode when idle time is over a default value.

Reginal-block scanning display and relative devices

A zone block scanning display has a primary display region with X lines x Y columns display units. Each display unit can display a part of a picture. The primary display region is divided into display sub-regions used as display zone blocks. Each zone block has lines X columns display units. After a pixel data sequence is received, the adjacent pixel data can be displayed in a same zone block.

Method of proceeding error inspection and related device

Game execution system

The invention provides a game executing system, which includes a display unit, an image capturing unit, and a processing unit. At least one game component is placed on the display unit, and at least one picture of the corresponding picture game is displayed. The image capturing unit captures a corresponding game component and an image of the picture displayed by the display unit. The processing unit receives image, and executes a game decision of the corresponding picture game according to the image. The game executing system can implement picture game by combining the real component with the virtual picture and can keep the reality sense of the real game component in the prior picture game dispensing with memorizing the game rule.

Block contact plugs for mos devices

The invention discloses an integrated circuit structure, which comprises a semiconductor substrate, a gate stack overlying the semiconductor substrate, a gate spacer on a sidewall of the gate stack, a first contact plug equipped with an inner edge contacting a sidewall of the gate spacer and a top surface level with a top surface of the gate stack, and a second contact plug over the first contactplug and contacting the first contact plug. The cross-sectional area of the second contact plug is smaller than the cross-sectional area of the first contact plug.

Display device, display system and driving method thereof

The invention provides a display system and the driving method, the system includes a display panel, a memorizing device, a display memory, a display control circuit, a driving circuit, and a digital/analog transferring circuit. The memorizing device is used to memorize the display data of pulral pels on the display panel, the display control circuit generates display data and records it into thedisplay memory. When the data in the second unit of the display memory is not the same with the data in the first unit of the correspondent memorizing device, the control circuit transmits the data of the second memorizing unit to the driving circuit to update the data in the first unit. The digital/analog transferring circuit uses the data in the updated first unit to drive correspondent pel.

Method for forming oxide layer-nitride layer-oxide layer in single reactor

The present invention relates to process of forming oxide layer-nitride layer-oxide layer in one single reactor. The process includes providing one substrate, forming the first oxide layer on the substrate, forming the first buffering layer on the oxide layer, forming SiN layer on the first buffering layer, forming the second buffering layer on the SiN layer, and forming the second oxide layer onthe second buffering layer successively.

Method for decreasing granule amount of material layer with low dielectric constant

Method of proceeding error inspection and related device

The present invention relates to a method for checking error and its related device. Said invention can divide the storage space provided by an internal memory into an error-checking/correcting range and a non-error-checking/correcting range. When a data is fetched or written, it can judge that the address of said data is belonged to said error checking/correcting range or said non-error-checking/correcting range, and can define that said data execution error can be checked/corrected or not.

Method for forming superthin grid dielectric layer by using soft nitrogen-contained plasma

Data error check method and relative device

The invention discloses method and relevant device for carrying out checking and correcting data error in accessing memory. In the optimized instance, the invention can fetch multiple data and multiple checking codes. The multiple data can be regarded as an integrated data, and multiple checking codes can be regarded as an integrated checking data, which can be utilized to check and correct said integrated data, or that is equivalent to check and correct original multiple data. For example, in case of accessing memory in doubling data rate under 32 bits data architecture, the invention regards two pieces of 32 bits data fetched in same clock cycle as a piece of 64 bits data. Moreover, checking of data error under 32 bits architecture can be realized by using algorithm in use for 64 bits data/8 bits checking codes.

Method for increasing sticking property of dielectric material of semiconductor

First, barrier layer is formed on a substrate. Then the first intermediate layer is formed with adherence accelerant being deposited on the barrier layer by method of Chemical Vapor Deposition (CVD).The adherence accelerant is an organic material such as methyltriacetoxysilane. Next, the first dielectric layer covers the first intermediate layer. The second intermediate layer is formed with adherence accelerant being deposited on the first dielectric layer by method of CVD. Following the third intermediate layer is formed with adherence accelerant being deposited on etch ending layer by method of CVD. Last, the second dielectric layer covers the third intermediate layer.

Flash memory structure

Semiconductor component with dual whole metal silicide grids and manufacturing method thereof

The invention discloses a semiconductor element with full-metal-silicide dual-gate, which comprises a first transistor, a second transistor, a dielectric layer and an interlayer insulation layer. The first transistor is arranged on a substrate and includes a first metal silicide gate and a first source/drain. The second transistor is arranged on the substrate and includes a second metal silicide gate and a second source/drain. The material of the first metal silicide gate is different from that of the second metal silicide gate. The first metal silicide gate and the second metal silicide gate are produced in the same metal silicidation technology. The dielectric layer entirely covers the first and the second transistors, and the interlayer insulation layer is arranged on the dielectric layer.

Flash memory structure

The structure of the flash memory includes one electron-trapped layer, one grid electrode and one source/drain electrode area. The electron-trapped layer is a stack composed of one layer of the dielectric layer made from the material with high dielectric constant and one layer of the second oxide layer in sequence. The grid is positioned on the electron-trapped layer. The source/drain areas are located on the substrate at the two sides of the electron-trapped layer. The invention reduces the variance of the threshold voltage so as to enhance the performance of the flash memory to maintain thedata in it.

Flash memory structure

The structure of the flash memory includes one tunneling oxide layer, one floating grid, one dielectric lamination layer and one area of the control grid and the source/drain area. The dielectric lamination is a stack, positioned between the floating grid and the control grid, and composed of one first oxide layer, one layer of the dielectric layer amde from the material with high dielectric constant and one layer of the second oxide layer in sequence. The floating grid is positioned on the tunneling oxide layer. The control grid is positioned on the dielectric lamination. The source/drain areas are located on the substrate at the two sides of the floating grid. The invention can lower the magnitute of voltage needed to apply for operating the flash memory so as to reduce energy loss.

Stack structure for metal inlay, forming method and metal inlay method thereof

Game execution system

The invention provides a game executing system, which includes a display unit, an image capturing unit, and a processing unit. At least one game component is placed on the display unit, and at least one picture of the corresponding picture game is displayed. The image capturing unit captures a corresponding game component and an image of the picture displayed by the display unit. The processing unit receives image, and executes a game decision of the corresponding picture game according to the image. The game executing system can implement picture game by combining the real component with thevirtual picture and can keep the reality sense of the real game component in the prior picture game dispensing with memorizing the game rule.

Display device

Method for improving interface kink between pure silicate glass and phosphorosilicate glass and phosphor containing structure thereof

The invention discloses a method of improving the kinks of unmixed SiO2 glass (USG) and phosphosilicate glass (PSG), increasing the flow of hydrogen phosphide by stages from zero to a final set value to slowly carry away the residual hydrogen phosphide at the valve mouth of a flow controller but avoiding hydrogen phosphide overshooting, and further impoving USG and PSG interface kinks, where hydrogen phosphide (PH3) gas flow can be increased in a mode of arithmetical, geometric or irregular progression. An interface layer containing P situated between USG and PSG layers increases the P content from 0% to 100% by stages, and the total thickness of the interface layer is at least greater than 100 angstrom.

High-fidelity (Hi-Fi) audio system and driving method thereof

The invention relates to a high-fidelity (Hi-Fi) audio system and a driving method thereof. The Hi-Fi audio system is suitable for connecting with an Hi-Fi codec and comprises an Hi-Fi audio controller, a virtual Hi-Fi codec and a digital signal processor (DSP), wherein the virtual Hi-Fi codec is connected with the Hi-Fi audio controller for providing a simulated Hi-Fi codec architecture to an operating system and receiving and sending audio data; the DSP is connected with the virtual Hi-Fi codec for buffering or decoding the audio data; the virtual Hi-Fi codec composes a plurality of virtualtool sets according to the Hi-Fi codec architecture to form the simulated Hi-Fi codec architecture so that the operating system takes the virtual Hi-Fi codec as the Hi-Fi codec. The invention can process un-decoded audio data without configuring a higher-cost audio decoder or a Hi-Fi codec with the audio decoder, thereby decreasing the cost.

Method for mfg. semiconductor internal storage module with gate stacked dielectric layer

A method for making a semiconductor internal storage module with gate stack dielectric layers. The processes follow: the first dielectric layer is formed on the first conducting semiconductor substrate; the first conducting layer is formed on the first dielectric layer; the second dielectric layer is formed on the first conducting layer, wherein the 2nd dielectric layer is formed by stacking the 1st silica layer, a silicon nitride layer, a silicon oxide nitride layer, and the 2nd silica layer; the 2nd conducting layer of formed on the 2nd dielectric layer; the 1st dielectric layer, the 1st conducting layer, the 2nd dielectric layer, and the 2nd conducting layer are pattern etched, forming the 1st gate dielectric layer, a floating logic gate, the 2nd gate dielectric layer, and a control gate.

Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof

The invention discloses a method for manufacturing an MOS transistor with a metal grid, which comprises the following steps of: providing a floor; a grid sacrificial layer is arranged over the floor; a clearance wall circles the grid sacrificial layer; the floors in the two opposite sides of the grid sacrificial layer are respectively provided with a doping area; an incline edge is formed on the clearance wall and a groove is formed in the clearance wall; an obstructing layer and a metal grid are formed in the grove and the incline edge and the problem of bad step coverage of the obstructing layer can not happen. The invention also discloses an MOS transistor with a Y type metal grid.

Method for making a brake-pole dielectric layer by using single wafer process

A method of processing gate dielectric layer with a single wafer process contains two steps separately processed in a single wafer reaction chamber and a single wafer quick heating reaction chamber first, to put a single wafer in a single wafer reaction chamber to form a silicon oxynitvide layer on the surface of the silicon wafer by nitration then to put the silicon wafer in the single wafer quick ehating process reaction chamber performing oxidation process along with steam to turn the silicon oxynitvide contained laeyr to a silicon oxide with silicon oxynitvide base as a gate dielectric layer.

用于电脑系统的显示器

... 本发明提供一种显示器及相关装置。该显示器包含有一显示图形画面的主显示区，其具有多行及多列的显像单元，各显像单元用来依据一对应的像素数据来显示该图形画面的一部分。该显示器主显示区中又划分出多个较小的子显示区做为显示用区块(tile)，各区块亦具有多行及多列的显像单元；各区块显像单元的行数及列数分别小于该主显示区的行数及列数的显像单元；而该显示器接收序列传输的像素数据后，可以将相邻的像素数据显示于一相同的区块。 ...

Method for leveling semiconductor sedimentary deposit

The invention relates to a method of flattening semiconductor deposition, firstly providing a substrate; then using high-density plasma chemical gas phase deposition process to form a semiconductor deposition on the substrate; then using spattering etching process to process the deposition surface; successively, using chemomechanical grinding process to flatten the deposition surface. It can improve the grinding efficiency of a chemomechanical grinder by using the spattering etching process.

制作栅极介电层的方法

... 一种以单一晶片工序制作栅极介电层的方法，所述方法包括分别在一单晶片反应室及一单晶片快速加热反应室进行的两步骤：首先，置放一单一硅晶片于单晶片反应室中，并进行氮化步骤以形成含氮氧化硅层于硅晶片的表面上。然后，置放硅晶片于单晶片快速加热工序反应室中，并进行随同蒸气产生氧化的工序，将此含氮氧化硅层氧化成具氮氧化硅底层的氧化硅层，以供做栅极介电层。 ...

Method for forming superthin grid dielectric layer by using soft nitrogen-contained plasma

A method for forming a ultra-thin grafting dielectric layer with soft plastma with nitrogen is to carry out the preazotization step of azotizing the base surface with soft plasma containing nitrogen with the density of 10 to the power 9 -10 to the power 13 cm -3, then to carry out the step of heat oxidation step to the base to formultra-thin grating dielectric layer on the base. This invention utilizes the soft plasma with nitrogen to azotize the base surface first to control thickness of the successive oxidation layer to avoid harm to the base surface structure in the existing ionic insertion method when nitrogen ions are divectly inserted into the base.

Method for arbitrating bus control right and its arbitrator

The invention relates to the method for arbitrating the right of controlling the bus and the arbitrator used in the bus where there are multiple master control sets connected. The arbitrator includesmultiple time counter, which are connected to the said multiple master control sets respectively. The invented method includes following steps. Based on the data transfer signal sent by one master control set, the time counting value is generated, and based on the occurrence of the signal for transferring data successfully, the time counting value is reset. When the time counting value is larger than the preset threshold, the priority grade of the master control set for using the bus is changed.

Integrated image chip architecture with multiple display function

An integrated image chip architecture with multiple display function, is composed of an integrated image chip for outputting the first image signal to the first display, an accelerating image processing interface connected with said image chip and the second display, and an accelerating image processing controller connected to said accelerating image processing interface for outputting the secondimage signal to the second display. Its advantages are low cost and easy implementation.

Heteropolyacid material constructed by Dawson type polyacid and six-core copper complex, and preparation method and application thereof

The invention discloses a heteropolyacid material constructed by a Dawson type polyacid and a six-core copper complex, and a preparation method and application thereof. The hybrid material is prepared from Na2WO4.2H2O, CuCl2.2H2O, H3PO4, 1,10-phenanthroline (or 2,2'-biyridine) and H2O by a hydrothermal method. The material is used for degrading methyl orange, methyl blue, rose color, Congo red or an organic dye which has the same chromophore as the organic dye. The hybrid material has the advantages of maintaining the photo-catalytic activity of the heteropolyacid for degrading the organic dye, overcoming the defects of easy dissolution of the polyacid in a polar solvent, difficult treatment of organic dye-containing wastewater and difficult recovery, also overcoming the defect that the heteropolyacid can only generally show photo-catalysis in ultraviolet light and having extremely high photo-catalytic activity even at a visible region, along with obvious absorption effect at the visible ...

Method for reducing chip set power consumption and apparatus thereof

Semiconductor component with dual whole metal silicide grids and manufacturing method thereof

The invention discloses a semiconductor element with full-metal-silicide dual-gate, which comprises a first transistor, a second transistor, a dielectric layer and an interlayer insulation layer. The first transistor is arranged on a substrate and includes a first metal silicide gate and a first source/drain. The second transistor is arranged on the substrate and includes a second metal silicide gate and a second source/drain. The material of the first metal silicide gate is different from that of the second metal silicide gate. The first metal silicide gate and the second metal silicide gateare produced in the same metal silicidation technology. The dielectric layer entirely covers the first and the second transistors, and the interlayer insulation layer is arranged on the dielectric layer.

浅沟渠隔离区的制造方法

The method includes step: partial filling the formed trench with first insulation layer; carrying out a surface processing procedure on surface and sidewall of the first insulation layer to form a process layer; then, removing process layer; forming second insulation layer on the first insulation layer to fill in the trench so as to form a shallow trench isolation zone. In the above said procedure, second insulation layer is filled in trench after ratio between depth and width of trench has been lowered and controlled. Thus, the invention avoids pore spaces formed on the shallow trench isolation zone caused by ratio between depth and width of trench.

存储器的制造方法

The present invention is a memory manufacturing method. The method comprises the following steps: providing a substrate, forming the gate oxide layer and the character lines on the substrate, next depositing the lining oxide layer on the substrate using CVD without plasma source to cover the substrate and the character lines, and then forming the dielectric layer on the lining oxide layer, wherein the lining oxide layer and the dielectric layer are formed continuously in the same reacting chamber.

Method for arbitrating bus control right and its arbitrator

Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof

The invention discloses a method for manufacturing an MOS transistor with a metal grid, which comprises the following steps of: providing a floor; a grid sacrificial layer is arranged over the floor; a clearance wall circles the grid sacrificial layer; the floors in the two opposite sides of the grid sacrificial layer are respectively provided with a doping area; an incline edge is formed on the clearance wall and a groove is formed in the clearance wall; an obstructing layer and a metal grid are formed in the grove and the incline edge and the problem of bad step coverage of the obstructing layer can not happen. The invention also discloses an MOS transistor with a Y type metal grid.

在半导体制作过程中通过氘以形成多晶硅层的方法

... 本发明揭露一种在半导体制作过程中通过氘以形成多晶硅层的方法。首先，提供半导体衬底，其中半导体衬底上具有介电层。然后，分解包含氯与氘的硅烷以形成多晶硅层在介电层上。 ...

Atomic layer precipitation method for forming silicon nitride gap wall

The atomic layer precipitation process of forming silicon nitride gap wall includes the steps of: creating one first solid product layer on element with one eccessive first gas as reactant gas beforepumping out the first gas; and creating one second solid product layer on the first solid product layer through chemical reaction with the released seocnd gas. In the new generation of element of 0.13 micron or 0.18 micron, the element size is reduced and the deposited thickness is relatively thinner. The atom layer precipitation process is su8itable for the said requirement in precipitating silicon nitride gap wall.

Process for preparing small doped polysilicon

The invented method for producing the N type adulterated polysilicon is as follows. The reacting gas source, the N type adulterated gas source and the gas source of the catalyzer are passed into the reaction chamber of the chemical vapor deposition. The processing step of the chemical vapor deposition is carried out so as to form the thin film of the N type adulterated polysilicon.

Polysilicon layer forming process with deuterium during semiconductor production

The present invention reveals one kind of polysilicon layer forming process with deuterium during semiconductor production. One semiconductor substrate with dielectric layer is first provided. Silanecontaining chlorine and deuterium is then decomposed to form polysilicon layer on the substrate.

具有高高宽比的浅沟渠隔离结构的填充方法

The method is suitable to forming an isolated groove in an IC on semiconductor substrate. First, a semiconductor substrate possessing a pad oxide layer, a nitrided layer and a patternized photoresistive layer. Next, part of nitrided layer, pad oxide layer and semiconductor substrate are removed so as to form a groove. Then, after groove is formed, the photoresistive layer is removed, and first filling layer is formed in the groove. Finally, etching back first filling layer by using wet spin etching so as to form second filling layer on the first filling layer.

Atomic layer precipitation method for forming silicon nitride gas wall