Radiation-hardened package for an electronic device

The package comprises a carrier, an electronic device arranged on the carrier, a shield arranged on the electronic device on a side facing away from the carrier, and an absorber film comprising nanomaterial applied on or above the shield.

Pixel structure with multiple transfer gates

A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element ...

Pixel array

A pixel array for imaging comprises an array of pixels of a first pixel type and a second pixel type. Each pixel of the first pixel type comprises a first photo-sensitive element having a first area. Each pixel of the second pixel type comprises a second photo-sensitive element and a third photo-sensitive element. The second photo-sensitive element has a second area, which is smaller than the first area. Only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit. The third photo-sensitive element is connected to a charge drain via a permanent connection or a switchable connection. Outputs of the second photo-sensitive elements can be used to perform phase detect autofocussing.

Pixel cell and method for operating a pixel cell

A pixel cell includes a pixel set with a plurality of pixels, with each pixel of the pixel set being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell further includes a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set and to operate the pixel set in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel is used to generate individual rolling shutter output signals.

Pixel array with individual exposure control for a pixel or pixel region

Method and device for determining corrected color aspects of a pixel in an imaging device

The invention is a method for determining at least two corrected color values for a pixel, said pixel being embedded in a configuration of pixels and having a color filter for filtering substantially one color type while obtaining a measurement on the pixel. The method comprises the steps of measuring at least one signal on said pixel; transforming the measured signal into a representation having at least a luminance and a chrominance part; and transforming said representation into a color space representation of said pixel, said pixel having at least two color values in said color space representation.

Analog-to-digital conversion in pixel arrays

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Image sensor system, electronic device and method for operating an image sensor

An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.

Pixel drive voltage generation using a charge pump

An image sensor comprises an array comprising rows and columns of pixels, a first number N of connection lines connected to a first number N of pixels of the array, a voltage regulating circuit having an output, a first terminal, and a driver circuit. The driver circuit has a first number N of switches coupled to the first number N of connection lines and to the output of the voltage regulating circuit, and a first number N of further switches coupled to the first number N of connection lines and to the first terminal. The first number N is at least two.

PIXEL ARRAY

A pixel array for imaging comprises an array of pixels of a first pixel type and a second pixel type. Each pixel of the first pixel type comprises a first photo-sensitive element having a first area. Each pixel of the second pixel type comprises a second photo-sensitive element and a third photo-sensitive element. The second photo-sensitive element has a second area, which is smaller than the first area. Only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit. The third photo-sensitive element is connected to a charge drain via a permanent connection or a switchable connection. Outputs of the second photo-sensitive elements can be used to perform phase detect autofocussing. 1. A pixel array for imaging comprising an array of pixels of a first pixel type and a second pixel type , wherein:each pixel of the first pixel type comprises a first photo-sensitive element having a first area;each pixel of the second pixel type comprises a second photo-sensitive element having a second area, which is smaller than the first area, and a third photo-sensitive element, wherein only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit, and wherein the third photo-sensitive element is connected to a charge drain via one of a permanent connection and a switchable connection.2. A pixel array according to wherein the switchable connection comprises a transfer gate.3. A pixel array according to wherein the switchable connection comprises a transfer gate claim 1 , a reset switch and a floating diffusion between the transfer gate and the reset switch.4. A pixel array according to comprising isolation between the second photo-sensitive element and the third photo-sensitive element.5. A pixel array according to wherein the isolation between the second photo-sensitive element and the third photo-sensitive element comprises one of:shallow trench isolation between the second photo- ...

Backside illuminated image sensor

The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit.

Pixel having two cascade-connected sample stages, pixel array, and method of operating same

A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Semiconductor device for indirect detection of electromagnetic radiation and method of production

The semiconductor device comprises a substrate of semiconductor material having a main surface, an integrated circuit in the substrate, a photodetector element or array of photodetector elements arranged at or above the main surface, and at least one nanomaterial film arranged above the main surface. At least part of the nanomaterial film has a scintillating property. The method of production includes the use of a solvent to apply the nanomaterial film, in particular by inject printing, by silk-screen printing, by spin coating or by spray coating.

Analogue-to-digital converter and method for using the same

An analogue-to-digital (A/D) converter converts an analogue input signal to a digital code representing the analogue input signal. The A/D converter includes a comparator for comparing the input signal with a reference signal, a search logic block for determining the digital code, and an A/D converter arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. At least a first portion of the A/D converter is implemented with equal capacitors and may be controlled by a thermometer coded signal. Additionally, the A/D converter may include a second portion implemented using binary weighted capacitors controlled by a thermometer coded or binary coded signal. The A/D converter may also include a plurality of A/D converters coupled by an analogue addition circuit or a weighted summing amplifier.

IMAGE SENSOR

An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M connected between the first sense node A and the second sense node B; and a buffer amplifier M having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS and a second reset control line RS to continuously switch on one of the first reset transistor M and the second reset transistor M during a readout period of an operational cycle of the pixels. 1. An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels , each of the pixels comprising:a pinned photodiode;a first sense node;a second sense node;a transfer gate connected between the pinned photodiode and the first sense node;a first reset transistor connected between a voltage reference line and the second sense node;a second reset transistor connected between the first sense node and the second sense node; anda buffer amplifier having an input connected to the first sense node;the image sensor further comprising:a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array;a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array;and wherein the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in each of the conversion gain modes the control logic is arranged ...

PIXEL DRIVE VOLTAGE GENERATION USING A CHARGE PUMP

An image sensor comprises an array comprising rows and columns of pixels, a first number N of connection lines connected to a first number N of pixels of the array, a voltage regulating circuit having an output, a first terminal, and a driver circuit. The driver circuit has a first number N of switches coupled to the first number N of connection lines and to the output of the voltage regulating circuit, and a first number N of further switches coupled to the first number N of connection lines and to the first terminal. The first number N is at least two.

Pixel structure, image sensor device and system with pixel structure, and method of operating the pixel structure

A photodetector in semiconductor material is provided with a first transfer gate between the photodetector and a first diffusion region in the semiconductor material, a second transfer gate between the photodetector and a second diffusion region in the semiconductor material, a capacitor connected between the first diffusion region and the second diffusion region, a first switch connected between the first diffusion region and a first reference voltage, and a second switch connected between the second diffusion region and a second reference voltage.

Image sensor

An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor M3 connected between a voltage reference line Vrst and the second sense node B; a second reset transistor M4 connected between the first sense node A and the second sense node B; and a buffer amplifier M1 having an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RS1 and a second reset control line RS2 to continuously switch on one of the first reset transistor M3 and the second reset transistor M4 during a readout period of an operational cycle of the pixels.

Pixel array with shared readout circuitry

A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

Pixel array with reduced sensitivity to defects

An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element. The array is configured such that, in the event of a defect in a row select line, the first supply line is set to ground, or a low voltage, and the reset switch is turned on to put the buffer amplifier into the high impedance state.

Method of manufacture of a backside illuminated image sensor

A method of manufacturing a backside illuminated image sensor includes providing a start material that has a layer of semiconductor material on a substrate. The layer of semiconductor material has a first face and a second, backside, face. The layer of semiconductor material is processed to form semiconductor devices in the layer adjacent the first face. At least a part of the substrate is removed to leave an exposed face. A passivation layer is formed on the exposed face, the passivation layer having negative fixed charges. The passivation layer can be Al2O3 (Sapphire). The passivation layer can have a thickness less than 5 m, advantageously less than 1 m, and more advantageously in the range 1 nm-150 nm. Another layer, or layers, can be provided on the passivation layer, including: an anti-reflective layer, a layer to improve passivation, a layer including a color filter pattern, a layer comprising a microlens.

Analog-to-digital conversion and method of analog-to-digital conversion

An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Electronic Power Conversion Circuit

An electronic power conversion circuit is presented for converting an input power to an output power. The circuit comprises at least one conversion block and a clock generator. Each conversion block comprises an input, an output and a plurality of charge storage elements and switches between the input and output. Each block is alternately switchable between a first state in which electric charge is loaded from the input and a second state in which electric charge is supplied as converted power to the output. The clock generator generates clock signals for controlling the switches and thereby switches between the first and second states. The circuit is characterized in that the clock generator comprises at least one input node for receiving at least one input parameter and in that the clock generator is provided for varying the frequency of the clock signals in relation to the at least one input parameter.

Pixel structure

A pixel structure comprises an epitaxial layer ( 1 ) of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer ( 1 ) and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element ( 13 ) for converting charges from the charge storage node to a voltage signal and an output circuit ( 21, 22 ) for selectively outputting the voltage signal from the pixel structure.

Pixel Structure

A pixel structure comprises an epitaxial layer () of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer () and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element () for converting charges from the charge storage node to a voltage signal and an output circuit () for selectively outputting the voltage signal from the pixel structure. 1. A pixel structure comprising:an epitaxial layer of a first conductivity type;a photo-sensitive element comprising a first region of a second conductivity type and a second region of the first conductivity type positioned between the epitaxial layer and the first region;a charge storage node which is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element;a third region of the second conductivity type positioned between the charge storage node and the epitaxial layer;a charge-to-voltage conversion element for converting charges from the charge storage node to a voltage signal; and,an output circuit for selectively outputting the voltage signal from the pixel structure.2. A pixel structure according to wherein the first conductivity type is n-type and the second conductivity type is p-type.3. A pixel structure according to wherein a dopant level of the third region is higher than a dopant level of the epitaxial layer.4. A pixel structure according to wherein a dopant level of the third region is higher than a dopant level of the epitaxial layer by a factor of at least 100.5. A pixel structure according to wherein a dopant ...

Semiconductor pixel arrays with reduced sensitivity to defects

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

In-pixel differential transconductance amplifier for ADC and image sensor architecture

An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal.

Pixel array with reduced sensitivity to defects

An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element. The array is configured such that, in the event of a defect in a row select line, the first supply line is set to ground, or a low voltage, and the reset switch is turned on to put the buffer amplifier ...

Pixel array capable of performing pipelined global shutter operation including a first and second buffer amplifier

A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

PIXEL STRUCTURE WITH MULTIPLE TRANSFER GATES

A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element to the second charge conversion element via the second transfer gate.

Pixel Array With Global Shutter

A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. 1. A pixel comprising:a pinned photodiode for generating charges in response to incident radiation;a sense node;a transfer gate, connected between the pinned photodiode and the sense node, for controlling transfer of charges to the sense node;a reset switch connected to the sense node for resetting the sense node to a predetermined voltage;a first buffer amplifier having an input connected to the sense node;a sample stage, connected to an output of the first buffer amplifier, which is operable to sample a value of the sense node; and,a second buffer amplifier having an input connected to the sample stage.2. A pixel according to wherein the sample stage comprises:a sample switch connected to an output of the first buffer amplifier; and,a storage element for storing a signal level sampled by the sample switch.3. A pixel according to further comprising a discharge switch for resetting the sample stage.4. A pixel according to wherein the first buffer amplifier is connected to a first control line which is operable to discharge the sample stage.5. A pixel according to wherein the reset switch is also connected to the first control line.6. A pixel according to further comprising a read switch connected to the output of the second buffer amplifier for reading a signal from the pixel.7. A pixel according to wherein the sample stage comprises a sample switch connected to a ...

ANALOGUE-TO-DIGITAL CONVERTER AND METHOD FOR USING THE SAME

The present disclosure is related to an analogue-to-digital (A/D) converter (1) for converting an input signal (Vin) to a digital code representing said input signal. The A/D converter comprises a comparator (3) for comparing the input signal with a reference signal (VA), a search logic block (4) for determining the digital code and a digital-to-analogue converter (5) arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. The digital-to-analogue converter comprises at least a first portion implemented with equal capacitors (20). The ADC optionally further comprises a second portion implemented with binary weighted capacitors. The first portion is arranged for being controlled by a thermometer coded signal. The converter avoids charging-discharging of large capacitors during the search and therefore reduces the lost energy.

Semiconductor pixel arrays with reduced sensitivity to defects

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Pixel array with individual exposure control using at least two transfer gates for a pixel or pixel region

A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.

Differential readout of a pixel array with elimination of pixel- and column-wise fixed pattern noise

The present invention discloses an amplifying circuit, comprising an amplifying element with at least an input terminal and an output terminal. A signal input node is provided, the signal levels of which at least two moments in time are to be amplified by the amplifying element. At least two connecting lines are provided between the signal input node and the amplifying element, for transferring a signal from the signal input node to the input terminal of the amplifying element. A memory element is located on at least one of the connecting lines, for storing a signal level of the signal input node at a moment in time, and a switching element is disposed on each connecting line, between the memory element and the input terminal of the amplifying element if a memory element is provided on the connecting line, for consecutively connecting signal levels of the signal input node at different moments in time to the same amplifying element. The amplifying circuit has at least one output node, each ...

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

An image sensor arrangement for determining a three-dimensional image comprises an image sensor comprising an array of global shutter pixels and a control unit which is configured to drive the image sensor in an imaging mode and in a time-of-flight mode. In the imaging mode, the control unit drives the pixels according to an imaging timing sequence. In the time-of-flight mode, the control unit drives the pixels according to a time-of-flight, TOF, timing sequence. At least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase, respectively.

SYSTEM AND METHOD FOR ESTIMATING REMAINING RUN-TIME OF AUTONOMOUS SYSTEMS BY INDIRECT MEASUREMENT

A system and method for estimating remaining run-time of an autonomous system by indirect measure is disclosed. In one aspect, the system includes a load circuit, an energy storage system (ESS) and an energy storage management system (ESM). The load circuit includes functional blocks. The ESS stores electric energy and is connected to the load circuit and configured to supply the varying electric current to the load circuit. The ESM is configured to estimate a remaining run-time of the autonomous system. The ESM includes an input connected to one of the functional blocks of the load circuit from which a first parameter being an indirect measure for the varying electric current supplied from the energy storage system to the load circuit is received. The ESM determines the remaining run-time from this first parameter.

Resonant cavity enhanced image sensor

The semiconductor image sensor device comprises a semiconductor layer having a main surface and an opposite rear surface, and a charge carrier generating component at the main surface. The charge carrier generating component is arranged between a top reflecting layer and a bottom reflecting layer, which are arranged outside the semiconductor layer.

SEMICONDUCTOR PIXEL ARRAYS WITH REDUCED SENSITIVITY TO DEFECTS

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Fast and low-power multiplexing circuit and use thereof in imaging devices

A multiplexing circuit for use in imaging devices is described comprising a series of signal input nodes, a series of first memory elements for storing a signal level on the corresponding signal input nodes and at least a first output node comprising a second memory element. A series of first switching elements is provided, each first switching element being connected to a first memory element on one side and a first output node on the other side, and a second switching element is provided to bring the first output node in a known state. The readout requires less energy consumption than known methods using amplifiers. The signal levels stored on the first memory elements may be outputs from pixels which may be formed in an array of columns and rows. The signal levels from different pixels may be combined together to improve signal to noise ratios.

PIXEL ARRAY WITH GLOBAL SHUTTER

A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled. 1. An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level and a secondanalog signal level comprising: an input for receiving a ramp signal;', 'an input for receiving at least one clock signal;', 'a set of N counters, where N≧2, wherein the N counters are arranged to use N clock signals which are offset in phase from one another;, 'at least one input for receiving the first analog signal level and the second analog signal level;'}a control stage which is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level and the second analog signal level; andan output stage for outputting the digital value which is a function of values accumulated by the N counters during a period when they are enabled.2. An analog-to-digital converter according to wherein the set of N counters is divided into a first sub-set of counters and a second sub-set of counters claim 1 , and wherein the control stage is arranged to enable the first sub-set of counters or the second sub-set of counters.3. An analog-to-digital converter according to wherein the ...

Pixel of a semiconductor image sensor and method of manufacturing a pixel

A pixel with enhanced quantum efficiency comprises a semiconductor body that has a first surface configured as an entrance surface and a light capturing region configured for capturing light that is incident on the first surface. The pixel further comprises a structured interface, isolation layers on at least two surfaces of the semiconductor body that are perpendicular to the first surface, and a filter element that is arranged at a distance from the first surface such that light that is incident on the first surface at an angle of incidence smaller than a critical angle impinges on the filter element.

Semiconductor pixel arrays with reduced sensitivity to defects

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organised in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

PIXEL ARRAY WITH INDIVIDUAL EXPOSURE CONTROL FOR A PIXEL OR PIXEL REGION

A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them. 1. A pixel array comprising: a photo-sensitive element that generates charge in response to incident light;', 'a charge conversion element;', 'a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line;', 'an output stage;, 'a plurality of pixel structures, each pixel structure comprisinga first transfer gate control line connected to the first transfer gates of a first sub-set of the pixel structures in the array;a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array,wherein the first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.2. The pixel array according to claim 1 , wherein the first sub-set of pixel structures and the second sub-set of pixel structures have only one pixel structure in common between them.3. The pixel array according to claim 1 , wherein the first sub-set of pixel structures and the second sub-set of pixel ...

PIXEL OF A SEMICONDUCTOR IMAGE SENSOR AND METHOD OF MANUFACTURING A PIXEL

A pixel with enhanced quantum efficiency comprises a semiconductor body that has a first surface configured as an entrance surface and a light capturing region configured for capturing light that is incident on the first surface. The pixel further comprises a structured interface, isolation layers on at least two surfaces of the semiconductor body that are perpendicular to the first surface, and a filter element that is arranged at a distance from the first surface such that light that is incident on the first surface at an angle of incidence smaller than a critical angle impinges on the filter element. 1. A pixel comprising:a semiconductor body having a first surface configured as an entrance surface and a light-capturing region configured for capturing light incident on the first surface;a structured interface;isolation layers on at least two surfaces of the semiconductor body that are perpendicular to the first surface; anda filter element arranged at a distance from the first surface such that light incident on the first surface at an angle of incidence smaller than a critical angle impinges on the filter element.2. The pixel according to claim 1 , wherein the filter element is arranged such that the light incident at the angle of incidence smaller than the critical angle has to traverse the filter element before entering the semiconductor body.3. The pixel according to claim 1 , wherein a transmission value of the filter element depends on the angle of incidence and/or on a wavelength of the light.4. The pixel according to claim 3 , wherein the filter element is configuredto reflect light if the angle of incidence is larger than the critical angle; andto transmit light if the angle of incidence is less than or equal to the critical angle.5. The pixel according to claim 1 , wherein the filter element comprises a dichroic filter.6. The pixel according to claim 5 , further comprising a waveguide structure arranged between the filter element and the first surface.7 ...

SEMICONDUCTOR DEVICE FOR INDIRECT DETECTION OF ELECTROMAGNETIC RADIATION AND METHOD OF PRODUCTION

The semiconductor device comprises a substrate of semiconductor material having a main surface, an integrated circuit in the substrate, a photodetector element or array of photodetector elements arranged at or above the main surface, and at least one nanomaterial film arranged above the main surface. At least part of the nanomaterial film has a scintillating property. The method of production includes the use of a solvent to apply the nanomaterial film, in particular by inject printing, by silk-screen printing, by spin coating or by spray coating. 1. A semiconductor device for detection of electromagnetic radiation , comprising:a substrate of semiconductor material having a main surface,an integrated circuit in the substrate,a nanomaterial film arranged above the main surface, at least part of the nanomaterial film having a scintillating property, anda photodetector element or array of photodetector elements arranged in the substrate at the main surface or arranged in a semiconductor layer between the main surface and the nanomaterial film, the photodetector element or array of photodetector elements being configured to detect electromagnetic radiation transformed by the nanomaterial film.2. The semiconductor device according to claim 1 , further comprising:a dielectric layer arranged between the nanomaterial film and the photodetector element or array of photodetector elements.3. The semiconductor device according to claim 1 , wherein the nanomaterial film comprises nanodots claim 1 , nanorods or nanowires or any combination thereof.4. The semiconductor device according to claim 1 , further comprising:a further nanomaterial film, at least part of the further nanomaterial film having an absorbing property and covering an area of the main surface outside the photodetector element or array of photodetector elements.5. The semiconductor device according to claim 4 , wherein the further nanomaterial film comprises nanodots claim 4 , nanorods or nanowires or any ...

Backside illuminated image sensor

The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit.

RADIATION-HARDENED PACKAGE FOR AN ELECTRONIC DEVICE

The package comprises a carrier, an electronic device arranged on the carrier, a shield arranged on the electronic device on a side facing away from the carrier, and an absorber film comprising nanomaterial applied on or above the shield. 1. A package for an electronic device , comprising:a carrier,an electronic device arranged on the carrier,a shield arranged on the electronic device on a side facing away from the carrier, andan absorber film comprising nanomaterial applied on or above the shield.2. The package of claim 1 , wherein the shield and the absorber film are only arranged on a partial area of an upper surface of the electronic device facing away from the carrier.3. The package of claim 2 , further comprising:an integrated circuit of the electronic device, the shield and the absorber film being only arranged above the integrated circuit.4. The package of claim 3 , further comprising:a transistor forming a component of the integrated circuit, the shield and the absorber film being only arranged above the transistor.5. The package of claim 1 , wherein the shield is formed from aluminum claim 1 , copper claim 1 , tungsten or a combination thereof.6. A package for an electronic device claim 1 , comprising:a carrier, andan electronic device arranged on the carrier, the electronic device being provided with a cover comprising nanomaterial, with an absorber film comprising nanomaterial, or with an adhesive layer comprising nanomaterial, anda further electronic device arranged on the carrier on a side opposite the electronic device, the further electronic device being provided with a cover comprising nanomaterial, with an absorber film comprising nanomaterial, or with an adhesive layer comprising nanomaterial.7. The package of claim 6 , whereinat least one of the electronic device and the further electronic device is provided with a cover, andthe cover comprises nanomaterial or is provided with an absorber film comprising nanomaterial.8. The package of claim 7 , ...

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

An image sensor arrangement for determining a three-dimensional image comprises an image sensor comprising an array of global shutter pixels and a control unit which is configured to drive the image sensor in an imaging mode and in a time-of-flight mode. In the imaging mode, the control unit drives the pixels according to an imaging timing sequence. In the time-of-flight mode, the control unit drives the pixels according to a time-of-flight, TOF, timing sequence. At least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase, respectively.

RESONANT CAVITY ENHANCED IMAGE SENSOR

The semiconductor image sensor device comprises a semiconductor layer having a main surface and an opposite rear surface, and a charge carrier generating component at the main surface. The charge carrier generating component is arranged between a top reflecting layer and a bottom reflecting layer, which are arranged outside the semiconductor layer. 2. The semiconductor image sensor device according to claim 1 , whereinthe top reflecting layer is provided for incidence of radiation and is arranged above the main surface, andthe bottom reflecting layer is arranged above the rear surface.3. The semiconductor image sensor device according to claim 1 , whereinthe top reflecting layer is provided for incidence of radiation and is arranged above the rear surface, andthe bottom reflecting layer is arranged above the main surface.4. The semiconductor image sensor device according to claim 1 , further comprising:a photodiode forming the charge carrier generating component,a region of a first conductivity type in the semiconductor layer at the main surface,a region of a second conductivity type, which is opposite to the first conductivity type, the region of the second conductivity type being contiguous with the region of the first conductivity type, thus forming the photodiode,a sense node at or near the main surface, anda transfer gate at the main surface between the photodiode and the sense node.5. The semiconductor image sensor device according to claim 1 , further comprising:a dielectric layer on or above the main surface, the dielectric layer being arranged between the semiconductor layer and the top reflecting layer, and the top reflecting layer being provided for incidence of radiation.6. The semiconductor image sensor device according to claim 1 , further comprising:a dielectric layer on or above the main surface, the dielectric layer being arranged between the semiconductor layer and the bottom reflecting layer, and the top reflecting layer being provided for ...

PIXEL CELL AND METHOD FOR OPERATING A PIXEL CELL

A pixel cell includes a pixel set with a plurality of pixels, with each pixel of the pixel set being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell further includes a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set and to operate the pixel set in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel is used to generate individual rolling shutter output signals. 1. A pixel cell comprising:a pixel set with a plurality of pixels, with each pixel comprising a photodiode and a transfer gate coupled to the photodiode; and a floating diffusion coupled to all of the transfer gates;', 'a column output line;', 'a sample-and-hold stage coupled to the floating diffusion;', 'a first switch coupling the sample-and-hold-stage to the column output line; and', 'a second switch coupling the floating diffusion to the column output line or to a further column output line., 'a readout circuit comprising'}2. The pixel cell according to claim 1 , wherein the readout circuit is configured claim 1 , in a global shutter mode of operation claim 1 , tocontrol the plurality of pixels such that corresponding charges generated by the photodiode of each of the plurality of pixels in response to incident radiation are simultaneously transferred to the floating diffusion in accordance with transfer control signals simultaneously transmitted to the transfer gates;generate a global shutter output signal depending on the corresponding charges from the photodiode of each of the plurality of pixels, in particular depending on a sum or an average of said corresponding charges from the ...

3D CAMERA SYSTEM WITH ROLLING-SHUTTER IMAGE SENSOR

The system comprises an array of addressable light sources, which is configured for an activation of the light sources individually or in groups, an image sensor comprising pixels, which are configured for the detection of a predefined light pattern, and a rolling shutter of the image sensor. The array of addressable light sources is configured for a consecutive activation of the light sources according to the predefined light pattern or part of the predefined light pattern, and the rolling shutter is configured to expose areas of the image sensor in accordance with the activation of the light sources, so that the pixels in an exposed area are illuminated and the pixels that are outside the exposed area are shielded from illumination.

IN-PIXEL DIFFERENTIAL TRANSCONDUCTANCE AMPLIFIER FOR ADC AND IMAGE SENSOR ARCHITECTURE

An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal. 1. An image sensor comprising: a photosensitive device for sensing incident light and for outputting an analog signal,', 'a first node for receiving the analog signal, and', 'a first in-pixel part of an analog-to-digital converter (ADC) for outputting at least one current signal, the first in-pixel part of the ADC being a Differential Transconductance Amplifier with a first differential input connected to the first node for receiving the analog signal present on the first node, and a second differential input for receiving a reference signal;, 'a first die with a pixel array comprising a plurality of pixels, each pixel of the pixel array having a pixel structure comprisinga second die with a second part of the ADC, wherein the first die and the second die are stacked together; andat least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die,wherein:the first in-pixel part of the ADC is adapted to output the at least one current signal to the at least one output bus, andthe second part of the ADC is adapted to receive the at least one current signal and to generate a digital ...

ANALOG-TO-DIGITAL CONVERSION AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

An analog-to-digital converter () comprises an analog signal input () for receiving an analog signal and an amplifying stage () configured to generate a set of N amplified analog signals, where N is an integer≥2. The set of N signals have different gains. The ADC has a ramp signal input () for receiving a ramp signal and a clock input () for receiving at least one clock signal. A comparison stage () is connected to the set of amplified analog signals (SigG, SigG) and to the ramp signal input (). The comparison stage () is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage () based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period. 1. An analog-to-digital converter for an imaging device comprising:an analog signal input for receiving an analog signal from a pixel array of the imaging device;an amplifying stage configured to generate a set of N amplified analog signals, where N is an integer≥2, the set of N signals having different gains;a ramp signal input for receiving a ramp signal;a clock input for receiving at least one clock signal;a comparison stage connected to the amplified analog signals and to the ramp signal input, the comparison stage comprising a minimum of two comparators and being configured to compare the amplified analog signals with the ramp signal during a conversion period to provide comparison outputs;a counter stage; anda control stage which is configured to control the counter stage based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period, wherein the handover point is indicative of a point at which a comparison of a different one of the amplified analog signals with the ramp signal can be used to control the counter stage.2. The ...

PIXEL STRUCTURE, IMAGE SENSOR DEVICE AND SYSTEM WITH PIXEL STRUCTURE, AND METHOD OF OPERATING THE PIXEL STRUCTURE

A photodetector in semiconductor material is provided with a first transfer gate between the photodetector and a first diffusion region in the semiconductor material, a second transfer gate between the photodetector and a second diffusion region in the semiconductor material, a capacitor connected between the first diffusion region and the second diffusion region, a first switch connected between the first diffusion region and a first reference voltage, and a second switch connected between the second diffusion region and a second reference voltage. 1. A pixel structure for a semiconductor imaging device , comprising:a photodetector in a semiconductor material,a first transfer gate between the photodetector and a first diffusion region in the semiconductor material,a second transfer gate between the photodetector and a second diffusion region in the semiconductor material,a capacitor connected between the first diffusion region and the second diffusion region,a first switch connected between the first diffusion region and a first reference voltage, anda second switch connected between the second diffusion region and a second reference voltage.2. The pixel structure according to claim 1 , wherein the photodetector is a pinned photodiode in a substrate comprising the semiconductor material.3. The pixel structure according to claim 1 , further comprising:buffer amplifiers connected to the first diffusion region and the second diffusion region.4. The pixel structure according to claim 1 , wherein the first reference voltage and the second reference voltage are equal.5. The pixel structure according to claim 4 , wherein the first reference voltage and the second reference voltage are equal to a supply voltage.6. The pixel structure according to one of claim 1 , wherein the first reference voltage or the second reference voltage is connected to a supply voltage.7. The pixel structure according to claim 1 , further comprising:a select transistor connected to a column bus.8 ...

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

An image sensor arrangement for determining a three-dimensional image comprises an image sensor (IS) comprising an array of global shutter pixels and a control unit (CTRL) which is configured to drive the image sensor in an imaging mode (IM) and in a time-of-flight mode (TM). In the imaging mode (IM), the control unit (CTRL) drives the pixels according to an imaging timing sequence. In the time-of-flight mode (TM), the control unit (CTRL) drives the pixels according to a time-of-flight, TOF, timing sequence. At least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase (∅1, ∅2), respectively.

Radiation-hardened package for an electronic device and method of producing a radiation-hardened package

The package includes a carrier (1) and an electronic device (2) on the carrier. A nanomaterial is provided for improved X-ray radiation hardness. A cover (3) or part of a cover (3), which is applied over the electronic device, is at least partially made from nanomaterial. The cover may be a glob top or an injection-molded cover.

Apparatus and method for detecting two photon absorption

The present invention relates to an apparatus for detecting a two-photon absorption event comprising : - a pulsed laser light source having an emission spectrum with a linewidth centred at a first wavelength L 1 ; - a detector comprising a two-dimensional array of n x m pixels, with m and n > 2, wherein each pixel comprises a photodiode having a bandgap energy E g and operable below the avalanche breakdown voltage of the photodiode, - filtering means disposed between the pulsed laser light source and the detector, said filtering means comprising a first filter configured to substantially block light from the pulsed laser light source with a wavelength less than or equal to hc/E g ; wherein the first wavelength L 1 is less than 2hc/E g and is greater than hc/E g ; and - synchronization means for enabling synchronization between the pulsed laser light source and the detector.

Analogue-to-digital converter and method for using the same

The present invention is related to an analogue-to-digital (A/D) converter (1) for converting an input signal (V in ) to a digital code representing said input signal. The A/D converter comprises a comparator (3) for comparing the input signal with a reference signal (V A ), a search logic block (4) for determining the digital code and a digital-to-analogue converter (5) arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. The digital-to-analogue converter comprises at least a first portion implemented with equal capacitors (20). The ADC optionally further comprises a second portion implemented with binary weighted capacitors. The first portion is arranged for being controlled by a thermometer coded signal. The converter avoids charging-discharging of large capacitors during the search and therefore reduces the lost energy.

Time delay integration in imaging devices

Active pixel array with charge binning

A pixel array comprises pixels (10) arranged in columns. A pixel (10) comprises a photo-sensitive element (11) for generating charges responsive to electromagnetic radiation and a buffer amplifier (M2) for buffering a voltage proportional to the charges generated by the photo-sensitive element. A first switch (M3) selectively connects an output of the buffer amplifier to an active pixel mode column output line (9). A second switch (M1) selectively transfers at least part of the charges generated by the photo-sensitive element (11) to a passive pixel mode column output line (15). The pixel (10) can be selectively operated in a conventional, active pixel mode, and in a passive pixel/charge binning mode. The second switch (M1) can be a reset switch, with the second output line operable, on a time-shared basis, as a supply line for providing the reference voltage. Another embodiment has the first switch and the second switch connected to a single column output line which is operable, on a time-shared basis, as the active pixel mode column output line and as the passive pixel mode column output line.

Pixel structure, image sensor device and system with pixel structure, and method of operating the pixel structure

A photodetector (PD) in semiconductor material (S) is provided with a first transfer gate (TX1) between the photodetector and a first diffusion region (FD1) in the semiconductor material, a second transfer gate (TX2) between the photodetector (PD) and a second diffusion region (FD2) in the semiconductor material, a capacitor (C) connected between the first diffusion region (FD1) and the second diffusion region (FD2), a first switch (RST1) connected between the first diffusion region (FD1) and a first reference voltage (V ref 1), and a second switch (RST1) connected between the second diffusion region (FD2) and a second reference voltage (V ref 2).

Pixel array with reduced sensitivity to defects

Method of manufacture of a backside illuminated image sensor

A method of manufacturing a backside illuminated image sensor includes providing a start material that has a layer of semiconductor material on a substrate. The layer of semiconductor material has a first face and a second, backside, face. The layer of semiconductor material is processed to form semiconductor devices in the layer adjacent the first face. At least a part of the substrate is removed to leave an exposed face. A passivation layer is formed on the exposed face, the passivation layer having negative fixed charges. The passivation layer can be Al2O3 (Sapphire). The passivation layer can have a thickness less than 5 μm, advantageously less than 1 μm, and more advantageously in the range 1 nm-150 nm. Another layer, or layers, can be provided on the passivation layer, including: an anti-reflective layer, a layer to improve passivation, a layer including a color filter pattern, a layer comprising a microlens.

Analog-to-digital conversion in pixel arrays

An analog-to-digital converter (51) for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input (81) for receiving the first analog signal level and the second analog signal level, an input (82) for receiving a ramp signal and an input (83) for receiving at least one clock signal. A set of N counters, where N≥2, are arranged to use N clock signals which are offset in phase from one another. A control stage (57) is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage (65, 66) is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Pixel cell and method for operating a pixel cell

A pixel cell (10) comprises a pixel set with a plurality of pixels (11-14), with each pixel of the pixel set (11-14) being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell (10) further comprises a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set (11-14) and to operate the pixel set (11-14) in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel (11-14) is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel (11-14) is used to generate individual rolling shutter output signals.

Pixel of a semiconductor image sensor and method of manufacturing a pixel

Analog-digital-wandler und verwendungsverfahren dafür

Pixel structure with multiple transfer gates

Analog-to-digital conversion in pixel arrays

Analog-to-digital conversion and method of analog-to-digital conversion

An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Image sensor system, electronic device and method for operating an image sensor

Image sensor system, electronic device and method for operating an image sensor

An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.

Image sensor system, electronic device and method for operating an image sensor

An image sensor system has a pixel array (PIX1) with a plurality of pixels (PXL1, PXL2, …, PXLN), each of the pixels comprising a photodiode (PD), a pixel buffer (SF) and a transfer gate (TX) coupled between the photodiode (PD) and an input of the pixel buffer (SF). A voltage supply block (VSB) is configured to generate a pixel supply voltage (VDDPIX) from an input voltage (VDD) based on a first reference voltage (VR1) and to provide the pixel supply voltage (VDDPIX) to the pixel array (PIX1). A calibration processing block (PROC) is configured to determine an average pixel signal (VPA) based on an average of individual pixel signals at outputs of the pixels of the pixel array (PIX1) and to determine a correction value (∆V) based on the average pixel signal (VPA) and a reference pixel signal (VPR). A correction processing block (CORR) is configured to determine the first reference voltage (VR1) based on a combination of a second reference voltage (VR2) and the correction value (∆V).

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

An image sensor arrangement for determining a three-dimensional image comprises an image sensor (IS) comprising an array of global shutter pixels and a control unit (CTRL) which is configured to drive the image sensor in an imaging mode (IM) and in a time-of-flight mode (TM). In the imaging mode (IM), the control unit (CTRL) drives the pixels according to an imaging timing sequence. In the time-of-flight mode (TM), the control unit (CTRL) drives the pixels according to a time-of-flight, TOF, timing sequence. At least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase (Ø1, Ø2), respectively.

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

Pixel array with global shutter

A pixel comprising: a photo-sensitive element for generating charges in response to incident radiation; a sense node; a transfer gate, connected between the photo-sensitive element and the sense node, for controlling transfer of charges to the sense node; a reset switch connected to the sense node for resetting the sense node to a predetermined voltage; a first buffer amplifier having an input connected to the sense node; a first sample stage, connected to an output of the first buffer amplifier, which is selectively operable to sample a value of the sense node; a second sample stage connected in cascade with the first sample stage which is selectively operable to sample a value of the sense node; and a second buffer amplifier having an input connected to the second sample stage; wherein the transfer gate is adapted for transferring substantially all charge from the photosensitive element to the sense node when the transfer gate is opened.

Pixel array with global shutter

A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

Image sensor for determining a three-dimensional image and method for determining a three-dimensional image

An image sensor arrangement for determining a three-dimensional image comprises an image sensor (IS) comprising an array of global shutter pixels and a control unit (CTRL) which is configured to drive the image sensor in an imaging mode (IM) and in a time-of-flight mode (TM). In the imaging mode (IM), the control unit (CTRL) drives the pixels according to an imaging timing sequence. In the time-of-flight mode (TM), the control unit (CTRL) drives the pixels according to a time-of-flight, TOF, timing sequence. At least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase (Ø1, Ø2), respectively.