MEHRSCHICHTKANALSTRUKTUREN UND VERFAHREN ZUM FERTIGEN DERSELBEN IN FELDEFFEKTTRANSISTOREN

Eine Halbleiterstruktur umfasst einen ersten Stapel Halbleiterschichten, der über einem Halbleitersubstrat angeordnet ist, wobei der erste Stapel Halbleiterschichten eine erste SiGe-Schicht und eine Vielzahl von Si-Schichten, die über der ersten SiGe-Schicht angeordnet sind, umfasst und die Si-Schichten im Wesentlichen frei von Ge sind, und einen zweiten Stapel Halbleiterschichten, der benachbart zu dem ersten Stapel Halbleiterschichten angeordnet ist, wobei der zweite Stapel Halbleiterschichten die erste SiGe-Schicht und eine Vielzahl von zweiten SiGe-Schichten, die über der ersten SiGe-Schicht angeordnet sind, umfasst und wobei die erste SiGe-Schicht und die zweiten SiGe-Schichten unterschiedliche Zusammensetzungen aufweisen. Die Halbleiterstruktur umfasst ferner einen ersten Metall-Gate-Stapel, der wechselweise mit dem ersten Stapel Halbleiterschichten angeordnet ist, um ein erstes Bauelement auszubilden, und einen zweiten Metall-Gate-Stapel, der wechselweise mit dem zweiten Stapel Halbleiterschichten ...

Integrated circuit device

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Recessing STI to increase FIN height in FIN-first process

A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.

Recessing STI to Increase FIN Height in FIN-First Process

A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

HALBLEITERVORRICHTUNGSSTRUKTUR UND DEREN HERSTELLUNGSVERFAHREN

Eine Halbleitervorrichtungsstruktur ist bereitgestellt. Die Halbleitervorrichtungsstruktur umfasst ein Substrat und eine dielektrische Finnenstruktur über dem Substrat. Die Halbleitervorrichtungsstruktur umfasst auch eine Halbleiterfinnenstruktur, die an die dielektrische Finnenstruktur angrenzt. Die Halbleitervorrichtungsstruktur umfasst auch einen Metallgatestapel quer über die dielektrische Finnenstruktur und die Halbleiterfinnenstruktur. Die Halbleitervorrichtungsstruktur umfasst auch ein Source/Drain-Merkmal über der Halbleiterfinnenstruktur. Die Halbleitervorrichtungsstruktur umfasst auch einen Source/Drain-Abstandhalter, der zwischen dem Source/Drain-Merkmal und der dielektrischen Finnenstruktur angeordnet ist.

Gate-All-Around Device with Trimmed Channel and Dipoled Dielectric Layer and Methods of Forming the Same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure. 1. A method of forming a semiconductor device , comprising:forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the first stack structure and the second stack structure includes semiconductor layers separated from each other and stacked up along a direction generally perpendicular to a top surface of the substrate;depositing a first interfacial layer around each of the semiconductor layers of the first stack structure and the second stack structure;depositing a gate dielectric layer around the first interfacial layer of the first stack structure and the second stack structure;forming a dipole oxide layer around the gate dielectric layer of the first stack structure and the second stack structure;removing the dipole oxide layer around the gate dielectric layer of the second stack structure;performing an annealing process to the semiconductor device to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer ...

Structure for protecting metal-insulator-metal capacitor in memory device from charge damage

A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process.

FinFET devices and methods of forming

In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.

HALBLEITERSTRUKTUR MIT SELBSTAUSGERICHTETER RÜCKSEITIGER STROMSCHIENE

Die vorliegende Offenbarung stellt eine Halbleiterstruktur bereit, welche ein Substrat aufweisend eine Vorderseite und eine Rückseite; einen aus dem Substrat extrudierten und von einem Isolationsmerkmal umgebenen aktiven Bereich; einen Gate-Stapel gebildet an der Vorderseite des Substrats und angeordnet am aktiven Bereich; ein erstes und ein zweites Source-/Drain-Merkmal (S/D-Merkmal) gebildet am aktiven Bereich und eingefügt mit dem Gate-Stapel dazwischen; ein vorderseitiges Kontaktmerkmal angeordnet an einer oberen Fläche des ersten S/D Merkmals; ein rückseitiges Kontaktmerkmal angeordnet an und elektrisch verbunden mit einer unteren Fläche des zweiten S/D-Merkmals; und eine Halbleiterschicht angeordnet an einer unteren Fläche des ersten S/D-Merkmals mit einer ersten Dicke und einer unteren Fläche des Gate-Stapels mit einer zweiten Dicke, welche größer ist als die erste Dicke, aufweist.

Semiconductor devices and methods for manufacturing the same

A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

Integrated circuit device, semiconductor device, and method for forming the same

Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

Methods for forming integrated circuits

A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

Semiconductor structure and method for manufacturing the same

The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.

LINER FOR A BI-LAYER GATE HELMET AND THE FABRICATION THEREOF

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions. 1. A semiconductor device , comprising:a semiconductor layer;a gate structure disposed over the semiconductor layer;a spacer disposed on a sidewall of the gate structure, wherein a height of the spacer is greater than a height of the gate structure; anda liner disposed on the gate structure and on the spacer, wherein the spacer and the liner have different material compositions.2. The semiconductor device of claim 1 , wherein the liner has a greater dielectric constant than the spacer.3. The semiconductor device of claim 2 , wherein a dielectric constant of the liner is greater than about 4.4. The semiconductor device of claim 1 , wherein:the gate structure is disposed on a sidewall of a first portion of the spacer; andthe liner is disposed on a sidewall of a second portion of the spacer, wherein the second portion is disposed above the first portion.5. The semiconductor device of claim 4 , wherein the liner is further disposed on a top surface of the spacer.6. The semiconductor device of claim 4 , further comprising an interlay dielectric (ILD) layer;wherein:the spacer is disposed between the ILD layer and the gate structure;a height of the ILD layer is greater than a height of the spacer; andthe liner is further disposed on a portion of a sidewall of the ILD layer.7. The semiconductor device of claim 1 , further comprising: a dielectric structure disposed over the liner claim 1 , wherein the dielectric structure contains a dielectric material having a dielectric constant greater than about 4 claim 1 , and wherein the dielectric structure has a T-shaped profile in a cross-sectional view.8. The ...

Devices including gate spacer with gap or void and methods of forming the same

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Semiconductor structure and method for manufacturing the same

Fin spacer protected source and drain regions in FinFETs

A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH MIXED THRESHOLD VOLTAGES BOUNDARY ISOLATION OF MULTIPLE GATES AND STRUCTURES FORMED THEREBY

A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.

Silicon and silicon germanium nanowire formation

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

STRUKTUR UND BILDUNGSVERFAHREN FÜR HALBLEITERVORRICHTUNG MIT ISOLIERUNGSSTRUKTUR

Eine Halbleitervorrichtungsstruktur und ein Verfahren zur Herstellung einer Halbleitervorrichtungsstruktur werden bereitgestellt. Die Halbleitervorrichtungsstruktur umfasst eine Halbleiterfinne über einem Substrat und mehrere Halbleiternanostrukturen, die über der Halbleiterfinne hängen. Die Halbleitervorrichtungsstruktur umfasst auch einen Gatestapel, der sich über die Halbleiterfinne erstreckt, und der Gatestapel ist um jede der Halbleiternanostrukturen gewickelt. Die Halbleitervorrichtungsstruktur umfasst ferner eine erste epitaktische Struktur und eine zweite epitaktische Struktur, die die Halbleiternanostrukturen sandwichartig einschließen. Jede der ersten epitaktischen Struktur und der zweiten epitaktischen Struktur erstreckt sich über eine obere Fläche der Halbleiterfinne hinaus. Weiterhin umfasst die Halbleitervorrichtungsstruktur eine Isolierungsstruktur zwischen der Halbleiterfinne und dem Gatestapel. Die Isolierungsstruktur erstreckt sich ferner über gegenüberliegende Seitenwände ...

Silicon and Silicon Germanium Nanowire Formation

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process. 1. A semiconductor device comprising: a first nanostructure channel extending from a first source region to a first drain region, the first nanostructure channel having a first width;', 'a second nanostructure channel extending from the first source region to the first drain region, the second nanostructure channel being over the first nanostructure channel, the second nanostructure channel having a second width less than the first width;', 'a first dielectric layer surrounding the first nanostructure channel and the second nanostructure channel; and', 'a first gate electrode over the first dielectric layer and at least partially surrounding the first nanostructure channel and the second nanostructure channel., 'a first nanostructure transistor over a substrate, the first nanostructure transistor comprising2. The semiconductor device of further comprising:an interfacial layer surrounding the first nanostructure channel and the second nanostructure channel, the interfacial layer being between the first dielectric layer and the first nanostructure channel and the second nanostructure channel; anda first work ...

GATE-ISOLATION FÜR MULTIGATE-VORRICHTUNG

Hier werden selbstjustierte Gate-Schneideverfahren offenbart, mit denen dielektrische Gate-Isolationsfinnen hergestellt werden, um Gates von Multigate-Vorrichtungen gegeneinander zu isolieren. Eine beispielhafte Vorrichtung weist Folgendes auf: eine erste Multigate-Vorrichtung mit ersten Source-/Drain-Elementen und einem ersten Metallgate, das eine erste Kanalschicht umschließt; und eine zweite Multigate-Vorrichtung mit zweiten Source-/Drain-Elementen und einem zweiten Metallgate, das eine zweite Kanalschicht umschließt. Eine dielektrische Gate-Isolationsfinne trennt das erste Metallgate von dem zweiten Metallgate. Die dielektrische Gate-Isolationsfinne weist eine erste dielektrische Schicht mit einer ersten Dielektrizitätskonstante und eine zweite dielektrische Schicht mit einer zweiten Dielektrizitätskonstante auf, die über der ersten dielektrischen Schicht angeordnet ist. Die zweite Dielektrizitätskonstante ist höher als die erste Dielektrizitätskonstante. Das erste Metallgate und das ...

SELBSTJUSTIERENDE RÜCKSEITIGE SOURCE-KONTAKT-STRUKTUR UND VERFAHREN ZU IHRER HERSTELLUNG

Eine Halbleitervorrichtung gemäß der vorliegenden Offenbarung weist auf: ein Source-Merkmal und ein Drain-Merkmal, mehrere Halbleiter-Nanostrukturen, die sich zwischen dem Source-Merkmal und dem Drain-Merkmal erstrecken, eine Gate-Struktur, die sich um jede der mehreren Halbleiter-Nanostrukturen herum legt, eine untere dielektrische Schicht über der Gate-Struktur und dem Drain-Merkmal, eine rückseitige Stromversorgungsschiene, die über der unteren dielektrischen Schicht angeordnet ist, und einen rückseitigen Source-Kontakt, der zwischen dem Source-Merkmal und der rückseitigen Stromversorgungsschiene angeordnet ist. Der rückseitige Source-Kontakt erstreckt sich durch die untere dielektrische Schicht.

Mixed workfunction metal for nanosheet device

A method includes depositing a first conductive material on a first-type channel stack and a second-type channel stack, the first conductive material having a first workfunction, the first conductive material being formed between multiple layers of both the first-type channel stack and the second-type channel stack. The method further includes partially removing the first conductive material from the second-type channel stack such that the first conductive material remains between the multiple layers of both the first-type channel stack and the second-type channel stack and fully removing the first conductive material from the second-type channel stack. The method further includes depositing a second conductive material over both the first-type channel stack and the second-type channel stack such that the second conductive material covers both the first-type channel stack and the first conductive material in between the layers of the first-type channel stack, the second conductive material ...

MEHRFACHGATEVORRICHTUNG UND ZUGEHÖRIGE VERFAHREN

Ein Verfahren zum Herstellen einer Vorrichtung umfasst das Bereitstellen einer ersten Finne in einem Bereich einer ersten Vorrichtungsart und einer zweiten Finne in einem Bereich einer zweiten Vorrichtungsart. Sowohl die erste als auch die zweite Finne weisen eine Mehrzahl von Halbleiterkanalschichten auf. Eine zweistufige Vertiefung eines STI-Bereichs auf gegenüberliegenden Seiten sowohl der ersten als auch der zweiten Finne wird durchgeführt, um eine erste Anzahl von Halbleiterkanalschichten der ersten Finne und eine zweite Anzahl von Halbleiterkanalschichten der zweiten Finne freizulegen. Eine erste Gatestruktur wird im Bereich der ersten Vorrichtungsart gebildet, und eine zweite Gatestruktur wird im Bereich der zweiten Vorrichtungsart gebildet. Die erste Gatestruktur wird über der ersten Finne mit der ersten Anzahl freigelegter Halbleiterkanalschichten gebildet, und die zweite Gatestruktur wird über der zweiten Finne mit der zweiten Anzahl freigelegter Halbleiterkanalschichten gebildet ...

P-METALL-GATE-FIRST-GATE-ERSETZUNGSPROZESS FÜR MEHRFACHGATE-VORRICHTUNGEN

Es werden Mehrfachgate-Vorrichtungen und Verfahren zum Herstellen davon hierin offenbart. Ein beispielhaftes Verfahren umfasst das Bilden einer Gate-Dielektrikumsschicht um erste Kanalschichten herum in einer p-Gate-Region und um zweite Kanalschichten herum in einer n-Gate-Region. Es werden Opfermerkmale zwischen den zweiten Kanalschichten in der n-Gate-Region gebildet. Es wird eine p-Austrittsarbeitsschicht über der Gate-Dielektrikumsschicht in der p-Gate-Region und der n-Gate-Region gebildet. Nach dem Entfernen der p-Austrittsarbeitsschicht aus der n-Gate-Region werden die Opfermerkmale zwischen den zweiten Kanalschichten in der n-Gate-Region entfernt. Es wird eine n-Austrittsarbeitsschicht über der Gate-Dielektrikumsschicht in der n-Gate-Region gebildet. Es wird eine Metallfüllschicht über der p-Austrittsarbeitsschicht in der p-Gate-Region und der n-Austrittsarbeitsschicht in der n-Gate-Region gebildet.

Semiconductor device and method of forming the same

A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH STRESSOR

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure.

Semiconductor device

A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

Semiconductor structure and method for forming the same

A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.

Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion. 1. A semiconductor structure , comprising:a substrate;a fin disposed on the substrate, the fin including a source region, a drain region, and a channel region disposed between the source and drain regions, the channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein;a gate stack engaging the channel region of the fin; andgate spacers disposed between the gate stack and the source and drain regions of the fin,wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.2. The semiconductor structure of claim 1 , wherein the ...

Integrated Circuit with a Fin and Gate Structure and Method Making the Same

The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition. 1. A semiconductor structure comprising:a first device fin and a second device fin formed on a substrate;a first dielectric fin and a second dielectric fin formed on the substrate, wherein the first dielectric fin being interspersed between the first and second device fins, the second dielectric fin is spaced away from the first and second device fins; anda gate stack formed on the first and second device fins and the first and second dielectric fins, whereinthe first dielectric fin includes a first dielectric material layer and is free of a second dielectric material layer;the second dielectric fin includes both the first and second dielectric material layers; andthe first and second dielectric material layers are different from each other in composition.2. The semiconductor structure of claim 1 , whereinthe first dielectric material layer includes a high-k dielectric material; andthe second dielectric material layer includes a carbon-containing material.3. The semiconductor structure of claim 2 , whereinthe first dielectric material layer is chosen from a metal oxide, a metal nitride and a combination thereof; andthe second dielectric material layer includes carbon and silicon.4. The semiconductor structure of claim 3 , wherein{'sub': 2', '2', '2', '3, 'the first dielectric material layer includes at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and aluminum oxide (AlO); and'}the second dielectric material layer includes one of silicon carbon oxide, silicon ...

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends exceeding a top surface of the semiconductor fin. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure further extends exceeding opposite sidewalls of the first epitaxial structure.

GATE-ALL-AROUND-VORRICHTUNGEN MIT SELBSTAUSGERICHTETER ABDECKUNG ZWISCHEN KANAL UND RÜCKSEITIGER LEISTUNGSSCHIENE

Eine Halbleitervorrichtung weist eine erste Interconnect-Struktur; mehrere Kanalschichten, die über der ersten Interconnect-Struktur gestapelt sind; einen Gate-Stapel, der um jede der Kanalschichten mit Ausnahme einer untersten der Kanalschichten geschlungen ist; ein Source/Drain-Element, das den Kanalschichten benachbart ist; eine erste leitfähige Durchkontaktierung, die die erste Interconnect-Struktur mit einem Boden des Source/Drain-Elements verbindet; und ein dielektrisches Element zwischen der untersten der Kanalschichten und der ersten leitfähigen Durchkontaktierung auf.

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION THEREOF

MULTI-GATE DEVICES AND METHOD OF FABRICATING THE SAME

Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin. 1. A method of manufacturing a semiconductor device , comprising:providing a semiconductor substrate;forming an epitaxial stack on the semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers;patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin;recessing a portion of the semiconductor fin to form source/drain spaces;laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities;forming inner spacers in the plurality of cavities;performing a treatment process to remove an inner spacer residue in the source/drain spaces;forming S/D features in the source/drain spaces; andforming a gate structure engaging the semiconductor fin.2. The method of claim 1 , wherein the performing the treatment process comprises a selectively etching process.3. The method of claim 2 , wherein the selectively etching process comprises:forming a patterned mask layer having an opening, ...

SEMICONDUCTOR DEVICE STRUCTURE WITH SILICIDE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. A top surface of the dielectric fin is close to the epitaxial structure. The semiconductor device structure includes a silicide layer wrapping around the epitaxial structure and partially between the dielectric fin and the epitaxial structure. The silicide layer covers a lower surface of the epitaxial structure, and the lower surface is lower than the top surface of the dielectric fin.

DRAINSEITIGE VERTIEFUNG FÜR VORRICHTUNG MIT RÜCKSEITIGER STROMSCHIENE

Eine Halbleitertransistorvorrichtung umfasst eine Kanalstruktur, eine Gatestruktur, eine erste Source-/Drain-Epitaxiestruktur, eine zweite Source-/Drain-Epitaxiestruktur, einen Gate-Kontakt und einen rückseitigen Source-/Drain-Kontakt. Die Gatestruktur umschließt die Kanalstruktur. Die erste Source-/Drain-Epitaxiestruktur und die zweite Source-/Drain-Epitaxiestruktur sind an entgegengesetzten Enden der Kanalstruktur angeordnet. Der Gate-Kontakt ist auf der Gatestruktur angeordnet. Der rückseitige Source-/Drain-Kontakt ist unter der ersten Source-/Drain-Epitaxiestruktur angeordnet. Die zweite Source-/Drain-Epitaxiestruktur weist eine konkave untere Fläche auf.

Semiconductor device structure and method forming the same

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends exceeding a top surface of the semiconductor fin. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure further extends exceeding opposite sidewalls of the first epitaxial structure.

Semiconductor device

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

SILIZIUMKANAL-ANLASSEN

Eine Halbleitervorrichtung gemäß der vorliegenden Offenbarung umfasst eine Finnenstruktur über einem Substrat, vertikal gestapelte Siliziumnanostrukturen, die über der Finnenstruktur angeordnet sind, eine Isolationsstruktur, die um die Finnenstruktur angeordnet ist, eine germaniumhaltige Grenzflächenschicht, die um jede der vertikal gestapelten Siliziumnanostrukturen gewickelt ist, eine Gatedielektrikumschicht, die um die germaniumhaltige Grenzflächenschicht gewickelt ist, und eine Gateelektrodenschicht, die um die Gatedielektrikumschicht gewickelt ist.

Method for forming a semiconductor arrangement

A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Method for manufacturing semiconductor device

A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

Buried Power Rail and Method Forming Same

A method includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions. 1. A method of forming an integrated circuit structure , the method comprising:etching a semiconductor substrate to form two semiconductor strips, wherein the two semiconductor strips are over a bulk portion of the semiconductor substrate;etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate;forming a liner dielectric layer lining the trench;forming a buried contact in the trench;forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips; andforming isolation regions on opposite sides of the two semiconductor strips, wherein the buried power rail is underlying a portion of the isolation regions.2. The method of claim 1 , wherein the buried power rail is at a same level as a portion of the two semiconductor strips.3. The method of further comprising:recessing the isolation regions, wherein top portions of the two semiconductor strips protrude higher than top surfaces of remaining portions of the isolation regions to form a first semiconductor fin and a second conductor fin;forming a first source/drain region based on the first semiconductor fin; andforming a contact plug to electrically connect the first source/drain region to the buried power rail and the buried contact.4. The ...

Liner for a bi-layer gate helmet and the fabrication thereof

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Memory component

A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack. 1. A method for forming a semiconductor device structure , comprising:forming a first gate stack and a second gate stack over a substrate, wherein the substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure, the first gate stack wraps around a first upper portion of the first fin structure, and the second gate stack wraps around a second upper portion of the second fin structure;partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack;forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack; andforming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the second stressor is in direct contact with the second fin structure.3. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the first fin ...

Transistors with different threshold voltages

A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Dual channel gate all around transistor device and fabrication methods thereof

A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the ...

KAPAZITÄTSREDUZIERUNG FÜR EINE VORRICHTUNG MIT EINER RÜCKSEITIGEN LEISTUNGSVERSORGUNGSSCHIENE

Eine Halbleitertransistorvorrichtung weist eine Kanalstruktur, eine Gatestruktur, eine erste epitaktische Source-/Drainstruktur, eine zweite epitaktische Source-/Drainstruktur, einen Gatekontakt und einen rückseitigen Source-/Drainkontakt auf. Die Gatestruktur umschließt die Kanalstruktur. Die erste epitaktische Source/Drainstruktur und die zweite epitaktische Source/Drainstruktur sind an entgegengesetzten Enden der Kanalstruktur angeordnet. Der Gatekontakt ist auf der Gatestruktur angeordnet. Der rückseitige Source-/Drainkontakt ist unter der ersten epitaktischen Source-/Drainstruktur angeordnet. Die erste epitaktische Source-/Drainstruktur weist eine konkave untere Fläche auf, die den rückseitigen Source-/Drainkontakt kontaktiert.

SEMICONDUCTOR DEVICE STRUCTURE WITH SILICIDE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a first dielectric layer over the base portion and a first sidewall of the fin portion. The method includes forming a first spacer layer over the first dielectric layer. The method includes forming a first dielectric fin over the first spacer layer. The method includes forming an epitaxial structure over the fin portion, wherein a void is surrounded by the epitaxial structure, the first dielectric layer, and the first spacer layer. The method includes removing the first spacer layer between the epitaxial structure and the first dielectric fin. The method includes forming a silicide layer over the epitaxial structure, wherein a first lower portion of the silicide layer covers a lower surface of the epitaxial structure and is in the void. 1. A method for forming a semiconductor device structure , comprising:providing a substrate, wherein the substrate has a base portion and a fin portion over the base portion;forming a first spacer layer over the base portion and a first sidewall of the fin portion;forming a first dielectric fin over the first spacer layer, wherein the first spacer layer separates the first dielectric fin from the fin portion and the base portion;forming an epitaxial structure over the fin portion, wherein the first spacer layer is partially between the epitaxial structure and the first dielectric fin;removing the first spacer layer between the epitaxial structure and the first dielectric fin; andforming a silicide layer wrapping around the epitaxial structure.2. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:forming a second spacer layer over a second sidewall of the fin portion and the base portion during forming the first spacer layer over the first sidewall and the base portion, wherein the epitaxial structure is between the first spacer layer and the second ...

Forming gate stacks of FinFETs through oxidation

An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Gate-all-around field-effect transistor device

A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Selective Inner Spacer Implementations

A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and a second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure. 1. A semiconductor device , comprising: a first vertical stack of channel members,', 'a first gate structure over and around the first vertical stack of channel members,', 'a plurality of inner spacer features; and, 'a first plurality of gate-all-around (GAA) devices in a first device area, wherein each of the first plurality of GAA devices comprises a second vertical stack of channel members, and', 'a second gate structure over and around the second vertical stack of channel members,, 'a second plurality of GAA devices in a second device area, wherein each of the second plurality of GAA devices compriseswherein two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features,wherein two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.2. The semiconductor device of claim 1 , wherein the first device area is a logic device area and the second device area is a memory device area.3. The ...

TRANSISTOREN MIT VERSCHIEDENEN SCHWELLENSPANNUNGEN

Ein Halbleiter, der einen ersten Gate-all-around-Transistor (GAA-Transistor), einen zweiten GAA-Transistor und einen dritten GAA-Transistor aufweist. Der erste GAA-Transistor enthält mehrere erste Kanalelemente, eine Gate-Dielektrikumschicht über den mehreren ersten Kanalelementen, eine erste Austrittsarbeitsschicht über der Gate-Dielektrikumschicht, und eine Haftschicht über der ersten Austrittsarbeitsschicht. Der zweite GAA-Transistor enthält mehrere zweite Kanalelemente, die Gate-Dielektrikumschicht über den mehreren zweiten Kanalelementen und eine zweite Austrittsarbeitsschicht über der Gate-Dielektrikumschicht, die erste Austrittsarbeitsschicht über und in Kontakt mit der zweiten Austrittsarbeitsschicht, und die Haftschicht über der ersten Austrittsarbeitsschicht. Der dritte GAA-Transistor enthält mehrere dritte Kanalelemente, die Gate-Dielektrikumschicht über den mehreren dritten Kanalelementen und die Haftschicht über der Gate-Dielektrikumschicht.

FINFET-VORRICHTUNGEN MIT RÜCKSEITIGER STROMSCHIENE UND RÜCKSEITIGER SELBSTJUSTIERENDER DURCHKONTAKTIERUNG

Eine Halbleiterstruktur umfasst eine Stromschiene auf einer Rückseite der Halbleiterstruktur, eine erste Interconnect-Struktur auf einer Vorderseite der Halbleiterstruktur, und ein Source-Merkmal, ein Drain-Merkmal, eine erste Halbleiterfinne und eine Gate-Struktur, die sich zwischen der Stromschiene und der ersten Interconnect-Struktur befinden. Die erste Halbleiterfinne verbindet das Source-Merkmal und das Drain-Merkmal. Die Gate-Struktur ist auf einer Vorderfläche und zwei Seitenflächen der ersten Halbleiterfinne angeordnet. Die Halbleiterstruktur umfasst des Weiteren eine Isolationsstruktur, die zwischen der Stromschiene und dem Drain-Merkmal und zwischen der Stromschiene und der ersten Halbleiterfinne angeordnet ist, und eine Durchkontaktierung, die durch die Isolationsstruktur hindurch verläuft und das Source-Merkmal mit der Stromschiene verbindet.

Semiconductor structure

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a dielectric fin structure over the substrate. The semiconductor device structure also includes a semiconductor fin structure adjacent to the dielectric fin structure. The semiconductor device structure also includes a metal gate stack across the dielectric fin structure and the semiconductor fin structure. The semiconductor device structure also includes a source/drain feature over the semiconductor fin structure. The semiconductor device structure also includes a source/drain spacer interposed between the source/drain feature and the dielectric fin structure.

FinFETs with Source/Drain Cladding

A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Hybrid scheme for improved performance for P-type and N-type FinFETs

A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Structure and Method for FinFET Device with Buried Sige Oxide

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer. 1. A semiconductor device , comprising:a substrate;a fin feature over the substrate, wherein the fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion, wherein the second semiconductor material is different from the first semiconductor material;a semiconductor oxide feature disposed on sidewalls of the first portion; anda gate stack disposed on the fin feature, wherein the gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature, wherein a portion of the gate dielectric layer is below the interfacial layer.2. The semiconductor device of claim 1 , wherein the portion of the gate dielectric layer is directly under a top surface of the first portion.3. The semiconductor device of claim 1 , wherein the portion of the gate dielectric layer is directly under a portion of the semiconductor oxide feature.4. The semiconductor device of claim 1 , wherein the portion of the gate dielectric layer is directly under the interfacial layer.5. The semiconductor device of claim 1 , ...

Hybrid Scheme for Improved Performance for P-type and N-type FinFETs

A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Semiconductor device structures and methods for forming the same

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

INTEGRATED CIRCUIT STRUCTURE AND THE METHOD FOR FORMING THE SAME

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure includes a substrate including a first region and a second region, a first FET device disposed in the first region, and a second FET device disposed in the second region. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets stacked over the substrate and separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. In some embodiments, the fin structure has a first width, each of the nanosheets has a second width, and the second width is greater than the first width. 1. A semiconductor structure comprising:a substrate comprising a first region and a second region; a fin structure;', 'a first work function metal layer over the fin structure; and', 'a high-k gate dielectric layer between the first work function metal layer and the fin structure; and, 'a first field effect transistor (FET) device disposed in the first region, wherein the first FET device comprises a plurality of nanosheets stacked over the substrate and separated from each other;', 'a second work function metal layer surrounding each of the nanosheets; and', 'the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets,, 'a second FET device disposed in the second region, wherein the second FET device compriseswherein the fin structure has a first width, each of the nanosheets has a second width, and the second width is greater than the first width.2. The semiconductor structure of claim 1 , wherein the first work function metal layer is a p-type work function metal layer claim 1 , and the second work function metal layer is an n-type work function metal layer.3. The ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.

SELBSTAUSGERICHTETES METALL-GATE FÜR MULTIGATE-VORRICHTUNG

Offenbart hierin sind selbstausgerichtete Gate-Schneidetechniken für Multigate-Vorrichtungen, die Multigate-Vorrichtungen mit asymmetrischen Metallgate-Profilen und asymmetrischen Source/Drain-Merkmal-Profilen bereitstellen. Eine beispielhafte Multigate-Vorrichtung umfasst eine Kanalschicht, ein Metallgate, das einen Abschnitt der Kanalschicht umwickelt, und Source/Drain-Merkmale, die über einem Substrat angeordnet sind. Die Kanalschicht erstreckt sich entlang einer ersten Richtung zwischen den Source/Drain-Merkmalen. Eine erste dielektrische Finne und eine zweite dielektrische Finne sind über dem Substrat angeordnet und unterschiedlich konfiguriert. Die Kanalschicht erstreckt sich in einer zweiten Richtung zwischen der ersten dielektrischen Finne und der zweiten dielektrischen Finne. Das Metallgate ist zwischen der Kanalschicht und der zweiten dielektrischen Finne angeordnet. In einigen Ausführungsformen ist die erste dielektrische Finne auf einem ersten Isolationsmerkmal angeordnet und ...

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a substrate, a first dielectric layer adjacent to the fin structure, and a second dielectric layer covering a sidewall of the first dielectric layer. The first dielectric layer has a different etching selectivity than the second dielectric layer. A bottom portion of the second dielectric layer is lower than a bottom surface of the first dielectric layer. The semiconductor device structure also includes a source/drain feature over the fin structure and covering a sidewall of the second dielectric layer, nanostructures over the fin structure, and a gate stack wrapping around the nanostructures.

Semiconductor Devices and Methods

Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width. 1. A method comprising:depositing a first sheet over a semiconductor substrate;depositing a first semiconductor material over the first sheet;depositing a second sheet over the first semiconductor material;depositing a second semiconductor material over the second sheet;patterning the first sheet, the first semiconductor material, the second sheet, and the second semiconductor material into a fin with a first width and a second width, the first width being greater than the second width;removing the first sheet and the second sheet to form a first nanostructure from the first semiconductor material and a second nanostructure from the second semiconductor material;depositing a gate dielectric layer to surround the first nanostructure and the second nanostructure; anddepositing a gate electrode around the gate dielectric layer.2. The method of claim 1 , wherein the depositing the gate electrode comprises forming the gate electrode at least partially over a first corner of the first nanostructure.3. The method of claim 2 , wherein after the depositing the gate dielectric layer claim 2 , a gate spacer is adjacent to the gate dielectric layer and at least partially over a second corner of the first nanostructure claim 2 , the second corner being adjacent to a portion of the fin with the ...

STRUKTUR UND BILDUNGSVERFAHREN EINER HALBLEITERVORRICHTUNG MITSTRESSOR

Es wird eine Halbleitervorrichtungsstruktur und ein Verfahren zum Bilden einer Halbleitervorrichtungsstruktur bereitgestellt. Die Halbleitervorrichtungsstruktur enthält mehrere Halbleiternanostrukturen über einem Substrat und zwei epitaktische Strukturen über dem Substrat. Jede der Halbleiternanostrukturen liegt zwischen den epitaktischen Strukturen und die epitaktischen Strukturen sind p-Typ dotiert. Die Halbleitervorrichtungsstruktur enthält auch einen Gate-Stapel, der die Halbleiternanostrukturen umhüllt. Die Halbleitervorrichtungsstruktur enthält ferner eine dielektrische Stressorstruktur zwischen dem Gate-Stapel und dem Substrat. Die epitaktischen Strukturen erstrecken sich über eine obere Fläche der dielektrischen Stressorstruktur hinaus.

Semiconductor device

A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

HALBLEITERVORRICHTUNGEN MIT RÜCKSEITIGER STROMSCHIENE UND RÜCKSEITIGER SELBSTJUSTIERENDER DURCHKONTAKTIERUNG

Eine Halbleiterstruktur umfasst ein Source-Merkmal, ein Drain-Merkmal, eine oder mehrere Kanalschichten, die das Source-Merkmal und das Drain-Merkmal verbinden, und eine Gate-Struktur zwischen dem Source-Merkmal und dem Drain-Merkmal. Die Gate-Struktur nimmt jede der einen oder der mehreren Kanalschichten in Eingriff. Die Halbleiterstruktur umfasst des Weiteren ein erstes Source-Silicid-Merkmal über dem Source-Merkmal, einen Source-Kontakt über dem ersten Source-Silicid-Merkmal, ein zweites Source-Silicid-Merkmal unter dem Source-Merkmal, eine Durchkontaktierung unter dem zweiten Source-Silicid-Merkmal, und eine Stromschiene unter der Durchkontaktierung. Das erste und das zweite Source-Silicid-Merkmal umgeben das Source-Merkmal in einer Querschnittsansicht vollständig. Die Stromschiene ist eine rückseitige Stromschiene.

GATE-STRUKTURIERUNGSPROZESS FÜR MEHR-GATE-VORRICHTUNGEN

Ein Verfahren umfasst das Bereitstellen einer ersten und einer zweiten Kanalschicht in einer p-Region bzw. in einer n-Region, das Bilden einer Gate-Dielektrikumschicht um die erste und die zweite Kanalschicht herum, und das Bilden einer Opferschicht um die Gate-Dielektrikumschicht herum. Die Opferschicht fließt in den Raum zwischen den ersten Kanalschichten und zwischen den zweiten Kanalschichten ein. Das Verfahren umfasst des Weiteren das Ätzen der Opferschicht, dergestalt, dass nur Abschnitte der Opferschicht in dem Raum zwischen den ersten Kanalschichten und zwischen den zweiten Kanalschichten zurückbleiben, das Bilden einer Maske, die die p-Region bedeckt und die n-Region frei lässt, das Entfernen der Opferschicht aus der n-Region, das Entfernen der Maske, und das Bilden einer n-Austrittsarbeitsmetallschicht um die Gate-Dielektrikumschicht in der n-Region herum und über der Gate-Dielektrikumschicht und der Opferschicht in der p-Region.

Semiconductor device structure and method for forming the same

A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.

HALBLEITERSTRUKTUR UND HERSTELLUNGSVERFAHREN

Die vorliegende Offenbarung stellt eine Halbleiterstruktur und ein Herstellungsverfahren bereit. Die Halbleiterstruktur weist ein Substrat, einen Transistor auf dem Substrat und eine Isolationsstruktur auf. Der Transistor weist einen epitaxialen Bereich auf dem Substrat auf, welcher eine erste Seitenbegrenzung und eine zweite Seitenbegrenzung gegenüber der ersten Seitenbegrenzung aufweist, wobei die erste Seitenbegrenzung des epitaxialen Bereichs konform zu einer Seitenwand der Isolationsstruktur ist.

HALBLEITERVORRICHTUNGEN MIT DIELEKTRISCHEN FINNEN UND VERFAHREN ZU DEREN HERSTELLUNG

Ein Verfahren umfasst ein Bereitstellen einer Struktur, die Folgendes aufweist: zwei Finnen, die sich von einem Substrat erstrecken; eine Isolationsstruktur, die untere Teile der Finnen isoliert; Source/Drain-Elemente (S/D-Elemente) über jeder der Finnen; eine dielektrische Finne, die in einer Längsrichtung parallel zu den Finnen orientiert ist und zwischen den zwei Finnen und über der Isolationsstruktur angeordnet ist; einen Dummy-Gatestapel über der Isolationsstruktur, den Finnen und der dielektrischen Finne; und eine oder mehrere dielektrische Schichten über Seitenwänden des Dummy-Gatestapels. Das Verfahren umfasst weiterhin Folgendes: Entfernen des Dummy-Gatestapels, sodass ein Gategraben in der einen oder den mehreren dielektrischen Schichten entsteht, wobei die dielektrische Finne in dem Gategraben freigelegt wird; Trimmen der dielektrischen Finne, um eine Breite der dielektrischen Finne zu reduzieren; und nach dem Trimmen Herstellen eines High-k-Metallgates in dem Gategraben.

Semiconductor device

According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Semiconductor device

In one example, a semiconductor device includes a substrate, a first elongated fin structure disposed on the substrate, and a second elongated fin structure disposed on the substrate. The longitudinal axis of the first elongated fin structure is aligned with a longitudinal axis of the second elongated fin structure. The device further includes a dummy structure extending between the first elongated fin structure and the second elongated fin structure. The dummy structure includes a dielectric material.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a substrate, a first dielectric layer adjacent to the fin structure, and a second dielectric layer covering a sidewall of the first dielectric layer. The first dielectric layer has a different etching selectivity than the second dielectric layer. A bottom portion of the second dielectric layer is lower than a bottom surface of the first dielectric layer. The semiconductor device structure also includes a source/drain feature over the fin structure and covering a sidewall of the second dielectric layer, nanostructures over the fin structure, and a gate stack wrapping around the nanostructures ...

GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICE

A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires. 1. A method of forming a semiconductor device , the method comprising:forming semiconductor fins over a substrate and a patterned mask layer over the semiconductor fins, wherein the semiconductor fins comprise epitaxial layers over semiconductor strips, wherein the epitaxial layers comprise alternating layers of a first semiconductor material and a second semiconductor material;forming hybrid fins over isolation regions on opposing sides of the semiconductor fins, wherein each of the hybrid fins comprises a dielectric fin and a dielectric structure over the dielectric fin;forming a gate structure over the semiconductor fins and over the hybrid fins;removing first portions of the patterned mask layer, first portions of the epitaxial layers, and first portions of the dielectric structures that are disposed beyond sidewalls of the gate structure without substantially removing the dielectric fins;forming an interlayer dielectric (ILD) layer over the dielectric fins and around the gate structure;removing a gate ...

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a dielectric fin structure over the substrate. The semiconductor device structure also includes a semiconductor fin structure adjacent to the dielectric fin structure. The semiconductor device structure also includes a metal gate stack across the dielectric fin structure and the semiconductor fin structure. The semiconductor device structure also includes a source/drain feature over the semiconductor fin structure. The semiconductor device structure also includes a source/drain spacer interposed between the source/drain feature and the dielectric fin structure.

FinFET structure and method for fabricating the same

A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.

Integrated chip

In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material. The first gate electrode structure also includes a passivation layer that completely surrounds the first and second conductive rings, is arranged directly between the first and second nanosheet channel structures, and comprises a second material different ...

FinFETs with source/drain cladding

A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH STRESSOR

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

STRUKTUR UND BILDUNGSVERFAHREN EINER HALBLEITERVORRICHTUNG MITVERSPANNER

Eine Halbleitervorrichtungsstruktur und ein Verfahren zum Bilden einer Halbleitervorrichtungsstruktur werden bereitgestellt. Die Halbleitervorrichtungsstruktur weist mehrere Halbleiter-Nanostrukturen auf einem Substrat und zwei epitaxiale Strukturen auf dem Substrat auf. Jede der Halbleiter-Nanostrukturen befindet sich zwischen den epitaxialen Strukturen. Die Halbleitervorrichtungsstruktur weist außerdem einen Gate-Stapel auf, der um die Halbleiter-Nanostrukturen herum gelegt ist. Die Halbleitervorrichtungsstruktur weist des Weiteren eine Verspannerstruktur zwischen dem Gate-Stapel und dem Substrat auf. Die epitaxialen Strukturen erstrecken sich über eine Oberseite der Verspannerstruktur hinaus.

Method of forming semiconductor structure

A method includes depositing a first conductive material on a first-type channel stack and a second-type channel stack, the first conductive material having a first workfunction, the first conductive material being formed between multiple layers of both the first-type channel stack and the second-type channel stack. The method further includes partially removing the first conductive material from the second-type channel stack such that the first conductive material remains between the multiple layers of both the first-type channel stack and the second-type channel stack and fully removing the first conductive material from the second-type channel stack. The method further includes depositing a second conductive material over both the first-type channel stack and the second-type channel stack such that the second conductive material covers both the first-type channel stack and the first conductive material in between the layers of the first-type channel stack, the second conductive material ...

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME

Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof

A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin. 1. A method of forming a semiconductor device , comprising:providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, wherein the first and second semiconductor layers have different material compositions and are alternatingly disposed with respect to each other in a vertical direction, wherein each of the first and second semiconductor layers extends over first and second regions of the substrate;patterning the first semiconductor layers and the second semiconductor layers to form a first fin in the first region and a second fin in the second region;removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin;forming a ...

GATE-ISOLATION FÜR MEHR-GATE-VORRICHTUNG

Die im vorliegenden Text offenbarten Gate-Schneidtechniken bilden Gate-Isolationsfinnen, um die Metall-Gates von Mehr-Gate-Vorrichtungen voneinander zu isolieren, bevor die Mehr-Gate-Vorrichtungen gebildet werden, und insbesondere, bevor die Metall-Gates der Mehr-Gate-Vorrichtungen gebildet werden. Eine beispielhafte Vorrichtung umfasst eine erste Mehr-Gate-Vorrichtung mit ersten Source/Drain-Merkmalen und einem ersten Metall-Gate, das eine erste Kanalschicht umgibt, und eine zweite Mehr-Gate-Vorrichtung mit zweiten Source/Drain-Merkmalen und einem zweiten Metall-Gate, das eine zweite Kanalschicht umgibt. Eine Gate-Isolationsfinne, die das erste Metall-Gate und das zweite Metall-Gate trennt, weist eine erste dielektrische Schicht mit einer ersten Dielektrizitätskonstante und eine zweite dielektrische Schicht mit einer zweiten Dielektrizitätskonstante, die über der ersten dielektrischen Schicht angeordnet ist, auf. Die zweite Dielektrizitätskonstante ist kleiner als die erste Dielektrizitätskonstante ...

Methods of fabricating semiconductor devices

A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.

Methods for forming semiconductor device and semiconductor structure, and semiconductor device

Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

Method for manufacturing semiconductor device

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

A METHOD (AND RELATED APPARATUS) FOR FORMING A SEMICONDUCTOR DEVICE WITH REDUCED SPACING BETWEEN NANOSTRUCTURE FIELD-EFFECT TRANSISTORS

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby

A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.

Integrated Circuits with Backside Power Rails

Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer. 1. An integrated circuit device comprising:a substrate that includes a silicon (Si) layer and a silicon germanium (SiGe) layer over the Si layers;a plurality of fins over the substrate; andan interconnect conductor disposed within the Si layer and extending between two of the plurality of fins.2. The integrated circuit device of claim 1 , further comprising:a source/drain feature disposed over one of the plurality of fins; anda source/drain contact in electrical communication with the source/drain feature,wherein the source/drain contact is in electrical communication with the interconnect conductor.3. The integrated circuit device of claim 2 , wherein the interconnect conductor extends from between two of the plurality of fins claim 2 , through the SiGe layer claim 2 , and into the Si layer.4. The integrated circuit device of claim 3 , wherein a portion of the interconnect conductor in the Si layer extends laterally under the SiGe layer and the two of the plurality of fins.5 ...

Uniform Gate Width for Nanostructure Devices

According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack. 1. A semiconductor device comprising:a substrate; a plurality of nanostructures;', 'a gate device surrounding each of the nanostructures;', 'inner spacers along the gate device and between the nanostructures, wherein a width of the inner spacers differs between different layers of the fin stack., 'a fin stack comprising2. The semiconductor device of claim 1 , further comprising gate regions between the plurality of nanostructures claim 1 , the gate regions varying in depth by layer.3. The semiconductor device of claim 2 , wherein variation by layer is within a range of 2-12 nanometers.4. The semiconductor device of claim 1 , wherein the sidewall spacers comprise at least one of: SiCN claim 1 , SiOCN claim 1 , and SiON.5. The semiconductor device of claim 1 , wherein the inner spacers vary by layer within a range of about 4-15 nanometers with respect to a width for each sidewall spacer.6. The semiconductor device of claim 1 , wherein the sidewall spacers comprise at least one of: SiCN claim 1 , SiOCN claim 1 , and SiON.7. The semiconductor device of claim 1 , wherein channel length of each nanostructure is substantially uniform.8. A semiconductor device comprising:a substrate; two source/drain regions;', 'a fin stack having a plurality of channel features extending between the two source/drain regions;', 'a gate feature surrounding the plurality of channel features so as to include a plurality of gate regions between each of the channel features; and', 'sidewall spacers along sidewalls of the gate feature and between the channel features, wherein a width of the sidewall spacers differs between different layers of the fin stack;, 'a ...

Etch profile control of polysilicon structures of semiconductor devices

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second ...

Tuning Tensile Strain on FinFET

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. 1. A semiconductor structure comprising: a first fin;', 'first source/drain regions in the first fin;', 'a first channel region interposed between the first source/drain regions; and', 'a first gate electrode overlying the first channel region; and, 'a first device comprisinga first dielectric layer on opposing sides of the first gate electrode, the first dielectric layer being a contracted dielectric, the first gate electrode having convex sidewalls projecting toward concave sidewalls of the first dielectric layer.2. The semiconductor structure of claim 1 , wherein the first device is a NMOS device.3. The semiconductor structure of claim 1 , further comprising a dielectric spacer interposed between the first gate electrode and the first dielectric layer.4. The semiconductor structure of claim 1 , wherein the dielectric spacer having a convex sidewall projecting toward the concave sidewall of the first dielectric layer.5. The semiconductor structure of claim 1 , further comprising a second device claim 1 , the second device comprising:a second fin;a second gate electrode overlying the second fin; anda second dielectric layer adjacent the second gate electrode, wherein sidewalls of the second dielectric layer and the second gate electrode are linear.6. The semiconductor structure of claim 5 , wherein the second dielectric layer comprises a different material than the first dielectric layer.7. The semiconductor structure of ...

MULTI-GATE DEVICE AND RELATED METHODS

A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region. 1. A method of fabricating a semiconductor device , comprising:providing a dummy structure including a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers, wherein the dummy structure is disposed at an active edge adjacent to an active region;performing a metal gate etching process to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface; andafter performing the metal gate etching process, performing a dry etching process to form a cut region along the active edge, wherein the gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.2. The method of claim 1 , wherein the gate dielectric layer includes both an ...

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK

A semiconductor device structure and the fabrication method are provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The second channel structure is longer than the first channel structure. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a first gate spacer extending along a sidewall of the first gate stack. In addition, the semiconductor device structure includes a second gate stack over the second channel structure and a second gate spacer extending along a sidewall of the second gate stack. The second gate stack has a portion extending along the second gate spacer, and the portion of the second gate stack has a second width. Half of the first width is greater than the second width. 1. A semiconductor device structure , comprising:a first channel structure and a second channel structure over a substrate, wherein the second channel structure is longer than the first channel structure;a first gate stack over the first channel structure, wherein the first gate stack has a first width;a first gate spacer extending along a sidewall of the first gate stack;a second gate stack over the second channel structure; anda second gate spacer extending along a sidewall of the second gate stack, wherein the second gate stack has a portion extending along the second gate spacer, the portion of the second gate stack has a second width, and half of the first width is greater than the second width.2. The semiconductor device structure as claimed in claim 1 , further comprising:a first protective structure over the first gate stack; anda second protective structure over the second gate stack.3. The semiconductor device structure as claimed in claim 2 , wherein a top of the first gate spacer is higher than a top of the first gate stack claim 2 , and a top of the ...

Multigate device with air gap spacer and backside rail contact and method of fabricating thereof

Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES

A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer. 1. A semiconductor device , comprising: a first plurality of channel members,', 'an interfacial layer over the first plurality of channel members,', 'a gate dielectric layer over the interfacial layer,', 'a first work function layer over and in contact with the gate dielectric layer, and', 'a glue layer over the first work function layer;, 'a first gate-all-around (GAA) transistor comprising a second plurality of channel members,', 'the interfacial layer over the second plurality of channel members,', 'the gate dielectric layer over the interfacial layer,', 'a second work function layer over and in contact with the gate dielectric layer,', 'the first work function layer over and in contact with the second work function layer, and', 'the glue layer over the first work function layer; and, 'a second GAA transistor comprising a third plurality of channel members,', 'the interfacial layer over the third plurality of channel members,', 'the gate dielectric layer over the interfacial layer, and', 'the glue layer over the gate dielectric layer., 'a third GAA ...

MULTI-GATE DEVICE AND RELATED METHODS

A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure. 1. A method of fabricating a semiconductor device , comprising:providing a fin including a plurality of semiconductor channel layers and a plurality of multilayer epitaxial layers that interpose the plurality of semiconductor channel layers, wherein each of the plurality of multilayer epitaxial layers includes a first epitaxial layer interposed between a second epitaxial layer and a third epitaxial layer, and wherein the first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate;laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers;forming an inner spacer between adjacent layers of the plurality of semiconductor channel layers, wherein the inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface; andreplacing each of the multilayer epitaxial ...

Spacer Structure For Nano-Sheet-Based Devices

A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has. 1. A semiconductor device , comprising:a semiconductor substrate having a top surface;a first source/drain feature and a second source/drain feature over the semiconductor substrate;a first suspended channel layer over the semiconductor substrate, a second suspended channel layer over the first suspended channel layer, and a third suspended channel layer over the second suspended channel layer, the first, the second, and the third suspended channel layers each extending in parallel to the top surface and each connecting the first and the second source/drain features along a first direction parallel to the top surface;a first gate portion between the first and the second suspended channel layers, and a second gate portion between the second and the third suspended channel layers; anda first inner spacer between the first and the second suspended channel layers and between the first gate portion and the first source/drain feature, and a second inner spacer between the second and the third suspended channel layers and between the second gate portion and the first source/drain ...

Gate Isolation Structure

A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer. 1. A semiconductor device , comprising:a first gate structure and a second gate structure aligned along a direction;a first metal layer disposed over the first gate structure;a second metal layer disposed over the second gate structure; anda gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.2. The semiconductor device of claim 1 , wherein the gate isolation structure comprises a void.3. The semiconductor device of claim 1 ,wherein the gate isolation structure comprises a lower portion disposed between the first gate structure and the second gate structure and an upper portion disposed between the first metal layer and the second metal layer,wherein a width of the lower portion along the direction is greater than a width of the upper portion along the direction.4. The semiconductor device of claim 3 , further comprising:a first self-aligned contact (SAC) dielectric layer over the first metal layer; anda second SAC dielectric layer over the second metal layer,wherein the upper portion is further disposed between the first SAC dielectric layer and the second SAC dielectric layer.5. The semiconductor device of claim 1 ,wherein the first gate structure is disposed between the gate isolation structure and a dielectric fin,wherein the first metal layer extends over the dielectric fin.6. The semiconductor device of claim 5 ,wherein the gate isolation structure is a single layer,wherein the dielectric fin comprises a liner and a ...

Method for manufacturing semiconductor structure

A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.

Semiconductor devices with fin-top hard mask and methods for fabrication thereof

The present disclosure provide a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

Stacked Gate-All-Around FinFET and Method Forming the Same

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics. 1. A device comprising:a first semiconductor strip;a first gate dielectric surrounding the first semiconductor strip;a second semiconductor strip overlapping the first semiconductor strip;a second gate dielectric surrounding the second semiconductor strip, wherein the first gate dielectric contacts the second gate dielectric; anda metal gate electrode partially encircling each of the first semiconductor strip and the second semiconductor strip.2. The device of claim 1 , wherein the first gate dielectric forms a full ring encircling the first semiconductor strip claim 1 , and the second gate dielectric forms a full ring encircling the second semiconductor strip.3. The device of claim 1 , wherein the metal gate electrode comprises a first middle portion overlapped by the second semiconductor strip claim 1 , and the first middle portion further overlaps the first semiconductor strip.4. The device of claim 3 , wherein the first middle portion of the metal gate electrode tapers deeper into a space between the first semiconductor strip and the second semiconductor strip.5. The device of further comprising a second middle portion overlapped by the second semiconductor strip claim 3 , and overlapping the first semiconductor strip claim 3 , wherein the first middle portion and the second middle portion extend toward each other claim 3 , and are spaced apart from teach other by the first gate dielectric and the second gate dielectric.6. The device of claim 1 , ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

SEMICONDUCTOR DEVICE STRUCTURE WITH HARD MASK LAYER OVER FIN STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure. 1. A semiconductor device structure , comprising:a fin structure formed over a substrate;a hard mask layer formed over the fin structure;a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer; anda source/drain (S/D) structure formed adjacent to the gate structure.2. The semiconductor device structure as claimed in claim 1 , wherein the gate structure further comprises:a high-k dielectric layer surrounding the hard mask layer and the fin structure; anda work function layer surrounding the high-k dielectric layer, wherein the hard mask layer and the fin structure are separated by the high-k dielectric layer and the work function layer.3. The semiconductor device structure as claimed in claim 1 , further comprising:a contact etch stop layer (CESL) formed over the S/D structure; andan inter-layer dielectric (ILD) structure formed over the CESL, wherein a sidewall of the hard mask layer is in direct contact with the CESL and the ILD structure.4. The semiconductor device structure as claimed in claim 1 , wherein sidewalls of the hard mask layer are substantially aligned with sidewalls of the fin structure.5. The semiconductor device structure as claimed in claim 1 , further comprising:an inner spacer formed between the gate structure and the S/D structure, wherein the inner spacer is formed along a sidewall of the portion of ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A semiconductor device , comprising:semiconductor wires disposed over a substrate;a source/drain epitaxial layer wrapping around a source/drain region of each of the semiconductor wires;a gate dielectric layer disposed on and wrapping around a channel region of each of the semiconductor wires;a gate electrode layer disposed on the gate dielectric layer; andinsulating spacers each disposed between the gate dielectric layer and the source/drain epitaxial layer,wherein an additional insulating spacer is disposed above an uppermost one of the semiconductor wires.2. The semiconductor device of claim 1 , wherein each of the insulating spacers and the additional insulating spacer includes two layers.3. The semiconductor device of claim 2 , wherein the two layers are a first layer and a second layer formed on the first layer claim 2 , and the first layer has a smaller thickness than the second layer.4. The semiconductor device of claim 2 , wherein the insulating spacers and the additional insulating spacer include at least one of SiOC claim 2 , SiOCN and SiCN.5. The semiconductor device of claim 2 , wherein the first layer of the insulating spacers is in contact ...

Silicon and Silicon Germanium Nanowire Formation

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH MIXED THRESHOLD VOLTAGES BOUNDARY ISOLATION OF MULTIPLE GATES AND STRUCTURES FORMED THEREBY

A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer. 1. A semiconductor device , comprising:a plurality of first semiconductor nanosheets spaced apart from each other and disposed in a p-type device region;a plurality of second semiconductor nanosheets spaced apart from each other and disposed in an n-type device region;an isolation structure formed at a boundary between the p-type and n-type device regions;a gate dielectric layer surrounding each of the first semiconductor nanosheets and each of the second semiconductor nanosheets and on the isolation structure;a p-type work function layer surrounding each of the first semiconductor nanosheets; andan n-type work function layer surrounding each of the second semiconductor nanosheets, over the isolation structure and on the p-type work function layer, wherein the p-type work function layer has an edge located between the first semiconductor nanosheets and the isolation structure.2. The semiconductor device as claimed in claim 1 , wherein there is a first distance between a center line of the first semiconductor nanosheets and the boundary claim 1 , and there is a second distance between the edge of the p-type work function layer and the boundary claim 1 , and the second distance is greater than 0 nm and shorter than or equal to half of the first distance.3. The ...

SEMICONDUCTOR STRUCTURES AND METHODS THEREOF

A method includes providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another; forming an interfacial layer wrapping around each of the semiconductor layers; forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers; and forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers. With the capping layer wrapping around each of the semiconductor layers, the method further includes performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer. After the performing of the thermal treatment, the method further includes removing the capping layer. 1. A method , comprising:providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another;forming an interfacial layer wrapping around each of the semiconductor layers;forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers;forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers;with the capping layer wrapping around each of the semiconductor layers, performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer; andafter the performing of the thermal treatment, removing the capping layer.2. The method of claim 1 , after the removing of the capping layer claim 1 , further comprising:forming a work function metal layer over the high-k dielectric layer and wrapping around each of the semiconductor layers.3. The method of claim 2 , further comprising:forming a bulk metal layer over the work function metal layer.4. The method of claim 1 , wherein the capping layer includes an oxygen-scavenging oxide or an oxygen-scavenging nitride claim 1 , and the thermal treatment ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer. 1. (canceled)2. A semiconductor device structure , comprising:a first gate electrode layer;a second gate electrode layer adjacent the first gate electrode layer;a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature has a first surface;a first conductive layer disposed on the first gate electrode layer, wherein the first conductive layer has a second surface;a second conductive layer disposed on the second gate electrode layer, wherein the second conductive layer has a third surface, wherein the first surface, the second surface, and the third surface are coplanar;a third conductive layer disposed over the first conductive layer;a fourth conductive layer disposed over the second conductive layer;a dielectric layer disposed on the first surface of the dielectric feature, wherein the dielectric layer is disposed between the third conductive layer and the fourth conductive layer;a first plurality of semiconductor layers, wherein ...

SEMICONDUCTOR DEVICE FABRICATION METHODS AND STRUCTURES THEREOF

A method includes providing semiconductor channel layers over a substrate; forming a first dipole layer wrapping around the semiconductor channel layers; forming an interfacial dielectric layer wrapping around the first dipole layer; forming a high-k dielectric layer wrapping around the interfacial dielectric layer; forming a second dipole layer wrapping around the high-k dielectric layer; performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer; removing the second dipole layer; and forming a work function metal layer wrapping around the high-k dielectric layer. 1. A method comprising:providing semiconductor channel layers over a substrate;forming a first dipole layer wrapping around the semiconductor channel layers;forming an interfacial dielectric layer wrapping around the first dipole layer;forming a high-k dielectric layer wrapping around the interfacial dielectric layer;forming a second dipole layer wrapping around the high-k dielectric layer;performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer;removing the second dipole layer; andforming a work function metal layer wrapping around the high-k dielectric layer.2. The method of claim 1 , wherein the first dipole layer includes a p-dipole material and the second dipole layer includes an n-dipole material.3. The method of claim 2 , wherein the first dipole layer includes germanium oxide claim 2 , aluminum oxide claim 2 , gallium oxide claim 2 , or zinc oxide.4. The method of claim 2 , wherein the second dipole layer includes lanthanum oxide claim 2 , yttrium oxide claim 2 , or titanium oxide.5. The method of claim 1 , wherein the work function metal layer is free of aluminum.6. The method of claim 5 , wherein the work function metal layer includes titanium nitride claim 5 , tantalum nitride claim 5 , tungsten carbonitride claim 5 , or titanium silicon nitride.7. A ...

Semiconductor devices with backside power rail and methods of fabrication thereof

Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material. 1. A semiconductor device structure , comprising:a semiconductor fin comprising a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface;a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin;a first source/drain epitaxial feature in contact with the semiconductor fin;a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer, wherein the first inner spacer is in contact with the first source/drain epitaxial feature, and wherein the first inner spacer comprises a first material; anda first spacer in contact with the first inner spacer, wherein the first spacer comprises a second material different from the first material.2. The semiconductor device structure of claim 1 , further comprising:a dielectric material in contact with the second surface of the semiconductor fin;a ...

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF

Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration. 1. A semiconductor device , comprising:a first epitaxial feature, wherein the first epitaxial feature comprises a dopant of a first concentration;a first source/drain feature in contact with the first epitaxial feature, wherein the first source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration;a semiconductor channel in contact with the first source/drain feature and the first epitaxial feature;an inner spacer in contact with the first source/drain feature and the first epitaxial feature; anda gate structure, wherein the gate structure is in contact with the inner spacer and a portion of the first epitaxial feature.2. The semiconductor device of claim 1 , wherein the first epitaxial feature comprises an epitaxially formed silicon layer.3. The semiconductor device of claim 2 , wherein the epitaxial feature is an un-doped epitaxial silicon layer claim 2 , and the first concentration is an intrinsic concentration of the dopant.4. The semiconductor device of claim 2 , wherein the dopant is one of a p-type dopant and n-type dopant.5. The semiconductor device of claim 1 , further comprising:a second epitaxial feature, wherein the first and second epitaxial features are positioned on opposing ends of the semiconductor channel; anda second source/drain ...

Semiconductor Device with Gate Isolation Structure and Method for Forming the Same

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to from a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.

Semiconductor Structures and Methods Thereof

A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Metal Gate Patterning Process and Devices Thereof

A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.

MULTI-GATE DEVICE AND RELATED METHODS

A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers. 1. A method of fabricating a semiconductor device , comprising:providing a first fin in a first device type region and a second fin in a second device type region, wherein each of the first and second fins include a plurality of semiconductor channel layers;performing a two-step recess of a shallow trench isolation (STI) region on opposing sides of each of the first and second fins to expose a first number of semiconductor channel layers of the plurality of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers of the plurality of semiconductor channel layers of the second fin in the second device type region; andforming a first gate structure in the first device type region and a second gate structure in the second device type region, wherein the first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.2. The method of claim 1 , wherein a first step of the two- ...

Input/Output Semiconductor Devices

A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer. 1. A semiconductor device , comprising: a first plurality of channel members,', 'a first interfacial layer over the first plurality of channel members,', 'a first hafnium-containing dielectric layer over the first interfacial layer, and', 'a metal gate electrode layer over the first hafnium-containing dielectric layer; and, 'a first gate-all-around (GAA) transistor comprising a second plurality of channel members,', 'a second interfacial layer over the second plurality of channel members,', 'a second hafnium-containing dielectric layer over the second interfacial layer, and', 'the metal gate electrode layer over the second hafnium-containing dielectric layer,, 'a second GAA transistor comprisingwherein a first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer,wherein a third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing ...

Hybrid Scheme for Improved Performance for P-type and N-type FinFETs

A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed. 1. A device comprising:a bulk semiconductor substrate; a higher portion over and contacting the bulk semiconductor substrate; and', 'a lower portion underlying and joined to the higher portion, wherein the lower portion is laterally recessed from opposing edges of the higher portion;, 'an isolation region comprising a first semiconductor fin protruding higher than the isolation region, wherein a first sidewall of the first semiconductor fin is substantially vertically aligned to a second sidewall of the higher portion of the isolation region;', 'a first gate dielectric overlying a portion of the first semiconductor fin; and', 'a first gate electrode over the first gate dielectric; and, 'an n-type Fin Filed-Effect Transistor (FinFET) comprising a second semiconductor fin protruding higher than the isolation region, wherein a third sidewall of the second semiconductor fin is substantially vertically aligned to a fourth sidewall of the higher portion of the isolation region;', 'a second gate dielectric overlying a portion of the second semiconductor fin, wherein the first gate dielectric and the second gate dielectric are portions of a continuous gate dielectric; and', 'a second gate electrode over the second gate dielectric., 'a p-type FinFET ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a fin protruding from the front surface, the fin including: a first semiconductor layer in proximal to the front surface, a second semiconductor layer stacked over the first semiconductor layer, a gate between the first semiconductor layer and the second semiconductor layer, and a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region laterally surrounding the fin, wherein the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including: a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section, wherein an absolute value of a derivative at the third section is greater than an absolute value of a derivative at the second section. 1. A semiconductor structure , comprising:a substrate having a front surface; a first semiconductor layer in proximal to the front surface;', 'a second semiconductor layer stacked over the first semiconductor layer;', 'a gate between the first semiconductor layer and the second semiconductor layer; and', 'a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate; and, 'a fin protruding from the front surface, the fin comprising a first section proximal to the S/D region;', 'a second section proximal to the gate; and', 'a third section between the first section and the second section,', 'wherein an absolute value of a derivative at the third section is greater than an absolute value of a derivative at the second section., 'a source/drain (S/D) region laterally surrounding the fin, wherein the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface comprising2. The semiconductor structure of claim 1 , wherein an absolute value of a derivative at ...

Devices Including Gate Spacer with Gap or Void and Methods of Forming the Same

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion. 1. A semiconductor device comprising:a void located surrounded by a dielectric material, the dielectric material in physical contact with a semiconductor substrate;a contact located on a first side of the dielectric material, the contact and the dielectric material having a straight interface; anda gate dielectric located on a second side of the dielectric material.2. The semiconductor device of claim 1 , wherein the dielectric material comprises silicon carbon oxynitride.3. The semiconductor device of claim 1 , wherein the dielectric material comprises silicon oxycarbide.4. The semiconductor device of claim 1 , wherein the dielectric material has a substantially same thickness along the straight interface.5. The semiconductor device of claim 1 , wherein a first height of the void is within a range from about 0.3 times and about 0.7 times a second height of the contact and a capping material.6. The semiconductor device of claim 5 , wherein the dielectric material is planar with the capping material.7. The semiconductor device of claim 1 , wherein the dielectric material extends further away from the semiconductor substrate than the gate dielectric claim 1 , and wherein the gate dielectric extends further away from the semiconductor substrate than the void.8. A semiconductor device comprising:a source/drain region adjacent to a lightly doped source/drain region;a gate spacer in physical contact with both the source/drain ...

WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region. 1. An integrated chip , comprising: a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region;', 'a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region;, 'a first transistor arranged over a substrate and having a first conductivity type, wherein the first transistor comprises a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region; and', 'a second channel structure embedded in the second gate electrode layer and extending from the third source/drain region to the fourth source/drain region., 'a second transistor arranged laterally beside the first transistor and having the first conductivity type, wherein the second transistor comprises2. The integrated chip of claim 1 ,wherein the first gate ...

SEMICONDUCTOR STRUCTURE WITH HYBRID NANOSTRUCTURES

Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer. 1. A semiconductor structure , comprising:a substrate;a first fin structure formed over the substrate;an isolation structure formed around the first fin structure;a protection layer formed on the isolation structure;first nanostructures formed over the first fin structure; anda gate structure surrounding the first nanostructures,wherein a bottom surface of the gate structure and a top surface of the isolation structure are separated by the protection layer.2. The semiconductor structure as claimed in claim 1 , wherein the protection layer covers a sidewall of the gate structure.3. The semiconductor structure as claimed in claim 1 , further comprising:second nanostructures formed over a second fin structure over the substrate, wherein the isolation structure is formed around the second fin structure; anda dielectric fin structure formed between the first nanostructures and the second nanostructures,wherein the protection layer extends on opposite sidewalls of the dielectric fin structure.4. The semiconductor structure as claimed in claim 1 , further comprising:a source/drain structure connected to the first nanostructures; anda dielectric fin structure formed on the isolation structure,wherein the dielectric fin structure is separated from the isolation structure and the source/drain structure by the protection layer.5. The semiconductor ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers. 1. A method comprising:forming a fin in a multilayer stack, the fin comprising a substrate and at least one first layer over the substrate;forming a gate electrode over the fin;etching an opening in the fin adjacent the gate electrode;forming a recess along a sidewall of the opening, the recess being formed in the at least one first layer;depositing an spacer material in the recess;forming a bottom spacer at a bottom of the opening, the bottom spacer forming a first interface with the spacer material;forming a source/drain region over the bottom spacer; andforming a dielectric structure through the gate electrode and into the substrate of the fin, a bottom of the dielectric structure being above a bottom of the bottom spacer.2. The method of claim 1 , wherein the spacer material within the recess has a thickness larger than the at least one first layer.3. The method of claim 1 , wherein forming the bottom spacer further comprises the bottom spacer being formed to a height of between about 3 nm and about 30 nm.4. The method of claim 3 , wherein a length of the first interface is between about 3 nm and about 15 nm.5. The method of claim 1 , further comprising forming a cut gate dielectric prior to the forming the dielectric structure.6. The method of ...

Gate Structure and Patterning Method

A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions. 1. A method , comprising:exposing a plurality of channel regions including a p-type channel region and an n-type channel region;forming a gate dielectric layer over the exposed channel regions;forming a work function metal (WFM) structure over the gate dielectric layer, wherein the WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and wherein the p-type WFM portion is thinner than the n-type WFM portion; andforming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.2. The method of claim 1 , wherein the formation of the WFM structure comprises:depositing an n-type WFM layer over the gate dielectric layer; andpatterning the n-type WFM layer to remove a portion of the n-type WFM layer deposited over the p-type channel region.3. The method of claim 2 , wherein the n-type WFM layer is patterned using a wet etch process based on etch selectivity between the n-type WFM layer and the gate dielectric layer.4. The method of claim 3 , wherein the etch selectivity is such that the wet etch process etches the n-type WFM layer at an etch rate that is at least 100 times faster than the gate dielectric layer.5 ...

GATE STRUCTURE AND PATTERNING METHOD

A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer. 1. A semiconductor device , comprising:a semiconductor substrate;a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate dielectric layer disposed over the plurality of channel regions;', 'a work function metal (WFM) structure disposed over the gate dielectric layer, wherein the WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region; and', 'a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer., 'a gate structure comprising2. The semiconductor device of claim 1 , wherein the n-type WFM layer is disposed over and in direct contact with the gate dielectric layer.3. The semiconductor device of claim 2 , wherein the n-type WFM layer has a work function equal to or less than 4.4 eV.4. The semiconductor device of claim 1 , wherein the p-type WFM layer is in direct contact with the gate dielectric layer.5. The semiconductor device of claim 4 , wherein the p-type WFM layer has a work function equal to or greater than 4.8 eV.6. The ...

Backside Power Rail Structure and Methods of Forming Same

Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail. 1. A method of forming a semiconductor device , the method comprising:depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a first sacrificial layer over the semiconductor substrate, a first channel layer over the first sacrificial layer, a second sacrificial layer over the first channel layer, and a second channel layer over the second sacrificial layer;etching the first sacrificial layer using a first etch process to form a first recess;forming a first dielectric layer in the first recess, wherein the first dielectric layer has a trapezoid shape;forming a source/drain region that extends through the first dielectric layer;etching the second sacrificial layer using a second etch process to form a second recess;forming a gate stack over the first channel layer, over the second channel layer, and in the second recess;thinning a backside of the semiconductor substrate to expose surfaces of the first dielectric layer and the source/drain region; andforming a backside power rail electrically connected to the source/drain region, wherein the first dielectric layer is disposed between the backside power rail and the first channel layer.2. The method of claim 1 , wherein the first sacrificial layer has a first germanium concentration that is lower than a ...

Semiconductor Device and Method

A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material. 1. A semiconductor device comprising:a semiconductor substrate;a first nanostructure over the semiconductor substrate;a first gate stack over the semiconductor substrate and surrounding the first nanostructure;a first epitaxial source/drain region adjacent the first gate stack and the first nanostructure;a first inner spacer layer between the first gate stack and the first epitaxial source/drain region in a first direction parallel to a major surface of the semiconductor substrate, the first inner spacer layer comprising a first material, wherein the first inner spacer layer has a first thickness in the first direction;a second nanostructure over the semiconductor substrate;a second gate stack over the semiconductor substrate and surrounding the second nanostructure;a second epitaxial source/drain region adjacent the second gate stack and the second nanostructure; anda second inner spacer layer between the second gate stack and the second epitaxial source/drain region in the first direction, the second inner spacer layer comprising a ...

Devices Including Gate Spacer with Gap or Void and Methods of Forming the Same

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion. 1. A method of manufacturing a semiconductor device , the method comprising:forming a dummy gate stack over a semiconductor fin;forming a first spacer adjacent to the dummy gate stack;forming a second spacer adjacent to the first spacer;forming a third spacer adjacent to the second spacer;forming a conductive contact in physical contact with the third spacer;replacing the dummy gate stack with a gate stack;removing the second spacer to form a void between the first spacer and the third spacer; andcapping the void.2. The method of claim 1 , wherein the second spacer comprises aluminum oxide.3. The method of claim 2 , wherein the first spacer comprises silicon nitride.4. The method of claim 1 , wherein the capping the void comprises depositing a dielectric material at least partially into the void.5. The method of claim 4 , wherein the dielectric material comprises silicon carbon oxynitride.6. The method of claim 1 , wherein after the capping the void the void has a height that is between about 0.3 times to about 0.7 times a height of the first spacer over the semiconductor fin.7. The method of claim 1 , wherein the second spacer has a width between about 2 nm and about 4 nm.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a tri-layer spacer over a semiconductor fin and adjacent to a dummy gate stack;replacing the dummy gate stack with a conductive gate;forming a conductive ...

MULTI-GATE DEVICE AND RELATED METHODS

A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer. 1. A method of fabricating a semiconductor device , comprising:forming a first dielectric-filled trench within a first part of a dummy gate, wherein the first dielectric-filled trench covers a first part of a first hybrid fin;forming a metal-filled trench within a second part of the dummy gate; andetching-back a metal layer within the metal-filled trench, wherein a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the first hybrid fin after the etching-back the metal layer.2. The method of claim 1 , wherein the first dielectric-filled trench covers a second hybrid fin adjacent to the first hybrid fin.3. The method of claim 1 , further comprising:prior to forming the first dielectric-filled trench within the first part of the dummy gate, forming a second dielectric-filled trench within a third part of the dummy gate, wherein the second dielectric-filled trench covers a second part of the first hybrid fin, and wherein the third part of the dummy gate interposes the first part of the dummy gate and the second part of the dummy gate.4. The method of claim 3 , further ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer. 1. A semiconductor device structure , comprising:a fin structure formed over a substrate; a first layer; and', 'a fill layer over the first layer; and, 'a gate structure formed over the fin structure, wherein the gate structure comprisesa protection layer formed over the fill layer of the gate structure, wherein the protection layer is separated from the first layer by the fill layer, and a first width of a bottom surface of the protection layer is greater than or equal to a second width of a top surface of the fill layer.2. The semiconductor device structure as claimed in claim 1 , wherein the fin structure comprises a plurality of nanostructures.3. The semiconductor device structure as claimed in claim 1 , wherein the protection layer is not in direct contact with the first layer.4. The semiconductor device structure as claimed in claim 1 , further comprising:a second layer formed over the first layer, wherein the fill layer is formed over the first layer and the second layer.5. The semiconductor device structure as claimed in claim 4 , wherein the fill layer is separated from the first layer by the second layer.6. The semiconductor device structure as claimed in claim 4 , wherein a top surface of the second layer is in direct contact with a bottom surface of the protection layer.7. The semiconductor device structure as claimed in claim 4 , wherein the fill layer is surrounded by the second layer and the protection layer.8. The semiconductor device structure as claimed in claim 1 , further comprising:an insulating layer formed over ...

Stacked Gate-All-Around FinFET and Method Forming the Same

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics. 1. A method comprising:forming a first semiconductor strip and a second semiconductor strip separated from each other;forming a gate stack;epitaxially growing a first source/drain region and a second source/drain region from the first semiconductor strip and the second semiconductor strip, respectively, wherein the first source/drain region and the second source/drain region merge with each other, and wherein the first source/drain region and the second source/drain region are formed on a side of the gate stack;performing an etching process to separate the first source/drain region and the second source/drain region from each other;forming a first silicide layer and a second silicide layer on the first source/drain region and the second source/drain region, respectively; andforming a contact plug on both of the first silicide layer and the second silicide layer.2. The method of claim 1 , wherein before the etching process claim 1 , the first source/drain region and the second source/drain region comprise:faceted upper portions; andstraight lower portions having straight sidewalls.3. The method of claim 2 , wherein before the etching process claim 2 , dielectric layers are in contact with the straight sidewalls of the straight lower portions.4. The method of further comprising claim 3 , after the etching process claim 3 , removing the dielectric layers.5. The method of further comprising forming an etch stop layer wherein the etch stop layer comprises ...

Formation method of semiconductor device with isolation structure

A method for forming a semiconductor device structure is provided. The method includes forming first nanostructures and second nanostructures over a semiconductor substrate. The method also includes forming a dielectric fin between the first nanostructures and the second nanostructures. The method further includes forming a metal gate stack wrapped around the first nanostructures, the second nanostructures, and the dielectric fin. In addition, the method includes forming an insulating structure penetrating into the metal gate stack and aligned with the dielectric fin.

SEMICONDUCTOR STRUCTURE WITH HYBRID NANOSTRUCTURES AND METHOD FOR FORMING THE SAME

Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap. 1. A method for manufacturing a semiconductor structure , comprising:forming a first fin structure comprising first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate;forming an isolation structure surrounding the first fin structure;forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure;etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure; andforming a protection layer covering a sidewall of the first capping layer and filling in the first gap.2. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:removing the first capping layer and the first semiconductor material layers of the first fin structure;thinning the second semiconductor material layers after the first semiconductor material layers and the first capping layer are removed;forming a third semiconductor material layer surrounding the second semiconductor material layers; andforming a gate structure ...

INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width. 1. A method for forming a semiconductor structure , the method comprising:forming a stack of semiconductor layers over a semiconductor substrate, wherein the stack of semiconductor layers comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers;forming a first stack of masking layers over the stack of semiconductor layers with a first width and a second stack of masking layers laterally offset from the stack of semiconductor layers with a second width less than the first width; andperforming a patterning process on the semiconductor substrate and the stack of semiconductor layers according to the first and second stacks of masking layers, thereby defining a first fin structure laterally adjacent to a second fin structure, wherein the first fin structure has the first width and the second fin structure has the second width, and wherein the stack of semiconductor layers directly overlies the first fin structure and has the first width.2. The method of claim 1 , wherein forming the first stack of masking ...

Semiconductor Device With Gate Isolation Features And Fabrication Method Of The Same

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece that includes a substrate, first channel members and second channel members over the substrate, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin. The method also includes forming a metal cap layer at the frontside of the workpiece and depositing a dielectric feature on the dielectric fin. The dielectric feature dividing the metal cap layer into a first segment and a second segment. The method also includes etching the isolation feature to form a trench at the backside of the substrate, depositing a spacer on sidewalls of the trench, etching the dielectric fin from the trench, and depositing a seal layer in the trench. 1. A method , comprising:providing a workpiece including a frontside and a backside, the workpiece including a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, a first gate structure engaging the first plurality of channel members, a second gate structure engaging the second plurality of channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin and sandwiched between the first and second portions of the substrate, wherein the substrate is at the backside of the workpiece and the first and second pluralities of channel members are at the frontside of the workpiece;forming a metal cap layer at the frontside of the workpiece, the metal cap layer electrically connecting the first and second gate structures;depositing a dielectric feature on the dielectric fin, the dielectric feature dividing the metal cap layer into a first ...

Structure and formation method of semiconductor device with hybrid fins

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Semiconductor Device with Backside Self-Aligned Power Rail and Methods of Forming the Same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature. 1. A semiconductor device comprising:a dielectric layer formed over a conductive feature;a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other;a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; anda first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.2. The semiconductor device of claim 1 , further comprising a power rail formed below the conductive feature claim 1 , wherein the power rail electrically contacts the first epitaxial feature via the conductive feature.3. The semiconductor device of claim 1 , further comprising a second epitaxial feature disposed over a second ...

METHOD FOR FORMING SIDEWALL SPACERS AND SEMICONDUCTOR DEVICES FABRICATED THEREOF

Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers. 1. A semiconductor device , comprising:a source/drain feature;first and second channel layers in contact with the source/drain feature; anda sidewall spacer in contact with the source/drain feature, wherein the sidewall spacer includes a first fin sidewall spacer portion, a second fin sidewall spacer portion, and a gate sidewall spacer portion connecting the first and second fin sidewall spacer portions, the first fin sidewall spacer portion contacts first sidewalls of the first and second channel layers, and the second sidewall fin portion contacts second sidewalls of the first and second channel layers.2. The semiconductor device of claim 1 , further comprising:an inner spacer in contact with the sidewall spacer.3. The semiconductor device of claim 2 , wherein the inner spacer includes a top surface claim 2 , a bottom surface opposing the top surface claim 2 , and first and second sidewalls connecting the top surface and the bottom surface claim 2 , the top surface is in contact with the first channel layer claim 2 , the bottom surface is in contact with the second channel layer claim 2 , the first sidewall is in contact with the first fin sidewall spacer portion claim 2 , and the second sidewall is in contact with the second fin sidewall spacer portion.4. The semiconductor device of claim 2 , wherein the inner spacer and the sidewall spacer include the same material.5. The semiconductor device of claim 2 , wherein the inner spacer and the sidewall spacer include different materials.6. The ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height. 1. A semiconductor device structure , comprising:a plurality of semiconductor layers;a first source/drain epitaxial feature in contact with the plurality of semiconductor layers, wherein the first source/drain epitaxial feature comprises a bottom portion having substantially straight sidewalls;a spacer comprising a gate spacer portion and one or more source/drain spacer portions, wherein each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature; anda dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portions, wherein the dielectric feature has a second height substantially greater than the first height.2. The semiconductor device structure of claim 1 , further comprising a gate electrode layer surrounding at least a portion of each of the plurality of semiconductor layers.3. The semiconductor device structure ...

Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Semiconductor devices with backside power rail and backside self-aligned via

A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap. 1. A semiconductor device structure , comprising:a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall;a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction;a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer; anda first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.2. The semiconductor device structure of claim 1 , further comprising:a second semiconductor layer disposed adjacent the second sidewall of the first dielectric feature, the second semiconductor layer extending along the second direction.3. The semiconductor device structure of claim 2 , further comprising:a high-K dielectric layer disposed on the second dielectric feature and surrounding at least three surfaces of the first ...

Hybrid Scheme for Improved Performance for P-type and N-type FinFETs

A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed. 1. A device comprising:a first semiconductor strip having a first top surface orientation; and a lower portion having the first top surface orientation; and', 'an upper portion over the lower portion, wherein the upper portion has a second top surface orientation different from the first top surface orientation., 'a first source/drain region overlapping the first semiconductor strip, wherein the first source/drain region comprises2. The device of claim 1 , wherein the lower portion and the upper portion are formed of a same semiconductor material claim 1 , and have a same composition.3. The device of claim 1 , wherein the first top surface orientation is (100) claim 1 , and the second top surface orientation is (110) or (100) R45.4. The device of claim 1 , wherein the upper portion comprises:an inner portion; andan outer portion forming a ring encircling the inner portion, wherein the inner portion and the outer portion comprise different semiconductor materials.5. The device of further comprising a void between the lower portion and the upper portion.6. The device of claim 1 , wherein the lower portion and the upper portion are in contact with each other.7. The device of further comprising an isolation region contacting a sidewall of the first ...

SELF-ALIGNED STRUCTURE FOR SEMICONDUCTOR DEVICES

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins. 1. A method of forming a semiconductor structure , the method comprising:forming first and second fins protruding from a top surface of a substrate;forming a spacing layer over the substrate and on opposing sidewalls of the first and second fins, wherein the spacing layer forms an opening between the opposing sidewalls of the first and second fins;forming an isolation fin structure in the opening, wherein a bottom surface of the isolation fin structure is above the top surface of the substrate;etching back the spacing layer such that the isolation fin structure and the first and second fins are protruding from the spacing layer;forming a gate structure over the isolation fin structure and the first and second fins; andforming a gate isolation structure in the gate structure, wherein the gate isolation structure is formed over the isolation fin structure.2. The method of claim 1 , further comprising growing first and second epitaxial source/drain structures on the first and second fins claim 1 , respectively.3. The method of claim 2 , further comprising forming a metal contact on the first and second epitaxial source/drain structures and on the isolation fin structure.4. The method of claim 3 , further comprising forming a contact etch stop layer between the metal contact ...

DUAL CRYSTAL ORIENTATION FOR SEMICONDUCTOR DEVICES

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures. 1. A method of fabricating a semiconductor device , comprising:forming a spacer on sidewalls of a device layer and a dielectric layer;forming a silicon germanium (SiGe) epitaxy layer comprising a slanted sidewall and a vertical sidewall, and wherein the vertical sidewall is in contact with the spacer;depositing a polysilicon structure on the slanted sidewall and between the device layer and the SiGe epitaxy layer;etching the device layer and the dielectric layer to form a first fin structure comprising a portion of the device layer with a first top surface crystal orientation;removing the polysilicon structure; andetching the SiGe epitaxy layer to form a second fin structure comprising a portion of the SiGe epitaxy layer, wherein the second fin structure comprises a second top surface crystal orientation different from the first top surface crystal orientation.2. The method of claim 1 , wherein forming the SiGe epitaxy layer comprises depositing a SiGe material and etching the SiGe material.3. The method of claim 1 , further comprising depositing a silicon nitride layer on the polysilicon structure.4. The method of claim 3 , ...

NANOSTRUCTURE WITH VARIOUS WIDTHS

A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features. 1. A semiconductor structure , comprising:first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other, wherein the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers;first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively,wherein the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/ ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer. 1. A method for forming a semiconductor device structure , comprising:forming first and second fins from a substrate;forming a dielectric feature between the first and second fins;forming a first source region and a first drain region from first fin;forming a second source region and a second drain region from the second fin;forming a gate electrode layer between the first source region and the first drain region and between the second source region and the second drain region;recessing the gate electrode layer to a level below a top surface of the dielectric feature; andselectively forming a first conductive layer on the gate electrode layer, wherein the dielectric feature separates the first conductive layer into two segments.2. The method of claim 1 , wherein a top surface of the first conductive layer is substantially coplanar with a top surface of the dielectric feature.3. The method of claim 1 , further comprising forming a dielectric layer on the dielectric feature.4. The method of claim 3 , ...

Devices Including Gate Spacer with Gap or Void and Methods of Forming the Same

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion. 1. A semiconductor device , comprising:a gate electrode on a substrate;a plurality of spacers on side surfaces of the gate electrode; anda first insulating layer and a second insulating layer on an external side surface of the plurality of spacers,wherein the plurality of spacers comprises a first spacer on each of the side surfaces of the gate electrode, an air-gap spacer on an external side surface of the first spacer, and a second spacer on an external side surface of the air-gap spacer,wherein the air-gap spacer is an empty spacer surrounded by the first and second spacers and the substrate, andwherein the first insulating layer and the second insulating layer have different properties.2. The semiconductor device of claim 1 , wherein an upper surface of the plurality of spacers claim 1 , an upper surface of a gate capping layer claim 1 , and an upper surface of the second insulating layer are substantially coplanar with one another3. The semiconductor device of claim 1 , wherein the second spacer has a first height and the air-gap spacer has a second height claim 1 , the second height being in a range from about 0.3 times the first height to about 0.7 times the first height.4. The semiconductor device of claim 1 , wherein the plurality of spacers further comprises an air-gap cap.5. The semiconductor device of claim 4 , wherein the air-gap cap comprises silicon carbon oxynitride (SiCON).6. The semiconductor device of ...

FINFET DEVICES WITH BACKSIDE POWER RAIL AND BACKSIDE SELF-ALIGNED VIA

A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail. 1. A semiconductor structure , comprising:a power rail on a back side of the semiconductor structure;a first interconnect structure on a front side of the semiconductor structure;a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure, wherein the first semiconductor fin connects the source feature and the drain feature, and the gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin;an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin; anda via penetrating through the isolation structure and connecting the source feature to the power rail.2. The semiconductor structure of claim 1 , further comprising:a silicon layer between the drain feature and the isolation structure.3. The semiconductor structure of claim 1 , further comprising a second semiconductor fin that is aligned with the first semiconductor fin along a lengthwise direction of the first semiconductor fin claim 1 , wherein the source feature directly interfaces with the first and the second ...

FinFET Device With High-K Metal Gate Stack

Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin. 1. A device comprising:a fin structure having a first fin portion having a first width extending from a substrate, a second fin portion having a second width disposed over the first fin portion, and a third fin portion having a third width disposed over the second fin portion, wherein the second width is greater than the first width and the third width; andan isolation feature disposed over the substrate, wherein the isolation feature physically contacts first sidewalls of the first fin portion, second sidewalls of the second fin portion, and third sidewalls of the third fin portion.2. The device of claim 1 , wherein the isolation feature physically contacts a top surface of the second fin portion.3. The device of claim 1 , wherein the isolation feature physically contacts a bottom portion of the third sidewalls of the third fin portion and the isolation feature does not physically contact an upper portion of the third sidewalls of the third fin portion.4. The device of claim 1 , wherein the isolation feature physically contacts a top surface of the ...

Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof

A semiconductor structure includes a first fin, which includes a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section, and a second fin, which includes a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section, wherein a shape or an area of the first cross section is different from that of the second cross section. 1. A semiconductor structure , comprising:a substrate;a first fin disposed on the substrate and extending lengthwise in a first direction, the first fin including a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section perpendicular to the first direction; anda second fin disposed on the substrate and extending lengthwise in the first direction, the second fin including a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section perpendicular to the first direction,wherein a shape or an area of the first cross section is different from that of the second cross section.2. The semiconductor structure of claim 1 , wherein an area of the first cross section is larger than that of the second cross section.3. The semiconductor structure of claim 2 , wherein a ratio between the area of the first cross section and that of the second cross section ...

Epitaxial Features Confined by Dielectric Fins and Spacers

A semiconductor device includes a substrate, a dielectric isolation structure disposed on the substrate, a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure, first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin, a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins, and an epitaxial feature over the semiconductor fin. The epitaxial feature has a bottom portion laterally between the first and second dielectric fins. 1. A semiconductor device , comprising:a substrate;a dielectric isolation structure disposed on the substrate;a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure;first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin;a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins; andan epitaxial feature over the semiconductor fin, wherein the epitaxial feature has a bottom portion laterally between the first and second dielectric fins.2. The semiconductor device of claim 1 , wherein the dielectric block interfaces with the semiconductor fin.3. The semiconductor device of claim 1 , further comprising:a gate stack disposed on the semiconductor fin; anda spacer layer over sidewalls of the gate stack, wherein the spacer layer is laterally between the semiconductor fin and each of the first and second dielectric fins.4. The semiconductor device of claim 3 , further comprising:an oxide layer disposed on the dielectric isolation structure, wherein the oxide layer is laterally between the spacer layer and each of the first and second dielectric fins.5. The semiconductor device of claim 1 , wherein the epitaxial feature has a top portion above the first and second dielectric fins.6. The semiconductor device of claim 5 , wherein the top portion of the ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer. 115-. (canceled)16. A method for forming a semiconductor structure , comprising:alternatingly stacking first semiconductor layers and second semiconductor layers over a substrate;patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure in a first region of the substrate and a second fin structure in a second region of the substrate;forming a dielectric fin structure between the first fin structure and the second fin structure;etching the first fin structure to form a first source/drain recess and etching the second fin structure to form a second source/drain recess;forming a mask element over the second region of the substrate;forming a first source/drain feature in the first source/drain recess, wherein the first source/drain feature is interfaced with the dielectric fin structure;forming a silicon germanium layer over the first source/drain feature;oxidizing the silicon germanium layer;removing the mask element; andforming a second source/drain feature in the second source/drain recess, wherein the second source/drain feature is interfaced with the dielectric fin structure.17. The method for forming the semiconductor structure as claimed in claim 16 , further comprising claim 16 , after forming the first source/drain recess and the second source/drain recess:laterally recessing the first semiconductor layers of the first fin structure to form first notches and laterally recessing the first semiconductor layers of the ...

ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region. 1. A semiconductor structure , comprising:a substrate;a first vertical structure and a second vertical structure formed over the substrate; andan isolation structure between the first and second vertical structures, wherein the isolation structure comprises a center region and footing regions formed on opposite sides of the center region, each of the footing regions tapered towards the center region from a first end of the each footing region to a second end of the each footing region.2. The semiconductor structure of claim 1 , wherein a bottom surface of each of the footing regions is substantially coplanar with a top surface of each of the first and the second vertical structures.3. The semiconductor structure of claim 1 , wherein the footing regions comprise a first footing region and a second footing region opposite to the first footing region claim 1 , wherein a separation between the first end of the first footing region and the first end of the second footing region is less than an other separation between the second end of the first footing region and the second end of the second footing region.4. The semiconductor structure of claim 1 , wherein a top surface of the central region is higher than an other top surface of each of the first and the second vertical structures.5. The semiconductor structure of claim 1 , wherein the central region comprises sidewalls substantially ...

ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively. 1. A method , comprising:doping a fin structure;depositing an oxide layer on a top surface and sidewalls of the fin structure;oxidizing the fin structure through the top surface at a first oxidation rate to form a first oxide region; andoxidizing the fin structure through the sidewalls at a second oxidation rate to form a second oxide region, wherein the second oxidation rate is less than the first oxidation rate.2. The method of claim 1 , wherein doping the fin structure comprises:forming an amorphous region on the fin structure, the amorphous region comprising an amorphous material; anddoping the amorphous region.3. The method of claim 2 , wherein forming the amorphous region comprises:depositing a layer of insulating material on the fin structure;forming a recessed region within the layer of insulating material and on the fin structure;depositing a layer of the amorphous material on the layer of ...

Multi-Gate Device and Method of Fabrication Thereof

A method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin. 1. A method , comprising:forming a semiconductor fin extruding from a substrate;forming a sacrificial capping layer on sidewalls of the semiconductor fin;forming first and second dielectric fins sandwiching the semiconductor fin;forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins;forming gate spacers on sidewalls of the sacrificial gate stack;removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins;removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; andforming a metal gate stack in the gate trench engaging the semiconductor fin.2. The method of claim 1 , wherein the sacrificial capping layer includes amorphous or polycrystalline semiconductor material.3. The method of claim 2 , wherein the semiconductor material is silicon germanium.4. The method of claim 1 , wherein the forming of the sacrificial capping layer includes:depositing an amorphous silicon layer covering the semiconductor fin;forming an ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;removing first semiconductor layers from a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space, wherein the second semiconductor layers remain in the source/drain space;laterally etching the first semiconductor layers through the source/drain space;forming a first inner spacer made of an oxide material on an end of each of the etched first semiconductor layers by oxidation process;forming a second inner spacer made of a dielectric material over the first inner spacer;forming a source/drain epitaxial layer in the source/drain space and to cover the second inner spacer; andforming a source/drain contact layer in contact with the source/drain epitaxial layer that wraps around the second semiconductor layers.2. The method of claim 1 , wherein an end of the inner spacer facing the end of each of the etched first semiconductor layers has a round ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure. 1. A semiconductor device , comprising:a semiconductor substrate having a fin structure;a gate stack across the fin structure;a spacer structure on a sidewall of the gate stack;an epitaxial structure on the semiconductor substrate; anda dielectric structure in the spacer structure and extending along a lower portion of the spacer structure and across the fin structure.2. The semiconductor device according to claim 1 , wherein the dielectric structure is between the gate stack and the epitaxial structure.3. The semiconductor device according to claim 1 , wherein the dielectric structure is in contact with the epitaxial structure.4. The semiconductor device according to claim 1 , wherein the spacer structure comprises a first spacer layer claim 1 , a second spacer layer claim 1 , and a third spacer layer claim 1 , and the second spacer layer is between the first spacer layer and the third spacer layer claim 1 , and the second spacer layer has a lower dielectric constant than the first spacer layer and the third spacer layer.5. The semiconductor device according to claim 4 , wherein the second spacer layer is spaced apart from the epitaxial structure.6. The semiconductor device according to claim 4 , wherein the third spacer layer has a sidewall substantially aligned with a sidewall of the dielectric structure.7. The semiconductor device according to claim 1 , further comprising an etch stop layer and an interlayer dielectric over the epitaxial structure claim 1 , wherein the etch stop layer is between the dielectric structure and the interlayer dielectric.8. A semiconductor device claim ...

Transistors with Different Threshold Voltages

A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer. 18-. (canceled)9. A method comprising:providing a workpiece comprising a substrate, first vertically stacked channel members in a first area of the substrate, second vertically stacked channel members in a second area of the substrate, and third vertically stacked channel members in a third area of the substrate;depositing a gate dielectric layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;depositing a sacrificial layer over the gate dielectric layer;etching the sacrificial layer such that a portion of the sacrificial layer remains disposed between adjacent ones of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;selectively removing all of the sacrificial layer in the second area;depositing a first work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel ...

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE

A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack. The semiconductor device structure also includes an insulating structure penetrating through a bottom surface of the dielectric protection structure and extending into the metal gate stack to be aligned with the dielectric fin. 1. A semiconductor device structure , comprising:a first fin structure over a semiconductor substrate, wherein the first fin structure has a plurality of first semiconductor nanostructures suspended over the semiconductor substrate;a second fin structure over the semiconductor substrate, wherein the second fin structure has a plurality of second semiconductor nanostructures suspended over the semiconductor substrate;a dielectric fin between the first fin structure and the second fin structure;a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin;a dielectric protection structure over the metal gate stack; andan insulating structure penetrating through a bottom surface of the dielectric protection structure and extending into the metal gate stack to be aligned with the dielectric fin.2. The semiconductor device structure as claimed in claim 1 , wherein the ...

Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions. 1. A method , comprising: a semiconductor fin structure;', 'source/drain regions disposed on opposite sides of the semiconductor fin structure;', 'a gate structure disposed over the semiconductor fin structure;', 'gate spacers disposed on sidewalls of the gate structure; and, 'providing a semiconductor device that includesetching the semiconductor device, wherein the gate structure is etched at a faster rate than the gate spacers during the etching; andafter the etching, forming a liner over the gate structure and the gate spacers.2. The method of claim 1 , wherein:the semiconductor device further includes an interlayer dielectric (ILD) structure disposed on sidewalls of the gate spacers; andthe gate spacers are etched at a faster etching rate than the ILD structure during the etching.3. The method of claim 2 , wherein the forming the liner further comprises forming the liner over the ILD structure.4. The method of claim 1 , wherein the forming the liner comprises forming a liner that contains a dielectric material having a dielectric constant greater than about 4.5. The method of claim 1 , wherein the forming the liner comprises forming a liner having a thickness in a range between about 0.5 nanometers and about 5 nanometers.6. The method of claim 1 , further comprising: after the etching but before the forming the liner claim 1 , re-forming a portion of the gate structure.7. The method of claim 6 , wherein:the gate structure includes a work function (WF) metal layer;the etching partially etches away the WF metal layer; andthe re-forming the portion of the gate structure comprises depositing a first metal ...

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, forming a dielectric fin structure laterally spaced apart from the semiconductor fin structure, forming a source/drain spacer between the semiconductor fin structure and the dielectric fin structure, etching an upper portion of the semiconductor fin structure to expose a lower portion of the semiconductor fin structure, and forming a source/drain feature over the lower portion of the semiconductor fin structure. The source/drain spacer is interposed between the source/drain feature and the dielectric fin structure. 1. A method for forming a semiconductor device structure , comprising:forming a semiconductor fin structure over a substrate;forming a dielectric fin structure laterally spaced apart from the semiconductor fin structure;forming a source/drain spacer between the semiconductor fin structure and the dielectric fin structure;etching an upper portion of the semiconductor fin structure to expose a lower portion of the semiconductor fin structure; andforming a source/drain feature over the lower portion of the semiconductor fin structure, wherein the source/drain spacer is interposed between the source/drain feature and the dielectric fin structure.2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the dielectric fin structure is made of a first dielectric material with a dielectric constant less than about 7 claim 1 , and the source/drain spacer is made of a second dielectric material with a dielectric constant greater than about 7.3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:forming an isolation structure between the semiconductor fin structure and the dielectric fin structure, wherein the source/drain spacer is formed over the isolation structure.4. The method for forming the semiconductor device structure as claimed in ...

Semiconductor Liner of Semiconductor Device

The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant. 1. A device comprising:a semiconductor substrate;a fin extending from the semiconductor substrate, the fin comprising a first material having a first lattice constant;a semiconductor liner contacting outermost sidewalls of a portion of the fin, the semiconductor liner having a second lattice constant different than the first lattice constant; andan oxide of the semiconductor liner forming a notch extending inward from a sidewall of the fin.2. The device of claim 1 , wherein the first material is silicon and the semiconductor liner is selected from the group consisting of SiGe and SiGeB.3. The device of claim 1 , wherein the oxide of the first material comprises SiGeOx or SiGeBOy.4. The device of claim 1 , further comprising a second fin extending from the semiconductor substrate claim 1 , and further wherein the semiconductor liner extends from an outermost sidewall of the fin to an outermost sidewall of the second fin.5. The device of claim 1 , wherein the notch narrows a current path in the fin.6. The device of claim 1 , further comprising a gate dielectric in contact with the notch.7. The device of claim 1 , wherein:the semiconductor liner has a first thickness along the outermost sidewalls of the portion of the fin;the notch has a second thickness; andthe second thickness is greater than the first thickness. ...

SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND BACKSIDE SELF-ALIGNED VIA

A semiconductor structure includes a source feature, a drain feature, one or more channel layers connecting the source feature and the drain feature, and a gate structure between the source feature and the drain feature. The gate structure engages each of the one or more channel layers. The semiconductor structure further includes a first source silicide feature over the source feature, a source contact over the first source silicide feature, a second source silicide feature under the source feature, a via under the second source silicide feature, and a power rail under the via. The first and the second source silicide features fully surround the source feature in a cross-sectional view. The power rail is a backside power rail. 1. A semiconductor structure , comprising:a source feature;a drain feature;one or more channel layers connecting the source feature and the drain feature;a gate structure between the source feature and the drain feature, the gate structure engaging each of the one or more channel layers;a first source silicide feature over the source feature;a source contact over the first source silicide feature;a second source silicide feature under the source feature;a via under the second source silicide feature; anda power rail under the via, wherein the first and the second source silicide features fully surround the source feature in a cross-sectional view.2. The semiconductor structure of claim 1 , further comprising:a drain silicide feature over the drain feature;a drain contact over the drain silicide feature;a first dielectric feature under the drain feature and extending from the drain feature to the power rail;a first dielectric layer on a sidewall of the drain feature; andan air gap that exposes multiple sides of the first dielectric layer.3. The semiconductor structure of claim 1 , wherein the second source silicide feature is also disposed on a sidewall of the source feature and connects with the first source silicide feature.4. The ...

P-Metal Gate First Gate Replacement Process for Multigate Devices

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region. 1. A method comprising:forming a gate dielectric layer in a gate trench in a gate structure, wherein the gate dielectric layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region;forming sacrificial features between the second channel layers in the n-type gate region;forming a p-type work function layer in the gate trench over the gate dielectric layer in the p-type gate region and the n-type gate region;removing the p-type work function layer from the gate trench in the n-type gate region;after removing the p-type work function layer, removing the sacrificial features between the second channel layers in the n-type gate region;forming an n-type work function layer in the gate trench over the gate dielectric layer in the n-type gate region, wherein the n-type work function layer surrounds the gate dielectric layer and the second channel layers in the n-type gate region; andforming a metal fill layer in the gate trench over the p-type work function layer in the p-type gate region and the n-type work function layer in the n- ...

Self-Aligned Source/Drain Metal Contacts And Formation Thereof

The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.

Gate Isolation for Multigate Device

Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

GATE-ALL-AROUND DEVICES HAVING SELF-ALIGNED CAPPING BETWEEN CHANNEL AND BACKSIDE POWER RAIL

A semiconductor device includes a first interconnect structure; multiple channel layers stacked over the first interconnect structure; a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature between the bottommost one of the channel layers and the first conductive via. 1. A semiconductor device , comprising:a first interconnect structure;multiple channel layers stacked over the first interconnect structure;a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers;a source/drain feature adjoining the channel layers;a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; anda dielectric feature between the bottommost one of the channel layers and the first conductive via.2. The semiconductor device of claim 1 , wherein the dielectric feature includes one or more high-k dielectric materials.3. The semiconductor device of claim 2 , wherein the dielectric feature further includes a low-k dielectric material surrounded by the one or more high-k dielectric materials.4. The semiconductor device of claim 2 , wherein the dielectric feature further includes a semiconductor oxide layer between the one or more high-k dielectric materials and the first conductive via.5. The semiconductor device of claim 1 , further comprising:a semiconductor fin structure directly below the channel layers and the source/drain feature, wherein the first conductive via is embedded in the semiconductor fin structure.6. The semiconductor device of claim 1 , further comprising:a dielectric fin structure directly below the channel layers and the source/drain feature, wherein the first conductive via is embedded in the dielectric fin structure.7. The semiconductor device of claim ...

FINFET DEVICES AND METHODS OF FORMING

In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region. 1. A device comprising:a substrate having a first region and a second region;a dielectric layer on the first region of the substrate;a first fin on the dielectric layer, the dielectric layer separating the first fin from the substrate;a second fin extending from the second region of the substrate, the second fin and the substrate being a continuous semiconductor material;a first gate stack on a first channel region of the first fin;a second gate stack on a second channel region of the second fin, the first channel region and the second channel region having the same type of first majority carriers;a first source/drain region in the first fin and adjacent the first channel region; anda second source/drain region in the second fin and adjacent the second channel region.2. The device of claim 1 , wherein the first majority carriers are holes.3. The device of claim 1 , wherein the first fin and the second fin comprise the same semiconductor material.4. The device of claim 3 , wherein the semiconductor material is silicon.5. The device of claim 1 , wherein a first distance from a topmost surface of ...

Wrap Around Silicide for FinFETs

A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess. 1. A device comprising:a semiconductor substrate;isolation regions extending into the semiconductor substrate;a semiconductor fin between opposing portions of the isolation regions and protruding higher than the isolation regions;a gate stack on a first sidewall and a first top surface of the semiconductor fin;a source/drain region on a side of, and connecting to, the semiconductor fin; anda silicide region contacting a second top surface and second sidewalls of the source/drain region, wherein the silicide region extends to top surfaces of the isolation regions.2. The device of claim 1 , wherein the source/drain region comprises vertical and straight sidewalls extending to the top surfaces of the isolation regions.3. The device of claim 2 , wherein the vertical and straight sidewalls of the source/drain region comprise a first vertical and straight sidewall and a second vertical and straight sidewall parallel to each other.4. The device of claim 2 , wherein substantially all parts of the source/drain region higher than the top surfaces of the isolation regions are formed of a homogenous semiconductor material.5. The device of claim 1 , wherein the isolation regions comprise:a dielectric region formed of a first dielectric material; anda dielectric layer formed of a second dielectric material different from the first dielectric material, wherein the top surfaces of the isolation regions comprise a top ...