СПОСОБ ПРЕДВАРИТЕЛЬНОЙ ОЧИСТКИ И СПОСОБ ПОЛУЧЕНИЯ ТОНКОЙ ПЛЕНКИ НИЗКОТЕМПЕРАТУРНОГО ПОЛИКРЕМНИЯ, ЖИДКОКРИСТАЛЛИЧЕСКОЕ УСТРОЙСТВО ОТОБРАЖЕНИЯ И СИСТЕМА ДЛЯ ЕЕ ИЗГОТОВЛЕНИЯ

Настоящее изобретение относится к области технологий отображения жидкокристаллическими устройствами и, в частности, к способу изготовления тонкой пленки низкотемпературного поликремния, включающему: выращивание буферного слоя и затем слоя аморфного кремния на подложке; нагрев слоя аморфного кремния до температуры выше комнатной и выполнение предварительной очистки поверхности слоя аморфного кремния; использование отжига эксимерным лазером (ELA) для облучения слоя аморфного кремния, предварительно очищенного на предыдущем этапе, чтобы преобразовать аморфный кремний в поликремний. Настоящее изобретение также предлагает систему для изготовления тонкой пленки низкотемпературного поликремния. Путем совершенствования системы для изготовления тонкой пленки низкотемпературного поликремния и способа предварительной очистки настоящее изобретение уменьшает неравномерность толщины слоя аморфного кремния и неравномерность слоя поликремния, получаемого на последующем этапе облучения эксимерным лазером ...

СПОСОБ ПРЕДВАРИТЕЛЬНОЙ ОЧИСТКИ И СПОСОБ ПОЛУЧЕНИЯ ТОНКОЙ ПЛЕНКИ НИЗКОТЕМПЕРАТУРНОГО ПОЛИКРЕМНИЯ, ЖИДКОКРИСТАЛЛИЧЕСКОЕ УСТРОЙСТВО ОТОБРАЖЕНИЯ И СИСТЕМА ДЛЯ ЕЕ ИЗГОТОВЛЕНИЯ

СПОСОБ ПОЛУЧЕНИЯ НЕЗАВИСИМОЙ ПОДЛОЖКИ ИЗ НИТРИДА III ГРУППЫ

... 1. Способ получения независимой подложки (100) из нитрида III группы, включающий следующие стадии:- осаждение первого слоя (102) нитрида III группы на подложку (101) для выращивания;- формирование механически ослабленного жертвенного слоя (110) в полученной таким образом структуре;- осаждение второго слоя (107) нитрида III группы на первый слой (102) нитрида III группы и- отделение второго слоя (107) нитрида III группы от подложки (101) для выращивания по механически ослабленному жертвенному слою (110),отличающийся тем, что стадия формирования механически ослабленного жертвенного слоя (110) включает:- образование отверстий (105), проходящих от свободной поверхности первого слоя (102) нитрида III группы до граничной области (109) между первым слоем (102) нитрида III группы и подложкой (101) для выращивания, и- латеральное травление через отверстия (105) первого слоя (102) нитрида III группы в указанной граничной области (109);и на стадии осаждения второго слоя (107) нитрида III группы обеспечивают ...

SiC-Epitaxiewafer, Verfahren zum Herstellen eines SiC-Epitaxiewafers, SiC-Vorrichtung und Leistungsumwandlungsgerät

Method for producing a stack of layers on a crystalline substrate, which is free from nitride compound semiconductor by using metal organic gas-phase deposition, comprises forming a nitride-containing buffer layer on the substrate

The method for producing a stack of layers (2, 3, 4, 5, 6) on a crystalline substrate (1), which is free from nitride compound semiconductor by using metal organic gas-phase deposition, comprises forming a nitride-containing buffer layer on the substrate and then forming a crystalline layer made of group-III nitride compound semiconductor material, so that upper main surfaces (7, 8) of the buffer layer and crystalline layer are formed from nitrogen atoms. A contiguous region of upper main surface of the crystalline layer is smoothed. The crystalline layer has a diameter of more than 100 mu m. The method for producing a stack of layers (2, 3, 4, 5, 6) on a crystalline substrate (1), which is free from nitride compound semiconductor by using metal organic gas-phase deposition, comprises forming a nitride-containing buffer layer on the substrate and then forming a crystalline layer made of group-III nitride compound semiconductor material, so that upper main surfaces (7, 8) of the buffer layer ...

Synthetic diamond coated compound semiconductor substrates

GALLIUM NITRIDE MATERIALEN AND PROCEEDING FOR THE PRODUCTION OF LAYERS THESE MATERIALEN

PROCEDURE FOR THE BREED OF GAN SINGLE CRYSTALS

PRODUCTION OF LATTICE VOTE SEMICONDUCTOR SUBSTRATES

PROCEDURE FOR THE PRODUCTION OF A HETEROEPITAKTI MICROSTRUCTURE

PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ON GANBASIS

Method of producing self-supporting substrates comprising III-nitrides by means of heteroepitaxy on a sacrificial layer

Nanostructures and methods for manufacturing the same

III-V or II-VI compound semiconductor films on graphitic substrates

A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound.

HIGH GROWTH RATE DEPOSITION FOR GROUP III/V MATERIALS

Embodiments of the invention generally relate processes for epitaxial growing Group Ill/V materials at high growth rates, such as about 30 µm/hr or greater, for example, about 40 µm/hr, about 50 µm/hr, about 55 µm/hr, about 60 µm/hr, or greater. The deposited Group Ill/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group Ill/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group Ill/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group Ill/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

EPITAXIAL GROWING METHOD AND SUBSTRATE FOR EPITAXIAL GROWTH

An epitaxial growing method for growing a compound semiconductor layer (for example, a III-V compound semiconductor layer such as an InGaAs layer, an AlGaAs layer, an AlInAs layer, or an AlInGaAs layer) comprising three or four elements on a substrate (for example, an InP substrate) for growth held by a substrate support by an organic metal vapor phase deposition method, wherein the whole effective use region of the substrate is so polished that the angel of inclination with respect to the (100)-direction lies in the range from 0.00~ to 0.03~ or from 0.04~ to 0.24~, and the compound semiconductor layer with a thickness of 0.5 .mu.m or more is formed on the substrate for growth.

SEMICONDUCTOR FILM FROM COMPOUND III-V OR II-VI ON GRAPHITE SUBSTRATES

TEMPLATE FOR EPITAXIAL GROWTH AND METHOD OF PREPARING SAME, AND NITRIDE SEMICONDUCTOR DEVICE

Nanostructures and methods for manufacturing the same

METHODS OF FORMING III/IV SEMICONDUCTOR MATERIALS AND SEMICONDUCTOR STRUCTURES FORMED USING THE SAME

METHOD FOR GROWING AT LEAST ONE NANOWIRE FROM A LAYER OF A TRANSITION METAL NITRIDE OBTAINED TWO-STAGE

Le procédé de croissance d'au moins un nanofil (3) semi-conducteur, ledit procédé de croissance comporte une étape de formation, au niveau d'un substrat (1), d'une couche de nucléation (2) pour la croissance du nanofil (3) et une étape de croissance du nanofil (3). L'étape de formation de la couche de nucléation (2) comporte les étapes suivantes : le dépôt sur le substrat (1) d'une couche d'un métal de transition (4) choisi parmi Ti, V, Cr, Zr, Nb, Mo, Hf, Ta ; la nitruration d'au moins une partie (2) de la couche de métal de transition de sorte à former une couche de métal de transition nitruré présentant une surface destinée à la croissance du nanofil (3).

METHOD FOR MANUFACTURING A MONOCRYSTALLINE LAYER OF GAAS MATERIAL AND SUBSTRATE FOR EPITAXIAL GROWTH OF A MONOCRYSTALLINE LAYER OF GAAS MATERIAL

METHOD FOR PRODUCING A MONOCRYSTALLINE LAYER OF AN LNO MATERIAL AND SUBSTRATE FOR EPITAXIAL GROWTH OF A MONOCRYSTALLINE LAYER OF AN LNO MATERIAL

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

METHOD OF PRODUCING TEMPLATE FOR EPITAXIAL GROWTH AND NITRIDE SEMICONDUCTOR DEVICE

A method of manufacturing a wafer

필름, 필름의 제조방법 및 상기 필름을 포함하는 발광 다이오드

... 본 출원은 금속 질화물층 필름의 제조방법, 상기 방법에 의해 제조된 필름 및 상기 필름을 포함하는 발광 다이오드에 관한 것이다. 본 출원의 방법에 의하면, 황을 함유하는 화합물을 포함하는 용액에 금속 전구체를 포함하는 용액을 스프레이하여 금속 나노 입자 전구체의 폭발적인 반응 속도를 억제함으로써, 적은 비용으로도 상기 전구체 나노 입자의 입자 크기를 작게 제어할 수 있고, 이에 따라, 균일한 표면 거칠기를 가지는 필름을 대면적으로 제조할 수 있으며, 또한, 황을 함유하는 화합물과 금속 전구체의 반응에 의해 형성된 상기 금속 전구체 나노 입자가 황을 함유하므로, 상기 금속 나노 입자 전구체로부터 형성된 금속 질화물층 표면에서 황 성분이 광루미네선스 스펙트럼 상으로 검출되는 필름을 제공할 수 있다.

METHOD OF FORMING III/V SEMICONDUCTOR MATERIALS INCLUDING A THREE III- NITRIDE MATERIAL LAYER AND A SEMICONDUCTOR STRUCTURE FORMED USING THE SAME

PURPOSE: A method of forming III/V semiconductor materials and a semiconductor structure formed using the same are provided to epitaxially grow a three iii- nitride material on a substrate in a chamber. CONSTITUTION: A GaN(Gallium Nitride) layer is provided within a chamber. The InGaN(Indium Gallium Nitride) layer is epitaxially grown up on a surface of the GaN layer. A precursor gas mixture is provided within the chamber. The precursor gas mixture is selected to include one or more group III precursors and nitrogen precursors. The InGaN layer is grown up to less than the critical thickness of the InGaN layer. COPYRIGHT KIPO 2013 [Reference numerals] (AA) Lattice parameter(a)(A) of InGaN; (BB) Indium content(%) of InGaN ...

PRODUCTION METHOD FOR LIGHT EMITTING ELEMENT ABSRACT:

When p-type MgxZn1-xO is grown by an organometallic vapor growth method, a MgxZn1- xO layer is heat treated in an oxygen atmosphere during the growth and/or after the growth completion. In addition, the surface of a substrate to be grown and a material gas are irradiated with a ultraviolet ray when a semiconductor layer is vapor-grown. In addition, when a MgxZn1-xO buffer layer having its c-axis oriented in a layer thickness direction is formed by an atomic layer exitaxy method, a metal mono-atomic layer is grown at first. In addition, a ZnO-based semiconductor active layer is formed by a semiconductor material mainly consisting of ZnO containing Se or Te. A light emitting element is formed by using these techniques. © KIPO & WIPO 2008 ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME

PURPOSE: A semiconductor device is provided to reduce defects. CONSTITUTION: This semiconductor device comprises a substrate(102) which has on its surface a hollow(104) in a closed shape, when viewed from a substrate normal direction, and a semiconductor layer(103) formed on the surface of the substrate(102) by crystal growth at least from internal surface(105,106,107) of the hollow(104). © KIPO 2002 ...

Method of manufacturing single-crystal GaN substrate, and single-crystal GaN substrate

The present invention discloses a method to manufacture at a lower cost a GaN single crystal freestanding substrate of an off-axis angle having a crystal orientation that is displaced from (0001) instead of (0001) exact. With an off-axis angle (111) GaAs wafer as a starting substrate, GaN is vapor-deposited onto the starting substrate, which grows GaN crystal that is inclined at the same off-axis angle and in the same direction as is the starting substrate. Self-standing GaN substrates with the off-axis angle may be manufactured by utilizing a (111) GaAs base plate with the off-axis angle as a starting substrate, by forming onto the starting substrate a mask having a plurality of apertures, depositing through the mask a GaN single crystal layer, and then removing the starting substrate. The manufacturing of the GaN crystal having the off-axis angle of 0.1 to 25 DEG is possible.

Free standing substrate, method for manufacturing the same, and semiconductor light emitting element

The invention provides a free standing substrate, method for manufacturing the same, and a semiconductor light emitting element. The free standing substrate contains a semiconductor layer and inorganic particles. The inorganic particles are contained in the semiconductor layer. The method for making the free standing substrate contains the following process steps (a) - (c) in a sequential order. (a) the step of deploying inorganic particles on a substrate; (b)the step of growing the semiconductor layer; and (c) the step of separating the semiconductor layer and the substrate. In another aspect the method for making the free standing substrate contains the following process steps in a sequential order. (a) the step of growing a buffer layer on a substrate; (b)the step of deploying inorganic particles on the buffer layer; (c) growing a semiconductor layer; and (d) separating the semiconductor layer and the substrate. The semiconductor light emitting element contains the above free standing ...

Epitaxial substrate for electronic device, electronic device, method for producing epitaxial substrate for electronic device, and method for producing electronic device

The present invention is an epitaxial substrate for an electronic device, the epitaxial substrate having a Si-based substrate, an AlN initial layer provided on the Si-based substrate, and a buffer layer provided on the AlN initial layer, and the epitaxial substrate is characterized in that the roughness Sa of the surface on the buffer layer side of the AlN initial layer is 4 nm or more. Due to this configuration, provided is an epitaxial substrate for an electronic device, in which V-shaped pits in the buffer layer structure are prevented and longitudinal leak current characteristics can be improved when an electronic device is produced.

Method for improved growth of semipolar (al,in,ga,b)n

METHOD FOR PRODUCING III-N TEMPLATES AND THE REPROCESSING THEREOF AND III-N TEMPLATE

The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crytal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.

METHOD FOR MANUFACTURING A THICK EPITAXIAL LAYER OF GALLIUM NITRIDE ON A SILICON OR SIMILAR SUBSTRATE AND LAYER OBTAINED USING SAID METHOD

The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer (3; 3', 3") of GaN on a substrate (1) wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer (3a) of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer (4a) of BwAlxGaylnzN, (c2) growth of a layer (3b) of BwAlxGaylnzN, (c3) growth of an intermediate layer (4b) of BwAlxGaylnzN, at least one of the layers (3b, 4a, 4b) formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer (3; 3', 3") of GaN.

SEMICONDUCTOR STACKED BODY, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT

... [Problem] To provide a semiconductor stacked body having a low electric resistance in the thickness direction, a method for manufacturing the semiconductor stacked body, and a semiconductor element including the semiconductor stacked body. [Solution] A semiconductor stacked body (1) is provided, including a Ga2O3 substrate (2) having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer (3) formed on the Ga2O3 substrate (2), and a nitride semiconductor layer (4) formed on the AIN buffer layer (3).

Enhanced defect reduction for heteroepitaxy by seed shape engineering

A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

Epitaxial growth method of a zinc oxide based semiconductor layer, epitaxial crystal structure, epitaxial crystal growth apparatus, and semiconductor device

It is provided a hetero epitaxial growth method, a hetero epitaxial crystal structure, a hetero epitaxial growth apparatus and a semiconductor device, the method includes forming a buffer layer formed with the orienting film of an oxide, or the orienting film of nitride on a heterogeneous substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the buffer layer using a halogenated group II metal and an oxygen material. It is provided a homo epitaxial growth method, a homo epitaxial crystal structure, a homo epitaxial growth apparatus and a semiconductor device, the homo epitaxial growth method includes introducing reactant gas mixing zinc containing gas and oxygen containing gas on a zinc oxide substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the zinc oxide substrate.

Method for fabricating a carrier substrate

A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.

METHOD FOR ACHIEVING IMPROVED EPITAXY QUALITY (SURFACE TEXTURE AND DEFECT DENSITY) ON FREE-STANDING (ALUMINUM, INDIUM, GALLIUM) NITRIDE ((AL,IN,GA)N) SUBSTRATES FOR OPTO-ELECTRONIC AND ELECTRONIC DEVICES

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

Patterned Layer Design for Group III Nitride Layer Growth

A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

Epitaxial silicon carbide single crystal wafer and process for producing the same

An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 μm or more and 10 μm or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 μm or more and 100 μm or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.

Methods for improved growth of group III nitride semiconductor compounds

Methods are disclosed for growing group III-nitride semiconductor compounds with advanced buffer layer technique. In an embodiment, a method includes providing a suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. The method includes forming an AlN buffer layer by flowing an ammonia gas into a growth zone of the processing chamber, flowing an aluminum halide containing precursor to the growth zone and at the same time flowing additional hydrogen halide or halogen gas into the growth zone of the processing chamber. The additional hydrogen halide or halogen gas that is flowed into the growth zone during buffer layer deposition suppresses homogeneous AlN particle formation. The hydrogen halide or halogen gas may continue flowing for a time period while the flow of the aluminum halide containing precursor is turned off.

EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL WAFER AND PROCESS FOR PRODUCING THE SAME

An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 μm or more and 10 μm or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 μm or more and 100 μm or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.

COMPOSITE SUBSTRATE AND MANUFACTURING METHOD THEREOF

A composite substrate including a substrate and an aluminum nitride layer is provided. The aluminum nitride layer is disposed on a top surface of the substrate. Silicon is doped in the aluminum nitride layer to regulate residual stress, a film thickness of the aluminum nitride layer is less than 3.5 μm, a defect density of the aluminum nitride layer is less than or equal to 5×109/cm2, and a root mean square roughness of the top surface, facing away from the substrate, of the aluminum nitride layer is less than 3 nm. A manufacturing method of a composite substrate is also provided.

SEED WAFER FOR GaN THICKENING USING GAS- OR LIQUID-PHASE EPITAXY

Embodiments relate to fabricating a wafer including a thin, high-quality single crystal GaN layer serving as a template for formation of additional GaN material. A bulk ingot of GaN material is subjected to implantation to form a subsurface cleave region. The implanted bulk material is bonded to a substrate having lattice and/or Coefficient of Thermal Expansion (CTE) properties compatible with GaN. Examples of such substrate materials can include but are not limited to AlN and Mullite. The GaN seed layer is transferred by a controlled cleaving process from the implanted bulk material to the substrate surface. The resulting combination of the substrate and the GaN seed layer, can form a template for subsequent growth of overlying high quality GaN. Growth of high-quality GaN can take place utilizing techniques such as Liquid Phase Epitaxy (LPE) or gas phase epitaxy, e.g., Metallo-Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).

EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE

Provided is a crack-free epitaxial substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a first and a second lamination unit being alternately laminated such that each of an uppermost and a lowermost portion of the buffer layer is formed of the first lamination unit. The first lamination unit is formed of a first and a second composition layer having different compositions being alternately laminated so as to increase the thickness of the second composition layer in a portion more distant from the base substrate side, to thereby cause a compressive strain to exist in the first lamination unit such that it increases in a portion more distant from the base substrate. The second lamination unit is formed as an intermediate layer that is substantially strain-free and formed with a thickness of 15 nm or more and 150 nm or less.

SELECTIVE NANOSCALE GROWTH OF LATTICE MISMATCHED MATERIALS

Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially- single- particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

DYNAMIC HVPE OF COMPOSITIONALLY GRADED BUFFER LAYERS

Described herein are devices and methods related to compositionally graded buffers (CGB) and methods and/or systems for producing CGBs. CGBs enable the growth of high quality materials that are lattice mismatched to a substrate. More specifically, the present disclosure relates to methods for making CGBs by hydride vapor phase epitaxy (HVPE). HVPE methods using a single chamber for producing a CGB may result in a transience in the CGB layers as the flows supplying the reactants are switched to produce the next subsequent layer in the CGB. In contrast to this static style of grading, the present disclosure describes a dynamic method for producing CGBs, in which multiple growth chambers are utilized.

Nanostructures and methods for manufacturing the same

A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps. Thus a resonant tunneling diode comprises a nanowhisker having a seed particle melt at one end, and a column of a constant diameter with a nanometer dimension, such as to exhibit quantum confinement effects, the column comprising first and second semiconductor portions comprising respectively an emitter and a collector, and, disposed between the first and second semiconductor portions, third and fourth portions of material having a different band gap from that of the first and second semiconductor portions, and a fifth central portion of a semiconductor material having a different band gap from that of the third and fourth portions, disposed between the third and fourth portions and forming a quantum weil. The RTD is made by ...

METHOD OF MANUFACTURING WAFER

PROBLEM TO BE SOLVED: To provide a method for obtaining a wafer provided with a good epitaxial layer grown on a substrate having a lattice different from that of the epitaxial layer. SOLUTION: Surface roughness of the wafer is increased by polishing the on-axis silicon substrate in the polishing step 104. After a graded buffer layer, e.g. an SiGe layer, and a relaxation layer are formed on the wafer, CMP final polishing 108 is executed. COPYRIGHT: (C)2006,JPO&NCIPI ...

НЕПОЛЯРНАЯ СВЕТОДИОДНАЯ ЭПИТАКСИАЛЬНАЯ ПЛАСТИНА СИНЕГО СВЕЧЕНИЯ НА ПОДЛОЖКЕ ИЗ LAO И СПОСОБ ЕЕ ПОЛУЧЕНИЯ

Изобретение относится к светодиодной эпитаксиальной пластине и способу ее получения. Предложена неполярная светодиодная эпитаксиальная пластина синего свечения на подложке из алюмината лантана (LAO), содержащая последовательно нанесенные на подложку из LAO слои: буферный слой, выполненный из GaN с неполярной гранью m; первый нелегированный слой, представляющий собой неполярный нелегированный слой из u-GaN; первый легированный слой, представляющий собой неполярную легированную пленку из GaN типа n; слой квантовой ямы, представляющий собой неполярный слой квантовой ямы из InGaN/GaN; электронный инверсионный слой, представляющий собой электронный инверсионный слой из AlGaN с неполярной гранью m; и второй легированный слой, представляющий собой неполярную легированную пленку из GaN p типа. Также предложен способ получения неполярной светодиодной эпитаксиальной пластины синего свечения на подложке из LAO. Изобретения обеспечивают низкую плотность дефектов, высокое качество и хорошие оптические ...

Halbleiterlaminat und Prozess für seine Herstellung und Halbleiterelement

Problem: ein Halbleiterlaminat mit einem kleinen elektrischen Widerstand in der Dickenrichtung, einen Prozess zum Herstellen des Halbleiterlaminats und ein Halbleiterelement, das mit dem Halbleiterlaminat versehen ist, bereitzustellen. Lösung: Bereitgestellt ist ein Halbleiterlaminat (1) mit: einem Ga2O3-Substrat (2); einer AlGaInN-Pufferschicht (3), die auf dem Ga2O3-Substrat (2) gebildet ist; einer Nitridhalbleiterschicht (4), die auf der AlGaInN-Pufferschicht (3) gebildet ist und Si aufweist; und einem Si-reichen Bereich (4a), der in einem Gebiet gebildet ist, das auf der Seite der AlGaInN-Pufferschicht (3) in der Nitridhalbleiterschicht (4) lokalisiert ist, und eine Si-Konzentration von 5 × 1018/cm3 oder mehr hat.

EPITAXIESUBSTRAT FÜR EINE HALBLEITERVORRICHTUNG, VERFAHREN ZUR HERSTELLUNG EINES EPITAXIESUBSTRATS FÜR EINE HALBLEITERVORRICHTUNG, UND HALBLEITERVORRICHTUNG

Epitaxiesubstrat für eine Halbleitervorrichtung, bei dem eine Gruppe von Gruppe-III-Nitridschichten auf einem Basissubstrat (1) aus einkristallinem Silizium mit einer (111)-Orientierung, so dass eine (0001)-Kristallebene annähernd parallel zu einer Oberfläche des Basissubstrats (1) ist, gebildet ist, umfassend: eine erste aus AlN auf dem Basissubstrat (1) gebildete Gruppe-III-Nitridschicht (3); eine zweite aus InxxAlyyGazzN (xx + yy + zz = 1, 0 ≤ xx < 1, 0 ≤ yy < 1, und 0 < zz ≤ 1) auf der ersten Gruppe-III-Nitridschicht (3) gebildete Gruppe-III-Nitridschicht (4); und zumindest eine dritte Gruppe-III-Nitridschicht (5, 6), die auf der zweiten Gruppe-III-Nitridschicht epitaktisch gebildet ist, dadurch gekennzeichnet, dass: die erste Gruppe-III-Nitridschicht (3) eine Schicht ist, die mehrere Fehlstellen (d) enthält, die zumindest eine Art aus einem Stängelkristall, einem Kornkristall, einer Stängeldomäne und einer Korndomäne enthalten; eine Schnittstelle zwischen der ersten Gruppe-III-Nitridschicht ...

Halbleiterkomponente, die ein mit Kohlenstoff dotiertes Substrat aufweist

Gemäß einer Ausführungsform umfasst ein Verfahren zur Herstellung einer Halbleiterkomponente die Bereitstellung eines Halbleitermaterials, welches eine Fläche aufweist, Bildung einer epitaxialen Schicht von mit Kohlenstoff dotiertem Halbleitermaterial auf dem Halbleitersubstrat, wobei die epitaxiale Schicht eine Fläche aufweist, Bildung einer Keimbildungsschicht auf der epitaxialen Schicht; und Bildung einer Schicht aus III-Nitridmaterial auf der Keimbildungsschicht. Gemäß einer anderen Ausführungsform umfasst die Halbleiterkomponente ein Siliziumhalbleitersubstrat eines ersten Leitfähigkeitstyps; eine mit Kohlenstoff dotierte epitaxiale Schicht auf dem Siliziumhalbleitersubstrat; eine Pufferschicht über der mit Kohlenstoff dotierten Pufferschicht; und eine Kanalschicht über der mit Kohlenstoff dotierten Pufferschicht.

Method for producing GaN laminate substrate

The present invention includes: transferring a C-plane sapphire thin film 1t having an off-angle of 0.5-5° onto a handle substrate composed of a ceramic material having a coefficient of thermal expansion at 800 K that is greater than that of silicon and less than that of C-plane sapphire, thus preparing a GaN epitaxial growth substrate 11; performing high-temperature nitriding treatment on the GaN epitaxial growth substrate 11 and covering the surface of the C-plane sapphire thin film 1t with a surface treatment layer 11a made of AlN; having GaN grow epitaxially on the surface treatment layer 11a, thus preparing a GaN film carrier, the surface of which is made of an N-polarity surface; ion-implanting a GaN film 13; pasting and bonding together the GaN film-side surface of the ion-implanted GaN film carrier and a support substrate 12; performing peeling at an ion implantation region 13ion in the GaN film 13 and transferring a GaN thin film 13a onto the support substrate 12; and obtaining ...

METHOD FOR PRODUCING GaN LAMINATE SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ON GANBASIS

PROCEDURE FOR BREEDING A GAN SINGLE CRYSTAL, PROCEDURE FOR THE PRODUCTION OF A GAN SUBSTRATE, PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ON GANBASIS AND ELEMENT ON GAN BASIS

Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby

DIAMOND MATERIALS COMPRISING MULTIPLE CVD GROWN, SMALL GRAIN DIAMONDS, IN A SINGLE CRYSTAL DIAMOND MATRIX

The present technology relates to diamond materials and structures created using chemical vapor deposition techniques (i.e., creation of synthetic diamond). The chemical vapor deposited diamond includes a multiphase material comprising (a) a single crystalline matrix phase and (b) plurality of diamond grains, each of the plurality of diamond grains being crystallographically distinct from the single crystalline matrix phase.

METHOD FOR PRODUCING A LAMINATED BODY HAVING A1-BASED GROUP-III NITRIDE SINGLE CRYSTAL LAYER, LAMINATED BODY PRODUCED BY THE METHOD, METHOD FOR PRODUCING A1-BASED GROUP-III NITRIDE SINGLE CRYSTAL SUBSTRATE EMPLOYING THE LAMINATED BODY, AND ALUMINUM NITRIDE SINGLE CRYSTAL SUBSTRATE

Disclosed is a process for producing a laminate, comprising (1) the step of providing a base substrate having a surface formed of a single crystal of a material different from a material for constituting an Al-based group III nitride single crystal layer to be formed, (2) the step of forming an Al-based group III nitride single crystal layer having a thickness of 10 nm to 1.5 µm on the single crystal plane of the provided base substrate, (3) the step of forming a non-single crystal layer having a thickness of not less than 100 times the thickness of the Al-based group III nitride single crystal layer on the Al-based group III nitride single crystal layer without breaking the Al-based group III nitride single crystal layer, and (4) the step of removing the base substrate. The production process can provide a substrate that is suitable for use as a base substrate for the production of a self-supporting substrate of an Al-based group III nitride single crystal, has a surface formed of a single ...

Crystal layered structure and method for manufacturing same, and semiconductor element

Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure (1) including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0 <= x <= 1, 0 <= y <= 1, 0 <= z <= 1, x + y + z = 1) crystal on the Ga2O3 substrate (2); and a nitride semiconductor layer (4) comprising an AlxGayInzN (0 <= x <= 1, 0 <= y <= 1, 0 <= z <= 1, x + y + z = 1) crystal including oxygen as an impurity on the buffer layer (3). The oxygen concentration in a region (4a) having a thickness of no less than 200 nm on the nitride semiconductor layer (4) on the side towards the Ga2O3 substrate (2) is no less than 1.0*1018/cm3.

Epitaxial wafer, light-receiving element, optical sensor device, and method for manufacturing epitaxial wafer and light-receiving element

Provided is an epitaxial wafer within which is a layer containing antimony, and which can be manufactured efficiently with reduced yield-decreasing surface defects, and with which the inclusion of impurities that cause a deterioration in performance can be prevented; also provided are a light-receiving element and the like. The manufacturing method is characterized in that it has a step wherein a layer containing antimony (Sb) is grown on a substrate (1) using an all-organometallic vapor deposition method, and steps wherein layers up to and including a window layer (5) which do not contain antimony are grown on the antimony-containing layer, and the growth that occurs subsequent to growth of the antimony-containing layer and until growth of the window layer is completed occurs at a temperature of 425-525 DEG C.

Epitaxial growing method and substrate for epitaxial growth

Method for manufacturing deformation silicon substrate

This invention provides a method for manufacturing a deformation Si substrate, comprising at least forming a lattice relaxed SiGe layer on a silicon single crystal substrate, flattening the surface of the SiGe layer by CMP, and forming a deformation Si layer on the surface of the flattened SiGe layer. The method is characterized by, before the formation of the deformation Si layer on the surface of the flattened lattice relaxed SiGe layer, subjecting the surface of the SiGe layer to SC1 washing, heat treating the substrate provided with the SiGe layer subjected to SC1 washing in a hydrogen-containing atmosphere of 800 C or above, forming a protective Si layer on the surface of the SiGe layer on the heat treated substrate immediately after the heat treatment without lowering the temperature to below 800 C after the heat treatment, and forming a deformation Si layer on the surface of the protective Si layer at a temperature below the protective Si layer forming temperature. The above method ...

METHOD FOR DETERMINING PREFERRED DEPOSITION PARAMETERS FOR A TYRE III-V

Des première, deuxième et troisième séries d'échantillons (F7, F9, F11) sont réalisées successivement de manière à déterminer l'influence des paramètres de dépôt sur la qualité cristallographique d'une couche en matériau semi-conducteur de type III-V (F8, F10, F12). Les paramètres étudiés sont successivement la pression de dépôt, la température de dépôt et l'épaisseur déposée d'une sous-couche en matériau semi-conducteur de type III-V de manière à déterminer respectivement une premier pression de dépôt, une première température de dépôt à la première pression de dépôt et une première épaisseur déposée à la première température de dépôt et à la première pression de dépôt. La sous-couche en matériau semi-conducteur de type III-V est épaissie au moyen d'une deuxième couche en matériau semi-conducteur de type III-V déposée dans des conditions différentes.

METHOD FOR PRODUCING A CRYSTALLINE LAYER INTO COMPOUND III-NITRIDE-VAN-DER-WAALS EPITAXIALLY FROM A GRAPHENE

PROCESSES OF MASSIVE NITRIDE MATERIAL FORMATION III ON MATRIC LAYERS OF METAL NITRIDE GROWTH AND STRUCTURES FORMEES BY THESE PROCESSES

Des matériaux semiconducteurs massifs de nitrure III sont déposés en utilisant un procédé HVPE qui utilise un précurseur de trichlorure de métal sur une couche matricielle de nitrure de métal d'un substrat de croissance. Le dépôt du matériau semiconducteur massif de nitrure III peut être réalisé sans formation ex situ de la couche matricielle en utilisant un procédé MOCVD. Dans certains modes de réalisation, une couche matricielle de nucléation est formée ex situ en utilisant un procédé non-MOCVD avant le dépôt du matériau semiconducteur massif de nitrure III sur la couche matricielle en utilisant un procédé HVPE. Dans d'autres modes de réalisation, une couche matricielle de nucléation est formée in situ en utilisant un procédé MOCVD avant le dépôt du matériau semiconducteur massif de nitrure III sur la couche matricielle en utilisant un procédé HVPE. Dans d'autres modes de réalisation, une couche matricielle de nucléation est formée in situ en utilisant un procédé HVPE avant le dépôt du ...

MANUFACTORING PROCESS Of a THICK EPITAXIAL LAYER OF GALLIUM NITRIDE ON a SILICON SUBSTRATE OR ANALOGUE AND LAYER OBTAINED BY THE AFOREMENTIONED PROCESS

Fabricating epitaxial layer on semiconductor substrate in the fabrication of e.g. Schottky diode, by providing substrate, forming epitaxial layer in contact with seed layer epitaxy process, and adjusting lattice parameters of layers

L'invention concerne un procédé de fabrication d'une couche d'épitaxie sur un substrat comprenant une couche support et une couche germe, le procédé comprenant les étapes consistant à : - fournir (E0) un substrat (1) comprenant : o une couche support (3), et o une couche germe (4) présentant un premier paramètre de maille et comprenant au moins un élément de la troisième colonne (III) et de l'azote (N), le matériau de la couche d'épitaxie étant différent du matériau de la couche germe, - former par épitaxie une couche d'épitaxie (2) en contact de la couche germe (4), o ladite épitaxie étant réalisée à une température d'épitaxie, o ladite couche d'épitaxie (2) présentant un second paramètre de maille et comprenant au moins un élément de la troisième colonne (III) et de l'azote (N), ledit procédé étant caractérisé en ce qu'il comprend une opération (E1) d'adaptation de paramètre de maille permettant de rendre le premier paramètre de maille sensiblement égal au second paramètre de maille à ...

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

On On PROCEDE INTEGRATION UN COMPOSANT DE TYPE III-N, TEL THAT DU GaN, SUR UN SUBSTRAT NOMINAL DE SILICIUM (001)

METHODS OF FORMING Ⅲ/Ⅴ SEMICONDUCTOR MATERIALS, AND SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS

MANUFACTURING METHOD OF NITRIDE-BASED COMPOUND SEMICONDUCTOR SUBSTRATE AND NITRIDE-BASED COMPOUND SEMICONDUCTOR FREE-STANDING SUBSTRATE

GaN SUBSTRATE WITH AlxGa1-xN INTERMEDIATE LAYER FOR IMPROVING PLANARIZATION, METHOD OF MANUFACTURING GaN SUBSTRATE, NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE

PURPOSE: A GaN substrate, a method of manufacturing the GaN substrate, a nitride semiconductor device and a method of manufacturing the nitride semiconductor device are provided to improve planarization of the substrate by using AlxGa1-xN intermediate layer. CONSTITUTION: A GaN substrate(28) includes a substrate(14), a first AlxGa1-xN(0 Подробнее

EPITAXIAL WAFER, LIGHT-RECEIVING ELEMENT, OPTICAL SENSOR DEVICE, AND METHOD FOR MANUFACTURING EPITAXIAL WAFER AND LIGHT-RECEIVING ELEMENT

Method of manufacturing a substrate

Method for manufacturing deformation silicon substrate

This invention provides a method for manufacturing a deformation Si substrate, comprising at least forming a lattice relaxed SiGe layer on a silicon single crystal substrate, flattening the surface of the SiGe layer by CMP, and forming a deformation Si layer on the surface of the flattened SiGe layer. The method is characterized by, before the formation of the deformation Si layer on the surface of the flattened lattice relaxed SiGe layer, subjecting the surface of the SiGe layer to SC1 washing, heat treating the substrate provided with the SiGe layer subjected to SC1 washing in a hydrogen-containing atmosphere of 800 C or above, forming a protective Si layer on the surface of the SiGe layer on the heat treated substrate immediately after the heat treatment without lowering the temperature to below 800 C after the heat treatment, and forming a deformation Si layer on the surface of the protective Si layer at a temperature below the protective Si layer forming temperature. The above method ...

METHODS OF FORMING III/V SEMICONDUCTOR MATERIALS, AND SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS

METHODS OF FORMING III/V SEMICONDUCTOR MATERIALS, AND SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODSMethods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relativley high ratio, the layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Figure 4 ...

HIGH GROWTH RATE DEPOSITION FOR GROUP III/V MATERIALS

Embodiments of the invention generally relate processes for epitaxial growing Group Ill/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group Ill/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group Ill/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group Ill/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group Ill/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

GALLIUM NITRIDE MATERIAL AND DEVICE DEPOSITION ON GRAPHENE TERMINATED WAFER AND METHOD OF FORMING THE SAME

A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate. 1. A method of forming a semiconductor material comprising:forming a graphene layer on a semiconductor and carbon containing substrate;depositing a metal containing monolayer on the graphene layer;forming an epitaxial layer of a gallium containing material on the metal containing monolayer; andcleaving a layered stack of the metal containing monolayer and the epitaxial layer of the gallium containing material from the graphene layer that is present on the semiconductor and carbon containing substrate.2. The method of claim 1 , wherein the semiconductor and carbon containing substrate is comprised of silicon carbide having a single crystal crystalline structure.3. The method of claim 1 , wherein the steps of depositing the metal containing monolayer and forming the epitaxial layer of the gallium containing material are conducted in a chemical vapor deposition apparatus.4. The method of claim 3 , wherein prior to depositing the metal containing monolayer claim 3 , the graphene layer and the semiconductor and carbon containing substrate are heated within the chemical vapor deposition apparatus to a temperature ranging from 800° C. to 1200° C. for a time period ranging from 10 minutes to 20 minutes.5. The method of claim 4 , wherein the depositing the metal containing monolayer comprises forming an aluminum containing layer by flowing an aluminum containing source gas selected from the group consisting of trimethylaluminum (TMAl) claim 4 , aluminum chloride ( ...

Formation of highly dislocation free compound semiconductor on a lattice mismatched substrate

A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0≦x, y≦1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through ion implantation. A monocrystalline template layer of the compound semiconductor is then created on the buffer layer, and an epilayer of the compound semiconductor is grown on the template layer. A compound semiconductor based device structure may be formed in the epilayer.

Substrate for stressed systems and method of making same

A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method

A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore, a crystal growth occurs only from an upper part of a convex part 11. As shown in FIG. 1(b), therefore, a crystal unit 20 occurs when the crystal growth is started, and as the crystal growth proceeds, films grown in the lateral direction from the upper part of the convex part 11 as a starting point are connected to cover the concavo-convex surface of the substrate 1, leaving a cavity 13 in the concave part, as shown in FIG. 1(c), thereby giving a crystal layer 2, whereby the semiconductor base of the present invention is obtained. In this case, the part grown in the lateral direction, or the upper part of the concave part 12 has a low dislocation region and the crystal layer prepared has high quality. The manufacturing ...

GROUP 13 ELEMENT NITRIDE CRYSTAL SUBSTRATE AND FUNCTION ELEMENT

A crystal substrate 1 includes an underlying layer 2 and a thick film 3. The underlying layer 2 is composed of a crystal of a nitride of a group 13 element and includes a first main face 2a and a second main face 2b. The thick film 3 is composed of a crystal of a nitride of a group 13 element and provided over the first main face of the underlying layer. The underlying layer 2 includes a low carrier concentration region 5 and a high carrier concentration region 4 both extending between the first main face 2a and the second main face 2b. The low carrier concentration region 5 has a carrier concentration of 1017/cm3 or lower and a defect density of 107/cm2 or lower. The high carrier concentration region 4 has a carrier concentration of 1019/cm3 or higher and a defect density of 108/cm2 or higher. The thick film 3 has a carrier concentration of 1018/cm3 or higher and 1019/cm3 or lower and a defect density of 107/cm2 or lower.

Self-supported nitride semiconductor substrate and its production method, and light-emitting nitride semiconductor device using it

A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.

Zirconium and Hafnium Boride Alloy Templates on Silicon for Nitride Integration Applications

Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.

CRYSTAL LAYERED STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT

Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a GaOsubstrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a GaOsubstrate; a buffer layer comprising an AlGaInN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) crystal on the GaOsubstrate; and a nitride semiconductor layer comprising an AlGaInN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the GaOsubstrate is no less than 1.0×10/cm. 1. A crystal layered structure , comprising:{'sub': 2', '3, 'a GaOsubstrate;'}{'sub': x', 'y', 'z', '2', '3, 'a buffer layer comprising an AlGaInN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) crystal on the GaOsubstrate; and'}{'sub': x', 'y', 'z, 'a nitride semiconductor layer comprising an AlGaInN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) crystal containing oxygen as an impurity on the buffer layer,'}{'sub': 2', '3, 'sup': 18', '3, 'wherein an oxygen concentration in a region on a side of the GaOsubstrate of the nitride semiconductor layer, region having a thickness of not less than 200 nm, is not less than 1.0×10/cm.'}2. The crystal layered structure according to claim 1 , wherein the nitride semiconductor layer has a dislocation density of less than 1.0×10/cmon a surface thereof opposite the GaOsubstrate.3. The crystal layered structure according to claim 1 , wherein an oxygen concentration in a region on the side of the GaOsubstrate of the nitride semiconductor layer claim 1 , the region having a thickness of not less than 500 nm claim 1 , is not less than 1.0×10/cm.4. The crystal layered structure according to claim 1 , wherein the oxygen concentration in the region is not less than 5.0×10/cm.5. The crystal layered structure according to claim 1 , wherein the AlGaInN crystal of the buffer layer ...

SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Nitride semiconductor thin film and method for growing the same

The present invention relates to a nitride semiconductor thin film and a method for growing the same. The present invention has an advantage in that a plurality of grooves are formed on a substrate by partially etching the substrate, and leg portions for preventing longitudinal growth of a nitride semiconductor are formed within the grooves so that the nitride semiconductor thin film is grown laterally to cover top portions of the leg portions, thereby ensuring growth of a high quality nitride semiconductor thin film.

Method for fabricating wafer product and method for fabricating gallium nitride based semiconductor optical device

Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S 105 , a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11 a of a gallium oxide substrate 11 . After the growth of the buffer layer 13 , while supplying a gas G 2 , which contains hydrogen and nitrogen, into a growth reactor 10 , the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.

Low-temperature selective epitaxial growth of silicon for device integration

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal

According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×10 18 cm −3 or more and less than 1×10 21 cm −3 . The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

METHOD FOR PRODUCING DIAMOND LAYERS AND DIAMONDS PRODUCED BY THE METHOD

The present invention relates to a method for producing diamond layers, wherein firstly, in a first growing step, diamond is grown on a growing surface of a off axis or a off-axis heterosubstrate in such a way that a texture width, in particular a polar and/or azimuthal texture width, of a diamond layer produced during the growth decreases with increasing distance from the substrate and then, in a second growing step, diamond is grown in such a way that the texture width of the diamond layer remains substantially constant as the distance from the substrate further increases, and lattice planes of the substrate being inclined by an angle greater than zero with respect to the growing surface. 1. A method for producing diamond layers , wherein diamond is first grown in a first growth step onto a growth surface of an off-axis heterosubstrate or a off-axis heterosubstrate such that a texture width , in particular a polar and/or azimuthal texture width , of a diamond layer arising through the growing on reduces with an increasing distance from the substrate and then , in a second growth step , diamond is grown on so that the texture width of the diamond layer remains substantially constant with a further increasing spacing from the substrate , wherein networkplanes or network planes of the substrate being inclined by an angle greater than zero with respect to the growth surface.2. A method for producing diamond layers , wherein diamond is grown onto a growth surface of an off-axis heterosubstrate or a off-axis heterosubstrate; wherein the heterosubstrate has an iridium layer on an off-axis buffer layer , on a preferably monocrystalline silicon substrate; and wherein network planes of the iridium layer are inclined by an angle larger than zero with respect to the growth surface.3. The method in accordance with claim 2 , wherein the buffer layer is or has an oxide buffer layer claim 2 , preferably yttria-stabilized zirconia (YSZ) claim 2 , with the heterosubstrates ...

Base material for growing single crystal diamond and method for producing single crystal diamond substrate

The present invention is a base material for growing a single crystal diamond comprising a single crystal silicon substrate, a MgO film heteroepitaxially grown on a side of the single crystal silicon substrate where the single crystal diamond is to be grown, and an iridium film or a rhodium film heteroepitaxially grown on the MgO film. As a result, there is provided a base material for growing a single crystal diamond and a method for producing a single crystal diamond substrate which can grow the single crystal diamond having a large area and good crystallinity and produce a high quality single crystal diamond substrate at low cost.

BASE MATERIAL FOR GROWING SINGLE CRYSTAL DIAMOND AND METHOD FOR PRODUCING SINGLE CRYSTAL DIAMOND SUBSTRATE

A base material for growing a single crystal diamond that includes at least a single crystal SiC substrate, and an iridium film or a rhodium film heteroepitaxially grown on a side of the single crystal SiC substrate where the single crystal diamond is to be grown. As a result, there is provided a base material for growing a single crystal diamond and a method for producing a single crystal diamond substrate which can grow the single crystal diamond having a large area and good crystallinity and produce a high quality single crystal diamond substrate at low cost. 1. A method for producing a single crystal diamond substrate comprising at least the steps of:preparing a single crystal SiC substrate;heteroepitaxially growing an iridium film or a rhodium film over the prepared single crystal SiC substrate;heteroepitaxially growing a single crystal diamond on the iridium film or the rhodium film heteroepitaxially grown; andseparating the single crystal diamond heteroepitaxially grown to obtain the single crystal diamond substrate.2. The method for producing a single crystal diamond substrate according to claim 1 , wherein the step of heteroepitaxially growing a MgO film on the single crystal SiC substrate is performed before the step of heteroepitaxially growing the iridium film or the rhodium film and the iridium film or the rhodium film is heteroepitaxially grown on the MgO film.3. The method for producing a single crystal diamond substrate according to claim 1 , wherein before the step of heteroepitaxially growing the single crystal diamond claim 1 , a bias treatment is preliminarily performed on a surface of the iridium film or the rhodium film.4. The method for producing a single crystal diamond substrate according to claim 2 , wherein before the step of heteroepitaxially growing the single crystal diamond claim 2 , a bias treatment is preliminarily performed on a surface of the iridium film or the rhodium film.5. The method for producing a single crystal diamond ...

Gallium-Nitride-On-Diamond Wafers and Manufacturing Equipment and Methods of Manufacture

A method for integrating wide-gap semiconductors, and specifically, gallium nitride epilayers, with synthetic diamond substrates is disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure that comprises at least one layer of gallium nitride. Methods for manufacturing GaN-on-diamond wafers with low bow and high crystalline quality are disclosed along with preferred choices for manufacturing GaN-on-diamond wafers and chips tailored to specific applications. 1. A method for synthetic diamond growth comprising the steps of:(a) providing a vacuum chamber having means for evacuating;(b) providing an engineered wafer comprising at least one layer of gallium nitride, said wafer having a diameter and a growth surface;(c) providing a table having a surface for holding said wafer, said table operatively configured to rotate along an axis perpendicular to said engineered wafer;(d) placing said wafer on said surface;(e) providing a cooled chuck with means for monitoring a temperature of said chuck;(f) placing said table onto said chuck;(g) maintaining a gap between said table and said chuck;(h) providing a multiplicity of refractory-metal filaments arranged in a linear one-dimensional array stretched in proximity of said wafer, said array being parallel to said growth surface, said multiplicity of filaments distanced from said growth surface by not more than 25 mm;(i) providing reaction gases to the chamber wherein said reaction gases comprise hydrogen and at least one carbon-bearing gas, and establish a process pressure; and 'wherein said cooled chuck maintains said chuck temperature below 800° C.', '(j) providing electrical power to said multiplicity of refractory-metal filaments, said electrical power being not less than 3 kW for one wafer, for a time sufficient to grow desired thickness of synthetic diamond,'}2. The method of claim 1 , wherein said growth surface is comprised of silicon ...

LATTICE MATCHING LAYER FOR USE IN A MULTILAYER SUBSTRATE STRUCTURE

A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors. 1. A lattice matching layer for use in a multilayer substrate structure , the lattice matching layer including:a first chemical element, the first chemical element having a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than the room temperature, the hexagonal close-packed structure of the first chemical element having a first lattice parameter; anda second chemical element, the second chemical element having a hexagonal close-packed structure at room temperature with similar chemical properties to the first chemical element, the hexagonal close-packed structure of the second chemical element having a second lattice parameter, the second chemical element being miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature,wherein a lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.2. The lattice matching layer of claim 1 , wherein a linear ...

Semiconductor laminate and process for production thereof, and semiconductor element

A semiconductor laminate having small electric resistivity in the thickness direction; a process for producing the semiconductor laminate; and a semiconductor element equipped with the semiconductor laminate. include a semiconductor laminate including a Ga 2 0 3 substrate; an AlGalnN buffer layer which is formed on the Ga 2 0 3 substrate; a nitride semiconductor layer which is formed on the AlGalnN buffer layer and contains Si; and an Si-rich region which is formed in an area located on the AlGalnN buffer layer side in the nitride semiconductor layer and has an Si concentration of 5×10 18 /cm 3 or more.

GROWTH SUBSTRATE AND LIGHT EMITTING DEVICE COMPRISING THE SAME

A growth substrate including a substrate having a growth surface including a plurality of steps inclining in a first direction; a first layer disposed on the growth surface, the first layer including an A-plane or an M-plane in an upper part thereof, a plurality of protrusions having an inclined surface on an upper surface thereof, and nitride; a mask layer including a dielectric material and having at least a portion disposed on the protrusions; and a second layer disposed on the mask layer and including nitride. 1. A growth substrate comprising:a substrate having a growth surface including a plurality of steps inclining in a first direction; an A-plane or an M-plane in an upper part thereof,', 'a plurality of protrusions having an inclined surface on an upper surface thereof, and', 'nitride;, 'a first layer disposed on the growth surface, the first layer includinga mask layer including a dielectric material and having at least a portion disposed on the protrusions; anda second layer disposed on the mask layer and including nitride.2. The growth substrate according to claim 1 , wherein a width of an inclination direction of the steps of the substrate are uniform.3. The growth substrate according to claim 1 , wherein the substrate includes a material having a hexagonal system claim 1 , andwherein a virtual line connecting ends of the steps of the substrate forms an angle of inclination in a positive (+) direction from an R plane of the substrate.4. The growth substrate according to claim 3 , wherein the angle formed by the virtual line and the R plane of the substrate is 0.2° to 0.4°.5. The growth substrate according to claim 1 , wherein the mask layer and the second layer form an air void between each other.6. The growth substrate according to claim 1 , wherein the upper surface of the first layer and an upper surface of the second layer have an identical crystal plane.7. The growth substrate according to claim 1 , wherein the mask layer comprises at least one of a ...

GROUP III NITRIDE SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

The present invention provides a method for producing a Group III nitride semiconductor device which can relax strain between a Group III nitride semiconductor layer containing In and a semiconductor layer adjacent thereto, and a production method therefor. The well layer is a Group III nitride semiconductor layer containing In. The barrier layer is a Group III nitride semiconductor layer. The well layer and the barrier layer are brought into contact with each other in at least one of growing a well layer and growing a barrier layer. A gas containing hydrogen gas as a carrier gas is used in growing a well layer and growing a barrier layer. In growing a barrier layer, the flow rate of hydrogen gas is higher than the flow rate of hydrogen gas in growing a well layer. 1. A method for producing a Group III nitride semiconductor device , the method comprising:growing a first semiconductor layer; andgrowing a second semiconductor layer, whereinthe first semiconductor layer is a Group III nitride semiconductor layer containing In,the second semiconductor layer is a Group III nitride semiconductor layer,the second semiconductor layer has a band gap larger than a band gap of the first semiconductor layer, anda flow rate of hydrogen gas used as a carrier gas in growing a second semiconductor layer is larger than a flow rate of hydrogen gas in growing a first semiconductor layer.2. The method for producing a Group III nitride semiconductor device according to claim 1 , wherein the flow rate of the hydrogen gas is linearly increased or decreased at least one of an initial stage and a final stage of the growth of the second semiconductor layer.3. The method for producing a Group III nitride semiconductor device according to claim 1 , wherein a mixture gas of hydrogen gas and nitrogen gas is used as a carrier gas in growing a first semiconductor layer and the second semiconductor layer.4. The method for producing a Group III nitride semiconductor device according to claim 1 , ...

Semiconductor Structure with Annealing

Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures. 1. A method , comprising:obtaining a substrate;epitaxially growing a nucleation layer on the substrate, the nucleation layer including a group III nitride semiconductor layer;{'b': '1', 'epitaxially growing a buffer layer directly on the nucleation layer, the buffer layer grown at a first temperature T;'}{'b': 2', '2', '1, 'annealing the epitaxially grown buffer layer and the nucleation layer at a second temperature T, wherein the second temperature T is greater than the first temperature T; and'}epitaxially growing an n-type doped semiconductor layer over the annealed buffer layer.2. A method of epitaxially growing a semiconductor structure with low dislocation density , comprising:obtaining a substrate;epitaxially growing a nucleation layer on the substrate, the nucleation layer including a group III nitride semiconductor layer;{'b': '1', 'epitaxially growing a buffer layer on the nucleation layer at a first temperature T, the buffer layer including a group III nitride semiconductor layer;'}epitaxially growing a desorption minimizing layer on the buffer layer;{'b': 2', '2', '1, 'annealing the nucleation layer, the buffer layer and the desorption minimizing layer at a second temperature T, wherein the ...

DIAMOND SUBSTRATE AND METHOD FOR MANUFACTURING DIAMOND SUBSTRATE

The crystal plane in the interior of the diamond substrate has a curvature higher than 0 kmand equal to or lower than 1500 kmby preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer. 1. A diamond substrate formed of diamond single crystals , wherein a crystal plane in an interior of the diamond substrate has a curvature , and the curvature is higher than 0 kmand equal to or lower than 1500 km.2. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 400 km.3. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 200 km.4. The diamond substrate according to claim 1 , wherein a shape of the diamond substrate in an in-plane direction has a circular shape or a circular shape having an orientation flat plane claim 1 , anda diameter of the diamond substrate is equal to or larger than 0.4 inches.5. The diamond substrate according to claim 4 , wherein the diameter is equal to or larger than 2 inches.6. The diamond substrate according to claim 4 , wherein the diameter is equal to or larger than 2 inches and equal to or smaller than 8 inches.7. The diamond substrate according to claim 1 , wherein the crystal plane has an (001) plane.8. The diamond substrate according to claim 1 , wherein a surface roughness Ra of a surface of the diamond substrate is lower than 1 nm.9. The diamond substrate according to claim 8 , wherein the surface roughness Ra is equal to or lower than 0.1 nm.10. The diamond substrate according to claim 1 , ...

EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlGaN layer to the junction between the i-GaN channel layer and the i-AlGaN layer. 1. An epitaxial structure of N-face AlGaN/GaN , comprising:a substrate;a buffer layer (C-doped) layer on the substrate;a carbon doped (C-doped) i-GaN layer on the buffer layer (C-doped);{'sub': 'y', 'an i-AlGaN layer, located on said C-doped i-GaN layer;'}{'sub': 'y', 'an i-GaN channel layer, located on said i-AlGaN layer;'}{'sub': 'x', 'an i-AlGaN layer, located on said i-GaN channel layer;'}{'sub': 'x', 'a fluorine-ion structure, located in said i-AlGaN layer; and'}a first gate dielectric layer, located on said fluorine-ion structure;where x=0.1˜0.3 and y=0.05˜0.75.2. The structure of claim 1 , wherein an i-AlGaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-AlGaN layer and z=0.01˜0.75.3. The structure of claim 1 , wherein the two-dimensional electron gas in said i-GaN channel layer is depleted below said fluorine-ion structure and the two-dimensional electron gas is located at the junction between said i-GaN channel layer and said i-AlGaN layer.4. A method for fabricating an enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using an epitaxial structure of N-face AlGaN/ ...

SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD OF FORMING THE SAME

Provided is a semiconductor epitaxial structure including a nucleation layer disposed on a substrate; a buffer layer disposed on the nucleation layer; a semiconductor layer disposed on the buffer layer; a barrier layer disposed on the semiconductor layer; and a cap layer disposed on the barrier layer. In a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the buffer layer to a thickness of the semiconductor layer is represented as following formula: Y=aX1−bX2+cX3, X1≥0 nm, X2≥750 nm, X3≥515 nm, wherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is a ratio of X3 to X2. 1. A semiconductor epitaxial structure , comprising:a substrate;a nucleation layer disposed on a substrate;a buffer layer disposed on the nucleation layer;a semiconductor layer disposed on the buffer layer;a barrier layer disposed on the semiconductor layer; and {'br': None, 'i': Y=aX', 'bX', 'cX', 'X', 'X', 'X, '1−2+3, 1≥0 nm, 2≥750 nm, 3≥515 nm,'}, 'a cap layer disposed on the barrier layer, wherein in a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the semiconductor layer to a thickness of the buffer layer is represented as a formula ofwherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is the ratio of the thickness of the semiconductor layer to the thickness of the buffer layer (X3/X2) and falls between the maximum value or the minimum value.2. The semiconductor epitaxial structure according to claim 1 , wherein the maximum value of the ratio of the thickness of the semiconductor layer to the thickness of the buffer ...

A Two-Dimensional AlN Material and its Preparation Method and Application

The present invention discloses a two-dimensional AlN material and its preparation method and application, wherein the preparation method comprises the following steps: (1) selecting a substrate and its crystal orientation; (2) cleaning the surface of the substrate; (3) transferring a graphene layer to the substrate layer; (4) annealing the substrate; (5) using the MOCVD process to introduce H 2 to open the graphene layer and passivate the surface of the substrate; and (6) using the MOCVD process to grow a two-dimensional AlN layer. The preparation method of the present invention has the advantages that the process is simple, time saving and efficient. Besides, the two-dimensional AlN material prepared by the present invention can be widely used in HEMT devices, deep ultraviolet detectors or deep ultraviolet LEDs, and other fields.

METHOD FOR MANUFACTURING A MONOCRYSTALLINE LAYER OF DIAMOND OR IRDIUM MATERIAL AND SUBSTRATE FOR EPITAXICALLY GROWING A MONOCRYSTALLINE LAYER OF DIAMOND OR IRIDIUM MATERIAL

A process for producing a monocrystalline layer of diamond or iridium material comprises transferring a monocrystalline seed layer of SrTiOmaterial onto a carrier substrate of silicon material, followed by epitaxial growth of the monocrystalline layer of diamond or iridium material. 1. A process for producing a monocrystalline layer of diamond material , comprising transferring a monocrystalline seed layer of SrTiOmaterial to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of diamond material.2. The process of claim 1 , wherein the monocrystalline seed layer has a thickness of less than 10 μm claim 1 , preferably less than 2 μm claim 1 , and more preferably less than 0.2 μm.3. The process of claim 1 , wherein the transfer of the monocrystalline seed layer of SrTiOmaterial to the carrier substrate of silicon material comprises joining a monocrystalline substrate of SrTiOmaterial to the carrier substrate followed by thinning the monocrystalline substrate of SrTiOmaterial.4. The process of claim 3 , wherein the thinning step comprises forming a weakened zone delimiting a portion of the monocrystalline substrate of SrTiOmaterial to be transferred to the carrier substrate of silicon material.5. The process of claim 4 , wherein forming the weakened zone comprises implanting atomic and/or ionic species into the monocrystalline substrate of SrTiOmaterial.6. The process of claim 1 , wherein thinning the monocrystalline substrate of SrTiOmaterial comprises detaching at the weakened zone so as to transfer the portion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate of silicon material.7. The process of claim 3 , wherein joining the monocrystalline substrate of SrTiOmaterial to the carrier substrate comprises molecular adhesion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate.8. The process of claim 1 , wherein the monocrystalline seed layer of SrTiOmaterial is in the form of a ...

MONOLITHIC INTEGRATED LATTICE MISMATCHED CRYSTAL TEMPLATE AND PREPARATION METHOD THEREOF

The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template layer is fully relaxed. Compared to the prior art, the invention has advantages of simple preparation, achieving in various lattice constant material combinations on one substrate and low dislocation density, high crystal quality. 1. A monolithic integrated lattice mismatched crystal template by using low-viscosity material , characterized in that , includes:a first crystal layer having a first lattice constant;a buffer layer located on the first crystal layer, the buffer layer melting and converting to an amorphous state above its melting point;a template layer located on the buffer layer and having a second lattice constant, which differs from the first lattice constant of the first crystal layer; the lattice of the template layer being fully relaxed in the growth at a temperature above the glass transition temperature of the buffer layer.2. The crystal template according to claim 1 , characterized in that claim 1 , further includes:a second crystal layer located ...

METHOD OF MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE, AND BULK CRYSTAL

There is provided a method of manufacturing a group III nitride semiconductor substrate including: a fixing step S of fixing a base substrate, which includes a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor; a first growth step S of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using an HVPE method; a cooling step S of cooling a laminate including the susceptor, the base substrate, and the first growth layer; and a second growth step S of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method. 1. A method of manufacturing a group III nitride semiconductor substrate , comprising:a fixing step of fixing a base substrate, which comprises a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor;a first growth step of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using a hydride vapor phase epitaxy (HVPE) method;a cooling step of cooling a laminate comprising the susceptor, the base substrate, and the first growth layer after the first growth step; anda second growth step of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method after the cooling step.2. The method of manufacturing a group III nitride semiconductor substrate according to claim 1 , further comprising:a separation step of separating a group III nitride semiconductor substrate having at least one of the first growth layer or the second ...

METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER AND SEMICONDUCTOR EPITAXIAL WAFER

A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided. 111-. (canceled)12. A method for producing a semiconductor epitaxial wafer , comprising:fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate;observing an outer edge portion of the fabricated epitaxial wafer; andremoving portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present.13. The method for producing a semiconductor epitaxial wafer according to claim 12 , whereinin the step of removing, the portions in which the crack, the epitaxial layer peeling, and the reaction mark are present are ground without change in an outside diameter of the silicon-based substrate of the epitaxial wafer.14. The method for producing a semiconductor epitaxial wafer according to claim 13 , whereinafter the step of removing, a ground surface of the epitaxial wafer is turned into a mirror surface or a quasi-mirror surface by mixed acid etching.15. The method for producing a semiconductor epitaxial wafer according to claim 14 , whereinan overhang portion of the epitaxial layer, the overhang portion formed as a result of the silicon-based substrate being etched by the mixed acid etching, is removed by chamfering.16. The method for producing a semiconductor epitaxial wafer according to claim 12 , whereinthe semiconductor layer is composed of a nitride semiconductor.17. The method for producing a semiconductor epitaxial wafer according to claim 13 , ...

APPARATUS FOR MANUFACTURING A SECOND SUBSTRATE ON A FIRST SUBSTRATE INCLUDING REMOVAL OF THE FIRST SUBSTRATE

An apparatus includes a deposition chamber housing that accommodates a growth substrate, a supply nozzle to supply a deposition gas for forming a target large-size substrate on the growth substrate into the deposition chamber housing, a susceptor to support the growth substrate and expose a rear surface of the growth substrate to an etch gas, and an inner liner connected to the susceptor. The inner liner is to isolate the etch gas from the deposition gas and guide the etch gas toward the rear surface of the growth substrate. The susceptor includes a center hole that exposes the rear surface of the growth substrate and a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole. 1. An apparatus for manufacturing a substrate , the apparatus comprising:a deposition chamber housing that accommodates a growth substrate;a first supply to supply a deposition gas for forming a target substrate on the growth substrate into the deposition chamber housing;a susceptor to support the growth substrate and exposing a rear surface of the growth substrate;an inner liner connected to the susceptor; anda second supply to supply an etch gas to the rear surface of the growth substrate,wherein the inner liner is to isolate the etch gas from the deposition gas and guide the etch gas towards the rear surface of the growth substrate, a center hole to expose the rear surface of the growth substrate, and', 'a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole., 'wherein the susceptor includes'}2. The apparatus as claimed in claim 1 , wherein the support protrusion protrudes from the inner sidewall and extends along a circumference of the inner sidewall.3. The apparatus as claimed in claim 1 , wherein the support protrusion ...

METHODS OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS AND DEVICES THEREON

A method is disclosed for making sapphire glass, consisting of a layer of sapphire on glass. The sapphire layer, or crystalline AlO, is deposited on ordinary (soda-lime) glass via a textured MgO template. 1. A method of producing sapphire on glass , comprising:depositing an MgO film on glass; and{'sub': 2', '3, 'depositing AlOon said MgO film.'}2. The method of claim 1 , wherein said MgO film is crystalline.3. The method of claim 1 , wherein said AlOfilm is crystalline sapphire.4. The method of claim 1 , wherein said MgO film is deposited below about 600° C.5. The method of claim 1 , wherein the AlOfilm is single crystalline sapphire.6. The method of claim 1 , wherein said AlOis deposited below about 600° C.7. The method of claim 1 , wherein said glass is soda-lime.8. The method of claim 1 , wherein said glass is borosilicate.9. A method of depositing single crystalline semiconductors on sapphire glass below the softening temperature of ordinary glass.10. The method of claim 8 , wherein the semiconductor comprises Si claim 8 , Ge claim 8 , Ga claim 8 , or GaAs.11. The method of claim 8 , wherein said sapphire glass is a single crystalline sapphire substrate.12. The method of claim 8 , wherein said semiconductors are large grained.13. The method of where said sapphire glass is crystalline AlOnot single crystalline. U.S. Pat. No. 4,717,688 January 1987 Jaentsch . . . 148/171U.S. Pat. No. 5,326,719 July 1994 Green et al. . . . 427/74U.S. Pat. No. 5,544,616 August 1996 Ciszek et al. . . . 117/60U.S. Pat. No. 6,429,035 B2 August 2002 Nakagawa et al. . . . 438/57U.S. Pat. No. 6,784,139 B1 August 2004 Sankar et al. . . . 505/230Kass et al, Liquid Phase Epitaxy of Silicon: Potentialialities and Prospects“, Physica B, Vol 129, 161 (1985)Massalski et al, “Binary Alloy Phase Diagrams”, 2edition, (1990), ASM InternationalFindikoglu et al, “Well-oriented Silicon Thin Films with High Carrier Mobility on Polycrystalline Substrates”, Adv. Materials, Vol 17, 1527, (2005)Teplin et al ...

Electro-Optical Device, Manufacturing Method for Electro-Optical Device, and Electronic Apparatus

An electro-optical device includes a substrate, a mirror support pillar extending in a direction in which the pillar intersects with a surface of the substrate, and a mirror that is so disposed as to be distanced from the substrate and to be capable of being displaced with respect to the mirror support pillar. The mirror has a reflective metal film, and a reflection enhancing lamination film that covers a portion including a surface and a side surface of the reflective metal film. 1. An electro-optical device comprising:a substrate;a mirror that includes a reflective metal film and is disposed above one surface of the substrate so as to be distanced from the substrate;a support section that is disposed between the substrate and the mirror, the support section has a portion connected to part of the mirror to support the mirror; anda reflection enhancing lamination film that is disposed so as to cover at least a part of a surface of the mirror on an opposite side to the substrate and a side surface of the mirror.2. The electro-optical device according to claim 1 ,wherein the reflection enhancing lamination film includes a first oxide film and a second oxide film, the second oxide film having a larger refractive index than the first oxide film and disposed on a side of the first oxide film opposite to the reflective metal film.3. The electro-optical device according to claim 2 ,wherein the first oxide film is silicon oxide, andthe second oxide film is silicon nitride.4. The electro-optical device according to claim 1 ,wherein the reflective metal film is made of aluminum.5. The electro-optical device according to claim 1 ,wherein the mirror includes, between the reflective metal film and the substrate, a seed lamination film for aligning crystal plane orientations.6. The electro-optical device according to claim 5 ,wherein the seed lamination film is a lamination film including a titanium nitride layer which is disposed between the reflective metal film and the ...

GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE

There is provided a group III nitride semiconductor substrate (free-standing substrate ()) that is formed of a group III nitride semiconductor crystal and has a thickness of 300 μm or more and 1000 μm or less. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A difference in a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on each of the first and second main surfaces in parallel to an m axis of the group III nitride semiconductor crystal is 500 arcsec or less. 1. A group III nitride semiconductor substrate that is formed of a group III nitride semiconductor crystal and has a thickness of 300 μm or more and 1000 μm or less , wherein both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes , and a difference between half widths of an X-ray rocking curve (XRC) measured by making X-rays incident on each of the first and second main surfaces in parallel to an m axis of the group III nitride semiconductor crystal is 500 arcsec or less.2. The group III nitride semiconductor substrate according to claim 1 ,wherein the difference between the half widths of the XRC measured by making X-rays incident on each of the first and second main surfaces in parallel to the m axis of the group III nitride semiconductor crystal is 300 arcsec or less.3. The group III nitride semiconductor substrate according to or claim 1 ,wherein for both the first and second main surfaces both, the half width of the XRC measured by making X-rays incident in parallel to the m axis of the group III nitride semiconductor crystal is 500 arcsec or less.4. The group III nitride semiconductor substrate according to any one of to claim 1 ,wherein the difference between the half widths of the XRC measured by making X-rays incident on each of the first and second main surfaces in parallel to a projection axis of a c axis of the group III nitride semiconductor crystal is 500 arcsec or ...

NITRIDE SEMICONDUCTOR TEMPLATE AND METHOD FOR MANUFACTURING SAME

A nitride semiconductor template includes a GaOsubstrate, a buffer layer formed on the GaOsubstrate and including AlN as a principal component, a first nitride semiconductor layer formed on the buffer layer and including AlGaN (0.2 Подробнее

Method for producing a single-crystal film of aln material and substrate for the epitaxial growth of a single-crystal film of aln material

A process for producing a monocrystalline layer of AlN material comprises the transfer of a monocrystalline seed layer of SiC- 6 H material to a carrier substrate of silicon material, followed by the epitaxial growth of the monocrystalline layer of AlN material.

NUCLEATION LAYER DEPOSITION METHOD

A nucleation layer comprised of group III and V elements is directly deposited onto the surface of a substrate made of a group IV element. Together with a first gaseous starting material containing a group III element, a second gaseous starting material containing a group V element is introduced at a process temperature of greater than 500° C. into a process chamber containing the substrate. It is essential that at least at the start of the deposition process of the nucleation layer, a third gaseous starting material containing a group IV element is fed into the process chamber, together with the first and second gaseous starting material. The third gaseous starting material develops an n-doping effect in the deposited III-V crystal, which causes a decrease in damping at a dopant concentration of less than 1×10cm. 1321. A method for depositing a nucleation layer () comprised of group III and V elements directly onto a surface () of a substrate () made of a group IV element , the method comprising:{'b': ['8', '1'], '#text': 'introducing a first gaseous starting material containing a group III element together with a second gaseous starting material containing a group V element into a process chamber () containing the substrate () at a process temperature greater than 500° C.;'}{'b': ['3', '8'], '#text': 'at least at a start of the deposition of the nucleation layer (), feeding a third gaseous starting material containing a group IV element into the process chamber () together with the first and second gaseous starting materials; and'}{'b': ['4', '3', '6', '4', '5', '6', '4'], '#text': 'depositing a buffer layer () on the nucleation layer () and depositing an active layer () on the buffer layer () in such manner that a two-dimensional electron gas develops on a boundary surface () between the active layer () and the buffer layer (),'}{'b': '8', 'sup': ['17', '18', '−3'], '#text': 'wherein a partial pressure and/or mass flow of the third gaseous starting material in ...

Buffer layer for Gallium Nitride-on-Silicon epitaxy

Embodiments generally relate to multi-layer buffer structures on silicon. One method for forming such a structure comprises: providing a (111) silicon substrate; using ALD to deposit a first layer of AlN on the substrate; using first and second precursor materials at a first V-III ratio to deposit a plurality of AlN islands forming a second layer on the first layer; using the first and second precursor materials at a second V-III ratio, to deposit a third layer of AlN overlying and in contact with the islands and the first layer between the islands, forming domains; and using the first and second precursor materials at a third V-III ratio, to deposit a fourth layer of AlN on the third layer. All depositions occur at one predetermined temperature range. The fourth layer is characterized by a fourth layer top surface that is anatomically smooth. 1. A method for forming a multi-layer AlN buffer structure on silicon , the method comprising:providing a (111) oriented silicon substrate having a top surface;using atomic layer deposition to deposit, at a predetermined temperature range, a first layer of AlN on the top surface;using first and second precursor materials, characterized by a first V-III ratio, to deposit, at the predetermined temperature range, a plurality of AlN islands forming a second layer overlying and in contact with the first layer;using the first and second precursor materials, characterized by a second V-III ratio, to deposit, at the predetermined temperature range, a third layer of AlN, the third layer overlying and in contact with the islands and the first layer between the islands, forming domains; andusing the first and second precursor materials, characterized by a third V-III ratio, to deposit, at the predetermined temperature range, a fourth layer of AlN, the fourth layer overlying and in contact with the third layer, wherein the fourth layer is characterized by a fourth layer top surface that is anatomically smooth.2. The method of claim 1 , ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer. 1. A method for manufacturing a semiconductor component , comprising:providing a semiconductor material having a surface;forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface;forming a nucleation layer on the epitaxial layer; andforming a layer of III-nitride material on the nucleation layer.2. The method of claim 1 , wherein forming the epitaxial layer comprises epitaxially growing carbon doped silicon as the epitaxial layer claim 1 , wherein the epitaxially grown carbon doped silicon comprises substitutional carbon.3. The method of claim 2 , wherein forming the epitaxial layer comprises epitaxially growing carbon doped silicon having a 100% substitutional carbon concentration.4. The method of claim 1 , wherein forming the epitaxial layer comprises epitaxially growing carbon doped silicon having a carbon concentration ranging from 0.01% to 49.99%.5. The method of claim 1 , wherein forming the epitaxial layer of carbon doped semiconductor material on the semiconductor substrate includes doping with epitaxial layer with carbon having a graded concentration profile.6. The method of claim 5 , wherein the graded concentration profile of the carbon extends a first distance into the epitaxial layer ...

SEED WAFER FOR GaN THICKENING USING GAS- OR LIQUID-PHASE EPITAXY

Embodiments relate to fabricating a wafer including a thin, high-quality single crystal GaN layer serving as a template for formation of additional GaN material. A bulk ingot of GaN material is subjected to implantation to form a subsurface cleave region. The implanted bulk material is bonded to a substrate having lattice and/or Coefficient of Thermal Expansion (CTE) properties compatible with GaN. Examples of such substrate materials can include but are not limited to AlN and Mullite. The GaN seed layer is transferred by a controlled cleaving process from the implanted bulk material to the substrate surface. The resulting combination of the substrate and the GaN seed layer, can form a template for subsequent growth of overlying high quality GaN. Growth of high-quality GaN can take place utilizing techniques such as Liquid Phase Epitaxy (LPE) or gas phase epitaxy, e.g., Metallo-Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE). 1. A method comprising:providing a substrate bearing a bonding layer;transferring a layer of additional material to the bonding layer utilizing a first cleave process; andforming GaN over the layer of additional material.2. A method as in further comprising forming a precursor layer over the layer of additional material.3. A method as in further comprising depositing a GaN seed layer on the precursor layer prior to performing an epitaxial growth technique.4. A method as in wherein the depositing comprises performing Metallo-Organic Chemical Vapor Deposition (MOCVD).5. A method as in wherein the precursor layer comprises AlN.6. A method as in wherein the AlN comprises single-crystal AlN.7. A method as in wherein forming the GaN comprises performing an epitaxial growth technique.8. A method as in wherein the epitaxial growth technique comprises Liquid Phase Epitaxy (LPE).9. A method as in wherein the epitaxial growth technique comprises Hydride Vapor Phase Epitaxy (HVPE).10. A method as in wherein the additional ...

Method of Growing High Quality, Thick SiC Epitaxial Films by Eliminating Silicon Gas Phase Nucleation and Suppressing Parasitic Deposition

Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms. 1. A method of forming an epilayer on a surface of a substrate , the method comprising:positioning a silicon carbide seed substrate within a hot wall chemical vapor deposition (CVD) chamber,introducing one or more source gases into the hot wall CVD chamber to provide fluorine, carbon, and silicon to the hot wall CVD chamber, each of the source gases comprising one or more of fluorine, carbon, and silicon;heating the hot wall CVD chamber to a growth temperature of about 1400° C. to about 2000° C., silicon-fluorine bonds forming at the growth temperature, the silicon-fluorine bond formation inhibiting formation of silicon-silicon bonds in the heated hot wall CVD chamber, the heated hot wall CVD chamber atmosphere including Si—Si vapor in an amount that is less than 5% by volume;growing a homeoepitaxial film on the silicon carbide seed substrate at the growth temperature, the homeoepitaxial film comprising a silicon carbide crystal comprising silicon and carbon in the crystal at a 1:1 stoichiometric ratio.2. The method of claim 1 , wherein one or more of the source gases comprises SiHFwhere x=1 claim 1 , 2 claim 1 , or 3; and y=4−x.3. The method of claim 1 , wherein one or more of the source gases comprises CHFwhere x=0 claim 1 , 1 claim 1 , 2 claim 1 , or 3; and y=4−x.4. The method of claim 1 , wherein one of the source gases is HF.5. The method of claim 1 , wherein one or more of the source gases comprises both fluorine and silicon.6. The method of claim 1 , ...

Semiconductor Material Having a Compositionally-Graded Transition Layer

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. 115-. (canceled)16. A semiconductor material , comprising:a compositionally-graded transition layer having a back surface and a top surface, the compositionally-graded transition layer comprising a gallium nitride alloy, wherein a gallium concentration in the compositionally-graded transition layer increases from the back surface to the front surface;an intermediate layer formed under the compositionally-graded transition layer; and{'sup': '2', 'a gallium nitride material layer formed over the compositionally-graded transition layer, the gallium nitride material layer having a crack level of less than 0.005 μm/μm.'}17. The semiconductor material of claim 16 , wherein the composition of the compositionally-graded transition layer is graded continuously across the thickness of the transition layer.18. The semiconductor material of claim 16 , wherein the composition of the compositionally-graded transition layer is graded discontinuously across the thickness of the transition layer.19. The semiconductor material of claim 16 , wherein the compositionally-graded transition layer comprises an alloy of gallium nitride selected from ...

Method for Producing a Semiconductor Layer Sequence

A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate.

LAYERED SUBSTRATE WITH A MISCUT ANGLE COMPRISING A SILICON SINGLE CRYSTAL SUBSTRATE AND A GROUP-III NITRIDE SINGLE CRYSTAL LAYER

A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved. 122-. (canceled)23. A layered substrate comprising a silicon single crystal substrate and a wurtzite group-III nitride single crystal layer , when:an axis orthogonal to a normal line on a surface of the silicon single crystal substrate and overlapping a <11-2> axis of the silicon single crystal when observed from the direction of the normal line is a y-axis;an axis orthogonal to the normal line and the y-axis and configuring three orthogonal axes is an x-axis;a plane including the normal line and the y-axis is an ny-plane;a plane including the normal line and the x-axis is an nx-plane;an axis wherein a <111> axis of the silicon single crystal is projected onto the ny-plane is a <111>ny axis;an axis wherein the <111> axis is projected onto the nx-plane is a <111>nx axis;an axis wherein a <0001> axis of the group-III nitride single crystal is projected onto the ny-plane is a <0001>ny axis;an axis wherein the <0001> axis is projected onto the nx-plane is a <0001>nx axis;a rotation angle measured in the ny-plane from the normal line to the <111>ny axis is θx0;a rotation angle measured in the nx-plane from the normal line to the <111>nx axis is θy0;a rotation angle measured in the ny plane from the normal line to the <0001>ny axis is θx1; anda ...

METHOD FOR MANUFACTURING A MONOCRYSTALLINE LAYER OF GAAS MATERIAL AND SUBSTRATE FOR EPITAXIAL GROWTH OF A MONOCRYSTALLINE LAYER OF GAAS MATERIAL

A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiOmaterial to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material. 1. A process for producing a monocrystalline layer of GaAs material , comprising: transferring a monocrystalline seed layer of SrTiOmaterial to a carrier substrate of silicon material , followed by epitaxial growth of the monocrystalline layer of GaAs material.2. The process of claim 1 , wherein the monocrystalline seed layer has a thickness of less than 10 μm.3. The process of claim 2 , wherein the transfer of the monocrystalline seed layer of SrTiOmaterial to the carrier substrate of silicon material comprises joining a monocrystalline substrate of SrTiOmaterial to the carrier substrate claim 2 , followed thinning the monocrystalline substrate of SrTiOmaterial.4. The process of claim 3 , wherein the thinning of the monocrystalline substrate of SrTiOmaterial comprises forming a weakened zone delimiting a portion of the monocrystalline substrate of SrTiOmaterial to be transferred to the carrier substrate of silicon material.5. The process of claim 4 , wherein the formation of the weakened zone comprises implanting atomic and/or ionic species into the monocrystalline substrate of SrTiOmaterial.6. The process of claim 4 , wherein the thinning of the monocrystalline substrate of SrTiOmaterial comprises detaching at the weakened zone so as to transfer the portion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate of silicon material.7. The process of claim 3 , wherein the joining of the monocrystalline substrate of SrTiOmaterial to the carrier substrate comprises molecular adhesion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate.8. The process of claim 1 , wherein the monocrystalline seed layer of SrTiOmaterial is in a form of a plurality of tiles each transferred to the ...

METHOD FOR THE PRODUCTION OF A NITRIDE COMPOUND SEMICONDUCTOR LAYER

Described is a method for producing a nitride compound semiconductor layer, involving the steps of:—depositing a first seed layer () comprising a nitride compound semiconductor material on a substrate ();—desorbing at least some of the nitride compound semiconductor material in the first seed layer from the substrate ();—depositing a second seed layer () comprising a nitride compound semiconductor material; and—growing the nitride compound semiconductor layer () containing a nitride compound semiconductor material onto the second seed layer (). 1. Method for the production of a nitride compound semiconductor layer , comprising the steps:{'b': '1', 'deposition of a first seed layer () comprising a nitride compound semiconductor material onto a substrate,'}at least partial desorption of the nitride compound semiconductor material of the first seed layer from the substrate,{'b': '2', 'deposition of a second seed layer () comprising a nitride compound semiconductor material, and'}{'b': 3', '2, 'growth of the nitride compound semiconductor layer () comprising a nitride compound semiconductor material onto the second seed layer ().'}2. Method according to claim 1 , wherein the substrate is a sapphire substrate.3. Method according to claim 1 , wherein the substrate is a prepatterned substrate.4. Method according to claim 1 , wherein the nitride compound semiconductor material of the first seed layer comprises AlInGaN with 0≦x≦1 claim 1 , 0≦y≦1 and x+y≦1.52. Method according to claim lone of the preceding claims claim 1 , wherein the nitride-compound semiconductor material of the second seed layer () comprises AlInGaN with 0≦x≦1 claim 1 , 0≦y≦1 and x+y≦1.63. Method according to claim 1 , wherein the nitride compound semiconductor material of the nitride compound semiconductor layer () comprises AlInGaN with 0≦x≦1 claim 1 , 0≦y≦1 and x+y≦1.7. Method according to claim 1 , wherein deposition of the first seed layer claim 1 , the second seed layer and/or the nitride compound ...

METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE AND NITRIDE SEMICONDUCTOR SUBSTRATE

A method for manufacturing a nitride semiconductor substrate by using a vapor phase growth method includes: a step of preparing a base substrate that is constituted by a material different from a single crystal of a group III nitride semiconductor; a step of growing a base layer on the upper side of the base substrate; a first step of growing a first layer by epitaxially growing a single crystal of a group III nitride semiconductor directly on the base surface of the base layer, the single crystal of the group III nitride semiconductor having a top surface at which a (0001) plane is exposed, and a plurality of recessed portions formed by inclined interfaces other than the (0001) plane being generated in the top surface; and a second step of growing a second layer that has a mirror-finished surface. 1. A method for manufacturing a nitride semiconductor substrate by using a vapor phase growth method , comprising:a step of preparing a base substrate that is constituted by a material different from a single crystal of a group III nitride semiconductor;a step of growing a base layer that has a mirror-finished base surface and in which a low index crystal plane closest to the base surface is a (0001) plane, by epitaxially growing a single crystal of a group III nitride semiconductor on the upper side of the base substrate;a first step of growing a first layer by epitaxially growing a single crystal of a group III nitride semiconductor directly on the base surface of the base layer, the single crystal of the group III nitride semiconductor having a top surface at which a (0001) plane is exposed, a plurality of recessed portions formed by inclined interfaces other than the (0001) plane being generated in the top surface, the inclined interfaces being gradually expanded toward an upper side of the base surface of the base layer to make the (0001) plane disappear from the top surface, and a surface of the first layer being constituted only by the inclined interfaces; anda ...

Method for producing crystalline film

According to an aspect of a present inventive subject matter, a method for producing a crystalline film includes; gasifying a metal source containing a metal to turn the metal source into a metal-containing raw-material gas; supplying the metal-containing raw-material gas and an oxygen-containing raw-material gas into a reaction chamber onto a substrate including a buffer layer; and supplying a reactive gas into the reaction chamber onto the substrate to form a crystalline film on the substrate under a gas flow of the reactive gas.

Elimination of Basal Plane Dislocation and Pinning the Conversion Point Below the Epilayer Interface for SiC Power Device Applications

Methods are provided for growing basal plane dislocation (BPD)-free SiC device-ready epilayers, particularly suitable for 4H-SiC devices. The devices are formed via a substantially 100% conversion of BPDs to threading edge dislocations (TEDs) while pinning the conversion point below the epilayer interface. Methods include the formation of a recombination layer on a previously formed and etched buffer layer. Devices allow for improved reliability and efficiency of high voltage switches used in the day-to-day applications such as inverters, uninterrupted power supplies, and other high power handling devices employed in hybrid electric vehicles, aircraft electronic systems, etc. by enabling the manufacture of smaller, lighter, and more efficient, high power SiC devices in a cost effective, reliable platform. 1. A method of growing a composite SiC epilayer structure , the method comprising:growing a buffer layer on a surface of a SiC substrate, wherein the buffer layer comprises SiC;applying a molten mixture directly onto the buffer layer to form a treated buffer layer; andthereafter, growing a recombination layer on the treated buffer layer, wherein the recombination layer comprises SiC.2. The method of claim 1 , wherein the buffer layer is n-doped.3. The method of claim 1 , wherein the buffer layer has a dopant concentration of about 1×10cmor less.4. The method of claim 1 , wherein the buffer layer has a thickness of about 0.5 μm to about 5 μm.5. The method of claim 1 , wherein the application of the molten mixture converts basal plane dislocations present on the buffer layer to threading edge dislocations.6. The method of claim 1 , wherein the recombination layer is n-doped.7. The method of claim 3 , wherein the recombination layer has a dopant concentration that is greater than the dopant concentration of the buffer layer.8. The method of claim 4 , wherein the recombination layer has a thickness that is greater than a thickness of the buffer layer.9. The method of ...

METHOD FOR GROWING EPITAXIAL DIAMOND

A method for growing epitaxial diamond is provided here. A metallic layer is deposited on a diamond substrate and is followed by an epitaxial diamond film deposited on top of the metallic layer. As a buffer layer, the metallic layer relieves stress accumulated in the thin film of the epitaxial diamond to prevent cracks. In consequence, diamond epitaxial layers with desired thickness and good quality can be obtained. 1. A method for growing epitaxial diamond comprising:providing a diamond substrate;depositing at least a metallic layer on the diamond substrate, wherein a metal composition of the metallic layer has at least one of the following features that lattice mismatch between the metal composition and diamond is less than 15% and dissolution rate of carbon in the metal composition is less than 2 wt %;providing a reaction atmosphere; anddepositing an epitaxial diamond layer on the diamond substrate and the metallic layer.2. The method for growing epitaxial diamond according to claim 1 , wherein the diamond substrate is a single crystal diamond claim 1 , a polycrystalline diamond claim 1 , a homoepitaxial diamond film or a hetepitaxial diamond film.3. The method for growing epitaxial diamond according to claim 1 , wherein the metallic layer is a non-continuous film.4. The method for growing epitaxial diamond according to claim 1 , wherein the method to deposit the metallic layer on the diamond substrate is using evaporation deposition claim 1 , sputtering claim 1 , molecular beam epitaxy (MBE) growth method claim 1 , atmospheric pressure chemical vapor deposition claim 1 , low-pressure chemical vapor deposition claim 1 , plasma enhanced chemical vapor deposition claim 1 , spin coating method or chemical synthesis method.5. The method for growing epitaxial diamond according to claim 1 , wherein the metal composition of the metallic layer is selected from gold claim 1 , silver claim 1 , copper claim 1 , platinum claim 1 , iridium claim 1 , nickel claim 1 , cobalt ...

CRYSTAL, CRYSTALLINE FILM, SEMICONDUCTOR DEVICE INCLUDING CRYSTALLINE FILM, AND METHOD FOR PRODUCING CRYSTALLINE FILM

According to an aspect of a present inventive subject matter, a crystal includes: a corundum-structured oxide semiconductor as a major component, the corundum-structured oxide semiconductor including gallium and/or indium and doped with a dopant including germanium; a principal plane; a carrier concentration that is 1×10/cmor more; and an electron mobility that is 20 cm/Vs or more. 1. A crystal comprising:a corundum-structured oxide semiconductor as a major component, the corundum-structured oxide semiconductor comprising gallium and/or indium and doped with a dopant comprising germanium;a principal plane;{'sup': 18', '3, 'a carrier concentration that is 1×10/cmor more; and'}{'sup': '2', 'an electron mobility that is 20 cm/Vs or more.'}2. The crystal of claim 1 , whereinthe principal plane of the crystal is a c-plane.3. The crystal of claim 1 , whereinthe principal plane of the crystal is an m-plane.4. The crystal of claim 1 , whereinthe principal plane of the crystal comprises an off-angle.5. The crystal of claim 1 , whereinthe corundum-structured oxide semiconductor comprises a mixed crystal comprising gallium and one or more metals selected from among aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.6. The crystal of claim 1 , whereinthe crystal has a film shape as a crystalline film.7. The crystal of claim 5 , wherein the mixed crystal comprised in the corundum-structured oxide semiconductor comprises aluminum that is 1×10/cmor more.8. A crystalline film comprising:{'sup': 17', '3, 'an oxide semiconductor as a major component, the oxide semiconductor comprising aluminum that is 1×10/cmor more;'}{'sup': 18', '3, 'a carrier concentration that is 1×10/cmor more; and'}{'sup': '2', 'an electron mobility that is 20 cm/Vs or more.'}9. The crystalline film of claim 8 , whereinthe oxide semiconductor comprises gallium.10. The crystalline film of claim 8 , whereinthe oxide semiconductor comprises a mixed crystal.11. A ...

Improved Superconductor Compositions

A superconductor tape may be fabricated via Metal Organic Chemical Vapor Deposition (MOCVD) to achieve peel strengths greater than approximately 4.5 N/cm. The superconductor tape may be fabricated via MOCVD with a REBCO composition that includes the elements Samarium (Sm)-Barium(Ba)-Copper(Cu)-Oxygen(O). Varying levels of Copper (Cu) content can achieve peel strengths ranging between approximately 4.5 N/cm to approximately 8.0 N/cm. 1. A superconductor tape comprising:a substrate;a buffer layer overlying the substrate; anda superconductor layer overlying the buffer layer, wherein the superconductor tape exhibits a peel strength greater than 4.5 N/cm.2. The superconductor tape of claim 1 , wherein the superconductor layer comprises Samarium (Sm) claim 1 , Barium (Ba) claim 1 , Copper (Cu) claim 1 , and Oxygen (O).3. The superconductor tape of claim 2 , wherein the composition of the precursors of the cation elements is SmBaCuO claim 2 , where x is from approximately 2.3 to approximately 2.6 claim 2 , and z is from approximately 0 to approximately 1.4. The superconductor tape of claim 3 , wherein the superconductor tape further comprises at least one dopant transition metal (M).5. The superconductor tape of claim 4 , wherein the dopant transition metal consists of at least one of Zirconium (Zr) claim 4 , Tantalum (Ta) claim 4 , Tin (Sn) claim 4 , Hafnium (Hf) and Niobium (Nb).6. The superconductor tape of claim 5 , wherein the composition of the precursors of the cation elements is SmBaCuO:M claim 5 , where x is from approximately 2.3 to approximately 2.6 claim 5 , y is from approximately 0.05 to approximately 0.30 claim 5 , and z is from approximately 0 to approximately 1.7. A superconductor coil claim 1 , comprising the superconductor tape of .8. A superconductor tape comprising:a substrate;a buffer layer overlying the substrate;a superconductor layer overlying the buffer layer;a silver overlayer above the superconductor layer; andwherein the superconductor tape ...

Vertical semiconductor diode manufactured with an engineered substrate

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

NITRIDE SEMICONDUCTOR SINGLE CRYSTAL SUBSTRATE MANUFACTURING METHOD

A nitride semiconductor single crystal substrate manufacturing method includes providing a template that a first nitride semiconductor single crystal layer is hetero-epitaxially grown on a heterogeneous substrate, forming a plurality of linear grooves on a surface of the template that have a depth reaching an inside of the heterogeneous substrate, wherein a pattern of the plurality of the linear grooves has three-fold or six-fold rotational symmetry with respect to a central axis of the template, epitaxially growing a second nitride semiconductor single crystal layer on the template with the plurality of the linear grooves formed thereon, and cutting a nitride semiconductor single crystal substrate from the second nitride semiconductor single crystal layer. 1. A nitride semiconductor single crystal substrate manufacturing method , comprising:providing a template that a first nitride semiconductor single crystal layer is hetero-epitaxially grown on a heterogeneous substrate;forming a plurality of linear grooves on a surface of the template that have a depth reaching an inside of the heterogeneous substrate, wherein a pattern of the plurality of the linear grooves has three-fold or six-fold rotational symmetry with respect to a central axis of the template;epitaxially growing a second nitride semiconductor single crystal layer on the template with the plurality of the linear grooves formed thereon; andcutting a nitride semiconductor single crystal substrate from the second nitride semiconductor single crystal layer.2. The method according to claim 1 , wherein the first nitride semiconductor single crystal layer is an AlGaN (0≦X≦1) crystal grown by MOCVD method or HYPE method.3. The method according to claim 1 , wherein the second nitride semiconductor single crystal layer is an AlGaN (0≦Y≦1) crystal grown by HVPE method.4. The method according to claim 1 , wherein the first nitride semiconductor single crystal layer and the second nitride semiconductor single crystal ...

METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE

To provide a method for producing a Group III nitride semiconductor light-emitting device, which allows the formation of a high-temperature AlN buffer layer on an uneven substrate. This production method comprises forming an Al layer or Al droplets on the uneven shape of the uneven substrate, forming an AlN buffer layer while nitriding the Al layer; and forming a Group III nitride semiconductor layer on the AlN buffer layer. In the forming an Al layer, the internal pressure of a furnace is 1 kPa to 19 kPa, the temperature of the uneven substrate is 900° C. to 1,500° C., and an organic metal gas containing Al is supplied at a flow rate of 1.5×10mol/min or more. 1. A method for producing a Group III nitride semiconductor light-emitting device comprising:forming an Al layer or Al droplets on a surface of a substrate, the surface having an uneven shape comprising concaves and convexes, by flowing an organic metal gas containing Al without flowing an ammonia gas;forming an AlN buffer layer while nitriding the Al layer or the Al droplets by flowing the organic metal gas containing Al and the ammonia gas; andforming a Group III nitride semiconductor layer on the AlN buffer layer;wherein in the forming the Al layer or the Al droplets, the internal pressure of a furnace is set at any value in a range from 1 kPa to 19 kPa, the temperature of the substrate is set at any value in a range from 900° C. to 1,500° C., and an organic metal gas containing Al is supplied at a flow rate such that Al atoms are uniformly deposited on an entire surface of the substrate.2. The method for producing a Group III nitride semiconductor light-emitting device according to claim 1 , wherein in the forming the AlN buffer layer claim 1 , the internal pressure of a furnace claim 1 , the temperature of the substrate and the flow rate of the organic metal gas containing Al are kept at the same values as when the Al layer or the Al droplets is formed.3. The method for producing a Group III nitride ...

METHOD FOR MANUFACTURING A SINGLE CRYSTAL DIAMOND

A method for manufacturing a single crystal diamond in which vapor phase synthetic single crystal diamond is additionally deposited on a single crystal diamond seed substrate obtained by vapor phase synthesis, includes a step of measuring flatness of the seed substrate, a step of determining whether or not to flatten the seed substrate based on the measurement result of the flatness, and any one of the following two steps of a step of additionally depositing the vapor phase synthetic single crystal diamond after flattening the seed substrate for which the flattening is necessary based on the determination and a step of additionally depositing the vapor phase synthetic single crystal diamond without flattening the seed substrate for which the flattening is not necessary based on the determination. 1. A method for manufacturing a single crystal diamond in which a single crystal diamond seed substrate obtained by vapor phase synthesis is placed on a stage and vapor phase synthetic single crystal diamond is additionally deposited thereon , the method comprising:(1) a step of measuring flatness of the single crystal diamond seed substrate prior to additional deposition of the vapor phase synthetic single crystal diamond;(2) a step of determining whether or not to flatten the single crystal diamond seed substrate based on the measurement result of the flatness; and (3a) a step of additionally depositing the vapor phase synthetic single crystal diamond after flattening the single crystal diamond seed substrate for which the flattening is necessary based on the determination; and', '(3b) a step of additionally depositing the vapor phase synthetic single crystal diamond without flattening the single crystal diamond seed substrate for which the flattening is not necessary based on the determination., '(3) any one of the following two steps of2. The method for manufacturing a single crystal diamond according to claim 1 , wherein in the step (3a) claim 1 , according to the ...

METHOD FOR MANUFACTURING A CRYSTALLINE LAYER OF PZT MATERIAL, AND SUBSTRATE FOR EPITAXIAL GROWING A CYRSTALLINE LAYER OF PZT MATERIAL

A process for producing a crystalline layer of PZT material, comprising the transfer of a monocrystalline seed layer of SrTiOmaterial to a carrier substrate of silicon material, followed by epitaxial growth of the crystalline layer of PZT material. 1. A process for producing a crystalline layer of PZT material , comprising: transferring a monocrystalline seed layer of SrTiOmaterial to a carrier substrate of silicon material , followed by epitaxial growth of the crystalline layer of PZT material.2. The process of claim 1 , wherein the monocrystalline seed layer has a thickness of less than 10 μm.3. The process of claim 2 , wherein the transfer of the monocrystalline seed layer of SrTiOmaterial to the carrier substrate of silicon material comprises joining a monocrystalline substrate of SrTiOmaterial to the carrier substrate followed thinning the monocrystalline substrate of SrTiOmaterial.4. The process of claim 3 , wherein the thinning of the monocrystalline substrate of SrTiOmaterial comprises formation of a weakened zone delimiting a portion of the monocrystalline substrate of SrTiOmaterial intended to be transferred to the carrier substrate of silicon material.5. The process of claim 4 , wherein the formation of the weakened zone comprises implanting atomic and/or ionic species into the monocrystalline substrate of SrTiOmaterial.6. The process of claim 4 , wherein the thinning of the monocrystalline substrate of SrTiOmaterial comprises detaching at the weakened zone so as to transfer the portion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate of silicon material.7. The process of claim 3 , wherein the joining of the monocrystalline substrate of SrTiOmaterial to the carrier substrate comprises molecular adhesion of the monocrystalline substrate of SrTiOmaterial to the carrier substrate.8. The process of claim 1 , wherein the monocrystalline seed layer of SrTiOmaterial is in the form of a plurality of tiles each transferred to the carrier ...

Semiconductor material based on metal nanowires and porous nitride and preparation method thereof

Provided are a semiconductor material based on metal nanowires and a porous nitride, and a preparation method thereof. The semiconductor material includes: a substrate; a buffer layer formed on the substrate; and a composite material layer formed on the buffer layer the composite material layer includes: a transverse porous nitride template layer; and a plurality of metal nanowires filled in pores of the transverse porous nitride template layer.

Architectures Enabling Back Contact Bottom Electrodes For Semiconductor Devices

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned above the IBAD template layer. The at least one buffer layer has a resistivity of less than 100 μΩcm. The semiconductor device and method foster the use of bottom electrodes thereby avoiding complex and expensive lithography processes. 1. A semiconductor device comprising:a polycrystalline or amorphous substrate;an electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer positioned above the substrate; andat least one electrically conductive hetero-epitaxial buffer layer positioned above the IBAD template layer, wherein the at least one buffer layer has a resistivity of less than 100 μΩcm.2. The semiconductor device of claim 1 , wherein the IBAD template layer comprises Titanium Nitride (TiN).3. The semiconductor device of claim 1 , wherein the at least one buffer layer does not comprise an oxide.4. The semiconductor device of claim 1 , wherein the at least one buffer layer comprises a fluorite structure.5. The semiconductor device of claim 1 , wherein the at least one buffer layer comprises Nickel Silicide (NiSi).6. The semiconductor device of claim 1 , further comprising an electrically conductive amorphous layer positioned between the substrate and the IBAD template layer.7. The semiconductor device of claim 6 , wherein the amorphous layer comprises Titanium Nitride (TiN) or Tantalum-Nickel (Ta—Ni).8. The semiconductor device of claim 1 , further comprising an epitaxial Si film or an epitaxial Ge film positioned above the buffer layer.9. The semiconductor device of claim 1 , further comprising an epitaxial Si film positioned above the buffer layer claim 1 , ...

GROWTH OF A-B CRYSTALS WITHOUT CRYSTAL LATTICE CURVATURE

The present invention relates to a process for the production of III-V-, IV-IV- or II-VI-compound semiconductor crystals. The process starts with providing of a substrate with optionally one crystal layer (buffer layer). Subsequently, a gas phase is provided, which comprises at least two reactants of the elements of the compound semiconductor (II, III, IV, V, VI) which are gaseous at a reaction temperature in the crystal growth reactor and can react with each other at the selected reactor conditions. The ratio of the concentrations of two of the reactants is adjusted such that the compound semiconductor crystal can crystallize from the gas phase, wherein the concentration is selected that high, that crystal formation is possible, wherein by an adding or adjusting of reducing agent and of co-reactant, the activity of the III-, IV- or II-compound in the gas phase is decreased, so that the growth rate of the crystals is lower compared to a state without co-reactant. Therein, the compound semiconductor crystal is deposited at a surface of the substrate, while a liquid phase can form on the growing crystal. 1. (canceled)2. The process according to claim 1 , adding the reducing agent comprises adding the reducing agent in an amount that generates formation of an elementary metal of the first element claim 1 , on a surface of the crystal growth zone.3. (canceled)4. The process according to claim 14 , wherein the compound semiconductor is selected from GaN claim 14 , AlN claim 14 , GaAlN (0 Подробнее

METHOD FOR PRODUCING GRAPHENE, AND GRAPHENE PRODUCED BY THE METHOD

A method for producing grapheme is disclosed in which graphene is formed by supplying carbon to a heated transition metal surface, in order to form a high-quality uniform graphene film having no domain boundaries. The method includes forming a buffer thin film that is epitaxially grown on a Ni(111) substrate, and forming graphene on the buffer thin film. The buffer thin film is made of material selected from the group consisting of Fe, Co, Ni, Cu, Mo, Ru, Rh, Pd, W, Re, Ir and Pt, or from alloys thereof. The buffer thin film has a surface of three-fold symmetry or six-fold symmetry. 1. A method for producing graphene in which graphene is formed by supplying carbon to a heated transition metal surface , the method comprising:providing a Ni(111) substrate;epitaxially growing a buffer thin film on the Ni(111) substrate, andforming graphene on the buffer thin film.2. The method for producing graphene according to claim 1 , wherein the buffer thin film is made of material selected from the group consisting of Fe claim 1 , Co claim 1 , Ni claim 1 , Cu claim 1 , Mo claim 1 , Ru claim 1 , Rh claim 1 , Pd claim 1 , W claim 1 , Re claim 1 , Ir and Pt claim 1 , or from alloys thereof.3. The method for producing graphene according to claim 1 , wherein the buffer thin film has a surface of three-fold symmetry or six-fold symmetry.4. The method for producing graphene according to claim 1 , wherein the thickness of the buffer thin film ranges from 2 nm to 100 nm.5. The method for producing graphene according to claim 4 , wherein the surface roughness of the buffer thin film is no greater than 1 nm.6. Graphene which has been formed on a buffer layer that is epitaxially grown on a Ni(111) substrate.7. The graphene according to claim 6 , wherein the buffer thin film is made of material selected from the group consisting of Fe claim 6 , Co claim 6 , Ni claim 6 , Cu claim 6 , Mo claim 6 , Ru claim 6 , Rh claim 6 , Pd claim 6 , W claim 6 , Re claim 6 , Ir and Pt claim 6 , or from alloys ...

Epitaxial growth of compound semiconductors using lattice-tuned domain-matching epitaxy

A method of epitaxially growing a final film using a crystalline substrate wherein the final film cannot be grown directly on the substrate surface is disclosed. The method includes forming a transition layer on the upper surface of the substrate. The transition layer has a lattice spacing that varies between its lower and upper surfaces. The lattice spacing at the lower surface matches the lattice spacing of the substrate to within a first lattice mismatch of 7%. The lattice spacing at the upper surface matches the lattice spacing of the final film to within a second lattice mismatch of 7%. The method also includes forming the final film on the upper surface of the transition layer. 1. A method of epitaxially growing a desired film having a lattice spacing ausing a crystalline substrate having an upper surface and a lattice spacing a , the method comprising:{'sub': T', 'T', 'T', 's', 'T', 'T', 'F, 'forming on the upper surface of the substrate at least one transition layer having a lower surface, an upper surface, a thickness h, and a lattice spacing a(z) that varies between the lower and upper surfaces such that the lattice spacing a(0) at the lower surface satisfies m·a(0)=n·ato within a first lattice mismatch of 7%, where n, m are integers, and the lattice spacing a(h) at the upper surface satisfies the relationship i·a(h)=j·ato within a second lattice mismatch of within 7%, where i, j are integers; and'}forming the desired film on the upper surface of the transition layer.2. The method of claim 1 , wherein at least one of first and second lattice mismatches is within 2%.3. The method of claim 2 , wherein at least one of first and second lattice mismatches is within 1%.4. The method of claim 1 , wherein the substrate comprises a material selected from the group of material comprising: Si claim 1 , Ge claim 1 , SiGe claim 1 , AlN claim 1 , GaN claim 1 , SiC and diamond.5. The method of claim 1 , wherein substrate comprises Si claim 1 , and wherein forming the ...

Method for preparing a heterostructure

The present disclosure provides a method for preparing heterostructure, which includes providing a donor substrate and forming a sacrificial layer on a surface of the donor substrate; forming a thin film cover layer on a surface of the sacrificial layer, wherein a top surface of the thin film cover layer is an implantation surface; performing ion implantation from the implantation surface, such that a defect layer is formed in the sacrificial layer; providing an acceptor substrate, and bonding the acceptor substrate to the implantation surface of the thin film cover layer; removing the sacrificial layer along the defect layer. The method for preparing the heterostructure of the present disclosure can successfully transfer the thin film cover layer to the acceptor substrate. The present disclosure can provide a compliant substrate, while the semiconductor donor substrate material can be reused, therefore is energy-efficient and environmental-friendly. 1. A method for preparing heterostructure , comprising:1) providing a donor substrate and forming a sacrificial layer on a surface of the donor substrate;2) forming a thin film cover layer on a surface of the sacrificial layer, wherein a top surface of the thin film cover layer is an implantation surface;3) performing ion implantation from the implantation surface, such that a defect layer is formed in the sacrificial layer;4) providing an acceptor substrate, and bonding the acceptor substrate to the implantation surface of the thin film cover layer;5) removing the sacrificial layer along the defect layer, so as to separate the acceptor substrate bonded with the thin film cover layer from the donor substrate, to obtain a heterostructure of acceptor substrate-thin film cover layer.21. The method for preparing heterostructure according to claim 1 , wherein step ) further comprises forming a buffer layer on the surface of the donor substrate claim 1 , and the buffer layer is formed between the donor substrate and the ...

GAAS THIN FILM GROWN ON SI SUBSTRATE, AND PREPARATION METHOD FOR GAAS THIN FILM GROWN ON SI SUBSTRATE

Disclosed is a preparation method for a GaAs thin film grown on an Si substrate, said method comprising the following steps: (1) Si (111) substrate cleaning; (2) Si (111) substrate preprocessing; (3) Si (111) substrate oxide film removal; (4) first InGaAs buffer layer growth; (5) first InGaAs buffer layer in situ annealing; (6) GaAs buffer layer growth; (7) GaAs buffer layer in situ annealing; (8) second InGaAs buffer layer growth; (9) second InGaAs buffer layer in situ annealing; (10) GaAs epitaxial thin film growth. Also disclosed is a GaAs thin film grown on an Si substrate. The GaAs thin film obtained by the present invention has a good crystal quality, an even surface, and a positive promotional significance with regard to the preparation of semiconductor devices, particularly in the field of solar cells. 1. A preparation method for a GaAs thin film grown on a Si substrate , characterized in that the method comprises the following steps:(1) cleaning a Si substrate;(2) preprocessing the Si substrate;(3) removing the oxide film from the Si substrate;{'sub': x', '1-x', 'x', '1-x, 'sup': −5', '−8, '(4) growing a first InGaAs buffer layer: decreasing the temperature of the substrate to 350˜500° C., and growing an InGaAs buffer layer with a thickness of 2˜20 nm under the conditions of a reaction chamber pressure of 3.0×10˜2.5×10Pa, a V/III value of 20˜30, and a growth rate of 0.1˜0.5 ML/s, wherein 0.05 Подробнее

BUFFER LAYERS HAVING COMPOSITE STRUCTURES

Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction. 1. A method for manufacturing a material stack for semiconductor-based optoelectronic or electronic devices , comprising:providing a substrate;disposing a basis buffer layer of a first material above the substrate; and a first buffer sublayer of the first material, and', 'a second buffer sublayer of a second material disposed above the first buffer sublayer;, 'disposing a plurality of composite buffer layers above the basis buffer layer sequentially along a growth direction from the substrate to a last composite buffer layer of the plurality of composite buffer layers, each composite buffer layer except the last composite buffer layer includingwherein thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.2. The method of claim 1 , wherein thicknesses of the second buffer sublayers of the composite buffer layers increase along the growth direction.3. The method of claim 1 , wherein the basis buffer layer of the first material has a relaxed lattice constant for the first material claim 1 , and the ...

METHOD FOR PRODUCING A MONOCRYSTALLINE LAYER OF AN LNO MATERIAL AND SUBSTRATE FOR EPITAXIAL GROWTH OF A MONOCRYSTALLINE LAYER OF AN LNO MATERIAL

A process for producing a monocrystalline layer of LNO material comprises the transfer of a monocrystalline seed layer of YSZ material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material. 1. A process for producing a monocrystalline layer of lithium niobate (LNO) material , comprising: transferring a monocrystalline seed layer of yttria-stabilized zirconia (YSZ) material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material.2. The process of claim 1 , wherein the monocrystalline seed layer has a thickness of less than 10 μm claim 1 , preferably less than 2 μm claim 1 , and more preferably less than 0.2 μm.3. The process of claim 2 , wherein the transfer of the monocrystalline seed layer of YSZ material to the carrier substrate of silicon material comprises joining a monocrystalline substrate of YSZ material to the carrier substrate claim 2 , followed by thinning the monocrystalline substrate of YSZ material.4. The process of claim 3 , wherein the thinning comprises forming a weakened zone delimiting a portion of the monocrystalline substrate of YSZ material to be transferred to the carrier substrate of silicon material.5. The process of claim 4 , wherein the formation of the weakened zone comprises implanting atomic and/or ionic species into the monocrystalline substrate of YSZ material.6. The process of claim 4 , wherein the thinning comprises detaching at the weakened zone so as to transfer the portion of the monocrystalline substrate of YSZ material to the carrier substrate of silicon material.7. The process of claim 3 , wherein joining the monocrystalline substrate of YSZ material to the carrier substrate comprises molecular adhesiones of the monocrystalline substrate of YSZ material to the carrier substrate.8. The process of claim 3 , wherein the monocrystalline seed layer of YSZ material is in the form of a plurality of tiles each ...

Method for producing 3c-sic epitaxial layer, 3c-sic epitaxial substrate, and semiconductor device

A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed.

METHOD OF MANUFACTURING HIGH ELECTRON MOBILITY TRANSISTOR AND HIGH ELECTRON MOBILITY TRANSISTOR

A method of manufacturing a high electron mobility transistor, comprising steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less. 1. A method of manufacturing a high electron mobility transistor comprising steps of:forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less;forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure of 1 Pa or lower; andforming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.2. The method of manufacturing the high electron mobility transistor according to claim 1 ,wherein the step of forming the interface oxide layer is continued for at least 30 seconds.3. The method of manufacturing the high electron mobility transistor according to claim 1 ,wherein the steps of forming the interface oxide layer and forming the second SiN film set a ratio of a flow rate of dichlorosilane gas as a silicon raw material to a flow rate of ammonia gas as a nitrogen raw material to 1:1.4. The method of manufacturing the high electron ...

Superconducting Compounds and Methods for Making the Same

A superconducting article includes a substrate and a superconducting metal oxide film formed on the substrate. The metal oxide film including ions of an alkali metal, ions of a transition metal, and ions of an alkaline earth metal or a rare earth metal. For instance, the metal oxide film can include Rb ions, La ions, and Cu ions. The superconducting metal oxide film can have a critical temperature for onset of superconductivity of greater than 250 K, e.g., greater than room temperature. 1. A method of forming a superconducting article , the method comprising: exposing the substrate to one or more pulses of a reactant including one or more of the alkaline earth metal and the rare earth metal;', 'exposing the substrate to one or more pulses of a reactant including the transition metal; and', 'exposing the substrate to one or more pulses of a reactant including the alkali metal; and, 'forming a superconducting metal oxide film on a substrate by atomic layer deposition, the metal oxide film including ions of an alkali metal and ions of a transition metal, and ions of one or more of an alkaline earth metal and a rare earth metal, the forming includingannealing the substrate with the metal oxide film formed thereon.2. The method of claim 1 , in which the alkali metal ions comprise one or more of Li ions claim 1 , Na ions claim 1 , K ions claim 1 , Rb ions claim 1 , and Cs ions.3. The method of or claim 1 , in which the transition metal ions comprise one or more of Cu ions and Fe ions.4. The method of any of the preceding claims claim 1 , in which forming the metal oxide film on the substrate comprises forming a metal oxide film comprising La ions claim 1 , Rb ions claim 1 , and Cu ions.5. The method of claim 4 , in which the metal oxide film has a composition of (RbLa)CuO.6. The method of claim 5 , in which x is greater than or equal to 0.5.7. The method of any of the preceding claims claim 5 , comprising forming one or more of a diffusion barrier and a buffer layer on ...

REDUCTION OF BASAL PLANE DISLOCATIONS IN EPITAXIAL SiC USING AN IN-SITU ETCH PROCESS

A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas. 1. A method comprising:providing an off-axis silicon carbide substrate; andetching the surface of the substrate with a dry gas, hydrogen, or an inert gas.2. The method of claim 1 , wherein the substrate is a 4H-SiC substrate.3. The method of claim 1 , wherein the substrate is a 6H-SiC substrate4. The method of claim 1 , wherein the substrate is a 0-8° off-axis 4H-SiC substrate.5. The method of claim 1 , wherein the etching is performed with hydrogen.6. The method of claim 1 , wherein the etching is performed with silane.7. The method of claim 1 , wherein the etching is performed with argon.8. The method of claim 1 , wherein the etching is performed at 1450-1800° C.9. The method of claim 1 , wherein the etching is performed at 30-500 mbar of the dry gas.10. The method of claim 1 , wherein the etching is performed for up to 90 minutes.11. The method of claim 1 , further comprising:growing a doped buffer layer on the substrate after the etching.12. The method of claim 11 , wherein the doped buffer layer is doped with N.13. The method of claim 11 , wherein the doped buffer layer is doped with P.14. The method of claim 11 , wherein the doped buffer layer is about 0.5-30 μm thick.15. The method of claim 11 , further comprising:growing an epitaxial silicon carbide layer on the doped buffer layer. This application claims the benefit of U.S. Provisional Application No. 61/787,903, filed on Mar. 15, 2013. This application is a continuation-in-part application of pending U.S. patent application Ser No. 12/860,844, filed on Aug. 20, 2010, which claims the benefit of U.S. Provisional Application No. 61/235,455, filed on Aug. 20, 2009. These applications and all other publications or patent documents cited throughout this application are incorporated herein by reference.The present disclosure is generally related to SiC epitaxial growth ...

ELASTIC WAVE DEVICE AND METHOD FOR MANUFACTURING THE SAME

An elastic wave device includes a piezoelectric substrate including a primary surface and a first electrode which is provided on the primary surface of the piezoelectric substrate, which includes a first multilayer metal film including at least three metal films laminated in a bottom-to-top direction, and which includes at least an IDT film. The first multilayer metal film includes a Ti film as the topmost film and has a crystal orientation oriented in a predetermined direction so that the normal line direction of the plane of a Ti crystal of the Ti film coincides with the Z axis of a crystal of a piezoelectric body defining the piezoelectric substrate. 1. An elastic wave device comprising:a piezoelectric substrate including a primary surface; anda first electrode provided on the primary surface of the piezoelectric substrate and including a first multilayer metal film including at least three metal films laminated in a bottom-to-top direction, and at least an IDT electrode; whereinthe first multilayer metal film includes a Ti film defining a topmost film and has a crystal orientation oriented in a predetermined direction so that a normal line direction of a (001) plane of a Ti crystal of the Ti film coincides with a Z axis of a crystal of a piezoelectric body defining the piezoelectric substrate.2. The elastic wave device according to claim 1 , further comprising:a second electrode provided above the primary surface of the piezoelectric substrate and including a second multilayer metal film including metal films laminated in a bottom-to-top direction; whereina contact portion at which the first electrode and the second electrode are electrically connected to each other is provided by a portion at which a bottommost film of the second multilayer metal film and the topmost film of the first multilayer metal film are overlapped with each other;the first multilayer metal film includes an epitaxial film and the Ti film as the topmost film; andthe second multilayer metal ...

Multilayer stack for the growth of carbon nanotubes by chemical vapor deposition

The subject of the invention is the use, as catalyst support sublayer in a process for growing carbon nanotubes by chemical vapour deposition (CVD), of a multilayer stack formed of alternating layers of silica and of alumina, each of the layers having a thickness of less than or equal to 10 nm and consisting of one or more superposed atomic monolayer(s). It also relates to a multilayer structure comprising a substrate which has, on at least one of its faces, such a multilayer stack, and also to the use thereof for the growth of a mat of carbon nanotubes, which are in particular spinnable, by chemical vapour deposition, preferably hot-filament chemical vapour deposition.

COMPOUND SEMICONDUCTOR SUBSTRATE

A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less. 1. A compound semiconductor substrate comprising:a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, whereinthe ground substrate is formed of a sintered body,the seed layer is formed of a single crystal,the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer,a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, andan FWHM of an X-ray diffraction peak of the buffer layer is 800 arcsec or less.2. The compound semiconductor substrate according to claim 1 , wherein a layer thickness of the compound semiconductor layer is 7 μm or more and 15 μm or less.3. The compound semiconductor substrate according to claim 1 , wherein the active layer is one obtained by forming an electron supply layer on an electron transit layer.4. The compound semiconductor substrate according to claim 2 , wherein the active layer is one obtained by forming an electron supply layer on an electron transit layer.5. The compound semiconductor substrate according to claim 3 , wherein a spacer ...

METHOD FOR GROWING GALLIUM NITRIDE BASED ON GRAPHENE AND MAGNETRON SPUTTERED ALUMINIUM NITRIDE

The present invention discloses a method for growing gallium nitride based on graphene and magnetron sputtered aluminum nitride, and a gallium nitride thin film. The method according to an embodiment comprises: spreading graphene over a substrate; magnetron sputtering an aluminum nitrite onto the graphene-coated substrate to obtain a substrate sputtered with aluminum nitrite; placing the substrate sputtered with aluminum nitride into a MOCVD reaction chamber and heat treating the substrate to obtain a heat treated substrate; growing an aluminum nitride transition layer on the heat treated substrate and a first and a second gallium nitride layer having different V-III ratios, respectively. The gallium nitrate thin film according to an embodiment comprises the following structures in order from bottom to top: a substrate (), a graphene layer (), an aluminum nitride nucleation layer () fabricated by using a magnetron sputtering method, an aluminum nitride transition layer () grown by MOCVD, and a first and a second gallium nitrate layer () having different V-III ratios. 120-. (canceled)21. A method for growing gallium nitride , comprising:spreading graphene over a substrate;magnetron sputtering an aluminum nitride onto the graphene-coated substrate, to obtain a substrate sputtered with aluminum nitride;placing the substrate sputtered with aluminum nitride in a metal organic chemical vapor deposition (MOCVD) reaction chamber and heat treating the substrate to obtain the heat-treated substrate; andgrowing a first gallium nitride layer and a second gallium nitride layer on the heat-treated substrate, respectively; wherein VIII ratio of the first gallium nitride layer is different from VIII ratio of the second gallium nitride layer.22. The method of claim 21 , wherein the substrate is any one of a silicon substrate claim 21 , a sapphire substrate claim 21 , and a copper substrate.23. The method according to claim 21 , wherein the substrate is a silicon substrate or a ...

METHOD OF MANUFACTURING A GALLIUM NITRIDE SUBSTRATE

In a method of manufacturing a GaN substrate, a capping layer may be formed on a first surface of a silicon substrate. A buffer layer may be formed on a second surface of the silicon substrate. The second surface may be opposite the first surface. A GaN substrate may be formed on the buffer layer by performing a hydride vapor phase epitaxy (HVPE) process. The capping layer and the silicon substrate may be removed. 1. A method of manufacturing a gallium nitride (GaN) substrate , the method comprising:forming a capping layer on a first surface of a silicon substrate;forming a buffer layer on a second surface of the silicon substrate, the second surface being opposite the first surface;forming a GaN substrate on the buffer layer by performing a hydride vapor phase epitaxy (HVPE) process; andremoving the capping layer and the silicon substrate.2. The method of claim 1 , wherein the removing the capping layer removes the capping layer by a chlorine-based etching gas.3. The method of claim 1 , wherein the forming a capping layer forms the capping layer of at least one of titanium (Ti) claim 1 , zirconium (Zr) claim 1 , hafnium (Hf) claim 1 , molybdenum (Mo) claim 1 , manganese (Mn) claim 1 , nickel (Ni) claim 1 , copper (Cu) claim 1 , zinc (Zn) claim 1 , chromium (Cr) claim 1 , Gallium (Ga) claim 1 , aluminum (Al) claim 1 , indium (In) claim 1 , and a nitride thereof.4. The method of claim 1 , wherein the forming a capping layer forms the capping layer by an atomic layer deposition (ALD) process claim 1 , a sputtering process or a chemical vapor deposition (CVD) process.5. The method of claim 1 , wherein the forming a GaN substrate forms the GaN substrate at a temperature of about 950° C. to 1200° C. by performing the HVPE process.6. The method of claim 1 , wherein the removing the capping layer and the silicon substrate removes the capping layer and the silicon substrate by the same dry etching process using a chlorine-based etching gas.7. The method of claim 6 , wherein ...

EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlGaN layer to the junction between the i-GaN channel layer and the i-AlGaN layer. 1. An epitaxial structure of N-face AlGaN/GaN , comprising:a silicon substrate;a C-doped buffer layer, located on said silicon substrate;a C-doped GaN layer, located on said C-doped buffer layer;{'sub': 'y', 'an i-AlGaN layer, located on said C-doped GaN layer;'}{'sub': 'y', 'an i-GaN channel layer, located on said i-AlGaN layer;'}{'sub': 'x', 'an i-AlGaN layer, located on said i-GaN channel layer;'}{'sub': 'x', 'a fluorine-ion structure, located in said i-AlGaN layer;'}a gate moat structure, located on said i-AlGaN layer and surrounding both sides of said fluorine-ion structure; anda first gate dielectric layer, located on said fluorine-ion structure;where x=0.1˜0.3 and y=0.05˜0.75.2. The structure of claim 1 , wherein an i-AlGaN grading buffer layer is further disposed between said C-doped GaN layer and said i-AGaN layer and z=0.01˜0.75.3. The structure of claim 1 , wherein the two-dimensional electron gas in said i-GaN channel layer is depleted below said fluorine-ion structure and the two-dimensional electron gas is located at the junction between said i-GaN channel layer and said i-AlGaN layer claim 1 ,4. A hybrid enhancement-mode N-face AlGaN/ ...

Graphene Hybrids for Biological and Chemical Sensing

Embodiments relate to a layered material (having a substrate, at least a buffer layer, with zero or more growth layers) that has been intercalated via a process that decouples (physically and electronically) the buffer layer from the substrate, thereby resulting in the creation of few-atom thick metal layers that exhibit a range of optical properties, including plasmonic or electronic resonance, that enables superior optical (e.g. Raman) detection of molecules. 1. A plasmonic or electronically resonant material , comprising:a substrate; andan epitaxial growth layer comprising a graphene layer; andan interface layer formed between the graphene layer and the substrate, the interface layer comprising graphene passivated with intercalant.2. The plasmonic or electronically resonant material recited in claim 1 , wherein the graphene layer comprises a plurality of pristine graphene layers.3. The plasmonic or electronically resonant material recited in claim 1 , wherein the substrate is silicon carbide.4. The plasmonic or electronically resonant material recited in claim 1 , wherein the intercalant is metal.5. The plasmonic or electronically resonant material recited in claim 1 , wherein the intercalant comprises any one or combination of europium claim 1 , hydrogen claim 1 , silicon claim 1 , gallium claim 1 , indium claim 1 , lithium claim 1 , sodium claim 1 , calcium claim 1 , iron claim 1 , palladium claim 1 , platinum claim 1 , gold claim 1 , silver claim 1 , germanium claim 1 , tin claim 1 , lead claim 1 , oxygen claim 1 , and fluorine.6. The plasmonic or electronically resonant material recited in claim 1 , further comprising at least one vapor deposition growth layer formed on top of the graphene layer.7. The plasmonic or electronically resonant material recited in claim 6 , wherein the at least one vapor deposition growth layer is a transition metal dichalcogenide layer.8. A sensor system claim 6 , comprising: a substrate; and', 'an epitaxial growth layer, ...

Semipolar nitride semiconductor structure and method of manufacturing the same

Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.

METHOD FOR EPITAXIAL GROWTH OF SINGLE CRYSTALLINE HETEROGENEOUS 2D MATERIALS AND STACKED STRUCTURE

Disclosed herein is a method for 2D epitaxial growth comprising: forming a single crystalline h-BN template; forming a plurality of nuclei by depositing a heterogeneous precursor on the h-BN template; and forming a heterogeneous structure layer by growing the plurality of deposited nuclei with a van der Waals epitaxial growth, wherein the heterogeneous structure layer is a single crystal. 1. A method for 2D epitaxial growth comprising:forming a single crystalline h-BN template;forming a plurality of nuclei by depositing a heterogeneous precursor on the h-BN template; andforming a heterogeneous structure layer by growing the plurality of deposited nuclei with a van der Waals epitaxial growth, wherein the heterogeneous structure layer is a single crystal.2. The method for 2D epitaxial growth according to claim 1 , wherein the plurality of deposited nuclei are oriented in one direction.3. The method for 2D epitaxial growth according to claim 1 , wherein the heterogeneous precursor comprises one or more of methane (CH) claim 1 , ethane (CH) and ethyne (CH); metal oxide (MO) and chalcogen (X) claim 1 , or borazine (HBNH) claim 1 , wherein the M is Mo or W and the X is S claim 1 , Se claim 1 , or Te.4. The method for 2D epitaxial growth according to claim 1 , wherein the method directly grows the heterogeneous structure layer continuously on the h-BN template immediately after forming the single crystalline h-BN template.5. The method for 2D epitaxial growth according to claim 1 , wherein the forming the single crystalline h-BN template comprises:stacking a second substrate on a first substrate;heating a stacked substrate to a melting temperature or higher of the second substrate; andforming the single crystalline h-BN template on the second substrate.6. The method for 2D epitaxial growth according to claim 2 , wherein a melting temperature of a first substrate is higher than a melting temperature of a second substrate.7. The method for 2D epitaxial growth according to ...

Selective sidewall growth of semiconductor material

A method of producing a bulk semiconductor material comprises the steps of providing a base comprising a substantially planar substrate having a plurality of etched nano/micro-structures located thereon, each structure having an etched, substantially planar sidewall, wherein the plane of each said etched sidewall is arranged at an oblique angle to the substrate, and selectively growing the bulk semiconductor material onto the etched sidewall of each nano/micro-structure using an epitaxial growth process. A layered semiconductor device may be grown onto the bulk semiconductor material.

METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DIODES USING AN ENGINEERED SUBSTRATE

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer. 1. A method of forming a semiconductor diode , the method comprising: providing a polycrystalline ceramic core;', 'encapsulating the polycrystalline ceramic core with a first adhesion shell;', 'encapsulating the first adhesion shell with a barrier layer;', 'forming a bonding layer on the barrier layer; and', 'joining a substantially single crystal layer to the bonding layer;, 'forming a substrate byforming a buffer layer on the substantially single crystal layer;forming a semi-insulating layer on the buffer layer;forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer, the first epitaxial N-type gallium nitride layer having a first doping concentration;forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer, the second epitaxial N-type gallium nitride layer having a second doping concentration less than the first doping concentration;forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer;removing a portion of the second epitaxial N-type gallium nitride layer and ...

Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films

Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten suspension mixture (e.g., including KOH (or KOH eutectic) and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.

METHOD FOR DETERMINING PREFERENTIAL DEPOSITION PARAMETERS FOR A THIN LAYER OF III-V MATERIAL

First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions. 1. A method for determining deposition parameters of a first layer made from semiconductor material of III-V type in a sample successively comprising:a monocrystalline layer of relaxed germanium epitaxially grown from a first surface of crystalline orientation of (001) type of a monocrystalline silicon layer,a first monocrystalline layer made from semiconductor material of III-V type formed by organometallic chemical vapor deposition,a second monocrystalline layer made from semiconductor material of III-V type formed by organometallic chemical vapor deposition, the stack formed by the first and second monocrystalline layers of semiconductor material of III-V type having a thickness E, the method comprising:making a first series of samples in which the first layer of semiconductor material of III-V type having a first thickness is covered by the second layer of semiconductor material having a second thickness, the deposition conditions of the first layer of semiconductor material of III-V type being chosen such that the deposition pressure differs between the samples of the first series, the deposition temperature being identical between the samples of the first series and equal to an initial ...

Method For Depositing A Crystal Layer At Low Temperatures, In Particular A Photoluminescent IV-IV Layer On An IV Substrate, And An Optoelectronic Component Having Such A Layer

A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as GeHor SiH; providing a halide of a second IV element (B), such as SnCl; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.; producing a carrier gas flow of an inert carrier gas, in particular N, Ar, He, which in particular is not H; transporting the hydride and the halide and decomposition products arising therefrom to the surface at a total pressure of at most 300 mbar; depositing the IV-IV layer, or a layer sequence consisting of IV-IV layers of the same type, having a thickness of at least 200 nm, wherein the deposited layer is, in particular, a SiGeSn layer, with x>0.08 and y≦1. 1. A method for depositing a monocrystalline semiconductor layer consisting of a first element (A) and a second element (B) , wherein the first element (A) is fed as part of a first gaseous starting material , in particular a hydride , and the second element (B) is fed as part of a second gaseous starting material , in particular a halide , together with a carrier gas formed by an inert gas , in particular N , Ar , He , into a process chamber of a CVD reactor , wherein radicals are produced from the first starting material , which radicals and the second starting material are brought to the surface of a semiconductor substrate heated to a ...

Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films

Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface. 1. A method of converting basal plane dislocations on a surface of a SiC substrate to threading edge dislocations , the method comprising:immersing the SiC substrate into a suspension mixture having a temperature of about 170° C. to about 800° C., wherein the suspension mixture comprises KOH and an alkaline earth oxide; andthereafter, growing an epitaxial film on the surface of the SiC substrate.2. The method as in claim 1 , wherein the SiC substrate is a SiC wafer claim 1 , and wherein the surface is defined by the SiC wafer.3. The method as in claim 1 , wherein the SiC substrate comprises a SiC wafer having a buffer epilayer thereon claim 1 , and wherein the surface of the SiC substrate is defined by the buffer epilayer.4. The method as in claim 3 , wherein the buffer epilayer comprises SiC.5. The method as in claim 3 , further comprising:prior to immersing the SiC substrate into the suspension mixture, growing the buffer epilayer on the surface of the SiC wafer.6. The method as in claim 1 , wherein the suspension mixture comprises the alkaline earth oxide in an amount of about 5% to about 80% by weight.7. The method as in claim 6 , wherein the suspension mixture comprises the alkaline earth oxide in an amount of about 5% to about 20% by weight.8. The method as in claim 1 , wherein the suspension mixture comprises KOH claim 1 , the alkaline earth oxide claim 1 , and at least one other salt.9. The method as in claim 8 , wherein the at ...

METHOD OF GROWING DIAMOND THIN FILM

The present invention is directed to a method of growing thin film diamond. Since there are micro-grooves formed between internal grains of the heterogeneous substrate during lateral epitaxy growth, diamond seeds are allowed to be embedded in the micro-grooves; surface damage caused by scratching method or seeding method also can be prevented. As a result, a continuous diamond thin film with uniform thickness and high quality can be obtained. 1. A growth method of diamond thin film comprising:providing a carrier substrate;forming a heterogeneous substrate on the carrier substrate via epitaxial growth, wherein the heterogeneous substrate comprises multiple grains and there are multiple irregular micro-grooves formed at junction between the multiple grains on a upper surface of the heterogeneous substrate;providing multiple diamond seeds embedded into the multiple micro-grooves; anddepositing a diamond thin film on the upper surface of the heterogeneous substrate.2. The growth method of diamond thin film according to claim 1 , wherein the heterogeneous substrate is immersed into a suspension fluid containing the multiple diamond seeds for ultrasonic vibration so as to make the multiple diamond seeds embedded into the multiple micro-grooves.3. The growth method of diamond thin film according to further comprising using a cleaning fluid to clean the heterogeneous substrate after providing multiple diamond seeds embedded into the multiple micro-grooves so as to remove multiple agglomerates of the multiple diamond seeds formed on the upper surface of the heterogeneous substrate.4. The growth method of diamond thin film according to claim 3 , wherein the cleaning fluid comprises at least one of water claim 3 , ethanol claim 3 , methanol claim 3 , and acetone.5. The growth method of diamond thin film according to claim 1 , wherein the carrier substrate and the heterogeneous substrate are composed of the same materials.6. The growth method of diamond thin film according to ...

VERTICAL SEMICONDUCTOR DIODE MANUFACTURED WITH AN ENGINEERED SUBSTRATE

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer. 1. A method of forming a semiconductor diode , the method comprising: providing a polycrystalline ceramic core;', 'encapsulating the polycrystalline ceramic core with a first adhesion shell;', 'encapsulating the first adhesion shell with a barrier layer;', 'forming a bonding layer on the barrier layer; and', 'joining a substantially single crystal layer to the bonding layer;, 'forming a substrate byforming a buffer layer on the substantially single crystal layer;forming a semi-insulating layer on the buffer layer;forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer, the first epitaxial N-type gallium nitride layer having a first doping concentration;forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer, the second epitaxial N-type gallium nitride layer having a second doping concentration less than the first doping concentration;forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer;removing a portion of the second epitaxial N-type gallium nitride layer and ...

PROCESS FOR OBTAINING A NITRIDE LAYER

A process for obtaining a nitride (N) layer preferably obtained from at least one of gallium (Ga), indium (In) and aluminium (Al), may include: on a stack including a substrate and at least the following layers successively disposed from the substrate: a creep layer having a glass transition temperature, T, and a crystalline layer, forming pads by etching the stack so that each pad includes at least a creep segment formed by at least a portion of the creep layer, and a crystalline segment formed by the crystalline layer; and growing by epitaxy a crystallite on each of the pads and continuing the epitaxial growth of the crystallites so as to form the nitride layer. The epitaxial growth may be carried out at a temperature T, such that T≥k1×T, with k1 being 0.8. 1. A process for obtaining a nitride (N) layer optionally obtained from gallium (Ga) , indium (In) , and/or aluminium (Al) , the process comprising:on a stack comprising a substrate and, successively disposed from the substrate{'sub': 'glass transition', 'a first layer, as a creep layer comprising a material having a glass transition temperature, T, and'}a second layer, as a crystalline layer, which is crystalline and different from the creep layer,forming pads by etching at least the crystalline layer and at least a portion of the creep layer so that:{'b': 1000', '1000, 'i': a', 'e, '(i) each pad (-) comprises(i-a) a first segment, as a creep segment, formed by at least a portion of the creep layer,; and (i-b) a second crystalline segment, as a crystalline segment, formed by the crystalline layer and surmounting the creep segment,; and each pad comprises a section whose maximum dimension is in a range of from 10 to 500 nm; andgrowing by epitaxy a crystallite on at least some of the pads and continuing the epitaxial growth of crystallites at least until coalescence of the crystallites carried by two adjacent pads, so as to form the nitride layer,{'sub': 'epitaxy', 'claim-text': {'br': None, 'i': T', '≥k', '×T, ...

NITRIDE SEMICONDUCTOR TEMPLATE, METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR TEMPLATE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR FREE-STANDING SUBSTRATE

There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer. 1. A nitride semiconductor template , comprising:a substrate having a front surface and a back surface opposite to the front surface;a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient: of the substrate; anda front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate,wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer in a case that only the front side semiconductor layer is formed without forming the back side semiconductor layer.2. The nitride semiconductor template according to claim 1 , wherein the thickness of the front side semiconductor layer is more than 20 μm.3. ...

ENHANCED DEFECT REDUCTION FOR HETEROEPITAXY BY SEED SHAPE ENGINEERING

A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region. 1. A heteroepitaxially grown structure , comprising:a cavity formed in a substrate has a shape with one or more surfaces and including a resistive neck region at an opening to a trench;a heteroepitaxially grown material formed on the substrate through the trench; andthe heteroepitaxially grown material including a first region in or near the cavity and a second region outside the first region.2. The structure as recited in claim 1 , wherein the second region is defect free.3. The structure as recited in claim 1 , wherein the one or more surfaces in the cavity face each other to direct defects to interact with each other.4. The structure as recited in claim 1 , further comprising a buffer layer lining the one more surfaces in the cavity.5. The structure as recited in claim 1 , wherein the one or more surfaces in the cavity include a continuous surface.6. The structure as recited in claim 1 , wherein the one or more surfaces constrain defects in four or more growth directions.7. The structure as recited in claim 1 , wherein the heteroepitaxially grown material forms a portion of an electronic device.8. The structure as recited in claim 1 , wherein the substrate includes an insulator claim 1 ,9. The structure as recited in claim 1 , wherein the substrate includes a metal.10. A hetero epitaxially grown structure claim 1 , comprising:a cavity formed in a crystalline semiconductor substrate having a shape with one or more surfaces and including a resistive neck region at an ...

DIAMOND SUBSTRATE

The crystal plane in the interior of the diamond substrate has a curvature higher than 0 kmand equal to or lower than 1500 kmby preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer. 1. A diamond substrate formed of diamond single crystals ,wherein the diamond substrate is one self-supported substrate as a flat plate shape in which a front surface and a rear surface of the diamond substrate are formed in parallel and evenly in appearance,a shape of the diamond substrate in an in-plane direction has a circular shape or a circular shape having an orientation flat plane,a diameter of the diamond substrate is equal to or larger than 0.4 inches and equal to or smaller than 8 inches, and{'sup': −1', '−1, 'a crystal plane in an interior of the diamond substrate has a curvature, and the curvature is higher than 0 kmand equal to or lower than 1500 km.'}2. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 400 km.3. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 200 km.4. The diamond substrate according to claim 1 , wherein the diameter is equal to or larger than 2 inches.5. The diamond substrate according to claim 1 , wherein the diameter is equal to or larger than 2 inches and equal to or smaller than 8 inches.6. The diamond substrate according to claim 1 , wherein the crystal plane has an (001) plane.7. The diamond substrate according to claim 1 , wherein a surface roughness Ra of a surface of the diamond substrate ...

EPITAXIAL GROWTH OF DEFECT-FREE, WAFER-SCALE SINGLE-LAYER GRAPHENE ON THIN FILMS OF COBALT

A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited. 1. A multilayer structure comprising:a silicon wafer, the silicon wafer comprising a front wafer surface, a back wafer surface, and a circumferential wafer edge joining the front wafer surface and the back wafer surface;a dielectric layer in contact with the front wafer surface of the silicon wafer;a layer comprising single crystalline cobalt in contact with the dielectric layer, the layer comprising single crystalline cobalt comprising a front cobalt layer surface, a back cobalt layer surface, and a bulk cobalt layer region between the front cobalt layer surface and the back cobalt layer surface, wherein the back layer cobalt surface is in contact with the dielectric layer; anda graphene layer in contact with the front cobalt layer surface of the layer comprising single crystalline cobalt.2. The multilayer structure of wherein the silicon wafer comprises a dopant selected from the group consisting of boron (p type) claim 1 , gallium (p type) claim 1 , phosphorus (n type) claim 1 , antimony (n type) claim 1 , and arsenic (n type) claim 1 , and any combination thereof.3. The multilayer structure of wherein the silicon wafer comprises boron (p type) dopant.4. The multilayer structure of wherein the silicon wafer comprises phosphorus (n type) dopant.5. The multilayer structure of wherein the silicon wafer comprises arsenic (n type) dopant.6. The multilayer structure of wherein the dielectric layer is selected from the group consisting of a silicon dioxide layer claim 1 , a silicon nitride layer claim 1 , a silicon oxynitride layer claim 1 , and any combination thereof.7. The multilayer structure of wherein the dielectric layer is a multilayer comprising at least two of a silicon dioxide layer claim 1 , a silicon ...

Semiconductor laminate structure and semiconductor element

Provided is a semiconductor laminate structure including a Ga 2 O 3 substrate and a nitride semiconductor layer with high crystal quality on the Ga 2 O 3 substrate, and also provided is a semiconductor element including this semiconductor laminate structure. In one embodiment, this semiconductor laminate structure includes a β-Ga 2 O 3 substrate including β-Ga 2 O 3 crystal and a principal surface inclined from a (− 201 ) surface to a [ 102] direction nd a nitride semiconductor layer including Al x Ga y In z N (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) crystal formed by epitaxial crystal growth on the principal surface of the β-Ga 2 O 3 substrate.

Epitaxial Structure and Growth Method of Group-III Nitrides

A Group-III nitrides epitaxial structure includes a Si substrate, and a Group-III nitrides layer disposed over the Si substrate, wherein an interface structure of “coexistence of Al atoms and SiN” between the Si substrate and the Group-III nitrides. Al atoms are configured to be absorbed to the Si substrate and connect the Group-III nitrides; and SiNare configured to release mismatch stress caused by heteroepitaxy. A fabricating method comprises: (1) providing a Si substrate; (2) forming an interface structure over a surface of the Si substrate , wherein the interface structure is arranged with both Al atoms and SiN, which are then cladded by an AlN epitaxial layer; and (3) growing Group-III nitrides over the interface structure wherein the Al atoms are configured to be absorbed to the Si substrate and connect the Group-III nitrides and the SiNis configured to release mismatch stress generated by heteroepitaxy. 1. A Group-III nitrides epitaxial structure , comprising:a Si substrate, anda Group-III nitrides layer disposed over the Si substrate, Al atoms, configured to be absorbed to the Si substrate and connect the Group-III nitrides layer; and', {'sub': x', 'y, 'SiN, configured to release mismatch stress caused by heteroepitaxy.'}], 'wherein an interface structure between the Si substrate and the Group-III nitrides layer is arranged with2. The structure of claim 1 , wherein:some regions of surface of the Si substrate are covered by the Al atoms;{'sub': x', 'y, 'some other regions of the surface of the Si substrate are covered by the SiN; and'}the interface structure is cladded inside by an AlN layer.3. The structure of claim 2 , wherein a thickness of the AlN layer His between around 1 nm and around 500 nm.4. The structure of claim 1 , wherein: the Group-III nitrides layer comprises at least one sub-layer of a Group-III nitride claim 1 , selected from a group consisting of AlN claim 1 , GaN claim 1 , InN claim 1 , AlGaN claim 1 , AlInN claim 1 , InGaN and (AlGa)InN ...

III-V OR II-VI COMPOUND SEMICONDUCTOR FILMS ON GRAPHITIC SUBSTRATES

A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound. 2. The composition of claim 1 , wherein the base layer comprises GaSb claim 1 , InAs claim 1 , AsSb claim 1 , SbBi claim 1 , Sb claim 1 , AlAsAb claim 1 , AlInSb claim 1 , or InAsSb.3. (canceled)4. (canceled)5. The composition of claim 1 , wherein the film or part of the film is doped.6. The composition of claim 1 , wherein the graphitic substrate is on a support.7. The composition of claim 1 , wherein the graphitic substrate is free of grain boundaries.8. The composition of claim 1 , wherein the film does not comprise AlN.9. The composition of claim 1 , wherein the base layer does not comprise GaN.10. The composition of claim 1 , wherein the film is grown using molecular beam epitaxy (MBE) claim 1 , migration-enhanced epitaxy (MEE) claim 1 , metal organic CVD (MOCVD) claim 1 , atomic layer molecular beam epitaxy (ALMBE) claim 1 , or a combination thereof.11. (canceled)12. (canceled)13. The composition of claim 1 , wherein the thickness of the base layer and the film is at least 250 nm.14. The composition of claim 1 , wherein the film comprises a plurality of group III-V compounds in different layers.15. The composition of claim 1 , wherein a lattice mismatch of the base layer is 2.5% or less to that of graphene.16. (canceled)17. A process for preparing the composition of claim 1 , the process comprising the steps of:(I) providing the base layer on said graphitic substrate, said base layer having a lattice mismatch of 2.5% or less to that of graphene; and(II) contacting said base layer with group III-V elements so as to grow the film comprising the group III-V compound.18. The process as claimed in claim 17 , wherein deposition of the base layer or formation of the film grown epitaxially on the graphitic substrate involves migration-enhanced ...

GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE

Provided is a method for manufacturing a group III nitride semiconductor substrate includes a substrate preparation step S of preparing a sapphire substrate, a heat treatment step S of performing a heat treatment on the sapphire substrate, a pre-flow step S of supplying a metal-containing gas over the sapphire substrate, a buffer layer forming step S of forming a buffer layer over the sapphire substrate under growth conditions of a growth temperature of 800° C. or higher and 950° C. or lower and a pressure of 30 torr or more and 200 torr or less, and a growth step S of forming a group III nitride semiconductor layer over the buffer layer under growth conditions of a growth temperature of 800° C. or higher and 1025° C. or lower, a pressure of 30 torr or more and 200 torr or less, and a growth speed of 10 μm/h or more. 1. A group III nitride semiconductor substrate comprising:a group III nitride semiconductor crystal,wherein the group III nitride semiconductor substrate has a film thickness of 400 μm or more,wherein exposed first and second main surfaces of the group III nitride semiconductor substrate, having a front and rear relationship, are both semipolar planes, andwherein a difference in half width of an X-ray Rocking Curve (XRC) between the first and second main surfaces, in which X-rays incident to each surface in parallel with a projection axis of a c-axis of the group III nitride semiconductor crystal are measured, is 100 arcsec or less.2. The group III nitride semiconductor substrate according to claim 1 ,wherein for both the half widths of the first and second main surfaces, the half widths of the X-ray Rocking Curve (XRC), in which X-rays incident in parallel with the projection axis of a c-axis of the group III nitride semiconductor crystal are measured, is 500 arcsec or less.3. A group III nitride semiconductor substrate comprising:a sapphire substrate; anda group III nitride semiconductor layer formed over the sapphire substrate and having an exposed ...

NUCLEATION STRUCTURE SUITABLE FOR EPITAXIAL GROWTH OF THREE-DIMENSIONAL SEMICONDUCTOR ELEMENTS

A nucleation structure for the epitaxial growth of three-dimensional semiconductor elements, including a substrate including a monocrystalline material forming a growth surface, a plurality of intermediate portions made of an intermediate crystalline material epitaxied from the growth surface and defining an upper intermediate surface, and a plurality of nucleation portions, made of a material including a transition metal forming a nucleation crystalline material, each epitaxied from the upper intermediate surface, and defining a nucleation surface suitable for the epitaxial growth of a three-dimensional semiconductor element. 1. A nucleation structure configured for the epitaxial growth of three-dimensional semiconductor elements , comprising:a substrate including a monocrystalline material forming a growth surface on which lies a plurality of nucleation portions made of a material comprising a transition metal, and a plurality of intermediate portions, each intermediate portion being made of an intermediate crystalline material epitaxied from the growth surface, thus having an alignment of the crystallographic orientations of its crystal lattice with those of the crystal lattice of the crystalline material of the substrate in at least one direction in the plane of the intermediate crystalline material and at least one direction orthogonal to the plane of the material, and defining an upper intermediate surface, on the opposite side to the growth surface;wherein each nucleation portion is made of a material including a transition metal forming a nucleation crystalline material, epitaxied from the upper intermediate surface, thus having an alignment of the crystallographic orientations of its crystal lattice with those of the crystal lattice of the intermediate material in at least one direction in the plane of the nucleation crystalline material and at least one direction orthogonal to the plane of the material, and defining a nucleation surface, on the opposite ...

Sic epitaxial wafer, manufacturing apparatus of sic epitaxial wafer, fabrication method of sic epitaxial wafer, and semiconductor device

A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

Substrate Structures and Methods

A process for separating a substrate from an epitaxial layer comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer. The method further comprises etching the lattice matching layer by one of a liquid or a vapor phase acid. The lattice matching layer is a metal alloy between the substrate and the epitaxial layer and serves as an etching release layer. The substrate can also be separated from an epitaxial layer by laser lift off process. The process comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer, directing laser light at the lattice matching layer, maintaining the laser light on the lattice matching layer for a sufficient period of time so that it is absorbed by free electrons in the lattice matching layer to allow decomposition of the lattice matching layer. 1. A process for separating a substrate from an epitaxial layer , comprising:forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer, wherein the lattice matching layer is a metal alloy;etching the lattice matching layer by one of a liquid or a vapor phase acid, wherein the metal layer is between the substrate and the epitaxial layer and serves as an etching release layer.2. The process of claim 1 , wherein the substrate comprises one of sapphire claim 1 , silicon or AIN material.3. The process of claim 1 , wherein the epitaxial layer comprises one of GaN or GaAs material.4. The process of claim 1 , wherein the acid comprises hydrochloric acid and trifluoroacetic acid.5. The process of claim 1 , wherein lattice matching layer comprises a first chemical element and a second chemical element claim 1 , and wherein at least one of the first chemical element and the second chemical element belongs to group four elements in the periodic table.6. The process of claim 6 , wherein the first chemical element comprises Zr and the second chemical element ...

METHOD FOR MAKING EPITAXIAL STRUCTURE

A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. A buffer layer is formed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are separated to form a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface. 1. A method for making epitaxial structure , the method comprising:placing a carbon nanotube layer on a first epitaxial growth surface of a substrate;epitaxially growing a buffer layer on the first epitaxial growth surface;growing a first epitaxial layer on the buffer layer;forming a second epitaxial growth surface by separating the substrate and the buffer layer; andgrowing a second epitaxial layer on the second epitaxial growth surface.2. The method of claim 1 , wherein the growing the buffer layer comprises forming a plurality of grooves on the buffer layer.3. The method of claim 2 , wherein the growing the buffer layer further comprises embedding the carbon nanotube layer in the plurality of grooves and exposing the carbon nanotube layer out of the buffer layer from the plurality of grooves.4. The method of claim 1 , wherein the carbon nanotube layer defines a plurality of apertures to expose a part of the first epitaxial growth surface to form a exposed part claim 1 , and the buffer layer is grown on the exposed part of the first epitaxial growth surface and through the plurality of apertures.5. The method of claim 4 , wherein sizes of the plurality of apertures are in a range from about 10 nanometers to about 500 micrometers.6. The method of claim 4 , wherein a dutyfactor of the carbon nanotube layer is in a range from about 1:4 to about 4:1.7. The method of claim 1 , wherein the carbon nanotube layer comprises a plurality of carbon nanotubes extending along a ...

Growth of Crystalline Materials on Two-Dimensional Inert Materials

A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. 1. A method of growing epitaxial GaN or AlN crystalline materials from two-dimensional inert materials consisting of:functionalizing a surface of a two-dimensional inert material and creating a functionalized surface;wherein the two-dimensional inert material is graphene;utilizing Atomic Layer Epitaxy;growing a nucleation layer from the functionalized surface;wherein the nucleation layer is grown via Atomic Layer Epitaxy; andgrowing a crystalline material from the nucleation layer;wherein the crystalline material is a monolayer crystalline epitaxial material;wherein the functionalizing a surface of a two-dimensional inert material further comprises pretreating the surface with ex-situ and/or in-situ pretreatment;{'sub': 2', '2', '2', '2', '3', 'x, 'wherein the pretreating the surface with ex-situ pretreatment comprises treating with one selected from the group consisting of XeF, plasma such as N, H, O, NH, NO, and wet chemicals;'}wherein the pretreating the surface with in-situ pretreatment is with a plasma;{'sub': 2', '2', '2', '2, 'wherein the plasma is one selected from the group consisting of H, N, mixture of Nand H, and ammonia; and'}wherein the monolayer crystalline material is a III-V compound semiconductor or a II-VI compound semiconductor.2. The method of growing epitaxial GaN or AlN crystalline materials from two-dimensional inert materials of wherein Raman measurements show a graphene 2D peak at 2719 cmafter the gallium nitride growth and X-ray diffraction analysis ...

Growth of Crystalline Materials on Two-Dimensional Inert Materials

A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.

Diamond Crystal

As the diamond crystal, a diamond crystal in a bulk form including dislocation concentration regions is formed. An interval between each of the dislocation concentration regions is from 10 nm to 4000 nm. The crystal orientation of crystal main face at the surface of the diamond crystal is any one of (100), (111), or (110). An external shape of the diamond crystal in a surface direction is a rectangle, a circle, or a circle having an orientation flat plane. The rectangle is set to have a side length of not less than 8.0 mm. The circle is set to have a diameter of not less than 8.0 mm. 1. A diamond crystal in a bulk form comprising dislocation concentration regions , wherein an interval between each of the dislocation concentration regions is from 10 nm to 4000 nm.2. The diamond crystal according to claim 1 , wherein a crystal orientation of crystal main face at a surface of the diamond crystal is any one of (100) claim 1 , (111) claim 1 , or (110).3. The diamond crystal according to claim 1 , wherein an external shape of the diamond crystal in a surface direction is a rectangle claim 1 , a circle claim 1 , or a circle having an orientation flat plane claim 1 , and in a case where the external shape is a rectangle claim 1 , the rectangle has a side length of not less than 8.0 mm claim 1 , and in a case where the external shape is a circle claim 1 , the circle has a diameter of not less than 8.0 mm.4. The diamond crystal according to claim 2 , wherein an external shape of the diamond crystal in a surface direction is a rectangle claim 2 , a circle claim 2 , or a circle having an orientation flat plane claim 2 , and in a case where the external shape is a rectangle claim 2 , the rectangle has a side length of not less than 8.0 mm claim 2 , and in a case where the external shape is a circle claim 2 , the circle has a diameter of not less than 8.0 mm. The present technology relates to a diamond crystal.A diamond crystal is expected to be an ultimate semiconductor material ...

Manufacturing method of gallium nitride substrate

A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

Mechanical Oscillator and Method for Producing Same

A material composed of an element having no catalytic action is epitaxially grown on a nickel layer to form a material layer. For example, iridium is epitaxially grown to form the material layer. Next, a cubic crystal is epitaxially grown on the material layer to form a crystal layer, and a laminate structure including the material layer and the crystal layer is patterned to form a vibrator shape part. The thickness of the material layer is controlled within a range in which lattice relaxation is not complete.

VAPOR PHASE GROWTH APPARATUS AND VAPOR PHASE GROWTH METHOD

A vapor phase growth apparatus according to an embodiment includes: a reactor; a supporter provided in the reactor, a substrate being capable of being placed on the supporter; a heater heating the substrate; a warpage measurement device measuring warpage of the substrate; a controller determining whether the measured warpage or a rate of change in the warpage is greater than a threshold value of the warpage or the rate of change in the warpage and stopping the heater on the basis of a determination result, the threshold value being stored in advance; a supplier supplying a process gas to the reactor; and an exhaust exhausting an exhaust gas from the reactor. 1. A vapor phase growth apparatus comprising:a reactor;a a supporter provided in the reactor, a substrate being capable of being placed on the supporter;a heater heating the substrate;a warpage measurement device measuring warpage of the substrate;a controller determining whether the measured warpage or a rate of change in the warpage is greater than a threshold value of the warpage or the rate of change in the warpage and stopping the heater on the basis of a determination result, the threshold value being stored in advance;a supplier supplying a process gas to the reactor; andan exhaust exhausting an exhaust gas from the reactor.2. The vapor phase growth apparatus according to claim 1 , wherein a plurality of the reactors is provided claim 1 , and further comprising:the supplier supplying a predetermined amount of process gas to each of the reactors;the exhaust exhausting the exhaust gas from the reactors; andthe controller stopping the heater in any one of the reactors.3. The vapor phase growth apparatus according to claim 2 , wherein the supplier supplies the predetermined amount of process gas to each of the reactors from a unified gas supply source.4. The vapor phase growth apparatus according to claim 1 , wherein the substrate is a silicon substrate claim 1 , andthe process gas includes trimethylgallium ...

ORIENTED ALUMINA SUBSTRATE FOR EPITAXIAL GROWTH

An oriented alumina substrate for epitaxial growth according to an embodiment of the present invention includes crystalline grains constituting a surface thereof, the crystalline grains having a tilt angle of 0.1° or more and less than 1.0° and an average sintered grain size of 10 μm or more. 1. An oriented alumina substrate for epitaxial growth , comprising:crystalline grains constituting a surface thereof,the crystalline grains having a tilt angle of 0.1° or more and less than 1.0° and an average sintered grain size of 10 μm or more.2. The oriented alumina substrate for epitaxial growth according to claim 1 ,wherein the crystalline grains constituting the surface has an average sintered grain size of 20 μm or more.3. The oriented alumina substrate for epitaxial growth according to claim 1 ,wherein the content of each of Na, Mg, Si, P, Ca, Fe, Ti, and Zn is 1,500 ppm or less.4. The oriented alumina substrate for epitaxial growth according to claim 2 ,wherein the content of each of Na, Mg, Si, P, Ca, Fe, Ti, and Zn is 1,500 ppm or less.5. The oriented alumina substrate for epitaxial growth according to claim 1 ,wherein the content of Mg is 15 ppm or more.6. The oriented alumina substrate for epitaxial growth according to claim 2 ,wherein the content of Mg is 15 ppm or more.7. The oriented alumina substrate for epitaxial growth according to claim 3 ,wherein the content of Mg is 15 ppm or more.8. The oriented alumina substrate for epitaxial growth according to claim 4 ,wherein the content of Mg is 15 ppm or more. The present invention relates to an oriented alumina substrate for epitaxial growth.As substrates for epitaxial growth for light-emitting devices such as light-emitting diodes (LEDs) and semiconductor devices, sapphire (single crystal α-alumina) substrates and composite substrates in which layers of semiconductor crystals such as GaN are grown on sapphire substrates are used. Substrates, for light-emitting devices, having a structure including an n-type GaN ...

ORIENTED ALUMINA SUBSTRATE FOR EPITAXIAL GROWTH

An oriented alumina substrate for epitaxial growth according to an embodiment of the present invention includes crystalline grains constituting a surface thereof, the crystalline grains having a tilt angle of 1° or more and 3° or less and an average sintered grain size of 20 μm or more. 1. An oriented alumina substrate for epitaxial growth , comprising:crystalline grains constituting a surface thereof,the crystalline grains having a tilt angle of 1° or more and 3° or less and an average sintered grain size of 20 μm or more.2. The oriented alumina substrate for epitaxial growth according to claim 1 ,wherein the content of each of Na, Mg, Si, P, Ca, Fe, Ti, and Zn is 1,500 ppm or less.3. The oriented alumina substrate for epitaxial growth according to claim 1 ,wherein the content of Mg is 15 ppm or more.4. The oriented alumina substrate for epitaxial growth according to claim 2 ,wherein the content of Mg is 15 ppm or more. The present invention relates to an oriented alumina substrate for epitaxial growth.As substrates for epitaxial growth for light-emitting devices such as light-emitting diodes (LEDs) and semiconductor devices, sapphire (single crystal α-alumina) substrates and composite substrates in which layers of semiconductor crystals such as GaN are grown on sapphire substrates are used. Substrates, for light-emitting devices, having a structure including an n-type GaN layer, multiple quantum well (MQW) layers, and a p-type GaN layer stacked, in this order, on such a substrate for epitaxial growth are mass-produced, the MQW layers including quantum well layers of InGaN layers and barrier layers of GaN layers alternately stacked.However, sapphire substrates are generally small in area and are expensive. The inventors report the use of oriented alumina substrates in place of sapphire substrates (see PTLs 1 and 2). In PTL 1, a substrate for a light-emitting device is produced by forming a GaN seed crystal layer on an oriented alumina substrate by an MOCVD method, ...