Mit einem Suchmaschinendienst kombiniertes Werbesystem und Verfahren zu dessen Durchführung

Werbesystem, das mit Suchmaschinendiensten kombiniert ist, das einen Client (100) und einen Server (200) umfasst, wobei der Server (200) einen serverseitigen Sendeempfänger (210), der ein Emotionssignal (SE) und einen Suchbegriff (SK) vom Client (100) empfängt; eine Suchmaschine (135, 240), die Suchfunktionen gemäß dem Suchbegriff (SK) durchführt und ein Suchergebnis (RS) erzeugt; einen Emotionsanalysator (220), der das Emotionssignal (SE) analysiert und einen Emotionsparameter (PE) eines Nutzers erzeugt, wobei der Emotionsparameter (PE) einen emotionalen Zustand des Nutzers repräsentiert; und eine Werbeplattform (230) umfasst, die nach zumindest einer empfohlenen Werbeanzeige (RA) sucht, die gemäß dem Emotionsparameter (PE) wie der emotionale Zustand des Nutzers klassifiziert ist; wobei der serverseitige Sendeempfänger (210) zudem das Suchergebnis (RS) und die zumindest eine empfohlene Werbeanzeige (RA) durch ein Netzwerk (150) an den Client (100) überträgt.

KLAPPRAD

Ein Kraftfahrzeug weist einen Aufbau auf, der dazu konfiguriert ist, einen demontierbaren Rahmen, ein Reserverad, eine demontierbare Kopfstütze und einen Wagenheber zu beherbergen. Der Rahmen, das Reserverad, die demontierbare Kopfstütze und der Wagenheber können zu einem Fahrrad zusammengebaut werden. Das Fahrrad weist folglich mindestens eine Komponente mit einem Doppelnutzen in einem Kraftfahrzeug auf.

Halbleitervorrichtung und dessen Herstellung

Eine Halbleitervorrichtung (200), die ein Substrat (210) und einen Gate-Stapel (260) umfasst, wobei der Gate-Stapel (260) mindestens einen Gate-Scheitel aufweist, der auf ein Gebiet in dem Substrat (210) unter dem Gate-Stapel (260) gerichtet ist. Die Halbleitervorrichtung (200) umfasst weiterhin eine Source-Struktur (240A), die mindestens einen Scheitel (232A) aufweist, der auf das Gebiet in dem Substrat (210) gerichtet ist, und eine Drain-Struktur (240B), die mindestens einen Scheitel (232B) aufweist, der auf das Gebiet in dem Substrat (210) gerichtet ist.

Halbleitereinrichtung

Halbleitereinrichtung, mit folgenden Merkmalen:ein Substrat (24) mit einer Anordnung aus Kontaktfeldern, die entlang eines Umfangs des Substrats angeordnet sind;ein Logikchip (28), der innerhalb der Anordnung aus Kontaktfeldern auf das Substrat aufgebracht ist; undNicht-Lötmittel-Hügelstrukturen (26), die auf weniger als alle verfügbaren Kontaktfelder, die entlang des Umfangs des Substrats angeordnet sind, aufgebracht sind,wobei die Anordnung aus Kontaktfeldern einen inneren Ring (56) aus Kontaktfeldern aufweist, der konzentrisch ist zu einem äußeren Ring (58) aus Kontaktfeldern, undwobei die Nicht-Lötmittel-Hügelstrukturen (26) auf nur abwechselnde Kontaktfelder in dem inneren Ring und dem äußeren Ring aufgebracht sind.

KINEMATISCHE VERBESSERUNGSVORRICHTUNG FÜR RADANORDNUNGEN

Ein Kraftfahrzeug enthält einen Keil, der durch Scherverbindungen an einem Konstruktionselement fixiert ist. Bei Anwendung einer nach hinten wirkenden Kraft wird der Keil abgeschert und zwischen das Konstruktionselement und eine Radanordnung bewegt, wo er rotierend einen Fahrzeugreifen verschiebt. Durch die nach hinten wirkende Kraft wird auch die Karosserie des Fahrzeugs seitlich verschoben. Der Keil ist durch eine Halteverbindung mit dem Konstruktionselement verbunden.

Gesichtsmaske mit eingebettetem Nasenpolster

Gesichtsmaske mit eingebettetem Nasenpolster (30), umfassend: Einen Maskenkörper (10) mit aufeinanderfolgender Außenschicht (11), Mittelschicht (13) und Innenschicht (15); sowie ein Nasenpolster (30), das an der Außenschicht (11) angeordnet ist, worin sich die Innenschicht (15) erstreckt und wieder umkehrt, um eine Innenschichtlasche (15') zu bilden, und worin das Nasenpolster (30) von der Innenschichtlasche (15') und der Außenschicht (11) gemeinsam umschlossen wird, was die Bildung eines erhöhten Bereichs (40) an dem Maskenkörper (10) ermöglicht, der in seiner Position zu dem Nasenpolster (30) passt.

HALBLEITERVORRICHTUNG UND VERFAHREN

Halbleitervorrichtung, die umfasst:ein erstes Substrat (100); undeine Durchkontaktierung (130), die sich durch das erste Substrat (100) hindurch erstreckt, wobei das erste Substrat (100) umfasst:mehrere erste bogenförmige Aussparungen (108a) neben der Durchkontaktierung (130) in einer ersten Region (104a) des ersten Substrats, wobei jede der bogenförmige Aussparungen (108a) der mehreren ersten bogenförmige Aussparungen eine erste Tiefe (Si) hat; undmehrere zweite bogenförmige Aussparungen (108b) neben der Durchkontaktierung (130) in einer zweiten Region (104b) des ersten Substrats, wobei jede der bogenförmigen Aussparungen (108b) der mehreren zweiten bogenförmigen Aussparungen eine zweite Tiefe (S2) aufweist, wobei die zweite Tiefe (S2) größer als die erste Tiefe (Si) istwobei die Durchkontaktierung (130) eine Metallschicht (110) neben dem ersten Substrat umfasst, wobei die Metallschicht (110) in der ersten Region (104a) kontinuierlich und in der zweiten Region (104b) diskontinuierlich ...

MEHRSCHICHTKANALSTRUKTUREN UND VERFAHREN ZUM FERTIGEN DERSELBEN IN FELDEFFEKTTRANSISTOREN

Eine Halbleiterstruktur umfasst einen ersten Stapel Halbleiterschichten, der über einem Halbleitersubstrat angeordnet ist, wobei der erste Stapel Halbleiterschichten eine erste SiGe-Schicht und eine Vielzahl von Si-Schichten, die über der ersten SiGe-Schicht angeordnet sind, umfasst und die Si-Schichten im Wesentlichen frei von Ge sind, und einen zweiten Stapel Halbleiterschichten, der benachbart zu dem ersten Stapel Halbleiterschichten angeordnet ist, wobei der zweite Stapel Halbleiterschichten die erste SiGe-Schicht und eine Vielzahl von zweiten SiGe-Schichten, die über der ersten SiGe-Schicht angeordnet sind, umfasst und wobei die erste SiGe-Schicht und die zweiten SiGe-Schichten unterschiedliche Zusammensetzungen aufweisen. Die Halbleiterstruktur umfasst ferner einen ersten Metall-Gate-Stapel, der wechselweise mit dem ersten Stapel Halbleiterschichten angeordnet ist, um ein erstes Bauelement auszubilden, und einen zweiten Metall-Gate-Stapel, der wechselweise mit dem zweiten Stapel Halbleiterschichten ...

Verpackungskiste und ein Verfahren zur Herstellung derselben

Die vorliegende Erfindung offenbart eine Verpackungskiste und ein Verfahren zur Herstellung derselben. Die Verpackungskiste weist eine untere Abdeckung und eine obere Abdeckung auf. Die obere Abdeckung wird in ein kombiniertes erstes Element und ein in einer ersten Nut des ersten Elements befestigtes zweites Element aufgeteilt. Dabei stützt das erste Element direkt die verpackten Gegenstände, und die erste Puffereigenschaft des ersten Elements ist besser als die zweite Puffereigenschaft des zweiten Elements. Die untere Abdeckung wird in ein kombiniertes drittes Element und ein in einer zweiten Nut des dritten Elements befestigtes viertes Element aufgeteilt. Dabei stützt das dritte Element direkt die verpackten Gegenstände, und die dritte Puffereigenschaft des dritten Elements ist besser als die vierte Puffereigenschaft des vierten Elements. Mit Hilfe des vorstehenden Verfahrens werden bei vorliegende Erfindung die Materialkosten für die Verpackungskiste besonders reduzieren, wodurch such ...

9SPANNUNGSVERFOLGUNGSSCHALTUNG UND VERFAHREN FÜR DEREN BETRIEB

Eine Spannungsverfolgungsschaltung umfasst einen ersten, zweiten, dritten und vierten Transistor. Der erste Transistor befindet sich in einem ersten Well und umfasst ein erstes Gate, einen ersten Drain und eine erste Source, die mit einer ersten Spannungsversorgung gekoppelt sind. Der zweite Transistor umfasst ein zweites Gate, einen zweiten Drain und eine zweite Source. Die zweite Source ist mit dem ersten Drain gekoppelt. Das zweite Gate ist mit dem ersten Gate und dem Padspannungsterminal gekoppelt. Der dritte Transistor umfasst ein drittes Gate, einen dritten Drain und eine dritte Source. Der vierte Transistor umfasst ein viertes Gate, einen vierten Drain und eine vierte Source. Der vierte Drain ist mit der dritten Source gekoppelt. Die vierte Source ist mit dem Padspannungsterminal gekoppelt. Mindestens der dritte Transistor befindet sich in einem zweiten Well, das sich von dem ersten Well unterscheidet und von dem ersten Well in einer ersten Richtung getrennt ist.

Halbleiterstruktur mit lokaler zu einer Gate-Struktur selbstjustierten Zwischenverbindungsstruktur und statische Speicherzelle diese beinhaltend und Verfahren diese zu bilden

Halbleiterstruktur, die eine Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen aufweist, die parallele Seitenwände aufweisen und sich auf einem Halbleitersubstrat 8 befinden und ein konstantes Rastermaß in einer horizontalen Richtung senkrecht zu den parallelen Seitenwänden aufweisen, wobei: eine der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen (76, 80, 36, 38, 73) ein U-förmiges Gate-Dielektrikum 80 und einen metallischen Gate-Leiter-Elektroden-Anteil 76 beinhaltet, der ein metallisches Material aufweist; und eine weitere der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen eine Kontakt-Durchkontakt-Struktur 73 beinhaltet, die das metallische Material aufweist und mit einem von einem Source-Bereich und einem Drain-Bereich 34 eines Transistors leitfähig verbunden ist, der sich auf dem Halbleitersubstrat befindet; und ein Abstand zwischen einer Außenwand des U-förmigen Gate-Dielektrikums und einer Seitenwand ...

Verfahren zum Austausch von Chloratomen auf einer Folienschicht

Die vorliegende Erfindung offenbart ein Verfahren zum Austauschen von Chloratomen auf einer Folienschicht. Genauer gesagt werden genügend Austauschionen zum Austauschen der Chloratome in einem Plasmaverfahren durch Reduzieren eines Volumenverhältnisses von einem Gas in einem Gasgemisch gebildet (d. h. die Folienschicht kann mit den Ionen, die durch Dissoziation des Gases gebildet werden, geätzt werden) und eine Dissoziation des Gasgemischs vermindert ferner die Ätzreaktion auf die Folienschicht in einem Verfahren zum Austausch der Chloratome. Im Vergleich zu einem herkömmlichen Verfahren mit reinem Sauerstoff kann die vorliegende Erfindung das Rückätzungsproblem beim Stand der Technik verbessern, um Auswirkungen auf eine elektrische Eigenschaft eines Dünnschichttransistors zu vermeiden, und bietet den Vorteil einer reduzierten Herstellungszeit für eine gesteigerte Produktionsausbeute.

Kinderwagen

Kinderwagen, umfassend:einen Kinderwagenrahmen (10), der zwei gegenüberliegend angeordnete seitliche Abstützanordnungen (100), einen vorderen Sitzplatz (102) und einen hinteren Sitzplatz (104) aufweist, die zwischen den beiden seitlichen Abstützanordnungen (100) ausgebildet sind;eine vordere Sitzanordnung (12), die zwischen den beiden seitlichen Abstützanordnungen (100) angeordnet ist und sich im vorderen Sitzplatz (102) befindet; undeine hintere Sitzanordnung (14), die abnehmbar und höheneinstellbar zwischen den beiden seitlichen Abstützanordnungen (100) angeordnet ist und sich im hinteren Sitzplatz (104) befindet, dadurch gekennzeichnet, dass jede seitliche Abstützanordnung (100) eine obere Seitenstange (1000), eine untere Seitenstange (1002), ein vorderes Bein (1004) und ein hinteres Bein (1006) aufweist, wobei ein oberer Endbereich (1004a) des vorderen Beins (1004) mit einem vorderen Endbereich (1000a) der oberen Seitenstange (1000) verbunden ist, ein mittlerer Bereich (1004b) des vorderen ...

Fotografieverfahren mit Blickerkennung

Ein Fotografieverfahren und ein zugehöriges Kamerasystem werden offenbart. Das Kamerasystem umfasst eine Kamera und einen Einzelbild-Zwischenspeicher. Das Verfahren umfasst die folgenden Schritte: Erfassen einer Mehrzahl von ersten Eingabebildern mittels einer ersten Kamera, wenn ein Blick-Aufnahmemodus des Kamerasystems aktiviert ist; Speichern der ersten Eingabebilder in dem Einzelbild-Zwischenspeicher; Durchführen einer Gesichtserkennung an einer Mehrzahl von Erfassungsbildern, die den ersten Eingabebildern zugeordnet sind, um ein menschliches Gesicht in den Erfassungsbildern zu detektieren; Durchführen einer Blickerkennung an den Erfassungsbildern um zu erfassen, ob ein Auge des erkannten menschlichen Gesichts in den Erfassungsbildern in Richtung hin zu der ersten Kamera blickt; und Auswählen von einem gespeicherten ersten Eingabebild oder von mehreren der gespeicherten ersten Eingabebilder aus dem Einzelbild-Zwischenspeicher als Ausgabebilder, wenn erfasst wird, dass das Auge des erfassten ...

SYNCHRONISIERUNG DES LACKIERABLAUFS MEHRARMIGER ROBOTER

Lackierroboter, die ein auf einem Fördergerät sich bewegendes Teil bearbeiten, werden synchronisiert, indem für jeden der Roboter eine Mastersequenz von Computerprogrammbefehlen zur kollisionsfreien Bewegung von Robotern längs zugeordneter Mastersequenzwege relativ zu dem sich bewegenden Teil erzeugt werden, wobei jeder der Mastersequenzwege Positionen des zugeordneten Roboters und des Fördergerätes an vorbestimmten Synchronisierungspunkten enthält, und jede der Mastersequenzen auf einem Steuerelement, das mit dem zugeordneten Roboter verbunden ist, abgearbeitet wird, um den zugeordneten Roboter zu bewegen, und ein aktueller Weg des zugeordneten Roboters und des Fördergerätes gegenüber dem Mastersequenzweg verglichen wird. Das Verfahren umfasst des Weiteren das Bedienen der Steuerelemente zum Einstellen der aktuellen Wege basierend auf dem Vergleich zwischen dem Mastersequenzweg und dem aktuellen Weg, und das Bedienen der Steuerelemente, um einen Bewegungsstopp des Fördergerätes anzufordern ...

Vliessubstrate

Die vorliegende Offenbarung betrifft zum Teil ein Vliessubstrat, das eine oder mehrere Schichten von Fasern umfasst. Das Vliessubstrat hat eine spezifische Oberfläche im Bereich von ungefähr 0,5 m2/g bis ungefähr 5 m2/g.

Verfahren zum Bilden von FinFET-Halbleitervorrichtungen unter Verwendung einer Austauschgatetechnik und die resultierenden Vorrichtungen

Ein hierin offenbartes Verfahren umfasst unter anderem ein Bilden einer gehobenen Isolationsstruktur zwischen einem ersten Fin und einem zweiten Fin, wobei die gehobene Isolationsstruktur teilweise einen ersten Raum und einen zweiten Raum zwischen dem ersten Fin bzw. dem zweiten Fin festlegt, und ein Bilden einer Gatestruktur um den ersten Fin und den zweiten Fin und die gehobene Isolationsstruktur, wobei wenigstens Bereiche der Gatestruktur in dem ersten Raum und dem zweiten Raum angeordnet sind. Eine anschauliche Vorrichtung umfasst unter anderem einen ersten Fin und einen zweiten Fin, eine gehobene Isolationsstruktur, die zwischen dem ersten Fin und dem zweiten Fin angeordnet ist, erste und zweite Räume, die durch die Fins und die gehobene Isolationsstruktur festgelegt werden, und eine Gatestruktur, die um einen Bereich der Fins und die Isolationsstruktur herum angeordnet ist.

Sicherheitsgurtbaugruppe

Eine Baugruppe beinhaltet eine Basis und eine Sicherheitsgurtverankerung. Die Sicherheitsgurtverankerung weist ein erstes Ende, das ein kreisförmiges Loch definiert, das durch die Basis schwenkbar getragen wird, und ein zweites Ende auf, das bezogen auf das erste Ende ortsfest ist. Die Baugruppe beinhaltet ein Schloss, das bezogen auf das zweite Ende ortsfest ist. Die Baugruppe beinhaltet ein pyrotechnisches Betätigungselement, das an der Basis befestigt ist. Die Baugruppe beinhaltet ein Verbindungsstück, das sich von dem pyrotechnischen Betätigungselement zu der Sicherheitsgurtverankerung erstreckt.

Nanosheet-Feldeffekttransistor mit einem zweidimensionalen halbleitenden Material

Strukturen für einen Feldeffekttransistor und Verfahren zum Bilden von Strukturen für einen Feldeffekttransistor. In einem Schichtstapel ist eine Mehrzahl von Kanalschichten angeordnet und ein Source/Drain-Bereich ist mit der Vielzahl von Kanalschichten verbunden. Eine Gatestruktur umfasst eine Mehrzahl von Abschnitten, die jeweils die Mehrzahl von Kanalschichten umgeben. Die Mehrzahl von Kanalschichten umfasst ein zweidimensionales halbleitendes Material.

Elektrische Antriebseinheit mit einem Gehäuse

Die Erfindung betrifft eine elektrische Antriebseinheit (10), insbesondere zum Verstellen beweglicher Teile im Kraftfahrzeug, mit einem Gehäuse (11), aufweisend ein metallenes Motorgehäuse (12), das einen Stator und einen Rotor (20) aufnimmt, und ein sich axial daran anschließendes Elektronikgehäuse (30), das eine Elektronikeinheit (89) aufnimmt, und einen offenen Flansch (22) des Motorgehäuses (12) abschließt, wobei das Elektronikgehäuse (30) ein erstes axiales Gehäuseteil (31) aus Kunststoff (122) aufweist, wobei im Kunststoff (122) mindestens ein Leiterstreifen (120) integriert ist, der eine elektrisch leitende Verbindung zwischen dem Motorgehäuse (12) und dem Elektronikgehäuse (30) bildet, um eine Masseverbindung herzustellen, wobei die elektrisch leitende Verbindung mittels einer Schraube (38) hergestellt ist, die durch eine Aufnahme (118) im Flansch (22) hindurch in den Kunststoff (122) eingeschraubt ist.

VERTIKAL AUSGERICHTETER KOMPLEMENTÄRER TRANSISTOR

Eine Halbleitervorrichtung nach der vorliegenden Offenbarung weist einen ersten Transistor und einen über dem ersten Transistor angeordneten zweiten Transistor auf. Der erste Transistor weist mehrere Kanalbereiche, die vertikal übereinander gestapelt sind, und ein erstes Source/Drain-Element, das an die mehreren Kanalelemente angrenzt, auf. Der zweite Transistor weist eine Finnenstruktur und ein zweites Source/Drain-Element, das an die Finnenstruktur angrenzt, auf. Die Halbleitervorrichtung weist ferner ein leitendes Element auf, das das erste Source/Drain-Element und das zweite Source/Drain-Element elektrisch verbindet.

SELBSTAUSGERICHTETE GATE-ISOLATION MIT ASYMMETRISCHER EINSCHNITT-ANORDNUNG

Ein Verfahren zum Bilden einer Halbleiterstruktur weist auf: Bilden von Fins über einem Substrat, Bilden eines die Fins umgebenden Bereichs für eine flache Grabenisolation über dem Substrat und Bilden von Nanosheet-Stapeln, die Kanäle für Nanosheet-Feldeffekttransistoren bereitstellen. Das Verfahren weist außerdem auf: Bilden eines Kanalschutzüberzugs über einem Teilbereich von Seitenwänden und einer oberen Oberfläche eines ersten Nanosheet-Stapels, der über einem ersten Fin ausgebildet ist, wobei der Kanalschutzüberzug des Weiteren über einem Teilbereich des Bereichs für eine flache Grabenisolation gebildet wird, der sich von den Seitenwänden des ersten Nanosheet-Stapels in Richtung zu einem zweiten Nanosheet-Stapel erstreckt, der über einem zweiten Fin ausgebildet ist. Das Verfahren weist des Weiteren auf: Bilden von Gate-Stapeln, die freiliegende Bereiche der Nanosheet-Stapel umgeben, Bilden einer asymmetrischen selbstausgerichteten Gate-Isolations-Struktur über dem Kanalschutzüberzug ...

Polymersysteme mit Mehrfachformgedächtniseffekt und Verfahren zum Ausbilden von Polymersystemen mit Mehrfachformgedächtniseffekt

Polymersystem umfassend:eine erste Polymerzweifachformgedächtnismaterialschicht undeine zweite Polymerzweifachformgedächtnismaterialschicht, welche mit der ersten Polymerzweifachformgedächtnismaterialschicht verbunden ist, um ein Zweischichtpolymermaterial auszubilden,wobei die erste Polymerzweifachformgedächtnismaterialschicht und die zweite Polymerzweifachformgedächtnismaterialschicht einen gut voneinander getrennten thermischen Übergang aufweisen, wobei die DMA-Kurve des Zweischichtpolymermaterials ein mittelhohes Plateau in dem Speichermodul zwischen der Glasübergangstemperatur der ersten Polymerzweifachformgedächtnismaterialschicht und der zweiten Polymerzweifachformgedächtnismaterialschicht, ein höheres Plateau bei einer Temperatur von weniger als der Glasübergangstemperatur der ersten Polymerzweifachformgedächtnismaterialschicht und der zweiten Polymerzweifachformgedächtnismaterialschicht sowie ein tieferes Plateau bei einer Temperatur oberhalb der Glasübergangstemperatur der ersten ...

Snoop-Filter mit ausschließlicher Inhaberschaft

Verfahren zum Herstellen einer Cache-Kohärenz in einem Multiprozessorsystem (10), welches folgendes umfaßt: Speichern nur derjenigen Einträge in einem Snoop-Filter (24), die einen exklusiven Zustand aufweisen, wobei ein Eintrag einen Zustand einer Cachezeile umfasst, und wobei ein exklusiver Zustand einen exklusiven Besitz eines Caches (12) an einer Zeile anzeigt, wobei ein Cache (12) eine Zeile exklusiv besitzt, wenn kein anderer Cache (12) eine Kopie der Zeile in einem exklusiven, modifizierten oder geteilten Zustand aufweist; Aktualisieren (330) eines Eintrags in dem Snoop-Filter (24), wenn eine Anforderung einen exklusiven Besitz einer Zeile, die mit dem Eintrag verknüpft ist, ändert; und Senden (370) einer Invalidierungsnachricht an alle Prozessoren (11), deren Cachezeilen von dem Snoop-Filter (24) verfolgt werden, wenn eine Schreibanforderung zu einem Fehlzugriff führt.

Druckmessgerät für einen Fahrradreifen

Druckmessgerät für einen Fahrradreifen, aufweisend: einen Anzeigeabschnitt (10), der eine Anzeige aufweist; einen Schaft (20), der sich von dem Anzeigeabschnitt (10) längs erstreckt; eine Lufteinlassvorrichtung (40), die in dem Inneren des Schaftes (20) angeordnet und mit dem Anzeigeabschnitt (10) verbunden ist; eine Druckmessvorrichtung (30), welche mit einem dem Anzeigeabschnitt (10) gegenüberliegenden Ende des Schaftes (20) verbunden ist und einen Raum (33) aufweist, der zu dem Inneren des Schaftes (20) eine Verbindungsöffnung aufweist, und ein Luftfreigabemittel (50), das in der Lufteinlassvorrichtung (40) zwischen dem Anzeigeabschnitt (10) und der Druckmessvorrichtung (30) angeordnet ist, wobei in dem Raum (33) ein Steuerelement (34) längsverschiebbar angeordnet ist, das zwei Schlitze (341, 343) aufweist, die in der Wand der beiden Enden des Steuerelements (34) ausgebildet sind und zu dem Raum (33) hin einen Durchgang bilden, und am Außenumfang des Steuerelements (34) ein Luftdichtungselement ...

COMBINED METHOD OF IMPROVING THE DEGREE OF CRISPNESS OF THE PACKING AND PREVENTING ADHERENCE OF CHIPS FRUIT BY VACUUM

Méthode combinée d'amélioration du conditionnement du degré de croustillance et de prévention d'adhérence de chips de fruits par vide poussé La présente invention concerne une méthode combinée d'amélioration du conditionnement du degré de croustillance et de prévention d'adhérence de chips de fruits par vide poussé, comprenant une sélection des matières premières, un lavage, un épluchage, et un dénoyautage, caractérisée en ce que l'on découpe les fruits; puis on réalise un prétraitement, ce dernier permet notamment une protection des couleurs, la conservation de la croustillance et de prévenir contre l'adhérence de chips de fruit. Puis la matière prétraitée est repêchée, puis égouttée pour permettre sa dessiccation sous vide poussé, suivie d'une dessiccation postérieure avec jet combinée par micro-ondes à impulsions négatives et vide poussé. Pour finir la matière est emballée en sachets. Les chips de fruits améliorées de l'invention sont de sensation friable en bouche, de teneur nutritive ...

SOLUTION CONCENTREE CONTAINING POLYAMIDE, ITS USE IN PROCESSES DEFABRICATION OF COMPOSITIONS CONTAINING POLYAMIDE AND COMPOSITIONS OBTAINED

METHOD OF FORMING A BARRIER COATING ON THE SURFACE OF A CONTAINER AND DEVICE THEREFOR

APPARATUS Of IMAGERY HAS X-RAYS

OF ISOPRENE RUBBER GRAFTED POLYBUTADIENE, METHOD FOR PREPARING SAME, AND VULCANIZATE AND COMPOUND MIXTURE RESULTING THEREFROM

ELECTRICAL CONTACTOR AND METHOD OF DISMANTLING PHASE SEPARATOR APPERTAINING ELECTRICAL CONTACTOR

CHALCOGENIDE CERAMICS PHOTOELECTRIC PROPERTIES AND METHOD FOR MAKING SAME

METHOD HARDNESS

LIGHT VALVE AND METHOD OF MAKING SAME

Leveling instrument has LED and photoelectric elements that are arranged on sides of tubular element, where light-dense areas are arranged on tubular element for shading portion of light emitted from LED on tubular element

La présente invention propose un niveau qui comprend au moins un tube à bulle, un élément d'émission de lumière et une paire d'éléments photoélectriques, l'élément d'émission de lumière et les éléments photoélectriques étant disposés respectivement de chacun des deux côtés du tube à bulle, et la lumière émise par l'élément d'émission de lumière et passant à travers la bulle étant reçue par les éléments photoélectriques, des parties opaques destinées à bloquer une partie de la lumière étant disposées sur le tube à bulle.

PROCEEDED OF REGULATION OF FILLING Of an INTERNAL COMBUSTION ENGINE

Procédé de régulation de remplissage d'un moteur à combustion interne (1) auquel de l'air de combustion est envoyé par un trajet d'admission (2), dans lequel deux organes de réglage (8, 9) sont commandés en ce qui conceme leur position, lesquels organes de réglage sont disposés l'un en aval de l'autre dans le trajet d'admission (2) et commandent chacun le débit d'air dans le trajet d'admission (2), un débit d'air (MF) entrant dans le trajet d'admission (2) et une pression de tubulure d'admission (P) régnant dans le trajet d'admission entre les organes de réglage (8, 9) sont mesurés, formant des valeurs de mesure, la position réelle des deux organes de réglage (8, 9) et la vitesse de rotation réelle du moteur à combustion interne (1) sont détectées et, dans un modèle numérique pouvant être inversé, des valeurs de modèle pour le débit d'air (MF) et la pression de tubulure d'admission (P) sont déterminées et un ajustement du modèle a lieu via les valeurs de mesure et les valeurs de modèle ...

INTELLIGENT REAL-TIME RESPONSE TO CHANGES OF EQUILIBRIUM OF AN OILFIELD

La présente invention concerne des systèmes, des procédés et des supports lisibles par ordinateur pour surveiller et gérer en temps réel et de manière intelligente les changements d'équilibre d'un champ pétrolifère afin d'optimiser la production des hydrocarbures souhaités et la viabilité économique du champ. Dans certains exemples, un procédé peut impliquer la génération, sur la base d'une topologie d'un champ de puits, d'un graphe respectif pour les puits, chaque graphe respectif comprenant des dispositifs de calcul couplés à un ou plusieurs capteurs et/ou actionneurs. Le procédé peut impliquer la collecte, par l'intermédiaire des dispositifs de calcul, des paramètres respectifs associés à un ou plusieurs dispositifs de calcul, capteurs, actionneurs et/ou modèles, et l'identification d'un état mesuré associé aux dispositifs de calcul, capteurs, actionneurs et/ou modèles. En outre, le procédé peut impliquer la génération automatique, sur la base du graphe respectif et des paramètres respectifs ...

DIAPHRAGM OF BEAM AND DEVICE Of IMAGERY HAS X-RAYS

Avec pour but de proposer un diaphragme de faisceau ayant une grande valeur maximale d'ouverture d'ouverture pour une dimension de profil limitée, le diaphragme de faisceau comprend une paire de bagues de commande ayant des ouvertures coaxiales pour le passage de rayons X à travers elles et étant opposées l'une à l'autre axialement à travers un espacement et pouvant tourner coaxialement indépendamment l'une de l'autre, une lame positionnée entre la paire de bagues de commande, et des moyens d'ajustement de position qui, en fonction d'une rotation relative de la paire de bagues de commande, provoquent l'approche et l'éloignement de la lame d'un axe commun des ouvertures de façon à décrire une plan sectoriel dont le rayon augmente ou diminue de manière continue.

A spring holding assembly that is used for vehicle hasp actuator mechanism

Un mécanisme d'actionnement d'un ensemble verrou de véhicule comporte un moteur électrique ayant un arbre de sortie. Le mécanisme comporte également une vis sans fin couplée à l'arbre de sortie. Le mécanisme comporte en outre un engrenage à vis sans fin entraîné par la vis sans fin. Le mécanisme comporte en outre un ressort couplé de manière fonctionnelle à l'engrenage à vis sans fin et à un logement de verrou, le ressort ayant une première branche s'étendant à travers un orifice défini par l'engrenage à vis sans fin et une deuxième branche s'étendant dans un trou de réception défini par le logement, la première branche comportant un premier segment s'étendant le long d'un axe de première branche et un deuxième segment orienté selon un angle qui n'est pas parallèle à l'axe de première branche, le deuxième segment étant en contact avec une face de l'engrenage à vis sans fin afin d'empêcher le retrait du ressort.

MULTIPLE GLAZING HAS VARIABLE DIFFUSION BY LIQUID CRYSTALS, ITS MANUFACTORING PROCESS

La présente invention propose un vitrage multiple à diffusion variable par cristaux liquides (100), présentant des première et deuxième feuilles de verre plan flotté (1, 2) maintenues sur le bord de leurs faces internes (11, 21) par un joint (7), notamment en une matière de joint donnée, notamment essentiellement organique, des première et deuxième électrodes (3, 4), une couche (5) de cristaux liquides d'épaisseur moyenne E comprise entre 5 et 15 µm en incluant 5 µm et excluant 15 µm et incorporant des espaceurs (6). L'épaisseur de chacune des première et deuxième feuilles de verres est inférieure ou égale à 6,5 mm et chacune des faces internes revêtues des première et deuxième électrodes présentent une note de défauts dioptriques, exprimée en millidioptrie, inférieure ou égale à 2+2E/3 où l'épaisseur E de cristaux liquides est en µm. L'invention concerne aussi le procédé de fabrication d'un tel vitrage ...

DEVICE FOR DETECTING THE POSITION OF A MOTOR ROTOR

Ce dispositif est placé sur un stator (5). Selon l'invention : ledit dispositif de détection comprend un cadre de fixation (2), une carte à circuits imprimés (3), et un composant à effet Hall ; ledit cadre de fixation (2) comprend une partie de positionnement et une attache, une partie de fixation de connexion, une partie de fixation de carte à circuits imprimés (3), et une partie de fixation de composant à effet Hall ; ledit dispositif de détection est connecté par l'intermédiaire de ladite partie de positionnement et de ladite attache ; ladite partie de fixation de connexion est destinée à fixer un cordon d'alimentation connecté à une bobine d'enroulement du stator (5) ; ladite carte à circuits imprimés (3) est placée sur le cadre de fixation (2) par l'intermédiaire de la partie de fixation de carte à circuits imprimés (3) ; et ledit composant à effet Hall est placé sur ledit cadre de fixation (2) via ladite partie de fixation de composant à effet Hall et est connecté à ladite carte à ...

SLOT LINERS FOR AN ELECTRIC MACHINE

Caniveau d'encoche (40) pour un stator et un rotor d'une machine électrique (10), comportant un corps (54) conçu pour être logé dans une encoche du stator et/ou dans une encoche (48) du rotor, et s'étendant dans la longueur, d'une première extrémité (58) à une seconde extrémité opposée (60), et dans la largeur, d'un premier bord (62) à un second bord opposé (64) et comprenant un segment intérieur (70) et un premier et un second segments extérieurs (72, 74) qui s'étendent sur la longueur du corps (54). Les premier et second segments extérieurs (72, 74) bordent le segment intérieur (70) de telle manière que le segment intérieur (70) s'étende entre les premier et second segments extérieurs (72, 74) sur la longueur du corps (54). Le segment intérieur (70) comprend une matière différente de la matière des premier et second segments extérieurs (72, 74), de façon à présenter une conductivité thermique plus grande que celle des premier et second segments extérieurs (72, 74).

ADDITIVE Of MAGNESIUM HALIDE, CATALYTIC COMPONENT AND CATALYST INCLUDING/UNDERSTANDING IT, AND THEIR PREPARATION

La présente invention concerne un produit d'addition d'halogénure de magnésium. Elle concerne également un constituant catalytique comprenant ledit produit d'addition d'halogénure de magnésium, un catalyseur de polymérisation d'oléfines comprenant ledit constituant catalytique. Application : utilisation du produit d'addition d'halogénure de magnésium pour la préparation du constituant catalytique, utilisation du constituant catalytique dans un catalyseur pour la polymérisation d'oléfines et utilisation du catalyseur dans la polymérisation d'oléfines ; et procédé de polymérisation d'oléfines.

MANUAL DEVICE OF SAMPLING PREVENTING the DEFORMATION OF the SAMPLER Of SAMPLE BY FRICTION AND PROCESS Of OBTAINING a SAMPLE

Dispositif manuel de prélèvement d'échantillon empêchant la déformation du préleveur d'échantillon par frottement et procédé d'obtention d'un échantillon. Selon l'invention, la surface de prélèvement d'échantillon par frottement (7) est incurvée et s'étend de façon continue et régulière, à la manière d'un bout de doigt, un préleveur d'échantillon (8) étant appliqué sur ladite surface de prélèvement (7).

METHOD HYDRODESULFURIZATION OF A OLEFINIC GASOLINE.

La présente invention concerne un procédé de traitement d'une essence contenant des composés soufrés, des oléfines et des dioléfines, comprenant les étapes suivantes: a) on fractionne l'essence en au moins : • une coupe essence légère LCN; • une coupe essence intermédiaire MCN primaire; et • une coupe essence lourde HHCN primaire; b) on désulfure la coupe essence intermédiaire MCN primaire seule de manière à produire une coupe essence intermédiaire MCN primaire au moins partiellement désulfurée ; c) on désulfure la coupe essence lourde HHCN primaire seule de manière à produire une coupe lourde HHCN primaire au moins partiellement désulfurée; d) on envoie en mélange la coupe essence intermédiaire MCN primaire partiellement désulfurée et la coupe lourde HHCN primaire partiellement désulfurée dans une colonne de séparation de manière à séparer un flux gazeux contenant de l'hydrogène et de l'H2S, une coupe essence intermédiaire MCN secondaire à basses teneurs en soufre et en mercaptans et une ...

PLANE LAMP HAS DISCHARGE.

DEVICE Of LIGHTING HAS Electroluminescent diodes

THERMOSETTING, PREPARATION METHOD, POLYISOPRENE AND RUBBER PRODUCT RESULTING FROM THE VULCANIZATION THEREOF

LIGHTING LAMINATED GLAZING HAS ELECTROLUMINESCENT DIODES AND SA MANUFACTURE

ACCESSORY FOR WICK AND WICK-BASED ASSEMBLY

Un accessoire pour mèche (500) destiné à une mèche (600) contient un manchon doté d'une cavité de logement traversant le manchon et un élément limitant (550) alors qu'un trou limitant traverse l'élément limitant (550). Le manchon contient une première partie de butée servant à empêcher l'élément limitant (550) de traverser la cavité de logement et l'élément limitant (550) contient une première partie de paroi à trous formant une première paroi à trous qui donne au trou limitant un diamètre minimal de trou, et une seconde partie de paroi à trous formant une seconde paroi à trous qui donne au trou limitant un diamètre maximal de trou. L'élément limitant (550) est logé au moins en partie dans la cavité de logement, et une direction selon laquelle le trou limitant traverse l'élément limitant (550) est parallèle à la cavité de logement lorsque l'élément limitant (550) est arrêté par la première partie de butée.

D-C TRACTION MOTOR

SECTION OF CONCRETE COMPOSED OF SEVERAL PORTIONS FOR A MAST

L'invention concerne une section (10) de béton prévue pour former un mât (1) pour une éolienne (2), ladite section (10) s'étendant le long d'une direction longitudinale et comprenant une première bride et une seconde bride, dans laquelle la section (10) est composée de plusieurs parties (11, 12, 13) réparties le long de la direction longitudinale, lesdites parties comprenant au moins : -une première partie (11) avec une première extrémité et une seconde extrémité opposées entre elles dans la direction longitudinale, ladite première partie (11) comprenant la première bride (11') au niveau de sa première extrémité, la seconde extrémité de la première partie (11) est raccordée par une interface de raccordement (14) à une autre partie prolongeant ladite première partie (11), et - une seconde partie (12) avec une première extrémité (12a) et une seconde extrémité (12b) opposées entre elles dans la direction longitudinale, ladite seconde partie (12) comprenant la seconde bride (12') au niveau ...

REACTOR AND ALKYLATION PROCESS USING THE REACTOR

La présente invention prévoit un réacteur pour au moins deux matières liquides, comportant un logement de réacteur fermé (1) ; un tube d'alimentation (10) ayant des entrées de matière liquide (11, 12) destinées à recevoir des matières liquides correspondantes de manière respective ; un tube de distribution (20) qui communique avec le tube d'alimentation et s'étendant dans le logement de réacteur, le tube de distribution étant pourvu d'une pluralité de trous de distribution (21) dans la zone s'étendant dans le logement de réacteur ; un lit rotatif (30) sous la forme d'un cylindre creux, qui est disposé dans le logement de réacteur par l'intermédiaire d'un mécanisme de fixation (40), en divisant ainsi une cavité intérieure du logement de réacteur en une zone centrale (45) et une zone extérieure (46), le lit rotatif étant capable d'être entraîné en rotation par un mécanisme d'entraînement (42) ; et une sortie de matière (6) prévue dans une partie inférieure du logement de réacteur pour une ...

DEVICE FOR the APPLICATION OF COSMETIC PRODUCTS

PANEL HAS ELECTROLUMINESCENT DIODES

L'invention a pour objet un panneau lumineux (100) comportant : - une feuille transparente (1) en verre minéral ayant une face avant (11), et une face arrière (12) et une tranche, - une pluralité de diodes électroluminescentes (2) agencées en regard de la tranche ou dans un trou en bordure de l'une des faces, pour une propagation de la lumière dans l'épaisseur de la feuille, - des moyens de diffusion (3) de la lumière guidée, pour une extraction de ladite lumière via la face avant (11), qui sont des moyens de diffusion en surface (11) occupant la majorité de la face avant, ou des moyens de diffusion en volume dont la surface projetée sur la face avant occupe la majorité de la face avant, - un réflecteur spéculaire (4), en regard des moyens de diffusion et sur la face arrière, et avec un coefficient de réflexion spéculaire au moins égal à 80% pour l'ensemble des longueurs d'onde du spectre d'émission des diodes.

METHOD AND SYSTEM FOR LOCATING DEFECTS ON AN ELECTRIC CABLE

La présente invention concerne un procédé de diagnostic de défauts sur un câble comportant les étapes suivantes : - Mesure des paramètres S du câble ; - Détermination de l'impédance apparente du câble en fonction de la position z le long du câble, d'une part, à partir d'une extrémité du câble Zl(z), et d'autre part, à partir de l'autre extrémité du câble Zr(z) ; - Détermination d'une estimation de la résistance linéique R(z) du câble en fonction de la position z le long du câble : - Détection d'un défaut sur un câble lorsque la résistance linéique R(z) estimée s'éloigne d'une valeur de référence.

A COMPACT TWO-MIRROR

Poudrier à plusieurs miroirs comprenant : un cadre supérieur (11), un cadre inférieur (12) et un cadre intermédiaire (13) reliés par imbrication de telle manière que chacun du cadre supérieur (11) et du cadre inférieur (12) puisse osciller indépendamment à l'écart du cadre intermédiaire (13) ; le cadre intermédiaire (13) portant une surface ou des surfaces de support de poudre cosmétique ; et le cadre supérieur (11) portant un premier miroir (20) faisant face à la surface ou aux surfaces et le cadre inférieur (12) portant un deuxième miroir (20a) faisant face à la surface de support.

STRUCTURE OF COSMETIC CONTAINER OF TYPE HAS BALL

STATOR AND METHOD OF WINDING WIRE THEREFOR

Selon l'invention, ce stator (1) comprend : un noyau de stator (3), une pluralité d'enroulements (4) et une plaque d'isolation (5), une pluralité de dents (7) en position de saillie par rapport audit noyau de stator (3), lesdits enroulements (4) étant intégrés dans ladite encoche (8) et étant enroulé autour de ladite dent, ladite plaque d'isolation (5) étant placée à la surface dudit noyau de stator (3), une pluralité de cylindres étant placée sur ladite plaque d'isolation (5), une ligne de transition d'un enroulement en phase entre deux dents (7) adjacentes étant accrochée audit cylindre (6) ; et une pluralité de mécanismes de support étant disposée sur ledit cylindre.

A METHOD FOR TRACKING THE TIME CONCENTRATION PROFILE OF PARTICULATE MATERIALS IN AN AREA.

Méthode pour tracer le profil de concentration de particules dans une zone selon laquelle il est prévu de définir le nombre d'analyseurs de matières particulaires dans la zone supervisée à 3, de former une matrice de concentration (Etape 3) en fonction de la position des instruments des analyseurs de matières particulaires, de remplir les données de la matrice avec les valeurs de concentration obtenue par chacun des analyseurs, d'utiliser une méthode d'interpolation de Laplace (Etape 4) basée sur les données de concentration des analyseurs supervisant afin de générer dans la matrice des valeurs de concentration qui ne sont pas obtenues par les analyseurs supervisant, et de lisser les données (Etape 6) dans la matrice de concentration à l'aide d'une interpolation bicubique, puis d'associer chaque valeur de concentration dans la matrice à une valeur de couleur correspondante, et de tracer un profil de distribution de concentration de matières particulaires pour la zone.

RADIO FREQUENCY MICROELECTROMECHANICAL VARIABLE SWITCH

La présente invention a pour objet commutateur microélectromécanique radiofréquence (généralement désigné par les acronymes MEMS RF) ainsi qu'un procédé permettant de réaliser un tel commutateur.

PROCESS FOR THE SYNTHESIS OF ESTERS AND SAID CATALYST SYNTHESIS

L'invention porte sur un procédé de synthèse d'esters à partir d'alcools par couplage déshydrogénant en présence d'un catalyseur de formule 1 ainsi que sur l'utilisation de catalyseurs de formule 1 pour la synthèse d'esters. L'invention porte également sur de nouveaux catalyseurs ainsi que leurs utilisations. Formule 1 : ...

SYSTEM OF PURGING FOR TURBINE HAS COMBUSTION

Un système de purge par solvant (160/200/300) est couplé à un ensemble de chambres de combustion (116) couplé en communication fluidique avec au moins une source de carburant (134/144). Le système de purge par solvant comporte un système de purge par vapeur (200/300) incluant au moins un collecteur de vapeur (204) couplé en communication fluidique avec l'ensemble de chambres de combustion. Le système de purge par solvant comporte également un système de purge par solvant chimique (160) incluant au moins un collecteur de solvant chimique (164) couplé en communication fluidique avec l'ensemble de chambres de combustion.

NON-ISOLATED SWITCHING POWER SUPPLY FOR A LIGHT STRIP HIGH VOLTAGE

Une alimentation à découpage non isolée pour un bandeau lumineux haute tension est divulguée. L'alimentation à découpage non isolée comprend un circuit redresseur à pont intégral, un contacteur Q2, un condensateur électrolytique C2, un inducteur de stockage d'énergie L1, une diode D4 et un circuit PWM. Une sortie de signal PWM du circuit PWM est connectée à une électrode de contrôle du contacteur Q2, le contacteur Q2 et la diode D4 sont en connexion série entre les deux sorties du circuit redresseur à pont intégral, une électrode négative du tube contacteur D4 est connectée à une sortie positive +VCC du circuit redresseur à pont intégral, et l'inducteur de stockage d'énergie L1 est connecté entre une électrode négative du condensateur électrolytique C2 et une électrode positive de la diode D4. L'alimentation à découpage non isolée utilise une structure de circuit entièrement nouvelle ; la tension de l'inducteur de stockage d'énergie L1 est maintenue à 130V grâce à une modulation à largeur ...

METHOD FOR MAKING SHELL MOLD

L'invention concerne un procédé de fabrication de moule (1) carapace à plusieurs couches (2, 3, 4, 5) dont au moins une couche (2) de contact, à partir d'un modèle (6) de pièce à fabriquer en cire ou autre matériau semblable, le procédé comprenant une étape de trempage du modèle (6) dans une barbotine de contact formant la couche (2) de contact et comprenant un liant inorganique ou organique et une poudre, dans lequel la poudre est un mélange mullite-zircone.

PLANE LAMP HAS COPLANAR DISCHARGE AND USES

Lampe plane à décharge (100) transmettant un rayonnement dans l'ultraviolet ou le visible, comprenant : - des premier et deuxième éléments verriers plans (2, 3) ou sensiblement plans maintenus sensiblement parallèles entre eux et délimitant un espace interne (10) rempli de gaz (71), le premier et/ou le deuxième élément verrier étant en un matériau transmettant ledit rayonnement, - au moins une première électrode (41 a) et au moins une deuxième électrode (51a) lesquelles sont susceptibles d'être à des potentiels distincts et d'être alimentées par une tension alternative (V1), les première(s) et deuxième(s) électrodes étant associées à une ou des faces principales (21) du premier élément verrier, les première(s) et deuxième(s) électrodes étant essentiellement allongées et sensiblement parallèles entre elles, et séparées par au moins un espace dit interélectrodes de largeur donnée dite d1 sensiblement constante, caractérisée en ce qu'elle comprend en outre au moins une troisième électrode ...

A COMPACT FOLDING-COMPONENT

Un poudrier à composants pliants se compose d'une combinaison de composants de base (1), d'insert (2) et de capuchon (3), une première charnière (4) reliant l'insert (2) à la base (1) et une deuxième charnière (5) reliant l'insert (2) au capuchon (3), au moins l'une de ces charnières (4, 5) étant une charnière mobile.

POWER PLANT ULTRASILENCIEUSE CONTAINER CLASS

Verfahren zum Herstellen einer Halbleitervorrichtung und eine Halbleitervorrichtung

In Übereinstimmung mit einem Aspekt der vorliegenden Offenbarung, bei einem Verfahren zum Herstellen einer Halbleitervorrichtung, wird eine Finnenstruktur, in der erste Halbleiterschichten und zweite Halbleiterschichten abwechselnd gestapelt sind, gebildet. Eine Opfer-Gate-Struktur wird über der Finnenstruktur gebildet. Eine erste Deckschicht wird über der Opfer-Gate-Struktur gebildet, und eine zweite Deckschicht wird über der ersten Deckschicht gebildet. Eine epitaktische Source/Drain-Schicht wird gebildet. Nachdem die epitaktische Source/Drain-Schicht gebildet wurde, wird die zweite Deckschicht entfernt, wodurch ein Spalt zwischen der epitaktischen Source/Drain-Schicht und der ersten Deckschicht gebildet wird, aus dem ein Teil der Finnenstruktur freigelegt wird. Ein Teil der ersten Halbleiterschichten wird in dem Spalt entfernt, wodurch Räume zwischen den zweiten Halbleiterschichten gebildet werden. Die Räume werden mit einem ersten Isoliermaterial gefüllt.

Zusammengeführte Säulenstrukturen und Verfahren zum Erzeugen von Layoutdiagrammen davon

Ein Verfahren zum Erzeugen eines Layout-Diagramms einer leitfähigen Leitungsstruktur umfasst Folgendes: Bestimmen, dass eine erste Menge von ersten bis vierten kurzen Säulenmustern (die Abschnitte einer Metallisierungsschicht M(i) darstellen und in Bezug auf ein Netz angeordnet sind) einen Mindesttrennungsabstand in Alpha-Richtung für die Leitungsführung in Querrichtung verletzt, wobei (1) das Netz orthogonale Alpha- und Beta-Leiterbahnen aufweist und (2) die kurzen Säulenmuster lange Achsen aufweisen, die im Wesentlichen mit einer ersten von den Alpha-Leiterbahnen zusammen auf einer Leiterbahn ausgerichtet sind und einen ersten Abstand (der Trennung in Alpha-Richtung zwischen unmittelbar benachbarten Elementen der ersten Menge) aufweisen, der kleiner als der TVR-Abstand ist; und Zusammenführen von Paarungen von den ersten & zweiten und dritten & vierten kurzen Säulenmustern in entsprechende erste und zweite mittlere Säulenmuster, die einen zweiten Alpha-Richtungstrennungsabstand aufweisen ...

BILDSENSOR MIT PADSTRUKTUR

Die vorliegende Offenbarung betrifft einen Bildsensor mit einer Padstruktur, die während eines Front-End-Of-Line-Prozesses gebildet wird. Die Padstruktur kann vor dem Bilden von Rückseiten-Deep-Trench-Isolationsstrukturen und Metallgitterstrukturen gebildet werden. Eine Öffnung wird auf einer Rückseite des Bildsensorbauteils gebildet, um die eingebettete Padstruktur freizulegen und elektrische Verbindungen zu bilden.

Chemische Reinigung einer Halbleitervorrichtung

Ein Verfahren zum Ausbilden einer Halbleitervorrichtung umfasst ein Ausbilden eines leitfähigen Merkmals in einer ersten dielektrischen Schicht, ein Ausbilden einer oder mehrerer dielektrischer Schichten über der ersten dielektrischen Schicht, und ein Ausbilden einer Durchkontaktierungsöffnung in der einen oder den mehreren dielektrischen Schichten, wobei eine Unterseite der Durchkontaktierungsöffnung das leitfähige Merkmal freilegt. Das Verfahren umfasst ferner ein Reinigen der Durchkontaktierungsöffnung unter Verwendung einer chemischen Mischung, und ein Spülen der Durchkontaktierungsöffnung unter Verwendung eines mit basischen Ionen dotierten Wassers nach dem Reinigen der Durchkontaktierungsöffnung.

Integrierte Fan-Out-Packages und Verfahren zu deren Herstellung

Eine Halbleiterstruktur weist Folgendes auf: einen Die, der in ein Formmaterial eingebettet ist, wobei der Die auf einer ersten Seite Die-Verbindungselemente hat; eine erste Umverteilungsstruktur auf der ersten Seite des Dies, wobei die erste Umverteilungsstruktur über die Die-Verbindungselemente elektrisch mit dem Die verbunden ist; eine zweite Umverteilungsstruktur auf einer zweiten Seite des Dies, die der ersten Seite entgegengesetzt ist; und ein thermisch leitfähiges Material in der zweiten Umverteilungsstruktur, wobei der Die zwischen das thermisch leitfähige Material und die erste Umverteilungsstruktur geschichtet ist und das thermisch leitfähige Material durch die zweite Umverteilungsstruktur verläuft und elektrisch isoliert ist.

Elektrische Antriebseinheit mit einem Polgehäuse und einem Elektronikgehäuse

Die Erfindung betrifft eine Elektrische Antriebseinheit (10), insbesondere zum Verstellen beweglicher Teile im Kraftfahrzeug, mit einem Gehäuse (11), aufweisend ein metallenes Polgehäuse (12), das einen Stator und einen Rotor (20) aufnimmt, und ein separat gefertigtes, sich axial daran anschließendes Elektronikgehäuse (30), das eine Elektronikeinheit (89) aufnimmt, wobei im Inneren des Elektronikgehäuses (30) mindestens ein Kontaktelement (100) integriert ist, das eine elektrisch leitende Verbindung zwischen dem Polgehäuse (12) und dem Elektronikgehäuse (30) bildet, um eine Masseverbindung herzustellen, wobei das Kontaktelement (100) mit mindestens einem freien axialen Ende (102) an der Innenseite (15) des Polgehäuses (12) federnd anliegt, und das freie Ende (102) ausgehend von einem sich quer zur Rotorachse (20) erstreckenden Befestigungsbereich (106) des Kontaktelements (100) aus der Tangentialrichtung (26) axial nach unten umgebogen ist, so dass es sich näherungsweise in Axialrichtung ...

Infrarot-Bandpassfilterstruktur und Infrarotbandpassfilter mit dieser Infrarot-Bandpassfilterstruktur

Die Erfindung betrifft eine Infrarot-Bandpassfilterstruktur, die aus einer Vielzahl von SiAl:H-Schichten (21) und einer Vielzahl von Schichten (22) mit niedrigerem Brechungsindex besteht, die abwechselnd gestapelt werden, wobei die Schichten (22) mit niedrigerem Brechungsindex ein Oxid sind, wobei die Infrarot-Bandpassfilterstruktur (20) im Wellenlängenbereich von 800 nm bis 1600 nm ein zumindest teilweise überlappendes Durchlassband besitzt, wobei das Durchlassband eine Mittenwellenlänge hat, wobei sich die Mittenwellenlänge in der Größe um kleiner als 11 nm verschiebt, wenn sich der Einfallswinkel von 0° auf 30° ändert. Die Erfindung betrifft ferner einen Infrarot-Bandpassfilter, der auf der ersten Seite eines Substrats (10) die oben genannte Infrarot-Bandpassfilterstruktur (20) und auf der der ersten Seite gegenüberliegenden zweiten Seite des Substrats eine Antireflexionsschicht (30) aufweist. Dadurch kann die Sputtereffizienz erhöht werden, wodurch die Herstellungskosten reduziert werden ...

Hybrides sequenzielles und simultanes Prozesssimulationssystem

Ein Druck- und Durchflussnerechnungsverfahren, das die Drücke und Durchflüsse in einem Prozessnetzwerk effizient auflöst, verwendet sowohl ein simultanes als auch ein sequenzielles Auflösungsverfahren. Das Berechnungsverfahren bestimmt zunächst für jedes der Prozessnetzwerkelemente auf Grundlage des aktuellen Status des Elements einen Durchflussleitwert, linearisiert Druck- und Durchflussbeziehungen in jedem Durchflussweg des Prozessnetzwerks, indem es einen linearisierten Durchflussleitwert für jedes Prozesselement bestimmt, und bestimmt dann ein zusammengefasstes Prozessnetzwerk mit einer linearisierten, zusammengefassten Prozesskomponente in jedem Durchflussweg, um ein vereinfachtes Prozessnetzwerk zu erzeugen. Sodann wird ein simultanes Auflösungsverfahren verwendet, um die Drücke und Durchflüsse an jedem eines Satzes von Übergangsknoten des vereinfachten Prozessnetzwerks aufzulösen, und anschließend ein wird ein sequenzielles Auflösungsverfahren angewandt, um die Drücke und Durchflüsse ...

Karbonisiertes Material und Verfahren zum Induzieren von Zelldifferenzierung mit demselben

Verfahren zum Induzieren von Zelldifferenzierung mit einem karbonisierten Material, aufweisend: Bereitstellen eines Fasergewebes, das eine Polyacrylnitril-Faser aufweist; Karbonisieren des Fasergewebes bei hoher Temperatur zum Herstellen eines karbonisierten Materials (100), wobei das Fasergewebe für 1 bis 25 Minuten in einer Umgebung karbonisiert wird, die einen Druck zwischen 100 Torr und Atmosphärendruck und eine Temperatur zwischen 500 und 1200°C aufweist;wobei der Umgebung während des Karbonisierungsvorgangs ein inertes Gas zugeführt wird; wobei das karbonisierte Material (100) eine Mehrzahl von Kohlenstofffasern (10) aufweist, wobei jede der Mehrzahl von Kohlenstofffasern (10) einen Hauptteil (12) und eine Mehrzahl von Stützen (14) aufweist; wobei die Mehrzahl von Stützen (14) auf einer Oberfläche des Hauptteils (12) angeordnet sind und derart angehäuft sind, dass ihre Achsen in verschiedenen Richtungen angeordnet sind; und Ausbringen einer Zelle (20), die eine Fähigkeit aufweist, ...

Inspektionssystem und Verfahren zu dessen Steuerung

Ein Inspektionssystem umfasst eine Strahlungsquelle, einen Bilddetektor und eine Platzierungsvorrichtung. Die Platzierungsvorrichtung umfasst einen Träger und einen Rotationsmechanismus. Was die Verbindungen anbelangt, so ist die Platzierungsvorrichtung eingerichtet, um zwischen der Strahlungsquelle und dem Bilddetektor angeordnet zu werden, und der Rotationsmechanismus ist eingerichtet, um mit dem Träger verbunden zu sein. Was die Betriebsweise anbelangt, so werden die Strahlungsquelle und der Bilddetektor so angetrieben, dass sie entlang eines zuvor bestimmten Pfades bewegt werden, der Träger ist eingerichtet, um mindestens ein Objekt zu tragen, und der Rotationsmechanismus ist eingerichtet, um den Träger zu drehen.

Kindersicherheitssitz

Kindersicherheitssitz (1) mit einer Sitzrichtung (10), wobei der Kindersicherheitssitz (1) umfasst: eine Rückenlehne (12); eine Kopfstütze (14), die an der Rückenlehne (12) angeordnet ist, wenn ein Kind (2) im Kindersicherheitssitz (1) sitzt, wobei der Kopf des Kindes (2) an der Kopfstütze (14) anliegt und der Sitzrichtung (10) zugewandt ist; zwei Verschiebeschlitzstrukturen (16), die an der Rückenlehne (12) ausgebildet sind, wobei die Verschiebeschlitzstruktur (16) eine erste Halteposition (162a) und eine zweite Halteposition (162b) aufweist; und zwei Verschiebestangen (18), die mit zwei gegenüberliegenden Seiten der Kopfstütze (14) entsprechend den beiden Verschiebeschlitzstrukturen (16) verbunden sind und in den beiden Verschiebeschlitzstrukturen (16) verschiebbar angeordnet sind, wobei die Verschiebestange (18) an der ersten Halteposition (162a) oder der zweiten Halteposition (162b) positioniert sein kann, wobei, wenn die Verschiebestange (18) an der ersten Halteposition (162a) positioniert ...

VERFAHREN UND VORRICHTUNG ZUR ERKENNUNG EINES ZWEITEN FAHRZEUGS IM UMFELD EINES ERSTEN FAHRZEUGS

Die Erfindung betrifft ein Verfahren und eine korrespondierende Vorrichtung für ein erstes Fahrzeug, zur Erkennung wenigstens eines zweiten Fahrzeugs (4) im Umfeld des ersten Fahrzeugs, wobei die Erkennung des zweiten Fahrzeugs (4) anhand von mittels wenigstens einer am ersten Fahrzeug angeordneten Kamera (2) erfassten Bilddaten (1) erfolgt, und wobei die Erkennung des zweiten Fahrzeugs (4) auf Basis wenigstens eines in den Bilddaten (1) ermittelten Fahrzeugrads des zweiten Fahrzeugs (4) erfolgt.

Verfahren und Struktur zum Bilden von ETSOI-Kondensatoren, -Dioden, -Widerständen und - Back-Gate-Kontakten

Ein ETSOI-Transistor und eine Kombination aus Kondensatoren, Übergangsdioden, Bank-End-Kontakten und Widerständen werden jeweils durch Ätzen durch eine ETSOI-Schicht (20) und BOX-Schicht (15) in einem Transistor- und Kondensatorgebiet davon in einem HK/MG(80, 85)-Austauschgate-Prozess gebildet. Die Bildung des Kondensators und weiterer Einheiten ist mit einem CMOS-Prozess mit ETSOI-Austauschgate kompatibel. Eine Kondensator-Elektrode mit niedrigem Widerstand ermöglicht den Erhalt eines Kondensators und von Einheiten mit hoher Qualität. Die Topographielosigkeit beim Strukturieren des Dummy-Gate (27) wird durch Lithografie in Verbindung mit einer geeigneten Ätzung ermöglicht.

Zusammengesetzte Universalverpackungsbox für mehrere Größen

Die vorliegende Erfindung schafft eine zusammengesetzte Universalverpackungsbox für mehrere Größen, welche einen Boxkörper und in dem Boxkörper angeordnete wasserabweisende Pads aufweist. Der Boxkörper weist eine erste und eine zweite Wand, die einander gegenüberliegen, eine dritte und eine vierte Wand, die einander gegenüberliegen, vier Eckteile, die eine Verbindung zwischen der ersten, zweiten, dritten und vierten Wand herstellen, und eine kreuzförmige Stützstrebe auf, die mit einem Mittelbereich jeder der ersten, zweiten, dritten und vierten Wand verbunden ist, wobei die Verbindungen zwischen der ersten, der zweiten, der dritten und der vierten Wand und den Eckteilen und die Verbindungen zwischen der ersten, der zweiten, der dritten und der vierten Wand und der Stützstrebe sämtlich lösbare Verbindungen sind. Die zusammengesetzte Universalverpackungsbox für mehrere Größen verwendet ein Stützelement mit vier Enden, welche jeweils elastische Verbindungsvorsprünge bilden, und eine erste, ...

Schräge und kreisförmige Grenze für Linienverfolgung und kreisförmige Verfolgung

Ein Verfahren zum Steuern der Bewegung eines Roboters (R) relativ zu einer Förderband-Strömungsrichtung (10b) eines sich bewegenden Förderbands (10) beinhaltet die folgenden Schritte: Erstellen (30) eines Verfolgungsrahmens (10a, 10b) zum Koordinieren einer Position und Bewegung des Roboters (R) relativ zu einer Objektauflagefläche des Förderbands (10); Festsetzen (31) einer stromaufwärtigen Grenze (13) senkrecht oder schräg zu einer Förderband-Strömungsrichtung (1 Oa) des Förderbands (10); Festsetzen (32) einer stromabwärtigen Grenze (12) senkrecht oder schräg zur Förderband-Strömungsrichtung (10a); optional Festsetzen (33) einer kreisförmigen Grenze (22), welche die stromaufwärtige Grenze (13) und die stromabwärtige Grenze (12) teilweise überlappt, wobei die stromaufwärtige Grenze (13), die stromabwärtige Grenze (12) und die kreisförmige Grenze (22) positioniert werden, um einen Aufnahmebereich (14) relativ zur Auflagefläche zu definieren; und Betreiben (34) des Roboters (R), um Objekte ...

Deckelkörper eines Scheibenwischermotors, Scheibenwischermotor, hinterer Schei-benwischer und Fahrzeug

Das Gebrauchsmuster betrifft einen Deckelkörper des Scheibenwischermotors, wobei der Deckelkörper einen Teildeckel und einen Getriebedeckel aufweist. Der Deckelkörper weist ferner mehrere am Getriebedeckel angeordnete Schweißstifte auf, wobei durch Schweißen der Enden der Schweißstifte der Teildeckel am Getriebedeckel befestigt wird, nachdem die Enden der Schweißstifte durch die am Teildeckel angeordneten Durchgangslöcher hin gehen. Das Gebrauchsmuster stellt ferner einen mit dem Deckelkörper versehenen Scheibenwischermotor, einen mit dem Scheibenwischermotor versehenen hinteren Scheibenwischer und ein mit dem hinteren Scheibenwischer ausgestattetes Fahrzeug zur Verfügung. Der Deckelkörper des Scheibenwischermotors des vorliegenden Gebrauchsmusters hat viele Vorteile, wie flexible Anordnung, stabile Verbindung, keiner Raumbedarf und gute Bedienbarkeit.

Elektrischer Verbinder und Herstellungsverfahren desselben

Elektrischer Verbinder (100), umfassend:ein Anschlussmodul (10), das ein Isoliergehäuse (11), und eine Reihe oberer Kontakte (21), eine Reihe unterer Kontakte (22) und eine Abschirmplatte (30) umfasst, die in dem Isoliergehäuse (11) eingebettet sind;wobei das Isoliergehäuse (11) eine Basis (12) und eine passende Zunge (13) umfasst, die sich von der Basis (12) erstreckt, wobei die passende Zunge (13) eine obere Fläche (1301), eine untere Fläche (1302) und eine vordere Fläche (1303) davon definiert;wobei die oberen und unteren Kontakte (21,22) Kontaktabschnitte (211,221), die zu der oberen und unteren Fläche (1301,1302) der passenden Zunge (13) freiliegen, und Lötabschnitte (213,223) aus der Basis (12), und Verbindungsabschnitte (212,222), welche jeweils die Kontaktabschnitte (211,221) und die Lötabschnitte (213,223) verbinden, umfassen;wobei die Abschirmplatte (30) zwischen den oberen und unteren Kontakten (21,22) angeordnet ist und ein Paar von Seitenverriegelungen (31) umfasst;wobei das ...

Fangschichtsubstratstapeltechnik zum Verbessern der Leistung für RF-Vorrichtungen

Einige Ausführungsformen der vorliegenden Offenbarung sind an eine Vorrichtung gerichtet. Die Vorrichtung umfasst ein Substrat, das eine über einer Isolierschicht angeordnete Siliziumschicht umfasst. Das Substrat umfasst eine Transistorvorrichtungsregion und eine Hochfrequenz-(RF)-Region. Eine Kopplungsstruktur ist über dem Substrat angeordnet und umfasst mehrere innerhalb einer dielektrischen Struktur angeordnete Metallschichten. Ein Handhabungssubstrat ist über einer oberen Fläche der Kopplungsstruktur angeordnet. Eine Fangschicht trennt die Kopplungsstruktur und das Handhabungssubstrat.

LUFTSPALT IN INNEREN ABSTANDSHALTERN UND VERFAHREN ZUM FERTIGEN DESSELBEN IN FELDEFFEKTTRANSISTOREN

Eine Halbleiterstruktur umfasst einen Stapel von Halbleiterschichten, die über einem Substrat angeordnet sind, einen metallischen Gatestapel, der einen oberen Abschnitt, der über dem Stapel von Halbleiterschichten angeordnet ist, und einen unteren Abschnitt, der mit dem Stapel von Halbleiterschichten wechselweise angeordnet ist, aufweist, einen inneren Abstandshalter, der auf Seitenwänden des unteren Abschnitts des metallischen Gatestapels angeordnet ist, einen Luftspalt, der in dem inneren Abstandshalter umschlossen ist, und ein epitaktisches Source/Drain- (S/D-) Merkmal, das über dem inneren Abstandshalter und angrenzend an den metallischen Gatestapel angeordnet ist.

FLEECE-MASCHENWARE UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Die vorliegende Offenbarung stellt eine Fleece-Maschenware bereit, die ein Basismaterial und eine Vielzahl von zweiten Fadenabschnitten umfasst. Das Basismaterial umfasst mindestens einen ersten Faden. Die zweiten Fadenabschnitte stehen von einer Oberfläche des Basismaterials vor. Wenigstens ein Abschnitt des ersten Fadens ist mit den zweiten Fadenabschnitten verschmolzen und verbunden.

Phasenwechselspeicher

Die Erfindung betrifft einen Phasenwechselspeicher (10) zum nichtflüchtigen Speichern von binären Inhalten, welcher die binären Inhalte durch lokales Schalten eines Materials (18) zwischen einer amorphen und einer kristallinen Phase elektrisch und/oder optisch nichtflüchtig speichert, wobei der Zustand bezüglich der elektrischen Leitfähigkeit des Materials (18) und/oder bezüglich der Reflexionseigenschaften des Materials (18) den Informationsgehalt des Phasenwechselspeichers (10) festlegt. Weiterhin betrifft die Erfindung ein Verfahren für einen Phasenwechselspeicher (10) zum nichtflüchtigen Speichern von binären Inhalten, welcher die binären Inhalte durch lokales Schalten eines Materials (18) zwischen einer amorphen und einer kristallinen Phase elektrisch und/oder optisch nichtflüchtig speichert, wobei der Zustand bezüglich der elektrischen Leitfähigkeit des Materials (18) und/oder bezüglich der Reflexionseigenschaften des Materials den Informationsgehalt des Phasenwechselspeichers (10 ...

GEMEINSAM GENUTZTER DECODIERERSCHALTKREIS UND VERFAHREN

Ein Schaltkreis enthält einen Auswahlschaltkreis, der eingerichtet ist, eine erste Adresse an einem ersten Eingang und eine zweite Adresse an einem zweiten Eingang zu empfangen, die erste Adresse an einen Ausgang weiterzugeben, wenn ein Auswahlsignal einen ersten logischen Zustand hat, und die zweite Adresse an den Ausgang weiterzugeben, wenn das Auswahlsignal einen zweiten logischen Zustand hat, der sich von dem ersten logischen Zustand unterscheidet. Der Schaltkreis enthält außerdem einen Dekodierer, der eingerichtet ist, die weitergegebene erste Adresse oder zweite Adresse zu decodieren.

Lichtblockierschicht für eine Bildsensorvorrichtung

Die vorliegende Offenbarung richtet sich auf ein Verfahren zum Ausbilden einer Lichtblockiermaterialschicht auf einer Rückseitenbeleuchtungs-Bildsensorvorrichtung. Die Lichtblockiermaterialschicht kann Lichtstrahlen, die auf die Rückseitenbeleuchtungs-Bildsensorvorrichtung in streifenden Einfallswinkeln auftreffen, blockieren oder absorbieren. Die Lichtblockiermaterialschicht kann unter Verwendung eines selbstjustierenden Prozesses ausgebildet werden, der das Verwenden einer fotolithografischen Maske oder fotolithografischer Operationen nicht erfordert. Zum Beispiel kann die Lichtblockiermaterialschicht über einer Bildsensorvorrichtung ausgebildet und anschließend geätzt werden, so dass die Lichtblockiermaterialschicht in Bereichen verbleibt, in denen Lichtstrahlen, die in streifenden Einfallswinkeln auftreffen, in die Rückseitenbeleuchtungs-Bildsensorvorrichtung gelangen.

TENT-WAY STRETCHABLE TYPE OF LOW CONGESTION

POLYAMIDES HAS RAISED FLUIDITY, ITS MANUFACTORING PROCESS, COMPOSITIONSCOMPRENANT THIS COPOLYAMIDE

ELECTRIC SHEARS

Sécateur électrique qui comprend un boîtier (1), un moteur reçu à l'intérieur du boîtier (1), un mécanisme de transmission (3), une lame mobile (21) et une lame fixe (22) s'étendant à partir de l'extrémité avant du boîtier (1). La lame fixe (22) est montée de manière fixe sur le boîtier (1) et la lame mobile (21) est reliée de manière rotative à la lame fixe (22) par l'intermédiaire d'un arbre (4) et entraînée par le moteur par l'intermédiaire du mécanisme de transmission (3). Un dispositif de verrouillage actionnable manuellement par l'utilisateur est disposé sur l'arbre (4) pour verrouiller la lame mobile (21), le dispositif de verrouillage étant apte à être commuté entre une première position dans laquelle la lame mobile (21) est verrouillée pour rester reliée au mécanisme de transmission (3) et une seconde position dans laquelle la lame mobile (21) est apte à être libérée du mécanisme de transmission (3). Ainsi, le remplacement de la lame mobile (21) est très simple et pratique.

DEVICE Of LIGHTING HAS Electroluminescent diodes

SHELL FOR PORTABLE TELECOMMUNICATION SYSTEM

CHEMICAL-MECHANICAL POLISHING COMPOSITION STABILIZED AND METHOD FOR POLISHING A SUBSTRATE

Micro-discharged exhaust gas processing device has at least two stage exchange segments each having jet spurt hole and diffusing hole, air hole on exchange gas chamber of first stage exchange segment, and mixing gas chambers

... 1. Dispositif de traitement de gaz d'échappement à émission réduite comprenant : - un conteneur, - au moins des première et deuxième sections d'échange (2) comprenant chacune au moins un gicleur (21) et un orifice (22) de diffusion correspondant, une chambre (23) d'échange de gaz disposée reliant ledit gicleur (21) et ledit orifice (22) de diffusion, - une ouverture (24) de communication conduisant à l'atmosphère, prévue au niveau de la chambre (23) d'échange de la première section d'échange, - une chambre (3) de mélange de gaz reliant deux sections d'échange (2) consécutives, - un tuyau (6) d'échappement prévu au niveau de la chambre (3) de mélange de gaz d'une dernière section d'échange (2).

ROTARY PADDLE OF STEAM TURBINE AND SECTION LOW PRESSURE Of an ENGINE HAS STEAM TURBINE

Aube rotative (20) de turbine à vapeur pour section basse pression d'un moteur (10) à turbine à vapeur. L'aube rotative (20) de turbine à vapeur comprend une partie formant pale profilée (42). Une section emplanture (44) est fixée à une extrémité de la pale profilée (42). Une section queue d'aronde (40) fait saillie depuis la section emplanture (44), la section queue d'aronde (40) étant constituée par une queue d'aronde à entrée tangentielle. Une section bout (46) est fixée à la pale profilée (42) en une extrémité opposée à l'emplanture (44). Une coiffe (48) fait partie intégrante du bout (46). L'aube rotative (20) comporte une zone annulaire de sortie d'une superficie d'environ 1,68 m2 (18,1 ft2) ou plus.

ACTIVE MATERIAL FOR NEGATIVE ELECTRODE OF ALKALINE STORAGE BATTERIES SUCH AS NICKEL METAL HYDRIDE

Un alliage hydrurable de formule R1-x-yYxMgyNis-zMz dans laquelle : R représente un ou plusieurs éléments choisis parmi La, Ce, Nd, Pr, Gd, Sm ; M représente un ou plusieurs éléments choisis parmi Mn, Fe, Al, Co, Cu, Zr, Sn et Cr ; 0 < x ≤ 0,5 ; 0 ≤ y ≤ 0,3 ; 3,3 < s < 3,85 et 0 < z ≤ 0,5 ; ledit alliage comprenant au moins une phase cristalline de structure A2B7 et/ou au moins une phase cristalline de structure A5B19, la maille cristalline principale de la phase cristalline de structure A2B7 et/ou celle de la phase cristalline de structure A5B19 présentant un taux de déformation, mesuré avant hydruration, inférieur ou égal à 0,040% +/- 0,002%, le rayon atomique moyen des atomes constituant le groupe A étant inférieur ou égal à 1,810 A.

Illuminant assembly structure

An illuminant assembly structure comprises a hollow cover and an luminous device: the cover is concavely provided with an accommodating groove at the bottom for at least a conductive part accommodated inside and has several raised rims extending from the cover's inner edge; the luminous device comprises a circuit substrate and a shield and has at least a rotary vane extended from its outer surface wherein the circuit substrate is provided with a plurality of illuminants and rotary vanes including resilient electrodes and the shield allows a plurality of opening units to be opened on each rotary vane. The resilient electrodes are exposed via the shield's all opening units and are tightly coupled with the conductive parts for the illuminants growing with the luminous device installed on the cover's center and turned to a specific angle.

SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer. 1. A method of forming Field Effect Transistors (FETs) , said method comprising:defining FET locations on a layered semiconductor wafer;converting portions of a buried layer beneath source/drain regions of one or more defined FETs to a dielectric material; andforming source/drain contacts to said one or more defined FETs.2. A method of forming FETs as in claim 1 , wherein defining FET locations comprises forming a gate in each FET location.3. A method of forming FETs as in claim 2 , wherein defining FET locations further comprises forming dielectric sidewalls along each gate.4. A method of forming FETs as in claim 1 , wherein converting portions comprises opening orifices at source/drain regions of said one or more defined FETs through a surface layer to a buried layer of said layered semiconductor wafer.5. A method of forming FETs as in claim 4 , wherein opening said orifices comprises forming sacrificial sidewalls outboard of gate sidewalls claim 4 , said orifices being formed outboard of said sacrificial sidewalls and removed after converting said portions.6. A method of forming FETs as in claim 4 , wherein the surface layer is a Gallium Arsenide (GaAs) layer claim 4 , the buried layer is Aluminum Arsenide (AlAs) layer and the dielectric material is Aluminum Oxide (AlO).7. A method of forming FETs as in claim 6 , ...

III-V FIELD EFFECT TRANSISTOR (FET) AND III-V SEMICONDUCTOR ON INSULATOR (IIIVOI) FET, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer. 1. A method of forming Field Effect Transistors (FETs) , said method comprising:defining FET locations on a layered semiconductor wafer, one or more defined FETs having exposed channel ends;converting portions of a buried layer beneath source/drain contact regions at said exposed channel ends to a dielectric material;forming channel end caps on channel sidewalls at opposite said exposed channel ends; andforming source/drain contacts to said end caps.2. A method of forming FETs as in claim 1 , wherein defining FET locations comprises forming a gate in each FET location.3. A method of forming FETs as in claim 2 , wherein defining FET locations further comprises forming dielectric sidewalls along each gate.4. A method of forming FETs as in claim 1 , wherein converting portions comprises:etching a surface layer to a buried layer of said layered semiconductor wafer; andsub-etching an upper portion of said buried layer.5. A method of forming FETs as in claim 4 , wherein converting portions further comprises converting exposed sub-etched surfaces to a dielectric material layer.6. A method of forming FETs as in claim 4 , wherein the surface layer is a Gallium Arsenide (GaAs) layer claim 4 , the buried layer is Aluminum Arsenide (AlAs) layer and the ...

WAFER BONDED SOLAR CELLS AND FABRICATION METHODS

A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.

METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE

A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate. 1. A method of removing a semiconductor device layer from a base substrate , said method comprising:providing a crack propagation layer on an upper surface of a base substrate;forming a semiconductor device layer including at least one semiconductor device on the crack propagation layer;etching end portions of the crack propagation layer to initiate a crack in the crack propagation layer;cleaving the etched crack propagation layer to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate; andremoving the cleaved crack propagation layer portion from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion from the upper surface of the base substrate.2. The method of claim 1 , wherein the providing the crack propagation layer includes selecting a material that has a fracture toughness that is less than the base substrate and less than the semiconductor device layer.3. The method of claim 2 , wherein said material of the crack propagation ...

SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT

A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed. 1. A metal oxide field effect transistor device , comprising:a III-V substrate;a source region and a drain region self-aligned to a gate stack and formed from diffused dopants with a dopant concentration sufficient to make the source region and the drain region n-type; andcontact regions self-aligned with and formed within each of the source region and the drain region, the contact regions being formed from a diffused metal.2. The device as recited in claim 1 , wherein substrate includes a p-type substrate and the sufficient dopant concentration converts the source and drain regions to n-type regions.3. The device as recited in claim 1 , wherein the III-V substrate includes InGaAs and the contact regions include a metal that forms an alloy with the InGaAs.4. The device as recited in claim 3 , wherein the metal includes Ni and the alloy includes a Ni—InGaAs alloy.5. The device as recited in claim 1 , wherein the diffused dopants include Ge. This application is a Continuation application of co-pending U.S. patent application Ser. No. 13/173,680 filed on Jun. 30, 2011, incorporated herein by reference in its entirety.1. Technical FieldThe present invention relates to semiconductor devices and more particularly to a self-aligned metal oxide semiconductor ...

MONOLITHIC MULTI-JUNCTION PHOTOVOLTAIC CELL AND METHOD

A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate. 1. A method for fabrication of a multi junction photovoltaic device , comprising:providing a parent substrate including a single crystal III-V material, the parent substrate forming a first cell of the multi junction photovoltaic device;epitaxially growing a lattice-matched Germanium layer on the III-V material to foam a second cell of the multi junction photovoltaic device; andbonding the Germanium layer to a foreign substrate to form the multi-junction photovoltaic device.2. The method as recited in claim 1 , wherein the parent substrate includes one of GaAs or AlGaAs.3. The method as recited in claim 1 , wherein epitaxially growing includes performing an ultra-high vacuum chemical vapor deposition (UHV-CVD) claim 1 , metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process to grow the Germanium layer.4. The method as recited in claim 3 , wherein the UHV-CVD or MOCVD process is performed at or below 500 degrees Celsius.5. The method as recited in claim 3 , wherein the UHV-CVD or MOCVD process has a pressure adjusted to control growth rate of the Germanium layer and the pressure is between about 0.1 mTorr and 1000 mTorr.6. The method as recited in claim 1 , further comprising performing an ultra-high vacuum prebake to desorb contaminants from the parent substrate before epitaxially growing the Germanium layer.7. The method as recited in claim 6 , wherein performing an ultra-high vacuum prebake includes applying a temperature of between about 500 degrees Celsius to about 650 degrees Celsius.8. A method for ...

HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS

A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used. 1. A method of releasing a semiconductor device layer from a base substrate , said method comprising:forming a sacrificial phosphide-containing layer on an upper surface of a base substrate;forming a semiconductor device layer on an upper surface of the sacrificial phosphide-containing layer; andremoving the sacrificial phosphide-containing layer from between the semiconductor device layer and the base substrate, wherein said removing comprises etching with a non-HF containing etchant.2. The method of claim 1 , wherein said base substrate is an III-V compound semiconductor material.3. The method of claim 1 , wherein said base substrate is a Ge-containing semiconductor material.4. The method of claim 3 , further comprising forming a semiconductor buffer layer between the Ge-containing semiconductor substrate and the sacrificial phosphide-containing layer.5. The method of claim 3 , wherein said semiconductor buffer layer is an III-V compound semiconductor material.6. The method of claim 1 , wherein said non-HF etchant is a non-HF containing acid.7. The method of claim 6 , wherein said non-HF containing acid is selected from the group consisting of HCl claim 6 , HBr claim 6 , HI and mixtures thereof.8. The method of claim 1 , wherein said removing the sacrificial phosphide-containing layer utilizing said non-HF containing etchant is performed at a ...

HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE

A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially. 1. A method of releasing multiple semiconductor device layers from atop a base substrate , said method comprising:forming a multilayered stack on a base substrate, said multilayered stack comprising, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness; andselectively removing said first and second sacrificial material layers by etching, wherein the second sacrificial material layer etches at a faster rate than the first sacrificial material layer, thereby sequentially releasing the second semiconductor device layer followed by the first semiconductor device layer.2. The method of claim 1 , wherein said first and second sacrificial material layers comprise an III-V compound semiconductor material claim 1 , and said etching comprises an HF containing etchant.3. The method of claim 1 , wherein said first and sacrificial material layers comprise a ...

HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE

In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness. 1. A semiconductor structure comprising:a base substrate; anda multilayered stack on a base substrate, said multilayered stack comprising, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.2. The semiconductor structure of claim 1 , wherein said base substrate comprises an III-V compound semiconductor material.3. The semiconductor structure of claim 1 , wherein said base substrate comprises a Ge-containing semiconductor material claim 1 , and wherein a semiconductor buffer layer is located between the Ge-containing semiconductor material and said multilayered structure.4. The semiconductor structure of claim 1 , wherein said first and second sacrificial material layers are comprised of a different semiconductor material than said base substrate and said first and second semiconductor device layers.5. The semiconductor structure of claim 1 , wherein said first and second sacrificial material layers are comprised of a same semiconductor material as the first and second semiconductor device layers and wherein a first protection layer is formed beneath each semiconductor device layer claim 1 , and wherein a second protection layer is formed on exposed surfaces of each semiconductor device layer.6. A semiconductor structure comprising:a multilayered stack located on a base substrate, said ...

SPALLING WITH LASER-DEFINED SPALL EDGE REGIONS

Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled. 1. A method of removing a material layer region of a base substrate , said method comprising:forming at least a stressor layer atop an uppermost surface of a base substrate;forming a trench by laser ablation at least within the stressor layer to define an edge of a material layer region to be spalled; andspalling the material layer region of the base substrate.2. The method of claim 1 , further comprising at least one of a metal-containing adhesion layer and a plating seed layer located beneath said stressor layer.3. The method of claim 1 , wherein said trench stops on said uppermost surface of the base substrate.4. The method of claim 1 , wherein said trench stops within the base substrate.5. The method of claim 1 , wherein said trench formed by laser ablation is expanded by other etch processes to form an expanded width opening.6. The method of claim 1 , wherein said stressor layer is a metal claim 1 , a polymer or any combination thereof.7. The method of claim 6 , wherein said stressor layer includes at least said polymer claim 6 , and said polymer is a spall inducing tape layer.8. The method of claim 1 , wherein said laser ablation comprises pulsed irradiation performed at one of a fluence ...

HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS

Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed. 1. A method of integrating a Group III nitride material and silicon , said method comprising:providing a structure comprising, from bottom to top, a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer;forming an opening through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and partially within the (100) silicon layer, wherein a surface of the (100) silicon layer beneath the uppermost surface of the (100) silicon layer is exposed;forming a conformal dielectric material liner atop remaining portions of the blanket layer of dielectric material and within said opening;removing horizontal portions of the conformal dielectric material liner to provide template dielectric spacers partially covering said exposed surface of the (100) silicon layer;forming an epitaxial semiconductor material on a ...

HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE

A method of removing a plurality of semiconductor device layers from an underlying base substrate. A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. Each successive sacrificial material layer that is formed is thicker than the previously formed sacrificial material layer. An etch is then performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially. 1. A method of releasing multiple semiconductor device layers from atop a base substrate , said method comprising:forming a multilayered stack on a base substrate, said multilayered stack comprising, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness; andselectively removing said first and second sacrificial material layers by etching, wherein the second sacrificial material layer etches at a faster rate than the first sacrificial material layer, thereby sequentially releasing the second semiconductor device layer followed by the first semiconductor device layer.2. The method of claim 1 , wherein said first and second sacrificial material layers comprise an III-V compound semiconductor material claim 1 , and said etching comprises an HF containing etchant.3. The method of claim 1 , wherein said first and sacrificial material layers comprise a phosphide-containing material claim 1 , and said etching comprises a non-HF containing etchant.4. The method of claim 1 , wherein said ...

FLEXIBLE III-V SOLAR CELL STRUCTURE

Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures. 1. A structure comprising:a germanium substrate;a buffer region formed directly on the germanium substrate, the buffer region including a highly doped, electrically conductive layer comprising gallium arsenide, anda solar cell structure in inverted order on the buffer region, the solar cell structure including an absorbing layer comprising gallium arsenide, an emitter layer, a window layer adjoining the highly doped, electrically conductive layer of the buffer region, the emitter and window layers being formed between the buffer region and the absorbing layer, and a back surface field layer formed on a side of the absorbing layer opposite from the substrate,wherein the highly doped, electrically conductive layer is functional as a buffer layer between the germanium substrate and the solar cell structure, thereby preventing antiphase defects, and is further employable as an ohmic contact layer for the solar cell structure, there being no etch stop layer between the germanium substrate and the solar cell structure.2. The structure of claim 1 , wherein the highly doped claim 1 , electrically conductive layer comprises Si:InGaAs.3. The structure of claim 1 , wherein the substrate is p-type germanium 6° off towards <111> orientation.4. The structure of claim 1 , further including a metal stressor layer attached to the solar cell structure and a flexible handle layer attached to the metal layer for ...

HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS

A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used. 1. A method of releasing a semiconductor device layer from a base substrate , said method comprising:forming a sacrificial phosphide-containing layer on an upper surface of a base substrate;forming a semiconductor device layer on an upper surface of the sacrificial phosphide-containing layer; andremoving the sacrificial phosphide-containing layer from between the semiconductor device layer and the base substrate, wherein said removing comprises etching with a non-HF containing etchant.2. The method of claim 1 , wherein said base substrate is an III-V compound semiconductor material.3. The method of claim 1 , wherein said base substrate is a Ge-containing semiconductor material.4. The method of claim 3 , further comprising forming a semiconductor buffer layer between the Ge-containing semiconductor substrate and the sacrificial phosphide-containing layer.5. The method of claim 3 , wherein said semiconductor buffer layer is an III-V compound semiconductor material.6. The method of claim 1 , wherein said non-HF etchant is a non-HF containing acid.7. The method of claim 6 , wherein said non-HF containing acid is selected from the group consisting of HCl claim 6 , HBr claim 6 , HI and mixtures thereof.8. The method of claim 1 , wherein said removing the sacrificial phosphide-containing layer utilizing said non-HF containing etchant is performed at a ...

TRANSISTOR FORMATION USING COLD WELDING

A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. 1. A semiconductor device , comprising:a first semiconductor substrate having a first metal layer formed directly on a major surface of the first semiconductor substrate;a second semiconductor substrate having a second metal layer formed directly on a major surface of the second substrate; anda cold weld interface coupling the second metal layer to the first metal layer.2. The device as recited in claim 1 , wherein at least one of the first metal layer and the second metal layer includes a textured three-dimensional surface.3. The device as recited in claim 1 , wherein the first semiconductor substrate includes a semiconductor component.4. The device as recited in claim 3 , wherein the first metal layer joined to the second metal layer forms a ground plane and the semiconductor component includes a transistor such that the ground plane reduces short channel effects in the transistor.5. The device as recited in claim 1 , wherein the first metal layer joined to the second metal layer forms a heat sink for the first semiconductor substrate and the second substrate.6. The device as recited in claim 1 , wherein the first metal layer and the second metal layer include a same metal material.7. The device as recited in claim 1 , wherein the first metal layer and the second metal layer include different metal materials.8. The device as recited in claim 1 , wherein the second semiconductor substrate includes one of a flexible material and a metallic material.9. A semiconductor device ...

TRANSISTOR FORMATION USING COLD WELDING

A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. 1. A method for fabrication of a semiconductor device , comprising:providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate;providing a second substrate assembly including a second substrate and a second metal layer formed on the second substrate; andjoining the first metal layer to the second metal layer using a cold welding process wherein at least one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.2. The method as recited in claim 1 , wherein the first substrate includes semiconductor components and the second substrate includes semiconductor components and joining the first metal layer to the second metal layer includes cold welding the first and second substrate back-to-back to form a stack of semiconductor components.3. The method as recited in claim i claim 1 , wherein at least one of the first metal layer and the second metal layer includes a textured three-dimensional surface.4. The method as recited in claim 1 , wherein at least one of the first substrate and the second substrate includes a sacrificial layer claim 1 , and the method further comprises removing the sacrificial layer to release one of the first substrate and the second substrate where the sacrificial layer is formed.5. The method as recited in claim 4 , wherein at least one of the first substrate and the second substrate that is removed is reusable.6. The method as ...

WAFER BONDED SOLAR CELLS AND FABRICATION METHODS

A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch. 1. A photovoltaic device , comprising:at least two light-responsive cells stacked in series, each cell having a material formed independently of the other and each including different band gap energies and having different lattice constants; andan interface layer of a transparent conductive material disposed between each pair of the at least two light-responsive cells.2. The photovoltaic device as recited in claim 1 , wherein the interface between at least one pair of the at least two light-responsive cells includes at least one metal layer.3. The photovoltaic device as recited in claim 1 , wherein the at least two cells include four cells having an interface layer of a transparent conductive material disposed between each pair of the four cells.4. The photovoltaic device as recited in claim 3 , wherein the four cells include a top cell with a band gap energy of about 1.8 electron-volts claim 3 , a second cell adjacent to the top cell with a band gap energy of about 1.4 electron-volts claim 3 , a third cell adjacent to the second cell with a band gap energy of about 1.0 electron-volts and a bottom cell adjacent to the third cell with a band gap energy of about 0.6 electron-volts.5. The photovoltaic device as recited in claim 4 , wherein the top cell includes GaInP claim 4 , the second cell includes GaAs claim 4 , the third cell includes Si and the bottom cell includes Ge.6. The photovoltaic device as recited in claim 4 , wherein the top cell includes GaInP claim 4 , the second cell includes GaAs claim 4 , the third cell includes InGaAs and the bottom cell includes Ge.7. The photovoltaic device as recited in claim 4 , ...

MULTIPLE VIA STRUCTURE AND METHOD

A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts. 1. A method for forming a device with a multi-tiered contact structure , comprising:forming first contacts in via holes down to a first level;forming a dielectric capping layer over exposed portions of the first contacts;forming a dielectric layer over the capping layer;opening via holes in the dielectric layer down to the capping layer;opening holes in the capping layer through the via holes to expose the first contacts; andforming contact connectors and second contacts in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.2. The method as recited in claim 1 , wherein the first contacts reach a depth of the first level and a portion of the second contacts land on a second level claim 1 , which is vertically offset from the first level.3. The method as recited in claim 2 , wherein a vertical offset between the first level and the second level is greater than 40 nm.4. The method as recited in claim 2 , wherein the first level includes first complementary metal oxide semiconductor devices (CMOS) and the second level includes second CMOS devices having an opposite conductivity from the first CMOS devices.5. The method as recited in claim 1 , wherein opening holes in the capping layer includes:employing the dielectric layer as a mask; andsubjecting ...

PREPARATION OF LOW DEFECT DENSITY OF III-V ON SI FOR DEVICE FABRICATION

A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa. 1. A semiconducting material , comprising:a substrate;a high aluminum content III-V material layer disposed on the substrate, the III-V material layer comprising at least one III element and a V element, the at leasing one III element comprising Al and being present in an amount of least 50 at. % based on total atomic weight of the at least one III element;a graded layer of an In containing III-V material disposed on the high aluminum content III-V material layer, the In containing III-V material being InGaAs or InAlAs and comprising In in an increasing atomic gradient up to 35 at. % based on total atomic weight of InGa or InAl; anda InGaAs layer disposed on the graded layer, the InGaAs layer comprising about 25 to about 100 at. % In based on total atomic weight of InGa.2. The semiconducting material of claim 1 , wherein the high aluminum content III-V material layer is partially oxidized to include AlO.3. The semiconducting material of claim 1 , wherein the graded layer has a thickness in a range from about 0.5 to about 1.5 micrometers. This application is a continuation of and claims priority from U.S. patent application Ser. No. 14/697,953, filed on Apr. 28, 2015, entitled “PREPARATION OF LOW DEFECT DENSITY OF III-V ON SI FOR DEVICE FABRICATION,” the entire contents of which are incorporated herein by reference.The present disclosure generally relates to semiconductor devices, and more specifically, to semiconducting materials ...

III-V LASERS WITH INTEGRATED SILICON PHOTONIC CIRCUITS

III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light. 1. A laser , comprising:a three-layer semiconductor stack formed from III-V semiconductors on a substrate, wherein a middle layer has a lower bandgap than a top layer and a bottom layer;a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; anda waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.2. The laser of claim 1 , wherein the stack has a height-to-width aspect ratio greater than 1.3. The laser of claim 1 , wherein the mirror region comprises alternating regions of a first and a second non-conductive material having different indices of refraction.4. The laser of claim 3 , wherein the alternating regions have a separation based on a wavelength of the emitted light.5. The laser of claim 1 , further comprising front and back contacts that contact the top and bottom of the stack claim 1 , respectively.6. The laser of claim 5 , wherein the back contact includes a conductive layer in the substrate that connects to the bottom layer of the stack.7. The laser of claim 1 , wherein the mirror and waveguide regions are monolithically grown on an insulator layer of the substrate.8. The laser of claim 1 , further comprising a plurality of said three-layer semiconductor stack arranged in parallel on the substrate.9. The laser of claim 1 , wherein the waveguide region comprises:a surface perpendicular to the stack; andan extension from said surface ...

METAL PARTICLE ENHANCED FORSTER RESONANCE ENERGY TRANSFER FOR ORGANIC OPTOELECTRONIC DEVICE

A photovoltaic device that includes an organic or quantum dot sensitizer layer for absorbing light spectra and providing excitons. The sensitizer layer may include metal particles embedded therein for increased exciton transfer efficiency. The photovoltaic device may further include a junction comprising an electron donor layer and electron acceptor layer for charge carrier transport. 1. An photovoltaic device comprising;an organic sensitizer layer for absorbing light spectra and providing excitons, wherein the sensitizer layer comprises metal particles embedded therein for increased exciton transfer efficiency; anda junction comprising an electron donor layer and electron acceptor layer for charge carrier transport.2. The photovoltaic device of claim 1 , wherein the organic sensitizer layer comprises chloroaluminum phthalocyanine (ClAlPc) claim 1 , phenyl-C61-butyric acid methyl ester (PCBM) claim 1 , tin (II) phthalocyanine (SnPc) claim 1 , subphthalocyanine (SubPc) claim 1 , carbon 60 (C60) claim 1 , copper phthalocyanine (CuPc) claim 1 , squaraine (SQ) or a combination thereof.3. The photovoltaic device of claim 1 , wherein the metal particles comprise silver (Ag) claim 1 , aluminum (Al) claim 1 , copper (Cu) claim 1 , gold (Au) claim 1 , tungsten (W) claim 1 , platinum (Pt) claim 1 , tantalum (Ta) claim 1 , titanium (Ti) claim 1 , gold (Au) or a combination thereof.4. The photovoltaic device of claim 1 , wherein the metal particles have a particle size ranging from 20 nm to 200 nm.5. The photovoltaic device of claim 1 , wherein the metal particles are dispersed to provide a spacing between adjacent metal particles ranging from 50 nm and 200 nm.6. The photovoltaic device of claim 1 , further comprising an anode in direct contact with a surface of the organic sensitizer layer that is opposite a surface of the organic sensitizer layer that is present on the electron donor layer.7. The photovoltaic device of further comprising a cathode on a surface of the junction ...

A METHOD FOR FORMING A CRYSTALLINE COMPOUND III-V MATERIAL ON A SINGLE ELEMENT SUBSTRATE

A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. 1. A method for forming a crystalline compound material on a single element substrate , comprising:etching a high aspect ratio trench in a single element crystalline substrate;forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench;removing the dielectric from the bottom of the trench to expose the substrate at the bottom of the trench; andselectively growing a crystalline compound material on the substrate at the bottom of the trench.2. The method as recited in claim 1 , wherein selectively growing the crystalline compound material includes epitaxially growing the crystalline compound material below a surface of the substrate.3. The method as recited in claim 1 , wherein the high aspect ratio trench includes a height to width aspect ratio of greater than 1:1.4. The method as recited in claim 1 , wherein the substrate includes monocrystalline silicon and forming the dielectric layer includes forming a silicon dioxide layer.5. The method as recited in claim 1 , wherein the silicon dioxide layer includes a thickness of 500 nm or less on sidewalls of the trench.6. The method as recited in claim 1 , wherein etching the high aspect ratio trench includes:forming an etch mask layer on the substrate; andpatterning the etch mask layer to expose the substrate to locate trench positions.7. The method as recited in claim 1 , wherein forming the dielectric layer includes one of: thermal growth claim 1 , chemical vapor deposition claim 1 , and atomic layer deposition.8. The method as ...

SEMICONDUCTOR DEVICE HAVING A III-V CRYSTALLINE COMPOUND MATERIAL SELECTIVELY GROWN ON THE BOTTOM OF A SPACE FORMED IN A SINGLE ELEMENT SUBSTRATE.

A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. 1. A semiconductor device , comprising:a single element substrate;a subsurface space formed in the single element crystalline substrate;a dielectric layer formed over the substrate and on sidewalls of the space; anda III-V crystalline compound material selectively grown on the substrate at the bottom of the space.2. The device as recited in claim 1 , wherein defects in the crystalline compound material exist below a surface of the substrate.3. The device as recited in claim 1 , wherein the space includes one of a high aspect ratio trench and a volume having the sidewalls extending laterally beyond a surface opening in the substrate.4. The device as recited in claim 1 , wherein the substrate includes monocrystalline silicon and the dielectric layer includes a silicon dioxide layer wherein the silicon dioxide layer includes a thickness of 500 nm or less on the sidewalls.5. The device as recited in claim 1 , wherein the III-V crystalline compound material is included in an electronic device. This application is a Continuation application of co-pending U.S. patent application Ser. No. 13/968,756 filed on Aug. 16, 2013, incorporated herein by reference in its entirety.1. Technical FieldThe present invention relates to semiconductor processing, and more particularly to methods and devices for preparing silicon for III-V material growth.2. Description of the Related ArtSingle-element semiconductors, such as silicon and germanium, often do not provide the performance or characteristics that are needed in the ...

DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON

A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A dual phase gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. 1. A method for selectively forming a dual phase gallium nitride material on a silicon substrate , said method comprising:forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate;patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate;etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate;forming a contiguous AlN buffer layer on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate; andforming a dual phase gallium nitride material on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure, wherein said dual phase gallium nitride material comprises a wurtzite phase and a ...

SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON

A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. 1. A semiconductor structure comprising:a (100) silicon substrate having a plurality of patterned dielectric material structures located on an uppermost surface of the silicon substrate and a plurality of openings located within the silicon substrate and beneath the plurality of patterned dielectric material structures, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane; anda gallium nitride material surrounding each sidewall of each patterned dielectric material structure and located adjacent to the surface of the silicon substrate having the (111) crystal plane.2. The semiconductor structure of claim 1 , wherein said (100) silicon substrate comprises a bulk semiconductor material.3. The semiconductor structure of claim 1 , wherein said (100) silicon substrate comprises a topmost layer of a silicon-on-insulator substrate.4. The semiconductor structure of claim 1 , wherein each patterned dielectric material structure has four sidewalls.5. The semiconductor structure of claim 1 , wherein said gallium nitride material is selected from GaN claim 1 ...

CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. 1. A semiconductor structure comprisingat least one dielectric bonding material layer located on a handle substrate; anda first epitaxial semiconductor portion and a second epitaxial semiconductor portion, wherein at least a lower portion of one of said first and second epitaxial semiconductor portions is embedded within said at least one bonding material layer, wherein one of said first and second epitaxial semiconductor portions comprises a single crystalline elemental semiconductor material, and another of said first and second epitaxial semiconductor portions comprises a single crystalline compound semiconductor material.2. The semiconductor structure of claim 1 , wherein each of said first and second epitaxial semiconductor portions has a bottommost surface that is a crystallographic facet.3. The semiconductor structure of claim 1 , wherein surfaces of each of said first and second epitaxial semiconductor portions includes a plurality of angled crystallographic facets that are not horizontal and not vertical.4. The semiconductor structure of ...

CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. 1. A method of forming a semiconductor structure comprisingforming a first trench and a second trench through a dielectric template material layer on a single crystalline substrate;forming a first template epitaxial semiconductor material portion within said first trench by epitaxy of a first template semiconductor material and forming a second template epitaxial semiconductor material portion within said second trench by epitaxy of a second template semiconductor material, wherein one of the first and second template semiconductor materials is an elemental semiconductor material, and another of said first and second template semiconductor materials is a compound semiconductor material;epitaxially growing a first epitaxial semiconductor portion including a first semiconductor material that is different from said first template semiconductor material on said first template epitaxial semiconductor material portion;epitaxially growing a second epitaxial semiconductor portion including a second semiconductor material that is different from said second ...

SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON

A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. 1. A method for selectively forming a gallium nitride material on a silicon substrate , said method comprising:forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate;patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate;etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate;forming a contiguous AlN buffer layer on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate; andforming a gallium nitride material on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure.2. The method of claim 1 , wherein the blanket layer of dielectric material is formed by a thermal process.3. The method of ...

RESONANT CAVITY STRAINED GROUP III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE AND METHOD TO FABRICATE SAME

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe, where 0.8 Подробнее

EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING

A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput. 1. A method for performing epitaxial lift-off , the method comprising the steps of:providing a support structure having an upper surface which is angled relative to a bottom of a container; a growth substrate with a top and bottom surface;', 'a sacrificial layer on the top surface of the growth substrate; and', 'a device layer on the sacrificial layer;, 'receiving a sample comprisingsupporting the sample whereby an entire bottom surface of the growth substrate rests on the upper surface of the support structure inside the container; andfilling the container with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate;wherein the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant while filling the container with the wet etchant.2. The method of claim 1 , wherein the growth substrate comprises a III-V material.3. (canceled)4. The method of claim 1 , wherein the sacrificial layer comprises aluminum arsenide.5. The method of claim 1 , wherein the ...

Sputter target magnet

A method for modifying magnetic field distribution in a deposition chamber is disclosed. The method includes the steps of providing a target magnetic field distribution, removing a first plurality of fixed magnets in the deposition chamber, replacing each of the first plurality of fixed magnets with respective ones of a second plurality of magnets, performing at least one of adjusting a position of at least one of the second plurality of the magnets, and adjusting a size of at least one of the second plurality of magnets, adjusting a magnetic flux of at least one of the second plurality of magnets, measuring the magnetic field distribution in the deposition chamber, and comparing the measured magnetic field distribution in the deposition chamber with the target magnetic field distribution.

Resonant Cavity Strained Group III-V Photodetector And LED On Silicon Substrate And Method To Fabricate Same

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe, where 0.8 Подробнее

Stress Assisted Wet and Dry Epitaxial Lift Off

A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate. 1. A method , comprising:providing a sacrificial release layer on a base substrate;forming a device layer on the sacrificial release layer;depositing a metal stressor layer on the device layer;etching the sacrificial release layer; andusing epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.2. The method of claim 1 , further comprising removing the metal stressor layer from the device layer.3. The method of claim 1 , wherein providing a sacrificial release layer on a base substrate comprises epitaxially forming the sacrificial release layer on the base substrate.4. The method of claim 1 , wherein forming a device layer on the sacrificial release layer comprises providing a layer of III-V material claim 1 , applying a hardmask to pattern the layer of III-V material claim 1 , and etching the patterned hardmask.5. The method of claim 1 , wherein depositing a metal stressor layer on the device layer comprises depositing a metal by one or more of physical vapor deposition claim 1 , chemical vapor deposition claim 1 , and atomic layer chemical vapor deposition.6. The method of claim 1 , wherein etching the sacrificial release layer comprises applying one or more of a liquid etchant and a gas etchant.7. A method claim 1 , comprising:providing a base substrate;epitaxially forming a sacrificial release layer on the base substrate;epitaxially forming a layer of III-V material on the sacrificial release layer;depositing a metal stressor layer on the layer of III-V material to cause the layer of III-V material on the sacrificial release layer and the metal stressor layer to curve away from the ...

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIAL SEMICONDUCTOR MATERIAL FORMED USING LATERAL OVERGROWTH

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer. 1. An electrical device comprising:an optical interconnect positioned on a portion of the semiconductor substrate that is positioned between portions of a semiconductor substrate including electrical components, the optical interconnect is present on at least one interlevel dielectric layer that is present over at least one of the electrical components, the optical interconnect including a III-V light emission device and a III-V light detection device, wherein at least one material layer of the optical interconnect is an epitaxial material that is in direct contact with a semiconductor material layer of the substrate that is overlying a dielectric layer.2. The electrical device of claim 1 , wherein the semiconductor substrate is an SOI substrate.3. The electronic device of further comprising a dielectric waveguide positioned between the III-V light emission device and the III-V light detection device.4. The electronic device of claim 1 , wherein the electronic components comprises a switching device selected from the group consisting of field effect transistor (FET) claim 1 , fin field effect transistor (FinFET) claim 1 , metal oxide semiconductor ...

III-V PHOTONIC INTEGRATED CIRCUITS ON SILICON SUBSTRATE

A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure. 1. A semiconductor device comprising:a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure;a III-V optoelectronic device is present in direct contact with and atop the isolation dielectric material in a first region of the second portion of the substrate structure; anda dielectric wave guide is present in direct contact with and atop the isolation dielectric in a second region of the second portion of the substrate structure.2. The semiconductor device of claim 1 , wherein the substrate structure is a semiconductor on insulator (SOI) substrate claim 1 , wherein a semiconductor on insulator (SOI) layer provides the semiconductor material layer in the first portion of the substrate structure claim 1 , the SOI layer being present directly on the buried dielectric layer claim 1 , wherein the buried dielectric layer is present direction on a base semiconductor layer of the SOI substrate.3. The semiconductor device of claim 1 , wherein the semiconductor material layer is a silicon including material claim 1 , and the buried ...

III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain. 117.-. (canceled)18. A field effect transistor comprising:a source;a raised source disposed at least partially on the source and comprising III-V material;a diffusion barrier disposed at least partially on the raised source and comprising transition metal bonded with silicon or germanium;wherein the diffusion barrier is self-aligned with a gate stack, the gate stack being formed above a channel region of the transistor and laterally adjacent with the source.19. The field effect transistor of claim 18 , wherein the raised source comprises indium gallium arsenide.20. The field effect transistor of claim 18 , wherein the field effect transistor is a three-dimensional claim 18 , multi-gate device.21. The field effect transistor of claim 18 , further comprising first spacers formed on sidewalls of the gate stack.22. The field effect transistor of claim 21 , further comprising second spacers formed on sides of the first spacers.23. The field effect transistor of claim 18 , wherein the diffusion barrier comprises a compound consisting essentially of titanium bonded to germanium.24. The field effect transistor of claim 18 , wherein the field effect transistor is a planar field effect transistor. The present invention relates to the ...

ASYMMETRIC III-V MOSFET ON SILICON SUBSTRATE

A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material. 1. A semiconductor structure comprising:at least one functional gate structure straddling over a surface of a high mobility semiconductor channel material;a source region located on one side of said at least one functional gate structure and consisting of a source-side epitaxial doped semiconductor material extending laterally from a sidewall surface of said high mobility semiconductor channel material; anda drain region located on another side of said at least one functional gate structure and consisting of a drain-side epitaxial doped semiconductor material and a portion of said high mobility semiconductor channel material that extends beyond a sidewall surface of said at least one functional gate structure, wherein said source-side epitaxial doped semiconductor material and said drain-side epitaxial doped semiconductor material comprise a different semiconductor material than said high mobility semiconductor channel material.2. The semiconductor structure of claim 1 , wherein said drain-side epitaxial doped semiconductor material has a first surface that directly contacts a topmost surface of said high mobility semiconductor channel material that extends beyond said sidewall surface of said at least one functional gate structure claim 1 , a second surface that directly contacts a sidewall surface of said high mobility semiconductor channel material that extends beyond said sidewall ...

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIALLY FORMED MATERIAL

An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic tight detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device. 1. An electrical device comprising:a first semiconductor device positioned on a first portion of a type IV semiconductor substrate;an optoelectronic light emission device comprising type III-V semiconductor materials that is in electrical communication with the first semiconductor device, wherein the optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate;a dielectric waveguide present on a second portion of the type IV semiconductor substrate; andan optoelectronic light detection device comprising type III-V semiconductor material present on a third portion of the type IV semiconductor device, wherein the dielectric waveguide is positioned between and aligned with the optoelectronic light detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.2. The electronic device of claim 1 , wherein the first ...

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIAL SEMICONDUCTOR MATERIAL FORMED USING LATERAL OVERGROWTH

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer. 1. An electrical device comprising:a first semiconductor device positioned on a first portion of a semiconductor on insulator (SOI) substrate;a second semiconductor device positioned on a third portion of the SOI substrate; andan optical interconnect positioned on a second portion of the semiconductor substrate that is positioned between the first and third portions of the semiconductor substrate, the optical interconnect is present on at least one interlevel dielectric layer that is present over at least one of the first and second semiconductor devices, the optical interconnect including a III-V light emission device, a dielectric waveguide and III-V light detection device, wherein at least one material layer of at least one of the III-V light emission device and the III-V light detection device is an epitaxial material that is in direct contact with abuse semiconductor substrate of the SOI substrate through a via extending through the least one interlevel dielectric layer and a buried dielectric layer of the SOI substrate.2. The electronic device of claim 1 , wherein the first semiconductor device comprises a switching device selected from the ...

INTEGRATED CIRCUIT WITH HETEROGENEOUS CMOS INTEGRATION OF STRAINED SILICON GERMANIUM AND GROUP III-V SEMICONDUCTOR MATERIALS AND METHOD TO FABRICATE SAME

A structure includes an off-axis Si substrate with an overlying s-SiGelayer and a BOX between the off-axis Si substrate and the s-SiGelayer. The structure further includes pFET fins formed in the s-SiGelayer and a trench formed through the s-SiGelayer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-SiGelayer has a value of x that results from a condensation process that merges an initial s-SiGelayer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed. 1. A method , comprising:providing a starting substrate that comprises an off-axis Si substrate, an overlying dielectric layer and an on-axis Si layer disposed on the dielectric layer;{'sub': 1-x', 'x, 'epitaxially growing a s-SiGelayer on a surface of the on-axis Silicon layer;'}{'sub': 1-x', 'x', '1-x', 'x', '1-x', 'x, 'merging the s-SiGelayer and the on-axis Si layer to form a merged s-SiGelayer and an oxide layer disposed on the merged s-SiGelayer;'}{'sub': 1-x', 'x, 'forming a trench through the oxide layer, the merged s-SiGelayer, the dielectric layer and partially into the off-axis Si substrate;'}epitaxially growing in the trench a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer on the buffer layer, a semi-insulating Group III-V layer on the first Group III-V layer and a second Group III-V layer on the semi-insulating Group III-V layer; and{'sub': 1-x', 'x', '1-x', 'x, 'patterning and etching the merged s-SiGelayer and the second Group III-V layer to form a plurality of pFET fins in the merged s-SiGelayer and a plurality of nFET fins in the second Group III-V layer.'} ...

CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. 1. A semiconductor structure comprisingat least one dielectric bonding material layer located on a handle substrate; anda first epitaxial semiconductor portion and a second epitaxial semiconductor portion, wherein one of said first and second epitaxial semiconductor portions comprises a single crystalline elemental semiconductor material, and another of said first and second epitaxial semiconductor portions comprises a single crystalline compound semiconductor material, wherein said at least one dielectric bonding material layer comprises:a first dielectric bonding material layer not contacting said first and second epitaxial semiconductor portions; anda second dielectric bonding material layer underlying all of said first dielectric bonding material layer and contacting said first epitaxial semiconductor portion.2. The semiconductor structure of claim 1 , further comprising:a first field effect transistor located on said handle substrate, wherein said first epitaxial semiconductor portion comprises a body region, a source region, and a drain region ...

CRYSTAL FORMATION ON NON-LATTICE MATCHED SUBSTRATES

A semiconductor structure can be created by forming an insulator layer over a surface of a substrate. An intermediate layer can be formed on top of the insulator layer, wherein openings in the intermediate layer may expose regions of the insulator. Openings may be formed in the exposed regions of the insulator layer to create exposed areas of the substrate. A first element of a multi-element semiconductor can be deposited onto the exposed regions of the insulator layer, into the openings in the exposed regions of the insulator layer, and onto the exposed areas of the substrate. A capping layer can be formed over the first element of the multi-element semiconductor. The first element can be melted. A liquid solution can be created by dissolving a second element of the multi-element semiconductor into first element. A multi-element semiconductor, seeded off the substrate, can be formed from the liquid solution. 1. A method for creating semiconductor structure , having a single crystal multi-element semiconductor with a first lattice constant , on a crystalline semiconductor substrate having a second lattice constant different from the multi-element semiconductor , the method comprising:forming an insulator layer over a first top surface of the semiconductor substrate;forming an intermediate layer over a second top surface of the insulator layer;forming an opening in the intermediate layer to create an exposed region of the second top surface of the insulator layer;forming an opening in the exposed region to create an exposed area of the first top surface of the semiconductor substrate;depositing a first element of the multi-element semiconductor onto the exposed region, into the opening in the exposed region, and onto the exposed area;forming a capping layer that extends over the first element of the multi-element semiconductor;melting the first element of the multi-element semiconductor forming a melt, the melt encapsulated between the capping layer, the exposed ...

Integrated Circuit With Heterogeneous CMOS Integration Of Strained Silicon Germanium And Group III-V Semiconductor Materials And Method To Fabricate Same

A structure includes an off axis Si substrate with an overlying s-SiGe, layer and a BOX between the off-axis Si substrate and the s-SiGelayer. The structure further includes pFET fins formed in the s-SiGelayer and a trench formed through the s-SiGe, layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-SiGelayer has a value of x that results from a condensation process that merges an initial s-SiGelayer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed. 1. A structure comprising:{'sub': 1−x', 'x', '1−x', 'x, 'an off-axis Si substrate having an overlying s-SiGelayer and a buried oxide layer disposed between the off-axis Si substrate and the s-SiGelayer;'}{'sub': 1−x', 'x, 'a first plurality of pFET fins formed in the s-SiGelayer;'}{'sub': 1−x', 'x, 'a trench formed through the s-SiGelayer, the buried oxide layer and partially into the off-axis Si substrate, the trench containing a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer; and'}a first plurality of nFET fins formed in the second Group III-V layer.2. The structure as in claim 1 , further comprising a dielectric spacer disposed on vertical sidewalls of the trench.3. The structure as in claim 1 , where the s-SiGelayer has a value of x that results from a condensation process that merges an initial s-SiGelayer having an initial value of x with an underlying initial on-axis <100> Si ...

III-V PHOTONIC INTEGRATED CIRCUITS ON SILICON SUBSTRATE

A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure. 1. A semiconductor device comprising:a substrate structure including an isolation dielectric material that is present directly on a buried dielectric layer;a III-V optoelectronic device in direct contact with the isolation dielectric material and on the buried dielectric layer of the substrate structure; anda dielectric wave guide is present in direct contact with the isolation dielectric of the substrate structure, the dielectric waveguide being composed of a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, silica and combinations thereof.2. The semiconductor device of claim 1 , wherein the substrate structure includes a semiconductor on insulator (SOI) substrate claim 1 , wherein a semiconductor on insulator (SOI) layer provides a semiconductor material layer in a first portion of the substrate structure claim 1 , the SOI layer being present directly on the buried dielectric layer claim 1 , wherein the buried dielectric layer is present directly on a base semiconductor layer of the SOI substrate.3. The semiconductor device of claim 2 , wherien the III-V optoelectronic device and the dielectric wave guide are substantially aligned along a first plane of the substrate claim 2 ...

CRACK CONTROL FOR SUBSTRATE SEPARATION

A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack. 1. A method for separating a layer for transfer , comprising:forming a crack guiding layer on a surface of a substrate;forming a device layer on the crack guiding layer; andweakening the crack guiding layer by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer to remove the device layer from the substrate.2. The method as recited in claim 1 , wherein forming the crack guiding layer on the surface of the substrate includes growing the crack guiding layer on a monocrystalline substrate.3. The method as recited in claim 1 , wherein the crack guiding layer includes AlAs and the device layer includes a III-V material.4. The method as recited in claim 1 , wherein weakening the crack guiding layer includes exposing the crack guiding layer to oxygen or a compound including oxygen.5. The method as recited in claim 1 , further comprising forming a stress inducing layer on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces.6. The method as recited in claim 5 , wherein forming the stress inducing layer includes depositing one of Ni claim 5 , W claim 5 , Co and SiGe.7. The method as recited in claim 1 , further comprising forming recesses in the crack guiding layer by etching the crack guiding layer at exposed portions at a periphery to pre-form a crack.8. The method as recited in claim 1 , further comprising forming a protection layer on the ...

PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL

A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. 1. A semiconductor structure , comprising:a III-V monocrystalline layer that includes a source and drain region for a device;a crystalline germanium surface layer that includes a source and drain extension for the respective source and drain regions of the device; andan interlayer formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.2. The semiconductor structure as recited in claim 1 , wherein the III-V monocrystalline layer includes one of GaAs claim 1 , InP claim 1 , GaP claim 1 , GaN claim 1 , GaSb and alloys thereof.3. The semiconductor structure as recited in claim 1 , wherein the interlayer includes one of P claim 1 , As claim 1 , Ga claim 1 , Si or combinations thereof.4. The semiconductor structure as recited in claim 1 , wherein the interlayer includes a thickness of less than about 20 nm.5. The semiconductor structure as recited in claim 1 , wherein the interlayer includes a thickness of less than about 5 nm.6. The semiconductor structure as recited in claim 1 , wherein the surface layer includes a defect density of less than 109/cm2.7. A semiconductor structure claim 1 , ...

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. 1. A method for fabricating a semiconductor device with selective oxidation , the method comprising:providing a semiconductor substrate comprising a stack of two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers are disposed on a top surface of the semiconductor substrate;depositing an insulating material on the semiconductor substrate;etching one or more recesses into the insulating material to form a set of fins;selectively oxidizing one of the two crystalline semiconductor layers;forming a dummy gate structure and a set of spacers along sides of the dummy gate structure;forming a source drain region adjacent to the dummy gate structure;removing the dummy gate structure; andreleasing the selectively oxidized crystalline semiconductor layer.2. The method of claim 1 , further comprising:forming a replacement gate structure between the set of spacers; anddepositing a high-K material around the replacement gate structure.3. The method of claim 1 , wherein the stack of two crystalline semiconductor layers comprises a first layer configured to oxidize to an insulator and a second semiconductor layer configured to not oxidize to an insulator.4. The method of claim 1 , wherein the step of selectively oxidizing one of the two crystalline semiconductor layers comprises exposing the semiconductor substrate in water ...

PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL

A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. 1. A method for fabricating a semiconductor structure , comprising:forming a source and drain region for a device in a III-V monocrystalline layer;removing impurities from the III-V monocrystalline layer;forming an interlayer directly on the III-V monocrystalline layer over the source and drain regions from a material selected to provide stronger nucleation bonding between the interlayer and a germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer; andgrowing a crystalline germanium surface layer directly on the interlayer to form a source and drain extension for the respective source and drain regions of the device, such that a continuous, relatively defect-free germanium surface layer is provided.2. The method as recited in claim 1 , wherein removing impurities includes baking the III-V monocrystalline layer at a temperature of between 500 and 800 degrees C.3. The method as recited in claim 2 , wherein baking includes subjecting the III-V monocrystalline layer to a reactive chemical flow.4. The method as recited in claim 1 , further comprising treating the interlayer before forming the germanium surface layer by baking the interlayer layer at a temperature of between 450 and 600 degrees C.5. The method as recited in claim 4 , wherein baking the interlayer layer includes subjecting the interlayer layer to a reactive chemical flow to remove ...

ENHANCED DEFECT REDUCTION FOR HETEROEPITAXY BY SEED SHAPE ENGINEERING

A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region. 1. A heteroepitaxially grown structure , comprising:a cavity formed in a substrate has a shape with one or more surfaces and including a resistive neck region at an opening to a trench;a heteroepitaxially grown material formed on the substrate through the trench; andthe heteroepitaxially grown material including a first region in or near the cavity and a second region outside the first region.2. The structure as recited in claim 1 , wherein the second region is defect free.3. The structure as recited in claim 1 , wherein the one or more surfaces in the cavity face each other to direct defects to interact with each other.4. The structure as recited in claim 1 , further comprising a buffer layer lining the one more surfaces in the cavity.5. The structure as recited in claim 1 , wherein the one or more surfaces in the cavity include a continuous surface.6. The structure as recited in claim 1 , wherein the one or more surfaces constrain defects in four or more growth directions.7. The structure as recited in claim 1 , wherein the heteroepitaxially grown material forms a portion of an electronic device.8. The structure as recited in claim 1 , wherein the substrate includes an insulator claim 1 ,9. The structure as recited in claim 1 , wherein the substrate includes a metal.10. A hetero epitaxially grown structure claim 1 , comprising:a cavity formed in a crystalline semiconductor substrate having a shape with one or more surfaces and including a resistive neck region at an ...

VERTICAL FIELD EFFECT TRANSISTORS WITH CONTROLLED OVERLAP BETWEEN GATE ELECTRODE AND SOURCE/DRAIN CONTACTS

An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar. 1. A method of forming a vertical field effect transistor with a controlled gate overlap , comprising:forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer;forming a first pillar on a portion of the fourth semiconductor layer composed of the first dielectric layer and a first drain contact surrounded by a deposited first spacer, the first drain contact composed of the fifth semiconductor layer;forming a second pillar below the first pillar including a second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer;forming a first source contact composed of the first semiconductor layer; andforming a gate electrode on a portion of the first source contact surrounding a portion of the first pillar and the second pillar.2. The method of claim 1 , wherein ...

Resonant Cavity Strained Group III-V Photodetector And LED On Silicon Substrate And Method To Fabricate Same

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe(, where 0.8 Подробнее

III-V CMOS CO-INTEGRATION

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces. 1. A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element , the method comprising:forming a mandrel in the region;growing III-V semiconductor materials on the mandrel;pulling the mandrel from a gate space in which a capped gate structure is formable and from source or drain (S/D) contact spaces; andgrowing III-V semiconductor materials in the S/D contact spaces.2. The method according to claim 1 , wherein the mandrel comprises at least one of silicon or silicon germanium.3. The method according to claim 1 , wherein the III-V semiconductor materials comprise indium-gallium-arsenide (InGaAs).4. The method according to claim 1 , wherein the growing of the III-V semiconductor materials on the mandrel comprises growing the III-V semiconductor material on sidewalls of the mandrel.5. The method according to claim 4 , wherein:the pulling of the mandrel from the gate space comprises leaving the grown III-V semiconductor materials in place; andthe forming of the capped gate structure in the gate space comprises forming the capped gate structure between the grown III-V semiconductor materials left in place.6. The method according to further comprising depositing and planarizing middle-of-line (MOL) dielectric following the growing of the III-V semiconductor materials in the S/D contact spaces.7. A method of fabricating a semiconductor device in p- and n-type field effect transistor (PFET and NFET) regions of a wafer element claim 1 , the method comprising:forming capped gate structures in ...

EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING

A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput. 1. A method for performing epitaxial lift-off , the method comprising the steps of:providing a support structure having an upper surface which is angled relative to a bottom of a container; a growth substrate with a top and bottom surface;', 'a sacrificial layer on the top surface of the growth substrate; and', 'a device layer on the sacrificial layer;, 'receiving a sample comprisingsupporting the sample whereby an entire bottom surface of the growth substrate rests on the upper surface of the support structure inside the container; andfilling the container with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate;wherein the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant while filling the container with the wet etchant; andwherein, while filling the container with the wet etchant, the bottom surface of the growth substrate is not in contact with the wet etchant.2. The method of claim 1 , wherein the growth substrate comprises a III-V ...

INTEGRATION OF III-V COMPOUND MATERIALS ON SILICON

A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices. 1. A method of forming a semiconductor device , the method comprising:depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; andgrowing a III-V compound material on the aluminum-base interlayer.2. The method of claim 1 , wherein the aluminum-base interlayer is about 0.1 nanometer to about 50 nanometers.3. The method of claim 1 , wherein the aluminum-base interlayer is deposited via a chemical vapor deposition or atomic layer deposition process.4. The method of claim 1 , wherein the aluminum-base interlayer comprises an interlayer material that is compositionally different from the III-V compound material grown on the aluminum-base interlayer.5. The method of claim 1 , wherein the aluminum-base interlayer comprises AlAs claim 1 , AlP claim 1 , AlInP claim 1 , InAlAs claim 1 , AlGaAs claim 1 , or combinations thereof.6. The method of claim 1 , wherein the III-V compound material is grown continuously layer by layer.7. The method of claim 1 , wherein the aluminum-base interlayer and the III-V compound material are deposited or grown between dielectric stacks deposited on the silicon substrate.8. The method of claim 1 , wherein the silicon substrate is a patterned substrate comprising silicon fins forming trenches; each silicon fins having a top surface and two sidewalls; and wherein a hard mask material is deposited on top surfaces of the silicon fins and dielectric layers are ...

Analog front end circuit with noise cancellation

The disclosure includes a touch display apparatus having AFE circuit that performs a noise cancellation of an AFE channel by utilizing noise signal received by a neighboring AFE channels. The first AFE channel includes a first integrator having an input terminal coupled to the first terminal receiving a first sensing signal. The second AFE channel includes an input amplifier. The second AFE channel is coupled between the input terminal of the first integrator in the first AFE channel and a second terminal connected to the touch panel. The second AFE channel is configured to generate a reversal input signal based on a second sensing signal received by the second terminal and couple the reversal input signal to a common node between the first integrator and the first terminal.

DUAL ISOLATION FIN AND METHOD OF MAKING

A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer. 1. A method of making a dual isolation fin comprising:applying a mask to portions of a substrate and etching exposed areas of the substrate to form a mandrel;forming a dielectric layer disposed on a surface of the substrate and adjacent to the mandrel;forming a first epitaxially formed material on an exposed portion of the mandrel;forming a second epitaxially formed material on the first epitaxially formed material;forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material;removing the mask and mandrel after forming the first isolation layer to form an open area of the substrate;removing the first epitaxially formed material after removing the mask and mandrel; andforming a second isolation layer in the open area of the substrate.2. The method of claim 1 , wherein the substrate comprises silicon.3. The method of claim 1 , wherein the mandrel has a height of 50 to 200 nanometers.4. The method of claim 1 , wherein the dielectric layer has a thickness of 30 to 100 nanometers.5. The method of claim 1 , wherein the first epitaxially formed material has a lattice constant intermediate to the second epitaxially formed material lattice constant and the mandrel lattice constant.6. The method of claim 1 , wherein the second ...

SMOOTHING SURFACE ROUGHNESS OF III-V SEMICONDUCTOR FINS FORMED FROM SILICON MANDRELS BY REGROWTH

A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers. 1. A method of forming a III-V semiconductor vertical fin , comprising:forming a fin mandrel on a substrate;forming a spacer layer on the substrate surrounding the fin mandrel;forming a wetting layer on each of the sidewalls of the fin mandrel;aiming a fin layer on each of the wetting layers;removing the fin mandrel;removing the wetting layer on each of the fin layers; andforming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.2. The method of claim 1 , wherein the wetting layers are made of aluminum arsenide (AlAs) or indium phosphide (InP).3. The method of claim 2 , wherein the wetting layers are formed by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE).4. The method of claim 1 , wherein the fin layers are a III-V semiconductor material.5. The method of claim 4 , wherein the material of the fin layers are selected from the group consisting of indium phosphide (InP) claim 4 , indium arsenide (InAs) claim 4 , indium-gallium-arsenide (InGaAs) claim 4 , and combinations thereof.6. The method of claim 5 , wherein the fin layers are formed by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE).7. The method of claim 6 , wherein the fin mandrel is made of single crystal silicon claim 6 , and the wetting layer is formed on a {111} crystal face of the fin ...

REACTIVATION OF A DEPOSITED METAL LINER

Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material. 1. A method of forming a metal nitride liner in a phase change memory device , the method comprising:depositing a metal nitride liner on a heater element in a dielectric material and on the dielectric material;performing a sputter clean process to remove surface oxides on the metal nitride liner;performing a nitridation of the metal nitride liner with a nitrogen plasma; and;depositing a phase change material on the metal nitride liner.2. The method of claim 1 , wherein the depositing the metal liner claim 1 , the sputter clean process claim 1 , the nitridation of the metal nitride liner claim 1 , and the depositing the phase change material on the metal nitride liner occur while maintaining an oxygen-free environment.3. The method of claim 1 , further comprising forming a top electrode over the phase change material.4. The method of claim 1 , wherein depositing the metal nitride liner on the heater element in the dielectric material and on the dielectric material claim 1 , further comprises patterning and selectively etching a portion of a layer of the metal nitride liner on the dielectric material.5. The method of claim 2 , wherein the nitridation of the metal liner using the nitrogen plasma repairs damage to a top surface of the metal nitride occurring during the sputter clean process and provides a desired electrical resistance of the metal nitride liner by adjusting one or more of a stoichiometry of the metal nitride liner and an atomic ...

INTEGRATION OF GE-CONTAINING FINS AND COMPOUND SEMICONDUCTOR FINS

A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin. The dielectric masking layer and fin cap dielectrics can removed to provide germanium-containing semiconductor fins and compound semiconductor fins. 1. A semiconductor structure comprising:a ring-shaped compound semiconductor fin comprising a compound semiconductor material and located on an insulator layer; anda pair of germanium-containing semiconductor material portions in contact with sidewalls of said ring-shaped compound semiconductor fin.2. The semiconductor structure of claim 1 , wherein said ring-shaped compound semiconductor fin comprises:a pair of lengthwise semiconductor fin sections that are parallel to each other; anda pair of widthwise semiconductor fin sections.3. The semiconductor structure of claim 2 , wherein inner sidewalls of said pair of widthwise semiconductor fin sections and end portions of inner sidewalls of said pair of lengthwise semiconductor fin sections are in contact with said pair of germanium-containing semiconductor material portions.4. The semiconductor structure of claim 1 , further comprising a compound semiconductor material layer comprising ...

III-V FINFETS ON SILICON SUBSTRATE

A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. 1. A fin field effect transistor , comprising:a substrate formed from a monocrystalline silicon or germanium material;a dielectric layer having trenches formed therein, the dielectric layer having a lower surface present on a first portion of an upper surface of the substrate;a plurality of parallel fins formed from a III-V material in the trenches and being in contact with a second portion of the upper surface of the substrate that is adjacent and coplanar with the first portion of the upper surface of the substrate, the trenches being initially dimensioned and configured to have a high aspect ratio including a height to width ratio of greater than about 1:1 to enable non-lattice-matched crystalline III-V material to be formed on the substrate;a gate stack including a barrier layer, a gate dielectric and a gate conductor formed transversely to the plurality of parallel fins; andraised source and drain regions formed from a III-V material and being in contact with the fins on opposite sides of the gate stack.2. The transistor as recited in claim 1 , wherein the fins include side wall spacers about a top portion and the top portion includes implanted ...

III-V FINFETS ON SILICON SUBSTRATE

A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. 1. A method for forming fin field effect transistors , comprising:forming one or more dielectric layers on a silicon substrate;forming high aspect ratio trenches in the one or more dielectric layers down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1;epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins;etching the one or more dielectric layers to expose a portion of the fins;epitaxially growing a barrier layer on the portion of the fins;forming a gate stack over the fins in a transverse orientation relative to a longitudinal direction of the fins;forming a spacer around the portion of the fins and the gate stack;implanting dopants into the portion of the fins; andgrowing source and drain regions over the fins using a non-silicon containing semiconductor material.2. The method as recited in claim 1 , wherein the non-silicon containing semiconductor material includes at least one of a III-V material and a II-VI material.3. The method as recited in claim 1 , wherein epitaxially growing a non-silicon containing semiconductor ...

III-V TRANSISTOR DEVICE WITH DOPED BOTTOM BARRIER

A method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, forming a raised source/drain region on the first layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate. 1. A method for forming a semiconductor device , the method comprising:forming a sacrificial gate stack on a channel region of a first layer of a substrate;forming a spacer adjacent to the sacrificial gate stack;forming a raised source/drain region on the first layer of the substrate adjacent to the spacer after forming the spacer adjacent to the sacrificial gate stack;forming a silicide region on the source/drain region;forming a dielectric layer over the raised source/drain region after forming the silicide region on the source/drain region;removing the sacrificial gate stack to expose the channel region of the first layer of the substrate; andimplanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate.2. The method of claim 1 , further comprising forming a metal gate stack on the channel region of the first layer of the substrate.3. The method of claim 1 , wherein the forming the raised source/drain region includes growing a doped semiconductor material on an exposed portion of the first layer of the substrate.5. The method of claim 1 , wherein the second layer of the ...

III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer. 1. An electrical device comprising:a base semiconductor layer;a dielectric layer present on the base semiconductor layer;a first III-V semiconductor material area present in a trench in the dielectric layer, wherein the III-V semiconductor material is in direct contact with at least the dielectric layer at a base of the trench, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer;a second III-V semiconductor material area present in the trench in the dielectric layer wherein the III-V semiconductor material is in direct contact with at least the dielectric layer at a base of the trench and the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; anda semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric ...

III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer. 1. A method of forming a semiconductor device , the method comprising:forming a trench in a dielectric layer, the dielectric layer being present on a semiconductor substrate;forming a via within the trench, wherein the via extending from a base of the trench present at a depth within the dielectric layer to an exposed upper surface of the semiconductor substrate;epitaxially forming a III-V semiconductor material extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench;forming a trench in the epitaxially formed III-V semiconductor to result in a first III-V semiconductor area comprising the via and a second III-V semiconductor area free of the via. wherein the trench in the epitaxially formed III-V semiconductor extends from a top surface through a bottom surface of the epitaxially formed III-V semiconductor; andforming the semiconductor device on the second III-V semiconductor area.2. The method of claim 1 , further comprising filling the trench in the epitaxially formed III-V semiconductor with a dielectric material prior to ...

PCM CELL WITH RESISTANCE DRIFT CORRECTION

Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature. 1. A method for forming a phase-change memory device , comprising:forming a fin structure from a first material; andforming a phase change memory cell, around the fin structure, from a phase change material that includes two solid state phases at an operational temperature.2. The method of claim 1 , further comprising forming a heater before forming the fin structure claim 1 , wherein the fin structure is formed on the heater.3. The method of claim 1 , wherein the first material has a resistivity at the operational temperature that is between a resistivity of a first phase of the phase change material at the operational temperature and a resistivity of a second phase of the phase change material at the operational temperature.4. The method of claim 3 , wherein the first material is titanium nitride and the phase change material is a germanium-antimony-tellurium alloy.5. The method of claim 1 , further comprising etching the fin structure and the phase change memory cell to form a pillar.6. The method of claim 1 , further comprising forming a top electrode over the phase change memory cell and the fin structure.7. The method of claim 6 , wherein forming the top electrode is performed before the phase change memory cell is formed claim 6 , using the top electrode as a mask to etch the phase change memory cell.8. The method of claim 6 , wherein forming the phase change memory cell is performed before top electrode is formed.9. A method for forming a phase-change memory device claim 6 , comprising:forming a bottom electrode on a substrate;forming a heater on the bottom electrode;forming a fin structure from a first material on the heater;forming a phase change memory cell, around the fin structure, ...

BONDING PROCESS USING TEMPERATURE CONTROLLED CURVATURE CHANGE

A first substrate including a radius of curvature and a stressor layer is first provided. An outermost bowed, e.g., curved, surface of the first substrate is then brought into intimate contact with a surface of a second substrate. Bonding of the entirety of the first substrate to the second substrate is then achieved by reducing the radius of curvature of the first substrate by controlling the temperature at which bonding occurs. 1. A method of bonding a first substrate to a second substrate , said method comprising:providing a first substrate having a radius of curvature and containing a stressor layer;contacting an outermost bowed surface of said first substrate to a portion of a surface of a second substrate; andbonding said first substrate to an entirety of said surface of said second substrate, wherein said bonding is performed at a temperature that removes said radius of curvature of said first substrate.2. The method of claim 1 , wherein said first substrate comprises a spalled material portion of a base substrate.3. The method of claim 2 , wherein said spalled material portion of said base substrate is provided by a method that comprises:forming said stressor layer above a surface of said base substrate; andremoving said material portion of said base substrate from said base substrate by performing a spalling process.4. The method of claim 3 , further comprising forming an edge exclusion material on said surface and at each vertical edge of said base substrate prior to forming said stressor layer.5. The method of claim 4 , wherein said edge exclusion material comprises a photoresist material claim 4 , a polymer claim 4 , a hydrocarbon material claim 4 , an ink claim 4 , a metal claim 4 , or a paste.6. The method of claim 3 , further comprising forming a handle substrate on an exposed surface of said stressor layer prior to performing said spalling process.7. The method of claim 6 , wherein said spalling process further comprises pulling or peeling said ...

III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER

A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins. 1. A field effect transistor , comprising:a plurality of fins, at least a portion of a given fin comprising a respective source region;a raised source disposed at least partially on the plurality of fins and comprising III-V material;a diffusion barrier disposed at least partially on the raised source and comprising transition metal bonded with silicon or germanium; anda gate stack capacitively coupled at least to the respective source regions of the fins.2. The field effect transistor of claim 1 , wherein the raised source comprises indium gallium arsenide.3. The field effect transistor of claim 1 , wherein the field effect transistor is a three-dimensional claim 1 , multi-gate device.4. The field effect transistor of claim 1 , wherein the fins comprise indium gallium arsenide.5. The field effect transistor of claim 1 , wherein the fins pass through the gate stack.6. The field effect transistor of claim 1 , wherein the gate stack and the fins are disposed on a buried oxide layer.7. The field effect transistor of claim 6 , wherein the buried oxide layer has recessed regions between respective fins. This patent application is a divisional of U.S. patent application Ser. No. 14/870,794 filed Sep. 30, 2015, entitled “III-V MOSFET WITH SELF-ALIGNED DIFFUSION BARRIER” The complete disclosure of the aforementioned U.S. patent application Ser. No. 14/870,794 is expressly incorporated herein by reference in its entirety for all purposes.This application is also related to U.S ...

DUAL ISOLATION FIN AND METHOD OF MAKING

A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer. 1. A semiconductor structure comprising:a substrate and a mandrel;a dielectric layer disposed on a surface of the substrate and adjacent to the mandrel;a first epitaxially formed material disposed on a portion of the dielectric layer and adjacent to the mandrel;a second epitaxially formed material disposed on a portion of the dielectric layer and adjacent to the first epitaxially formed material; anda first isolation layer disposed on top of the surface of the dielectric layer and adjacent to the second epitaxially formed material.2. The structure of claim 1 , wherein the mandrel has a height of 50 to 200 nanometers.3. The structure of claim 1 , wherein the mandrel comprises silicon.4. The structure of claim 1 , wherein the first isolation layer has a thickness less than the height of the second epitaxially formed material.5. The structure of claim 1 , wherein the dielectric layer has a thickness of 30 to 100 nanometers.6. The structure of claim 1 , wherein the first epitaxially formed material has a lattice constant intermediate to a lattice constant of the second epitaxially formed material and a lattice constant of the mandrel.7. The structure of claim 1 , wherein the second epitaxially formed material has a thickness less than or equal to 30 nanometers.8. The ...

III-V CMOS INTEGRATION ON SILICON SUBSTRATE VIA EMBEDDED GERMANIUM-CONTAINING LAYER

After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor. 1. A semiconductor structure comprisinga substrate comprising a handle substrate, a compound semiconductor template layer present on the handle substrate, and a buried insulator layer present on the compound semiconductor template layer;a top elemental semiconductor layer portion present on a first portion of the substrate and in contact with a top surface of the buried insulator layer; anda stack of compound semiconductor layers present on a second portion of the substrate and comprising a compound semiconductor buffer layer in contact with a top surface of the compound semiconductor template layer and a top compound semiconductor layer present on the compound semiconductor buffer layer, wherein a lower portion of the stack is laterally surrounded by the buried insulator layer, and wherein an upper portion of the top compound semiconductor layer protrudes above a horizontal plane including a top surface of the top elemental semiconductor layer portion.2. The semiconductor structure of claim 1 , wherein the compound semiconductor template layer comprises germanium or silicon germanium.3. The semiconductor structure of claim 1 , wherein the compound semiconductor ...

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIAL SEMICONDUCTOR MATERIAL FORMED USING LATERAL OVERGROWTH

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer. 1. An electrical device comprising:a first electrical component positioned on a first portion of a semiconductor on insulator (SOI) substrate;a second electrical component positioned on a third portion of the SOI substrate; andan optical interconnect positioned on a second portion of the semiconductor substrate that is positioned between the first and third portions of the semiconductor substrate, the optical interconnect is present on at least one interlevel dielectric layer that is present over at least one of the first and second electrical components, the optical interconnect including a III-V light emission device and a III-V light detection device, wherein at least one material layer of at least one of the III-V light emission device and the III-V light detection device is an epitaxial material that is in direct contact with a semiconductor material layer of the SOI substrate.2. The electronic device of further comprising a dielectric waveguide positioned between the III-V light emission device and the III-V light detection device.3. The electronic device of claim 1 , wherein the first electronic component comprises a switching device ...

SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material. 1. A method for forming an epitaxial structure , comprising:opening up portions of a two-dimensional material on a semiconductor material to expose the semiconductor material; andepitaxially growing a structure in the portions opened up in the semiconductor material such that the epitaxial growth is selective to the exposed semiconductor material relative to the two-dimensional material.2. The method as recited in claim 1 , wherein the two dimensional material includes graphene.3. The method as recited in claim 1 , wherein the two dimensional material includes MoSor WS.4. The method as recited in claim 1 , wherein the two-dimensional material is transferred to the semiconductor material by a layer transfer process.5. The method as recited in claim 1 , wherein opening up portions of the two-dimensional material includes forming an etch mask using lithography and etching the two-dimensional material to open up the portions.6. The method as recited in claim 1 , further comprising removing the two-dimensional material.7. A method for forming an epitaxial structure claim 1 , comprising:patterning a two-dimensional material on a semiconductor substrate by opening up portions of the two-dimensional material to expose the semiconductor substrate;selectively growing a structure on exposed portions of the semiconductor substrate using an epitaxial growth process such that the epitaxial growth is selective to the exposed semiconductor material relative to the two-dimensional material; andremoving the two-dimensional material.8. ...

Resonant Cavity Strained Group III-V Photodetector And LED On Silicon Substrate And Method To Fabricate Same

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe, where 0.8 Подробнее

CRACK CONTROL FOR SUBSTRATE SEPARATION

A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack. 1. A method for separating a layer for transfer , comprising:forming a crack guiding layer on a substrate;forming a device layer on the crack-guiding layer;weakening the crack guiding layer by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer;forming a stress inducing layer on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces; andremoving the device layer from the substrate by propagating the crack.2. The method as recited in claim 1 , wherein the crack guiding layer includes AlAs and the device layer includes a III-V material.3. The method as recited in claim 1 , wherein weakening the crack guiding layer includes exposing the crack guiding layer to oxygen or a compound including oxygen.4. The method as recited in claim 1 , further comprising etching the crack guiding layer at exposed portions on a periphery to pre-form the crack.5. The method as recited in claim 1 , wherein forming the stress inducing layer includes depositing one of Ni claim 1 , W claim 1 , Co and SiGe.6. The method as recited in claim 1 , further comprising forming a protection layer on the substrate before forming the crack guiding layer.7. The method as recited in claim 1 , further comprising applying a holder substrate to the device layer to enable transport for transferring the device layer.8. The method as recited in claim 1 , further comprising reusing the ...

HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS

Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a () silicon layer, a () silicon layer located on an uppermost surface of the () silicon layer, a Group III nitride material layer located on an uppermost surface of the () silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the () Si layer and within a portion of the () silicon layer. A dielectric spacer is then formed within the opening An epitaxial semiconductor material is then formed on an exposed surface of the () silicon layer within the opening and thereafter planarization is performed. 1. A method of integrating a Group III nitride material and silicon , said method comprising:{'b': 100', '111', '100', '111, 'providing a structure comprising, from bottom to top, a () silicon layer, a () silicon layer located on an uppermost surface of the () silicon layer, a Group III nitride material layer located on an uppermost surface of the () silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer;'}{'b': 111', '100', '100', '100, 'forming an opening through the blanket layer of dielectric material, the Group III nitride material layer, the () Si layer and partially within the () silicon layer, wherein a surface of the () silicon layer beneath the uppermost surface of the () silicon layer is exposed;'}forming a conformal dielectric material liner atop remaining portions of the blanket layer of dielectric material and within said opening;{'b': '100', 'removing horizontal portions of the conformal dielectric material liner to provide template dielectric spacers partially covering said exposed surface of the () silicon layer;'}{'b': '100', ' ...

Resonant Cavity Strained Group III-V Photodetector And LED On Silicon Substrate And Method to Fabricate Same

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe, where 0.8 Подробнее

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. 1. A method for fabricating a semiconductor device with selective oxidation , the method comprising:providing a semiconductor substrate comprising a stack of two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers are disposed on a top surface of the semiconductor substrate;depositing an insulating material on the semiconductor substrate;etching one or more recesses into the insulating material to form a set of fins;selectively oxidizing one of the two crystalline semiconductor layers;forming a dummy gate structure and a set of spacers along sides of the dummy gate structure;forming a source drain region adjacent to the dummy gate structure;removing the dummy gate structure; andreleasing the selectively oxidized crystalline semiconductor layer.2. The method of claim 1 , further comprising:forming a replacement gate structure between the set of spacers; anddepositing a high-K material around the replacement gate structure.3. The method of claim 1 , wherein the stack of two crystalline semiconductor layers comprises a first layer configured to oxidize to an insulator and a second semiconductor layer configured to not oxidize to an insulator.4. The method of claim 1 , wherein the step of selectively oxidizing one of the two crystalline semiconductor layers comprises exposing the semiconductor substrate in water ...

CMOS With Middle Of Line Processing Of III-V Material On Mandrel

A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures. 116-. (canceled)17. A structure , comprising:a substrate having a handle layer of silicon, a buried oxide layer on the handle layer, an NFET layer of silicon-on-insulator on an NFET portion of the buried oxide layer, and a PFET layer of silicon-on-insulator or SiGe on a PFET portion of the buried oxide layer;fins in the silicon-on-insulator or SiGe of the PFET layer;source/drains in the PFET layer;one or more first metal gates on the fins, wherein the fins, the source/drains in the PFET layer, and the one or more first metal gates on the fins are annealed;channel structures of III-V material in the silicon-on-insulator in the NFET portion, wherein the channel structures are not annealed;source/drains in the NFET portion; andone or more second metal gates on the channel structures in the NFET layer.18. The structure of claim 17 , further comprising a high-k dielectric layer on the channel structures in the NFET layer.19. The structure of claim 17 , wherein the one or more second metal gates are capped.20. The structure of claim 19 , wherein the one ...

REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER

In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. 1. A semiconductor device comprising:a III-V base semiconductor layer;a III-V ground plane layer present on the III-V base semiconductor layer;an island of undoped III-V aluminum containing semiconductor layer that is present on the III-V ground plane layer;aluminum containing oxide regions on opposing sides of the island of the undoped III-V aluminum containing semiconductor layer;a III-V channel layer that is present on the island of the undoped III-V aluminum containing semiconductor layer;a raised III-V source region and a raised III-V drain region are present on the aluminum containing oxide regions and positioned on opposing sides of the III-V channel layer; anda gate structure on the III-V channel layer.2. The semiconductor device of claim 1 , wherein interconnects are formed to the raised III-V source region and the raised III-V drain region claim 1 , and wherein said interconnects are obstructed from penetrating to the III-V ground plane layer by the aluminum containing oxide regions.3. The semiconductor device of claim 1 , wherein the III-V ground plane layer is doped to an n-type conductivity.4. The semiconductor device of claim 1 , wherein the III-V ground plane layer is comprised of aluminum arsenic (AlAs).5. The ...

REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER

In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. 1. A method of forming a semiconductor device comprising:forming a gate structure on a channel portion of III-V semiconductor substrate, wherein the III-V semiconductor substrate includes a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer that is present on the aluminum containing III-V semiconductor layer, wherein the gate structure is present on the III-V channel layer;oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure;forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized; andforming interconnects to the raised source region and the raised drain region.2. The method of claim 1 , wherein the aluminum containing III-V semiconductor layer is comprised of an undoped semiconductor.3. The method of claim 2 , wherein a ground plane layer of a doped aluminum containing III-V semiconductor material is present between the aluminum containing III-V semiconductor layer and the III-V base substrate layer.4. The method of claim 2 , wherein the ground plane layer is doped to an n-type ...

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR STRUCTURE WITH III-V AND SILICON GERMANIUM TRANSISTORS ON INSULATOR

Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET. 1. A CMOS structure comprising:a NFET, formed on a wafer, having a gate stack and a channel;a PFET, formed on the wafer, having a gate stack and a channel;wherein the channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material;wherein there is a height difference between a terminal of the NFET and a terminal of the PFET; andthe gate stack NFET is the same height as the gate stack PFET.2. The CMOS structure of claim 1 , wherein the NFET channel and/or the PFET channel has a thickness of 10 nm or less.3. The CMOS structure of claim 1 , wherein the terminal of the NFET includes III-V semiconductor material.4. The CMOS structure of claim 1 , wherein the III-V semiconductor material is InGaAs with low In content.5. The CMOS structure of claim 1 , wherein the valence band offset is about 0.5 eV or less.6. The CMOS structure of claim 1 , wherein the PFET channel includes SiGe or Ge.7. The CMOS structure of claim 1 , wherein the height difference between the terminal of the NFET and the terminal of the PFET is a thickness of the ...

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIALLY FORMED MATERIAL

An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic light detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device. 1. An electrical device comprising:a first semiconductor device positioned on a first portion of a type IV semiconductor substrate;an optoelectronic light emission device comprising type III-V semiconductor materials that is in electrical communication with the first semiconductor device, wherein the optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate; andan optoelectronic light detection device comprising type III-V semiconductor material present on a second portion of the type IV semiconductor device.2. The electronic device of claim 1 , wherein the first semiconductor device comprises a switching device selected from the group consisting of field effect transistor (FET) claim 1 , fin field effect transistor (FinFET) claim 1 , metal oxide semiconductor field effect transistor (MOSFET) claim 1 , bipolar junction transistor (BJT) claim 1 , Schottky barrier semiconductor device claim 1 , junction field effect ...

SMOOTHING SURFACE ROUGHNESS OF III-V SEMICONDUCTOR FINS FORMED FROM SILICON MANDRELS BY REGROWTH

A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers. 1. A III-V semiconductor vertical fin device , comprising:a spacer layer on a substrate, wherein the material of the spacer layer is a flowable oxide;a vertical fin on the spacer layer, wherein the vertical fin is a binary or ternary III-V semiconductor material;a gate structure over a middle section of the vertical fin.2. The III-V semiconductor vertical fin device of claim 1 , wherein the material of the vertical fin is selected from the group consisting of indium phosphide (InP) claim 1 , indium arsenide (InAs) claim 1 , indium-gallium-arsenide (InGaAs) claim 1 , and combinations thereof.3. The III-V semiconductor vertical fin device of claim 2 , further comprising a source/drain on each of the opposite sides of the gate structure.4. The III-V semiconductor vertical fin device of claim 3 , wherein the source/drains are made of the same III-V semiconductor material as the vertical fin.5. The III-V semiconductor vertical fin device of claim 4 , wherein the vertical fin has a height in the range of about 30 nm to about 70 nm.6. The III-V semiconductor vertical fin device of claim 3 , further comprising a fin mandrel slab on the substrate.7. The III-V semiconductor vertical fin device of claim 6 , further comprising an oxide layer on the fin mandrel slab.8. The III-V semiconductor vertical fin device of claim 7 , wherein the fin mandrel slab is single crystal silicon and the oxide layer is a native oxide layer on the silicon.9. The III-V ...

REDUCED CURRENT LEAKAGE SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein. 1. A method to fabricate a semiconductor device , the method comprising:receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon;etching the channel layer to expose an extension region below the gate structure;epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant; andepitaxially growing a source or drain on the halo layer using a second in-situ dopant that has an opposite doping polarity than the first in-situ dopant.2. The method of claim 1 , wherein the halo layer provides an energy band barrier for the semiconductor device.3. The method of claim 1 , wherein the gate structure comprises a dummy gate or real gate.4. The method of claim 1 , wherein the gated substrate comprises one or more fins.5. The method of claim 1 , wherein the channel layer is undoped.6. The method of claim 1 , wherein the halo layer laterally overlaps the gate.7. The method of claim 1 , wherein the channel layer comprises a group III material and a group V material.8. The method of claim 1 , wherein the source or drain comprises a group III material and a group V material.9. The method of claim 1 , wherein a concentration of the first in-situ dopant is varied to provide a doping gradient in the halo ...

REDUCED CURRENT LEAKAGE SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein. 1. A semiconductor device comprising:a substrate including a top surface;a channel formed over the top surface of the substrate;a halo layer that is epitaxially grown and covers a sidewall of the channel and a portion of the substrate that is lateral to the channel; anda source or drain formed over the halo layer that is epitaxially grown;2. The semiconductor device of claim 1 , wherein the halo layer provides an energy band barrier for the semiconductor device.3. The semiconductor device of claim 2 , wherein the halo layer comprises a first in-situ dopant and the source or drain comprises a second in-situ dopant that has an opposite doping polarity than the first in-situ dopant.4. The semiconductor device of claim 1 , wherein the source or drain is substantially free of amorphous regions.5. The semiconductor device of claim 1 , wherein the source or drain is substantially completely crystalline.6. The semiconductor device of claim 1 , wherein the channel comprises a group III material and a group V material.7. The semiconductor device of claim 1 , wherein the source or drain comprises a group III material and a group V material.8. The semiconductor device of claim 1 , wherein the halo layer substantially modifies a bandgap for the semiconductor device relative to ...

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. 1. (canceled)2. A method of fabricating a semiconductor device , the method comprising:providing a stack of two layers disposed on a base layer, wherein a first layer of the two layers is an oxidized layer;forming a dummy gate;forming source and drain regions in contact with sides of the two layers;removing the dummy gate to provide a gate opening;etching the first layer through the gate opening to provide a lower gate region; andforming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region below the upper gate portion, and wherein the second width is greater than the first width.3. The method of claim 2 , wherein providing the stack of two layers disposed on the base layer comprises:depositing two crystalline semiconductor layers on the base layer; andselectively oxidizing one of the two crystalline semiconductor layers to provide the first layer.4. The method of claim 3 , wherein selectively oxidizing the one of the two crystalline semiconductor layers comprises:exposing the semiconductor substrate in water vapor at a temperature in a range of approximately 350 degrees to approximately 550 degrees Celsius.5. The method of claim 3 , wherein the two crystalline ...

PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER

A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench. 1. A method of forming a semiconductor device comprising:forming a trench in a dielectric layer, the dielectric layer being present on a semiconductor including substrate;forming a via within the trench, wherein the via extending from a base of the trench present at a depth within the dielectric layer to an exposed upper surface of the semiconductor including substrate;epitaxially forming a III-V semiconductor material extending from the exposed upper surface of the semiconductor including substrate filling at least a portion of the trench; andforming the semiconductor device on the III-V semiconductor material that is present in the trench.2. The method of claim 1 , wherein the dielectric layer is comprised of an oxide claim 1 , nitride or oxynitride material.3. The method of claim 1 , wherein the semiconductor including substrate is comprised of a silicon including material.4. The method of claim 1 , wherein the III-V semiconductor material is selected from the group consisting of aluminum antimonide (AlSb) claim 1 , aluminum arsenide (AlAs) claim 1 , aluminum nitride (AlN) claim 1 , aluminum phosphide (AlP) claim 1 , gallium arsenide (GaAs) claim 1 , gallium phosphide (GaP) claim 1 , indium antimonide (InSb) claim 1 , indium arsenic (InAs) claim 1 , indium nitride (InN) claim 1 , indium phosphide (InP) claim 1 , aluminum gallium arsenide (AlGaAs) claim 1 , indium gallium phosphide (InGaP) claim 1 , aluminum indium arsenic (AlInAs) claim 1 , aluminum indium antimonide (AlInSb) claim 1 , ...

MOBILE DEVICE, APPLICATION DISPLAY METHOD, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM

A display method includes requesting a memory to allocate a first memory space for the first application corresponding to a first adjusted size adjusted from a first default size of a first destination frame of the first application, requesting the memory to allocate a second memory space for the second application corresponding to a second default size of a second destination frame of the second application, synthesizing a first application image generated in the first memory space and a second application image generated in the second memory space, and controlling a display component to display the display image. 1. A mobile device comprising:a memory;a display component; and execute a first application, a second application, a window manager, and an image synthesizer;', 'determine, through the window manager, a first default size of a first destination frame of the first application and a second default size of a second destination frame of the second application;', 'request, through the window manager, the memory to allocate a first memory space for the first application corresponding to a first adjusted size adjusted from the first default size;', 'request, through the window manager, the memory to allocate a second memory space for the second application corresponding to the second default size;', 'generate, through the first application, a first application image with the first adjusted size in the first memory space;', 'generate, through the second application, a second application image with the second default size in the second memory space;', 'synthesize, through the image synthesizer, the first application image with the first adjusted size and the second application image with the second default size to generate a display image; and', 'control the display component to display the display image., 'a processing component electrically connected to the memory and the display component, wherein the processing component is configured to2. The mobile device as ...

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. 1. A method for fabricating a semiconductor device with selective oxidation , the method comprising:depositing a stack of two crystalline semiconductor layers over a base layer, wherein the base layer comprises a semiconductor substrate and a first insulator layer;forming a selectively oxidized crystalline semiconductor layer by selectively oxidizing a first of the two crystalline semiconductor layers to yield a selectively oxidized layer that serves as an insulator for a second of the two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers maintain a layered configuration after oxidation of the first of the two crystalline semiconductor layers;forming a dummy gate and a set of sidewall spacers positioned adjacent to the dummy gate structure, in direct contact with sidewalls of the dummy gate;forming source and drain regions in contact with each side of the selectively oxidized layer and the second of the two crystalline semiconductor layersetching the selectively oxidized crystalline semiconductor layer;removing the dummy gate; andforming a replacement gate layer between a plurality of walls within the set of sidewall spacers.2. The method of claim 1 , further comprising the step of:depositing a high-K insulator around the replacement gate layer.3. The method of claim 1 , wherein selectively oxidizing one of ...

T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR

A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. 1. A semiconductor structure comprising:at least one semiconductor material portion located on a surface of a buried insulator layer;a base region extending upward from a recessed semiconductor surface of said at least one semiconductor material portion, wherein said base region comprises a vertical stack of, from bottom to top, an extrinsic base region and an intrinsic base region, said extrinsic base region comprising a first compound semiconductor material portion of a first conductivity type and a first dopant concentration and said intrinsic base region comprising another first compound semiconductor material portion of the first conductivity type and a second dopant concentration, wherein said second dopant concentration is less than the first dopant concentration;a collector region comprising a second compound semiconductor material portion of a second conductivity type which is opposite of the first conductivity type is located on one side on the base region and in direct contact with a sidewall surface of said intrinsic base region; andan ...

SPALLING USING DISSOLVABLE RELEASE LAYER

A method of performing spalling of a semiconductor substrate in which a release layer is used between a handling substrate and a stressor layer. The release layer is removed using a liquid that does not damage the spalled semiconductor substrate. 1. A method of forming a semiconductor structure , the method comprising:forming a stressor layer on a crystalline substrate, wherein the stressor layer is under tensile stress;forming a release layer on the stressor layer;forming a handling substrate on the release layer;performing spalling of the substrate, wherein spalling propagates a fracture in the crystalline substrate using a force necessary to propagate the fracture, and wherein the release layer withstands the force necessary to propagate the fracture;removing the release layer and the handling substrate using a release solvent.2. The method of claim 1 , wherein the release layer comprises a polymer.3. The method of claim 2 , wherein the release layer comprises polymethylmethacrylate.4. (canceled)5. The method of claim 1 , wherein the crystalline substrate is a single crystalline substrate.6. The method of claim 1 , wherein the stressor layer comprises a metal.7. The method of wherein the metal of the stressor layer comprises nickel claim 6 , chromium claim 6 , iron or tungsten.8. The method of claim 1 , wherein the stressor layer comprises a polymer.9. The method of claim 1 , wherein the fracture occurs less than 100 microns below the surface of the crystalline substrate.1012-. (canceled)13. The method of claim 1 , further comprising removing the stressor layer by etching the stressor layer.14. A method of forming a semiconductor structure claim 1 , the method comprising:forming a stressor layer on a crystalline substrate, wherein the stressor layer is under tensile stress;forming a release layer on the stressor layer;forming a handling substrate on the release layer;performing spalling of the substrate, wherein spalling propagates a fracture in the crystalline ...

POST GROWTH HETEROEPITAXIAL LAYER SEPARATION FOR DEFECT REDUCTION IN HETEROEPITAXIAL FILMS

A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure. 110-. (canceled)11. A semiconductor structure for reducing defects , the structure comprising:a first crystalline material epitaxially grown over a crystalline substrate;a second crystalline material epitaxially grown over the first crystalline material, where openings are formed within the second crystalline material;a thermally stable material deposited in the openings after converting the first crystalline material into a non-crystalline material; anda capping layer deposited over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure;wherein the substantially enclosed semiconductor structure is annealed.12. The structure of claim 11 , wherein the first crystalline material is converted to a non-crystalline material by oxidation.13. The structure of claim 12 , wherein the non-crystalline material separates the substrate from the second crystalline material.14. The structure of claim 11 , wherein the first crystalline material is a III-V semiconductor.15. The structure of claim 11 , wherein the first crystalline material is a high aluminum (Al) content group III-V semiconductor material.16. The structure of claim 11 , wherein the first crystalline material is a material ...

POST GROWTH HETEROEPITAXIAL LAYER SEPARATION FOR DEFECT REDUCTION IN HETEROEPITAXIAL FILMS

A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure. 1. A method for reducing defects in a semiconductor structure , the method comprising:epitaxially growing a first crystalline material over a crystalline substrate;epitaxially growing a second crystalline material over the first crystalline material;patterning and removing portions of the second crystalline material to form openings;converting the first crystalline material into a non-crystalline material;depositing a thermally stable material in the openings;depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure; andannealing the substantially enclosed semiconductor structure.2. The method of claim 1 , wherein the first crystalline material is converted to a non-crystalline material by oxidation.3. The method of claim 2 , wherein the non-crystalline separates the substrate from the second crystalline material.4. The method of claim 1 , wherein the first crystalline material is a III-V semiconductor.5. The method of claim 1 , wherein the first crystalline material is a high aluminum (Al) content group III-V semiconductor material.6. The method of claim 1 , wherein the first crystalline material is a material that is converted to porous ...

OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS

A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. 1. A semiconductor structure comprising:a semiconductor fin comprising an III-V compound semiconductor material located on a surface of an insulator layer;a functional gate structure orientated perpendicular to and straddling a portion of the semiconductor fin, wherein a semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than said semiconductor fin is located beneath the functional gate structure, said semiconductor channel material is present on at least each vertical sidewall of said semiconductor fin and vertically aligned to edges of said functional gate structure;a dielectric spacer located on each vertical sidewall surface of said functional gate structure; anda doped semiconductor material having a higher dopant content than both said semiconductor fin and said semiconductor channel material located on each side of the functional gate structure and underneath each dielectric spacer, wherein a portion of the doped semiconductor material located beneath each ...

OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS

A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. 1. A method of forming a semiconductor structure comprising:forming a semiconductor fin comprising an III-V compound semiconductor material on a surface of an insulator layer;epitaxially growing a semiconductor channel material on exposed surfaces of the semiconductor fin, wherein said semiconductor channel material has an electron mobility greater than silicon and comprises a different semiconductor material than said semiconductor fin;forming a gate structure straddling a portion of the semiconductor fin, wherein said gate structure is orientated perpendicular to said semiconductor fin, and wherein a dielectric spacer is present on each vertical sidewall of said gate structure;selectively etching portions of the semiconductor channel material from atop the structure not protected by the gate structure and from beneath each dielectric spacer, wherein an undercut is provided beneath each dielectric spacer; andepitaxially growing a doped semiconductor material having a higher dopant content than both said semiconductor fin and said semiconductor ...

III-V LASERS WITH INTEGRATED SILICON PHOTONIC CIRCUITS

III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light. 1. A laser , comprising:a three-layer semiconductor stack formed from III-V semiconductors on a substrate, wherein a middle layer has a lower bandgap than a top layer and a bottom layer;a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; anda waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.2. The laser of claim 1 , wherein the stack has a height-to-width aspect ratio greater than 1.3. The laser of claim 1 , wherein the mirror region comprises alternating regions of a first and a second non-conductive material having different indices of refraction.4. The laser of claim 3 , wherein the alternating regions have a separation based on a wavelength of the emitted light.5. The laser of claim 1 , further comprising front and back contacts that contact the top and bottom of the stack claim 1 , respectively.6. The laser of claim 5 , wherein the back contact includes a conductive layer in the substrate that connects to the bottom layer of the stack.7. The laser of claim 1 , wherein the mirror and waveguide regions are monolithically grown on an insulator layer of the substrate.8. The laser of claim 1 , further comprising a plurality of said three-layer semiconductor stack arranged in parallel on the substrate.9. The laser of claim 1 , wherein the waveguide region comprises:a surface perpendicular to the stack; andan extension from said surface ...

TRANSISTOR FORMATION USING COLD WELDING

A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. 1. A method for fabrication of a semiconductor device , comprising:joining a first substrate assembly including a first substrate, a sacrificial layer, a semiconductor layer, and a first metal layer to a second substrate assembly including a second substrate and a second metal layer; wherein the first metal layer is joined to the second metal layer by cold welding; andremoving at least a portion of the sacrificial layer using an etch process, wherein by said removing the sacrificial layer, the first substrate is released from a cold welded assembly of the semiconductor layer, the first metal layer, the second metal layer and the second substrate.2. The method as recited in claim 1 , wherein the joining of the first metal layer to the second metal layer includes cold welding the first and second substrate back-to-back to form a stack of semiconductor components.3. The method as recited in claim 1 , wherein the first substrate and the second substrate are composed of semiconductor materials.4. The method as recited in claim 1 , wherein the semiconductor layer comprises a III-V semiconductor material.5. The method as recited in claim 4 , wherein the semiconductor layer is a monocrystalline material.6. The method as recited in claim 1 , wherein at least one of the first metal layer and the second metal layer includes a textured three-dimensional surface.7. The method as recited in claim 1 , wherein at least one of the first substrate and the second substrate is comprised of ...

MULTI-STATE TRANSISTOR DEVICES WITH MULTIPLE THRESHOLD VOLTAGE CHANNELS

A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage. 1. A method of forming a multi-state nanosheet transistor device , comprising:forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments;forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments;removing the sacrificial layer segments;depositing a gate dielectric layer on the differentially doped nanosheet layer segments; andforming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.2. The method of claim 1 , wherein the differentially doped nanosheet layer segments have a dopant concentration in a range of about 1×10cmto about 1×10cm.3. The method of claim 1 , wherein the alternating sequence of ...

PREPARATION OF LOW DEFECT DENSITY OF III-V ON SI FOR DEVICE FABRICATION

A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa. 117.-. (canceled)18. A semiconducting material , comprising:a substrate;a high aluminum content III-V material layer disposed on the substrate, the high aluminum content III-V material layer comprising at least one III element and a V element, the at least one III element comprising Al and being present in an amount of least 50 atomic % (at. %) based on total atomic weight of the at least one III element, and the high aluminum content III-V material layer being partially oxidized to include AlO;a graded layer of an indium (In) containing III-V material disposed on the high aluminum content III-V material layer, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 at. % based on total atomic weight of InGa or InAl; anda InGaAs layer disposed on the graded layer, the InGaAs layer comprising about 25 to about 100 at. % In based on total atomic weight of InGa.19. (canceled)20. The semiconducting material of claim 18 , wherein the graded layer has a thickness in a range from about 0.5 to about 1.5 micrometers. The present disclosure generally relates to semiconductor devices, and more specifically, to semiconducting materials on silicon substrates.Semiconducting III-V compounds and materials, e.g., indium-gallium-arsenic (InGaAs) and indium-gallium-antimony (InGaSb), in transistor channel devices have low band gaps and high ...

PREPARATION OF LOW DEFECT DENSITY OF III-V ON SI FOR DEVICE FABRICATION

A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa. 1. A method of forming a semiconducting material , the method comprising:depositing a high aluminum content III-V material layer on a substrate, the high aluminum content Ill-V material layer comprising at least one III element and a V element, the at least one III element comprising Al and being present in an amount of least 50 atomic % (at. %) based on total atomic weight of the at least one III element, and the high aluminum content III-V material layer being partially oxidized to include AlO;depositing a graded buffer on the high aluminum content III-V material layer to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; andforming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.2. The method of claim 1 , wherein the substrate comprises silicon (Si) claim 1 , germanium (Ge) claim 1 , or a combination thereof.3. (canceled)4. The method of claim 1 , wherein the high aluminum content material layer is AlAs.5. (canceled)6. The method of claim 1 , wherein the graded layer has a thickness in a range from about 100 nanometers (nm) to about 10 micrometers.7. The method of claim 1 , wherein the layer of ...